**2.2 Measurement scheme using microcontroller and CPLD**

The schematic circuit diagram (CPU and control module) of the microcontroller scheme is given in **Figure 2**. The hardware and software for CPU and control unit are to be contained within the microcontroller. Design of the CPU and control hardware was tested using the ATmega8535 development board and breadboard. The power supply was then tested and found to be functional. After the first programming the microprocessor was configured to use the external oscillator [26–30]. Testing of the communication between the Atmel chip and other chips in the circuit design was successful using the communication protocol designed. Switching between two voltage levels required the use of the microcontroller on board comparator. It was

#### *DC Motor Synchronization Speed Controller Based on Microcontroller DOI: http://dx.doi.org/10.5772/intechopen.93080*

**Figure 2.** *Schematic circuit diagram of CPU and control unit.*

important that the circuit was reverted to switching between 5 and 0 V; therefore, a standard I/O pin on the Atmel could be confined to detect the communications signal. This test avoided the complication of noise interfering with the synchronization signal [26]. The Vero board circuitry was tested successfully. The CY7C374 is a flash erasable complex programmable logic device and is part of the FLASH370 family of high-density, high-speed CPLDs [29, 30].

#### **2.3 Measurement scheme for speed and direction control module**

The schematic diagram for speed and direction control module for two dc Motors with built-in power supply is given in **Figure 3**. In dc motor speed and direction control module, the device L6203 combines a full H-bridge in a single package and it was noted that this device is perfectly matched for controlling dc motors. The power stage was carried out this device which is essential for both direction and speed control for dc motor control. A current regulator (L6506) along with this device (L6203) provides a constant current drive for dc motors that control the speed of the system [7]. The value of peak current may be obtained as:

$$\text{peak current may be obtained as:}$$

$$I\_{peak} = \frac{V\_{ref}}{R\_{sense}}\tag{1}$$

The voltage across the sense resister (RS) was detected by the current regulator L6506 in order to control the motor current, and it evaluates detected voltage to monitor the speed of the motor during the brake of the motor. A suitable resistor was used between the RS and each sense input of the L6506. It was noted that the relations between the inputs of the device of L6203 and the outputs of the L6506 require a lengthy path. It was noted that a resistor should be connected between each input

#### **Figure 3.**

*Schematic diagram for speed and direction control module for two dc motor.*

of the L6203 and ground its terminal. We have used the sunbber circuit very close to the output connections of the device L6203 which was fabricated by the series of resister (R) and capacitor (C). Moreover, each power output connection and ground terminal was connected with the help of one diode (BYW98). An appropriate big capacitor was used and linked close to the supply pin of the device L6203, when the power supply cannot sink current properly. It is important that a capacitor at pin 17 of the L6506 allows the system application work smoothly. The L6506 was proposed for work with double bridge drivers, such as the device L6203 to drive dc motors. The major purpose of the device (L6203) was to detect and monitor the current in each of the load windings (dc motors). The dual chopper was run using a general on chip oscillator. An ordinary on chip oscillator was used to drive the dual chopper and it wad regulated the working frequency for the pulse width modulated drive. The sunbber circuit on pin 1 sets the working frequency which was calculated as: *<sup>f</sup>* = \_1

$$f = \frac{1}{0.69RC}, \text{ where R > 10 K} \tag{2}$$

The oscillator gives signals to set the two flip flops which in turn cause the outputs to trigger the drive. The current in the load winding (dc motor) attained the computerized programmed peak point, then the voltage across the sense resister becomes equivalent to the reference voltage (Vref) signal which leads to the comparator readjusts its flip flop interrupting the drive current until the next oscillator signal appears. A suitable choice of the value of reference voltage (Vref) and sense resister were used to program the peak current for each dc motor. It was examined that the ground noise issues in multiple arrangements has been avoided by synchronizing the oscillators. This was done by the oscillator output of the master device was connected to the sync pins of each of the devices and the R/C pin of the unused oscillators was grounded [7–11].
