**3.2 Simulation results**

In this section, the simulation measurements of encoder interface with motors by using the Cypress and Wrap software were presented. The calculations of

### *Automation and Control*

simulated waveforms with each module for implementation of CPLD (CY7C374i) were shown. Also, this subsection describes the implementation of C-code of AVR ATmege8535 microcontroller. The compiler software simulator has been used for both functional and timing simulation [29, 30]. For functional simulation, the written code was simulated before synthesis. After fitting (CPLDs) or place, simulate the design using the same original test bench as a test fixture, but with logic and routing delays added. In case of any major problems which have made an assumption on the device specification that was incorrect, or has not measured some aspect of the signal required to/ from the programmable logic device. Consequently, we have collected data on the problem and go back to the drawing (or behavioral) board. The output master up, reset, slave up and mixed simulation waveforms for encoder interface with motor for synchronization control of dc motors are shown in **Figures 4**–**7**. These presented timing waveforms show a successful prototype of a synchronization control system for dc motors. The designed system was


#### **Figure 4.**

*Master up timing simulated wave form for encoder interface with motors.*


#### **Figure 5.**

*Reset timing simulated wave form for encoder interface with motors.*


#### **Figure 6.**

*Slave up timing simulated wave form for encoder interface with motors.*

#### **Figure 7.**

*Mixed timing simulated wave form for encoder interface with motors.*

demonstrated the advantages of a synchronization control system over an analog system and improved the possibility for security when data mentioned on graphic interface module, challenge and competition when synchronization of dc motors speed required in industry, especially in textile.
