**1. Introduction**

First MOSFET measurements at liquid Helium temperature have been reported as soon as in late 1960s [1–3], leading to some remarkable discoveries like the integer quantum Hall effect [4]. Since then, many works have been published on the electrical characteristics of MOSFETS down to 4.2 K [5–7]. The interest of operating electronic circuits at cryogenic temperatures has been demonstrated a few decades ago, and relies on the performance improvement and/or on the necessity to have electronics in cryogenic environment [5–7]. With the emerging field of quantum computing, for which read-out and control electronics of the quantum bits (qubits) is required in the proximity of the qubit itself, the study of CMOS devices at low and very low temperature, well below 100 K, has received a renewed attention [8–10]. In particular, qubit control requires high-frequency and large-bandwidth signals, as well as low-power electronics to be compatible with the cooling power of modern refrigerators [11–14]. Circuits fabricated from advanced nodes CMOS are good candidates to fulfill the specifications for quantum computing applications [15–18].

Key advantages of operating at low temperatures include the better electrical performance of MOSFETs, with higher carrier drift velocity and so higher on-state drain current and transconductance, steeper subthreshold slope, lower leakage current [6, 19]. Some works have studied bulk MOSFETs operation at cryogenic temperature emphasizing in particular kink behavior and freeze-out effects in those devices [7, 15, 20–24]. Recently, outstanding characteristics have been demonstrated at 4.2 K on advanced CMOS technologies [19, 25–27], in particular for Fully Depleted Silicon-On-Insulator (FDSOI) [28–32]. Ultrathin film FDSOI devices (with typically silicon thickness less than 10 nm) are immune to kink effects [33], and freeze-out has finally little impact on the DC characteristics of MOSFETs in advanced technologies [34]. Apart from the performance itself of the circuits at these low temperatures, and the figures of merit for analog or digital applications, specific attention to power dissipation has to be brought as well, as the available cooling power is limited in cryostat, and depends of the different cooling stages (typically ≈1 W at 4 K and less than 1 mW below 100mk) [11].

In that context, FDSOI technology offers a significant advantage over other available technologies, as it allows designing low power electronics, threshold voltage tunability thanks to its back bias ability, and offers low variability due to the undoped channel [35]. Extensive electrical characterization of advanced CMOS devices at deep cryogenic operation, including device electrostatics, carrier transport, mismatch and variability, or self-heating, is thus seriously needed.

Numerical issues appears with the modeling and simulation of MOSFETs at cryogenic and deep–cryogenic temperatures, in particular due to energy kBT approaching zero in equations and the extremely small intrinsic carrier density [34, 36]. Besides these difficulties, accurate models must correctly include, among other things, the temperature dependence of the main electrical parameters, such as carrier mobility, saturation velocity, threshold voltage, … , as well as thermal effects [37, 38]. On the other hand, new physical phenomena appear as the device temperature decreases that need to be characterized and properly modeled [19].

Because these aspects are essential for the development of compact models and robust design tools, this chapter presents a review of recent results obtained on 28 nm FDSOI transistors operated down to deep cryogenic temperatures. More specifically, we first discuss in Section 2 the major device electrical properties in terms of transfer characteristics and MOSFET parameters versus temperature. Then, we describe in Section 3 the self-heating phenomena, which could alter the FDSOI device performances. The matching and variability properties of scaled transistors limiting the analog applications are then addressed in Section 4. The development of compact model necessary for FDSOI circuit design at deep cryogenic temperatures is presented in Section 5. Finally, in Section 6, we illustrate the operation of elementary circuits at very low temperatures regarding inverter delay and oscillator frequency.

### **2. Cryogenic FDSOI device operation**

In this section, we present the measurement of the main electrical properties of FDSOI devices operating down to 4.2 K, such as the capacitance and charge control characteristics, the drain current Id(Vg) transfer curves as well as the main MOSFET parameters (threshold voltage Vth, subthreshold swing, mobility).

#### **2.1 Devices under test**

The measurements were performed on 28 nm FDSOI MOSFETs with silicon film thickness tsi = 7 nm and buried oxide (BOX) thickness tBOX = 25 nm from STMicroelectronics. NMOS and PMOS transistors were processed from (100)

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

handle substrate, with <100> oriented channel, and a high-κ/metal gate Gate-First architecture (**Figure 1**) [39]. Regular-Vth (RVT) and low-Vth (LVT) transistors are available through a doped back plane (NWELL or PWELL, with typically NA,D = 10<sup>18</sup> cm<sup>3</sup> ) below the BOX. Thin (GO1, with equivalent oxide thickness EOT = 1.1 nm) and thick oxide (GO2, EOT = 3.2 nm) devices have been characterized using a cryogenic probe station down to 4.2 K.

### **2.2 Capacitance and charge control**

The electrostatic charge control of FDSOI devices has been characterized by split C-V measurements with a conventional LCR meter. To this end, the gate-to-channel capacitance Cgc = dQi/dVg, with Qi the inversion charge in the channel, has been measured at 500 kHz frequency on large area N and P MOS devices as a function of the front gate voltage Vg with body bias Vb = 0 V for several temperatures down 4.2 K (**Figure 2**). As can be seen, the Cgc(Vg) curves are almost temperature independent above threshold, whereas a strong improvement of the turn-on behavior is obtained at low temperature, related to the subthreshold slope increase. These characteristics have been well reproduced by Poisson-Schrodinger simulations (see **Section 5.1**), providing precise extraction of front oxide EOT values for GO1 and GO2 transistors [41].

The influence of the AC level (Vosc) of the LCR meter oscillator used during Cgc measurements at 4.2 K has been studied and is reported in **Figure 3a**. Indeed, due to the strong non linearity of the Qi(Vg) curves in subthreshold region at very low temperature, the turn-on behavior of the Cgc(Vg) curve below threshold is not well captured for a too large AC level (here 40 mV, currently used at T = 300 K). However, for an AC level of 1 mV, getting closer to the thermal voltage kBT/q at

#### **Figure 1.**

*Schematics of 28 nm FDSOI N- and PMOSFETs with regular-VTH (RVT) and low-VTH (LVT) flavors. Forward and reverse back biases (FBB and RBB) can be applied depending on the doping of the back plane.*

#### **Figure 2.**

*Cgc(Vg) characteristics (solid lines) for N- and PMOS GO1 and GO2 devices from 300 K down to 4.2 K, at VB = 0 V. the Cgc(Vg) 1D-PS modeling is shown in symbols (frequency = 1 MHz, AC level = 40 mV, W=L=9 μm). After Cardoso* et al*. [40].*

4.2 K, where kB is the Boltzmann constant and q the magnitude of the electron charge, the turn-on behavior of Cgc(Vg) below threshold is well accounted for. These results can be well modeled by integrating the ideal Cgc(Vg) curve over one period of the AC signal, providing the measured capacitance Cgc,meas as follows [42]:

$$\mathbf{C\_{gc,meas}}\left(\mathbf{V\_{g}}\right) = \frac{1}{\mathbf{T}\mathbf{p}} \int\_{0}^{\mathbf{T\_{p}}} \mathbf{C\_{gc}}\left(\mathbf{V\_{g}} + \delta\mathbf{V\_{g}}(\mathbf{t})\right) \mathbf{dt} \tag{1}$$

where δVg(t) = Vosc.sin(2πt/Tp) is the AC signal of period Tp (**Figure 3b**).

#### **2.3 Drain current characteristics, threshold voltage and subthreshold slope**

The Id(Vg) transfer characteristics of same devices have been measured in linear region (Vd = 50 mV) for various temperatures and are shown in **Figure 4**. As usually observed in cryo-electronics for bulk CMOS devices [7], the drain current above threshold is highly increased due to mobility improvement of both electrons and holes, resulting from the suppression of phonon scattering. Similarly, the turnon behavior of the curves below threshold is greatly improved as the temperature is lowered.

The threshold voltage Vth of the devices has been extracted by the constant current method (*i.e.* Vg for which Id = 10�<sup>7</sup> � W/L) and typical variations with

#### **Figure 3.**

*Experimental (a) and modeled (b) Cgc(Vg) characteristics for NMOS GO1 devices (W = L = 10 μm) at 4.2 K for two AC levels: 40 mV (red solid lines) and 1 mV (blue dashed lines).*

*Id(Vg) characteristics for GO1 N and P MOS devices for various temperatures obtained in linear region (Vd = 50 mV).*

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

#### **Figure 5.**

*(a) Experimental Vth extracted on NMOS GO1 transistor (W = 1 μm, L = 24 nm) as a function of T at VDS = 50 mV and 0.9 V, and at Vb = 0 V and 1.4 V. (b) Modeled Vth vs. T for Vds = 50 mV and Vb = 0 and 1.4 V. After Cardoso et al. [43].*

temperature are shown in **Figure 5a**. As in bulk MOS devices [7], Vth increases as the temperature is reduced, here with sensitivity around 0.7 to 1 mV/K. It should be mentioned that in FDSOI devices with undoped film as in our case, the Vth variation with T is not explained by the temperature dependence of the Fermi level in the silicon film as for bulk MOS devices [44]. Actually, a simple model for Vth read by constant current method can be derived assuming a single subband for the inversion layer with a critical inversion charge density nth as:

$$V\_{th} = V\_{th} + \frac{q.n\_{th}}{\mathcal{C}\_{ox}} + \frac{\mathcal{C}\_{b\cdot}(V\_{th} - V\_b)}{\mathcal{C}\_{ox}} \tag{2}$$

with *Vsth* <sup>¼</sup> *<sup>V</sup>*<sup>0</sup> <sup>þ</sup> *kBT <sup>q</sup> : ln e nth kBT:A*2*<sup>D</sup>* � <sup>1</sup> being a threshold surface potential associated with a given constant inversion charge density nth (here 1010/cm2 ), and where V0 is a constant, A2D the 2D subband density of states, Cox and Cbox respectively the front gate oxide and the buried oxide capacitance and Cb = Cbox.Csi/(Csi + Cbox) the body to front channel coupling capacitance. As can be seen from **Figure 5b**, a good qualitative agreement between model and experiment can be achieved with Eq. (2).

An important feature of FDSOI devices is the strong Vth control allowed by the back bias, which is not possible in FinFET and NW architectures, and very limited in bulk MOS devices [7], especially in forward biasing. Typical dependence of Vth with back bias are illustrated in **Figure 6** for both P and N MOS FDSOI devices of various flavors and gate oxide thicknesses (GO1 and GO2), at T = 4.2 K and T = 300 K. As can be seen from this figure, it appears that the threshold voltage control with back biasing (ΔVth/ΔVb) is insensitive to temperature down to cryogenic conditions, and that Vth can be decreased to values close to zero volt. Interestingly, this makes it possible to operate the FDSOI devices at deep cryogenic temperatures with very small supply voltage (≈0.1–0.2 V), enabling low power dissipation.

Another important parameter in FET operation is the so called subthreshold slope, S = dln(Id)/dVg, or its inverse the subthreshold swing SS, which characterizes the turn-on efficiency of the MOSFET below threshold. Typical subthreshold swing SS (mV/dec) variations with drain current in weak inversion region are shown in

#### **Figure 6.**

*Measurements of Vth vs. Vb for N- and P-type, RVT and LVT, GO1 (a) and GO2 (b) MOSFETs, at 300 K and 4.2 K, VDS = 50 mV. As T is decreased, Vb can be used to shift Vth back to its value at room temperature. After Cardoso et al. [40].*

**Figure 7.**

*Extracted subthreshold current* vs*. Id (a) and SS vs. T (b) for NMOS LVT from 300 K to 4.2 K. After Cardoso et al. [45].*

**Figure 7a**, revealing a plateau from which an average subthreshold swing can be extracted and plotted versus temperature (**Figure 7b**). Indeed, the subthreshold swing SS is varying linearly with temperature down to 25-30 K before plateauing around 10-20 mV/decade at deep cryogenic temperatures. The SS(T) linear behavior is usual for all FET devices and simply related to the Maxwell-Boltzmann statistics prevailing in weak inversion where SS = kT/q.(Cox + Cb + Cit)/Cox, Cit being the interface trap density capacitance [7]. The SS(T) plateau is generally attributed to the presence of an exponential tail of subband states, likely due to potential-fluctuations-induced disorder [46–48] and that minimizes the drain current turn-on efficiency at deep cryogenic temperatures.

#### **2.4 Carrier mobility**

Finally, the effective carrier mobility μeff is investigated as being a driving parameter of MOSFET in linear region. In **Figure 8a** and **b** are illustrated typical mobility variations with inversion charge *Ninv* as obtained by split C-V method in *Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

#### **Figure 8.**

*Experiments and analytical model of μeff vs. Ninv for NMOS GO1 (a) and GO2 (b), varying T. power law exponent (c) vs. T for N and PMOS. After Cardoso* et al*. [49].*

such FDSOI MOS devices for various temperatures. As can be seen, there is a strong improvement (up to 10 times) of the maximum mobility with temperature lowering due to phonon scattering reduction [7]. As already found for bulk Si MOSFET [7], the effective mobility exhibits a bell-shaped behavior with inversion charge at low temperature, where the mobility is limited by combined Coulomb and surface roughness scattering processes. As also shown in **Figure 8**, the mobility can be well fitted by an empirical model inspired from bulk MOSFET results and written as:

$$\mu\_{\rm eff} = \mu\_m \frac{\left(\theta\_1 \frac{Q\_i}{C\_{\rm ox}}\right)^{n-2}}{1 + \left(\theta\_1 \frac{Q\_i}{C\_{\rm ox}}\right)^{n-1} + \left(\theta\_2 \frac{Q\_i}{C\_{\rm ac}}\right)^n} \tag{3}$$

where μ<sup>m</sup> stands for an amplitude mobility value close to the maximum one, θ<sup>1</sup> and θ<sup>2</sup> are the first and second order attenuation coefficients and n is a power law exponent varying between ≈2 and ≈3 as the temperature is changed from 300 K down to 4.2 K, as illustrated in **Figure 8c**. It should be noted that this mobility law *vs*. inversion charge will be useful for compact modeling purpose (see **Section 5**).

As was already mentioned, a specific feature of FDSOI devices is their operation in forward back biasing condition, enabling a significant lowering of the threshold voltage as illustrated in **Figure 9a** for T = 4.2 K. Interestingly, for sufficiently large Vb, the drain current measured at low Vd and very low temperatures (here T = 4.2 K) is increasing above back channel threshold before to decrease significantly and then to increase again well above front channel threshold. Actually, this decrease of the drain current just happens when the front channel is opening and has been attributed to a reduction of the mobility due to remote inter-subband scattering (IS) as well explained in [50]. To better understand this behavior, we have computed the drain current of the back channel after subtraction of the front channel component, taken as being the one in absence of back channel formation i.e. when Vb = 0 V (see **Figure 9b**). This assumption has been validated by Poisson-Schrodinger simulation (not shown here). Doing the same with Cgc(Vg) characteristics for various Vb's, the inversion charge in the back channel has also been computed after integration of capacitance vs. Vg as is usual in split C-V technique (**Figure 10a**). As a result, note that the back channel charge is plateauing after the

#### **Figure 9.**

*a) Id(Vg) characteristics at 4.2 K for various Vb (= 0, 2 V, 4 V) and b) Back channel Id(Vg) curves after subtraction of front channel component also shown in green dashed line.*

**Figure 10.**

*a) Ninv vs. Vg for Back channel for Vb = 2 V, 4 V. Green curve shows Ninv(Vg) for front channel at Vb = 0. b) Back channel μeff vs. back channel Ninv and c) Back channel μeff vs. front channel Ninv for Vb = 2 V, 4 V. Green curves show front channel μeff vs. front channel Ninv at Vb = 0 V.*

opening of front channel. The effective mobility in the back channel has been computed and plotted versus inversion charge density in the back channel or versus the front one as shown in **Figure 10b** and **c**. As can be seen, μeff first increases with the back channel inversion charge density before to decrease as the back channel charge saturates (**Figure 10b**). Instead, μeff in back channel decreases with the front channel inversion charge, which clearly indicates that the opening of the front channel is responsible for the back channel mobility decrease. This is precisely the signature of remote inter-subband scattering, which happens when carriers in the back interface 2D subband can interact with the front interface 2D subband. In this situation, some carriers at the back interface can experience scattering mechanisms in the front interface due to the overlap of the back and front subband wave functions. It should be mentioned that this phenomenon of inter-subband scattering is canceling out when the temperature is increased (T > 50 K) due to thermal broadening as well as when the drain voltage is increased due to the averaging over the channel of the conductance by integration over space [50].

### **3. Self-heating phenomena**

In FDSOI devices or multi-gate field effect transistors like FinFETs and nanowire FETs, low thermally conductive materials such as the buried oxide (BOX) or the thin Si layer constituting the channel hinder the dissipation of the heat generated in the drain side. Consequently, the channel temperature can significantly rise when the device is in ON operation. This self-heating effect (SHE) can in *Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

turn severely affect the device performance, by reducing the carrier mobility, shifting the threshold voltage [51] or degrading the device reliability [52, 53], with implications to IC design. SHE has been widely studied for room temperature operation of circuits [54]. The thermal effects play a more fundamental role in cryogenic electronics – operating at various temperature stages with different available cooling powers –, as the temperature increase due to SH can be of the same order or even higher than the ambient temperature [55]. Furthermore, at very low temperature (well below 1 K), the cooling power drops down drastically (typically, 1 W at 1 K, 1 mW at 100mK) and thermal management thus becomes an additional constraint.

In this regard, the study of self-heating effects at cryogenic temperatures provides valuable information for performance optimization. In addition, to be accurate at cryogenic temperatures, models must take into account these thermal effects, as the device temperature can deviate significantly from the ambient one.

#### **3.1 Self-heating characterization technique**

The experimental evaluation of self-heating was performed by using the conventional DC technique based on gate resistance thermometry [56]. In this method, the gate dielectric layer is thin enough to assume that the temperature of the channel is equal to that of the gate electrode. Inset of **Figure 11** shows the typical 2 terminal gate structure that we used to measure the gate resistance RG. RG is measured between two contacts G1 and G2 using an LCR-meter. By varying the ambient temperature Tamb from 4.2 K up to 300 K, we record the change in the electrical gate resistance as a function of the input power P = IDS VDS. The temperature increase ΔT is deduced from RG values at zero power (and so without SHE). Then the differential thermal resistance, RTH\* = ∂ΔT/∂P|Tamb can be defined. This differential thermal resistance relates the change of ΔT due to a change in power dissipation P at a given Tamb [55].

#### **3.2 Study of thermal resistance**

In **Figure 11** we have plotted the differential thermal resistance measured on an ultrathin film FDSOI transistor (tSi = 11 nm) as a function of the device temperature

#### **Figure 11.** *(symbols) Differential thermal resistance RTH\* measured as a function of the device temperature Tdevice = Tamb + ΔT from 450 K down to 4.2 K, with a corresponding numerical fitting curve (line).*

**Figure 12.**

*Thermal resistance RTH\* versus device temperature, for wide and ultrathin FDSOI MOSFETs. After Triantopoulos* et al*. [55].*

defined as Tdevice = Tamb + ΔT. All the RTH\* data acquired for various ambient temperatures and dissipated power values merge into a single RTH\* versus Tdevice curve, which thus provides a complete description of the temperature dependence of the thermal resistance for a given device. The thermal resistance depends mainly on the device geometry W and L, as well as on the BOX thickness, but not significantly on the Si film thickness in the 7 nm to 24 nm range typical of FDSOI devices (**Figure 12**) [55].

Our results show that in thin film devices, the thermal resistance RTH\* of the device is strongly temperature dependent, especially at very low temperature, as illustrated in **Figures 11** and **12**. As the device temperature decreases from 300 K down to 4 K, RTH\* is multiplied by 3 to 6. In FDSOI devices, the BOX tends to confine the heat in the channel, and therefore the total thermal resistance depends on both the thermal conductivity of Si and SiO2, which have different temperature dependence and magnitude (**Figure 13**). RTH\* follows the temperature dependence of the inverse of the silicon dioxide thermal conductivity in the whole range of explored temperatures [57].

Besides considerations over the dominant thermal path in the device, the RTH\* vs*.* Tdevice plot can be used into thermal model in order to reconstruct the channel

**Figure 13.** *Thermal conductivity data versus temperature for bulk and Si-layer compared to that for bulk and SiO2-layer. After Triantopoulos* et al*. [55].*

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

temperature increase ΔT as a function of operating ambient temperature Tamb and input power P using the following expression,

$$P = \int\_{0}^{\Delta T} \frac{d\Delta T'}{R\_{TH} \, ^\ast (T\_{amb} + \Delta T')} \tag{4}$$

Substituting a given analytical expression of RTH\* (Tdevice) in Eq. (4) the value of ΔT at each Tamb and for each value of dissipated power can be calculated (**Figure 14**). This leads in particular to a nonlinear temperature increase of the device with the dissipated power. In this specific low temperature environment, the device temperature can significantly increase and thus highly deviate from the ambient temperature, depending on the applied gate and drain voltages, as illustrated in **Figures 15** and **16**.

#### **Figure 14.**

*Calculated channel temperature increase ΔT (line) as a function of the dissipated power P using Eq. (4) and a fitting expression for RTH\*(Tdev). Experimental data (symbols) are also shown for a direct comparison. After Triantopoulos* et al*. [55].*

#### **Figure 15.**

*(a) IDS vs. VGS measured on NMOS at Tamb = 4.2 K and VDS = 0.9 V for different gate lengths, and (b) corresponding device temperature,Tdev vs. VGS.*

#### **Figure 16.**

*(a) IDS vs. VDS measured at Tamb = 4.2 K on NMOS with L = 60 nm for different VGS values, and (b) corresponding Tdev. Vs. VDS.*
