**5. Device compact modeling approach**

In previous sections, we focus our efforts on understanding individual device physics and variability at cryogenic temperature. In this section, we present typical Poisson-Schrodinger simulation results for the capacitance and charge control in FDSOI structures operated down to deep-cryogenic temperatures and their application for building up an analytical compact model for charge and drain current in FDSOI MOSFET including back biasing effect.

#### **5.1 Poisson-Schrodinger simulations**

Poisson-Schrodinger (PS) simulations were conducted after solving selfconsistently the Schrodinger and Poisson equations given below:

$$H(\psi) = E \cdot \psi \tag{6}$$

$$\nabla(\varepsilon\_r \nabla V) = -\frac{q \cdot n(\mathbf{x})}{\varepsilon\_0} \tag{7}$$

with H the Hamiltonian, E the system energy, ψ the electron wave function, ε<sup>0</sup> and ε<sup>r</sup> the vacuum and relative silicon permittivity, n the carrier density as a function of position *x* in the Si channel depth. The electrical potential V, the subband energies Ei,j and wave functions ψi,j for valley *j* and level *i* are numerically calculated in a FDSOI structure for given front and back gate voltages. Then, the electron density is obtained after summing the different valleys and subband contributions as:

$$m(\mathbf{x}) = \sum\_{j=1}^{2} \sum\_{i=1}^{i\_{\max}} \mathbf{g}\_{j} A\_{2D,j} k\_{B} T \boldsymbol{\nu}\_{i,j}^{2}(\mathbf{x}) \, F\_{0} \left( \frac{E\_{f} - E\_{i,j}}{k\_{B} T} \right) \tag{8}$$

where kBT is the thermal energy, F0 is the zero-order Fermi-Dirac integral function, Ef the Fermi level, Ei,j the subband energy, *gj* the valley degeneracy, and A2D,j the 2D density of states of valley *j*.

It should be noted that in order to compute the PS equations down to very low temperature (1 K), special truncation caution has been taken to avoid numerical overload in the F0 Fermi integral function accounting for Fermi-Dirac statistics. PS simulations were also possible at 0 K by replacing the F0 Fermi-Dirac integral function by a Heaviside function, thus mimicking the fully degenerate metallic statistics.

The 1D FDSOI structure used for PS simulation is depicted in **Figure 23**, showing the band diagram across the stack and typical electron density profile in the channel obtained at T = 4 K for a given bias condition.

**Figure 24** demonstrates the variations of the inversion charge Qi in the Si film as a function of front gate voltage Vg with Vb = +3 V, obtained from PS simulations for various temperatures between 0 K and 60 K. A strong increase of the subthreshold slope with temperature dropping can be noticed, reaching infinity at T = 0 K, which is an interesting feature for transistors operating at such low temperatures.

**Figure 25** shows the inversion charge control by field effect through the variations of the gate-to-channel capacitance Cgc(Vg) = dQi/dVg with front gate voltage *Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

#### **Figure 23.**

*Typical band diagram and electron distribution from PS simulation for a FDSOI structure (Vg = 1 V, tox = 1 nm, tbox = 25 nm, tsi = 7 nm, Vb = 0 V,T = 4 K). After Aouad et al. [41].*

#### **Figure 24.**

*Inversion charge Qi(Vg) calculated for different temperatures (tox = 1 nm, tbox = 25 nm, tsi = 7 nm, Vb = +3 V). After Aouad et al. [41].*

#### **Figure 25.**

*Cgc(Vg) curves for different back biases Vb (tox = 1 nm, tbox = 25 nm, tsi = 10 nm,T = 4 K). After Aouad et al. [41].*

for various back gate biases Vb. The onset of the back inversion channel for Vb = +3 V is evidenced by an additional plateau in the Cgc(Vg) curve, followed by the front channel opening. This effect clearly demonstrates the capacitive coupling, through the silicon channel, between the front gate and the back channel inversion layer, which leads to a lower capacitance.

The impact of temperature on the Cgc(Vg) characteristics is shown in **Figure 26**, clearly revealing the rounding of the curves with temperature rise above T = 10 K.

#### **5.2 Compact modeling**

Following the PS simulation results, an analytical model has been established considering that front and back channel charges can be evaluated separately at each interface within a single subband approximation with energy level of a triangular potential well [41]. The coupling between the front and back channels is realized owing to the silicon channel capacitance Csi and the charge sheet approximation with Fermi-Dirac statistics.

In this case, the charge conservation equations at front and back interfaces are expressed by:

$$V\_{\mathcal{S}} = V\_{fb} + V\_{s1} + \frac{qN\_{imv1}}{C\_{ox}} + \frac{C\_{\dot{s}1} \cdot (V\_{s1} - \Delta V(F\_1) - V\_{s2} + \Delta V(F\_2))}{C\_{ox}} \tag{9}$$

$$\mathbf{V}\_{b} = \mathbf{V}\_{fb} + \mathbf{V}\_{i2} + \frac{qN\_{iw2}}{\mathbf{C}\_{b\text{ax}}} + \frac{\mathbf{C}\_{si}(\mathbf{V}\_{i2} - \Delta\mathbf{V}(\mathbf{F}\_2) - \mathbf{V}\_{i1} + \Delta\mathbf{V}(\mathbf{F}\_1))}{\mathbf{C}\_{b\text{ax}}} \tag{10}$$

where the front and back interface 2D charge densities read,

$$N\_{inv1,2} = A\_{2d} \, k\_B. T.F\_0 \left[ \frac{V\_{s1,2} - V\_0 - \Delta V(F\_{1,2})}{k\_B T} \right] \tag{11}$$

where Vs1 (Vs2) is the front (back) interface surface potential, Cox (Cbox) the front (back) oxide capacitance, Csi the silicon film capacitance. The front and back electric field are given by:

$$F\_{\mathbf{1}} = \left(V\_{\mathbf{f}} - V\_{\mathbf{f}1} - V\_{\mathbf{f}b}\right) \Big/\_{\mathbf{\tilde{3}}\_{\text{ox}}} \tag{12}$$

$$F\_2 = \left(V\_b - V\_{\iota2} - V\_{\text{fb}}\right) \zeta\_{\mathfrak{d}\_{\text{box}}} \tag{13}$$

with the Airy subband potential shift *ΔV F*ð Þ¼ *K* � j j *F* þ *F*<sup>0</sup> <sup>2</sup>*=*<sup>3</sup> with K = 1.75 � <sup>10</sup>�<sup>5</sup> V1/3 cm2/3 [67]. As the film quantization effect is dominating when

#### **Figure 26.**

*Cgc(Vg) curves for different temperatures (tox = 1 nm, tbox = 25 nm, tsi = 10 nm, Vb = +3 V). After Aouad et al. [41].*

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

the electrical field approaches zero, an offset field F0 is added to the electric field to account for the flat band quantum confinement [41].

Typical Qi(Vg) and Cgc(Vg) characteristics obtained by this Airy-based analytical model are presented in **Figures 27** and **28**, along with the PS simulation results. As can be seen, the compact model provides a good agreement with PS data, emphasizing its physical consistency in terms of charge and capacitance.

The total drain current in the channel can then computed, within the gradual channel approximation, by integrating the channel conductance between source and drain for the front and back channel and by adding their contribution as:

$$I\_d = \frac{W}{L} \int\_0^{V\_d} \mu\_{\text{eff}1}(\mathbf{Q}\_{i1}) \mathbf{Q}\_{i1} (V\_{s1} - U\_c) \, dU\_c + \frac{W}{L} \int\_0^{V\_d} \mu\_{\text{eff}2}(\mathbf{Q}\_{i2}) \mathbf{Q}\_{i2} (V\_{s2} - U\_c) \, dU\_c \tag{14}$$

where Uc is the quasi Fermi level shift between source and drain common to both channels, Qi1,2 = q.Ninv1,2 are the front and back inversion charges obtained from Eq. (11) and μeff1,2 are the front and back channel effective mobility evaluated separately using Eq. (3). In absence of inter-subband scattering, the drain current calculated using Eqs. (3) and (14) does not exhibit a decrease for Vb = 4 V when the front channel is opening, in contrast to the experimental results discussed in **Section 2.3** (see **Figure 29**). Inter-subband scattering can be taken into account

#### **Figure 28.**

*Cgc(Vg) curves obtained from PS simulations (solid lines) and analytical modeling (dashed lines) for various parameters Vb =* �*3, 0, +3 V (T = 4 K, tox = 1 nm, tbox = 25 nm, tsi = 10 nm). After Aouad et al. [41].*

#### **Figure 29.**

*Drain current vs. front gate voltage Vg: Experimental (red solid line) and modeled with IS (dashed blue line) and modeled without IS (green dashed line) for Vb = 4 V and 0 V at T = 4.2 K.*

#### **Figure 30.**

*Experimental (red solid line) and modeled (dashed blue line) back channel mobility μeff vs. front channel inversion charge density Ninv1 for Vb = 4 V at T = 4.2 K. model parameters: A = 0.45, b = 0.55 and c = 1.5 <sup>10</sup>12/cm2 .*

through an additional explicit dependence of the back channel mobility with the front inversion charge density of the form, μeff2,IS = μeff2.[a + b.exp.(-Ninv1/c)], with *a, b* and *c* being fitting parameters (**Figure 30**). By this way, the drain current can reasonably be well modeled as shown in **Figure 29** (dashed blue line), inferring the crucial role of remote inter-subband scattering in the back channel mobility.

### **6. Basic circuit operation at cryogenic temperatures**

Although operational cryo-CMOS circuits have been demonstrated down to 30 mK [17, 30, 68–70], unfortunately no mature models are yet available to accurately predict the behavior of passive and active devices at cryogenic temperatures [71, 72]. Due to this lack of compact models at cryogenic temperatures, designers are faced to a blind-design procedure, which reduces the optimization of cryogenic integrated circuits [12, 30, 32, 58, 73–75]. Using the extensive electrical characterizations of single FDSOI transistors at cryogenic temperatures, it is however possible to already design efficient circuits.

Among them oscillators are essential building blocks in many digital and analog circuits. They are required for example to generate a clock signal in the control

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

circuit of quantum computers [30, 76], and so must be also efficient at cryogenic temperature. Here we have electrically characterized ring oscillator (RO) fabricated from 28 nm-FDSOI technology [30, 77]. **Figure 31a** shows the delay per stage of a 101-stages RO as a function of temperature from 300 K down to 4.2 K. Without any back-biases applied on the MOSFETs composing the inverter stages, decreasing the temperature results in slowing down the RO. This can be explained by the threshold voltage shift at cryogenic temperature, which leads to a decrease of the effective current evaluated from the single characteristics of NMOS and PMOS transistors.

The effective drive current IEFF, which is a measure of the current drive of the MOSFET during switching and correlates well to circuit delay, can be defined for a single inverter as [78],

$$I\_{\rm EFF} = \left(\frac{\mathbf{1}}{I\_{\rm EFF, NMMOS}} + \frac{\mathbf{1}}{I\_{\rm EFF, PMOS}}\right)^{-1} \tag{15}$$

with

$$I\_{\text{EFF,NMOS/PMOS}} = \frac{(I\_H + I\_L)}{2} \tag{16}$$

where

$$\begin{aligned} I\_H &= I\_{DS}(V\_{GS} = V\_{DD}, V\_D = V\_{DD}/2 \text{ }) \\ I\_L &= I\_{DS}(V\_{GS} = V\_{DD}/2, V\_D = V\_{DD}) \end{aligned} \tag{17}$$

#### **Figure 31.**

*(a) Delay per stage versus temperature of a 101-stages RO (L = 34 nm, WNMOS = 420 nm, WPMOS = 600 nm) for different supply voltages VDD = 0.8, 1, and 1.2 V showing the RO slowing down due to the increase of VTH at low temperature. (b) Delay per stage versus temperature for VDD = 0.8, 1, and 1.2 V in the case of compensated VTH. The RO speeds up at low temperature due to the carrier mobility enhancement (from Bohuslavskyi et al. [77]).*

**Figure 32a** shows the evolution of IEFF as a function of temperature, in the case where no VBG is applied. We observed that IEFF decreases with temperature, and this decrease is stronger as VDD is decreased (3 decades degradation from 300 K to 4.2 K for VDD = 0.8 V). This IEFF variation is linked with the temperature dependence of IDS-VGS curves. A zero-temperature coefficient point (ZTC), corresponding to a gate voltage for which the drain current exhibits no temperature dependence, is systematically observed on the measured IDS vs. VGS curves, as illustrated in **Figure 33** and already evidenced in **Figures 4** and **17** [79]. For |VGS| < | VZTC| the drain current decreases as T decreases (∂IDS/∂T|VGS = cte > 0), whereas for

#### **Figure 32.**

*(a) Effective current IEFF measured on single NMOS and PMOS transistors (L = 34 nm, WNMOS = 210 nm, WPMOS = 300 nm) for different supply voltages VDD = 0.8, 1, and 1.2 V; the effective current decreases as the temperature is reduced. (b) IEFF versus temperature for VDD = 0.8, 1, and 1.2 V in the case of compensated VTH; in that case the effective current increases as the temperature is reduced (from Bohuslavskyi et al. [77]).*

#### **Figure 33.**

*(a) Drain current IDS measured on single NMOS and PMOS transistors (L = 30 nm, WNMOS=WPMOS = 210 nm) as a function of gate voltage VGS for different temperature from 300 K down to 4.2 K. a zero temperature coefficient (ZTC) point for which the drain current (IDS) is independent of the temperature is evidenced for NMOS and PMOS.*

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*


It is worth noticing that for the pMOS the ZTC point is located at higher |VGS| (≈1.1 V) compared to the nMOS devices (≈0.7 V). The IEFF temperature dependence is mainly driven by the region with positive T-dependence ∂ IDS/∂T|VGS = cte, *i.e.* for |VGS| below |VZTC|.

If a back bias VBG is applied, it is possible to shift the threshold voltage back to its room temperature value (**Figure 6**). In that configuration, the drain current IDS increases with the temperature decrease whatever VGS and VDS values, due to mobility and saturation velocity improvement with T decrease at a given |VGS-VTH| overdrive gate voltage (see **Section 2.4**). Consequently, the effective current IEFF follows the same trend with respect to T (**Figure 32b**). Thus a correctly chosen forward back bias on NMOS and PMOS will lead to a speed-up of the RO as T decreases (**Figure 31b**). At a given temperature, the back biasing VBG allows to tune the frequency as illustrated in **Figure 34**. Finally by playing with the supply voltage VDD and VBG it is also possible to manage power consumption and performance [30, 77]. It has been illustrated at 110mK on a VCO RO (**Figure 35**) where back bias allows switching from low power mode (*e.g.* 27 μW at 2GHz) to high performance mode (*e.g*. 6.9GHz for 268 μW).

#### **Figure 34.**

*Oscillating frequency as a function of VCO voltage for a VCO RO (L = 28 nm). Forward Back-biasing increases maximal frequency (from Guevel et al. [30]).*

#### **Figure 35.**

*Power as a function of supply voltage VDD and back bias voltage VBGRO (L = 28 nm). Forward back-biasing decreases power for same frequency (from Guevel et al. [30]).*
