**4. Mismatch and variability properties**

The device mismatch is a key property to be known for the development of transistor compact models and the design of electronic circuits [58–60]. This section presents variability results obtained on FDSOI MOSFETs down to 4.2 K. To this end, an integrated on-chip matrix of individually addressable transistors has been used to increase the sample size statistics.

#### **4.1 Devices under test**

The measurements were performed on both N- and P-type transistors fabricated using the same 28 nm FDSOI technology as those described in **Section 2.1**. In order to provide statistical analysis on variability and mismatch at low temperature, matrices of transistors were produced with integrated addressability in an approach similar to [61]. An automated measurement system was implemented thanks to the on-chip multiplexed arrangement. The device chips were wire-bonded on a chip carrier connected to a printed circuit board (PCB) and mounted on a dipstick to reach 4.2 K in a liquid helium bath. Each die comprises 512 matched pairs of MOSFETs (256 pairs of RVT plus 256 pairs of LVT) addressable through 10-bits selection (210 = 1024 transistors).

#### **4.2 Threshold voltage variability**

**Figure 17** shows typical drain current Id(Vg) characteristics for short channel Ntype MOS transistors, at 300 K and at 4.2 K. Twenty four devices were measured for each MOS type at low drain voltage (|Vd| = 50 mV) to illustrate device variability. In **Figure 18** the logarithmic scaled Id(Vg) emphasizes the subthreshold oscillation variability at low and high drain voltage (Vd = 50 mV and 0.9 V), at 4.2 K. The oscillations observed in the subthreshold current are a known signature of short channel MOSFETs operating at deep cryogenic temperatures, and could result from the presence of impurities in the channel [63, 64]. The threshold voltage was

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

#### **Figure 17.**

*Id*(*Vg) curves for 24 short channel (L = 28 nm) N-type LVT MOSFETs at 4.2 K and 300 K, at Vd = 50 mV. After Cardoso et al. [62].*

#### **Figure 18.**

*Id(Vg) curves for 24 short channel (L = 28 nm) N-type LVT MOSFETs at 4.2 K, at Vd = 50 mV and 0.9 V. After Cardoso et al. [62].*

extracted following the constant current criterion, at Id = 10�<sup>7</sup> W/L (A). Such current level represents the standard value used for Vth extraction, and it is well above the region where the oscillations are mainly identified, as highlighted in **Figure 18** by a dashed line.

**Figure 19** shows the Pelgrom plots of the standard deviation of ΔVth, σΔVT, for NMOS devices (similar results have been obtained for PMOS). It can be seen that σΔVT well follows the area scaling linear dependence with respect to 1/ ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> at 4.2 K, as it is the case at 300 K, for all channel dimensions explored in this study (1 μm ≤ L ≤ 28 nm, 80 nm ≤ W ≤ 25 μm). This result does not reveal any specific variation with channel width and channel length due to e.g. line edge roughness (LER) for such geometries. From 300 K to 4.2 K, the extracted linear slopes, ΔσΔVT/Δ(1/ ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> ), indicates that the threshold voltage mismatch performance degrades by ≈25% for NMOS and PMOS, at |Vd| = 50 mV, when temperature is decreased from 300 K down to 4.2 K. Since the metal gate granularity and the local charges in the gate dielectric are the main sources of threshold voltage variability in FDSOI technology [65], the slight increase of σΔVT at 4.2 K may likely be attributed to the increase of interface charge density [63]. Moreover, in **Figure 19**, it can be seen that short channel MOSFETs (L = 28 nm) exhibit higher threshold voltage variability at high drain bias (Vd = 0.9 V), which could be due to Drain Induced Barrier Lowering (DIBL).

**Figure 19.**

*Pelgrom plot of threshold voltage variability σΔVT for NMOS at Vd = 50 mV and 0.9 V, 4.2 K (left) and 300 K (right). After Cardoso et al. [62].*

**Figure 20** shows the threshold voltage individual mismatch parameter, AΔVT = σΔVT*:* ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> , plotted as a function of 1/ ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> , for 28 nm FDSOI transistors studied in this work and 40 nm bulk MOSFETs from [61], at 300 K and 4.2 K. Despite AΔVT degradation at low temperature, FDSOI remains highly competitive compared to bulk technology, mainly due to the suppression of random dopant fluctuation (RDF) induced variability in FDSOI. In **Figure 20**, it can also be observed that AΔVT does not exhibit higher values for the short channel MOSFETs (i.e. high 1/ ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> values), for which subthreshold oscillations have been observed at low temperature (**Figure 18**). This means that such oscillations do not have a significant impact on the threshold voltage variability, mainly because they occur below the drain current level where the threshold voltage is extracted, as discussed before.

#### **Figure 20.**

*AΔVT versus 1/* ffiffiffiffiffiffiffiffiffi <sup>W</sup>*:*<sup>L</sup> <sup>p</sup> *for NMOS, at Vd = 50 mV, 4.2 K and 300 K. dashed lines indicate the extracted linear slope values from the Pelgrom plots. Dotted lines show typical 40 nm bulk CMOS technology data [61]. After Cardoso* et al*. [62].*

*Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS… DOI: http://dx.doi.org/10.5772/intechopen.98403*

### **4.3 Drain current variability**

The drain current variability, σ(ΔId/Id), has also been directly measured on the 28 nm FDSOI transistors studied here and their variations with gate voltage overdrive are shown in **Figure 21** for 300 K and 4.2 K. As is usual, σ(ΔId/Id) is maximized below threshold before to decrease in strong inversion, where it might slightly increase again due to the contribution of access resistance Rs variability [66]. Actually, these variations can be very well fitted by the model of Eq. (5) developed for room temperature:

$$
\sigma \left(\frac{\Delta \mathbf{I\_d}}{\mathbf{I\_d}}\right)^2 = \left(\frac{\mathbf{g\_m}}{\mathbf{I\_d}}\right)^2 . \sigma\_{\Delta \text{VT}}\,^2 + \left(\mathbf{1} - \mathbf{g\_d}\,\mathbf{R\_s}\right)^2 . \sigma\_{\Delta \theta/\theta}\,^2 + \mathbf{g\_d^2} . \sigma\_{\Delta \text{Rs}}\,^2 \tag{5}
$$

where gm is the transconductance and gd is the output conductance. In this model, the drain current variability is controlled by three matching parameters related respectively to the threshold voltage, σΔVT, the gain factor σΔβ/<sup>β</sup> (β = W/L. Cox.μ0, with μ<sup>0</sup> being the low-field carrier mobility) and to the access resistance σΔRs. Typical matching parameters extracted from the drain current modeling, as well as their respective contributions are summarized in **Figure 22**. It indicates that there is a slight degradation of variability at low temperature and that the matching

#### **Figure 21.**

*Measured and modeled σ(ΔId/Id) variations with Vgt = Vg-Vth. σΔRs varies from 0 to 8% of Rs = 377 Ω.μm (T = 300 K) and 266 Ω.μm (T = 4.2 K). After Cardoso* et al*. [45].*

#### **Figure 22.**

*Summary of matching performance and respective parameter contributions at 300 K (RT) and 4.2 K (LT) for NMOS (W = 1.39 μm, L = 28 nm). After Cardoso et al. [45].*

is mainly dominated by threshold voltage variability in weak inversion and by gain factor and access resistance mismatch at strong inversion.
