**2. Low-voltage design techniques and approaches**

In this section, the survey of low-voltage design techniques and approaches that can be used in a standard CMOS technology (no additional process steps) are presented. Generally, low-voltage design techniques can be divided into two groups: conventional methods and unconventional ones. Unconventional methods include bulk-driven (BD) approach, dynamic threshold technique, floating-gate method, quasi-floating gate, and bulk-driven quasi-floating gate approaches. However, only the circuits designed by the bulk-driven and dynamic threshold approaches can be implemented in the standard CMOS technologies without any modification of the fabrication process. On the other hand, the conventional techniques such as circuits with rail-to-rail input/output operating range, MOS transistors working in sub-threshold region, level shifter techniques or MOS transistor in self-cascode structure represent commonly used approaches in the area of lowvoltage IC design.

Since only circuits designed by the bulk-driven approach can be implemented in pure CMOS technology, in this chapter, we focus on this LV circuit design technique. At the end of this chapter, some examples of experimental and siliconproven analog/mixed-signal circuits designed by the BD approach are presented.

#### **2.1 MOS transistor in sub-threshold operation region**

Firstly, it is vital to explain the operation regions of the MOS transistor, since this is the most important aspect for analog IC design. The optimum IC design is characterized by the minimum power consumption, minimum silicon area and sufficient frequency response, gain and other circuit specifications. Analog and mixed-signal circuit design procedure of systems using (ultra) low-power supply voltage introduces an extra layer of challenges for even seasoned circuit designers. The problems low supply voltage introduces, negatively influence several design considerations, circuit attributes and possible design options. The first and foremost is the substantially limited inversion level the MOS transistors operate in. This results, among others, in higher mismatch between transistor parameters, exponential temperature sensitivity, and drastically lowered operational frequency. We must not forget the increased silicon area requirements due to large transistors compensating for low transconductance values, increased noise and difficulties with precise secondary effects modeling. All of the above are typical drawbacks of low-voltage/low-power circuit design and their application [3]. The second issue is topological. It lies in constrained possible number of stacked transistors, in order to ensure their operation in saturation region. According to [4], the *theoretical* lower limit for saturation voltage of a MOS transistor in deep the sub-threshold region is defined as *VDSsat min* ð Þ <sup>≈</sup><sup>4</sup> � *kT q* , which at room temperature, equals to approximately 105 mV. However, with increasing inversion level, this value grows with square root trend.

The situation has been greatly improved by the development of design-oriented charge-sheet based EKV MOS transistor model (named after its authors—Enz-Krummenacher-Vittoz) [5]. EKV model defines the parameters of MOS device dependent on continuous range of inversion level unlike the industry-standard threshold voltage-based BSIM models. EKV model also introduced the so-called *gm=ID* design approach, which avails simple, yet accurate hand-calculations, straightforward transistor sizing and complete technology independence. In [4], the author defines the level of inversion, also called *inversion coefficient* (IC) of a MOS structure by Eq. (1).

$$IC = \left[ \ln \left( 1 + e^{\frac{V\_{GS} - V\_{TH}}{2\pi J\_T}} \right) \right]^2 = \frac{I\_D}{I\_{tech} \cdot \frac{W}{L}},\tag{1}$$

moderate inversion, as the voltage headroom decreases and the level of the thresh-

In the conventional approaches, MOS transistor is usually controlled by its gate potential. However, the current flowing through the device can also be modulated by the bulk-source voltage *VBS*, which is usually considered a parasitic effect and may introduce undesired body transconductance *gmb*. In the BD design approach, the input signal is applied to the transistor bulk, while a bias voltage is connected to the gate in order establish a channel between the source and drain terminals. If a constant *VGS* is kept as the bias voltage and the input signal is applied to the bulk electrode, then a JFET-like transistor behavior can be obtained. In other words, the inversion channel width is modulated according to the voltage applied to the bulk. Using the bulk as the signal input results in significantly reduced need to overcome

The effect of the *VBS* on the drain current is embedded in the threshold voltage *VTH*. The threshold voltage of MOS transistor can be expressed by Eq. (3). It also serves as *very important* link between *gm=ID*, IC and bulk-driven design approaches.

where *VTH*<sup>0</sup> is the threshold voltage with *VBS* = 0 V, *γ* is technology-specific

In order to analyze the properties of a MOS transistor driven by the bulk terminal, the conventional gate-driven and bulk-driven single stage common-source amplifiers, depicted in **Figures 3** and **4**, have been investigated and compared. From **Figures 3** and **4**, it can be observed that the input capacitance of the BD single stage amplifier will be higher than in the case of the GD amplifier. It is caused by a parasitic capacitance *Cbsub* between the bulk and substrate terminals. In the case of the GD amplifier, the input capacitance depends on *Cgs* and *Cgd* capacitances, while the BD amplifier has the input capacitance dependent on the bulk-source *Cbs*,

Thus, changes in *VBS* value will result in modification of *VTH*, which will inevitably modify the inversion coefficient according to Eq. (1) and finally, control

bulk-drain *Cbd* and bulk-substrate *Cbsub* capacitances combined together.

*Gate-driven common-source amplifier. (a) Schematic diagram, and (b) Small-signal model.*

<sup>2</sup>j j <sup>Φ</sup>*<sup>F</sup>* � *VBS* <sup>p</sup> � ffiffiffiffiffiffiffiffiffiffiffi

2j j Φ*<sup>F</sup>* � � <sup>p</sup> , (3)

*VTH* <sup>¼</sup> *VTH*<sup>0</sup> � *<sup>γ</sup>* ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

body factor, and Φ*<sup>F</sup>* is technology-specific Fermi's potential.

old voltage remains fairly constant over time (**Figure 1**).

**2.2 Bulk-driven design approach**

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

the threshold voltage at the MOS transistor.

the MOS transistor drain current.

**Figure 3.**

**23**

where *VGS* is voltage between gate and source terminal of the MOS transistor, *VTH* is a MOS transistor's threshold voltage, *n* is sub-threshold so-called slope factor, *UT* is Boltzmann's thermal voltage (25.86 mV at room temperature), *W* is MOS transistor channel width, *L* is MOS transistor channel length, and *Ispecific* technology specific, current when a square MOS device (W = L) is in the middle of inversion range IC = 1.

The point when IC = 1 also determines the conditions when the drain diffusion current equals drain drift current. The interpolated dependency of *transconductance efficiency*—*gm=ID* as a function of IC is defined by Eq. (2). It represents very powerful formula since it is completely technology independent [6]. Furthermore, it can be easily implemented into a spreadsheet, introducing automated calculations and transistor sizing.

$$\frac{\mathcal{g}\_m}{I\_D} = \frac{1}{n.U\_T.\left(\frac{1}{2} + \sqrt{\frac{1}{4} + IC}\right)}\tag{2}$$

**Figure 2** depicts the dependency of *gm=ID* on the inversion coefficient—IC, governed by Eq. (2). The area where IC ≤ 0.1 represents the sub-threshold operation region that is also called *weak inversion*. The MOS transistor operating under these conditions exhibits high voltage gain, low drain current, low saturation voltage but also large dimensions in order to compensate low transconductance and very low cut-off frequency. When inversion coefficient becomes IC ≥ 10, the MOS devices is operating in *strong inversion* or above the threshold voltage—the traditional working conditions. MOS transistor can process signals at high frequencies and does not require much of silicon area. However, the gain lowers and the drain current increases. The region in between of the weak and strong inversion (0.1 ≤ IC ≥ 10) describes a smooth transition between these two states. It is often called a *moderate inversion* and it represents a very good trade-off of the transistor and circuit parameters. Furthermore, the modern nanoscale CMOS technologies, working with lowered power supply voltage, are shifting the transistor operation into the

**Figure 2.** *gm=ID as a function of inversion coefficient—IC.*

moderate inversion, as the voltage headroom decreases and the level of the threshold voltage remains fairly constant over time (**Figure 1**).

#### **2.2 Bulk-driven design approach**

*IC* ¼ *ln* 1 þ *e*

*gm ID*

range IC = 1.

**Figure 2.**

**22**

*gm=ID as a function of inversion coefficient—IC.*

and transistor sizing.

*Integrated Circuits/Microchips*

*VGS*�*VTH* <sup>2</sup>*:n:UT* h i � � <sup>2</sup>

where *VGS* is voltage between gate and source terminal of the MOS transistor, *VTH* is a MOS transistor's threshold voltage, *n* is sub-threshold so-called slope factor, *UT* is Boltzmann's thermal voltage (25.86 mV at room temperature), *W* is MOS transistor channel width, *L* is MOS transistor channel length, and *Ispecific* technology specific, current when a square MOS device (W = L) is in the middle of inversion

The point when IC = 1 also determines the conditions when the drain diffusion current equals drain drift current. The interpolated dependency of *transconductance*

<sup>2</sup> þ

**Figure 2** depicts the dependency of *gm=ID* on the inversion coefficient—IC, governed by Eq. (2). The area where IC ≤ 0.1 represents the sub-threshold operation region that is also called *weak inversion*. The MOS transistor operating under these conditions exhibits high voltage gain, low drain current, low saturation voltage but also large dimensions in order to compensate low transconductance and very low cut-off frequency. When inversion coefficient becomes IC ≥ 10, the MOS devices is operating in *strong inversion* or above the threshold voltage—the traditional working conditions. MOS transistor can process signals at high frequencies and does not require much of silicon area. However, the gain lowers and the drain current increases. The region in between of the weak and strong inversion (0.1 ≤ IC ≥ 10) describes a smooth transition between these two states. It is often called a *moderate inversion* and it represents a very good trade-off of the transistor and circuit parameters. Furthermore, the modern nanoscale CMOS technologies, working with lowered power supply voltage, are shifting the transistor operation into the

ffiffiffiffiffiffiffiffiffiffiffiffiffi 1 <sup>4</sup> þ *IC*

� � <sup>q</sup> (2)

*efficiency*—*gm=ID* as a function of IC is defined by Eq. (2). It represents very powerful formula since it is completely technology independent [6]. Furthermore, it can be easily implemented into a spreadsheet, introducing automated calculations

> <sup>¼</sup> <sup>1</sup> *n:UT:* <sup>1</sup>

<sup>¼</sup> *ID Itechnology: <sup>W</sup> L*

, (1)

In the conventional approaches, MOS transistor is usually controlled by its gate potential. However, the current flowing through the device can also be modulated by the bulk-source voltage *VBS*, which is usually considered a parasitic effect and may introduce undesired body transconductance *gmb*. In the BD design approach, the input signal is applied to the transistor bulk, while a bias voltage is connected to the gate in order establish a channel between the source and drain terminals. If a constant *VGS* is kept as the bias voltage and the input signal is applied to the bulk electrode, then a JFET-like transistor behavior can be obtained. In other words, the inversion channel width is modulated according to the voltage applied to the bulk. Using the bulk as the signal input results in significantly reduced need to overcome the threshold voltage at the MOS transistor.

The effect of the *VBS* on the drain current is embedded in the threshold voltage *VTH*. The threshold voltage of MOS transistor can be expressed by Eq. (3). It also serves as *very important* link between *gm=ID*, IC and bulk-driven design approaches.

$$V\_{TH} = V\_{TH0} \pm \chi \left(\sqrt{2|\Phi\_F| - V\_{BS}} - \sqrt{2|\Phi\_F|}\right),\tag{3}$$

where *VTH*<sup>0</sup> is the threshold voltage with *VBS* = 0 V, *γ* is technology-specific body factor, and Φ*<sup>F</sup>* is technology-specific Fermi's potential.

Thus, changes in *VBS* value will result in modification of *VTH*, which will inevitably modify the inversion coefficient according to Eq. (1) and finally, control the MOS transistor drain current.

In order to analyze the properties of a MOS transistor driven by the bulk terminal, the conventional gate-driven and bulk-driven single stage common-source amplifiers, depicted in **Figures 3** and **4**, have been investigated and compared.

From **Figures 3** and **4**, it can be observed that the input capacitance of the BD single stage amplifier will be higher than in the case of the GD amplifier. It is caused by a parasitic capacitance *Cbsub* between the bulk and substrate terminals. In the case of the GD amplifier, the input capacitance depends on *Cgs* and *Cgd* capacitances, while the BD amplifier has the input capacitance dependent on the bulk-source *Cbs*, bulk-drain *Cbd* and bulk-substrate *Cbsub* capacitances combined together.

**Figure 3.** *Gate-driven common-source amplifier. (a) Schematic diagram, and (b) Small-signal model.*

**Figure 4.** *Bulk-driven single stage amplifier. (a) Schematic diagram, and (b) Small-signal model.*

The transconductance of the conventional GD transistor can be expressed by the following Eq. (4)

$$\mathbf{g}\_m = \beta \frac{\mathbf{W}}{L} \cdot (\mathbf{V}\_{\rm GS} - \mathbf{V}\_{\rm TH}) \tag{4}$$

*iout iin*

*iout iin*

as follows:

**Figure 5.**

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

*model.*

the lower transconductance *gmb*.

and given by Eq. (12).

**25**

<sup>≈</sup> *gmb:Vbs*

*Schematic diagram and small-signal model for fT*,*BD calculation. (a) Schematic diagram, and (b) Small-signal*

<sup>≈</sup> *gmb*

transition frequency of the BD MOS transistor can be expressed as follows:

*fT*,*BD* <sup>¼</sup> *gmb*

*v*2 *noise* <sup>¼</sup> *<sup>i</sup>* 2 *ds g*2 *m*

*noise*,*BD* <sup>¼</sup> *gm*

*ro* <sup>¼</sup> <sup>1</sup> *λIDS*

*v*2

Similarly, the input referred noise of the BD MOS transistor is given by Eq. (11), where one can observe that the BD MOS transistor suffers from higher noise due to

> *gmb* <sup>2</sup>

The small-signal output resistance for both GD and BD transistors is identical,

where *VA* represents early voltage and *IDS* is the current flowing through the MOS transistor. As mentioned above, the BD technique uses bulk terminal for the

<sup>¼</sup> *VA IDS*

� *v*2

*fT*,*BD* ≈ð Þ� 0*:*2÷0*:*3 *fT*,*GD*

As can be observed from Eq. (9), the transition frequency of the BD MOS transistor is about five times lower than in the case of a MOS transistor driven by gate terminal. Another important parameter of the amplifier is the noise introduced into the circuit by the active component. The input referred noise of the GD MOS transistor depends on the current *ids* and transconductance *gm*, and can be expressed

<sup>2</sup>*<sup>π</sup>* � *<sup>ω</sup><sup>T</sup>*,*BD*

*fT*,*BD* <sup>¼</sup> <sup>1</sup>

*jω*ð Þ *Cbs* þ *Cbsub* þ *Cbd :Vbs*

2*π*ð Þ *Cbs* þ *Cbsub* þ *Cbd*

(8)

(9)

*o* (10)

*noise* (11)

, (12)

*jω*ð Þ *Cbs* þ *Cbsub* þ *Cbd*

If we consider that unity small-signal gain is obtained at frequency *ω<sup>T</sup>*,*BD*, the

It is important to point out that Eq. (4) is only valid when the MOS transistor operates in the strong inversion. In the weak inversion, the transconductance is proportionally dependent on the drain current, as given by Eq. (5).

$$\mathbf{g}\_{m\_{wi}} = \frac{I\_{DS\_{wi}}}{n \cdot U\_T} \tag{5}$$

The relationship between the transconductance of a GD transistor *gm* and BD transistor *gmb* is given by Eqs. (4) and (6).

$$\begin{aligned} \mathbf{g}\_{mb} &= \frac{\mathbf{y}}{2\sqrt{|\mathbf{2}\phi\_F - \mathbf{V}\_{br}|}} \cdot \mathbf{g}\_m \\\\ \mathbf{g}\_{mb} &= \frac{\mathbf{C}\_{btot}}{\mathbf{C}\_{gtot}} \cdot \mathbf{g}\_m \\\\ \mathbf{g}\_{mb} &\approx (\mathbf{0}.2 \div \mathbf{0}.3) \cdot \mathbf{g}\_m \end{aligned} \tag{6}$$

where *Cbtot* and *Cgtot* are the total parasitic capacitances between bulk and channel and gate and channel, respectively. It can be observed that transconductance of the BD MOS transistor is only 20–30% of transconductance of the GD MOS transistor.

In order to determine the frequency performance of the BD transistor, schematic diagram, and small-signal model (depicted in **Figure 5**) have to be employed. Using small-signal model, the transition frequency *fT*,*BD* of the BD MOS transistor can be obtained. Firstly, it is important to define the transition frequency of the GD MOS transistor given by Eq. (7).

$$f\_{T,GD} = \frac{\mathcal{g}\_m}{2\pi \mathcal{C}\_{\mathfrak{g}^\*}}\tag{7}$$

The transfer function and current gain of the BD MOS transistor can be expressed by Eq. (8).

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 5.**

The transconductance of the conventional GD transistor can be expressed by the

It is important to point out that Eq. (4) is only valid when the MOS transistor operates in the strong inversion. In the weak inversion, the transconductance is

> *gmwi* <sup>¼</sup> *IDSwi n* � *UT*

The relationship between the transconductance of a GD transistor *gm* and BD

2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi <sup>∣</sup>2*ϕ<sup>F</sup>* � *Vbs*<sup>∣</sup> <sup>p</sup> � *gm*

*<sup>L</sup>* � ð Þ *VGS* � *VTH* (4)

(5)

(6)

(7)

*gm* <sup>¼</sup> *<sup>β</sup> <sup>W</sup>*

*Bulk-driven single stage amplifier. (a) Schematic diagram, and (b) Small-signal model.*

proportionally dependent on the drain current, as given by Eq. (5).

*gmb* <sup>¼</sup> *<sup>γ</sup>*

*gmb* ≈ð Þ� 0*:*2÷0*:*3 *gm*

where *Cbtot* and *Cgtot* are the total parasitic capacitances between bulk and channel and gate and channel, respectively. It can be observed that transconductance of the BD MOS transistor is only 20–30% of transconductance of the GD

In order to determine the frequency performance of the BD transistor, schematic diagram, and small-signal model (depicted in **Figure 5**) have to be employed. Using small-signal model, the transition frequency *fT*,*BD* of the BD MOS transistor can be obtained. Firstly, it is important to define the transition frequency of the GD MOS

*fT*,*GD* <sup>¼</sup> *gm*

The transfer function and current gain of the BD MOS transistor can be

2*πCgs*

*gmb* <sup>¼</sup> *Cbtot Cgtot* � *gm*

transistor *gmb* is given by Eqs. (4) and (6).

following Eq. (4)

*Integrated Circuits/Microchips*

**Figure 4.**

MOS transistor.

transistor given by Eq. (7).

expressed by Eq. (8).

**24**

*Schematic diagram and small-signal model for fT*,*BD calculation. (a) Schematic diagram, and (b) Small-signal model.*

$$\begin{aligned} \frac{i\_{out}}{i\_{in}} &\approx \frac{\mathcal{g}\_{mb} \cdot V\_{bs}}{j\alpha (\mathcal{C}\_{bs} + \mathcal{C}\_{bubb} + \mathcal{C}\_{bd}) \cdot V\_{bs}}\\ \frac{i\_{out}}{i\_{in}} &\approx \frac{\mathcal{g}\_{mb}}{j\alpha (\mathcal{C}\_{bs} + \mathcal{C}\_{bubb} + \mathcal{C}\_{bd})} \end{aligned} \tag{8}$$

If we consider that unity small-signal gain is obtained at frequency *ω<sup>T</sup>*,*BD*, the transition frequency of the BD MOS transistor can be expressed as follows:

$$\begin{aligned} f\_{T,BD} &= \frac{1}{2\pi} \cdot \alpha\_{T,BD} \\ f\_{T,BD} &= \frac{g\_{mb}}{2\pi (C\_{bs} + C\_{bsub} + C\_{bd})} \\ f\_{T,BD} &\approx (\mathbf{0}.\mathbf{2} \div \mathbf{0}.\mathbf{3}) \cdot f\_{T,GD} \end{aligned} \tag{9}$$

As can be observed from Eq. (9), the transition frequency of the BD MOS transistor is about five times lower than in the case of a MOS transistor driven by gate terminal. Another important parameter of the amplifier is the noise introduced into the circuit by the active component. The input referred noise of the GD MOS transistor depends on the current *ids* and transconductance *gm*, and can be expressed as follows:

$$
v\_{noise}^2 = \frac{i\_{ds}^2}{\mathcal{g}\_m^2} o\\ \tag{10}$$

Similarly, the input referred noise of the BD MOS transistor is given by Eq. (11), where one can observe that the BD MOS transistor suffers from higher noise due to the lower transconductance *gmb*.

$$
\upsilon\_{noise,BD}^2 = \left(\frac{\mathcal{g}\_m}{\mathcal{g}\_{mb}}\right)^2 \cdot \upsilon\_{noise}^2 \tag{11}
$$

The small-signal output resistance for both GD and BD transistors is identical, and given by Eq. (12).

$$r\_o = \frac{\mathbf{1}}{\lambda I\_{DS}} = \frac{V\_A}{I\_{DS}},\tag{12}$$

where *VA* represents early voltage and *IDS* is the current flowing through the MOS transistor. As mentioned above, the BD technique uses bulk terminal for the signal input, which results in significantly reduced need to overcome the threshold voltage at the MOS transistor input, as a whole. In summary, we can state the important advantages of the BD design technique, which include the following:


Bulk terminals of both MOS devices M1 and M2 are tied together and connected to the input branch. The gate terminals are biased by static voltage *Vbias*. On the input side, the voltage drop *VBS* is created by the input reference current flow. This voltage is also applied to the output branch, through the bulk terminal of M2. Hence, the output current is modulated by means of bulk-driving according Eq. (3).

Another widely and frequently implemented circuit topologies the differential amplifier is depicted in **Figure 7**; however, in the bulk-driven configuration. The devices M1 and M2 have their gate terminals tied to the lowest potential to guarantee the highest possible level of inversion. The traditional topology of the differential amplifier suffers from a limited input common-mode range (*VCM*) due to necessity of exceeding the input pair threshold voltage and minimal saturation voltage of the biasing high-side transistor *Mb*. The *VCM* voltage range can be

The input BD transistors are used to obtain the rail-to-rail input voltage range, which is important for achieving a sufficient voltage swing when low supply voltage value is used, which greatly enhances the input common-mode range (ICMR). Additional benefit of employing the bulk-driven differential amplifier rather than conventional one lies in highly linear voltage-to-current conversion thanks to

*VCM* ¼ *VDD* � *VDSsat Mb* ð Þ � *VTH* (13)

**3.2 BD differential amplifier**

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 6.**

*Simple BD current mirror.*

described by Eq. (13).

**Figure 7.** *BD differential pair.*

**27**

Unfortunately, if compared to traditional GD design approach, the bulk-driven design method also exhibits the following disadvantages:


The last drawback, however, can be effectively mitigated by lowering the power supply voltage below the threshold voltage of a PN junction or by usage of an expensive silicon-on-insulator (SOI) fabrication process. This step would prevent the turn-on of the parasitic bipolar transistor in the substrate.

#### **3. Design examples of low-voltage analog ICs**

In this section, several design examples and circuit topologies of basic analog IC building blocks using bulk-driven approach are presented. The described blocks have been silicon-proven through fabrication in a standard CMOS nanotechnology and measurement evaluation of the chip prototypes.

#### **3.1 BD current mirrors**

One of the most widely used circuit structures employed in IC design are arguably the current mirrors (CM). It is a two-port circuit, which processes the input current *IREF* and generates the output current *IOUT* based on the formula *IOUT* ¼ *k* � *IREF*, where *k* denotes an amplification (or mirroring) coefficient. **Figure 6** depicts the BD configuration of a simple CM. Obviously, more complicated CM structures can be designed using bulk-driven transistors [7].

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 6.** *Simple BD current mirror.*

signal input, which results in significantly reduced need to overcome the threshold voltage at the MOS transistor input, as a whole. In summary, we can state the important advantages of the BD design technique, which include the following:

• BD MOS transistor depletion characteristics significantly reduce the need to overcome the threshold voltage *VTH* at the transistor input and increases the

• Easy to implement in a standard CMOS technology (twin-well process, both

Unfortunately, if compared to traditional GD design approach, the bulk-driven

• Body transconductance *gmb* of the BD MOS transistor is 4–5 times lower than the gate transconductance *gm*, which leads to inferior frequency response and

• Input capacitance of the BD MOS transistor is greater, if compared to the

• BD MOS transistors fabricated in a standard CMOS process are prone to the

The last drawback, however, can be effectively mitigated by lowering the power

In this section, several design examples and circuit topologies of basic analog IC building blocks using bulk-driven approach are presented. The described blocks have been silicon-proven through fabrication in a standard CMOS nanotechnology

One of the most widely used circuit structures employed in IC design are arguably the current mirrors (CM). It is a two-port circuit, which processes the input current *IREF* and generates the output current *IOUT* based on the formula *IOUT* ¼ *k* � *IREF*, where *k* denotes an amplification (or mirroring) coefficient. **Figure 6** depicts the BD configuration of a simple CM. Obviously, more complicated CM

supply voltage below the threshold voltage of a PN junction or by usage of an expensive silicon-on-insulator (SOI) fabrication process. This step would prevent

voltage headroom for low-voltage applications.

• Better linearity due to low, transconductance (*gmb*).

design method also exhibits the following disadvantages:

• Input noise of the BD MOS transistor is increased.

the turn-on of the parasitic bipolar transistor in the substrate.

**3. Design examples of low-voltage analog ICs**

and measurement evaluation of the chip prototypes.

structures can be designed using bulk-driven transistors [7].

• Possibility to operate with a low value of the power supply.

• Suitable for rail-to-rail voltage range.

decreased gain-bandwidth product.

MOS devices available).

*Integrated Circuits/Microchips*

traditional GD device.

**3.1 BD current mirrors**

**26**

catastrophic latch-up effect.

Bulk terminals of both MOS devices M1 and M2 are tied together and connected to the input branch. The gate terminals are biased by static voltage *Vbias*. On the input side, the voltage drop *VBS* is created by the input reference current flow. This voltage is also applied to the output branch, through the bulk terminal of M2. Hence, the output current is modulated by means of bulk-driving according Eq. (3).

#### **3.2 BD differential amplifier**

Another widely and frequently implemented circuit topologies the differential amplifier is depicted in **Figure 7**; however, in the bulk-driven configuration. The devices M1 and M2 have their gate terminals tied to the lowest potential to guarantee the highest possible level of inversion. The traditional topology of the differential amplifier suffers from a limited input common-mode range (*VCM*) due to necessity of exceeding the input pair threshold voltage and minimal saturation voltage of the biasing high-side transistor *Mb*. The *VCM* voltage range can be described by Eq. (13).

$$V\_{CM} = V\_{DD} - V\_{DS\text{at}(Mb)} - V\_{TH} \tag{13}$$

The input BD transistors are used to obtain the rail-to-rail input voltage range, which is important for achieving a sufficient voltage swing when low supply voltage value is used, which greatly enhances the input common-mode range (ICMR). Additional benefit of employing the bulk-driven differential amplifier rather than conventional one lies in highly linear voltage-to-current conversion thanks to

**Figure 7.** *BD differential pair.*

almost perfectly constant transconductance *gmb*. The disadvantage of presented topology is linked to the grounded gate terminals of the differential transistor pair. This way, the ground noise will be picked up by the transistors, which degrades the power supply rejection ratio (PSRR) [8]. An example of the BD differential pair use was published in [9], where it was used as the input pair of a variable-gain amplifier (VGA).

#### **3.3 Variable-gain amplifier (VGA)**

#### *3.3.1 Description of BD VGA*

**Figure 8** shows the block diagram of a two-stage VGA. The first stage is formed by a variable-gain differential difference amplifier (DDA) designed using BD approach. The second stage has a fixed gain and is created by a BD common-source amplifier (CSA). For stabilization of the operational point of both stages, two BD common-mode feedback (CMFB) circuits have to be employed. To achieve good stability of the CMFB loop as well as the whole two-stage VGA, frequency compensation circuitry has been applied.

The schematic diagram of the low-voltage VGA circuit is depicted in **Figure 9**. The input stage of the proposed topology is formed by DDA with bulk-driven MOS transistors, in order to obtain rail-to-rail input voltage range. The negative aspect of this solution lies in the reduced voltage gain and the gain-bandwidth product (GBW) [8]. Therefore, it is safe to state, that the proposed approach is suitable for low-voltage and low-frequency applications.

circuitry. The proposed compensation approach removes the feed-forward path between the outputs of both amplifying stages by introducing a sufficient voltage gain the feedback path (transistor M15 and M16). The position of the dominant pole is, therefore, maintained, but the position of the output pole gets shifted by the factor of introduced gain. The compensation capacitor *Cc* is employed

between the virtual ground handled by the devices M13 and M14, and the output

From the design point of view, it is important to ensure good stability and investigate the parameters that influence the gain of the proposed two-stage VGA. For this purpose, the small-signal model of VGA shown in **Figure 10** was used. We have to note that the output capacitance of the first stage was neglected. Thanks to the overall symmetry of the topology, we can perform the small-signal analysis just for one half-circuit and investigate the influence of þ*Vin* and �*Vin* separately. The total voltage gain will be, therefore, equal to the sum of the partial contributions of

The resulting formula defining the total DC gain of the discussed VGA is follows:

where *A*<sup>1</sup> and *A*<sup>2</sup> is gain of the first stage and the second stage, respectively. The total transconductance and the total output resistance of the first VGA stage are denoted as *Gm*<sup>1</sup> and *Rout*1, respectively. The same parameters associated with the second stage are named *Gm*<sup>2</sup> and *Rout*2. The impact of frequency compensation block has been neglected for additional simplification of the small-signal analysis Eq. (14).

*Av* ¼ *Gm*1*Rout*<sup>1</sup> � *Gm*2*Rout*<sup>2</sup> ¼ *A*<sup>1</sup> � *A*<sup>2</sup> (14)

� *gmb*<sup>4</sup> ¼ *gmb*<sup>1</sup> � *C* � *gmb*<sup>4</sup> (15)

*3.3.2 Design principle of VGA based on small-signal analysis*

*Gm*<sup>1</sup> and *Gm*<sup>2</sup> depicted in **Figure 10** are defined follows:

*gds*<sup>1</sup> þ *gm*<sup>5</sup>

*Gm*<sup>1</sup> <sup>¼</sup> *gmb*<sup>1</sup> � *gm*<sup>5</sup>

node of the VGA.

*Schematic diagram of VGA.*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 9.**

the respective gain stages.

**29**

In general, the overall VGA voltage gain can be controlled by adjusting either the total conductance or the total output impedance [8]. Thus, transistors M5 and M6 were employed to control the VGA gain. Modification of control voltage *VCTRL* modulates the current flow through the input devices M1 and M2, which eventually changes their effective transconductance. This will, in effect, vary the voltage amplification of the first stage, which will result in modification of overall gain of the proposed VGA. The total VGA voltage gain is directly proportional to the transconductance of the gain control devices *gm*<sup>5</sup> and *gm*6. The input transistors along with the gain control devices form a cascode configuration, hence their smallsignal parameters affect the overall output resistance of the first stage. Detailed small-signal analysis of the complete VGA is conducted in the following subsection. The second stage represents a BD common-source stage with the fixed gain that offers rail-to-rail input voltage range and a wide swing (nearly rail-to-rail) at the VGA output. Two CMFB circuits were used to achieve the stable operational point of both VGA stages.

**Figure 9** depicts the implemented frequency compensation circuit. The second amplification stage of the proposed VGA consists of devices M9–M12 and transistors M13–M16 along with capacitors *Cc* are responsible for the stability of the whole

**Figure 8.** *Block diagram of VGA.*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 9.** *Schematic diagram of VGA.*

almost perfectly constant transconductance *gmb*. The disadvantage of presented topology is linked to the grounded gate terminals of the differential transistor pair. This way, the ground noise will be picked up by the transistors, which degrades the power supply rejection ratio (PSRR) [8]. An example of the BD differential pair use was published in [9], where it was used as the input pair of a variable-gain

**Figure 8** shows the block diagram of a two-stage VGA. The first stage is formed

The schematic diagram of the low-voltage VGA circuit is depicted in **Figure 9**. The input stage of the proposed topology is formed by DDA with bulk-driven MOS transistors, in order to obtain rail-to-rail input voltage range. The negative aspect of this solution lies in the reduced voltage gain and the gain-bandwidth product (GBW) [8]. Therefore, it is safe to state, that the proposed approach is suitable for

In general, the overall VGA voltage gain can be controlled by adjusting either the total conductance or the total output impedance [8]. Thus, transistors M5 and M6 were employed to control the VGA gain. Modification of control voltage *VCTRL* modulates the current flow through the input devices M1 and M2, which eventually changes their effective transconductance. This will, in effect, vary the voltage amplification of the first stage, which will result in modification of overall gain of the proposed VGA. The total VGA voltage gain is directly proportional to the transconductance of the gain control devices *gm*<sup>5</sup> and *gm*6. The input transistors along with the gain control devices form a cascode configuration, hence their smallsignal parameters affect the overall output resistance of the first stage. Detailed small-signal analysis of the complete VGA is conducted in the following subsection. The second stage represents a BD common-source stage with the fixed gain that offers rail-to-rail input voltage range and a wide swing (nearly rail-to-rail) at the VGA output. Two CMFB circuits were used to achieve the stable operational point

**Figure 9** depicts the implemented frequency compensation circuit. The second amplification stage of the proposed VGA consists of devices M9–M12 and transistors M13–M16 along with capacitors *Cc* are responsible for the stability of the whole

by a variable-gain differential difference amplifier (DDA) designed using BD approach. The second stage has a fixed gain and is created by a BD common-source amplifier (CSA). For stabilization of the operational point of both stages, two BD common-mode feedback (CMFB) circuits have to be employed. To achieve good stability of the CMFB loop as well as the whole two-stage VGA, frequency com-

amplifier (VGA).

**3.3 Variable-gain amplifier (VGA)**

pensation circuitry has been applied.

low-voltage and low-frequency applications.

*3.3.1 Description of BD VGA*

*Integrated Circuits/Microchips*

of both VGA stages.

**Figure 8.**

**28**

*Block diagram of VGA.*

circuitry. The proposed compensation approach removes the feed-forward path between the outputs of both amplifying stages by introducing a sufficient voltage gain the feedback path (transistor M15 and M16). The position of the dominant pole is, therefore, maintained, but the position of the output pole gets shifted by the factor of introduced gain. The compensation capacitor *Cc* is employed between the virtual ground handled by the devices M13 and M14, and the output node of the VGA.

#### *3.3.2 Design principle of VGA based on small-signal analysis*

From the design point of view, it is important to ensure good stability and investigate the parameters that influence the gain of the proposed two-stage VGA. For this purpose, the small-signal model of VGA shown in **Figure 10** was used. We have to note that the output capacitance of the first stage was neglected. Thanks to the overall symmetry of the topology, we can perform the small-signal analysis just for one half-circuit and investigate the influence of þ*Vin* and �*Vin* separately. The total voltage gain will be, therefore, equal to the sum of the partial contributions of the respective gain stages.

The resulting formula defining the total DC gain of the discussed VGA is follows:

$$A\_v = G\_{m1} R\_{out1} \cdot G\_{m2} R\_{out2} = A\_1 \cdot A\_2 \tag{14}$$

where *A*<sup>1</sup> and *A*<sup>2</sup> is gain of the first stage and the second stage, respectively. The total transconductance and the total output resistance of the first VGA stage are denoted as *Gm*<sup>1</sup> and *Rout*1, respectively. The same parameters associated with the second stage are named *Gm*<sup>2</sup> and *Rout*2. The impact of frequency compensation block has been neglected for additional simplification of the small-signal analysis Eq. (14).

*Gm*<sup>1</sup> and *Gm*<sup>2</sup> depicted in **Figure 10** are defined follows:

$$\mathbf{G}\_{m1} = \mathbf{g}\_{mb1} \cdot \frac{\mathbf{g}\_{m5}}{\mathbf{g}\_{d1} + \mathbf{g}\_{m5}} - \mathbf{g}\_{mb4} = \mathbf{g}\_{mb1} \cdot \mathbf{C} - \mathbf{g}\_{mb4} \tag{15}$$

**Figure 10.** *Small-signal model of the VGA.*

$$\mathbf{G}\_{m2} = \mathbf{g}\_{mb9} \tag{16}$$

Besides, the total transconductance *Gm*<sup>1</sup> also depends on *gds*1/*gm*<sup>5</sup> ratio. If numerator and denominator of the ratio are divided by *Ids*1, the following expression can

> <sup>¼</sup> *VCTRL* � *VTH*<sup>1</sup> 2 � ð Þ *VA*<sup>1</sup> þ *Vds*<sup>1</sup>

where *VCTRL* is the control voltage of VGA, and *VTH*1, *VA*1, and *Vds*<sup>1</sup> is the threshold voltage, Early voltage and voltage between source and drain of transistor M1, respectively. From Eq. (18), it can be observed that *gds*1/*gm*<sup>5</sup> ratio, which controls the total transconductance *Gm*, depends on the control voltage of the proposed VGA. Using the small-signal model depicted in **Figure 10**, the output

> � �*rds*<sup>5</sup> <sup>þ</sup> *rds*<sup>1</sup> � � |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} A

where *rds*1, *rds*4, *rds*5, *rds*7, *rds*9, and *rds*<sup>11</sup> are the output resistances of respective devices. The results of the presented small-signal analysis indicate that the first stage gain can be controlled by varying the transconductance of device M5, which is linearly dependent on the VGA control voltage (CTRL). However, the gain of the second stage defined by *gmb*9, *rds*9, and *rds*11, is completely independent of CTRL. The known location of the poles and zeros present in the proposed topology and their analytical definition is crucial for stability evaluation. The small-signal model of the circuit (**Figure 10**) has been used again for the pole-zero analysis. The overall small-signal model for both stages of the discussed VGA can be simplified to a single voltage-controlled current source (VCCS) with their associated output resistances *Rout*<sup>1</sup> and *Rout*2, respectively (dotted line and gray boxes). The respective smallsignal current generation can be expressed *VinGm*<sup>1</sup> and *Vout*1*Gm*2. Moreover, adopting the simplified model, the low-frequency gain can be re-written in more

> *Av* <sup>¼</sup> *<sup>A</sup>*1*A*<sup>2</sup> � *AM*15*rds*<sup>13</sup> <sup>þ</sup> *rds*<sup>13</sup> <sup>þ</sup> *rds*<sup>15</sup> ½ � *AM*15*rds*<sup>13</sup> þ *Rout*<sup>1</sup> þ *rds*<sup>13</sup> þ *rds*<sup>15</sup>

> > *<sup>p</sup>*<sup>1</sup> <sup>≈</sup> �<sup>1</sup>

where *AM*<sup>15</sup> is a small-signal gain of transistor M15 while *rds*<sup>13</sup> and *rds*<sup>15</sup> are the output resistances of transistors M13 and M15, respectively. If we consider that *Rout*<sup>1</sup> < < *AM*15*rds*<sup>13</sup> þ *rds*<sup>13</sup> þ *rds*15, the low-frequency gain of the designed amplifier can be approximately expressed as *A*1*A*2. Using this approximation, the error between simulated and calculated low-frequency gain will be about 3%.

The first pole defines the amplifier bandwidth (BW), and it is approximately

ð Þ *CL* <sup>þ</sup> *Cc Rout*<sup>2</sup> <sup>þ</sup> *AM*15*A*2*Rout*1*rds*13*Cc*

It was considered in the approximation that *Rout*<sup>1</sup> and *rds*<sup>13</sup> are much lower than *AM*15*rds*<sup>13</sup> þ *rds*15. Since, the VGA has the second stage with a fixed gain, by observation of Eq. (22), it can be concluded that BW might be influenced by resistance *Rout*1. Therefore, the design of the discussed VGA can be conducted in two different ways.

*AM*15*rds*13þ*rds*<sup>15</sup>

k*rds*4k*rds*<sup>7</sup> |fflfflfflffl{zfflfflfflffl} B

*Rout*<sup>2</sup> ¼ *rds*9k*rds*11, (20)

, (18)

, (19)

≈ *A*1*A*2, (21)

(22)

*gds*<sup>1</sup> *gm*<sup>5</sup> ¼ *gds*<sup>1</sup> *Ids*<sup>1</sup> *gm*<sup>5</sup> *Ids*<sup>1</sup>

resistances *Rout*<sup>1</sup> and *Rout*<sup>2</sup> of the proposed VGA are expressed as

*Rout*<sup>1</sup> ¼ 1 þ *gm*5*rds*<sup>1</sup>

be written:

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

detail as follows:

given by Eq. (22).

**31**

where *gmb*1, *gmb*4, and *gmb*<sup>9</sup> are bulk transconductance of transistors M1, M4, and M9, *gm*<sup>5</sup> is a transconductance of transistor M5, while *gds*<sup>1</sup> and *gds*<sup>5</sup> are output transconductance of transistors M1 and M5, respectively. In Eq. (15), we consider that *gm*<sup>5</sup> > > *gds*5. The total transconductance of the first stage can be varied by the transconductance of transistor M5, while the second stage has a fixed value of transconductance.

$$C = \frac{\mathcal{g}\_{m5}}{\mathcal{g}\_{ds1} + \mathcal{g}\_{m5}} = \frac{1}{1 + \frac{\varepsilon}{\mathcal{g}\_{m5}}} \tag{17}$$

One can observe that the total transconductance of VGA (*Gm*1) can be controlled by transconductance *gm*5, which depends on the control voltage (CTRL). **Figure 11** shows the dependence of the total transconductance *Gm*<sup>1</sup> on the coefficient *C* that can vary in the range from 0 to 1. If *gm*<sup>5</sup> < <*gds*1, the coefficient *C* from Eq. (17) becomes zero and the total transconductance of VGA will be equal to �*gmb*3. In the opposite case (when *gm*<sup>5</sup> > >*gds*1), coefficient *C* is equal to 1 and *Gm*<sup>1</sup> will be equal to *gmb*<sup>1</sup> � *gmb*3. This means that by increasing the transconductance *gm*5, the total transconductance *Gm*<sup>1</sup> is decreased.

**Figure 11.** *Transconductance Gm*<sup>1</sup> *versus the coefficient* C*.*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

Besides, the total transconductance *Gm*<sup>1</sup> also depends on *gds*1/*gm*<sup>5</sup> ratio. If numerator and denominator of the ratio are divided by *Ids*1, the following expression can be written:

$$\frac{\mathcal{g}\_{d\text{c1}}}{\mathcal{g}\_{m\text{5}}} = \frac{\frac{\mathcal{g}\_{d\text{1}}}{I\_{d\text{1}}}}{\frac{\mathcal{g}\_{m\text{5}}}{I\_{d\text{1}}}} = \frac{V\_{CTRL} - V\_{TH1}}{2 \cdot (V\_{A1} + V\_{d\text{c1}})},\tag{18}$$

where *VCTRL* is the control voltage of VGA, and *VTH*1, *VA*1, and *Vds*<sup>1</sup> is the threshold voltage, Early voltage and voltage between source and drain of transistor M1, respectively. From Eq. (18), it can be observed that *gds*1/*gm*<sup>5</sup> ratio, which controls the total transconductance *Gm*, depends on the control voltage of the proposed VGA. Using the small-signal model depicted in **Figure 10**, the output resistances *Rout*<sup>1</sup> and *Rout*<sup>2</sup> of the proposed VGA are expressed as

$$R\_{out1} = \underbrace{\left[\left(\mathbf{1} + \mathbf{g}\_{m\mathbf{S}} r\_{d\mathbf{d}1}\right) r\_{d\mathbf{s}5} + r\_{d\mathbf{d}1}\right]}\_{\mathbf{A}} ||r\_{d\mathbf{s}4}|| r\_{d\mathbf{s}7},\tag{19}$$

$$R\_{out2} = r\_{d\mathcal{O}} || r\_{d\text{-11}} \,\text{.}\tag{20}$$

where *rds*1, *rds*4, *rds*5, *rds*7, *rds*9, and *rds*<sup>11</sup> are the output resistances of respective devices. The results of the presented small-signal analysis indicate that the first stage gain can be controlled by varying the transconductance of device M5, which is linearly dependent on the VGA control voltage (CTRL). However, the gain of the second stage defined by *gmb*9, *rds*9, and *rds*11, is completely independent of CTRL.

The known location of the poles and zeros present in the proposed topology and their analytical definition is crucial for stability evaluation. The small-signal model of the circuit (**Figure 10**) has been used again for the pole-zero analysis. The overall small-signal model for both stages of the discussed VGA can be simplified to a single voltage-controlled current source (VCCS) with their associated output resistances *Rout*<sup>1</sup> and *Rout*2, respectively (dotted line and gray boxes). The respective smallsignal current generation can be expressed *VinGm*<sup>1</sup> and *Vout*1*Gm*2. Moreover, adopting the simplified model, the low-frequency gain can be re-written in more detail as follows:

$$A\_v = \frac{A\_1 A\_2 \cdot [A\_{M15} r\_{d13} + r\_{d13} + r\_{d15}]}{A\_{M15} r\_{d13} + R\_{out1} + r\_{d13} + r\_{d15}} \approx A\_1 A\_2,\tag{21}$$

where *AM*<sup>15</sup> is a small-signal gain of transistor M15 while *rds*<sup>13</sup> and *rds*<sup>15</sup> are the output resistances of transistors M13 and M15, respectively. If we consider that *Rout*<sup>1</sup> < < *AM*15*rds*<sup>13</sup> þ *rds*<sup>13</sup> þ *rds*15, the low-frequency gain of the designed amplifier can be approximately expressed as *A*1*A*2. Using this approximation, the error between simulated and calculated low-frequency gain will be about 3%.

The first pole defines the amplifier bandwidth (BW), and it is approximately given by Eq. (22).

$$p\_1 \approx \frac{-1}{(C\_L + C\_c)R\_{out2} + \frac{A\_{M15}A\_2 R\_{out1}r\_{d13}C\_c}{A\_{M15}r\_{d13} + r\_{d15}}} \tag{22}$$

It was considered in the approximation that *Rout*<sup>1</sup> and *rds*<sup>13</sup> are much lower than *AM*15*rds*<sup>13</sup> þ *rds*15. Since, the VGA has the second stage with a fixed gain, by observation of Eq. (22), it can be concluded that BW might be influenced by resistance *Rout*1. Therefore, the design of the discussed VGA can be conducted in two different ways.

*Gm*<sup>2</sup> ¼ *gmb*<sup>9</sup> (16)

(17)

where *gmb*1, *gmb*4, and *gmb*<sup>9</sup> are bulk transconductance of transistors M1, M4, and

One can observe that the total transconductance of VGA (*Gm*1) can be controlled by transconductance *gm*5, which depends on the control voltage (CTRL). **Figure 11** shows the dependence of the total transconductance *Gm*<sup>1</sup> on the coefficient *C* that can vary in the range from 0 to 1. If *gm*<sup>5</sup> < <*gds*1, the coefficient *C* from Eq. (17) becomes zero and the total transconductance of VGA will be equal to �*gmb*3. In the opposite case (when *gm*<sup>5</sup> > >*gds*1), coefficient *C* is equal to 1 and *Gm*<sup>1</sup> will be equal to *gmb*<sup>1</sup> � *gmb*3. This means that by increasing the transconductance *gm*5, the total

<sup>¼</sup> <sup>1</sup> 1 þ *<sup>g</sup> gm*<sup>5</sup>

M9, *gm*<sup>5</sup> is a transconductance of transistor M5, while *gds*<sup>1</sup> and *gds*<sup>5</sup> are output transconductance of transistors M1 and M5, respectively. In Eq. (15), we consider that *gm*<sup>5</sup> > > *gds*5. The total transconductance of the first stage can be varied by the transconductance of transistor M5, while the second stage has a fixed value of

> *<sup>C</sup>* <sup>¼</sup> *gm*<sup>5</sup> *gds*<sup>1</sup> þ *gm*<sup>5</sup>

transconductance.

**Figure 11.**

**30**

*Small-signal model of the VGA.*

*Integrated Circuits/Microchips*

**Figure 10.**

transconductance *Gm*<sup>1</sup> is decreased.

*Transconductance Gm*<sup>1</sup> *versus the coefficient* C*.*

The resistance *Rout*<sup>1</sup> is dependent on coefficients A and B (Eq. (19)), thus the bandwidth of the VGA can be either influenced by the controlling voltage or not. The resulting *Rout*<sup>1</sup> is defined by parallel combination of both coefficients, therefore their values determine the frequency properties of *Rout*1. When the portion of A dominates (A < < B), the control voltage will adjust *Gm*<sup>1</sup> and *Rout*1, which eventually allows for greater range of gain control. On the other hand, the bandwidth will be also influenced. The other option is when *Rout*<sup>1</sup> is determined by B (A > > B). In this case, the gain can be controlled in narrower range, but the bandwidth will be independent of CTRL. Based on the presented design considerations, we have chosen to employ the second option, in order to obtain constant bandwidth across the control voltage range.

To achieve a stable operation of the proposed VGA topology, the so-called *pole splitting* compensation technique has been implemented. The second pole *p*<sup>2</sup> needs to be positioned at much higher frequency then the GBW. The analytical definition of *p*<sup>2</sup> to GBW ratio is expressed as follows:

$$\frac{p\_2}{GBW} = \frac{\mathbf{1}/p\_1^2 \cdot [A\_{M15}r\_{ds13} + r\_{ds15} + R\_{out1}]}{A\_1A\_2R\_{out2}r\_{ds13}r\_{ds15}C\_LC\_c \cdot [r\_{ds15} + R\_{out1}]} \tag{23}$$

voltage comparator. As one can observe, the input signal is processed by bulkdriven MOS transistors. This is an elegant way to solve the issues with the threshold voltage of respective devices. The most dreaded problem associated with rather exotic bulk-driven circuits is so-called *latch-up effect*, which causes catastrophic short between the power supply rails. However, with power supply voltage set to *VDD* = 0.4 V, such an event cannot occur, because the threshold voltage of PN junction even at T = 150°C does not decrease below the specified value.

The input PMOS devices *Min*<sup>þ</sup> and *Min*� act as a current sources. The static current flowing through the input branches is being modulated by the input voltage according to Eq. (3). This voltage-to-current conversion occurs in highly linear

input voltage range. The current from the input branches is afterward copied by means of unity current mirror system comprised by devices M1–M10. The differential voltage is created in nodes called *diff* and *diff* by current-to-voltage conversion. The differential signal is further processed by digital block, which is depicted

the digital part. The input devices can be cut-off when their gate terminals are pulled up—digital block issues logic one, when the circuit function is being inhibited. Otherwise, the gates are pulled down by logic zero, which sets their operation in to active, saturation, and region. The schematic diagram omits four

The gate terminals of low-side devices employed in analog core are controlled by

*<sup>∂</sup>VBS* across whole

manner thanks to almost ideally constant transconductance *gmb* <sup>¼</sup> *<sup>∂</sup>ID*

in **Figure 13**.

**Figure 13.**

**33**

*Digital control and output block of the ultra-low-voltage comparator.*

**Figure 12.**

*Analog core of ultra-low-voltage comparator.*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

It is obvious, that for satisfactory amount of phase margin (PM), the numerator of Eq. (23) has to be greater than the denominator. It is widely accepted that PM = 60° is sufficient for maintaining a stable operation of amplifier circuits, which will be met when the ratio *p*2*=GBW* ≈2. An important remark regarding PM is that it is negatively affected by gain *A*1, hence very high value of *A*<sup>1</sup> will result in lowered PM. On the other hand, if the VGA is stable even with high gain level *A*1, it will maintain stability for low *A*1, too [8].

#### **3.4 Low-voltage BD comparator**

In this section, we would like to describe the proposed topology of a voltage comparator operating with the power supply voltage (*VDD*) of 0.4 V. Due to very limited voltage span, the comparator has to be able to process the input signals in rail-to-rail range. Another important feature regarding voltage comparators is the hysteresis. The proposed comparator topology contains four levels of hysteresis programmable by input digital code. Additional but very welcome feature especially in low-power circuits is enable function. Its whole purpose is to inhibit the circuit function and lower the internal current consumption into the leakage range. One can easily observe the main advantages of the discussed comparator topology. Unlike the traditional comparator circuit with three stacked MOS transistors, the proposed one, employing just two stacked devices, can obviously function with lower supply voltage levels. The second benefit lies in the rail-to-rail input voltage range achieved by only one differential structure, rather than parallel combination of two separate PMOS and NMOS amplifiers. Another important contribution, if compared to the traditional comparator, is based on the lack of the internal bias reference block. This feature simplifies and speeds up the design procedure, lowers the overall quiescent current consumption and enables setting the current flow through the circuit branches just by respective transistor sizing.

#### *3.4.1 Description of low-voltage comparator*

The analog core of the proposed circuit is depicted in **Figure 12** along with the devices' dimensions. Let us discuss the topology of the ultra-low-voltage rail-to-rail *Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

The resistance *Rout*<sup>1</sup> is dependent on coefficients A and B (Eq. (19)), thus the bandwidth of the VGA can be either influenced by the controlling voltage or not. The resulting *Rout*<sup>1</sup> is defined by parallel combination of both coefficients, therefore their values determine the frequency properties of *Rout*1. When the portion of A dominates (A < < B), the control voltage will adjust *Gm*<sup>1</sup> and *Rout*1, which eventually allows for

influenced. The other option is when *Rout*<sup>1</sup> is determined by B (A > > B). In this case, the gain can be controlled in narrower range, but the bandwidth will be independent of CTRL. Based on the presented design considerations, we have chosen to employ the second option, in order to obtain constant bandwidth across the control voltage

To achieve a stable operation of the proposed VGA topology, the so-called *pole splitting* compensation technique has been implemented. The second pole *p*<sup>2</sup> needs to be positioned at much higher frequency then the GBW. The analytical definition

It is obvious, that for satisfactory amount of phase margin (PM), the numerator

In this section, we would like to describe the proposed topology of a voltage comparator operating with the power supply voltage (*VDD*) of 0.4 V. Due to very limited voltage span, the comparator has to be able to process the input signals in rail-to-rail range. Another important feature regarding voltage comparators is the hysteresis. The proposed comparator topology contains four levels of hysteresis programmable by input digital code. Additional but very welcome feature especially in low-power circuits is enable function. Its whole purpose is to inhibit the circuit function and lower the internal current consumption into the leakage range. One can easily observe the main advantages of the discussed comparator topology. Unlike the traditional comparator circuit with three stacked MOS transistors, the proposed one, employing just two stacked devices, can obviously function with lower supply voltage levels. The second benefit lies in the rail-to-rail input voltage range achieved by only one differential structure, rather than parallel combination of two separate PMOS and NMOS amplifiers. Another important contribution, if compared to the traditional comparator, is based on the lack of the internal bias reference block. This feature simplifies and speeds up the design procedure, lowers the overall quiescent current consumption and enables setting the current flow

through the circuit branches just by respective transistor sizing.

The analog core of the proposed circuit is depicted in **Figure 12** along with the devices' dimensions. Let us discuss the topology of the ultra-low-voltage rail-to-rail

*3.4.1 Description of low-voltage comparator*

**32**

of Eq. (23) has to be greater than the denominator. It is widely accepted that PM = 60° is sufficient for maintaining a stable operation of amplifier circuits, which will be met when the ratio *p*2*=GBW* ≈2. An important remark regarding PM is that it is negatively affected by gain *A*1, hence very high value of *A*<sup>1</sup> will result in lowered PM. On the other hand, if the VGA is stable even with high gain level *A*1, it

<sup>1</sup> � ½ � *AM*15*rds*<sup>13</sup> þ *rds*<sup>15</sup> þ *Rout*<sup>1</sup> *A*1*A*2*Rout*2*rds*13*rds*15*CLCc* � ½ � *rds*<sup>15</sup> þ *Rout*<sup>1</sup>

(23)

greater range of gain control. On the other hand, the bandwidth will be also

range.

*Integrated Circuits/Microchips*

of *p*<sup>2</sup> to GBW ratio is expressed as follows:

*p*2

will maintain stability for low *A*1, too [8].

**3.4 Low-voltage BD comparator**

*GBW* <sup>¼</sup> <sup>1</sup>*=p*<sup>2</sup>

**Figure 12.** *Analog core of ultra-low-voltage comparator.*

voltage comparator. As one can observe, the input signal is processed by bulkdriven MOS transistors. This is an elegant way to solve the issues with the threshold voltage of respective devices. The most dreaded problem associated with rather exotic bulk-driven circuits is so-called *latch-up effect*, which causes catastrophic short between the power supply rails. However, with power supply voltage set to *VDD* = 0.4 V, such an event cannot occur, because the threshold voltage of PN junction even at T = 150°C does not decrease below the specified value.

The input PMOS devices *Min*<sup>þ</sup> and *Min*� act as a current sources. The static current flowing through the input branches is being modulated by the input voltage according to Eq. (3). This voltage-to-current conversion occurs in highly linear manner thanks to almost ideally constant transconductance *gmb* <sup>¼</sup> *<sup>∂</sup>ID <sup>∂</sup>VBS* across whole input voltage range. The current from the input branches is afterward copied by means of unity current mirror system comprised by devices M1–M10. The differential voltage is created in nodes called *diff* and *diff* by current-to-voltage conversion. The differential signal is further processed by digital block, which is depicted in **Figure 13**.

The gate terminals of low-side devices employed in analog core are controlled by the digital part. The input devices can be cut-off when their gate terminals are pulled up—digital block issues logic one, when the circuit function is being inhibited. Otherwise, the gates are pulled down by logic zero, which sets their operation in to active, saturation, and region. The schematic diagram omits four

**Figure 13.** *Digital control and output block of the ultra-low-voltage comparator.*

pull-up and pull-down devices, which are responsible for ensuring a definite and known potential in the analog core nodes, when the circuit function is being disabled.

Transistors *Mh*1–*Mh*<sup>6</sup> are used to introduce hysteresis into the transfer characteristics without any external component required. The principle of operation is rather simple, yet very effective. In our case, we created four different levels of symmetrical hysteresis. The amount of hysteresis is programmable by 2-bit input code processed by the controlling digital block. Based on this information, the gate terminals of respective devices are pulled up or down and creates hysteresis of 0, 10, 20, and 50 mV. Therefore, the static current flow in the input branches is disbalanced, which in effect, shifts the trip point of the comparator. The beauty of this method is in minimal area and current consumption overhead, since the amount of the hysteresis is determined by transistor size. Another important feature is the possibility of creating customized shape (e.g., non-symmetrical) and level of hysteresis.

expressed as a product of partial voltage amplifications (or as a sum of partial voltage gains) of respective stages. For even further simplification, we have also omitted the enable pull-up and pull-down devices, which do not affect the overall

overall amplification is dependent on the activated hysteresis devices.

The first stage is comprised of devices *Min*þ, *Mh*<sup>1</sup>��<sup>6</sup> and diode-connected MOS transistor M1. The input node is the actual comparator input terminal. The output node, in this case, is the node named "A". As one can observe, the bulk-driven *Min*<sup>þ</sup> inherently contains a negative voltage feedback, which unfortunately decreases the voltage amplification below unity. This is depicted as two current sources working against each other in the small-signal model. The precise analytical expression of the first stage voltage amplification is defined by Eq. (24). It is apparent, that the

*gdsMin*<sup>þ</sup> <sup>þ</sup> *gmMin*<sup>þ</sup> <sup>þ</sup> *gmbsMin*<sup>þ</sup> <sup>þ</sup> *gdsM*<sup>1</sup> <sup>þ</sup> *gmM*<sup>1</sup> <sup>þ</sup> <sup>P</sup>*gdsMh*<sup>1</sup>�*h*<sup>6</sup> <sup>þ</sup> <sup>P</sup>*gmMh*\_*act*

*AVB* <sup>¼</sup> *gmM*<sup>2</sup>

The third and final stage of the model is comprised of devices M3 and M9. However, due to already explained reasons, we can swap the MOS transistor M9 with device M5, if desired. The topology of this stage can be described as a common-source amplifier with MOS transistor acting as load with fixed-bias. The small-signal model also reveals the fact, that the final stage is driven by the first stage only. Hence, the second stage does not contribute to the overall amplification, at all. The analytical voltage amplification provided by the final stage is defined by

*AVdiff* <sup>¼</sup> *gmM*<sup>3</sup>

As we discussed earlier, the final voltage amplification is a product of partial amplification contributions of the respective stages. However, the final analytical formula is unnecessarily complex and can be significantly simplified, if the circuit designer follows some of the common sense rules. The most basic one is associated with the "reasonable" channel length and/or minimized channel length modulation along with saturation operation mode of the transistors employed in the analog

*gdsM*<sup>3</sup> þ *gdsM*<sup>9</sup>

The second amplification stage is consist of devices M2 and M4. The input port is the "A" node and the output port would be the node named "B." The devices form a classic configuration of PMOS common-source amplifier with diode-connected transistor acting as a load. The small-signal model yields an Eq. (25), which defines

*gdsM*<sup>2</sup> þ *gdsM*<sup>4</sup> þ *gmM*<sup>4</sup>

(24)

(25)

(26)

accuracy that much and can be therefore neglected.

*Small-signal model of the proposed ultra-low-voltage comparator.*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

*AVA* <sup>¼</sup> *gmbsMin*<sup>þ</sup> <sup>þ</sup> <sup>P</sup>*gmbsMh*\_*act*

the voltage amplification of the second stage.

Eq. (26).

**35**

**Figure 14.**

The controlling block and output latch are depicted in **Figure 13**. The controlling block processes the input signals of enable and hysteresis functions and the feedback signal from the output latch and the differential voltage from the analog core. The combinatorial logic issues logic states for the gate terminals of transistors in the analog core accordingly. It is also responsible for protecting the output latch from simultaneous switching based on the feedback information. Such an event has been observed with highly rippled power supply voltage. The output signal from the latch is afterwards "buffered" by digital inverter(s) sized accordingly to the capacitance load and speed/slew-rate requirements.

#### *3.4.2 Design considerations and analysis*

Let us discuss the design considerations of the proposed comparator topology. Since the power supply voltage has already been set to *VDD* = 0.4 V due to bulkdriven input stage, we need to determine the operational temperature, or in other words the temperature corners. The usual choice is set within the industrial standard 20°C and 85°C, which was also our case. Another important aspect is a selection of CMOS fabrication process node. Current standard (as of 2020) for analog/mixed-signal designs presets the choice into planar deep sub-micron technologies (e.g., 500, 350, 130, or 90 nm) thanks to their fair trade-off between the cost and the general properties of the process and available electronic components. Analog/mixed-signal designs in finer technology nodes usually face complications requiring advanced solutions and workarounds, which outweighs the advantages linked to smaller silicon circuit area or higher operational speed.

The final transistor sizes can be seen in **Figures 12** and **13**. From the designer's point of view, the analog part has to be symmetrical, which decreases the overall effort required during the design period. One can observe, rather large MOS transistor dimensions. This choice has been done, in order to mitigate the process fluctuations associated with nanoscale CMOS processes. Furthermore, it also increases the level of inversion within the respective devices since higher the inversion coefficient, the lower current mismatch and process sensitivity.

The small-signal model of the proposed topology is shown in **Figure 14**. Thanks to the overall symmetry of the analog core, we will greatly benefit from analyzing only one half of the circuit. We have chosen the left-hand side, for our analysis. Furthermore, the devices from both topology sides are mutually interchangeable for the sake of small-signal analysis, if needed. The nodes marked "A" and "B" in the transistor-level schematic (**Figure 12**) are also depicted in the small-signal model. Another analysis simplification is, that the overall voltage amplification can be

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Figure 14.**

pull-up and pull-down devices, which are responsible for ensuring a definite and known potential in the analog core nodes, when the circuit function is being

Transistors *Mh*1–*Mh*<sup>6</sup> are used to introduce hysteresis into the transfer characteristics without any external component required. The principle of operation is rather simple, yet very effective. In our case, we created four different levels of symmetrical hysteresis. The amount of hysteresis is programmable by 2-bit input code processed by the controlling digital block. Based on this information, the gate terminals of respective devices are pulled up or down and creates hysteresis of 0, 10, 20, and 50 mV. Therefore, the static current flow in the input branches is disbalanced, which in effect, shifts the trip point of the comparator. The beauty of this method is in minimal area and current consumption overhead, since the amount of the hysteresis is determined by transistor size. Another important feature is the possibility of creating customized shape (e.g., non-symmetrical) and

The controlling block and output latch are depicted in **Figure 13**. The controlling block processes the input signals of enable and hysteresis functions and the feedback signal from the output latch and the differential voltage from the analog core. The combinatorial logic issues logic states for the gate terminals of transistors in the analog core accordingly. It is also responsible for protecting the output latch from simultaneous switching based on the feedback information. Such an event has been observed with highly rippled power supply voltage. The output signal from the latch is afterwards "buffered" by digital inverter(s) sized accordingly to the capac-

Let us discuss the design considerations of the proposed comparator topology. Since the power supply voltage has already been set to *VDD* = 0.4 V due to bulkdriven input stage, we need to determine the operational temperature, or in other words the temperature corners. The usual choice is set within the industrial standard 20°C and 85°C, which was also our case. Another important aspect is a selection of CMOS fabrication process node. Current standard (as of 2020) for analog/mixed-signal designs presets the choice into planar deep sub-micron technologies (e.g., 500, 350, 130, or 90 nm) thanks to their fair trade-off between the cost and the general properties of the process and available electronic components. Analog/mixed-signal designs in finer technology nodes usually face complications requiring advanced solutions and workarounds, which outweighs the advantages

The final transistor sizes can be seen in **Figures 12** and **13**. From the designer's point of view, the analog part has to be symmetrical, which decreases the overall effort required during the design period. One can observe, rather large MOS transistor dimensions. This choice has been done, in order to mitigate the process fluctuations associated with nanoscale CMOS processes. Furthermore, it also increases the level of inversion within the respective devices since higher the inversion coefficient, the lower current mismatch and process sensitivity.

The small-signal model of the proposed topology is shown in **Figure 14**. Thanks to the overall symmetry of the analog core, we will greatly benefit from analyzing only one half of the circuit. We have chosen the left-hand side, for our analysis. Furthermore, the devices from both topology sides are mutually interchangeable for the sake of small-signal analysis, if needed. The nodes marked "A" and "B" in the transistor-level schematic (**Figure 12**) are also depicted in the small-signal model. Another analysis simplification is, that the overall voltage amplification can be

linked to smaller silicon circuit area or higher operational speed.

disabled.

*Integrated Circuits/Microchips*

level of hysteresis.

**34**

itance load and speed/slew-rate requirements.

*3.4.2 Design considerations and analysis*

*Small-signal model of the proposed ultra-low-voltage comparator.*

expressed as a product of partial voltage amplifications (or as a sum of partial voltage gains) of respective stages. For even further simplification, we have also omitted the enable pull-up and pull-down devices, which do not affect the overall accuracy that much and can be therefore neglected.

The first stage is comprised of devices *Min*þ, *Mh*<sup>1</sup>��<sup>6</sup> and diode-connected MOS transistor M1. The input node is the actual comparator input terminal. The output node, in this case, is the node named "A". As one can observe, the bulk-driven *Min*<sup>þ</sup> inherently contains a negative voltage feedback, which unfortunately decreases the voltage amplification below unity. This is depicted as two current sources working against each other in the small-signal model. The precise analytical expression of the first stage voltage amplification is defined by Eq. (24). It is apparent, that the overall amplification is dependent on the activated hysteresis devices.

$$A\_{V\_A} = \frac{\mathbf{g}\_{mb\text{Min}+} + \sum \mathbf{g}\_{mb\text{Min}\_{\text{Mh}\_{\text{att}}}}}{\mathbf{g}\_{mb\text{Min}\_{\text{tr}}} + \mathbf{g}\_{m\text{Min}\_{\text{tr}}} + \mathbf{g}\_{mb\text{Max}\_{\text{Mh}}} + \mathbf{g}\_{mb\text{M}} + \sum \mathbf{g}\_{db\text{Min}\_{\text{Id}} - b} + \sum \mathbf{g}\_{m\text{Min}\_{\text{att}}}} \tag{24}$$

The second amplification stage is consist of devices M2 and M4. The input port is the "A" node and the output port would be the node named "B." The devices form a classic configuration of PMOS common-source amplifier with diode-connected transistor acting as a load. The small-signal model yields an Eq. (25), which defines the voltage amplification of the second stage.

$$A\_{V\_{\mathcal{B}}} = \frac{\mathcal{g}\_{m\_{\mathcal{M}}}}{\mathcal{g}\_{d \models \mathcal{M}} + \mathcal{g}\_{d \models \mathcal{M} \ast} + \mathcal{g}\_{m \models \mathcal{M}}} \tag{25}$$

The third and final stage of the model is comprised of devices M3 and M9. However, due to already explained reasons, we can swap the MOS transistor M9 with device M5, if desired. The topology of this stage can be described as a common-source amplifier with MOS transistor acting as load with fixed-bias. The small-signal model also reveals the fact, that the final stage is driven by the first stage only. Hence, the second stage does not contribute to the overall amplification, at all. The analytical voltage amplification provided by the final stage is defined by Eq. (26).

$$A\_{V\_{\overline{\text{dif}}}} = \frac{\mathbf{g}\_{m\_{\text{M3}}}}{\mathbf{g}\_{ds\_{\text{M3}}} + \mathbf{g}\_{ds\_{\text{M9}}}} \tag{26}$$

As we discussed earlier, the final voltage amplification is a product of partial amplification contributions of the respective stages. However, the final analytical formula is unnecessarily complex and can be significantly simplified, if the circuit designer follows some of the common sense rules. The most basic one is associated with the "reasonable" channel length and/or minimized channel length modulation along with saturation operation mode of the transistors employed in the analog

#### *Integrated Circuits/Microchips*

core. If this requirement is met, the sum of output conductance *gds* of respective devices in the denominator of Eq. (24) can be neglected, since it is several orders of magnitude lower than the sum of their transconductances *gm*. Keeping in mind that the second stage does not contribute to the overall gain, we can re-write the resulting formula as follows:

$$A\_V \approx \left(\frac{\mathbf{g}\_{mb\text{sm}\_{\text{Min}}} + \sum \mathbf{g}\_{mb\text{sm}\_{\text{Mh}\_{\text{sat}}}}}{\mathbf{g}\_{m\_{\text{Min}}} + \mathbf{g}\_{mb\text{sm}\_{\text{Min}}} + \mathbf{g}\_{m\_{\text{M1}}} + \sum \mathbf{g}\_{m\_{\text{Mb}\_{\text{sat}}}}}\right) \cdot \left(\frac{\mathbf{g}\_{m\_{\text{M3}}}}{\mathbf{g}\_{ds\_{\text{M3}}} + \mathbf{g}\_{ds\_{\text{M9}}}}\right) \tag{27}$$

It is apparent that for the maximized voltage gain, one should increase the transconductance of M3 and minimize the output conductance of devices M3 and M9. Since the topology is symmetrical, the same applies for the counterparts of discussed transistors.

Another important design consideration is the minimum power supply voltage the circuit can reliably operate with. The presented topology contains only two stacked transistors that need to be saturated for correct functioning. Therefore, we can express the *theoretical* minimum power supply voltage at room temperature in as follows:

$$V\_{DD\_{\min}} = 2 \cdot V\_{DS\_{\text{tot}}} \approx 2 \cdot \left( 4 \cdot \frac{k.T}{q} \right)\_{T = 300K} \approx 206.88 \text{ mV} \tag{28}$$

The expression is taken from the EKV MOS transistor model theory for deep weak inversion [4]. In real scenario, the saturation voltage dependence on the level of inversion is of square root trend. Furthermore, considering a non-ideal conditions, the more realistic expectation is about *VDDmin* = 230 mV at room temperature.

#### **3.5 Ultra-low-voltage BD charge pump**

#### *3.5.1 Description of the BD charge pump*

CMOS realization of the conventional charge pump based on the cross-coupled voltage doubler is shown in **Figure 15**. This charge pump represents one of the highly efficient topologies suitable for on-chip implementation. Both types of MOS devices are employed in the cross-coupled charge pump. The proposed control approach mitigates the excessive voltage stress, which the thin gate oxide of the MOS transistor is exposed to. The voltage drop is comprised of the equivalent resistance of the switched capacitors and the voltage drop across the turned-on transistor [10].

The cross-coupled charge pump (**Figure 15**) is based on two inverters connected in cross-couple fashion. The discussed topology, exhibits the same level of minimal input switching voltage *V<sup>ϕ</sup>min* as the traditional CMOS inverter the sum of threshold voltages of the respective MOS transistors employed. Hence, a specific modifications to the circuit topology are required, in order to enable the implementation in ultra-low-voltage applications.

One of the possible alternatives is to employ an inverter with resistor acting as a load, which would create the so-called pseudo-inverter. However, the solution is unacceptable in low-power systems, since it notably increases the internal current consumption of the charge pump. Another possibility is to tie the bulk terminal of the MOS transistors to a fixed potential and lower their threshold voltage (**Figure 16(b)**). Unfortunately, this approach substantially increases the subthreshold leakage of the MOS transistors and their bulk current, as well. Hence, it

suffers from the same drawback as the solution mentioned previously. The most effective approach, as it seems, is the so-called dynamic threshold voltage control. The basic idea is depicted in **Figure 16(c)**. As one can observe, the bulk terminals are connected to the input signal. This way, the cut-off transistor exhibits nominal threshold voltage and the turned-on transistor exhibits lowered threshold voltage

*Different topology inverters in CMOS technology.(a) CMOS inverter, (b) CMOS inverter: reduced VTH*

**Figure 15.**

**Figure 16.**

**37**

*(c) CMOS inverter: dynamic VTH.*

*Conventional cross-coupled CP (one stage).*

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958* *Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

core. If this requirement is met, the sum of output conductance *gds* of respective devices in the denominator of Eq. (24) can be neglected, since it is several orders of magnitude lower than the sum of their transconductances *gm*. Keeping in mind that the second stage does not contribute to the overall gain, we can re-write the

It is apparent that for the maximized voltage gain, one should increase the transconductance of M3 and minimize the output conductance of devices M3 and M9. Since the topology is symmetrical, the same applies for the counterparts of

Another important design consideration is the minimum power supply voltage the circuit can reliably operate with. The presented topology contains only two stacked transistors that need to be saturated for correct functioning. Therefore, we can express the *theoretical* minimum power supply voltage at room temperature in

> *k:T q* � �

The expression is taken from the EKV MOS transistor model theory for deep weak inversion [4]. In real scenario, the saturation voltage dependence on the level of inversion is of square root trend. Furthermore, considering a non-ideal conditions, the more realistic expectation is about *VDDmin* = 230 mV at room temperature.

CMOS realization of the conventional charge pump based on the cross-coupled voltage doubler is shown in **Figure 15**. This charge pump represents one of the highly efficient topologies suitable for on-chip implementation. Both types of MOS devices are employed in the cross-coupled charge pump. The proposed control approach mitigates the excessive voltage stress, which the thin gate oxide of the MOS transistor is exposed to. The voltage drop is comprised of the equivalent resistance of the switched capacitors and the voltage drop across the turned-on

The cross-coupled charge pump (**Figure 15**) is based on two inverters connected in cross-couple fashion. The discussed topology, exhibits the same level of minimal input switching voltage *V<sup>ϕ</sup>min* as the traditional CMOS inverter the sum of threshold voltages of the respective MOS transistors employed. Hence, a specific modifications to the circuit topology are required, in order to enable the implementation in

One of the possible alternatives is to employ an inverter with resistor acting as a load, which would create the so-called pseudo-inverter. However, the solution is unacceptable in low-power systems, since it notably increases the internal current consumption of the charge pump. Another possibility is to tie the bulk terminal of

the MOS transistors to a fixed potential and lower their threshold voltage (**Figure 16(b)**). Unfortunately, this approach substantially increases the subthreshold leakage of the MOS transistors and their bulk current, as well. Hence, it

*T*¼300*K*

≈206*:*88 *mV* (28)

� *gmM*<sup>3</sup> *gdsM*<sup>3</sup> þ *gdsM*<sup>9</sup> !

(27)

resulting formula as follows:

*Integrated Circuits/Microchips*

discussed transistors.

as follows:

transistor [10].

**36**

ultra-low-voltage applications.

*AV* <sup>≈</sup> *gmbsMin*<sup>þ</sup> <sup>þ</sup> <sup>P</sup>*gmbsMh*\_*act*

*gmMin*<sup>þ</sup> <sup>þ</sup> *gmbsMin*<sup>þ</sup> <sup>þ</sup> *gmM*<sup>1</sup> <sup>þ</sup> <sup>P</sup>*gmMh*\_*act* !

*VDDmin* ¼ 2 � *VDSsat* ≈ 2 � 4 �

**3.5 Ultra-low-voltage BD charge pump**

*3.5.1 Description of the BD charge pump*

**Figure 15.** *Conventional cross-coupled CP (one stage).*

#### **Figure 16.**

*Different topology inverters in CMOS technology.(a) CMOS inverter, (b) CMOS inverter: reduced VTH (c) CMOS inverter: dynamic VTH.*

suffers from the same drawback as the solution mentioned previously. The most effective approach, as it seems, is the so-called dynamic threshold voltage control. The basic idea is depicted in **Figure 16(c)**. As one can observe, the bulk terminals are connected to the input signal. This way, the cut-off transistor exhibits nominal threshold voltage and the turned-on transistor exhibits lowered threshold voltage

where *N* is a number of stages used, *Vin* is the input voltage, *Vout* is the output voltage, *V<sup>ϕ</sup>* is the switching voltage, *Cin* is the switching capacitance, *Ctot* is sum of switching capacitance and parasitic capacitance *Ctot* ¼ *Cin* þ *Cs*, *IL* is sum of output and leakage currents *IL* ¼ *Iout* þ *Ileakage*, *Ron* is switch-on resistance of NMOS and

Due to limited voltage headroom, the sub-threshold operation is usually chosen for low-voltage/low-power charge pump designs. Although, when the input voltage is lesser than threshold voltage of MOS transistors, the overall efficiency will be degraded, since the switching properties of the devices are drastically reduced. The dependence of MOS transistor turn-on resistance *RON* on the overdrive voltage

*RON* � <sup>1</sup>

voltage can be included in the low-voltage CPs design [11–14].

lation model accuracy and fabrication process fluctuations as well.

*eVGS*�*VTH*

It can be observed that effective voltage *VEFF* in relation to *RON* acts as argument of exponential function located in denominator, which implicates the substantial sensitivity to change of this quantity. In order to overcome this issue, many techniques such as dynamic control, feed-forward biasing of the bulk electrode, multistage topology, implementation of charge transfer switches (CTS) parallel with pass gate switches (PGS) or backward control of the previous stage by body electrode

In order to fully verify the design concepts discussed in this chapter, the proposed circuit topologies have been designed in general purpose twin-well 130 nm CMOS technology. Both types of fabricated long-channel devices exhibit the standard threshold voltage around *VTH* = 260 mV at room temperature. **Figure 18** depicts the micrograph of the fabricated prototype chip along with the physical layout design. For better clarity, we omitted some of the top metal layers. The blue rectangles pin-point the location of the proposed circuits on chip. The chip also contains a stand-alone test transistor in order to verify the devices' compact simu-

(30)

PMOS transistor, and *Req* is equivalent resistance of switching capacitor.

(*VEFF* or *VGS* � *VTH*) is defined in Eq. (30).

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**3.6 Evaluation of the proposed LV circuits**

**Figure 18.**

**39**

*Micrograph and physical design of the prototype chip.*

**Figure 17.** *Bulk-driven cross-coupled CP (one stage).*

level, which improves its drain current and switching speed. The trade-off of this method is increased leakage current of one transistor only.

Dynamic threshold inverter topology (**Figure 16(c)**) can be considered as an appropriate building cell for ultra-low-power and low-voltage charge pump designs. A very important design consideration for such a system is inevitability of twin-well CMOS fabrication process, since both PMOS and NMOS devices have to be isolated from the common substrate by their own wells. Another consideration is restricted power supply voltage. Its level must not exceed 0.6 V (at room temperature). Otherwise, parasitic NPN and PNP bipolar transistors will turn on, which with the high probability may cause triggering of latch-up effect. These limitations have to be taken into account, if designing the charge pump with dynamic *VTH* MOS inverters.

The BD charge pump based on the cross-coupled topology is shown in **Figure 17**. The charge pump employing dynamic threshold CMOS inverter is able to process very low levels of input voltages. This also represents the main advantage of the proposed topology [10]. However, the drawback lies in the limited voltage range the charge pump can work with, because of the increased risk of latch-up triggering. Hence, the main application area of such charge pump topology is constrained to low-voltage and low-power systems.

#### *3.5.2 Design procedure of BD charge pump*

Theoretical value of the output voltage can be expressed as follows:

$$V\_{out} = V\_{in} + N\left(V\_{\phi} \cdot \frac{\mathbf{C}\_{in}}{\mathbf{C}\_{tot}} - I\_L \left(R\_{on} + \frac{R\_{eq}}{2}\right)\right),\tag{29}$$

#### *Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

where *N* is a number of stages used, *Vin* is the input voltage, *Vout* is the output voltage, *V<sup>ϕ</sup>* is the switching voltage, *Cin* is the switching capacitance, *Ctot* is sum of switching capacitance and parasitic capacitance *Ctot* ¼ *Cin* þ *Cs*, *IL* is sum of output and leakage currents *IL* ¼ *Iout* þ *Ileakage*, *Ron* is switch-on resistance of NMOS and PMOS transistor, and *Req* is equivalent resistance of switching capacitor.

Due to limited voltage headroom, the sub-threshold operation is usually chosen for low-voltage/low-power charge pump designs. Although, when the input voltage is lesser than threshold voltage of MOS transistors, the overall efficiency will be degraded, since the switching properties of the devices are drastically reduced. The dependence of MOS transistor turn-on resistance *RON* on the overdrive voltage (*VEFF* or *VGS* � *VTH*) is defined in Eq. (30).

$$R\_{ON} \sim \frac{1}{\mathbf{e}^{V\_{GS} - V\_{TH}}} \tag{30}$$

It can be observed that effective voltage *VEFF* in relation to *RON* acts as argument of exponential function located in denominator, which implicates the substantial sensitivity to change of this quantity. In order to overcome this issue, many techniques such as dynamic control, feed-forward biasing of the bulk electrode, multistage topology, implementation of charge transfer switches (CTS) parallel with pass gate switches (PGS) or backward control of the previous stage by body electrode voltage can be included in the low-voltage CPs design [11–14].

#### **3.6 Evaluation of the proposed LV circuits**

In order to fully verify the design concepts discussed in this chapter, the proposed circuit topologies have been designed in general purpose twin-well 130 nm CMOS technology. Both types of fabricated long-channel devices exhibit the standard threshold voltage around *VTH* = 260 mV at room temperature. **Figure 18** depicts the micrograph of the fabricated prototype chip along with the physical layout design. For better clarity, we omitted some of the top metal layers. The blue rectangles pin-point the location of the proposed circuits on chip. The chip also contains a stand-alone test transistor in order to verify the devices' compact simulation model accuracy and fabrication process fluctuations as well.

**Figure 18.** *Micrograph and physical design of the prototype chip.*

level, which improves its drain current and switching speed. The trade-off of this

Dynamic threshold inverter topology (**Figure 16(c)**) can be considered as an appropriate building cell for ultra-low-power and low-voltage charge pump designs. A very important design consideration for such a system is inevitability of twin-well CMOS fabrication process, since both PMOS and NMOS devices have to be isolated from the common substrate by their own wells. Another consideration is restricted power supply voltage. Its level must not exceed 0.6 V (at room temperature). Otherwise, parasitic NPN and PNP bipolar transistors will turn on, which with the high probability may cause triggering of latch-up effect. These limitations have to be taken into account, if designing the charge pump with dynamic *VTH* MOS

The BD charge pump based on the cross-coupled topology is shown in **Figure 17**. The charge pump employing dynamic threshold CMOS inverter is able to process very low levels of input voltages. This also represents the main advantage of the proposed topology [10]. However, the drawback lies in the limited voltage range the charge pump can work with, because of the increased risk of latch-up triggering. Hence, the main application area of such charge pump topology is constrained to

Theoretical value of the output voltage can be expressed as follows:

*Cin Ctot*

� *IL Ron* þ

*Req* 2

, (29)

*Vout* ¼ *Vin* þ *N Vϕ:*

method is increased leakage current of one transistor only.

inverters.

**38**

**Figure 17.**

*Bulk-driven cross-coupled CP (one stage).*

*Integrated Circuits/Microchips*

low-voltage and low-power systems.

*3.5.2 Design procedure of BD charge pump*

a promising alternative to standard design approach and circuit topologies are discussed in this chapter. We presented low-voltage and low-power design techniques, which are focused on driving the MOS transistor through its bulk terminal, as well as setting the operating point of employed MOS transistors within the subthreshold (weak inversion) or moderate inversion region. The combination of described design techniques provides the significant power consumption minimization (nW feasible), while maintaining acceptable circuit performance and parameters. The motivation for research and development in given scientific field is enormous and new published results are expected to grow in upcoming years. The proposed circuit topologies of basic analog IC building blocks have been designed and fabricated in 130 nm twin-well general purpose CMOS technology with industrial operating temperature range taken into account. The experimental measurements performed on the prototype chip samples confirm a successful implementation and correct circuit operation with ultra-low-power supply voltage. Hence, we can state that the feasibility of presented IC design approach has been successfully demonstrated and the circuit topologies have been silicon-proven, which opens the door for even deeper gradual investigation and understanding of given scientific topic with promising future impact on the IC industry as well.

*Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

**Author details**

**41**

Daniel Arbet†, Lukas Nagy† and Viera Stopjakova\*†

\*Address all correspondence to: viera.stopjakova@stuba.sk

of Technology, Bratislava, Slovakia

† These authors contributed equally.

provided the original work is properly cited.

Faculty of Electrical Engineering and Information Technology, Slovak University

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

**Figure 19.**

*Measured and simulated parameters of the proposed circuit topologies on the prototype chip. (a) VGA frequency response, (b) Comparator transfer characteristics, (c) Charge-Pump efficiency.*

The selected parameters of the proposed VGA, voltage comparator, and charge pump are depicted in **Figure 19**. The graphs contain the measured and simulated results for direct comparison and evaluation.

The comparison of simulated and measured data of frequency response of the proposed VGA is depicted in **Figure 19(a)**. We used the Monte-Carlo analysis results to obtain the borders of the expected gain range. As one can observe, the measured frequency response remains between the borders specified by the simulation and deviates only slightly from the Monte-Carlo mean curve. The measurement and simulation conditions were identical, the load capacitance of 10 pF, the control voltage *VCTRL* = 0.1 V, ambient room temperature, and power supply voltage of *VDD* = 0.6 V were used. The obtained measured results at these operating conditions were the following. The voltage gain of *aV* = 30 dB, gain-bandwidth of GBW = 1.2 MHz and bandwidth of *f*<sup>3</sup>*dB* = 40 kHz were observed. The worst-case discrepancy of the measured low-frequency gain compared to the mean Monte-Carlo curve is approximately 5.85 dB.

The transfer characteristics of the proposed rail-to-rail comparator are depicted in **Figure 19(b)**. The simulated results correlate very well with measured curves for all input voltage conditions. In our experiments, the comparator exhibited correct function for all four levels of hysteresis and the rail-to-rail operation has been confirmed by setting the reference voltage only 3 mV from the power supply range. This test can be considered quite strict, since it would also reveal issues with the input offset voltage. Monte-Carlo simulations performed on 3000 samples in corner and ambient temperatures resulted in the mean value of input offset *Voffset* = 592 uV with standard deviation of *σ* = 1.91 mV [15]. Furthermore, the power consumption at *VDD* = 0.4 V has been measured in the upper half of nW range including the ESD structures leakage, PCB, and oscilloscope probe parasitics. However, we have also observed correct operation with *VDD* = 0.25 V, which indeed astonishing result.

**Figure 19(c)** shows dependence of the efficiency on the output current. This is the example where the comparison of different charge pumps based on GD and BD cross-coupled inverter were compared. The best efficiency for the given parameters can be observed for the output current of 1*μA*, where the BD cross-coupled charge pump achieves the efficiency of 80% in four-stage architecture (N = 4) in given CMOS technology.

#### **4. Conclusions**

Considering the current onset of ultra-low-voltage and ultra-low-power operation requirements for today's CMOS analog/mixed-signal ICs and their fabrication,

#### *Ultra-Low-Voltage IC Design Methods DOI: http://dx.doi.org/10.5772/intechopen.91958*

a promising alternative to standard design approach and circuit topologies are discussed in this chapter. We presented low-voltage and low-power design techniques, which are focused on driving the MOS transistor through its bulk terminal, as well as setting the operating point of employed MOS transistors within the subthreshold (weak inversion) or moderate inversion region. The combination of described design techniques provides the significant power consumption minimization (nW feasible), while maintaining acceptable circuit performance and parameters. The motivation for research and development in given scientific field is enormous and new published results are expected to grow in upcoming years.

The proposed circuit topologies of basic analog IC building blocks have been designed and fabricated in 130 nm twin-well general purpose CMOS technology with industrial operating temperature range taken into account. The experimental measurements performed on the prototype chip samples confirm a successful implementation and correct circuit operation with ultra-low-power supply voltage. Hence, we can state that the feasibility of presented IC design approach has been successfully demonstrated and the circuit topologies have been silicon-proven, which opens the door for even deeper gradual investigation and understanding of given scientific topic with promising future impact on the IC industry as well.
