High Capacitance Dielectrics for Low Voltage Operated OFETs

*Navid Mohammadian and Leszek A. Majewski*

### **Abstract**

Low-voltage, organic field-effect transistors (OFETs) have a high potential to be key components of low-cost, flexible, and large-area electronics. However, to be able to employ OFETs in the next generation of the electronic devices, the reduction of their operational voltage is urgently needed. Ideally, to be power efficient, OFETs are operated with gate voltages as low as possible. To fulfill this requirement, low values of transistor threshold voltage (*Vt*) and subthreshold swing (*SS*) are essential. Ideally, *Vt* should be around 0 V and *SS* close to 60 mV/dec, which is the theoretical limit of subthreshold swing at 300 K. This is a very challenging task as it requires the gate dielectric thickness to be reduced below 10 nm. Here, the most promising strategies toward high capacitance dielectrics for low voltage operated OFETs are covered and discussed.

**Keywords:** thin-film transistor (TFT), organic field-effect transistor (OFET), low voltage transistor operation, high gate capacitance, ultra-thin dielectric, high-k dielectric, high-k/low-k hybrid dielectric, self-assembled monolayer (SAM), anodization

#### **1. Introduction**

In this chapter, the most important approaches toward reducing the operating voltage of organic field-effect transistors (OFETs) are described. First, the operation principle of OFETs is covered. This includes the description of the most common organic FET structures and the discussion of the device physics, which has mostly been derived from the theory of the metal-oxide-semiconductor field-effect transistor (MOSFET). Next, the key parameters of organic field-effect transistors that determine the operational voltage of these devices are discussed. Then, compatible electronic materials and device fabrication methods for low voltage operated OFETs are introduced. Finally, the chapter ends by presenting the state-of-the-art low voltage organic transistors and describing the latest key developments relating to manufacturing of such devices.

This chapter is organized in the following order: first, a brief overview of thinfilm transistor (TFT) history, applications, device architectures, as well as the basics of TFT operation and differences among TFTs, OFETs, and MOSFETs are presented in Section 2; then, different methods of decreasing the operating voltage of TFTs and OFETs are considered, and various electronic materials and fabrication techniques, which are used to realize low voltage transistor operation, are discussed in Section 3. Lastly, the key findings of this chapter are summarized in conclusions.

#### **2. Thin-film transistors (TFTs)**

Thin-film transistors (TFTs) were first introduced by Weimer in 1962 and are a class of field-effect transistors (FETs), which rely on the application of an electric field to the gate electrode to modulate the density of charge carriers in the channel, which is formed at the dielectric/semiconductor interface. A typical FET is made by stacking thin films of a semiconductor layer, a dielectric layer, and metal contacts. Therefore, it behaves in a similar way to the metal-oxide-semiconductor field-effect transistor (MOSFET). Even though TFTs and MOSFETs have been developed simultaneously, MOSFETs have dominated the majority of microelectronic research interests and industrial production due to their much better performance. However, the high MOSFET performance usually comes with high cost and high temperature processing, which is not compatible with the growing demand for low cost, low temperature processing of flexible, stretchable, and large-area electronics. Other dissimilarities between TFTs and MOSFETs, as shown in **Figure 1**, include structural and material differences. Usually, TFTs are made on insulating substrates [e.g. glass or flexible films such as polyethylene terephthalate (PEN) or poly(ethylene terephthalate) (PET)], while MOSFETs are fabricated on semiconducting silicon wafers that simultaneously act as substrates and device active layers. Importantly, both types of transistors operate in a fundamentally different way: MOSFETs operate in the inversion mode, and TFTs operate in the accumulation (enhancement) mode [1, 2].

nowadays, OFETs can compete with or even surpass a-Si:H TFTs in a broad range

In addition, it is believed that many next generation electronic devices will be portable and thus will require considerably reduced power consumption. As a result, the rapid development of low voltage TFTs and OFETs is highly desirable. However, before such low power devices can be realized, a significant reduction in transistor operational voltage is required. Unfortunately, it is still extremely challenging for both organic and metal oxide semiconductor transistors to achieve high performance and low operating voltages at the same time [7–9]. In this chapter, the most promising approaches toward high capacitance dielectrics for high performance, low voltage TFTs, and OFETs are discussed and evaluated.

Organic field-effect transistors can be fabricated on a variety of rigid and flexible substrates, namely, silicon/silicon oxide wafers, glass, PEN, PET, and other types of flexible films. Depending on the position of the gate electrode and where each layer is deposited, OFETs are categorized into four different structures, namely, coplanar bottom-gate, staggered bottom-gate, coplanar top-gate, and staggered top-gate, as shown in **Figure 2**. Staggered (also called bottom-contact) or coplanar (also called top-contact) configurations refer to whether the drain/source and gate electrodes are on the opposite or on the same side regarding the semiconductor layer. Although all of the abovementioned structures are used in the fabri-

cation of OFETs, each of them shows a better performance in a particular

application, and/or due to the fabrication limitations, one is more desirable than the other [3, 10]. For example, the coplanar top-gate structure is routinely used in flat

Although Si is the most common material used in electronics due to its advantages such as abundancy, low cost manufacturing, ease of doping, and high charge carrier mobility, novel applications in electronics such as flexible, stretchable, and large-area circuits and displays have directed the attention of scientists to alternative materials. Frequently, electronic devices such as discrete sensors, simple displays, as well as basic RFID tags and smart cards are realized in various shapes and sizes, and thus, unconventional electronic materials and device processing techniques have had to be researched to appropriately respond to these upward demands. From the most recent trends in material research, it appears that organic and metal oxide semiconductors are the two most promising alternatives to silicon

of electronic applications [6].

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

for low cost electronic applications.

**2.1 OFET architectures**

**Figure 2.**

**89**

*The most common structures of OFETs.*

The demand for low cost, large-area applications in flat panel displays (FPDs) fuelled research on finding a viable substitution for crystalline and polycrystalline silicon. In 1979, significantly cheaper amorphous hydrogenated silicon (a-Si:H) was developed, and subsequently, it was introduced to thin-film transistors as the active layer that resulted in an increased interest in TFTs [3]. Since then, the use of a-Si:H TFTs has gradually grown, and eventually, they have started to dominate the whole liquid crystal display (LCD) industry. Nowadays, a-Si:H TFTs are the backbone of both active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diode (AMOLED) display technologies.

In 1987, Koezuka et al. reported a special type of TFTs that used organic semiconductors as the active layer, so-called organic field-effect transistors (OFETs). The demonstrated devices used electrochemically polymerized polythiophene, which belongs to the family of conducting (i.e. conjugated) polymers (CPs) as the active layer [4]. Accordingly, it has been shown that the thin-film transistor design is the structure of choice for low conductivity materials such as organic semiconductors. As a result, the TFT design was utilized to realize a wide range of field-effect transistors using organic semiconductors (OSCs) [5]. Since then, the performance of organic semiconductors has continuously improved, and

#### **Figure 1.**

*Typical structures of (a) a bottom-gate top-contact TFT and (b) a MOSFET. Doped regions refer to the MOSFET source and drain regions.*

nowadays, OFETs can compete with or even surpass a-Si:H TFTs in a broad range of electronic applications [6].

Although Si is the most common material used in electronics due to its advantages such as abundancy, low cost manufacturing, ease of doping, and high charge carrier mobility, novel applications in electronics such as flexible, stretchable, and large-area circuits and displays have directed the attention of scientists to alternative materials. Frequently, electronic devices such as discrete sensors, simple displays, as well as basic RFID tags and smart cards are realized in various shapes and sizes, and thus, unconventional electronic materials and device processing techniques have had to be researched to appropriately respond to these upward demands. From the most recent trends in material research, it appears that organic and metal oxide semiconductors are the two most promising alternatives to silicon for low cost electronic applications.

In addition, it is believed that many next generation electronic devices will be portable and thus will require considerably reduced power consumption. As a result, the rapid development of low voltage TFTs and OFETs is highly desirable. However, before such low power devices can be realized, a significant reduction in transistor operational voltage is required. Unfortunately, it is still extremely challenging for both organic and metal oxide semiconductor transistors to achieve high performance and low operating voltages at the same time [7–9]. In this chapter, the most promising approaches toward high capacitance dielectrics for high performance, low voltage TFTs, and OFETs are discussed and evaluated.

#### **2.1 OFET architectures**

**2. Thin-film transistors (TFTs)**

*Integrated Circuits/Microchips*

(enhancement) mode [1, 2].

**Figure 1.**

**88**

*MOSFET source and drain regions.*

Thin-film transistors (TFTs) were first introduced by Weimer in 1962 and are a class of field-effect transistors (FETs), which rely on the application of an electric field to the gate electrode to modulate the density of charge carriers in the channel, which is formed at the dielectric/semiconductor interface. A typical FET is made by stacking thin films of a semiconductor layer, a dielectric layer, and metal contacts. Therefore, it behaves in a similar way to the metal-oxide-semiconductor field-effect transistor (MOSFET). Even though TFTs and MOSFETs have been developed simultaneously, MOSFETs have dominated the majority of microelectronic research interests and industrial production due to their much better performance. However, the high MOSFET performance usually comes with high cost and high temperature processing, which is not compatible with the growing demand for low cost, low temperature processing of flexible, stretchable, and large-area electronics. Other dissimilarities between TFTs and MOSFETs, as shown in **Figure 1**, include

structural and material differences. Usually, TFTs are made on insulating substrates [e.g. glass or flexible films such as polyethylene terephthalate (PEN) or poly(ethylene terephthalate) (PET)], while MOSFETs are fabricated on semiconducting silicon wafers that simultaneously act as substrates and device active layers. Importantly, both types of transistors operate in a fundamentally different way: MOSFETs

The demand for low cost, large-area applications in flat panel displays (FPDs) fuelled research on finding a viable substitution for crystalline and polycrystalline silicon. In 1979, significantly cheaper amorphous hydrogenated silicon (a-Si:H) was developed, and subsequently, it was introduced to thin-film transistors as the active layer that resulted in an increased interest in TFTs [3]. Since then, the use of a-Si:H TFTs has gradually grown, and eventually, they have started to dominate the whole liquid crystal display (LCD) industry. Nowadays, a-Si:H TFTs are the backbone of both active matrix liquid crystal displays (AMLCDs) and active matrix

In 1987, Koezuka et al. reported a special type of TFTs that used organic semiconductors as the active layer, so-called organic field-effect transistors (OFETs). The demonstrated devices used electrochemically polymerized

polythiophene, which belongs to the family of conducting (i.e. conjugated) polymers (CPs) as the active layer [4]. Accordingly, it has been shown that the thin-film transistor design is the structure of choice for low conductivity materials such as organic semiconductors. As a result, the TFT design was utilized to realize a wide range of field-effect transistors using organic semiconductors (OSCs) [5]. Since then, the performance of organic semiconductors has continuously improved, and

*Typical structures of (a) a bottom-gate top-contact TFT and (b) a MOSFET. Doped regions refer to the*

operate in the inversion mode, and TFTs operate in the accumulation

organic light-emitting diode (AMOLED) display technologies.

Organic field-effect transistors can be fabricated on a variety of rigid and flexible substrates, namely, silicon/silicon oxide wafers, glass, PEN, PET, and other types of flexible films. Depending on the position of the gate electrode and where each layer is deposited, OFETs are categorized into four different structures, namely, coplanar bottom-gate, staggered bottom-gate, coplanar top-gate, and staggered top-gate, as shown in **Figure 2**. Staggered (also called bottom-contact) or coplanar (also called top-contact) configurations refer to whether the drain/source and gate electrodes are on the opposite or on the same side regarding the semiconductor layer. Although all of the abovementioned structures are used in the fabrication of OFETs, each of them shows a better performance in a particular application, and/or due to the fabrication limitations, one is more desirable than the other [3, 10]. For example, the coplanar top-gate structure is routinely used in flat

**Figure 2.** *The most common structures of OFETs.*

*IDS* <sup>¼</sup> *<sup>W</sup>*

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

It is usually determined by the following expression:

*SS* <sup>¼</sup> ln 10 *kbT*

parameters are as follows (cf. **Figure 3a**, **b**):

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

desirable.

*gm* <sup>¼</sup> *dIDS*

swing.

**91**

and in the saturation regime,

where *μsat* is the charge carrier mobility in the saturation regime.

<sup>2</sup>*<sup>L</sup> CGμsat*ð Þ *VGS* � *Vt* <sup>2</sup>

Typical output and transfer characteristics of an OFET operating at 1 V are illustrated in **Figure 3a**, **b**, respectively. In general, the most essential OFET

• Turn-on voltage (*VON*) is the value of *VGS* at which *IDS* starts to increase.

• Threshold voltage (*Vt*) is the minimum *VGS* at which the number of the accumulated charge carriers at the dielectric/semiconductor interface is sufficient to create a conduction path (channel) between the source and the drain electrodes. The lower *Vt*, the lower the operational voltage of an OFET.

• Subthreshold swing (*SS*) is the parameter, which describes the necessary *VGS* to increase *IDS* by one order of magnitude (decade) in the subthreshold region, i.e., *VON < VGS < Vt*. As small value of *SS* as possible is highly desirable because it leads to lower device power consumption and higher device switching speed.

*q*

• On-off current ratio defines a ratio of the measured maximum to minimum source-drain current. High "on" and low "off" currents in an OFET are highly

• The field-effect mobility of charge carriers in the linear (*μlin*) and saturation regimes (*μsat*) is usually determined by calculating the transconductance (i.e.,

> *d* ffiffiffiffiffiffi *IDS* <sup>p</sup> *dVGS* � �

> > 1 2 *Ci W L*

• The total interfacial trap density *Nit* of an OFET can be calculated by Eq. (6) [9]:

*kT=<sup>q</sup>* � <sup>1</sup> � � *Ci*

*dVGS*) in both regions, respectively. In the linear regime,

*μsat* ¼

*Nit* <sup>¼</sup> *SS* logð Þ*<sup>e</sup>*

where *Ci* is the gate capacitance density, *q* is the electron charge, *k* is the Boltzmann constant,*T* is the temperature in Kelvin, and *SS* is the subthreshold

*<sup>μ</sup>lin* <sup>¼</sup> *gm Ci W <sup>L</sup> VDS*

where *kb* is the Boltzmann constant,*T* is the temperature in Kelvin, *q* is the electron charge, *Ci* is the gate dielectric capacitance, and *Cch* is the effective channel capacitance.

1 þ *Cch Ci*

� �, (3)

, (4)

*<sup>q</sup>*<sup>2</sup> (6)

(5)

, (2)

**Figure 3.** *Typical output (a) and transfer (b) characteristics of a low voltage OFET operating at 1 V.*

panel displays. In this structure, the drain/source electrodes are self-aligned with the channel region, which result in the minimization of the parasitic capacitance that reduces image flicker and sticking [10]. Also, top-gate structures usually have higher mobility than their bottom-gate counterparts [11]. The coplanar bottom-gate structure is usually used in electronic nose applications (i.e. e-sensing) due to a larger sensing area [12]. As the device structure directly affects the device performance in terms of contact resistance, parasitic capacitance, charge carrier mobility, sensing capability, and so on, it is crucial to meticulously determine the device architecture regarding the intended use of the device.

#### **2.2 Fundamentals of OFET operation**

In an n-channel OFET operating in the accumulation (enhancement) mode, when a positive voltage bias is applied to the gate terminal, electrons start to accumulate at the dielectric/semiconductor interface, which forms a current path (channel) between the source and the drain contacts. Once the source-drain voltage bias is applied, the current starts to flow from the source to the drain electrode. As illustrated in **Figure 3**, depending on the condition of the channel, there are three different operation modes of OFETs, namely, cut-off region, as well as linear and saturation regimes. If the applied gate voltage (*VGS*) is below a certain value, i.e., smaller than the threshold voltage (*Vt*), then it is not possible to accumulate enough charges (i.e. electrons) to open the channel. Therefore, no current can flow in the channel, which is called a cut-off region. On the other hand, if *VGS* > *Vt*, one can have two scenarios: first, when the drain-source voltage (*VDS*) is equal or larger than *VGS*-*Vt*, the amount of the source-drain current (*IDS*) flowing in the channel is constant and the OFET works in the saturation regime; second, if *VDS* is lower than *VGS-Vt*, *IDS* follows the Ohm's law and the resistance of the channel (*RC*) is proportional to *VDS* and inversely proportional to *IDS*. This region is called the linear regime, and *IDS* is described by:

$$I\_{DS} = C\_G \mu\_{\rm lin} \frac{W}{L} [(V\_{GS} - V\_t)V\_{DS}],\tag{1}$$

where *CG* is the gate capacitance per unit area, *μlin* is the charge carrier mobility in the linear regime, *W* is the channel width, and *L* is the channel length of the device.

In the saturation regime, *VDS* is equal or larger than *VGS*-*Vt,* and *IDS* is independent of *VDS*. Therefore, the equation is simplified to:

*High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

$$I\_{\rm DS} = \frac{W}{\mathfrak{L}L} C\_{\rm G} \mu\_{\rm sat} (V\_{\rm GS} - V\_t)^2,\tag{2}$$

where *μsat* is the charge carrier mobility in the saturation regime.

Typical output and transfer characteristics of an OFET operating at 1 V are illustrated in **Figure 3a**, **b**, respectively. In general, the most essential OFET parameters are as follows (cf. **Figure 3a**, **b**):


$$\text{SS} = \ln 10 \frac{k\_b T}{q} \left( 1 + \frac{C\_{ch}}{C\_i} \right), \tag{3}$$

where *kb* is the Boltzmann constant,*T* is the temperature in Kelvin, *q* is the electron charge, *Ci* is the gate dielectric capacitance, and *Cch* is the effective channel capacitance.


$$
\mu\_{lin} = \frac{\mathcal{g}\_m}{\mathcal{C}\_i \frac{W}{L} V\_{DS}},
\tag{4}
$$

and in the saturation regime,

$$
\mu\_{\rm sat} = \frac{\left(\frac{d\sqrt{I\_{DS}}}{dV\_{GS}}\right)}{\frac{1}{2}C\_i \frac{W}{L}}\tag{5}
$$

• The total interfacial trap density *Nit* of an OFET can be calculated by Eq. (6) [9]:

$$N\_{it} = \left(\frac{\text{SS}\,\log(e)}{kT/q} - 1\right)\frac{C\_i}{q^2} \tag{6}$$

where *Ci* is the gate capacitance density, *q* is the electron charge, *k* is the Boltzmann constant,*T* is the temperature in Kelvin, and *SS* is the subthreshold swing.

panel displays. In this structure, the drain/source electrodes are self-aligned with the channel region, which result in the minimization of the parasitic capacitance that reduces image flicker and sticking [10]. Also, top-gate structures usually have higher mobility than their bottom-gate counterparts [11]. The coplanar bottom-gate structure is usually used in electronic nose applications (i.e. e-sensing) due to a larger sensing area [12]. As the device structure directly affects the device performance in terms of contact resistance, parasitic capacitance, charge carrier mobility, sensing capability, and so on, it is crucial to meticulously determine the device

*Typical output (a) and transfer (b) characteristics of a low voltage OFET operating at 1 V.*

In an n-channel OFET operating in the accumulation (enhancement) mode, when a positive voltage bias is applied to the gate terminal, electrons start to accumulate at the dielectric/semiconductor interface, which forms a current path (channel) between the source and the drain contacts. Once the source-drain voltage bias is applied, the current starts to flow from the source to the drain electrode. As illustrated in **Figure 3**, depending on the condition of the channel, there are three different operation modes of OFETs, namely, cut-off region, as well as linear and saturation regimes. If the applied gate voltage (*VGS*) is below a certain value, i.e., smaller than the threshold voltage (*Vt*), then it is not possible to accumulate enough charges (i.e. electrons) to open the channel. Therefore, no current can flow in the channel, which is called a cut-off region. On the other hand, if *VGS* > *Vt*, one can have two scenarios: first, when the drain-source voltage (*VDS*) is equal or larger than *VGS*-*Vt*, the amount of the source-drain current (*IDS*) flowing in the channel is constant and the OFET works in the saturation regime; second, if *VDS* is lower than *VGS-Vt*, *IDS* follows the Ohm's law and the resistance of the channel (*RC*) is proportional to *VDS* and inversely proportional to *IDS*. This region is called the linear

architecture regarding the intended use of the device.

**2.2 Fundamentals of OFET operation**

**Figure 3.**

*Integrated Circuits/Microchips*

regime, and *IDS* is described by:

**90**

*IDS* ¼ *CGμlin*

dent of *VDS*. Therefore, the equation is simplified to:

*W*

where *CG* is the gate capacitance per unit area, *μlin* is the charge carrier mobility in the linear regime, *W* is the channel width, and *L* is the channel length of the device. In the saturation regime, *VDS* is equal or larger than *VGS*-*Vt,* and *IDS* is indepen-

*<sup>L</sup>* ½ � ð Þ *VGS* � *Vt VDS* , (1)

#### **3. Low voltage OFETs**

As mentioned in the previous section, *IDS* is described in the linear and saturation regimes by Eqs. (2) and (3), respectively. In the ideal case, the source-drain current should be maximum, while the gate bias voltage is as low as possible. However, this only can be achieved when both the threshold voltage (*Vt*) and the subthreshold swing (*SS*) are sufficiently low enabling an OFET to be operated at a low voltage and maximum performance [13]. Referring back to Eq. (2), the only parameters that can be changed to compensate the reduction in *IDS* are the gate dielectric capacitance (*CG*) and the channel width (*W*) and length (*L*). However, *W* and *L* depend on the device geometry. Therefore, in order to accumulate the same number of charges within the channel of an OFET and maintain high *IDS*, it is essential to increase the gate dielectric capacitance (*CG*). One may argue that increasing the gate capacitance may deteriorate the transistor's switching speed. Indeed, the maximum switching speed of an OFET is usually defined by its cut-off frequency *fc* as shown in Eq. (7) [14]:

$$f\_c = \frac{\mathbf{g}\_m}{2\pi \mathbf{C}\_G} = \frac{\mu (V\_G - V\_t)}{2\pi L^2},\tag{7}$$

net electric dipole moment of polar dielectrics is zero. Applying an external electric field forces the atoms or molecules within the polar dielectric medium to change their orientation and alignment to the electric field. The alignment of dipoles can be increased by increasing the external electric field and decreasing the temperature. On the contrary, nonpolar atoms and molecules do not have permanent dipole moment. When nonpolar atoms or molecules are subjected to an external electric field, the positive and negative charges are displaced in the opposite direction. This displacement continues until the external force is balanced by the restoring force due to the internal electric field. The internal electric field created due to the polarization of the dielectric is always opposite to the direction of the external electric field. Hence, the net electric field is reduced because of the polarization of the dielectric medium. However, when the external electric field is removed, the dipole moments of each nonpolar atom and molecule of the dielectric medium

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

In the case of a parallel plate capacitor, which consists of two parallel plates separated by a distance *d*, the electric field (*E*) is described by *E = V/d*, where *V* is a bias voltage applied to the capacitor. In vacuum, the charge (*Q*) on the plates is linearly proportional to the applied electric field and determined

*<sup>Q</sup>* <sup>¼</sup> *<sup>ε</sup>*0*<sup>E</sup>* <sup>¼</sup> *<sup>ε</sup>*0*<sup>V</sup>*

The ability of the capacitor to store charges is measured by its capacitance (*C*)

*<sup>V</sup>* <sup>¼</sup> *<sup>ε</sup>*<sup>0</sup>

*<sup>C</sup>* <sup>¼</sup> *<sup>Q</sup>*

between the plates, *Q* is the accumulated charge, and *V* is the potential difference between the plates. The polarization of a dielectric in a capacitor increases the capacitance by a factor equal to the relative permittivity *ε<sup>r</sup>* of the material (also

*C* ¼ *ε*0*ε<sup>r</sup>*

permittivity, *A* is the plate overlap area, and *d* is the distance between the two

appears to be much more viable option. However, the development of new

As shown in Eq. (10), the capacitance varies directly with *ɛ<sup>r</sup>* (*k*) and inversely with *d*. Consequently, in order to increase the capacitance of a parallel plate capacitor, two approaches are usually considered: the increase of *C* can be accomplished, first, by decreasing the dielectric thickness (*d*) and, second, by increasing the dielectric constant (*k*). However, conventional dielectric materials such as silicon dioxide or silicon nitride, which have been used abundantly in diverse applications throughout electronic devices, have reached their fundamental material limits, and decreasing their thickness below 2 nm is extremely challenging because it results in significantly increased leakage currents, which strongly affects the transistor operation reliability and its performance [18]. As a result, increasing *C* by employing high dielectric constant (high-k) materials using existing or novel high-k materials

*A*

where *<sup>ε</sup><sup>0</sup>* is the vacuum permittivity (8.86 � <sup>10</sup>–<sup>12</sup> <sup>C</sup><sup>2</sup>

where *<sup>ε</sup><sup>0</sup>* is the vacuum permittivity (8.86 � <sup>10</sup>–<sup>12</sup> <sup>C</sup><sup>2</sup>

referred to as the dielectric constant *k*). Accordingly,

*<sup>d</sup>* (8)

*<sup>d</sup>* (9)

*<sup>d</sup>* (10)

N�<sup>1</sup> m�<sup>2</sup>

), *d* is the distance

), *ɛ<sup>r</sup>* is the dielectric

N�<sup>1</sup> m�<sup>2</sup>

become zero.

by Eq. (8):

plates.

**93**

and is defined by:

where *μsat* is the charge carrier mobility in the saturation regime, *L* is the channel length, *VG* is the gate voltage, *Vt* is the threshold voltage, and *fc* is quantified by the *gm/CG* ratio.

As can be seen, increasing the gate capacitance directly decreases the cut-off frequency. However, low operation voltage OFETs are designed for completely different purposes and are typically not used in high switching speed applications because they are not meant to be a substitution for silicon-based transistors. For example, in OFET-based sensors, which generally sense analog quantities such as analyte concentration or pressure, the high operating frequency is not needed as analog quantities do not change rapidly [15]. Therefore, delivering the highest possible source-drain current at the lowest possible gate voltage is more critical than the high operation frequency. However, like in the design of any other electronic systems, some applications require high switching speed. It has been shown that thinning of the channel layer thickness [16] and engineering of the semiconductor/ dielectric interface in transistors may result in reduced trap density (*Nit*) within the channel [17], and in consequence, OFETs with improved *fc*. However, depending on the intended applications a trade-off situation should always be considered. To better understand the operation physics of organic FETs, the next part of this chapter discusses the background of dielectrics and the theory of parallel plate capacitors, as well as the influence of the gate insulator properties on the performance of OFETs.

#### **3.1 Dielectrics: background**

By definition, an insulator is a material, which has an extremely high resistivity to electric current. In other words, a lack of charge transport in insulator materials leads to insulating behavior. In general, insulators can be polar or nonpolar. The main difference between polar and nonpolar dielectrics is that the atoms or molecules of polar dielectrics have an asymmetric shape, whereas the atoms or molecules of nonpolar dielectrics have a symmetric shape. Polar atoms or molecules have a permanent dipole moment, and thus, they behave like tiny electric dipoles. In the absence of an external electric field, the tiny dipoles are randomly arranged, and the *High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

**3. Low voltage OFETs**

*Integrated Circuits/Microchips*

frequency *fc* as shown in Eq. (7) [14]:

by the *gm/CG* ratio.

performance of OFETs.

**92**

**3.1 Dielectrics: background**

*fc* <sup>¼</sup> *gm* 2*πCG*

As mentioned in the previous section, *IDS* is described in the linear and saturation regimes by Eqs. (2) and (3), respectively. In the ideal case, the source-drain current should be maximum, while the gate bias voltage is as low as possible. However, this only can be achieved when both the threshold voltage (*Vt*) and the subthreshold swing (*SS*) are sufficiently low enabling an OFET to be operated at a low voltage and maximum performance [13]. Referring back to Eq. (2), the only parameters that can be changed to compensate the reduction in *IDS* are the gate dielectric capacitance (*CG*) and the channel width (*W*) and length (*L*). However, *W* and *L* depend on the device geometry. Therefore, in order to accumulate the same number of charges within the channel of an OFET and maintain high *IDS*, it is essential to increase the gate dielectric capacitance (*CG*). One may argue that increasing the gate capacitance may deteriorate the transistor's switching speed. Indeed, the maximum switching speed of an OFET is usually defined by its cut-off

<sup>¼</sup> *<sup>μ</sup>*ð Þ *VG* � *Vt*

where *μsat* is the charge carrier mobility in the saturation regime, *L* is the channel

As can be seen, increasing the gate capacitance directly decreases the cut-off frequency. However, low operation voltage OFETs are designed for completely different purposes and are typically not used in high switching speed applications because they are not meant to be a substitution for silicon-based transistors. For example, in OFET-based sensors, which generally sense analog quantities such as analyte concentration or pressure, the high operating frequency is not needed as analog quantities do not change rapidly [15]. Therefore, delivering the highest possible source-drain current at the lowest possible gate voltage is more critical than the high operation frequency. However, like in the design of any other electronic systems, some applications require high switching speed. It has been shown that thinning of the channel layer thickness [16] and engineering of the semiconductor/ dielectric interface in transistors may result in reduced trap density (*Nit*) within the channel [17], and in consequence, OFETs with improved *fc*. However, depending on the intended applications a trade-off situation should always be considered. To better understand the operation physics of organic FETs, the next part of this chapter discusses the background of dielectrics and the theory of parallel plate capacitors, as well as the influence of the gate insulator properties on the

By definition, an insulator is a material, which has an extremely high resistivity to electric current. In other words, a lack of charge transport in insulator materials leads to insulating behavior. In general, insulators can be polar or nonpolar. The main difference between polar and nonpolar dielectrics is that the atoms or molecules of polar dielectrics have an asymmetric shape, whereas the atoms or molecules of nonpolar dielectrics have a symmetric shape. Polar atoms or molecules have a permanent dipole moment, and thus, they behave like tiny electric dipoles. In the absence of an external electric field, the tiny dipoles are randomly arranged, and the

length, *VG* is the gate voltage, *Vt* is the threshold voltage, and *fc* is quantified

<sup>2</sup>*πL*<sup>2</sup> , (7)

net electric dipole moment of polar dielectrics is zero. Applying an external electric field forces the atoms or molecules within the polar dielectric medium to change their orientation and alignment to the electric field. The alignment of dipoles can be increased by increasing the external electric field and decreasing the temperature. On the contrary, nonpolar atoms and molecules do not have permanent dipole moment. When nonpolar atoms or molecules are subjected to an external electric field, the positive and negative charges are displaced in the opposite direction. This displacement continues until the external force is balanced by the restoring force due to the internal electric field. The internal electric field created due to the polarization of the dielectric is always opposite to the direction of the external electric field. Hence, the net electric field is reduced because of the polarization of the dielectric medium. However, when the external electric field is removed, the dipole moments of each nonpolar atom and molecule of the dielectric medium become zero.

In the case of a parallel plate capacitor, which consists of two parallel plates separated by a distance *d*, the electric field (*E*) is described by *E = V/d*, where *V* is a bias voltage applied to the capacitor. In vacuum, the charge (*Q*) on the plates is linearly proportional to the applied electric field and determined by Eq. (8):

$$Q = \varepsilon\_0 E = \frac{\varepsilon\_0 V}{d} \tag{8}$$

The ability of the capacitor to store charges is measured by its capacitance (*C*) and is defined by:

$$C = \frac{Q}{V} = \frac{\varepsilon\_0}{d} \tag{9}$$

where *<sup>ε</sup><sup>0</sup>* is the vacuum permittivity (8.86 � <sup>10</sup>–<sup>12</sup> <sup>C</sup><sup>2</sup> N�<sup>1</sup> m�<sup>2</sup> ), *d* is the distance between the plates, *Q* is the accumulated charge, and *V* is the potential difference between the plates. The polarization of a dielectric in a capacitor increases the capacitance by a factor equal to the relative permittivity *ε<sup>r</sup>* of the material (also referred to as the dielectric constant *k*). Accordingly,

$$C = \varepsilon\_0 \varepsilon\_r \frac{A}{d} \tag{10}$$

where *<sup>ε</sup><sup>0</sup>* is the vacuum permittivity (8.86 � <sup>10</sup>–<sup>12</sup> <sup>C</sup><sup>2</sup> N�<sup>1</sup> m�<sup>2</sup> ), *ɛ<sup>r</sup>* is the dielectric permittivity, *A* is the plate overlap area, and *d* is the distance between the two plates.

As shown in Eq. (10), the capacitance varies directly with *ɛ<sup>r</sup>* (*k*) and inversely with *d*. Consequently, in order to increase the capacitance of a parallel plate capacitor, two approaches are usually considered: the increase of *C* can be accomplished, first, by decreasing the dielectric thickness (*d*) and, second, by increasing the dielectric constant (*k*). However, conventional dielectric materials such as silicon dioxide or silicon nitride, which have been used abundantly in diverse applications throughout electronic devices, have reached their fundamental material limits, and decreasing their thickness below 2 nm is extremely challenging because it results in significantly increased leakage currents, which strongly affects the transistor operation reliability and its performance [18]. As a result, increasing *C* by employing high dielectric constant (high-k) materials using existing or novel high-k materials appears to be much more viable option. However, the development of new

dielectric materials that possess high k and simultaneously show low leakage currents and high dielectric breakdown strength is not easy. Despite the obvious advantages of these materials in capacitor and OFET applications, they also possess serious drawbacks such as highly polar surfaces, which result in high charge trap densities particularly at the semiconductor/dielectric interface and polarization effects in the bulk, which lead to instability of the transistor threshold voltage and appearance of the source-drain current hysteresis [19]. In this light, many attempts to develop new high-k materials that can be inexpensively processed using novel, low cost deposition techniques have recently been carried out. Lately, a wide range of novel high dielectric constant materials ranging from high-k organic/inorganic nanocomposites, through multilayer high-k/low-k dielectric stacks to ultra-thin anodized oxides has been reported as promising alternatives to the conventional high-k insulators [20, 21]. In general, the dielectric materials used in OFETs are usually divided into four main categories, namely, inorganic [22, 23], organic [24, 25], electrolyte [26, 27], and hybrid dielectrics [28, 29].

#### **3.2 Dielectrics in electronic devices**

Dielectrics in electronic devices are usually utilized as insulators between conduction layers. A very important physical property of each dielectric is its energy gap (*Eg*). A large *Eg* is favorable because it requires electrons to acquire tremendous energy for excitation and transfer from the valence band to the conduction band. Usually, high-k dielectric materials have smaller *Eg* than SiO2. In regard to the gate leakage current, small energy gaps may display a higher probability of direct tunneling across the dielectric by Schottky emission and/or Poole-Frenkel effect [30]. The relation between the energy gap and the dielectric constant of the most common inorganic high-k materials is illustrated in **Figure 4**. **Table 1** summarizes their most important electrical and structural properties. The major applications of high-k dielectrics are in capacitors [31], transistors [32], and memory devices such as dynamic random-access memory (DRAM) [33] and resistive memories (memristors) [34].

**3.3 Dielectrics in low voltage OFETs**

**Ref. Dielectric Method VG**

*Examples of low voltage OFETs using organic dielectrics.*

[17] Cross-linked PVA

[42] P(VDF-TrFE-CFE)

**Table 2.**

**95**

Organic dielectrics applied in OFETs are typically thicker than 200 nm because they are routinely deposited from solution by spin-coating, drop casting, or ink-jet printing, which result in low dielectric capacitance and subsequently in high operating voltage OFETs (*VGS* > 20 V) [36, 37]. Therefore, different methods have been used to overcome this problem including decreasing the gate dielectric thickness by depositing ultra-thin insulator films (*d* < 10 nm) [38, 39], utilizing high-k organic insulator materials [40], or doing both at the same time [41]. In case of using high-k materials [36], several groups have successfully employed high dielectric constant organic insulators and significantly lowered the operation voltage of OFETs. **Table 2** shows few examples of recently reported low voltage OFETs using organic dielectrics. Among them, Li et al. used a high-k relaxor ferroelectric polymer as the gate

*The most important electrical, physical, and structural properties of some high-k inorganic materials [35].*

**Material Dielectric constant (k) Energy gap (eV) Crystal structure** SiO2 3.9 9 Amorphous Al2O3 9 8.8 Amorphous Ta2O5 26 4.4 Amorphous

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

HfO2 25 5.8 Monoclinic, tetragonal, cubic ZrO2 25 5.8 Monoclinic, tetragonal, cubic

TiO2 80 3.5 Tetragonal (rutile, anatase, brookite) WO3 42 2.6 Monoclinic, tetragonal, rhombic

Nb2O5 40 3.4 Amorphous

La2O3 27 5.8 Hexagonal HfSiO4 11 6.5 Tetragonal Si3N4 5–7.5 5.3 Hexagonal, tetragonal

Y2O3 15 6 Cubic

dielectric (*k* ≈ 60) and reduced the transistor operating voltage to 3 V [42]. Although *VG* was reduced to 3 V, it has been found that highly polar dielectric materials possess high surface energy, which leads to increased trapping and, as a consequence, significantly lower field-effect mobility. Also, it turned out that the fluorinated surfaces of such materials are often incompatible with solution-processed

> **Ci (nF/cm<sup>2</sup> )**

[39] PVP Spin coating 3 250 Pentacene 0.5 <sup>10</sup><sup>5</sup> <sup>2006</sup>

[43] PVA Spin coating 3 27 rr-P3HT 0.1 <sup>10</sup><sup>3</sup> <sup>2012</sup>

**Semiconductor μ**

Spin coating 2 12.2 TIPS-pentacene 1 104 <sup>2012</sup>

Spin coating 3 330 pBTTTC16 0.4 0.2 104 <sup>2012</sup>

**(cm2 /Vs)** **ION/IOFF Year**

**(V)**

*3.3.1 Organic dielectrics*

**Table 1.**

**Figure 4.** *Dielectric constant (*k*) vs. energy gap (*Eg*) for the most common inorganic dielectric materials [35].*


*High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

**Table 1.**

dielectric materials that possess high k and simultaneously show low leakage currents and high dielectric breakdown strength is not easy. Despite the obvious advantages of these materials in capacitor and OFET applications, they also possess serious drawbacks such as highly polar surfaces, which result in high charge trap densities particularly at the semiconductor/dielectric interface and polarization effects in the bulk, which lead to instability of the transistor threshold voltage and appearance of the source-drain current hysteresis [19]. In this light, many attempts to develop new high-k materials that can be inexpensively processed using novel, low cost deposition techniques have recently been carried out. Lately, a wide range of novel high dielectric constant materials ranging from high-k organic/inorganic nanocomposites, through multilayer high-k/low-k dielectric stacks to ultra-thin anodized oxides has been reported as promising alternatives to the conventional high-k insulators [20, 21]. In general, the dielectric materials used in OFETs are usually divided into four main categories, namely, inorganic [22, 23], organic

Dielectrics in electronic devices are usually utilized as insulators between conduction layers. A very important physical property of each dielectric is its energy gap (*Eg*). A large *Eg* is favorable because it requires electrons to acquire tremendous energy for excitation and transfer from the valence band to the conduction band. Usually, high-k dielectric materials have smaller *Eg* than SiO2. In regard to the gate leakage current, small energy gaps may display a higher probability of direct tunneling across the dielectric by Schottky emission and/or Poole-Frenkel effect [30]. The relation between the energy gap and the dielectric constant of the most common inorganic high-k materials is illustrated in **Figure 4**. **Table 1** summarizes their most important electrical and structural properties. The major applications of high-k dielectrics are in capacitors [31], transistors [32], and memory devices such as dynamic random-access memory (DRAM) [33] and resistive memories

*Dielectric constant (*k*) vs. energy gap (*Eg*) for the most common inorganic dielectric materials [35].*

[24, 25], electrolyte [26, 27], and hybrid dielectrics [28, 29].

**3.2 Dielectrics in electronic devices**

*Integrated Circuits/Microchips*

(memristors) [34].

**Figure 4.**

**94**

*The most important electrical, physical, and structural properties of some high-k inorganic materials [35].*

#### **3.3 Dielectrics in low voltage OFETs**

#### *3.3.1 Organic dielectrics*

Organic dielectrics applied in OFETs are typically thicker than 200 nm because they are routinely deposited from solution by spin-coating, drop casting, or ink-jet printing, which result in low dielectric capacitance and subsequently in high operating voltage OFETs (*VGS* > 20 V) [36, 37]. Therefore, different methods have been used to overcome this problem including decreasing the gate dielectric thickness by depositing ultra-thin insulator films (*d* < 10 nm) [38, 39], utilizing high-k organic insulator materials [40], or doing both at the same time [41]. In case of using high-k materials [36], several groups have successfully employed high dielectric constant organic insulators and significantly lowered the operation voltage of OFETs. **Table 2** shows few examples of recently reported low voltage OFETs using organic dielectrics.

Among them, Li et al. used a high-k relaxor ferroelectric polymer as the gate dielectric (*k* ≈ 60) and reduced the transistor operating voltage to 3 V [42]. Although *VG* was reduced to 3 V, it has been found that highly polar dielectric materials possess high surface energy, which leads to increased trapping and, as a consequence, significantly lower field-effect mobility. Also, it turned out that the fluorinated surfaces of such materials are often incompatible with solution-processed


**Table 2.**

*Examples of low voltage OFETs using organic dielectrics.*

organic semiconductors (OSCs) [43]. Machado and Hümmelgen have shown that using high-k cross-linked poly(vinyl alcohol) (crPVA, *k* 6.2) as the gate dielectric might result in well-performing poly(3-hexyltiophene) (P3HT) OFETs [43]. However, their devices operated with *VGS* > 5 V, and they suffered from relatively high leakage currents (*ILeak* > 20 nA at *VGS* = 5 V) [44]. Apart from using high-k insulator materials, a lot of efforts have been devoted to develop ultra-thin dielectric films (*d* < 10 nm), which can be processed from solution. Both cross-linked polymers of minimum thickness (<50 nm) [44] and self-assembled monolayers (SAMs) (e.g. octadecylphosphonic acid, ODPA) have been explored as the potential gate dielectric candidates for OFETs [45, 46]. However, cross-linked polymers and SAMs have usually been used in the bottom-gate OFETs, as they are difficult to be deposited on top of organic semiconductors (cf. **Figure 2**). Also, the possibility of contamination of the active layer by cross-linking agents, which may contribute to increased leakage currents and electrical instability of the transistors, limits the use of ultra-thin cross-linked polymer insulators to bottom-gate OFETs. In addition, it turns out that ultra-thin dielectrics are not fully compatible with low cost, high throughput printing techniques, and it is very challenging to process them reliably over large-area flexible substrates [47].

abundantly used in the electronic industry as an insulator [13]. The competent insulating behavior makes Al2O3 particularly suitable for low voltage OFETs. Thanks to its amorphous crystal structure, it can be deposited using a wide range of deposition techniques including r.f. magnetron sputtering, plasma-assisted oxidation, sol-gel, anodization, and so on. Also, the availability of aluminum in the form of plastic aluminized foils makes it a potential material of choice for the next generation of smart electronic goods. Al2O3 can be very thin (*d* ≤ 3 nm) and still maintain excellent insulating properties. As such, it has received a lot of attention from different research groups working on low voltage inorganic TFTs and OFETs in recent years. For example, in 2011, Avis et al. proposed a 70-nm thick sol-gel AlO*<sup>x</sup>* as the gate dielectric for 5 V zinc-tin-oxide (ZTO) thin-film transistors [49]. In the same year, Lan et al*.* proposed a 140 nm anodic Al*x*O*<sup>y</sup>* for using in indium oxide (In2O3) and indium-gallium-zinc-oxide (IGZO) TFTs [50]. Although the reported transistors operated at 6 V, their application may be somewhat limited due to the high temperature processing (*T* 300°C). Even though the abovementioned TFTs are incompatible with most of flexible plastic substrates, they can still be used in printed electronics but on high temperature plastic films or rigid substrates (e.g. glass). In parallel research, Chen et al. proposed high performance, low voltage ZnO TFTs employing 100 nm Al2O3 deposited by DC magnetron sputtering as the gate dielectric [51]. The minimum operating voltage of the proposed devices was 4 V, but due to the thick Al2O3, the transistors could not be operated with lower VGS. In 2017, Cai et al. reported 1 V IGZO TFTs that employed a 3 nm thick solution processed anodic Al2O3 [52]. The demonstrated devices operated at 1 V, had on/off

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

, displayed field-effect mobilities of around 5.4 cm2

Vs, and possessed subthreshold swing of 68 mV/dec, which is close to the theoretical limit of *SS* at 300 K. In 2018, Ma et al. proposed low voltage IGZO TFTs using a

In addition, there were few attempts to use pristine aluminum oxide as the gate

subthreshold swing 0.6 V/decade. The low voltage device was achieved by growing the oxide layer using atomic layer deposition (ALD) technique. ALD provides high quality, pinhole free oxide layers and is typically used for high performance TFTs and FETs. However, this material deposition method requires very expensive equipment, and the materials have to be synthesized in high vacuum, which may not meet the demands of low cost, room temperature, large-area manufacturing of electronics. Sun et al. reported 3 V pentacene OFETs using 50 nm thick solution deposited Al2O3 [55]. The demonstrated devices possessed field-effect mobility near

5 nm Al2O3 dielectric that resulted in transistors operating at 0.6 V [53].

/Vs, *ION/IOFF* current ratio about 10<sup>5</sup>

/Vs, *ION/IOFF* current ratio about 10<sup>6</sup>

*3.3.2.2 Tantalum pentoxide (Ta2O5)*

insulator in OFETs. For example, Shang et al. proposed low threshold voltage pentacene OFETs and circuits [54]. The demonstrated devices possessed field-effect

threshold swing 107 mV/decade. However, it appears that the best performing OFETs have been obtained with SAM-modified Al2O3 where self-assembled monolayers are used as a buffer between the organic semiconductor and the aluminum

Tantalum pentoxide (Ta2O5) is a highly promising dielectric material because it has high transparency, high melting point (1785°C), high dielectric constant and shows good thermal and chemical stabilities. As such, it has been used in a wide range of electronic applications such as in dynamic random-access memory

(DRAM), metal-insulator-metal (MIM) capacitors, memory resistors (memristors), and recently in organic and inorganic TFTs [58]. The dielectric constant of Ta2O5

/

, threshold voltage 0.3 V, and

, threshold voltage 0.9 V, and sub-

current ratios larger than 10<sup>5</sup>

mobility 0.16 cm2

3 cm2

**97**

oxide [56, 57].

A promising way forward to address this problem and realize low voltage OFETs with low capacitance dielectrics is to use a material blend consisting of a small molecule organic semiconductor and an insulating polymer as the active layer. Using this approach, Feng et al. reported low voltage (*VGS* < 2 V), solution-processed organic FETs with gate capacitance as small as 12.2 nF/cm2 (cf. **Table 2**). This was achieved by employing a bottom-gate bottom-contact OFET architecture and using 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene and UV crosslinked polyvinyl alcohol (PVA) as the active and the gate dielectric layers, respectively. It has been claimed that the low subthreshold swing value (*SS* 100 mV/dec) was achieved due to a significant decrease in the effective channel capacitance described by Eq. (3) and very smooth PVA surface with a root-mean-square (RMS) roughness 0.3 nm, which contributed to the exceptionally low interface trap density.

In summary, to realize low voltage operated OFETs, low values of threshold voltage and subthreshold swing are required. Alternatively, one can achieve low voltage operated OFETs reducing the number of traps optimizing the dielectric/semiconductor interface. However, both approaches are not trivial, and more materials and device research are needed to find the optimal solutions for the intended applications.

#### *3.3.2 Inorganic dielectrics*

Today silicon is the most used material in the electronic industry. Si can be reacted with oxygen to form excellent dielectrics [1]. However, SiO2 has relatively low dielectric constant (*k* = 3.9), and therefore, it is rather problematic to realize low voltage (1 ≤ *VG* ≤ 3) and ultra-low voltage (*VG* ≤ 1) OFETs. Decreasing the thickness of SiO2 to achieve the required capacitances is extremely difficult because of the charge tunneling effect that significantly increases the gate leakage current when SiO2 is thinner than 2 nm. In this case, several alternative metal oxide dielectrics (e.g. Al2O3, HfO2, Ta2O5, ZrO2, TiO2, Y2O3, CeO2, etc.) have been investigated to be used as a gate insulator in OFETs [48]. Herein, we focus on the two most promising metal oxide dielectrics for OFETs, namely, Al2O3 and Ta2O5.

#### *3.3.2.1 Aluminum oxide (Al2O3)*

Aluminum oxide is an inert, water insoluble metal oxide, which due to large energy gap (*Eg* 8.8 eV), high dielectric constant (*k* 9), and the low cost is

#### *High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

organic semiconductors (OSCs) [43]. Machado and Hümmelgen have shown that using high-k cross-linked poly(vinyl alcohol) (crPVA, *k* 6.2) as the gate dielectric might result in well-performing poly(3-hexyltiophene) (P3HT) OFETs [43]. However, their devices operated with *VGS* > 5 V, and they suffered from relatively high leakage currents (*ILeak* > 20 nA at *VGS* = 5 V) [44]. Apart from using high-k insulator materials, a lot of efforts have been devoted to develop ultra-thin dielectric films (*d* < 10 nm), which can be processed from solution. Both cross-linked polymers of minimum thickness (<50 nm) [44] and self-assembled monolayers (SAMs) (e.g. octadecylphosphonic acid, ODPA) have been explored as the potential gate dielectric candidates for OFETs [45, 46]. However, cross-linked polymers and SAMs have usually been used in the bottom-gate OFETs, as they are difficult to be deposited on top of organic semiconductors (cf. **Figure 2**). Also, the possibility of contamination of the active layer by cross-linking agents, which may contribute to increased leakage currents and electrical instability of the transistors, limits the use of ultra-thin cross-linked polymer insulators to bottom-gate OFETs. In addition, it turns out that ultra-thin dielectrics are not fully compatible with low cost, high throughput printing techniques, and it is very challenging to process them reliably over large-area flexible

A promising way forward to address this problem and realize low voltage OFETs

with low capacitance dielectrics is to use a material blend consisting of a small molecule organic semiconductor and an insulating polymer as the active layer. Using this approach, Feng et al. reported low voltage (*VGS* < 2 V), solution-processed organic FETs with gate capacitance as small as 12.2 nF/cm2 (cf. **Table 2**). This was achieved by employing a bottom-gate bottom-contact OFET architecture and using 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene and UV crosslinked polyvinyl alcohol (PVA) as the active and the gate dielectric layers, respectively. It has been claimed that the low subthreshold swing value (*SS* 100 mV/dec) was achieved due to a significant decrease in the effective channel capacitance described by Eq. (3) and very smooth PVA surface with a root-mean-square (RMS) roughness 0.3 nm, which contributed to the exceptionally low interface trap density. In summary, to realize low voltage operated OFETs, low values of threshold voltage and subthreshold swing are required. Alternatively, one can achieve low voltage operated OFETs reducing the number of traps optimizing the dielectric/semiconductor interface. However, both approaches are not trivial, and more materials and device research are needed to find the optimal solutions for the intended applications.

Today silicon is the most used material in the electronic industry. Si can be reacted with oxygen to form excellent dielectrics [1]. However, SiO2 has relatively low dielectric constant (*k* = 3.9), and therefore, it is rather problematic to realize low voltage (1 ≤ *VG* ≤ 3) and ultra-low voltage (*VG* ≤ 1) OFETs. Decreasing the thickness of SiO2 to achieve the required capacitances is extremely difficult because of the charge tunneling effect that significantly increases the gate leakage current when SiO2 is thinner than 2 nm. In this case, several alternative metal oxide dielectrics (e.g. Al2O3, HfO2, Ta2O5, ZrO2, TiO2, Y2O3, CeO2, etc.) have been investigated to be used as a gate insulator in OFETs [48]. Herein, we focus on the two most

Aluminum oxide is an inert, water insoluble metal oxide, which due to large energy gap (*Eg* 8.8 eV), high dielectric constant (*k* 9), and the low cost is

promising metal oxide dielectrics for OFETs, namely, Al2O3 and Ta2O5.

substrates [47].

*Integrated Circuits/Microchips*

*3.3.2 Inorganic dielectrics*

*3.3.2.1 Aluminum oxide (Al2O3)*

**96**

abundantly used in the electronic industry as an insulator [13]. The competent insulating behavior makes Al2O3 particularly suitable for low voltage OFETs. Thanks to its amorphous crystal structure, it can be deposited using a wide range of deposition techniques including r.f. magnetron sputtering, plasma-assisted oxidation, sol-gel, anodization, and so on. Also, the availability of aluminum in the form of plastic aluminized foils makes it a potential material of choice for the next generation of smart electronic goods. Al2O3 can be very thin (*d* ≤ 3 nm) and still maintain excellent insulating properties. As such, it has received a lot of attention from different research groups working on low voltage inorganic TFTs and OFETs in recent years. For example, in 2011, Avis et al. proposed a 70-nm thick sol-gel AlO*<sup>x</sup>* as the gate dielectric for 5 V zinc-tin-oxide (ZTO) thin-film transistors [49]. In the same year, Lan et al*.* proposed a 140 nm anodic Al*x*O*<sup>y</sup>* for using in indium oxide (In2O3) and indium-gallium-zinc-oxide (IGZO) TFTs [50]. Although the reported transistors operated at 6 V, their application may be somewhat limited due to the high temperature processing (*T* 300°C). Even though the abovementioned TFTs are incompatible with most of flexible plastic substrates, they can still be used in printed electronics but on high temperature plastic films or rigid substrates (e.g. glass). In parallel research, Chen et al. proposed high performance, low voltage ZnO TFTs employing 100 nm Al2O3 deposited by DC magnetron sputtering as the gate dielectric [51]. The minimum operating voltage of the proposed devices was 4 V, but due to the thick Al2O3, the transistors could not be operated with lower VGS. In 2017, Cai et al. reported 1 V IGZO TFTs that employed a 3 nm thick solution processed anodic Al2O3 [52]. The demonstrated devices operated at 1 V, had on/off current ratios larger than 10<sup>5</sup> , displayed field-effect mobilities of around 5.4 cm2 / Vs, and possessed subthreshold swing of 68 mV/dec, which is close to the theoretical limit of *SS* at 300 K. In 2018, Ma et al. proposed low voltage IGZO TFTs using a 5 nm Al2O3 dielectric that resulted in transistors operating at 0.6 V [53].

In addition, there were few attempts to use pristine aluminum oxide as the gate insulator in OFETs. For example, Shang et al. proposed low threshold voltage pentacene OFETs and circuits [54]. The demonstrated devices possessed field-effect mobility 0.16 cm2 /Vs, *ION/IOFF* current ratio about 10<sup>5</sup> , threshold voltage 0.3 V, and subthreshold swing 0.6 V/decade. The low voltage device was achieved by growing the oxide layer using atomic layer deposition (ALD) technique. ALD provides high quality, pinhole free oxide layers and is typically used for high performance TFTs and FETs. However, this material deposition method requires very expensive equipment, and the materials have to be synthesized in high vacuum, which may not meet the demands of low cost, room temperature, large-area manufacturing of electronics. Sun et al. reported 3 V pentacene OFETs using 50 nm thick solution deposited Al2O3 [55]. The demonstrated devices possessed field-effect mobility near 3 cm2 /Vs, *ION/IOFF* current ratio about 10<sup>6</sup> , threshold voltage 0.9 V, and subthreshold swing 107 mV/decade. However, it appears that the best performing OFETs have been obtained with SAM-modified Al2O3 where self-assembled monolayers are used as a buffer between the organic semiconductor and the aluminum oxide [56, 57].

## *3.3.2.2 Tantalum pentoxide (Ta2O5)*

Tantalum pentoxide (Ta2O5) is a highly promising dielectric material because it has high transparency, high melting point (1785°C), high dielectric constant and shows good thermal and chemical stabilities. As such, it has been used in a wide range of electronic applications such as in dynamic random-access memory (DRAM), metal-insulator-metal (MIM) capacitors, memory resistors (memristors), and recently in organic and inorganic TFTs [58]. The dielectric constant of Ta2O5


or *n*-octadecyltrichlorosilane (ODTS). As reported in [64, 65], carrier mobility is significantly improved with increasing the SAM alkyl chain length, i.e., HMDS < OTS < ODTS, in comparison with the untreated surface [66]. Also, having a longer alkyl chain SAM improves adhesion and hydrophobicity of the modified

*n*-octadecyltrichlorosilane (ODTS) is a self-assembled monolayer that has previously been shown to have good compatibility with SiO2 and metal oxide dielectrics. Nowadays, it is typically used as a passivation layer for metal oxides providing capping of polar surfaces or as a hydrophobic coating layer preventing electrical instability of organic semiconductors and OFETs [3]. Essentially, ODTS appears to be one of the most used SAMs in organic FETs. It has been reported that ODTS significantly improves dielectric/semiconductor interface by passivating the metal oxide dielectric surface that leads to the reduction of charge carrier traps and, in consequence, to higher charge carrier mobility [66]. During silanization, ODTS molecules are attached to the dielectric surface through the chemical reaction of – SiCl with –OH groups on the metal oxide surface. This results in –Si–O–M structures. The other two –SiCl bonds of the ODTS molecule react with proximate OTS

To achieve the best of both worlds, several research groups have been researching the organic-inorganic bilayer and multilayer dielectrics (also known as hybrid and high-k/low-k dielectric) for low voltage OFETs. Liu et al. reported polymer fieldeffect transistors utilizing two diketopyrrolopyrrole (DPP)-based copolymers (i.e. PDQT and PDVT-10) as the semiconductor and OTS-modified poly(vinyl alcohol) (PVA) as the gate dielectric [68]. Their devices operated at around 3 V, and it was claimed that the OTS modification of PVA enhanced carrier mobility, lowered the leakage current, resulted in less hysteresis, and generally led to better performing devices than OFETs with untreated PVA. Urasinska-Wojcik et al. fabricated 1 V organic FETs using a mixed SAM/Al2O3 bilayer as the gate dielectric and poly(3,6-di (2-thien-5-yl)-2,5-di (2-octyldodecyl)-pyrrolo([3,4-c]pyrrole-1,4-dione) thieno [3,2-b] thiophene) (DPPDTT) as the organic semiconducting layer [57]. As reported, the self-assembled monolayer surface modification made Al2O3 surface smoother, and it was concluded that the SAM passivation helped tuning the threshold voltage and improved field-effect mobility of the proposed OFETs when compared with untreated devices. Mohammadian et al. proposed 1 V OFETs gated by ODTS-treated Ta2O5 and DPPDTT as the organic semiconductor [69]. The proposed transistors

V<sup>1</sup> s 1

, threshold

molecules, which form a cross-linked monolayer (**Figure 5**).

operated with the field-effect carrier mobility around 0.2 cm2

*3.3.3.2 Organic-inorganic hybrid dielectrics*

*Schematic representation of the silanization reaction.*

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

surface [67].

**99**

**Figure 5.**

#### **Table 3.**

*Examples of low voltage TFTs and OFETs using inorganic dielectrics.*

depends on its thickness and deposition technique and varies from 35 in the bulk to 25 in a thin film [59]. This is at least two to six times larger than the dielectric constant of Al2O3 (*k* = 9) and SiO2 (*k* = 3.9), respectively. As a result, Ta2O5 appears to be a good candidate as the gate dielectric in OFETs. Ta2O5 can be grown using different methods, namely, thermal oxidation, plasma-assisted oxidation, r.f. sputtering, atomic layer deposition, and anodization [60]. However, its dielectric properties can significantly differ depending on which of the growth methods is used. Recently, Chiu et al. have used a 200 nm e-beam deposited Ta2O5 for amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, which operated at 3 V [61]. Lately, Bartic et al*.* have proposed 3 V bottom-gate bottom-contact and top-gate bottom-contact P3HT OFETs employing a 100 nm film of Ta2O5 deposited by ebeam evaporation as the gate dielectric [62]. Although both inorganic and organic transistors have yielded high performance, e-beam evaporation is a relatively expensive deposition technique, and it is not compatible with the idea of low cost, large-area electronics. In addition, thick Ta2O5 films employed in the aforementioned TFTs made it impossible to operate the transistors at or below 1 V, which hinders their use in special applications such as portable, ultra-low power electronics, or aqueous sensors. **Table 3** summarizes all device parameters of the abovediscussed TFTs and OFETs.

#### *3.3.3 Organic-inorganic bilayer dielectrics*

#### *3.3.3.1 Self-assembled monolayers (SAMs)*

Self-assembled monolayers (SAMs) are ordered, two-dimensional organic molecular assemblies formed spontaneously by chemical absorption of an amphiphilic surfactant on a variety of substrates. In particular, silane SAMs are long-chain hydrocarbon molecules, which form an ordered supramolecular structure on solid surfaces after absorption. As such, they have been vastly used for surface modification and capping. One highly promising way to suppress the insulator surface charge traps in OFETs is to treat the transistor dielectric surface with hydrophobic SAMs, such as hexamethyldisilane (HMDS) [63], octyltrichlorosilane (OTS),

*High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

**Figure 5.** *Schematic representation of the silanization reaction.*

or *n*-octadecyltrichlorosilane (ODTS). As reported in [64, 65], carrier mobility is significantly improved with increasing the SAM alkyl chain length, i.e., HMDS < OTS < ODTS, in comparison with the untreated surface [66]. Also, having a longer alkyl chain SAM improves adhesion and hydrophobicity of the modified surface [67].

*n*-octadecyltrichlorosilane (ODTS) is a self-assembled monolayer that has previously been shown to have good compatibility with SiO2 and metal oxide dielectrics. Nowadays, it is typically used as a passivation layer for metal oxides providing capping of polar surfaces or as a hydrophobic coating layer preventing electrical instability of organic semiconductors and OFETs [3]. Essentially, ODTS appears to be one of the most used SAMs in organic FETs. It has been reported that ODTS significantly improves dielectric/semiconductor interface by passivating the metal oxide dielectric surface that leads to the reduction of charge carrier traps and, in consequence, to higher charge carrier mobility [66]. During silanization, ODTS molecules are attached to the dielectric surface through the chemical reaction of – SiCl with –OH groups on the metal oxide surface. This results in –Si–O–M structures. The other two –SiCl bonds of the ODTS molecule react with proximate OTS molecules, which form a cross-linked monolayer (**Figure 5**).

#### *3.3.3.2 Organic-inorganic hybrid dielectrics*

To achieve the best of both worlds, several research groups have been researching the organic-inorganic bilayer and multilayer dielectrics (also known as hybrid and high-k/low-k dielectric) for low voltage OFETs. Liu et al. reported polymer fieldeffect transistors utilizing two diketopyrrolopyrrole (DPP)-based copolymers (i.e. PDQT and PDVT-10) as the semiconductor and OTS-modified poly(vinyl alcohol) (PVA) as the gate dielectric [68]. Their devices operated at around 3 V, and it was claimed that the OTS modification of PVA enhanced carrier mobility, lowered the leakage current, resulted in less hysteresis, and generally led to better performing devices than OFETs with untreated PVA. Urasinska-Wojcik et al. fabricated 1 V organic FETs using a mixed SAM/Al2O3 bilayer as the gate dielectric and poly(3,6-di (2-thien-5-yl)-2,5-di (2-octyldodecyl)-pyrrolo([3,4-c]pyrrole-1,4-dione) thieno [3,2-b] thiophene) (DPPDTT) as the organic semiconducting layer [57]. As reported, the self-assembled monolayer surface modification made Al2O3 surface smoother, and it was concluded that the SAM passivation helped tuning the threshold voltage and improved field-effect mobility of the proposed OFETs when compared with untreated devices. Mohammadian et al. proposed 1 V OFETs gated by ODTS-treated Ta2O5 and DPPDTT as the organic semiconductor [69]. The proposed transistors operated with the field-effect carrier mobility around 0.2 cm2 V<sup>1</sup> s 1 , threshold

depends on its thickness and deposition technique and varies from 35 in the bulk to 25 in a thin film [59]. This is at least two to six times larger than the dielectric constant of Al2O3 (*k* = 9) and SiO2 (*k* = 3.9), respectively. As a result, Ta2O5 appears to be a good candidate as the gate dielectric in OFETs. Ta2O5 can be grown using different methods, namely, thermal oxidation, plasma-assisted oxidation, r.f. sputtering, atomic layer deposition, and anodization [60]. However, its dielectric properties can significantly differ depending on which of the growth methods is used. Recently, Chiu et al. have used a 200 nm e-beam deposited Ta2O5 for amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, which operated at 3 V [61]. Lately, Bartic et al*.* have proposed 3 V bottom-gate bottom-contact and top-gate bottom-contact P3HT OFETs employing a 100 nm film of Ta2O5 deposited by ebeam evaporation as the gate dielectric [62]. Although both inorganic and organic transistors have yielded high performance, e-beam evaporation is a relatively expensive deposition technique, and it is not compatible with the idea of low cost, large-area electronics. In addition, thick Ta2O5 films employed in the aforementioned TFTs made it impossible to operate the transistors at or below 1 V, which hinders their use in special applications such as portable, ultra-low power electronics, or aqueous sensors. **Table 3** summarizes all device parameters of the above-

[61] Ta2O5 e-beam 200 3 89 a-IGZO 61.5 <sup>10</sup><sup>5</sup> <sup>2010</sup> [62] Ta2O5 e-beam 100 2 185 P3HT 0.02 <sup>10</sup><sup>5</sup> <sup>2002</sup>

Self-assembled monolayers (SAMs) are ordered, two-dimensional organic molecular assemblies formed spontaneously by chemical absorption of an amphiphilic surfactant on a variety of substrates. In particular, silane SAMs are long-chain hydrocarbon molecules, which form an ordered supramolecular structure on solid surfaces after absorption. As such, they have been vastly used for surface modification and capping. One highly promising way to suppress the insulator surface charge traps in OFETs is to treat the transistor dielectric surface with hydrophobic SAMs, such as hexamethyldisilane (HMDS) [63], octyltrichlorosilane (OTS),

discussed TFTs and OFETs.

**98**

**Ref. Dielectric Method d**

sputtering

sputtering

*Examples of low voltage TFTs and OFETs using inorganic dielectrics.*

[51] Al2O3 D.C.

*Integrated Circuits/Microchips*

[60] Ta2O5 R.f.

**Table 3.**

**(nm)**

**VG (V)** **Ci (nF/ cm2 )**

[49] Al2O3 Sol–gel 70 3 80 ZTO 33 <sup>10</sup><sup>8</sup> <sup>2011</sup> [50] Al2O3 Anodization 140 4 54 IGZO 21.6 <sup>10</sup><sup>8</sup> <sup>2011</sup>

[52] Al2O3 Anodization 3 1 1000 IGZO 5.4 <sup>10</sup><sup>5</sup> <sup>2017</sup> [53] Al2O3 ALD 5 0.6 720 IGZO 3.8 <sup>10</sup><sup>6</sup> <sup>2018</sup> [54] Al2O3 ALD 30 3 165 Pentacene 0.16 <sup>10</sup><sup>5</sup> <sup>2011</sup> [55] Al2O3 Spin coating 50 3 125 Pentacene 2.7 <sup>10</sup><sup>6</sup> <sup>2016</sup>

**Semiconductor**

100 4 117 ZnO 27 <sup>10</sup><sup>6</sup> <sup>2012</sup>

130 3 163 Pentacene 0.8 66 2004

**μ (cm2 / Vs)**

**ION/ IOFF** **Year**

*3.3.3 Organic-inorganic bilayer dielectrics*

*3.3.3.1 Self-assembled monolayers (SAMs)*


**Table 4.**

*Parameters of the previously demonstrated low voltage OFETs using organic/inorganic bilayer dielectrics.*

voltage 0.55 V, subthreshold swing 120 mV/dec, and current on/off ratio in excess of 5 103 . The ODTS surface treatment used in the reported OFETs did not only make the surface smoother and improve the charge carrier mobility but also was used as a support of the main Ta2O5 dielectric. It was found that adding the extra insulator layer to the high-k dielectric increased its overall thickness and therefore decreased the gate capacitance, but because of low threshold voltage (VT = 0.55 V), 1 V OFET operation was still possible. The same approach toward the gate dielectric engineering for low voltage OFETs was reported in [70, 71]. **Table 4** summarizes the key parameters of all above-discussed OFETs.

high (*T* 300°C), and thus it cannot be used for majority of plastic substrates. Second, a number of research groups reported several percentages of carbon con-

Plasma-assisted oxidation is a widespread oxidation technique, which relies on oxidation of materials using highly reactive oxygen species. In general, oxidation of metals up to 2 nm is a straightforward process, but deeper oxidations are difficult to produce because the initial layer shields further oxidation. The description of the complete plasma oxidation process is complex and consists of several parts: volume processes in chemically active plasma of oxygen or its mixtures with inert gases, transport of particles through the transient region between undisturbed plasma and metal sample immersed into plasma, processes on the surface of the sample, and the transport of both oxygen and metal ions through the growing oxide layer. Importantly, oxygen plasma is also widely used for cleaning, etching, and removing unwanted organic residues from surfaces [73]. Hsiao et al. have shown that high quality Al2O3 and Ta2O5 can be successfully grown by plasma-assisted oxidation in a

Spin coating is a common method to produce thin, uniform polymer films on flat substrates. In the spin-coating process (**Figure 7**), the solution is first deposited on the substrate, and then it is accelerated rapidly to a desirable spin speed. This method is normally used for deposition of polymer films with thicknesses, which range from few nanometers to several micrometers. Depending on the spin speed, spin acceleration, and viscosity (concentration) of the solution, the thickness of the

The material discussed in this section is tantalum oxide (Ta2O5), which is generally used as an insulator in electronic devices such as capacitors, memristors,

tamination in the deposited oxide layers [72].

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

*Schematic of the r.f. magnetron sputtering process.*

*3.4.3 Plasma-assisted oxidation*

**Figure 6.**

controlled environment [72].

**101**

*3.4.4 Solution-based techniques: spin-coating*

deposited layers can be precisely controlled [74].

*3.4.5 Other solution-based techniques: anodization*

#### **3.4 High-k metal oxide deposition techniques**

#### *3.4.1 Radio frequency (r.f.) magnetron sputtering*

Radio frequency (r.f.) magnetron sputtering is a thin-film vapor deposition (PVD) technique. The process begins when a voltage is applied to a target material in the presence of argon gas. In such an instance, plasma is created in the surrounding of the target and ionized argon gas molecules start to bombard the target atoms. This bombardment leads the atoms to be sputtered off into the plasma. Then, these vaporized atoms are deposited when they condense as a thin film on the substrate. In order to properly deposit the sputtered materials, several process parameters should carefully be considered. First, the distance between the samples and the target should be optimized. Second, the chamber pressure should carefully be controlled to get the best quality of the deposited films. Last but not least the applied sputtering power should not exceed the maximum value for a given material because higher applied power could result in the target damage and poor quality of the deposited films. Usually, for Ta deposition r.f. magnetron sputtering is performed in the optimum pressure *<sup>P</sup>* = 5 <sup>10</sup>–<sup>3</sup> mBar, samples are 10 cm apart from the target and power does not exceed 70 W. **Figure 6** demonstrates the schematic of the r.f. magnetron sputtering deposition process.

#### *3.4.2 Atomic layer deposition (ALD)*

Atomic layer deposition (ALD) is a popular material deposition method, which is a subclass of chemical vapor deposition (CVD) technique. ALD is a high yield process delivering a highly conformal, pinhole free oxide layers at a relatively low temperature. In this process, two chemicals react with each other, and the oxide is achieved by repeating sequential, self-limiting surface reactions where precursors are separately deposited onto the substrate [59]. One ALD advantage in comparison with other vacuum deposition methods is that the oxide layer grows per cycle (GPC) allowing to have a sub-nanometer control over the deposited layer. ALD has two main drawbacks. First, the temperature of the oxidation process is relatively

*High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

**Figure 6.** *Schematic of the r.f. magnetron sputtering process.*

high (*T* 300°C), and thus it cannot be used for majority of plastic substrates. Second, a number of research groups reported several percentages of carbon contamination in the deposited oxide layers [72].

### *3.4.3 Plasma-assisted oxidation*

voltage 0.55 V, subthreshold swing 120 mV/dec, and current on/off ratio in excess

make the surface smoother and improve the charge carrier mobility but also was used as a support of the main Ta2O5 dielectric. It was found that adding the extra insulator layer to the high-k dielectric increased its overall thickness and therefore decreased the gate capacitance, but because of low threshold voltage (VT = 0.55 V), 1 V OFET operation was still possible. The same approach toward the gate dielectric engineering for low voltage OFETs was reported in [70, 71]. **Table 4** summarizes the

*Parameters of the previously demonstrated low voltage OFETs using organic/inorganic bilayer dielectrics.*

**(V)**

230 + OTS thickness

thickness

thickness

**Ci (nF/cm<sup>2</sup> )** **OSC μ (cm<sup>2</sup> /Vs)**

3 28 PDVT-10 11 <sup>10</sup><sup>4</sup> <sup>2014</sup>

1 340 PDPP2TTT 0.1 103 <sup>2015</sup>

1 670 DPPDTT 0.2 5 <sup>10</sup><sup>3</sup> <sup>2019</sup>

**ION/ IOFF** **Year**

Radio frequency (r.f.) magnetron sputtering is a thin-film vapor deposition (PVD) technique. The process begins when a voltage is applied to a target material in the presence of argon gas. In such an instance, plasma is created in the surrounding of the target and ionized argon gas molecules start to bombard the target atoms. This bombardment leads the atoms to be sputtered off into the plasma. Then, these vaporized atoms are deposited when they condense as a thin film on the substrate. In order to properly deposit the sputtered materials, several process parameters should carefully be considered. First, the distance between the samples and the target should be optimized. Second, the chamber pressure should carefully be controlled to get the best quality of the deposited films. Last but not least the applied sputtering power should not exceed the maximum value for a given material because higher applied power could result in the target damage and poor quality of the deposited films. Usually, for Ta deposition r.f. magnetron sputtering is performed in the optimum pressure *<sup>P</sup>* = 5 <sup>10</sup>–<sup>3</sup> mBar, samples are 10 cm apart from the target and power does not exceed 70 W. **Figure 6** demonstrates the

Atomic layer deposition (ALD) is a popular material deposition method, which is a subclass of chemical vapor deposition (CVD) technique. ALD is a high yield process delivering a highly conformal, pinhole free oxide layers at a relatively low temperature. In this process, two chemicals react with each other, and the oxide is achieved by repeating sequential, self-limiting surface reactions where precursors are separately deposited onto the substrate [59]. One ALD advantage in comparison with other vacuum deposition methods is that the oxide layer grows per cycle (GPC) allowing to have a sub-nanometer control over the deposited layer. ALD has two main drawbacks. First, the temperature of the oxidation process is relatively

key parameters of all above-discussed OFETs.

**Ref. Dielectric Method d (nm) VG**

coating

Anodization 4 + ODTS

Anodization 4 + ODTS

[68] PVA/OTS Spin-

*Integrated Circuits/Microchips*

[57] Al2O3/ OTS

[69] Ta2O5/ ODTS

**3.4 High-k metal oxide deposition techniques**

*3.4.1 Radio frequency (r.f.) magnetron sputtering*

schematic of the r.f. magnetron sputtering deposition process.

*3.4.2 Atomic layer deposition (ALD)*

**100**

. The ODTS surface treatment used in the reported OFETs did not only

of 5 103

**Table 4.**

Plasma-assisted oxidation is a widespread oxidation technique, which relies on oxidation of materials using highly reactive oxygen species. In general, oxidation of metals up to 2 nm is a straightforward process, but deeper oxidations are difficult to produce because the initial layer shields further oxidation. The description of the complete plasma oxidation process is complex and consists of several parts: volume processes in chemically active plasma of oxygen or its mixtures with inert gases, transport of particles through the transient region between undisturbed plasma and metal sample immersed into plasma, processes on the surface of the sample, and the transport of both oxygen and metal ions through the growing oxide layer. Importantly, oxygen plasma is also widely used for cleaning, etching, and removing unwanted organic residues from surfaces [73]. Hsiao et al. have shown that high quality Al2O3 and Ta2O5 can be successfully grown by plasma-assisted oxidation in a controlled environment [72].

### *3.4.4 Solution-based techniques: spin-coating*

Spin coating is a common method to produce thin, uniform polymer films on flat substrates. In the spin-coating process (**Figure 7**), the solution is first deposited on the substrate, and then it is accelerated rapidly to a desirable spin speed. This method is normally used for deposition of polymer films with thicknesses, which range from few nanometers to several micrometers. Depending on the spin speed, spin acceleration, and viscosity (concentration) of the solution, the thickness of the deposited layers can be precisely controlled [74].

#### *3.4.5 Other solution-based techniques: anodization*

The material discussed in this section is tantalum oxide (Ta2O5), which is generally used as an insulator in electronic devices such as capacitors, memristors,

**Figure 7.** *Schematic of the spin-coating process.*

TFTs, and OFETs. One of the most reliable and straightforward ways to form tantalum oxide is electrochemical oxidation (so-called anodization). Several metals such as Al, Ti, and Ta have very high chemical affinity with oxygen. Therefore, under ambient conditions, they will rapidly react with this gas forming a "native oxide" on their surfaces. The "air-formed" oxide film protects the metals from further oxidation (i.e. oxidation of the metal bulk) but is extremely thin—its thickness varies from a few angstroms to circa 2 nm, and it is very often not homogenous in thickness and can contain numerous defects and flaws. For example, the native oxide layer of tantalum has been reported to be usually around 3–4 nm [75]. As a result, the native oxide cannot be used as a protective film for preventing corrosion or as an insulator in capacitors and transistors.

**Figure 9** illustrates the electric drive conditions for anodization in constant current mode (*IA* = const.). In the constant current mode, the thickness of an oxide depends only on the cell voltage, which is allowed to rise to the required value, i.e. the thickness *d* of the resulting films can be very precisely controlled via anodization voltage *VA* because *d=cVA*, where *c* is the anodization ratio describing the thickness of the formed film per applied volt (Å/V). Importantly, *c* is related to the

*Anodization voltage (*VA*) and anodization current (*IA*) vs. anodization time (*t*).*

*High Capacitance Dielectrics for Low Voltage Operated OFETs*

*DOI: http://dx.doi.org/10.5772/intechopen.91772*

1 . The anodization current *IA* is kept constant via the anodization voltage *VA* compensation until the desired voltage is achieved and then decreases to very low values. The "leakage current" flowing under constant voltage conditions is electronic, but if the voltage is increased, then ionic current begins to flow again with further film formation until a new equilibrium is established. However, it is not possible to increase the voltage to a very high value. The upper limit on voltage lies between 500 and 700 V due to breakdown and arcing in the barrier layer. The most interesting fact is that the thickness of the barrier type film is not affected by electrolyzing time, surface roughness, and temperature of the electrolyte. In fact, the formed oxide film will exactly follow or slightly smooth out the initial surface

The anodization ratio of tantalum anodized in 1 mM citric acid (CA) has been reported in the literature [74–76] and usually is between 1.8 and 2.2 nm/V. **Table 5** compares the information relating to the anodization of metals and in particular

**Ref. Metal oxide Anodization ratio (nm/V) Forming electrolyte** [74] Ta2O5 1.8 0.1 M H3PO4 [75] Ta2O5 2.2 0.01 M CA [76] Ta2O5 2.0 0.01 M CA [77] TiO2 1.5 0.001 M CA [66] Al2O3 1.3 0.001 M CA

*A summary of anodization ratios and forming electrolytes relating to the anodization of Al2O3, TiO2*

electric breakdown field *EB* via *EB* ≈ *c*

**Figure 9.**

topography of the anodized metal.

*CA—citric acid.*

**Table 5.**

**103**

*and Ta2O5.*

anodization of tantalum in the recent works [68, 78–80].

Anodization is an electrochemical process, which allows improving this natural oxide film and produces stable oxide films with negligible reactivity. **Figure 8** shows a typical anodization bath to perform the oxidation. During the process, the metal to be oxidized is made the anode. An electrolytic cell is filled with an electrolyte. It has been shown previously that the nature of the electrolyte determines the type of anodic oxide film. The electric circuit is completed with a counter electrode which is made of a chemically inert metal (e.g. Au, Pt) or alloy (e.g. stainless steel). In **Figure 8**, an Au plate is shown as the cathode.

**Figure 8.** *Schematic of the anodization process.*

*High Capacitance Dielectrics for Low Voltage Operated OFETs DOI: http://dx.doi.org/10.5772/intechopen.91772*

**Figure 9.** *Anodization voltage (*VA*) and anodization current (*IA*) vs. anodization time (*t*).*

**Figure 9** illustrates the electric drive conditions for anodization in constant current mode (*IA* = const.). In the constant current mode, the thickness of an oxide depends only on the cell voltage, which is allowed to rise to the required value, i.e. the thickness *d* of the resulting films can be very precisely controlled via anodization voltage *VA* because *d=cVA*, where *c* is the anodization ratio describing the thickness of the formed film per applied volt (Å/V). Importantly, *c* is related to the electric breakdown field *EB* via *EB* ≈ *c* 1 .

The anodization current *IA* is kept constant via the anodization voltage *VA* compensation until the desired voltage is achieved and then decreases to very low values. The "leakage current" flowing under constant voltage conditions is electronic, but if the voltage is increased, then ionic current begins to flow again with further film formation until a new equilibrium is established. However, it is not possible to increase the voltage to a very high value. The upper limit on voltage lies between 500 and 700 V due to breakdown and arcing in the barrier layer. The most interesting fact is that the thickness of the barrier type film is not affected by electrolyzing time, surface roughness, and temperature of the electrolyte. In fact, the formed oxide film will exactly follow or slightly smooth out the initial surface topography of the anodized metal.

The anodization ratio of tantalum anodized in 1 mM citric acid (CA) has been reported in the literature [74–76] and usually is between 1.8 and 2.2 nm/V. **Table 5** compares the information relating to the anodization of metals and in particular anodization of tantalum in the recent works [68, 78–80].


#### **Table 5.**

TFTs, and OFETs. One of the most reliable and straightforward ways to form tantalum oxide is electrochemical oxidation (so-called anodization). Several metals such as Al, Ti, and Ta have very high chemical affinity with oxygen. Therefore, under ambient conditions, they will rapidly react with this gas forming a "native oxide" on their surfaces. The "air-formed" oxide film protects the metals from further oxidation (i.e. oxidation of the metal bulk) but is extremely thin—its thickness varies from a few angstroms to circa 2 nm, and it is very often not homogenous in thickness and can contain numerous defects and flaws. For example, the native oxide layer of tantalum has been reported to be usually around 3–4 nm [75]. As a result, the native oxide cannot be used as a protective film for preventing corrosion

Anodization is an electrochemical process, which allows improving this natural

oxide film and produces stable oxide films with negligible reactivity. **Figure 8** shows a typical anodization bath to perform the oxidation. During the process, the metal to be oxidized is made the anode. An electrolytic cell is filled with an electrolyte. It has been shown previously that the nature of the electrolyte determines the type of anodic oxide film. The electric circuit is completed with a counter electrode which is made of a chemically inert metal (e.g. Au, Pt) or alloy (e.g. stainless steel).

or as an insulator in capacitors and transistors.

**Figure 7.**

**Figure 8.**

**102**

*Schematic of the anodization process.*

*Schematic of the spin-coating process.*

*Integrated Circuits/Microchips*

In **Figure 8**, an Au plate is shown as the cathode.

*A summary of anodization ratios and forming electrolytes relating to the anodization of Al2O3, TiO2 and Ta2O5.*
