**6.5 Passivation**

*Integrated Circuits/Microchips*

**6.2 Device isolation**

and pad oxide layers are etched.

feature size and annealed to form the polysilicon gate.

**6.3 Transistor making**

away (**Figure 5(xxi)**).

**6.4 Interconnection**

performed to form the well (**Figure 5(iii)**). The wafer subsequently undergoes annealing and drive-in processes to, respectively, repair the lattice damage caused

Next, shallow trench isolation STI is employed to isolate neighboring devices. Initially, pad oxide is grown via dry oxidation (**Figure 5(iv)**). Chemical vapor deposition CVD technique is then applied to deposit a layer of silicon nitride Si3N4 onto the oxide surface (**Figure 5(v)**). Pad oxide acts as a stress buffer to avoid cracks on the nitride film, whereas nitride film acts as a mask for silicon etching. A layer of photoresist is subsequently deposited onto the nitride layer (**Figure 5(vi)**). Lithography is performed to develop patterns on the photoresist (**Figure 5(vii)**). The nitride film and pad oxide are etched in accordance with the pattern formed at the photoresist (**Figure 5(viii)**and **(ix)**). The area protected under the nitride mask is known as the active region. As soon as the photoresist is stripped (**Figure 5(x)**), the substrate undergoes reactive ion etching (RIE) to form trenches (**Figure 5(xi)**). A thin layer of barrier oxide is grown in the trenches so as to block impurities from diffusing into the substrate during the CVD process. The trenches are then filled with oxide via the CVD process (**Figure 5(xii)**). The oxide at the surface of the substrate is removed using the chemical mechanical polishing (CMP) technique (**Figure 5(xiii)**). The STI is completed after annealing is performed, and the nitride

A thin layer of gate oxide is applied via dry oxidation (**Figure 5(xiv)**). Threshold voltage VTH adjust implantation is subsequently performed. This is then followed by thermal annealing to repair the lattice damage at the substrate surface. A layer of polysilicon is deposited onto the substrate surface after the annealing process (**Figure 5(xv)**). The polysilicon is then etched according to the dimension of the

Once the gate is formed, LDD is implanted to suppress hot electron effect in deep submicron MOSFETs (**Figure 5(xvii)**). The CVD process is applied to deposit a layer of silicon nitride Si3N4 onto the surface of the substrate (**Figure 5 (xviii)**). The nitride film is etched to form sidewall spacers at both sides of the gate (**Figure 5 (xix)**). The source/drain dopant is then implanted into the substrate. The substrate subsequently undergoes annealing after the implantation process (**Figure 5(xx)**). This is then followed by the removal of the thin oxide layer. A layer of titanium or cobalt is then deposited onto the surface. Rapid thermal annealing (RTA) is employed to form the self-aligned silicide layers on the gate and source/drain surfaces. At the final stage of the transistor fabrication process, the unreacted titanium or cobalt layer is etched

Once the arrays of transistors are fabricated, metallization is required to interconnect the transistors so as to form electrical circuitries. In the interconnection stage, a layer of premetal dielectric (PMD) is first formed by depositing a layer of borophosphosilicate glass BPSG onto the substrate surface (**Figure 5(xxii)**). The PMD acts as the first layer of insulator for multilevel interconnection. After the die is annealed, the BPSG is etched to form source/drain contacts (**Figure 5(xxiii)**). Metallization is applied by depositing and etching aluminum (Al) on the contacts

by the high-energy ion bombardment and to activate the dopant.

**12**

The passivation layer is the final dielectric layer deposited onto the die after the last metal interconnection is formed. Silicon nitride is usually used as the passivation layer.
