**Author details**

**Figure 18(a)** demonstrates the measured eye diagrams with 1.5 mApp 215-1 PRBS inputs at different data rates of 25 Gb/s and 32 Gb/s, respectively. It is clearly seen that the output voltage levels of larger than 210 mVpp were measured with 50-Ω loads with the input currents of 1.5 mApp. The differential voltage swings of the MC-TIA were measured to be 236 mVpp and 224 mVpp (with less than 5.1% mismatch) at 25-Gb/s operations and 211 mVpp and 198 mVpp (with less than 6.2% mismatch) for 32-Gb/s operations. For both cases, delay mismatch at the differential outputs were measured to be less than 2 ps. **Figure 18(b)** demonstrates the measured eye diagrams with 100 μApp 215-1 PRBS inputs, where the voltage swings of 7.91 mVpp and 8.23 mVpp (with less than 4% mismatch) were achieved for differential outputs at 32-Gb/s operations. Even in this case, delay mismatch at the

**Parameters [24] [34] [33] [32] [30] This work** CMOS [nm] 45 SOI 65 65 65 65 **65**

> RGC (single)

RGC+PA (single)

20.47 12.5 30 17.77 22.42 **19.8**

DMF (diff.)

**MC (diff.)**

SF (single)

VDD [V] 1.0 1.6/2.2 1.2 1.0/3.3 1.2 **1.2** BW [GHz] 30 40 21.6 21.4 50 **40** PD cap. [fF] 60 40 200 N/A 50 **50** TZ gain [dBΩ] 55 55 46.7 76.8 52 **54**

GD variation [ps] 3.9 32 N/A N/A N/A **10** Power dissip. [mW] 9 122 39.9 137.5 49.2 **55.2**

*\*INV, inverter; SF, source follower; RGC, regulated cascode; PA, post amplifier; DMF, dual-mode feedforward; single, single-*

*Bold:* **Table 3** *summarizes the performance of the MC-TIA with the previously reported CMOS TIAs, showing a low-noise*

] 0.29 0.54 0.56 0.32 0.96 **0.6**

(single)

Architecture INV

*ended; diff., differential; PD cap., photodiode capacitance.*

*low-power fully differential solution for 100-GbE applications.*

*Performance comparison with previously reported CMOS TIAs.*

Noise current spectral density

*Integrated Circuits/Microchips*

[pA/√Hz]

Chip size [mm<sup>2</sup>

**Table 3.**

**Table 3** summarizes the performance of the MC-TIA with the previously

We have demonstrated a number of CMOS integrated circuits for various optical applications, which included 4-channel 10-Gb/s/ch Tx and Rx array chipsets for HDMI active optical cables, 16-channel TIA array chip for 0.5–25 m range detection LiDAR, and 40-GHz TIA chip for 100 GbE. Even with advanced nano-CMOS technologies, we have proposed and exploited several novel circuit techniques for

feedforward and asymmetric preemphasis for high speed, double-gain feedforward for high gain, selectable equalizer for specific bandwidth, mirrored-cascode for fully differential topology, etc. We believe that the continuous introduction of novel circuit techniques is very crucial and necessary to develop low-cost CMOS ICs

their optimum performance, such as input data detection for low power,

differential outputs was measured to be less than 2 ps.

reported CMOS TIAs.

for various optical applications.

**3. Conclusions**

**146**

Sung Min Park Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, Republic of Korea

\*Address all correspondence to: smpark@ewha.ac.kr

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
