**4. Evaluation**

In this section, the various proposals in the literature are evaluated using the same SOT-MTJ technology in [13] on both cell and system level perspectives. The cell level analyses are done based on a 2 2 memory array. The simulations run over Cadence Virtuoso and using the SOT-MTJ Verilog-A model demonstrated in [25] and the parameters in **Table 1**. The system-level analyses are done using the non-volatile memory simulator, known as NVSim [26]. NVSim estimates the overall memory performance, power consumption, energy, and area based on the given memory cell parameters.

