**Author details**

The selected parameters of the proposed VGA, voltage comparator, and charge pump are depicted in **Figure 19**. The graphs contain the measured and simulated

*Measured and simulated parameters of the proposed circuit topologies on the prototype chip. (a) VGA*

*frequency response, (b) Comparator transfer characteristics, (c) Charge-Pump efficiency.*

The comparison of simulated and measured data of frequency response of the proposed VGA is depicted in **Figure 19(a)**. We used the Monte-Carlo analysis results to obtain the borders of the expected gain range. As one can observe, the measured frequency response remains between the borders specified by the simulation and deviates only slightly from the Monte-Carlo mean curve. The measurement and simulation conditions were identical, the load capacitance of 10 pF, the control voltage *VCTRL* = 0.1 V, ambient room temperature, and power supply voltage of *VDD* = 0.6 V were used. The obtained measured results at these operating conditions were the following. The voltage gain of *aV* = 30 dB, gain-bandwidth of GBW = 1.2 MHz and bandwidth of *f*<sup>3</sup>*dB* = 40 kHz were observed. The worst-case discrepancy of the measured low-frequency gain compared to the mean Monte-

The transfer characteristics of the proposed rail-to-rail comparator are depicted in **Figure 19(b)**. The simulated results correlate very well with measured curves for all input voltage conditions. In our experiments, the comparator exhibited correct function for all four levels of hysteresis and the rail-to-rail operation has been confirmed by setting the reference voltage only 3 mV from the power supply range. This test can be considered quite strict, since it would also reveal issues with the input offset voltage. Monte-Carlo simulations performed on 3000 samples in corner and ambient temperatures resulted in the mean value of input offset *Voffset* = 592 uV with standard deviation of *σ* = 1.91 mV [15]. Furthermore, the power consumption at *VDD* = 0.4 V has been measured in the upper half of nW range including the ESD structures leakage, PCB, and oscilloscope probe parasitics. However, we have also observed correct operation with *VDD* = 0.25 V, which indeed astonishing result. **Figure 19(c)** shows dependence of the efficiency on the output current. This is the example where the comparison of different charge pumps based on GD and BD cross-coupled inverter were compared. The best efficiency for the given parameters can be observed for the output current of 1*μA*, where the BD cross-coupled charge pump achieves the efficiency of 80% in four-stage architecture (N = 4) in given

Considering the current onset of ultra-low-voltage and ultra-low-power operation requirements for today's CMOS analog/mixed-signal ICs and their fabrication,

results for direct comparison and evaluation.

**Figure 19.**

*Integrated Circuits/Microchips*

Carlo curve is approximately 5.85 dB.

CMOS technology.

**4. Conclusions**

**40**

Daniel Arbet†, Lukas Nagy† and Viera Stopjakova\*† Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Bratislava, Slovakia

\*Address all correspondence to: viera.stopjakova@stuba.sk

† These authors contributed equally.

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
