**6. Microchip fabrication**

To fabricate the chip, the layout is sent to a fab or a foundry. In a fab, a singlecrystal semiconductor ingot is first grown. Wafers are then sliced from the ingot. The layout is printed onto the dice in each wafer.

The fabrication process for NMOS and PMOS transistors is similar. The main differences lie within the types and density of dopants applied to the substrate specifically in the formation of well, threshold voltage VTH adjust implantation, LDD implantation, source/drain implantation, etc. The process flow of fabricating a planar MOSFET is summarized in the following sections, and it is also graphically depicted in **Figure 5**. The process of chip fabrication can be broadly separated into five stages, i.e. (i) well formation, (ii) device isolation, (iii) transistor making, (iv) interconnection and (v) passivation [15].

#### **6.1 Well formation**

Initially, a p-type single-crystal silicon wafer is prepared (**Figure 5(i)**). In order to form a P (for NMOS) or N (for PMOS) well, screen oxide is first grown on the surface of the substrate (**Figure 5(ii)**). A high-energy ion implantation is then

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**Figure 5.**

*The fabrication process of a MOSFET.*

*Introductory Chapter: Integrated Circuit Chip DOI: http://dx.doi.org/10.5772/intechopen.92818* *Introductory Chapter: Integrated Circuit Chip DOI: http://dx.doi.org/10.5772/intechopen.92818*

*Integrated Circuits/Microchips*

**5.2 Logic circuit representation**

*The (a) basic structure and (b) cross section of a FinFET.*

**Figure 4.**

**5.3 Layout representation**

**6. Microchip fabrication**

**6.1 Well formation**

Once the HDL codes are successfully simulated, functional blocks from standard cell libraries are used to synthesize the behavioral representation of the design into logic circuit representation. Once the design is verified, the gate-level netlist is generated. The netlist consists of important information of the circuit such as the connectivity and nodes and is necessary in order to develop the layout of the design.

The physical layout of the design is created at the final stage. The process starts with floor planning which defines the core and routing areas of the chip. In order to optimize the design, the building blocks are usually adjusted and orientated by IC designers. This process is known as placement. Once this is completed, a routing

To fabricate the chip, the layout is sent to a fab or a foundry. In a fab, a singlecrystal semiconductor ingot is first grown. Wafers are then sliced from the ingot.

The fabrication process for NMOS and PMOS transistors is similar. The main differences lie within the types and density of dopants applied to the substrate specifically in the formation of well, threshold voltage VTH adjust implantation, LDD implantation, source/drain implantation, etc. The process flow of fabricating a planar MOSFET is summarized in the following sections, and it is also graphically depicted in **Figure 5**. The process of chip fabrication can be broadly separated into five stages, i.e. (i) well formation, (ii) device isolation, (iii) transistor making,

Initially, a p-type single-crystal silicon wafer is prepared (**Figure 5(i)**). In order to form a P (for NMOS) or N (for PMOS) well, screen oxide is first grown on the surface of the substrate (**Figure 5(ii)**). A high-energy ion implantation is then

process is performed to interconnect the building blocks.

The layout is printed onto the dice in each wafer.

(iv) interconnection and (v) passivation [15].

**10**

**Figure 5.** *The fabrication process of a MOSFET.*

performed to form the well (**Figure 5(iii)**). The wafer subsequently undergoes annealing and drive-in processes to, respectively, repair the lattice damage caused by the high-energy ion bombardment and to activate the dopant.

#### **6.2 Device isolation**

Next, shallow trench isolation STI is employed to isolate neighboring devices. Initially, pad oxide is grown via dry oxidation (**Figure 5(iv)**). Chemical vapor deposition CVD technique is then applied to deposit a layer of silicon nitride Si3N4 onto the oxide surface (**Figure 5(v)**). Pad oxide acts as a stress buffer to avoid cracks on the nitride film, whereas nitride film acts as a mask for silicon etching. A layer of photoresist is subsequently deposited onto the nitride layer (**Figure 5(vi)**). Lithography is performed to develop patterns on the photoresist (**Figure 5(vii)**). The nitride film and pad oxide are etched in accordance with the pattern formed at the photoresist (**Figure 5(viii)**and **(ix)**). The area protected under the nitride mask is known as the active region. As soon as the photoresist is stripped (**Figure 5(x)**), the substrate undergoes reactive ion etching (RIE) to form trenches (**Figure 5(xi)**). A thin layer of barrier oxide is grown in the trenches so as to block impurities from diffusing into the substrate during the CVD process. The trenches are then filled with oxide via the CVD process (**Figure 5(xii)**). The oxide at the surface of the substrate is removed using the chemical mechanical polishing (CMP) technique (**Figure 5(xiii)**). The STI is completed after annealing is performed, and the nitride and pad oxide layers are etched.

#### **6.3 Transistor making**

A thin layer of gate oxide is applied via dry oxidation (**Figure 5(xiv)**). Threshold voltage VTH adjust implantation is subsequently performed. This is then followed by thermal annealing to repair the lattice damage at the substrate surface. A layer of polysilicon is deposited onto the substrate surface after the annealing process (**Figure 5(xv)**). The polysilicon is then etched according to the dimension of the feature size and annealed to form the polysilicon gate.

Once the gate is formed, LDD is implanted to suppress hot electron effect in deep submicron MOSFETs (**Figure 5(xvii)**). The CVD process is applied to deposit a layer of silicon nitride Si3N4 onto the surface of the substrate (**Figure 5 (xviii)**). The nitride film is etched to form sidewall spacers at both sides of the gate (**Figure 5 (xix)**). The source/drain dopant is then implanted into the substrate. The substrate subsequently undergoes annealing after the implantation process (**Figure 5(xx)**). This is then followed by the removal of the thin oxide layer. A layer of titanium or cobalt is then deposited onto the surface. Rapid thermal annealing (RTA) is employed to form the self-aligned silicide layers on the gate and source/drain surfaces. At the final stage of the transistor fabrication process, the unreacted titanium or cobalt layer is etched away (**Figure 5(xxi)**).

#### **6.4 Interconnection**

Once the arrays of transistors are fabricated, metallization is required to interconnect the transistors so as to form electrical circuitries. In the interconnection stage, a layer of premetal dielectric (PMD) is first formed by depositing a layer of borophosphosilicate glass BPSG onto the substrate surface (**Figure 5(xxii)**). The PMD acts as the first layer of insulator for multilevel interconnection. After the die is annealed, the BPSG is etched to form source/drain contacts (**Figure 5(xxiii)**). Metallization is applied by depositing and etching aluminum (Al) on the contacts

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**Author details**

\*, Muammar Mohamad Isa<sup>2</sup>

\*Address all correspondence to: yeapkh@utar.edu.my

provided the original work is properly cited.

1 Universiti Tunku Abdul Rahman, Jalan Universiti, Kampar, Perak, Malaysia

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

2 Universiti Malaysia Perlis, Jalan Wang Ulu Arau, Kangar, Perlis, Malaysia

and Siu Hong Loh1

Kim Ho Yeap1

*Introductory Chapter: Integrated Circuit Chip DOI: http://dx.doi.org/10.5772/intechopen.92818*

once the packaging process is completed.

**6.5 Passivation**

ation layer.

**7. Packaging**

ally used to interconnect different levels of metal layers.

(**Figure 5(xxiv)**). Phosphosilicate glass PSG is used as the insulator material for the subsequent levels of metal interconnections. The insulator layers after PMD is known as the intermetal dielectric (IMD) layers. Vials filled with tungsten are usu-

The passivation layer is the final dielectric layer deposited onto the die after the last metal interconnection is formed. Silicon nitride is usually used as the passiv-

To protect the chip from harsh external environment (e.g. being exposed to UV light or moisture or being scratched), it is essential to encapsulate the chip in a ceramic or plastic package—a process known as packaging. The three most commonly used packaging techniques are (i) wire bonding, (ii) flip chip and (iii) tape-automated bonding (TAB) [10]. IC packaging marks the end of the entire chip manufacturing process. The chip is therefore ready to be released to the market,

(**Figure 5(xxiv)**). Phosphosilicate glass PSG is used as the insulator material for the subsequent levels of metal interconnections. The insulator layers after PMD is known as the intermetal dielectric (IMD) layers. Vials filled with tungsten are usually used to interconnect different levels of metal layers.
