**4.1 Cell-level evaluation**

diode's *R*load, which further decreases the required *V*Read, as shown in **Figure 6(b)**. Hence, the two factors that affect the required *V*Read (i.e. diode area and *R*load) are improved in this design compared to the MBC-DD and SLC diode-based SOT-MRAM designs. Hence, the smaller required *V*Read may permit the MLC-SD design to achieve smaller read energy consumption. Furthermore, MLC-SD cell requires employing two MTJs with different *R*<sup>P</sup> and *R*AP values as it is an MLC. Assuming that both the MTJs use the same materials, different MTJ resistances are achieved by varying either the MTJ dimensions (i.e. *W*MTJ and *L*MTJ), the dielectric thickness (*tox*), or combination of both [24]. It is essential to have a large minimum resistance difference (Δ*R*min) between the distinct in-parallel equivalent resistance states to increase the distinguishability and read speed. However, the MLC would mainly have smaller Δ*R*min compared to the SLC, which in-return may result in reduced reading speed and would be a competing factor with the reduced *V*Read to decide the

In this section, the various proposals in the literature are evaluated using the same SOT-MTJ technology in [13] on both cell and system level perspectives. The cell level analyses are done based on a 2 2 memory array. The simulations run over Cadence Virtuoso and using the SOT-MTJ Verilog-A model demonstrated in [25] and the parameters in **Table 1**. The system-level analyses are done using the non-volatile memory simulator, known as NVSim [26]. NVSim estimates the overall memory performance, power consumption, energy, and area based on the given

**Symbol Parameter Value**

*t*FL Free layer thickness (nm) 1.5 *K*u*V*/KT Thermal stability 46 *t*ox Tunnel barrier thickness (nm) 1.8

*R*AP MTJ high resistance value (kΩ) 15 TMR Tunnel magneto-resistance ratio (%) 114 *α* Gilbert damping 0.012 *ρ*HM Heavy metal (*W*) resistivity (μΩcm) 200

*t*HM Heavy metal thickness (nm) 3

*θ*SHE Spin hall angle 0.3 *P* Spin polarization 0.6

*<sup>Ђ</sup>* Reduced Planck constant (J s) 1.054 1034

*The parameters follow the experimental data of the SOT-MTJ in [13] and are explained in [11].*

) 50 100

) 1114

) 115 150

) 7

) 1.76 <sup>10</sup><sup>11</sup>

*<sup>W</sup>*MTJ *<sup>L</sup>*MTJ MTJ dimensions (*<sup>W</sup> <sup>L</sup>*) (nm<sup>2</sup>

*M*<sup>s</sup> Magnetization saturation (emu/cm<sup>3</sup>

*<sup>W</sup>*HM *<sup>L</sup>*HM HM dimensions (*<sup>W</sup> <sup>L</sup>*) (nm<sup>2</sup>

*<sup>J</sup>*co Critical current density (<sup>10</sup><sup>10</sup> A/m2

*γ* Gyromagnetic ratio (rad s<sup>1</sup> T<sup>1</sup>

read energy efficiency of this cell compared to the SLC proposals.

**4. Evaluation**

*Integrated Circuits/Microchips*

memory cell parameters.

**Table 1.**

**162**

*SOT-MTJ device parameters.*

**Table 2** presents a comparison between the different MRAM designs. In terms of area, MBC-DD and MLC-SD SOT-MRAM do offer the smallest 2-bit cell area among the various designs, which are estimated to be 36*F*<sup>2</sup> and 34.5*F*<sup>2</sup> , respectively, based on the rules in [16]. This is at least double the density compared to other MRAMs and achieves 75% smaller 1-bit effective area compared to conventional SOT-MRAM. From energy perspective, these designs consume at least 36% less energy compared with designs utilizing STT writing (S-MLC), due to the high energy efficiency of SOT writing. Unlike P-MLC and MLC-SD SOT-MRAM, MBC-DD has no write current leakage through the MTJ from the HM during write mode as the diodes are reverse-biased, which also leads to better energy efficiency. However, the significant area reduction for both MBC-DD and MLC-SD SOT-MRAMs comes with additional energy penalty in both worst-case write operation (i.e. writing non-identical bits) and read operation. The additional energy consumption in the worst-case write operation of non-identical bits is because of the enforced rule of using two MTJs per cell with different *I*c. For instance, writing two different bits ('10' or '01') in MBC-DD and MLC-SD consume higher energy (0.88 pJ with 10.5 ns delay) compared to writing two SLC SOT-MRAM (0.76 pJ). However, to write identical bits ('00' or '11') on the MBC-DD and MLC-SD cells require only a single write pulse, which leads to better energy efficiency than SLC SOT-MRAM. This is because programming two identical bits in the SLC SOT-MRAM always requires two write pulses. Thus, if equal probability of programming '00', '01', '10', and '11' is assumed, MBC-DD and MLC-SD designs may result in similar average energy efficiency to two bits of SLC SOT-MRAM, as shown in **Table 2**. Moreover, the


*a Energy and delay are the average of writing the data '00', '01', '10', '11'. <sup>b</sup>*

*<sup>Δ</sup>*R*min is* <sup>R</sup>*AP* <sup>R</sup>*<sup>P</sup> for SLC, while it is the minimum resistance difference among the four different states in MLC. <sup>c</sup> Area estimated based on standard design rules reported in [16].*

*d* F *is the minimum feature size of the employed technology (i.e. In 32 nm technology,* F *= 32 nm).*

#### **Table 2.**

*Comparison of various MRAM technologies.*

energy penalty for non-identical bits writing can be also minimized as discussed before. In terms of reading, MBC-DD maintains similar distinguishability to conventional SLC, as indicated by the Δ*R*min values in **Table 2**, because each of the two MTJs is sensed separately. This is unlike the P-MLC, S-MLC, and MLC-SD structures that have a reduced Δ*R*min as a result of relying on an MLC approach. However, to ensure sufficient diode drive current within the D-MTJs, a larger read voltage is needed compared to cells with read transistors, which does increase the read energy consumption compared to conventional SLC SOT-MRAM.

To clarify the pros and cons of the various memory technologies, three different memory capacities are considered, which are 256 KB, 1 MB, and 8 MB. **Figure 9** depicts the total leakage power consumption for the various designs with three different capacities. The volatile SRAM technology does consume significant leakage power, which increases by order of magnitudes for larger memory capacities. On the other hand, the nonvolatility of the MRAM designs results in relatively negligible leakage among the various capacities. This demonstrates the advantage of significant power consumption reduction by employing the nonvolatile MRAM designs as a replacement of the volatile SRAM, especially in battery-powered

From area perspective, **Figure 10** shows the comparison between the various memory technologies, estimated by NVSim, while being used as cache memory. **Figure 10(a)** reports the different MRAM designs relative to the overall SRAM memory area for the three different capacities. The figure indicates the significant reduction in the overall area by employing the various MRAM technologies in comparison to SRAM, which consumes at least 50% smaller silicon area. Furthermore, the area saving percentage increases noticeably for larger memory capacities. This is because for larger memory capacity, the impact of the cell area overtakes the impact of the periphery. The periphery area for MRAM consumes larger area than the periphery area of the SRAM due to the need for relatively larger write currents, whereas the cell area of the MRAM is much smaller than the SRAM cell area [29]. Hence, at larger capacities, the MRAMs that have significantly smaller cell area compared to SRAM would consume much lower overall silicon area. For instance, the area saving for the MBC-DD and MLC-SD cells, which are the cells with smallest footprints, can reach up to 90% smaller area

The impact of the smaller cell area is also clear while comparing the various MRAM technologies, as presented in **Figure 10(b)**. The smaller 1-bit effective area of S-MLC, SLC diode-based, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs by 28, 50, 50, 75, and 74% compared to the conventional SOT-MRAM results in similar overall memory silicon area reduction. In particular, for larger memory capacity (e.g. 8 MB), where the impact of the cell area is more significant, the overall memory silicon area of the various designs in the literature relative to conventional SOT-MRAM design shows approximately equal area reduction as the 1-bit effective area reduction. Moreover, the smaller silicon area consumption of the various proposed designs in the literature compared to SRAM and conventional SOT-MRAM with equivalent capacity permits realizing the cache memory using these cells with higher capacity under the iso-area assumption. For instance, 2 MB

*Total leakage power consumption of SRAM, STT-MRAM, conventional, SLC DSOT-MRAM, S-MLC,*

*P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for various memory capacities.*

compared to SRAM for large cache memory size, such as 8 MB size.

mobile devices that demand long idle durations.

*Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory*

*DOI: http://dx.doi.org/10.5772/intechopen.92120*

**Figure 9.**

**165**

The diode-based SLC SOT-MRAM design [14] does offer the advantage of maintaining a similar write energy efficiency compared to the conventional SOT-MRAM (i.e. baseline from write energy perspective). Moreover, it offers 50% 1-bit effective area savings compared to conventional SOT-MRAM, which is on level with P-MLC and S-MLC designs with the advantage of maintaining an SLC sensing approach. However, diode-based SLC SOT-MRAM still consumes double the area compared to the MBC-DD and MLC-SD designs, while it still also suffers from the energy and fabrication complexity penalty of employing a diode.

Similar to diode-based SLC SOT-MRAM, P-MLC design offers 50% 1-bit effective area savings compared to conventional SOT-MRAM, whereas S-MLC does offer only 28% savings as the transistor size needs to increase to supply the required STT current through the high resistance MTJ stack. On the other hand, both P-MLC and S-MLC do not employ a diode, which may aid in reducing the read energy and avoiding the fabrication process issues related to incorporating a diode. However, they suffer from other drawbacks that increase both energy consumption and fabrication complexity. In particular from energy perspective, S-MLC consumes high energy due to using STT technology in writing one of the two MTJs per cell, whereas P-MLC shares the additional write energy penalty issue in writing nonidentical bits per cell with MBC-DD and MLC-SD designs. In addition, both of the designs rely on the MLC sensing approach, which harms the sensing speed and distinguishability as reflected by the reduced Δ*R*min values.

Overall, if a figure-of-merit (FOM) is defined as the product of the area, read and write energy products [27], MBC-DD SOT-MRAM may outperform other designs by at least 34%, thanks to its significant area reduction and maintaining the SLC sensing approach.

#### **4.2 System-level evaluation**

As aforementioned, NVSim [26] is used to evaluate the various SOT-MRAM cells from a system-level perspective. NVSim does consider the different write/read peripherals, array organization, and routing network required in the overall memory architecture. NVSim supports various nonvolatile memories such as STT-MRAM, PCRAM, and ReRam in addition to the well-known volatile memories such as SRAM and DRAM. NVSim can be tuned to support SOT-MRAM as well. In this study, the comparison is based on the utilization of the various nonvolatile MRAM cells as cache memory and they are mainly compared to the current widely used technology as cache memory, which is the SRAM. SRAM does offer high performance; however, currently, it suffers from a significant increase in the 1-bit area and the leakage power consumption [28]. Thus, the utilization of an area-efficient, high-speed and nonvolatile SOT-MRAM would be a promising solution to replace the existing SRAM technology, especially in higher-level caches. The considered cache has 4-way set associativity and 64 Byte line size and is optimized to achieve the smallest overall silicon area. The 32 nm technology node is assumed for the various designs, in which the SRAM cell area is 170F<sup>2</sup> [28], and the same cell parameters for the various MRAM technologies are maintained as stated above.

energy penalty for non-identical bits writing can be also minimized as discussed before. In terms of reading, MBC-DD maintains similar distinguishability to conventional SLC, as indicated by the Δ*R*min values in **Table 2**, because each of the two

The diode-based SLC SOT-MRAM design [14] does offer the advantage of maintaining a similar write energy efficiency compared to the conventional SOT-MRAM (i.e. baseline from write energy perspective). Moreover, it offers 50% 1-bit effective area savings compared to conventional SOT-MRAM, which is on level with P-MLC and S-MLC designs with the advantage of maintaining an SLC sensing approach. However, diode-based SLC SOT-MRAM still consumes double the area compared to the MBC-DD and MLC-SD designs, while it still also suffers from the

Similar to diode-based SLC SOT-MRAM, P-MLC design offers 50% 1-bit effective area savings compared to conventional SOT-MRAM, whereas S-MLC does offer only 28% savings as the transistor size needs to increase to supply the required STT current through the high resistance MTJ stack. On the other hand, both P-MLC and S-MLC do not employ a diode, which may aid in reducing the read energy and avoiding the fabrication process issues related to incorporating a diode. However, they suffer from other drawbacks that increase both energy consumption and fabrication complexity. In particular from energy perspective, S-MLC consumes high energy due to using STT technology in writing one of the two MTJs per cell, whereas P-MLC shares the additional write energy penalty issue in writing nonidentical bits per cell with MBC-DD and MLC-SD designs. In addition, both of the designs rely on the MLC sensing approach, which harms the sensing speed and

Overall, if a figure-of-merit (FOM) is defined as the product of the area, read and write energy products [27], MBC-DD SOT-MRAM may outperform other designs by at least 34%, thanks to its significant area reduction and maintaining the

As aforementioned, NVSim [26] is used to evaluate the various SOT-MRAM cells from a system-level perspective. NVSim does consider the different write/read peripherals, array organization, and routing network required in the overall memory architecture. NVSim supports various nonvolatile memories such as STT-MRAM, PCRAM, and ReRam in addition to the well-known volatile memories such as SRAM and DRAM. NVSim can be tuned to support SOT-MRAM as well. In this study, the comparison is based on the utilization of the various nonvolatile MRAM cells as cache memory and they are mainly compared to the current widely used technology as cache memory, which is the SRAM. SRAM does offer high performance; however, currently, it suffers from a significant increase in the 1-bit area and the leakage power consumption [28]. Thus, the utilization of an area-efficient, high-speed and nonvolatile SOT-MRAM would be a promising solution to replace the existing SRAM technology, especially in higher-level caches. The considered cache has 4-way set associativity and 64 Byte line size and is optimized to achieve the smallest overall silicon area. The 32 nm technology node is assumed for the various designs, in which the SRAM cell area is 170F<sup>2</sup> [28], and the same cell parameters for the various MRAM technologies are maintained as stated above.

MTJs is sensed separately. This is unlike the P-MLC, S-MLC, and MLC-SD structures that have a reduced Δ*R*min as a result of relying on an MLC approach. However, to ensure sufficient diode drive current within the D-MTJs, a larger read voltage is needed compared to cells with read transistors, which does increase the

read energy consumption compared to conventional SLC SOT-MRAM.

energy and fabrication complexity penalty of employing a diode.

distinguishability as reflected by the reduced Δ*R*min values.

SLC sensing approach.

*Integrated Circuits/Microchips*

**164**

**4.2 System-level evaluation**

To clarify the pros and cons of the various memory technologies, three different memory capacities are considered, which are 256 KB, 1 MB, and 8 MB. **Figure 9** depicts the total leakage power consumption for the various designs with three different capacities. The volatile SRAM technology does consume significant leakage power, which increases by order of magnitudes for larger memory capacities. On the other hand, the nonvolatility of the MRAM designs results in relatively negligible leakage among the various capacities. This demonstrates the advantage of significant power consumption reduction by employing the nonvolatile MRAM designs as a replacement of the volatile SRAM, especially in battery-powered mobile devices that demand long idle durations.

From area perspective, **Figure 10** shows the comparison between the various memory technologies, estimated by NVSim, while being used as cache memory. **Figure 10(a)** reports the different MRAM designs relative to the overall SRAM memory area for the three different capacities. The figure indicates the significant reduction in the overall area by employing the various MRAM technologies in comparison to SRAM, which consumes at least 50% smaller silicon area. Furthermore, the area saving percentage increases noticeably for larger memory capacities. This is because for larger memory capacity, the impact of the cell area overtakes the impact of the periphery. The periphery area for MRAM consumes larger area than the periphery area of the SRAM due to the need for relatively larger write currents, whereas the cell area of the MRAM is much smaller than the SRAM cell area [29]. Hence, at larger capacities, the MRAMs that have significantly smaller cell area compared to SRAM would consume much lower overall silicon area. For instance, the area saving for the MBC-DD and MLC-SD cells, which are the cells with smallest footprints, can reach up to 90% smaller area compared to SRAM for large cache memory size, such as 8 MB size.

The impact of the smaller cell area is also clear while comparing the various MRAM technologies, as presented in **Figure 10(b)**. The smaller 1-bit effective area of S-MLC, SLC diode-based, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs by 28, 50, 50, 75, and 74% compared to the conventional SOT-MRAM results in similar overall memory silicon area reduction. In particular, for larger memory capacity (e.g. 8 MB), where the impact of the cell area is more significant, the overall memory silicon area of the various designs in the literature relative to conventional SOT-MRAM design shows approximately equal area reduction as the 1-bit effective area reduction. Moreover, the smaller silicon area consumption of the various proposed designs in the literature compared to SRAM and conventional SOT-MRAM with equivalent capacity permits realizing the cache memory using these cells with higher capacity under the iso-area assumption. For instance, 2 MB

#### **Figure 9.**

*Total leakage power consumption of SRAM, STT-MRAM, conventional, SLC DSOT-MRAM, S-MLC, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for various memory capacities.*

**Figure 10.**

*Area comparison of the STT-MRAM, conventional, SLC diode-based, S-MLC, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for different capacity relative to (a) SRAM and (b) conventional SOT-MRAM.*

**Figure 11.**

**Figure 12.**

**167**

*(e.g. type-x reported in [13]).*

*Comparison of the SRAM, STT-MRAM, conventional, SLC diode-based, S-MLC, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for different capacities relative to SRAM from (a) cache hit/miss energy per access*

*Cache write dynamic energy per access comparison of the SRAM, conventional, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for different capacity relative to SRAM assuming improved high-speed SOT-MTJ technology*

*perspective and (b) cache write dynamic energy per access perspective.*

*Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory*

*DOI: http://dx.doi.org/10.5772/intechopen.92120*

capacity of conventional SOT-MRAM consumes similar silicon area to an 8 MB capacity of MBC-DD SOT-MRAM. Higher memory capacity results in higher performance metrics, such as instruction per cycle (IPC) and energy efficiency due to reduced access counts for the off-chip memory [30].

From energy and performance perspective, SRAM can have higher hit/miss performance and energy efficiency compared to the various SOT-MRAM proposals at small memory capacity (e.g. 256 KB), as depicted by **Figure 11(a)**. This is because the impact of the large load capacitance of the SRAM cell would be minimal at these capacities [29]. However, for large memory capacity, the much higher load capacitance, parasitic, and routing complexity of the six transistors SRAM cell (as SRAM consume significantly larger silicon area compared to SOT-MRAM) causes the MRAM proposals to achieve better hit/miss performance and energy efficiency. On the contrary, the write energy for the various MRAM proposals is larger than that of the SRAM for the various memories capacity, as shown in **Figure 11(b)**. This is attributed to the larger write current requirement for the MRAM-based technologies relative to the SRAM technology. However, with improved SOT-MRAM technology such as the type-x SOT-MTJ [13] (achieves sub ns switching with write current of 100 μA), or the presented high-performance SOT-MRAM by IMEC [12] that achieves successful switching in 100's of ps range, the write energy can be reduced significantly, as illustrated in **Figure 12**. This makes the various

*Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory DOI: http://dx.doi.org/10.5772/intechopen.92120*

#### **Figure 11.**

capacity of conventional SOT-MRAM consumes similar silicon area to an 8 MB capacity of MBC-DD SOT-MRAM. Higher memory capacity results in higher performance metrics, such as instruction per cycle (IPC) and energy efficiency due to

*DD SOT-MRAMs for different capacity relative to (a) SRAM and (b) conventional SOT-MRAM.*

*Area comparison of the STT-MRAM, conventional, SLC diode-based, S-MLC, P-MLC, MLC-SD, and MBC-*

From energy and performance perspective, SRAM can have higher hit/miss performance and energy efficiency compared to the various SOT-MRAM proposals at small memory capacity (e.g. 256 KB), as depicted by **Figure 11(a)**. This is because the impact of the large load capacitance of the SRAM cell would be minimal at these capacities [29]. However, for large memory capacity, the much higher load capacitance, parasitic, and routing complexity of the six transistors SRAM cell (as SRAM consume significantly larger silicon area compared to SOT-MRAM) causes the MRAM proposals to achieve better hit/miss performance and energy efficiency. On the contrary, the write energy for the various MRAM proposals is larger than that of the SRAM for the various memories capacity, as shown in **Figure 11(b)**. This is attributed to the larger write current requirement for the MRAM-based technologies relative to the SRAM technology. However, with improved SOT-MRAM technology such as the type-x SOT-MTJ [13] (achieves sub ns switching with write current of 100 μA), or the presented high-performance SOT-MRAM by IMEC [12] that achieves successful switching in 100's of ps range, the write energy can be reduced significantly, as illustrated in **Figure 12**. This makes the various

reduced access counts for the off-chip memory [30].

**Figure 10.**

*Integrated Circuits/Microchips*

**166**

*Comparison of the SRAM, STT-MRAM, conventional, SLC diode-based, S-MLC, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for different capacities relative to SRAM from (a) cache hit/miss energy per access perspective and (b) cache write dynamic energy per access perspective.*

#### **Figure 12.**

*Cache write dynamic energy per access comparison of the SRAM, conventional, P-MLC, MLC-SD, and MBC-DD SOT-MRAMs for different capacity relative to SRAM assuming improved high-speed SOT-MTJ technology (e.g. type-x reported in [13]).*

SOT-MRAM proposals a viable and realistic solution to replace the SRAM technology in certain applications.

In conclusion, the previous discussion shows that the various proposed SOT-MRAM cells do offer nonvolatility (i.e. nearly zero leakage), smaller silicon area, and high performance. It also indicates that these designs can compete with the current CMOS volatile technologies such as SRAM and DRAM. However, further development to reduce the write energy for the existing SOT-MTJ technology may be required to widen the application window for such SOT-MRAM technologies.

#### **5. Conclusion**

This chapter presents the various SOT-MRAM proposals in the literature highlighting the pros, cons, and operation of each design. SOT-MRAM relies on SOT technology, which offers various advantages such as high energy efficiency, fast switching speed, and high device reliability. However, conventional SLC SOT-MRAM requires two transistors to access a single bit. This in return results in a relatively large 1-bit effective area, which limits its application for large memory capacities. Hence, the various proposals in the literature targets reducing the 1-bit effective area compared to both conventional SOT-MRAM while maintaining the main advantages of SOT technology.

The various SOT-MRAM proposals have been divided into two main categories, which are diode-based and nondiode-based SOT-MRAM cells. These various SOT-MRAM cells have been evaluated from both cell and system level perspectives. The system-level evaluation is performed based on the utilization of the various cells as cache memory, and they are mainly compared to the current widely used technology as cache, which is the SRAM. In particular, five different proposals have been investigated. These proposals are S-MLC, P-MLC, diode-based SLC, MBC-DD, and MLC-SD SOT-MRAMs that are shown to offer 70, 79, 79, 89, and 89% reduced 1-bit effective area compared to SRAM and 28, 50, 50, 74, and 75% compared to conventional SOT-MRAM, respectively.

From energy perspective, S-MLC, P-MLC, MBC-DD, and MLC-SD consume higher write energy compared to conventional SOT-MRAM. P-MLC, MBC-DD, and MLC-SD consume higher worst-case write energy while writing nonidentical bits on the cell due to the enforced rule of employing two SOT-MTJs with different *I*c. However, if an equal probability of programming the various bits options is assumed, average energy efficiency similar to conventional SOT-MRAM may be achieved, whereas S-MLC involves writing one of the two MTJs in the cell using the energyinefficient STT technology, which also degrades the device reliability as a result of supplying large current through the MTJ stack. On the other hand, diode-based SLC SOT-MRAM may achieve similar write energy to the conventional SLC SOT-MRAM. However, similar to other diode-based designs (MBC-DD and MLC-SD), it still incorporates a diode in the read operation, which may add additional energy penalty as the read voltage needs to be large enough to overcome the diode's on-voltage.

**Author details**

National University of Singapore, Singapore

provided the original work is properly cited.

\*Address all correspondence to: karim.ali@u.nus.edu

*Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory*

*DOI: http://dx.doi.org/10.5772/intechopen.92120*

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

Karim Ali

**169**

It is noteworthy that the SLC proposals such as diode-based SLC and MBC-DD would be preferred solutions, thanks to their offered significant area reduction in addition to maintaining the advantages of the SLC sensing such as improved BER. However, that requires further improvement in the diode-MTJ stack technology such that the diode transient response would match the required read performance and the diode's on voltage would be small, and thus, the read energy will be reasonable. On the other hand, the MLC proposals such as P-MLC, S-MLC, and MLC-SD require improvements in the MLC sensing techniques to enhance its sensing distinguishability and BER such that it will meet the industry standards.

*Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory DOI: http://dx.doi.org/10.5772/intechopen.92120*

SOT-MRAM proposals a viable and realistic solution to replace the SRAM technol-

In conclusion, the previous discussion shows that the various proposed SOT-MRAM cells do offer nonvolatility (i.e. nearly zero leakage), smaller silicon area, and high performance. It also indicates that these designs can compete with the current CMOS volatile technologies such as SRAM and DRAM. However, further development to reduce the write energy for the existing SOT-MTJ technology may be required to widen the application window for such SOT-MRAM technologies.

This chapter presents the various SOT-MRAM proposals in the literature highlighting the pros, cons, and operation of each design. SOT-MRAM relies on SOT technology, which offers various advantages such as high energy efficiency, fast switching speed, and high device reliability. However, conventional SLC SOT-MRAM requires two transistors to access a single bit. This in return results in a relatively large 1-bit effective area, which limits its application for large memory capacities. Hence, the various proposals in the literature targets reducing the 1-bit effective area compared to both conventional SOT-MRAM while maintaining the

The various SOT-MRAM proposals have been divided into two main categories, which are diode-based and nondiode-based SOT-MRAM cells. These various SOT-MRAM cells have been evaluated from both cell and system level perspectives. The system-level evaluation is performed based on the utilization of the various cells as cache memory, and they are mainly compared to the current widely used technology as cache, which is the SRAM. In particular, five different proposals have been investigated. These proposals are S-MLC, P-MLC, diode-based SLC, MBC-DD, and MLC-SD SOT-MRAMs that are shown to offer 70, 79, 79, 89, and 89% reduced 1-bit effective area compared to SRAM and 28, 50, 50, 74, and 75% compared to conven-

From energy perspective, S-MLC, P-MLC, MBC-DD, and MLC-SD consume higher write energy compared to conventional SOT-MRAM. P-MLC, MBC-DD, and MLC-SD consume higher worst-case write energy while writing nonidentical bits on the cell due to the enforced rule of employing two SOT-MTJs with different *I*c. However, if an equal probability of programming the various bits options is assumed, average energy efficiency similar to conventional SOT-MRAM may be achieved, whereas S-MLC involves writing one of the two MTJs in the cell using the energyinefficient STT technology, which also degrades the device reliability as a result of supplying large current through the MTJ stack. On the other hand, diode-based SLC SOT-MRAM may achieve similar write energy to the conventional SLC SOT-MRAM. However, similar to other diode-based designs (MBC-DD and MLC-SD), it still incorporates a diode in the read operation, which may add additional energy penalty as the read voltage needs to be large enough to overcome the diode's on-voltage. It is noteworthy that the SLC proposals such as diode-based SLC and MBC-DD would be preferred solutions, thanks to their offered significant area reduction in addition to maintaining the advantages of the SLC sensing such as improved BER. However, that requires further improvement in the diode-MTJ stack technology such that the diode transient response would match the required read performance and the diode's on voltage would be small, and thus, the read energy will be reasonable. On the other hand, the MLC proposals such as P-MLC, S-MLC, and MLC-SD require improvements in the MLC sensing techniques to enhance its sensing distinguishability and BER such that it will meet the industry standards.

ogy in certain applications.

*Integrated Circuits/Microchips*

main advantages of SOT technology.

tional SOT-MRAM, respectively.

**168**

**5. Conclusion**
