3.4 Rectifier-antenna matching

3.3 Antenna measurement results

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3.3.1 Designed antenna S-parameters

and the layers alignment in fabrication process.

summarized as 7.8 dBi, 91.6%, 26, 21.6 dB, 79.5°

3.3.2 Radiation characteristics

73.5°

Figure 18.

166

Antenna radiation pattern measurement set-up.

Figure 16 shows the reflection coefficient response of the antenna obtained from CST simulation compared with the calculated response of the equivalent circuit model by using Agilent ADS software in addition to the measured reflection coefficient. Good agreement was between the results of simulated, measured and ADS model. The antenna resonates at two bands 1.95 GHz (f1) and 2.45 GHz (f2). The circular patch is designed to radiate at 2.45 GHz by the direct feed with the transmission line placed behind substrate 2. Whereas, 1.95 GHz resonance frequency is designed to radiate due to the capacitive coupling between the circular patch on the top of substrate 1 and the circular slot located on the ground plane, where in 1.95 GHz case the disc antenna is considered as a feeder for the circular slot. The performance of the proposed antenna was simulated and optimized by commercial EM software CST Microwave Studio. A prototype of the proposed antenna was fabricated and tested. The reflection coefficient of the antenna was measured by R&S ZVA 67 Network Analyzer. It is noted that the simulated and measured results of the input impedances of the antenna are in good agreement. Only, a small shift in the measured S-parameters was observed due to the connector soldering, fabrication tolerance, the adhesive between the two layers of the antenna

The simulated and measured results of E-plane and H-plane for the high gain antenna at f1 and f2 are shown in Figure 17(a) and (b), respectively. The measured values of gain, radiation efficiency, F/B ratio, cross polarization level, 3 dB angular beamwidth at the first resonance frequency (f1) are 8.3 dBi, 90%, 12, 22.3 dB,

, respectively. While at the second resonance frequency, these values can be

radiation pattern of the antenna were measured by the Anechoic Chamber shown in

, respectively. The gain and

In this design, a scheme used in [49] is employed to achieve a dual-band impedance transformation at the two frequency bands (f1 and f2). This scheme is used to match between a complex and frequency-dependent rectifier input impedance (ZRec) and a real impedance of the antenna (ZAnt) by using four different sections (Section 1–4) as shown in Figure 19. The matching technique can be summarized in the following steps:

Step 1: Achieve the conjugate matching between the load values at both resonant frequencies, that is, moving the two impedance values of the load (rectifier) on the Smith chart to be located on the same real circle with the imaginary parts are equal on both sides of the Smith chart as shown in Figure 20.

Step 2: Cancel the imaginary part of the impedances at f1 and f2.

Step 3: Real to real impedance transformation.

Each section is characterized by two values Z and θ, where Z is the section characteristic impedance and θ is the section electrical length. The function of the first section (Section 1) is to make the real value of the rectifier input impedance at

Figure 19. Dual-band matching circuit.

Figure 20. Matching steps indicated on smith chart.

f1 is equal to that of the rectifier input impedance at f2 and the imaginary parts are also equal but with opposite signs (one is positive (inductive reactance) and the other one is negative (capacitive reactance)); Section 1 parameters (Z1 and θ1) can be calculated from [50] as:

$$Z\_1 = \sqrt{\left(R\_{r1}R\_{r2} + X\_{r1}X\_{r2} + \frac{X\_{r1} + X\_{r2}}{R\_{r2} - R\_{r1}}(R\_{r1}X\_{r2} - R\_{r2}X\_{r1})\right)}\tag{9}$$

$$\theta\_1 = \frac{n\pi + \arctan\frac{Z\_1(R\_{r1} - R\_2)}{R\_{r1}X\_{r2} - R\_2X\_{r1}}}{(m+1)}\tag{10}$$

where n is an arbitrary integer and m = f2/f1. Section 2 is used to cancel the imaginary parts of the admittance Y1 at the two frequencies f1 and f2. Section 2 parameters can be determined as [49]:

$$Z\_2 = \frac{\tan \theta\_2}{B\_1} \tag{11}$$

$$\theta\_2 = \frac{(1+p)\pi}{(1+m)}\tag{12}$$

where p is an integer. Sections 3 and 4 are used for real to real impedance transformation, and their parameters can be calculated from Eqs. (13)–(17) [49, 51]

$$Z\_4 = \sqrt{\left(\frac{Z\_{A\text{nt}}(\mathbf{1} + \tan^2 \theta\_4)}{G\_1} - Z\_{A\text{nt}}^2\right) \frac{\mathbf{1}}{\tan \theta\_4}}\tag{13}$$

$$\theta\_4 = \frac{(\mathbf{1} + s)\pi}{(\mathbf{1} + m)} \tag{14}$$

$$Z\_3 = \frac{\tan \theta\_3}{B\_4} \tag{15}$$

above-mentioned diodes category, so these diodes have a high cutoff frequency and high conversion efficiency. The capacitor Cs is used to store the energy in one half cycle to double the charging voltage for Cp at the other half cycle, Cs also acts as bandpass filter to block the DC voltage generated from the nonlinear diodes. Cp has two functions, it is used for bypassing the higher order modes, generated from the nonlinear diode to the ground and getting a smooth DC output voltage as well. Also the shunt connection between Cp and the load impedance RL acts as a low pass filter. The rectifier is designed on Rogers Duroid RO3003 with a relative permittivity (εr) of 3, substrate thickness (h) of 0.76 mm, a dielectric loss tangent (tanδ) of 0.0013 and a copper thickness (t) of 0.017 mm. The simulated complex rectifier input impedance (ZRec) at two frequencies are (8 j 28.2) and (26.1 j 39.7) at f1 and f2, respectively, with a resistive load of 1.5 kΩ. The circuit parameters have been optimized to achieve the maximum conversion efficiency at the two frequency bands for the received input power levels. The parameters of the rectifier as well as the matching circuit are illustrated in Figure 21, where each line is defined by the length (L) and width (W). Also, the prototype of the fabricated rectifier is shown in

Rectifier layout; L1 = 4.5 mm, W1 = 1.54 mm, L2 = 4 mm, W2 = 0.33 mm, L3 = 5 mm, W3 = 1.96 mm, L4 = 3.52 mm, W4 = 2 mm, L5 = 4 mm, W5 = 0.36 mm, L6 = 4.98 mm, W6 = 0.31 mm, L7 = 5 mm, W7 = 0.29 mm, L8 = 5.1 mm, W8 = 0.43 mm, L9 = 4.8 mm, W9 = 0.3 mm, L10 = 4.88 mm, W10 = 0.33 mm,

Rectenna Systems for RF Energy Harvesting and Wireless Power Transfer

DOI: http://dx.doi.org/10.5772/intechopen.89674

The rectifying circuit including the matching network is simulated using Keysight advanced design system (ADS), while the antenna was designed using

Figure 21.

169

Figure 22.

Figure 21.

Rectenna measurement setup.

L11 = 1.81 mm, W11 = 0.84 mm.

3.6 Rectenna measurements

$$\theta\_3 = \frac{(1+q)\pi}{(1+m)}\tag{16}$$

$$B\_4 = \frac{\left(Z\_{Ant}^2 - Z\_4^2\right)\tan\theta\_4}{Z\_{Ant}^2 \times Z\_4 + Z\_4^3 \times \tan^2\theta\_4} \tag{17}$$

where q and s are integers.

#### 3.5 Rectifier design

Several rectifiers' topologies are used for energy harvesting, for instance, diodes in parallel connection, diodes in series connection, voltage doubler circuits, multistage voltage multiplier and so forth. Voltage multipliers generate high voltages from a low voltage power source. However, in this design a half-wave voltage doubler circuit, which is a special case of voltage multipliers, is used for the rectification to get high voltage with conservation of the design simplicity. The rectifier design as well as the matching network is depicted in Figure 21 [52]. The voltage doubler circuit comprises two Avago HSMS2850 Schottky diodes and two SMD capacitors (Cs = Cp = 100 pF). The Schottky diode has a built-in voltage (Vb) of 0.150 V and a breakdown voltage (Vbr) of 3.8 V. Due to the small values of the series resistance and the barrier capacitance (Rs of 25Ω and Cb of 0.18 pF) for the

Rectenna Systems for RF Energy Harvesting and Wireless Power Transfer DOI: http://dx.doi.org/10.5772/intechopen.89674

#### Figure 21.

f1 is equal to that of the rectifier input impedance at f2 and the imaginary parts are also equal but with opposite signs (one is positive (inductive reactance) and the other one is negative (capacitive reactance)); Section 1 parameters (Z1 and θ1) can

<sup>θ</sup><sup>1</sup> <sup>¼</sup> <sup>n</sup><sup>π</sup> <sup>þ</sup> arctan <sup>Z</sup>1ð Þ Rr1�Rr<sup>2</sup>

where n is an arbitrary integer and m = f2/f1. Section 2 is used to cancel the imaginary parts of the admittance Y1 at the two frequencies f1 and f2. Section 2

> <sup>Z</sup><sup>2</sup> <sup>¼</sup> tan <sup>θ</sup><sup>2</sup> B1

<sup>θ</sup><sup>2</sup> <sup>¼</sup> ð Þ <sup>1</sup> <sup>þ</sup> <sup>p</sup> <sup>π</sup> ð Þ 1 þ m

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

� � 1

<sup>θ</sup><sup>4</sup> <sup>¼</sup> ð Þ <sup>1</sup> <sup>þ</sup> <sup>s</sup> <sup>π</sup> ð Þ 1 þ m

<sup>Z</sup><sup>3</sup> <sup>¼</sup> tan <sup>θ</sup><sup>3</sup> B4

<sup>θ</sup><sup>3</sup> <sup>¼</sup> ð Þ <sup>1</sup> <sup>þ</sup> <sup>q</sup> <sup>π</sup> ð Þ 1 þ m

Ant � <sup>Z</sup><sup>2</sup> 4 � � tan θ<sup>4</sup>

Several rectifiers' topologies are used for energy harvesting, for instance, diodes in parallel connection, diodes in series connection, voltage doubler circuits, multistage voltage multiplier and so forth. Voltage multipliers generate high voltages from a low voltage power source. However, in this design a half-wave voltage doubler circuit, which is a special case of voltage multipliers, is used for the rectification to get high voltage with conservation of the design simplicity. The rectifier design as well as the matching network is depicted in Figure 21 [52]. The voltage doubler circuit comprises two Avago HSMS2850 Schottky diodes and two SMD capacitors (Cs = Cp = 100 pF). The Schottky diode has a built-in voltage (Vb) of 0.150 V and a breakdown voltage (Vbr) of 3.8 V. Due to the small values of the series

resistance and the barrier capacitance (Rs of 25Ω and Cb of 0.18 pF) for the

Ant � <sup>Z</sup><sup>4</sup> <sup>þ</sup> <sup>Z</sup><sup>3</sup>

<sup>B</sup><sup>4</sup> <sup>¼</sup> <sup>Z</sup><sup>2</sup>

Z2

� <sup>Z</sup><sup>2</sup> Ant

<sup>4</sup> � tan <sup>2</sup>θ<sup>4</sup>

where p is an integer. Sections 3 and 4 are used for real to real impedance transformation, and their parameters can be calculated from Eqs. (13)–(17) [49, 51]

> ZAnt 1 þ tan <sup>2</sup> ð Þ θ<sup>4</sup> G1

Rr1Rr<sup>2</sup> þ Xr1Xr<sup>2</sup> þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

s� �

Xr<sup>1</sup> þ Xr<sup>2</sup> Rr<sup>2</sup> � Rr<sup>1</sup>

Rr1Xr2�Rr2Xr<sup>1</sup>

ð Þ Rr1Xr<sup>2</sup> � Rr2Xr<sup>1</sup>

ð Þ <sup>m</sup> <sup>þ</sup> <sup>1</sup> (10)

tan θ<sup>4</sup>

(9)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

be calculated from [50] as:

Z<sup>1</sup> ¼

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parameters can be determined as [49]:

Z<sup>4</sup> ¼

where q and s are integers.

3.5 Rectifier design

168

s

Rectifier layout; L1 = 4.5 mm, W1 = 1.54 mm, L2 = 4 mm, W2 = 0.33 mm, L3 = 5 mm, W3 = 1.96 mm, L4 = 3.52 mm, W4 = 2 mm, L5 = 4 mm, W5 = 0.36 mm, L6 = 4.98 mm, W6 = 0.31 mm, L7 = 5 mm, W7 = 0.29 mm, L8 = 5.1 mm, W8 = 0.43 mm, L9 = 4.8 mm, W9 = 0.3 mm, L10 = 4.88 mm, W10 = 0.33 mm, L11 = 1.81 mm, W11 = 0.84 mm.

Figure 22. Rectenna measurement setup.

above-mentioned diodes category, so these diodes have a high cutoff frequency and high conversion efficiency. The capacitor Cs is used to store the energy in one half cycle to double the charging voltage for Cp at the other half cycle, Cs also acts as bandpass filter to block the DC voltage generated from the nonlinear diodes. Cp has two functions, it is used for bypassing the higher order modes, generated from the nonlinear diode to the ground and getting a smooth DC output voltage as well. Also the shunt connection between Cp and the load impedance RL acts as a low pass filter.

The rectifier is designed on Rogers Duroid RO3003 with a relative permittivity (εr) of 3, substrate thickness (h) of 0.76 mm, a dielectric loss tangent (tanδ) of 0.0013 and a copper thickness (t) of 0.017 mm. The simulated complex rectifier input impedance (ZRec) at two frequencies are (8 j 28.2) and (26.1 j 39.7) at f1 and f2, respectively, with a resistive load of 1.5 kΩ. The circuit parameters have been optimized to achieve the maximum conversion efficiency at the two frequency bands for the received input power levels. The parameters of the rectifier as well as the matching circuit are illustrated in Figure 21, where each line is defined by the length (L) and width (W). Also, the prototype of the fabricated rectifier is shown in Figure 21.

#### 3.6 Rectenna measurements

The rectifying circuit including the matching network is simulated using Keysight advanced design system (ADS), while the antenna was designed using ANSYS high-frequency structure simulator (HFSS). The enhanced-gain antenna described in [45] is used as a receiving antenna in the proposed rectenna to increase the rectifier sensitivity. Hence, increasing rectenna capability to harvest from low input power levels. The receiving antenna and the rectifier are integrated on the same substrate, fabricated and measured in the measurement setup shown in Figure 22. An Agilent Technologies E8257D Analog signal generator is used to send a microwave signal which is connected to a horn antenna with 9 dBi gain at the two frequencies. On the other hand, the rectenna under test (RUT) is connected with a voltmeter to measure the DC output voltage. To take the antenna radiation characteristics into account, the antenna effective area is considered. Hence, the RF-DC conversion efficiency of the proposed rectenna (η) is calculated as the following:

$$\eta = \frac{V\_{DC}^2}{P\_{in} \times R\_L} \times 100\tag{18}$$

where VDC is the measured DC output voltage, Pin is the received RF input power and RL is the resistive load. Pin is defined in Eq. (19)

$$P\_{\rm in} = P\_D \times A\_{\rm eff} \tag{19}$$

(f1 and f2); Figure 24(a) and (b) show the comparison between the measured and simulated results of RF-to-DC conversion efficiency and the DC output voltage versus the input power at f1 and f2, respectively. The maximum measured conversion efficiency is 63% with input power range of 14 dBm (from 3.5 to 10.5 dBm) at f1, while the measured efficiency at f2 is 69% with input power from 4.5 to 11 dBm (15.5 dBm). There is a slight shift between the simulation and measurement results, where the maximum simulated RF-DC conversion efficiency are 66 and 73% at the same two frequencies, respectively. Due to the limitations in the experiments, the

Simulated and measured conversion efficiency in addition to the DC output voltage versus input power (a) at f1

Rectenna Systems for RF Energy Harvesting and Wireless Power Transfer

DOI: http://dx.doi.org/10.5772/intechopen.89674

This chapter presents a study of rectenna systems for RF energy harvesting and wireless power transfer. A survey about employing rectennas in WPT, low input received power rectennas, single and multi-band rectennas, wide input received power rectennas are introduced. Finally, dual-band rectenna using voltage doubler rectifier and four-section matching network is discussed. The first part of the rectenna design is the dual-band disc antenna with enhanced gain in order to collect a highest amount of RF energy. It radiates at 1.95 and 2.45 GHz. The measured results showed the gain of 8.3 and 7.8 dBi at 1.95 and 2.45 GHz, respectively. The disc antenna is integrated with a dual-band rectifier with four-section matching network to introduce a dual-frequency rectenna with higher conversion efficiency over wide band of the input power for multiband RF energy harvesting. The rectenna gives maximum RF-DC measured conversion efficiency of 63% and 69% at 1.95 GHz and 2.5 GHz, respectively. it also operates over a wide range of the input

power; it covers the range of 14 and 15.5 dBm at f1 and f2, respectively for a

conversion efficiency higher than 50% with load resistance (RL) = 1K. The rectenna is simulated, fabricated and measured. The simulated and measured results show

received input power is limited only up to 11 dBm.

4. Conclusions

Figure 24.

(b) at f2.

good agreement.

171

where PD is the RF power density and Aeff is the antenna effective area. PD and Aeff are calculated using Eqs. (20) and (21), respectively.

$$P\_D = \frac{P\_t G\_t}{4\pi r^2} \tag{20}$$

$$A\_{\rm eff} = G\_r \frac{\lambda^2}{4\pi} \tag{21}$$

Pt is the transmitting power, Gt is the horn antenna gain and r is the distance between the transmitter and the rectenna all are known. Therefore, the RF-to-DC conversion efficiency can be measured. For far-field measurements, r is chosen of 40 cm. Figure 23 shows the photo of the rectenna measurement setup.
