**2. MPCU based FIR filter architectures**

The FIR filter top-level module as shown in **Figure 2** consists of a datapath unit and a control unit. The control unit is realised using the microprogrammed approach. The MPCU consist of two main parts, the first part addresses the microinstructions stored in the control memory while the second part holds and generates microinstruction for the datapath unit [1–3].

**289**

**Figure 3.**

filter is listed in **Table 1** [1].

*First architecture of FIR filter [1].*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters*

The first architecture of *N*-tap FIR filter as shown in **Figure 3** comprises of a control and datapath units. The control signals generated by MPCU are fed to the datapath unit. For demonstration, the sequence of operation for a third-order FIR

*DOI: http://dx.doi.org/10.5772/intechopen.90662*

**Figure 2.** *FIR filter module.*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters DOI: http://dx.doi.org/10.5772/intechopen.90662*

**Figure 3.** *First architecture of FIR filter [1].*

The first architecture of *N*-tap FIR filter as shown in **Figure 3** comprises of a control and datapath units. The control signals generated by MPCU are fed to the datapath unit. For demonstration, the sequence of operation for a third-order FIR filter is listed in **Table 1** [1].

*Control Theory in Engineering*

*N*-tap or (*N*-*1*)

*N-tap direct form FIR filter.*

**Figure 1.**

coefficients.

chapter.

Direct form is the most commonly used FIR filter. As can be seen from **Figure 1**,

registers. The tap coefficients, {*W0*, *W1*, *W2*,……,*WN-1*} constitute the filter impulse response. The filter type (low pass, high pass or band pass) is determined by these

Different techniques for the field programmable gate array (FPGA) realisation of FIR filter using microprogrammed control unit (MPCU) have been reported in the literature [1–3]. Multipliers and adders play a dominant role in the optimal realisation of FIR filters [4, 5]. The objective of this chapter is to further explore this technique using Wallace tree multiplier with different adder configurations for optimal realisation of FIR filter [6]. The proposed design is modular and scalable

The rest of the chapter is organised as follows. Section 2 presents two different designs of MPCU-based FIR filters. Section 3 describes the design of Wallace tree multiplier using two different adder configuration. Section 4 presents the FPGA implementation results and its analysis. Finally, Section 5 concludes the

The FIR filter top-level module as shown in **Figure 2** consists of a datapath unit and a control unit. The control unit is realised using the microprogrammed approach. The MPCU consist of two main parts, the first part addresses the microinstructions stored in the control memory while the second part holds and gener-

which enables realisation of higher-order FIR filter.

**2. MPCU based FIR filter architectures**

ates microinstruction for the datapath unit [1–3].

th order FIR filter consist of *N* multipliers, *N*-*1* adders and *N* shift

**288**

**Figure 2.** *FIR filter module.*


### **Table 1.**

*Control signals for third-order FIR filter (Architecture-1).*

The datapath consist of the following modules:


For (*N-1*) th order FIR filter, the datapath unit of second architecture uses *N* multipliers and *N-1* adders. In addition to the multiplier and adder, the datapath also need the following modules for proper functioning of FIR filter as illustrated in **Figure 4**.


For illustration, the sequence of operation for third-order FIR filter in this case is listed in **Table 2** [2].

**291**

**Figure 4.**

*Second architecture of FIR filter [1].*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters*

*DOI: http://dx.doi.org/10.5772/intechopen.90662*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters DOI: http://dx.doi.org/10.5772/intechopen.90662*

**Figure 4.** *Second architecture of FIR filter [1].*

*Control Theory in Engineering*

• 8-bit data registers

**Table 1.**

• *N*-to-*M* decoder

• Multiplier

• Adder

For (*N-1*)

• 8-bit coefficient registers

• *N*:1 MUX for tap selection

• 2:1 MUX for dataflow control

• 16-bit accumulator

• 16-bit latch register.

• 8-bit data registers

• *M-*to-*N* decoder

listed in **Table 2** [2].

• 8-bit coefficient registers

• One 16-bit latch register

The datapath consist of the following modules:

*Control signals for third-order FIR filter (Architecture-1).*

**No. CS Branch address Control functions**

 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0

**LEn LD1 LD0 DC DL Dm YL**

• *N*:1 multiplexer (MUX) for data selection

th order FIR filter, the datapath unit of second architecture uses *N* multi-

pliers and *N-1* adders. In addition to the multiplier and adder, the datapath also need the following modules for proper functioning of FIR filter as illustrated in **Figure 4**.

For illustration, the sequence of operation for third-order FIR filter in this case is

**290**


#### **Table 2.**

**293**

**Figure 5.**

*Block diagram of Wallace tree multiplier.*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters*

To overcome the drawbacks associated with conventional array multiplier, tree multiplier is considered. Wallace tree is one such implementation of adder tree that results in high speed. A conventional Wallace tree multiplier uses half and full adders to multiply two numbers in three steps as shown in **Figure 5** [4]. First step is to multiply each bit of *n*-bit multiplicand with every bit of *n*-bit multiplier to yield

 results. Each bit carry different weights based on the position of the generated bits. The second step involves reduction of partial products using full and half adders. This process continues until two layer of partial products remain. In the last step, the remaining two layers of partial product are added using conventional

In this chapter, two different variants of Wallace tree multiplier are realised. First variant uses conventional full and half adders, while a carry skip adder

Carry look ahead adder (CLA) provides high-speed computation but at the cost of high power and high area. To overcome the drawbacks of CLA, CSKA is used

*DOI: http://dx.doi.org/10.5772/intechopen.90662*

(CSKA) is used in the second variant.

**3. Wallace tree multiplier**

*n2*

adder [5].

*Control signals for third-order FIR filter (Architecture-2).*

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters DOI: http://dx.doi.org/10.5772/intechopen.90662*
