**1. Introduction**

Digital filters play an important role in many digital signal processing (DSP) applications. These applications range from noise reduction, spectral shaping, equalisation, signal detection and signal analysis, etc. The basic building blocks of digital filter are adder, multiplier and register based delay elements. Based on the application requirement, these blocks are connected to realise a particular architecture of filter. There are several ways to realise digital filters. Two such filters used in different applications are finite impulse response (FIR) and infinite impulse response (IIR) filters. FIR filters are widely preferred for DSP applications because they are always stable, exhibit linear phase properties and provide no feedback. Convolution, the core operation of FIR filter, performed on a window of *N* data samples involves multiplication and addition. For optimal realisation of FIR filter, these arithmetic operation needs to be optimised.

**Figure 1.** *N-tap direct form FIR filter.*

Direct form is the most commonly used FIR filter. As can be seen from **Figure 1**, *N*-tap or (*N*-*1*) th order FIR filter consist of *N* multipliers, *N*-*1* adders and *N* shift registers. The tap coefficients, {*W0*, *W1*, *W2*,……,*WN-1*} constitute the filter impulse response. The filter type (low pass, high pass or band pass) is determined by these coefficients.

Different techniques for the field programmable gate array (FPGA) realisation of FIR filter using microprogrammed control unit (MPCU) have been reported in the literature [1–3]. Multipliers and adders play a dominant role in the optimal realisation of FIR filters [4, 5]. The objective of this chapter is to further explore this technique using Wallace tree multiplier with different adder configurations for optimal realisation of FIR filter [6]. The proposed design is modular and scalable which enables realisation of higher-order FIR filter.

The rest of the chapter is organised as follows. Section 2 presents two different designs of MPCU-based FIR filters. Section 3 describes the design of Wallace tree multiplier using two different adder configuration. Section 4 presents the FPGA implementation results and its analysis. Finally, Section 5 concludes the chapter.
