**4. Results and analysis**

All the top-level modules and sub-modules described in this chapter are coded in Verilog HDL using top-down hierarchical design methodology. The proposed designs are synthesised and implemented in Virtex-5 (xc5vlx50t-1ff1136) FPGA device using Synplify pro electronic design automation (EDA) tool [7]. The results are evaluated based on the slice look-up tables (LUTs), minimum period and maximum clock frequency of the target FPGA. **Tables 3** and **4** summarise the implementation results for both the FIR filter architectures.

It can be inferred that, generally, the Wallace tree multiplier using conventional full and half adder consumes less FPGA slice LUT (area) but at the cost of higher minimum period (delay). In the first architecture, Wallace tree multiplier using CSKA

**295**

**5. Conclusion**

**No. of taps**

**Table 3.**

**No. of taps**

**Table 4.**

**Filter order**

**Filter order**

> **Slice LUTs**

**Min. period (ns)**

*FPGA resource utilisation for first FIR filter using Wallace tree multiplier.*

**Min. period (ns)**

*FPGA resource utilisation for second FIR filter using Wallace tree multiplier.*

and half adders.

**Acknowledgements**

*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters*

has the lowest minimum period. It is therefore concluded that the first FIR filter architecture using Wallace tree multiplier with CSKA provides optimal result. It is also observed that more FPGA resources are utilised as we increase the order of the filter.

**Wallace tree using FA/HA Wallace tree using CSKA**

**Wallace tree using FA/HA Wallace tree using CSKA**

**Slice LUTs**

**Max. freq. (MHz)**

 3 147 12.093 82.7 142 10.143 98.6 7 181 12.479 80.1 147 11.448 87.4 15 184 12.166 82.2 180 10.491 85.3 31 212 12.616 79.3 155 10.300 97.1 63 209 12.319 81.2 154 11.044 90.5

> **Slice LUTs**

**Min. period (ns)**

**Min. period (ns)**

> **Max. freq. (MHz)**

> **Max. freq. (MHz)**

**Max. freq. (MHz)**

 3 278 13.876 72.1 284 11.026 90.7 7 687 19.756 50.6 699 17.552 57.0 15 1268 31.662 31.6 1371 29.150 34.3 31 2304 54.787 18.3 1670 52.377 19.1 63 4352 101.39 9.9 3319 98.678 10.1

In this chapter, we further explored the design of MPCU-based digital FIR filters. MPCU is a promising technique that could be utilised for optimal realisation of digital filters used in DSP systems. The overall performance of the FIR filter depends on the multiplier and adder used in the multiply-accumulate unit. Two different architectures of FIR filter were designed using Wallace tree multiplier employing two variants of adder, one using conventional full/half adders and the other using CSKA. All the designs were realised in Xilinx Virtex-5 FPGA using Synplify pro EDA tool. Based on the reports generated by the EDA tool, it is concluded that the design of first FIR filter using the Wallace tree multiplier with CSKA provides optimal result in comparison to the one using conventional full

The authors gratefully acknowledge the support provided by King Abdulaziz

City for Science and Technology (KACST) under the National Electronics,

Communication and Photonics research program.

*DOI: http://dx.doi.org/10.5772/intechopen.90662*

**Slice LUTs**


*Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters DOI: http://dx.doi.org/10.5772/intechopen.90662*

**Table 3.**

*Control Theory in Engineering*

which provides a balanced implementation [5]. A CSKA comprises of a basic ripple carry adder with a distinctive speed-up carry chain referred to as a skip chain. As

All the top-level modules and sub-modules described in this chapter are coded in Verilog HDL using top-down hierarchical design methodology. The proposed designs are synthesised and implemented in Virtex-5 (xc5vlx50t-1ff1136) FPGA device using Synplify pro electronic design automation (EDA) tool [7]. The results are evaluated based on the slice look-up tables (LUTs), minimum period and maximum clock frequency of the target FPGA. **Tables 3** and **4** summarise the

It can be inferred that, generally, the Wallace tree multiplier using conventional full and half adder consumes less FPGA slice LUT (area) but at the cost of higher minimum period (delay). In the first architecture, Wallace tree multiplier using CSKA

shown in **Figure 6**, a skip chain comprises of AND gate and 2:1 MUX.

implementation results for both the FIR filter architectures.

**294**

**4. Results and analysis**

*Block diagram of 4-bit CSKA.*

**Figure 6.**

*FPGA resource utilisation for first FIR filter using Wallace tree multiplier.*


**Table 4.**

*FPGA resource utilisation for second FIR filter using Wallace tree multiplier.*

has the lowest minimum period. It is therefore concluded that the first FIR filter architecture using Wallace tree multiplier with CSKA provides optimal result. It is also observed that more FPGA resources are utilised as we increase the order of the filter.
