**5.1 Charge trapping in defect levels**

The ultrathin nature makes 2D semiconductors highly suitable as the readout channel in memory, as their conductance can be modulated greatly by slight charge trapping, including by the inherent trap states in devices. In literatures, the prepared MoS2 often exhibits midgap trap states [54], and the device also suffers from interface defect states, e.g., at the interface with SiO2 [55], which may capture some charges under gate modulation by the shifted Fermi level EF (the trap states below EF are prone to be filled with electrons, while those states above EF tend to be empty). This usually results in large hysteresis in field-effect devices and different conduction states after positive and negative gate stress. However, the limited density of trap states restricted the on–off switch in memory. Lee et al. reported an improved device by introducing localized electronic states in MoS2 using tailored

SiO2 substrate with functional silanol groups (Si-OH)(**Figure 6a**) [56], which exhibit strong polar interaction and causes local potential fluctuation in energy band. The device is composed of thin MoS2 layer on SiO2 substrate, using the back-Si as the gate. The conduction state is reset by using positive gate bias (80 V) and then programmed using light exposure under gate bias (20 V). Applying *V*G = 80 V fills the traps with electrons, resulting in *OFF* states of channel when removing *V*G, while light exposure releases the trapped electrons by generating electron–hole pairs that promote the charge release. The device manifested highly linear readout charges programmed by light exposure time. However, since the trapped charges can be thermally activated to conduction/valanced band for trapped electrons/ holes, the programmed states exhibit transient change of conduction states after initial program (**Figure 6b**), and the charge readout is slow ~seconds.

The above optoelectronic memory works under visible light excitation due to the bandgap limit of MoS2. Wang et al. reported an infrared memory using the vdW heterostructure of MoS2/PbS [57], which is sensitive to 1550 nm radiation with the sensitization of narrow bandgap PbS thin flakes epitaxially grown on MoS2 (as illustrated in **Figure 6c**). The charge trapping is based on the electron injection into MoS2 by the generation of large amount of photoexcited electrons in PbS under light illumination, as indicated by the energy band diagram shown in **Figure 6d**. However, the device exhibits low resistance change by light exposure and transient conductance variation after program, due to the eventual recombination of electron–hole pairs in dark, which drive carrier distribution to equilibrium. Also, the program speed is directly determined by photon energy and the overall incident power, as the former governs the energy of photoexcited carriers (whether it is sufficient to overcome the interfacial potential barrier to be injected into the other side) and the latter determines the number of excited carriers. Alternatively, the charge trapping in defect states in dielectric materials tends to exhibit long retention time. Xiang et al. constructed a nonvolatile memory using WSe2 transferred on insulate h-BN layer (**Figure 6e**) [58]. The inherent defect states in h-BN are able

#### **Figure 6.**

*2D optoelectronic memories. (a) Schematic of a 2D memory based on MoS2 on tailored SiO2 surface and (b) the light exposure time programmed memory states in the device, reproduced with permission from Ref. [56], Copyright 2017 Nature Publishing Group. (c) An infrared memory based on vdW heterostructure of PbS/ MoS2 and (d) the schematic of its band alignment, reproduced with permission from Ref. [57], Copyright 2018 Science. (e) The schematic and optical image (inset) of an optoelectronic memory based on WSe2 on h-BN, (f) shows the device conductance change during electrical erase and optical program, reproduced with permission from Ref. [58], Copyright 2018 Nature Publishing Group.*

**159**

**Figure 7.**

*Emerging Artificial Two-Dimensional van der Waals Heterostructures for Optoelectronics*

memory exhibits long-term retention characteristics for more than 104

single-unit device but to the average of multiple connections [59].

to trap photoexcited carriers in WSe2, therefore enabling optoelectronic memory operation. The memory is operated under the simultaneous light exposure and gate bias, thus to force the charge trapping into the midgap states of h-BN. Because of the large bandgap of h-BN, the trapped charges can hardly move, and the resulted

optoelectronic memory can be feasibly transformed into multi-bit memory, by using either the amplitude of gate bias or the light irradiation power, wavelength, and pulse number as the input (**Figure 6f**). However, slight temporal change of conductance is still observed due to the recombination of photogenerated electron– hole pairs in WSe2 itself. Nevertheless, the strategy has been exploited to develop artificial optoelectronic synapses, the overall weight of which is less sensitive to the

Instead of charge trapping in random trap states, float gate structure exhibits well-described charge trapping characteristics and long-term retention characteristics [60]. The charge trapping can also be triggered by light irradiation to the light sensing semiconductor channel or float gate. Using 2D materials, the float gate structure can be assembled by h-BN as the insulate barrier and 2D semiconductors

**Figure 7a** displays the initial 2D float memory based on graphene and MoS2 separated by h-BN [61]. The device usually has the structure of a field-effect transistor but with an additional float gate inserted between the source-drain channel and the control gate. The memory behavior of the device by using MoS2 as the channel and graphene as the float gate is shown in **Figure 7b**. The charge trapping is based on the quantum tunneling under gate bias, which induces FN tunneling by lowering the effective tunneling barrier with trigonal potential profile in the insulate h-BN

*Several representative 2D float gate heterostructures. (a) The schematic configuration of a float gate memory based on MoS2/h-BN/graphene (b) shows the hysteresis memory behavior using back-Si gate, and the inset depicts the MoS2 conductance modulated by float gate potential, reproduced with permission from Ref. [61], Copyright 2013 Nature Publishing Group. (c) Schematic of the semi-float gate device base on graphene/h-BN/ WSe2 heterostructure for the formation of lateral diode and (d) its* IV *characteristic showing rectification behavior by the formation of p-n junction, reproduced with permission from Ref. [62], Copyright 2017 Nature Publishing Group. (e) A two-terminal optoelectronic memory based on vdW heterostructure of MoS2/h-BN/ graphene (f) displays its IV characteristics in dark and light illumination, showing the light programmed on and off states under positive bias, and the memory states are electrically erased using large negative bias,* 

*reproduced with permission from Ref. [20], Copyright 2017 Wiley-VCH.*

s. Such

*DOI: http://dx.doi.org/10.5772/intechopen.88433*

**5.2 Float gate heterostructures**

as the channel.

*Emerging Artificial Two-Dimensional van der Waals Heterostructures for Optoelectronics DOI: http://dx.doi.org/10.5772/intechopen.88433*

to trap photoexcited carriers in WSe2, therefore enabling optoelectronic memory operation. The memory is operated under the simultaneous light exposure and gate bias, thus to force the charge trapping into the midgap states of h-BN. Because of the large bandgap of h-BN, the trapped charges can hardly move, and the resulted memory exhibits long-term retention characteristics for more than 104 s. Such optoelectronic memory can be feasibly transformed into multi-bit memory, by using either the amplitude of gate bias or the light irradiation power, wavelength, and pulse number as the input (**Figure 6f**). However, slight temporal change of conductance is still observed due to the recombination of photogenerated electron– hole pairs in WSe2 itself. Nevertheless, the strategy has been exploited to develop artificial optoelectronic synapses, the overall weight of which is less sensitive to the single-unit device but to the average of multiple connections [59].

### **5.2 Float gate heterostructures**

*Smart Nanosystems for Biomedicine, Optoelectronics and Catalysis*

SiO2 substrate with functional silanol groups (Si-OH)(**Figure 6a**) [56], which exhibit strong polar interaction and causes local potential fluctuation in energy band. The device is composed of thin MoS2 layer on SiO2 substrate, using the back-Si as the gate. The conduction state is reset by using positive gate bias (80 V) and then programmed using light exposure under gate bias (20 V). Applying *V*G = 80 V fills the traps with electrons, resulting in *OFF* states of channel when removing *V*G, while light exposure releases the trapped electrons by generating electron–hole pairs that promote the charge release. The device manifested highly linear readout charges programmed by light exposure time. However, since the trapped charges can be thermally activated to conduction/valanced band for trapped electrons/ holes, the programmed states exhibit transient change of conduction states after

initial program (**Figure 6b**), and the charge readout is slow ~seconds.

The above optoelectronic memory works under visible light excitation due to the bandgap limit of MoS2. Wang et al. reported an infrared memory using the vdW heterostructure of MoS2/PbS [57], which is sensitive to 1550 nm radiation with the sensitization of narrow bandgap PbS thin flakes epitaxially grown on MoS2 (as illustrated in **Figure 6c**). The charge trapping is based on the electron injection into MoS2 by the generation of large amount of photoexcited electrons in PbS under light illumination, as indicated by the energy band diagram shown in **Figure 6d**. However, the device exhibits low resistance change by light exposure and transient conductance variation after program, due to the eventual recombination of electron–hole pairs in dark, which drive carrier distribution to equilibrium. Also, the program speed is directly determined by photon energy and the overall incident power, as the former governs the energy of photoexcited carriers (whether it is sufficient to overcome the interfacial potential barrier to be injected into the other side) and the latter determines the number of excited carriers. Alternatively, the charge trapping in defect states in dielectric materials tends to exhibit long retention time. Xiang et al. constructed a nonvolatile memory using WSe2 transferred on insulate h-BN layer (**Figure 6e**) [58]. The inherent defect states in h-BN are able

*2D optoelectronic memories. (a) Schematic of a 2D memory based on MoS2 on tailored SiO2 surface and (b) the light exposure time programmed memory states in the device, reproduced with permission from Ref. [56], Copyright 2017 Nature Publishing Group. (c) An infrared memory based on vdW heterostructure of PbS/ MoS2 and (d) the schematic of its band alignment, reproduced with permission from Ref. [57], Copyright 2018 Science. (e) The schematic and optical image (inset) of an optoelectronic memory based on WSe2 on h-BN, (f) shows the device conductance change during electrical erase and optical program, reproduced with permission* 

**158**

**Figure 6.**

*from Ref. [58], Copyright 2018 Nature Publishing Group.*

Instead of charge trapping in random trap states, float gate structure exhibits well-described charge trapping characteristics and long-term retention characteristics [60]. The charge trapping can also be triggered by light irradiation to the light sensing semiconductor channel or float gate. Using 2D materials, the float gate structure can be assembled by h-BN as the insulate barrier and 2D semiconductors as the channel.

**Figure 7a** displays the initial 2D float memory based on graphene and MoS2 separated by h-BN [61]. The device usually has the structure of a field-effect transistor but with an additional float gate inserted between the source-drain channel and the control gate. The memory behavior of the device by using MoS2 as the channel and graphene as the float gate is shown in **Figure 7b**. The charge trapping is based on the quantum tunneling under gate bias, which induces FN tunneling by lowering the effective tunneling barrier with trigonal potential profile in the insulate h-BN

#### **Figure 7.**

*Several representative 2D float gate heterostructures. (a) The schematic configuration of a float gate memory based on MoS2/h-BN/graphene (b) shows the hysteresis memory behavior using back-Si gate, and the inset depicts the MoS2 conductance modulated by float gate potential, reproduced with permission from Ref. [61], Copyright 2013 Nature Publishing Group. (c) Schematic of the semi-float gate device base on graphene/h-BN/ WSe2 heterostructure for the formation of lateral diode and (d) its* IV *characteristic showing rectification behavior by the formation of p-n junction, reproduced with permission from Ref. [62], Copyright 2017 Nature Publishing Group. (e) A two-terminal optoelectronic memory based on vdW heterostructure of MoS2/h-BN/ graphene (f) displays its IV characteristics in dark and light illumination, showing the light programmed on and off states under positive bias, and the memory states are electrically erased using large negative bias, reproduced with permission from Ref. [20], Copyright 2017 Wiley-VCH.*

layer. Alternatively using graphene as the channel results in low on–off ratio due to the zero-bandgap nature of graphene, by what the graphene channel can hardly be turned off. Notably, the thickness of h-BN is critical for the float memory, as too thin h-BN results in direct tunneling loss of charges and poor retention behavior, while too thick h-BN is good for retention but requires high operation voltages. The optimal thickness of h-BN is ~6–10 nm. The thin thickness of h-BN enables efficient tunneling of channel conductance by the float gate potential, as indicated in the inset of **Figure 7b**. Instead of graphene and MoS2, many other 2D semiconductors have been explored for the float memory, including WSe2, ReS2, BP, etc. [63–66]. They all displayed high on–off ratio up to 107 , which is likely to benefit multi-bit storage.

Because of the excellent tunability of charges in 2D channel, the float gate structure has been reformed into semi-float and two-terminal structures. **Figure 7c** shows a semi-float gate device with WSe2 as the channel [62], in which the graphene as float gate spans half of the channel. Thus, the charge trapping in graphene only modulates the carrier concentration in partially the overlapped region. Taking advantage of the ambipolar characteristic of WSe2, the gate region can be tuned either p- or n-doped, forming the lateral pn diodes or Schottky diodes with apparent rectification behavior (**Figure 7d**). A special advantage of such device is their reconfigurable device behavior on demand. The device structure can be further simplified into two-terminal structures by removing the control gate, which usually is the back-Si gate [20]. **Figure 7e** displays a schematic structure of such twoterminal float memory. The charge tunneling can be realized by applying enough source-drain bias as indicated in **Figure 7f**. Because of the nonuniform electric field in channel, the potential drop between drain and float gate is sufficient to induce charge injection into float gate. After applying negative *V*ds, electrons are injected into graphene, resulting in off state when reading at *V*ds > 0. However, shining light to the device releases the trapped charges and recovers the initial state. Thus, the memory can be electrically erased and programmed by light exposure. Due to the absorption limit of MoS2, the device is only programmable with wavelengths <650 nm. By controlling the light dose with power and duration, the device manifests 18 states, rendering potential application for multi-bit purposes. However, an essential drawback of such two-terminal device is the high power consumption during electrical erase, as high source-drain current is present compared to the negligible leakage current via gate coupling.

The various heterostructures by versatile 2D stacking have enabled the blossom of 2D optoelectronic devices. There is also an emerging of optoelectronic programmed logic elements using the flexible gate coupling in ultrathin thickness [67]. The pathway toward multifunctional 2D devices seems very promising to stimulate indispensable applications based on continuously expanding family of 2D materials.
