**Acknowledgements**

*Smart Nanosystems for Biomedicine, Optoelectronics and Catalysis*

They all displayed high on–off ratio up to 107

negligible leakage current via gate coupling.

storage.

layer. Alternatively using graphene as the channel results in low on–off ratio due to the zero-bandgap nature of graphene, by what the graphene channel can hardly be turned off. Notably, the thickness of h-BN is critical for the float memory, as too thin h-BN results in direct tunneling loss of charges and poor retention behavior, while too thick h-BN is good for retention but requires high operation voltages. The optimal thickness of h-BN is ~6–10 nm. The thin thickness of h-BN enables efficient tunneling of channel conductance by the float gate potential, as indicated in the inset of **Figure 7b**. Instead of graphene and MoS2, many other 2D semiconductors have been explored for the float memory, including WSe2, ReS2, BP, etc. [63–66].

Because of the excellent tunability of charges in 2D channel, the float gate structure has been reformed into semi-float and two-terminal structures. **Figure 7c** shows a semi-float gate device with WSe2 as the channel [62], in which the graphene as float gate spans half of the channel. Thus, the charge trapping in graphene only modulates the carrier concentration in partially the overlapped region. Taking advantage of the ambipolar characteristic of WSe2, the gate region can be tuned either p- or n-doped, forming the lateral pn diodes or Schottky diodes with apparent rectification behavior (**Figure 7d**). A special advantage of such device is their reconfigurable device behavior on demand. The device structure can be further simplified into two-terminal structures by removing the control gate, which usually is the back-Si gate [20]. **Figure 7e** displays a schematic structure of such twoterminal float memory. The charge tunneling can be realized by applying enough source-drain bias as indicated in **Figure 7f**. Because of the nonuniform electric field in channel, the potential drop between drain and float gate is sufficient to induce charge injection into float gate. After applying negative *V*ds, electrons are injected into graphene, resulting in off state when reading at *V*ds > 0. However, shining light to the device releases the trapped charges and recovers the initial state. Thus, the memory can be electrically erased and programmed by light exposure. Due to the absorption limit of MoS2, the device is only programmable with wavelengths <650 nm. By controlling the light dose with power and duration, the device manifests 18 states, rendering potential application for multi-bit purposes. However, an essential drawback of such two-terminal device is the high power consumption during electrical erase, as high source-drain current is present compared to the

The various heterostructures by versatile 2D stacking have enabled the blossom of 2D optoelectronic devices. There is also an emerging of optoelectronic programmed logic elements using the flexible gate coupling in ultrathin thickness [67]. The pathway toward multifunctional 2D devices seems very promising to stimulate indispensable applications based on continuously expanding family of 2D

As a summary, in this chapter, we have introduced various types of 2D heterostructures for both photodetection and optoelectronic memory, both of which extensively take advantage of the feasible field-effect modulation to the optoelectronic properties of 2D materials. In the past few years, we have witnessed the marvelous revolution of design and construction of functional devices using diverse 2D materials and feasible vdW stacking methods. The progress will undoubtedly continue given the remarkable flexibility of stacking 2D material in atomic thickness, which had been extremely challenging for 3D materials. However, one shall

, which is likely to benefit multi-bit

**160**

materials.

**6. Conclusions**

This work was supported by National Natural Science Foundation of China (Grant No. 61804059).
