**5.3 Current-Fed Push-Pull (CFPP) isolated boost SMR**

#### **5.3.1 System configuration and operation**

The power circuit and control scheme of the CFPP isolated boost SMR are shown in Figs. 11(a) and 11(b). In making the analysis, some assumptions are made: (i) all circuit components are ideal; (ii) the active voltage clamp circuits including *S*<sup>3</sup> , *S*4 and *Ca* are neglected; (iii) *vvV t in ac m* == = sinω 2 sin *V t ac* ω ; (iv) the circuit is operated under CCM. In the established current-fed push-pull SMR, the duty ratio *D*Δ *t T on s* / ( 0.5 1 < < *D* ) is set. The gate signal of *S*2 is generated from *S*1 by shifting 180° . Detailed analysis process can be referred to (Hsieh, 2010), only a brief description and some key formulas are given here. During analysis, the voltage transfer ratio from *in v* to *Vdc* can be derived as:

$$\frac{V\_{dc}}{\upsilon\_{in}} = \frac{N\_s}{N\_p} \frac{1}{\mathbf{2(1 - D)}}\tag{22}$$

Some Basic Issues and Applications of

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 269

Fig. 11. The current-fed push-pull isolated boost SMR: (a) power circuit; (b) control scheme

ω

<sup>1200</sup> ˆ( ) <sup>2</sup> 2 22.856A <sup>ˆ</sup> 110 2 0.9 0.75

×××

<sup>ˆ</sup> ( 0.5) <sup>ˆ</sup> 0.1( ) 2.2856A *ac <sup>s</sup>*

,min <sup>ˆ</sup> ( 0.5) 0.735mH *ac*

The inductances of an available inductor measured using HIOKI 3532-50 LCR meter are *L* = (2.03mH, ESR = 210m Ω at 120Hz) and (1.978mH, ESR = 5.68 Ω at 25kHz). Hence this

= ×= × =

 π

max

<sup>−</sup> Δ = ≤ = (26)

Δ (27)

*t* = can be calculated as:

(25)

The maximum inductor current occurred at 0.5

*<sup>P</sup> <sup>i</sup> V*

,min

η

,min

*L*

*L L VD T i i L*

*V D*

*s L*

*f i* <sup>−</sup> ≥ =

*ac*

The condition of boosting inductance *L* is obtained as:

*dc*

max

*L*

Let the inductor current ripple be:

It should be noted that the duty ratio *D* is a time varying function for the constant *Vdc* and time varying input DC voltage *in ac v v* = . Moreover, the variations of *Vdc* and *Vac* should be considered in making the derivation of component ratings.


Table 2. Measured characteristics of the developed bridgeless boost SMR under two loads

#### **5.3.2 Circuit design**

#### a. Specifications

The system variables and specifications of the established SMR are given as follows:

AC input voltage: 110V 10% /60Hz *Vac* = ± .

DC output: *Vdc* = 300V ~ 350V ( ≥ ×× = 110V 1.1 2 171V ), *Pdc* = 1200W .

Switching frequency: 25kHz *sf* = , Efficiency: η≥ 75% , 0.95 *PF* ≥ (Lagging).

#### b. Boosting inductor

To provide magnetization path of the inductor, duty cycle must be greater than 0.5 at any time, and from (22):

$$m \stackrel{\Delta}{=} \frac{N\_s}{N\_p} \le \frac{300}{\sqrt{2} \times 110} \frac{2(1 - 0.5)}{1} \tag{23}$$

Thus the turn ratio can be found to be 1.935 *n* ≤ . By choosing 1 *n* = , the instantaneous duty ratio at 0.5 ω π*t* = can be found from (22) as:

$$D\_{\text{max}} = 1 - \frac{\hat{V}\_{\text{ac, min}}}{2V\_{dc, \text{max}}} = 1 - \frac{140}{2 \times 350} = 0.8 \tag{24}$$

components are ideal; (ii) the active voltage clamp circuits including *S*<sup>3</sup> , *S*4 and *Ca* are

ω

the established current-fed push-pull SMR, the duty ratio *D*Δ *t T on s* / ( 0.5 1 < < *D* ) is set. The gate signal of *S*2 is generated from *S*1 by shifting 180° . Detailed analysis process can be referred to (Hsieh, 2010), only a brief description and some key formulas are given here.

It should be noted that the duty ratio *D* is a time varying function for the constant *Vdc* and time varying input DC voltage *in ac v v* = . Moreover, the variations of *Vdc* and *Vac* should be

> Resistive load ( *RL* = 400Ω )

*Vac* 110V/60Hz 110V/60Hz *Pac* 233.1W 497.5W *Vdc* 300.6V 300.2V *Pdc* 223.5W 475.9W

 95.88% 95.66% *THDi* 6.02% 6.11% *PF* (Lagging) 0.996 0.996 Table 2. Measured characteristics of the developed bridgeless boost SMR under two loads

The system variables and specifications of the established SMR are given as follows:

DC output: *Vdc* = 300V ~ 350V ( ≥ ×× = 110V 1.1 2 171V ), *Pdc* = 1200W .

To provide magnetization path of the inductor, duty cycle must be greater than 0.5 at any

300 2(1 0.5) 2 110 <sup>1</sup>

Thus the turn ratio can be found to be 1.935 *n* ≤ . By choosing 1 *n* = , the instantaneous duty

*<sup>V</sup>* =− =− = <sup>×</sup>

<sup>ˆ</sup> <sup>140</sup> <sup>1</sup> 1 0.8 2 2 350

,min

*ac dc V*

,max

<sup>−</sup> Δ ≤ ×

*s p N*

*N*

η

AC input voltage: 110V 10% /60Hz *Vac* = ± .

Switching frequency: 25kHz *sf* = , Efficiency:

*n*

max

*D*

*t* = can be found from (22) as:

1 2(1 )

; (iv) the circuit is operated under CCM. In

*vN D* <sup>=</sup> <sup>−</sup> (22)

Resistive load ( *RL* = 200Ω )

≥ 75% , 0.95 *PF* ≥ (Lagging).

(23)

(24)

ω

considered in making the derivation of component ratings.

Load Cases

Variables

**5.3.2 Circuit design**  a. Specifications

b. Boosting inductor

time, and from (22):

ratio at 0.5 ω

 π

η

2 sin *V t ac*

During analysis, the voltage transfer ratio from *in v* to *Vdc* can be derived as:

*dc s in p V N*

neglected; (iii) *vvV t in ac m* == = sin

Fig. 11. The current-fed push-pull isolated boost SMR: (a) power circuit; (b) control scheme The maximum inductor current occurred at 0.5 ω π*t* = can be calculated as:

$$\left(\hat{\mathbf{i}}\_{\perp}\right)\_{\text{max}} = \frac{P\_{\text{dc}}}{\hat{V}\_{\text{ac,min}}\eta} \times 2 = \frac{1200}{110 \times \sqrt{2} \times 0.9 \times 0.75} \times 2 = 22.856 \,\text{A} \tag{25}$$

Let the inductor current ripple be:

$$
\Delta \dot{i}\_L = \frac{\hat{V}\_{\text{ac,min}} (D - 0.5) T\_s}{L} \le 0.1 \{\hat{i}\_L\}\_{\text{max}} = 2.2856 \,\text{A} \tag{26}
$$

The condition of boosting inductance *L* is obtained as:

$$L \ge \frac{\hat{V}\_{ac,\text{min}}(D - 0.5)}{f\_s \Delta i\_L} = 0.735 \text{mH} \tag{27}$$

The inductances of an available inductor measured using HIOKI 3532-50 LCR meter are *L* = (2.03mH, ESR = 210m Ω at 120Hz) and (1.978mH, ESR = 5.68 Ω at 25kHz). Hence this

Some Basic Issues and Applications of

a. Current controller

b. Voltage controller

a. Dynamic model estimation

b. Controller design

2009a) one can solve to obtain:

here.

**5.3.3 Controller design of CFPP Isolated boost SMR** 

chosen via trial-and-error, and finally it is found that:

occurred, *re t* = restore time, *om* Δ*v* = maximum voltage dip.

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 271

Similarly, the upper value of *KPi* can be found from (17) to be 1.53 *K K Pi Pi* < = (*Vdc* is replaced by *<sup>p</sup> v* and 0 *ac v* = is set). Accordingly 0.5 *KPi* = is set. Then the integral gain is

<sup>2500</sup> ( ) 0.5 *Ii*

The robust current tracking error cancellation controller shown in Fig.11(b) is not applied

The voltage loop dynamic model and the proposed feedback control scheme are shown in Fig. 12, the SMR is reasonably represented by a first-order process in main dynamic frequency range. The voltage feedback sensing factor is set as *Kv* = 0.002V/V . The desired voltage response due to a step load power change is also sketched in Fig. 12, which possesses the key features: (i) no overshoot and steady-state error; (ii) the typical key response points indicated in Fig. 12 are: ( <sup>1</sup> *<sup>f</sup> t t* = , 1 0.5 Δ =Δ *V v dc om* ), ( <sup>2</sup> *<sup>m</sup> t t* = , Δ =Δ *V v dc om* <sup>2</sup> ), ( <sup>3</sup> *re t t* = , 3 0.1 Δ =Δ *V v dc om* ), with *<sup>f</sup> t* = fall time, *mt* = the time at which maximum dip being

( ) *Pv Iv*

The quantitative design technique presented in (Y.C. Chang & Liaw, 2009a) is applied to here to find the parameters of ( ) *G s cv* to have the desired regulation response shown in Fig.

*s*

i. Let the ( ) 6 10.5 *Gs K K s s cv Pv Iv* = + =+ be arbitrary set, and the SMR is normally

ii. A step load resistor change of *RL* = → 300Ω 200Ω ( Δ = *Pdc* 149.3W , *Pdc* = → 302.8W 452.1W ) is applied and the response of *Vdc* is recorded. By choosing three typical response points as indicated in Fig. 12 to be ( 4.4V − ,27.5ms), ( 7.6V − ,55ms) and ( 1V − ,1500ms), through careful derivation (Y.C. Chang & Liaw, 2009a), one can obtain the estimated dynamic model parameters are obtained:

7.95 *a* = , 2975.71 *b* = , *Kpl* =0.00084542 (32)

At the given operating point ( 300V *Vdc* = , *RL* = 300Ω ), the voltage regulation control specifications are defined as: ,max Δ = *Vdc* 5.0V , 800ms *re t* = for a step load power change of Δ = *Pdc* 149.3W . Following the quantitative design process presented in (Y.C. Chang & Liaw,

operated at the chosen operating point ( \* *Vdc* = 300V , *Pdc* = 302.8W ).

*Ks K G s*

*s s*

= + =+ (30)

<sup>+</sup> <sup>=</sup> (31)

*ci Pi <sup>K</sup> Gs K*

For the ease of implementation, the PI voltage feedback controller is chosen:

12. The details are neglected and only a brief description is given here.

*cv*

inductor is suited and employed here. Using the inductance of *L* = 1.978mH at *f* = 25kHz, the inductor current ripple given in (26) becomes *<sup>L</sup>* Δ = *i* 0.85A.

c. Output capacitor

The output filtering capacitor *Cd* = 2200 F/450V μ is chosen to yield the following peak-topeak voltage ripple:

$$
\Delta V\_{dc} = \frac{V\_{dc}}{\alpha\_1 R\_L C\_d} = \frac{P\_{dc}}{\alpha\_1 C\_d V\_{dc}} = \frac{1200}{2\pi \times 60 \times 2200 \times 10^{-6} \times 350} = 4.13\,\text{V} \tag{28}
$$

#### d. Power semiconductor devices

From (25) and (26), the maximum current flowing through the switches and all the diodes can be calculated as ,max max <sup>ˆ</sup> *ii i SL L* = + Δ= + × = ( ) 0.5 22.856 0.5 0.85 23.28A . The maximum voltage for the switches is 700V which is found from Fig. 11, and voltage rating for the load side rectifier diodes is 350V. Accordingly, the IGBT K40T120 (Infineon) (1200V, ID= 40A ( 100 C° , continuous), IDM = 105A (pulsed)) and the fast diode DSEP60-06A (IXYS) (600V, average current IFAVM = 60A) are chosen for implementing the switches and all the diodes, respectively.

#### e. Transformer design

The AMCU series UU core AMCU-80 manufactured by AMOSENSE Cooperation is used to wind the push-pull transformer here. The designed results (Hsieh, 2010) are summarized as followed. To lower the core loss, B = 0.25T is set, and thus the maximum flux density variation will be 2 0.25T 0.5T Δ=× = *B* . From Faraday's law, the turns of the primary side can be expressed as follows:

$$N\_p = \frac{n \times V\_{dc, \text{max}} (1 - D\_{\text{min}}) T\_s}{A\_c \times \Delta B} \tag{29}$$

The known parameters in (29) are: 1 *n* = , *Vdc* ,max =350V, min *D* = 0.5 , <sup>2</sup> *Ae* = 5.21cm , 40 s *Ts* = *μ* . Hence *Np* = 26.87 is found, and *N N p s* = = 32 are chosen here. The measured parameters of the designed transformer at *f* = 25kHz using HIOKI 3532-50 LCR meter are: *Lm* = 1.086mH , <sup>1</sup> *Lls* = 10.795 H*μ* , <sup>2</sup> *Lls* = 8.838 H*μ* , ESR 20.4 = Ω , where *Lls*1 and *Lls*2 denote the leakage inductances of the two transformer primary windings.

f. Active voltage clamp

As generally known that a current-fed push-pull boost converter may possess serious problems due to the voltage spikes caused by transformer leakage inductances, the problems lie in having lower efficiency and increased voltage stress of power switches. The active voltage clamp circuit (Kwon, 2008; Sangwon & Sewan, 2010) is used to solve this problem. As shown in Fig. 11(a), the active voltage clamp circuit consists of two auxiliary switches ( *S*<sup>3</sup> , *S*<sup>4</sup> ) and one capacitor *Ca* . These two auxiliary switches are switched in complement fashion to the two main switches ( *S*<sup>1</sup> , *S*<sup>2</sup> ) but with a small dead-time. The used components for active voltage clamp circuit are: *Ca* = 0.4 F/1000V *μ* , *S*3 and *S*4 are IGBT K40T120 (Infineon) (1200V, ID= 40A ( 100 C° , continuous), IDM = 105A (pulsed)), the deadtime 1 s *dt* = μis set here.

#### **5.3.3 Controller design of CFPP Isolated boost SMR**

#### a. Current controller

270 Electrical Generation and Distribution Systems and Power Quality Disturbances

inductor is suited and employed here. Using the inductance of *L* = 1.978mH at *f* = 25kHz,

is chosen to yield the following peak-to-

(28)

6

2 60 2200 10 350

<sup>1200</sup> 4.13V

× − <sup>=</sup> × Δ (29)

μ

 π*RC CV* <sup>−</sup> Δ= = = <sup>=</sup> ×× × ×

From (25) and (26), the maximum current flowing through the switches and all the diodes can be calculated as ,max max <sup>ˆ</sup> *ii i SL L* = + Δ= + × = ( ) 0.5 22.856 0.5 0.85 23.28A . The maximum voltage for the switches is 700V which is found from Fig. 11, and voltage rating for the load side rectifier diodes is 350V. Accordingly, the IGBT K40T120 (Infineon) (1200V, ID= 40A ( 100 C° , continuous), IDM = 105A (pulsed)) and the fast diode DSEP60-06A (IXYS) (600V, average current IFAVM = 60A) are chosen for implementing the switches and all the diodes,

The AMCU series UU core AMCU-80 manufactured by AMOSENSE Cooperation is used to wind the push-pull transformer here. The designed results (Hsieh, 2010) are summarized as followed. To lower the core loss, B = 0.25T is set, and thus the maximum flux density variation will be 2 0.25T 0.5T Δ=× = *B* . From Faraday's law, the turns of the primary side

,max min (1 ) *dc <sup>s</sup>*

*e nV D T*

The known parameters in (29) are: 1 *n* = , *Vdc* ,max =350V, min *D* = 0.5 , <sup>2</sup> *Ae* = 5.21cm , 40 s *Ts* = *μ* . Hence *Np* = 26.87 is found, and *N N p s* = = 32 are chosen here. The measured parameters of the designed transformer at *f* = 25kHz using HIOKI 3532-50 LCR meter are: *Lm* = 1.086mH , <sup>1</sup> *Lls* = 10.795 H*μ* , <sup>2</sup> *Lls* = 8.838 H*μ* , ESR 20.4 = Ω , where *Lls*1 and *Lls*2 denote

As generally known that a current-fed push-pull boost converter may possess serious problems due to the voltage spikes caused by transformer leakage inductances, the problems lie in having lower efficiency and increased voltage stress of power switches. The active voltage clamp circuit (Kwon, 2008; Sangwon & Sewan, 2010) is used to solve this problem. As shown in Fig. 11(a), the active voltage clamp circuit consists of two auxiliary switches ( *S*<sup>3</sup> , *S*<sup>4</sup> ) and one capacitor *Ca* . These two auxiliary switches are switched in complement fashion to the two main switches ( *S*<sup>1</sup> , *S*<sup>2</sup> ) but with a small dead-time. The used components for active voltage clamp circuit are: *Ca* = 0.4 F/1000V *μ* , *S*3 and *S*4 are IGBT K40T120 (Infineon) (1200V, ID= 40A ( 100 C° , continuous), IDM = 105A (pulsed)), the dead-

*A B*

the inductor current ripple given in (26) becomes *<sup>L</sup>* Δ = *i* 0.85A.

1 1

*V P <sup>V</sup>* ωω

*dc dc*

*L d d dc*

*p*

*N*

the leakage inductances of the two transformer primary windings.

The output filtering capacitor *Cd* = 2200 F/450V

*dc*

d. Power semiconductor devices

c. Output capacitor

peak voltage ripple:

respectively.

e. Transformer design

can be expressed as follows:

f. Active voltage clamp

time 1 s *dt* =

μ

is set here.

Similarly, the upper value of *KPi* can be found from (17) to be 1.53 *K K Pi Pi* < = (*Vdc* is replaced by *<sup>p</sup> v* and 0 *ac v* = is set). Accordingly 0.5 *KPi* = is set. Then the integral gain is chosen via trial-and-error, and finally it is found that:

$$\mathbf{G}\_{cl}(\mathbf{s}) = \mathbf{K}\_{p\_l} + \frac{\mathbf{K}\_{li}}{\mathbf{s}} = \mathbf{0}.5 + \frac{\mathbf{2500}}{\mathbf{s}} \tag{30}$$

The robust current tracking error cancellation controller shown in Fig.11(b) is not applied here.

b. Voltage controller

The voltage loop dynamic model and the proposed feedback control scheme are shown in Fig. 12, the SMR is reasonably represented by a first-order process in main dynamic frequency range. The voltage feedback sensing factor is set as *Kv* = 0.002V/V . The desired voltage response due to a step load power change is also sketched in Fig. 12, which possesses the key features: (i) no overshoot and steady-state error; (ii) the typical key response points indicated in Fig. 12 are: ( <sup>1</sup> *<sup>f</sup> t t* = , 1 0.5 Δ =Δ *V v dc om* ), ( <sup>2</sup> *<sup>m</sup> t t* = , Δ =Δ *V v dc om* <sup>2</sup> ), ( <sup>3</sup> *re t t* = , 3 0.1 Δ =Δ *V v dc om* ), with *<sup>f</sup> t* = fall time, *mt* = the time at which maximum dip being occurred, *re t* = restore time, *om* Δ*v* = maximum voltage dip.

For the ease of implementation, the PI voltage feedback controller is chosen:

$$\mathbf{G}\_{\rm cr}(\mathbf{s}) = \frac{\mathbf{K}\_{\rm p\_{\rm v}}\mathbf{s} + \mathbf{K}\_{\rm lv}}{\mathbf{s}} \tag{31}$$

The quantitative design technique presented in (Y.C. Chang & Liaw, 2009a) is applied to here to find the parameters of ( ) *G s cv* to have the desired regulation response shown in Fig. 12. The details are neglected and only a brief description is given here.

	- i. Let the ( ) 6 10.5 *Gs K K s s cv Pv Iv* = + =+ be arbitrary set, and the SMR is normally operated at the chosen operating point ( \* *Vdc* = 300V , *Pdc* = 302.8W ).
	- ii. A step load resistor change of *RL* = → 300Ω 200Ω ( Δ = *Pdc* 149.3W , *Pdc* = → 302.8W 452.1W ) is applied and the response of *Vdc* is recorded. By choosing three typical response points as indicated in Fig. 12 to be ( 4.4V − ,27.5ms), ( 7.6V − ,55ms) and ( 1V − ,1500ms), through careful derivation (Y.C. Chang & Liaw, 2009a), one can obtain the estimated dynamic model parameters are obtained:

$$a = 7.95 \text{ }, \; b = 2975.71 \text{ }, \; K\_{pl} = 0.00084542 \tag{32}$$

#### b. Controller design

At the given operating point ( 300V *Vdc* = , *RL* = 300Ω ), the voltage regulation control specifications are defined as: ,max Δ = *Vdc* 5.0V , 800ms *re t* = for a step load power change of Δ = *Pdc* 149.3W . Following the quantitative design process presented in (Y.C. Chang & Liaw, 2009a) one can solve to obtain:

$$\mathbf{G}\_{\rm cp}(\mathbf{s}) = \mathbf{K}\_{\rho\_{\rm p}} + \frac{\mathbf{K}\_{\rm lv}}{\mathbf{s}} = 10.0036 + \frac{33.8878}{\mathbf{s}} \tag{33}$$

Some Basic Issues and Applications of

300V *Vdc*

300V *Vdc*

summarized in Table 3. And the measured ( \*

(a)

*Li*′ \* *Li*

110V/60Hz *Vac* = and *RL* = 100Ω : (a) ( \*

this is mainly due to the addition of isolated HF transformer.

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 273

908.5W ) are shown in Figs.14(a) and 14(b), respectively. From the results, one can find that the developed SMR possesses good power quality control performances under wide load range. The lower efficiencies compared with the previous two types of SMRs are observed,

5V

5V

Fig. 13. Measured (upper) and simulated (lower) *Vdc* by PI control without ( 0 *Wd* = ) and

(a)

(b)

*Li* , *Li*′ ); (b) ( *ac v* , *ac i* )

Figs. 15(a) to 15(d) show the standard PMSM drives equipped with different front-end AC/DC converters. In making experimental works, the following inputs are set: (i) Diode

Fig. 14. Measured steady-state results of the current-fed push-pull boost SMR at

**5.4 Evaluation for the PMSM drive with different front-end AC/DC converters** 

*ac v*

*ac i*

300V *Vdc*

300V *Vdc*

500ms

with ( 0 *Wd* ≠ ) robust control due to a step load power change of Δ = *Pdc* 149.3W

( *Pdc* = → 302.8W 452.1W , \* *Vdc* = 300V ): (a) 0 *Wd* = ; (b) 0.5 *Wd* =

*Li* , *Li* ) and ( *ac v* , *ac i* ) under ( *RL* = 100Ω , *Pdc* =

(b)

5V

5V

500ms

6.25A

100V 30A

1ms

5ms

The simulated and measured output voltage responses (not shown here) are confirmed their closeness and satisfying the specified control specifications.

Fig. 12. The established current-fed push-pull boost SMR control scheme and the desired regulation response

#### c. Robust voltage error cancellation controller

A simple robust voltage error cancellation controller (RVECC) presented in (Chai & Liaw, 2007) is applied here to enhance the SMR voltage regulation control robustness. In the control system shown in Fig. 11(b), a robust compensation control command \* *Vdcr* is generated from the voltage error *<sup>v</sup>* ε through a weighting function ( ) /(1 ) *Ws W s ddd* = +τ with *Wd* being a weighting factor. The low pass filter process with cut-off frequency 1 /(2 ) 120Hz *cd <sup>d</sup> f* = = πτ ( 0.0013263 *<sup>d</sup>* τ = ) is used to reduce the effects of high-frequency noises on dynamic control behavior.

From Fig. 11(b) one can derive that the original voltage tracking error \* ε *v dc dc* = − *V V*′ will be reduced to

$$(V\_{dc}^{"\prime} - V\_{dc}^{\prime} = (1 - \frac{\mathcal{W}\_d}{1 + \tau\_d s})\mathcal{E}\_v = (1 - \mathcal{W}\_d)\mathcal{E}\_v \; , \; 0 \le \mathcal{W}\_d < 1\tag{34}$$

where the approximation is made for the main dynamic signals. Hence the original voltage error can be reduced by a factor of (1 ) − *Wd* within main dynamic frequency range. The selection of *Wd* must be made considering the compromise between control performance and effects of system noises.

Figs. 13(a) and 13(b) show the simulated and measured output voltage responses by PI control without ( 0 *Wd* = ) and with ( 0.5 *Wd* = ) robust control due to a step load power change of Δ = *Pdc* 149.3W ( *Pdc* = → 302.8W 452.1W , \* *Vdc* = 300V ). The results show that they are very close and the effectiveness of robust control in the improvement of voltage regulation response.

Let *Vac* =110V/60Hz and \* *Vdc* =300V, and the PI feedback and robust controls are all operated, the measured steady-state characteristics at ( *RL* = 400Ω , *Pdc* = 234.6W ), ( *RL* = 200Ω , *Pdc* = 465.8W ), ( *RL* = 133Ω , *Pdc* = 623.8W ) and ( *RL* = 100Ω , *Pdc* = 908.5W ) are

33.8878 ( ) 10.0036 *Iv*

The simulated and measured output voltage responses (not shown here) are confirmed their

Fig. 12. The established current-fed push-pull boost SMR control scheme and the desired

A simple robust voltage error cancellation controller (RVECC) presented in (Chai & Liaw, 2007) is applied here to enhance the SMR voltage regulation control robustness. In the control system shown in Fig. 11(b), a robust compensation control command \* *Vdcr* is

with *Wd* being a weighting factor. The low pass filter process with cut-off frequency

where the approximation is made for the main dynamic signals. Hence the original voltage error can be reduced by a factor of (1 ) − *Wd* within main dynamic frequency range. The selection of *Wd* must be made considering the compromise between control performance

Figs. 13(a) and 13(b) show the simulated and measured output voltage responses by PI control without ( 0 *Wd* = ) and with ( 0.5 *Wd* = ) robust control due to a step load power change of Δ = *Pdc* 149.3W ( *Pdc* = → 302.8W 452.1W , \* *Vdc* = 300V ). The results show that they are very close and the effectiveness of robust control in the improvement of voltage

Let *Vac* =110V/60Hz and \* *Vdc* =300V, and the PI feedback and robust controls are all operated, the measured steady-state characteristics at ( *RL* = 400Ω , *Pdc* = 234.6W ), ( *RL* = 200Ω , *Pdc* = 465.8W ), ( *RL* = 133Ω , *Pdc* = 623.8W ) and ( *RL* = 100Ω , *Pdc* = 908.5W ) are

ε

From Fig. 11(b) one can derive that the original voltage tracking error \*

\* ' (1 ) (1 ) <sup>1</sup> *d dc dc v d v d <sup>W</sup> V V <sup>W</sup> s* ε

τ

( 0.0013263 *<sup>d</sup>*

τ

*s s*

=+= + (33)

through a weighting function ( ) /(1 ) *Ws W s ddd* = +

ε

= ) is used to reduce the effects of high-frequency

 ε

− =− ≈− <sup>+</sup> , 0 1 ≤ < *Wd* (34)

τ

*v dc dc* = − *V V*′ will be

*cv Pv <sup>K</sup> Gs K*

closeness and satisfying the specified control specifications.

c. Robust voltage error cancellation controller

generated from the voltage error *<sup>v</sup>*

noises on dynamic control behavior.

regulation response

1 /(2 ) 120Hz *cd <sup>d</sup> f* = = πτ

and effects of system noises.

regulation response.

reduced to

summarized in Table 3. And the measured ( \* *Li* , *Li* ) and ( *ac v* , *ac i* ) under ( *RL* = 100Ω , *Pdc* = 908.5W ) are shown in Figs.14(a) and 14(b), respectively. From the results, one can find that the developed SMR possesses good power quality control performances under wide load range. The lower efficiencies compared with the previous two types of SMRs are observed, this is mainly due to the addition of isolated HF transformer.

Fig. 13. Measured (upper) and simulated (lower) *Vdc* by PI control without ( 0 *Wd* = ) and with ( 0 *Wd* ≠ ) robust control due to a step load power change of Δ = *Pdc* 149.3W ( *Pdc* = → 302.8W 452.1W , \* *Vdc* = 300V ): (a) 0 *Wd* = ; (b) 0.5 *Wd* =

Fig. 14. Measured steady-state results of the current-fed push-pull boost SMR at 110V/60Hz *Vac* = and *RL* = 100Ω : (a) ( \* *Li* , *Li*′ ); (b) ( *ac v* , *ac i* )

#### **5.4 Evaluation for the PMSM drive with different front-end AC/DC converters**

Figs. 15(a) to 15(d) show the standard PMSM drives equipped with different front-end AC/DC converters. In making experimental works, the following inputs are set: (i) Diode

Some Basic Issues and Applications of

Resistive load ( *RL* = 400Ω )

*<sup>r</sup>* ), ( *HA* , \*

tracking errors exist in speed and phase current under \*

*HA*

*as \* i*′ *as <sup>i</sup>*

*ac i*

(a) 5ms

*<sup>r</sup>* ),( *HA* , \*

diode rectifier front-end at: (a) ( 220V/60Hz *Vac* = , \*

ω

*ac v*

Load Cases

Variables

η

The measured ( \*

PMSM drive under \*

Fig. 16. Measured ( \*

(b): ( 220V/60Hz *Vac* = , \*

ω*r* ,ω

( \* ω

**5.4.1 Diode rectifier front-end** 

ω*r* ,ω

ω

100rpm 2000rpm \* ω*r* ω*r*

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 275

Resistive load ( *RL* = 200Ω )

*Vac* 110V/60Hz 110V/60Hz 110V/60Hz 110V/60Hz *Pac* 298.6W 557.4W 697.4W 1082.2W *Vdc* 301.2V 300.8V 300.5V 300.3V *Pdc* 234.6W 465.8W 623.8W 908.5W

 78.57% 83.57% 89.45% 83.95% *THDi* 8.83% 6.62% 6.53% 3.82% *PF* (Lagging) 0.997 0.998 0.998 0.998

Table 3. Measured characteristics of the current-fed push-pull boost SMR under four loads

*as i* , *as i*′ ) and ( *ac v* , *ac i* ) at ( \*

the insufficient DC-link voltage (*Vdc* = 278.4V ) established by rectifier for encountering the back-EMF effect. In addition, the peaky *ac i* leads to poor power factor and high *THDi* .

3000rpm

5ms

*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

5ms

4A

200V 10A

*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω ) are shown in Fig. 16(a) and Fig. 16(b), and the corresponding steady-state characteristics are listed in Table 4. One can notice the normal operation of the

ω

*HA*

*as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with

*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω );

ω

*as i*′

\* ω*r*

> *\* as i*

*ac v*

*ac i*

(b) 5ms

ω*r*

*<sup>r</sup>* = 2000rpm . However, the results in Fig. 16(b) indicate that large

ω

Resistive load ( *RL* = 133Ω )

Resistive load ( *RL* = 100Ω )

*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ) and

*<sup>r</sup>* = 3000rpm . This is mainly due to

5ms

5ms

4A

200V 10A

100rpm

rectifier: 220V/60Hz *Vac* = ,*Vdc* will vary with loading conditions; (ii) SMRs: 110V/60Hz *Vac* = , *Vdc* = 300V with satisfactory regulation control, the switching frequency 25kHz *sf* = is set. The measured results are summarized as follows:

Fig. 15. The circuit configuration of established standard PMSM drive with SMR front-end: (a) diode rectifier front-end; (b) standard boost SMR front-end; (c) bridgeless boost SMR front-end; (d) current-fed push-pull boost SMR front-end


Table 3. Measured characteristics of the current-fed push-pull boost SMR under four loads

#### **5.4.1 Diode rectifier front-end**

274 Electrical Generation and Distribution Systems and Power Quality Disturbances

rectifier: 220V/60Hz *Vac* = ,*Vdc* will vary with loading conditions; (ii) SMRs: 110V/60Hz *Vac* = , *Vdc* = 300V with satisfactory regulation control, the switching frequency

> *Ls Ls*

EC Encoder signals

> *as i bs i cs i*

c

(b)

(a)

PMSM

*eas ebs ecs*

*n*

*Ls Ls*

> *Ls Ls*

PMSM

*eas ebs ecs*

*n*

*Ls Ls*

PMSM

*eas ebs ecs*

*n*

*Te* ω*r*

*sr sr sr*

EC Encoder signals

*as i bs i cs i*

c

*N*

*T*<sup>1</sup> *T*3 *T*<sup>5</sup>

*T*<sup>4</sup> *T*<sup>6</sup> *T*2

b

*Te* ω*r*

PMSM

*eas ebs ecs*

*n*

*Te* ω*r*

*sr sr sr*

EC Encoder signals

> *sr sr sr*

EC Encoder signals

*as i bs i cs i*

c

(c)

*Pdc*

a

(d) Fig. 15. The circuit configuration of established standard PMSM drive with SMR front-end: (a) diode rectifier front-end; (b) standard boost SMR front-end; (c) bridgeless boost SMR

*Te* ω*r*

*sr sr sr*

*as i bs i cs i*

c

*T*<sup>1</sup> *T*<sup>3</sup> *T*<sup>5</sup>

*T*4 *T*6 *T*2

b

*N*

*T*<sup>1</sup> *T*<sup>3</sup> *T*<sup>5</sup>

a *Cd*

*Pdc*

*T*<sup>4</sup> *T*6 *T*<sup>2</sup>

b

*N*

*Cd Vdc*

PMSG

Dynamic load *Ls*

*TL*

*PL*

PMSG

PMSG

Dynamic load *Ls*

*TL*

Dynamic load *Ls*

*TL*

*PL*

*RL*

*PL*

PMS G

Dynamic load *Ls*

*TL*

*PL*

*RL*

*RL*

*RL*

25kHz *sf* = is set. The measured results are summarized as follows:

*T*<sup>1</sup> *T*<sup>3</sup> *T*<sup>5</sup>

*T*4 *T*6 *T*2

b

*Vdc*

*L D*

*iL*

Standard boost SMR front-end

> *S si*

Bridgeless boost SMR front-end *di*

*Cd*

*Vdc*

*Vdc*

*Np Ns* :

*D*<sup>1</sup> *D*<sup>2</sup>

*D*<sup>3</sup> *D*<sup>4</sup>

*id*

*Pdc*

*iac* a

*vac*

*ac i*

*ac i*

*<sup>L</sup> 0.5L i*

*0.5L*

<sup>1</sup> *S* <sup>2</sup> *S*

*S*1

Current-fed push-pull boost SMR front -end

3 *S*

*Lm*

*Lm*

front-end; (d) current-fed push-pull boost SMR front-end

*S*2

*Ca S*4

*Pac*

*L*

*<sup>L</sup> Pac <sup>i</sup>*

*Lv*

*vac ac i* *ac v*

*Pac*

*vac*

*Pac*

*N*

*Pdc*

a

*Cd*

The measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( *HA* , \* *as i* , *as i*′ ) and ( *ac v* , *ac i* ) at ( \* ω*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ) and ( \* ω*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω ) are shown in Fig. 16(a) and Fig. 16(b), and the corresponding steady-state characteristics are listed in Table 4. One can notice the normal operation of the PMSM drive under \* ω*<sup>r</sup>* = 2000rpm . However, the results in Fig. 16(b) indicate that large tracking errors exist in speed and phase current under \* ω*<sup>r</sup>* = 3000rpm . This is mainly due to the insufficient DC-link voltage (*Vdc* = 278.4V ) established by rectifier for encountering the back-EMF effect. In addition, the peaky *ac i* leads to poor power factor and high *THDi* .

Fig. 16. Measured ( \* ω*r* ,ω*<sup>r</sup>* ),( *HA* , \* *as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with diode rectifier front-end at: (a) ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ); (b): ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

Some Basic Issues and Applications of

Variables

η

Cases

front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

*as <sup>i</sup>*′ \* *as i*

*ac v*

(a)

ω

front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

Cases

ω*r* ,ω

Fig. 18. Measured ( \*

(b): ( 220V/60Hz *Vac* = , \*

Variables

η

*ac i*

*<sup>r</sup>* ), ( *HA* , \*

bridgeless boost SMR front-end at: (a) ( 220V/60Hz *Vac* = , \*

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 277

*Vac* 110V/60Hz 110V/60Hz *Pac* 546.5W 1145.3W *Vdc* 300.6V 300.3V *Pdc* 365.9W 791.2W

 66.95% 69.08% *THDi* 8.493% 7.085% *PF* (Lagging) 0.998 0.997

Table 5. Measured characteristics of the standard PMSM drive fed by standard boost SMR

100V 10A

4A

5ms

*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

\* ω

5ms

*<sup>r</sup>* = 2000rpm \*

ω

*<sup>r</sup>* = 3000rpm

*ac v*

*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω );

*<sup>r</sup>* = 3000rpm

*as <sup>i</sup>*′ \* *as i*

(b)

ω

*as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with

ω

*<sup>r</sup>* = 2000rpm \*

*Vac* 110V/60Hz 110V/60Hz *Pac* 543.9W 1142.4W *Vdc* 300.4V 300.1V *Pdc* 364.8W 790.3W

 67.07% 69.18% *THDi* 8.238% 7.022% *PF* (Lagging) 0.998 0.996

Table 6. Measured characteristics of the standard PMSM drive fed by bridgeless boost SMR

*ac i*

100V 20A

4A

5ms

5ms

\* ω


Table 4. Measured characteristics of the standard PMSM drive fed by diode rectifier frontend under two speeds ( 220V/60Hz *Vac* = , *RL* = 44.7Ω )

#### **5.4.2 Three boost SMR front-ends**

(i) Standard boost SMR: Fig. 17(a), Fig. 17(b) and Table 5; (ii) Bridgeless boost SMR: Fig. 18(a), Fig. 18(b) and Table 6; (iii) CFPP boost SMR: Fig. 19(a), Fig. 19(b) and Table 7. The results indicate that for all cases, the close winding current tracking performances are obtained, and thus good line drawn power quality characteristics are achieved.

Further observations find that: (i) the efficiencies of bridgeless SMR are slightly higher than those of standard boost SMR; (ii) the efficiencies of the CFPP SMR are lower than the other two SMRs. This is mainly due to the increased losses in the high-frequency transformer.

Fig. 20(a) and Fig. 20(b) show the measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( \* *qs i* , *qs i*′ ) and *Vdc* of the whole PMSM drive with CFPP boost SMR front-end at (*Vdc* = 300V ,ω*<sup>r</sup>* = 2400rpm, *RL* = 44.7Ω ) due to a step speed command change of 100rpm and due to a step load resistance change from *RL* = 75Ω to *RL* = 44.7Ω . The results indicate that good speed tracking and regulating responses are obtained by the developed SMR-fed PMSM drive. And the DC-link voltages *Vdc* are well regulated under these two cases.

Fig. 17. Measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( *HA* , \* *as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with standard boost SMR front-end at: (a) ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ); (b): ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

*Vac* 220V/60Hz 220V/60Hz *Pac* 527.5W 969.4W *Vdc* 295.9V 278.4V *Pdc* 366.7W 706.3W

 69.52% 72.86% *THDi* 72.95% 65.54% *PF* (Lagging) 0.751 0.758

Table 4. Measured characteristics of the standard PMSM drive fed by diode rectifier front-

(i) Standard boost SMR: Fig. 17(a), Fig. 17(b) and Table 5; (ii) Bridgeless boost SMR: Fig. 18(a), Fig. 18(b) and Table 6; (iii) CFPP boost SMR: Fig. 19(a), Fig. 19(b) and Table 7. The results indicate that for all cases, the close winding current tracking performances are

Further observations find that: (i) the efficiencies of bridgeless SMR are slightly higher than those of standard boost SMR; (ii) the efficiencies of the CFPP SMR are lower than the other two SMRs. This is mainly due to the increased losses in the high-frequency transformer.

> ω*r* ,ω*<sup>r</sup>* ), ( \*

step speed command change of 100rpm and due to a step load resistance change from *RL* = 75Ω to *RL* = 44.7Ω . The results indicate that good speed tracking and regulating responses are obtained by the developed SMR-fed PMSM drive. And the DC-link voltages

> 100V 10A

4A

5ms

5ms

ω

obtained, and thus good line drawn power quality characteristics are achieved.

*<sup>r</sup>* = 2000rpm \*

ω

*<sup>r</sup>* = 3000rpm

*qs i* , *qs i*′ ) and *Vdc* of the whole PMSM

*<sup>r</sup>* = 2400rpm, *RL* = 44.7Ω ) due to a

*ac v*

*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ); (b):

*as <sup>i</sup>*′ \* *as i*

(b)

*as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with

ω

*ac i*

100V 20A

4A

5ms

5ms

\* ω

Cases

end under two speeds ( 220V/60Hz *Vac* = , *RL* = 44.7Ω )

Fig. 20(a) and Fig. 20(b) show the measured ( \*

*Vdc* are well regulated under these two cases.

(a)

ω*r* ,ω

ω

Fig. 17. Measured ( \*

( 220V/60Hz *Vac* = , \*

*as <sup>i</sup>*′ \* *as i*

drive with CFPP boost SMR front-end at (*Vdc* = 300V ,

*ac v*

*ac i*

*<sup>r</sup>* ), ( *HA* , \*

standard boost SMR front-end at: (a) ( 220V/60Hz *Vac* = , \*

*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

Variables

η

**5.4.2 Three boost SMR front-ends** 


Table 5. Measured characteristics of the standard PMSM drive fed by standard boost SMR front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

Fig. 18. Measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( *HA* , \* *as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with bridgeless boost SMR front-end at: (a) ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ); (b): ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )


Table 6. Measured characteristics of the standard PMSM drive fed by bridgeless boost SMR front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

Some Basic Issues and Applications of

**6.1.1 System configuration** 

*Lf*

*Lf*

*vab ia*

> *ib ci*

\**vo*

A/D

A/D

2000 / 500 *C FV <sup>o</sup>* = μ

2 /(105 ) 0.253 *o o o o* Δ = *v V RC V* ω

*s K v v* 1+τ*vo*

*ia <sup>s</sup> K i i* 1+τ

+

\**vor \*vo*1 *w* (*s*) *<sup>v</sup>*

Robust voltage control scheme

> Notch filter *HNF* (*s*)

*Cf*

*vbn Lb*

*Cf*

*vo* ′

*<sup>v</sup>* <sup>Σ</sup> <sup>+</sup>

Robust error canceller

*Lb <sup>b</sup>*<sup>1</sup> *<sup>i</sup>*

*b*2 *i*

*b*3 *i*

*Lb*

*Cf*

*Lf*

*van*

*vcn n*

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 279

The applications of three types of single-phase SMRs as the AC-DC front-end converters of PMSM drives and their comparative evaluation have been introduced in the previous section. In this section, a SMR fed switched-reluctance motor (SRM), a SMR based electric vehicle battery charger and a flyback SMR based battery plug-in charger are presented to

Fig. 21 shows the power circuit and control scheme of a three-phase single-switch (3P1SW) fed SRM drive (Chai et al, 2010). The two power stages possess the following key features:

**6. Some specific applications of Switch-Mode Rectifier** 

**6.1 Switch-Mode Rectifier fed Switched-Reluctance Motor drive** 

*D*

*iD*

*S*

+

*<sup>d</sup> <sup>d</sup> i* , *p*

3P1SW SMR Front-end Switched reluctance motor drive

−

*Ro* = *Rd*

*Cd <sup>d</sup> o v v* =

*S*

*tri v*

*ih*

*wh* (*s*)

Fig. 21. A three-phase single-switch SMR fed drive and its control scheme

Threephase rectification

energy storage inductor is 15.459 (10 ) *L H kHz <sup>b</sup>* =

Feedback controller *Gcv* <sup>+</sup> − Σ ε

*H* (*s*) *LF vc* LPF

*ah i*

*<sup>e</sup>*−1/180*<sup>s</sup> bh <sup>i</sup> ch i*

*/ s e*−1 90

*c*1 *v*

− <sup>+</sup> <sup>Σ</sup> *vc ch v*

PWM modulator

*DA*

ω*r* <sup>∗</sup> <sup>∑</sup> <sup>+</sup> − ' ω*r*

a. SRM drive: The SRM drive is manufactured by TASC Drives Ltd., which is rated as 4 phase, 8/6 pole, 400V, 1500rpm, 4kW. Its windings are excited by a 2(n+1) Miller's converter from the SMR established DC-link voltage. The lower switches *S*1 to *S*4 are in charge of commutation, and the upper switches *SA* (phase windings 1 and 3) and *SB*

b. 3P1SW SMR: The ratings of the 3P1SW SMR are: (1) AC input: three-phase, *VL* = 220 ± 10%*Vrms* , 60Hz; (2) DC output: 400V, *V V o d* = = 4 ( 40 ) *P kW R o o* = =Ω . The

μ

DSP

Robust current harmonic compensation scheme

(phase windings 2 and 4) are used for performing PWM switching control.

= . Input filter: 3.3 F *Cf* =

*W*1

*i* 1

εω

SRM drive control scheme

> Speed control scheme

*SA*

*D*<sup>1</sup> *D*<sup>3</sup> *D*<sup>2</sup>

*S*<sup>1</sup> *S*<sup>3</sup> *S*<sup>2</sup> *S*<sup>4</sup> *DB*

*HB HA*

Commutation logic generator

*S*1 *S*2 *S*3 *S*4

Phase winding current command generator

(Commutation tuning)

*i*<sup>2</sup> *i*3 *i*<sup>4</sup>

*W*<sup>2</sup> *W*<sup>3</sup> *W*<sup>4</sup>

*RL*

EC PMSG

*S A SB*

*SA SB*

Randomband HCC PWM schemes

*A*/ *D*

*i* <sup>1</sup> ~ *i*<sup>4</sup> ′ ′

Encorder

μ*H* .

*HB H A ECA*,*B*

ω*r*

SRM

*SB D*4

*i* <sup>1</sup> <sup>~</sup> *<sup>i</sup>*<sup>4</sup> ′ ′ *cI*

interface *d* / *dt*

. The output filtering capacitor is

and *Lf* = 123.679

with the corresponding peak-to-peak DC output voltage ripple:

μ

PIO

*<sup>S</sup>*<sup>1</sup> *<sup>S</sup>*<sup>2</sup> *<sup>S</sup>*<sup>3</sup> *<sup>S</sup>*<sup>4</sup> <sup>1</sup> *<sup>S</sup>*<sup>2</sup> *<sup>S</sup>*<sup>3</sup> *<sup>S</sup>*<sup>4</sup> *<sup>S</sup>*

θ *<sup>r</sup> Nos* θ*on* θ*ff* , ,

\* <sup>4</sup> \* 1 *i* ~ *i*

> θ*r*

*S*<sup>1</sup> *S*<sup>2</sup> *S*<sup>3</sup> *S*<sup>4</sup>

*H AH <sup>B</sup>*

Hall signals

Isolated gate drivers

further comprehend the advantages of using SMR.

Fig. 19. Measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( *HA* , \* *as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with current-fed push-pull SMR front-end at: (a) ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω ); (b): ( 220V/60Hz *Vac* = , \* ω*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )


Table 7. Measured characteristics of the standard PMSM drive fed by current-fed push-pull boost SMR front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

Fig. 20. Measured ( \* ω*r* ,ω*<sup>r</sup>* ), ( \* *qs i* , *qs i*′ ) and *Vdc* of the whole PMSM drive with current-fed push-pull boost SMR front-end at (*Vdc* = 300V , \* ω*<sup>r</sup>* = 2400rpm , *RL* = 44.7Ω ): (a) due to a step speed command change of 100rpm: (b) due to a step resistive load change from *RL* = 75Ω to *RL* = 44.7Ω

\* *as i as i*′

*as i* , *as i*′ ) and ( *ac v* , *ac i* ) of the standard PMSM drive with

ω

ω

*<sup>r</sup>* = 3000rpm

200ms

50ms

500ms

*<sup>r</sup>* = 2400rpm , *RL* = 44.7Ω ): (a) due to a step

50rpm

1A

10V

*ac v ac i* 4A

100V 20A

5ms

5ms

*<sup>r</sup>* = 2000rpm , *RL* = 44.7Ω );

4A

100V 10A

(a) (b)

*<sup>r</sup>* = 2000rpm \*

*Vac* 110V/60Hz 110V/60Hz *Pac* 597.8W 1231.8W *Vdc* 301.2V 300.7V *Pdc* 365.3W 792.1W

 61.10% 64.30% *THDi* 3.90% 4.02% *PF* (Lagging) 0.998 0.998

Table 7. Measured characteristics of the standard PMSM drive fed by current-fed push-pull

2400rpm

ω*r*

(b)

*qs i* , *qs i*′ ) and *Vdc* of the whole PMSM drive with current-fed

\* *qs i qs i*′

300V *Vdc*

ω

speed command change of 100rpm: (b) due to a step resistive load change from *RL* = 75Ω to

10ms

20ms

100ms

2A

10V

5ms

5ms

*<sup>r</sup>* = 3000rpm , *RL* = 44.7Ω )

\* ω

\* *as <sup>i</sup> as <sup>i</sup>*′

Fig. 19. Measured ( \*

(b): ( 220V/60Hz *Vac* = , \*

Variables

η

\* ω*r*

> \* *qs i qs i*′

*Vdc*

ω*r* ,ω*<sup>r</sup>* ), ( \*

push-pull boost SMR front-end at (*Vdc* = 300V , \*

ω*r*

300V

Fig. 20. Measured ( \*

*RL* = 44.7Ω

ω*r* ,ω

ω

Cases

*ac v ac i*

*<sup>r</sup>* ), ( *HA* , \*

current-fed push-pull SMR front-end at: (a) ( 220V/60Hz *Vac* = , \*

boost SMR front-end under two speeds (*Vdc* = 300V , *RL* = 44.7Ω )

2400rpm 50rpm

(a)
