**3.3.2 Modified three-phase single-switch ZCT SMR**

In the modified 3P1SW ZCT SMR presented in (Das & Moschopoulos, 2007). The addition of the transformer in the auxiliary circuit let the circulating energy from the auxiliary circuit be transferred to the output. Hence it possesses higher efficiency than the classical type.

#### **3.3.3 Three-phase three-switch bridgeless ZCT SMR**

As to the three-phase bridgeless ZCT SMR (Mahdavi & Farzanehfard, 2009), the auxiliary circuit provides soft-switching condition through ZCT approach for all semiconductor devices without any extra current and voltage stress.

Some Basic Issues and Applications of

*d*

**4.2 Three-phase SMRs** 

2

*m*

2

*m*

3 2

has *P P o d* = , i.e.,

=

2

*m*

*V*

*ac an a bn b cn c*

*e*

+

 π

 π

<sup>2</sup> <sup>3</sup> cos6 35 *m*

*<sup>V</sup> tP p R R* − Δ+ ω

*R*

ω

ω

*e*

*R*

*e e*

where *Pac* = average AC power, *ac*

*van*

*vcn*

+

*n*

*a b v*

+ <sup>+</sup> *Re*

*b*

*c*

*a*

+

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 261

 ω 2 *d d d <sup>V</sup> <sup>t</sup> C R*

ω

Δ = (6)

 ωπ

(7)

 ωπ

ω

<sup>=</sup> (5)

2 *ac ac*

*d*

*v*

ω

ω*C R*

For a well-regulated three-phase single-switch (3P1SW) DCM SMR shown in Fig. 5, it can be regarded as a loss-free emulated resistor *Re* viewing from the phase AC source with line drawn current having dominant 5th and 7th harmonics (Chai et al, 2010). Hence, the three-

sin( 2 / 3) <sup>1</sup> 1 [sin( 2 / 3) sin 5( 2 / 3) sin7( 2 / 3)] 5 7

*V t ttt*

*V t ttt*

sin( 2 /3) <sup>1</sup> 1 [sin( 2 / 3) sin 5( 2 / 3) sin7( 2 / 3)] 5 7

2 2 3

*ac* = *PP <sup>d</sup>* = *PP od*

*m d*

*e d*

Control *<sup>d</sup>* scheme *v td* )(

2

*V V <sup>P</sup>*

*ac*

*b*1 *i*

*b*2 *i*

*b*3 *i*

*Lb*

*d*

*d d V*

sin 1 1 [sin sin 5 sin7 ] 5 7

 ωπ

<sup>−</sup> −− −− − +

 ωπ

ωωω

+− +− +

*p* = ripple AC power. By neglecting all power losses, one

*D*

*S*

*R R* = = (8)

*<sup>D</sup>* Load *i*

+

− *Cd <sup>d</sup> Rd v*

Δ=− = <sup>1</sup> sin2

Then the voltage ripple ( ) *<sup>d</sup>* Δ*v t* can be found by integrating the above equation:

2 2 1 1 ( ) cos2 sin2

*d ed dd e V V v t tdt <sup>t</sup> C RV CV R* ω

phase line drawn instantaneous power can be approximately expressed as:

*V t p vi vi vi ttt R*

ω

=++= − − +

*e*

ωπ

ωπ

δ

*Lf*

*i*

*b i*

*c i*

*Cf*

*vbn Lb*

*f C*

*Lb <sup>a</sup>*

*Cf*

*f L*

*Lf*

Fig. 5. Conceptual configuration of a three-phase DCM SMR

*ac ac*

 δ

2

*m*

From (5) one can get the peak to peak value of output ripple voltage:

**4.2.1 Three-Phase Single-Switch (3P1SW) SMR** 

#### **4. Operation principle and some key issues of SMR**

#### **4.1 Single-phase SMRs**

Fig. 4 shows the conceptual configuration of a single-phase SMR. The AC source input voltage is expressed as *ac m* sin 2 sin *ac vV t V t* = = ω ω . If the AC input current *ac i* can be regulated to be sinusoidal and kept in phase with *ac v* , then the ideal SMR is similar to an emulated resistor with the effective resistance of *Re* viewing from the utility grid. In reality, the double line frequency output voltage ripple always exists for an actual SMR with finite value of output filtering capacitor. This ripple may contaminate to distort the current command, and hence to worsen the power quality control performance. The output power *p*( )*t* of the SMR shown in Fig. 4 can be expressed as:

$$\begin{split} p(t) &= P\_{ac} = \frac{V\_m^2}{R\_c} \sin^2 \alpha t = \frac{V\_m^2}{2R\_c} (1 - \cos 2\alpha t) = \frac{V\_{ac}^2}{R\_c} - \frac{V\_{ac}^2}{R\_c} \cos 2\alpha t \\ &= \frac{V\_d^2}{R\_d} - \frac{V\_{ac}^2}{R\_c} \cos 2\alpha t \stackrel{\Delta}{=} P\_d + P\_{ac2} \end{split} \tag{1}$$

where *Pd* and *Pac*2 respectively denote the output DC and the double-frequency power components. From the average power invariant property in (1), one can obtain the following equivalent resistance transfer relationship:

Fig. 4. Conceptual configuration of a single-phase SMR

$$\frac{V\_d}{V\_{ac}} = \sqrt{\frac{R\_d}{R\_c}}\tag{2}$$

By neglecting the capacitor ESR *cr* in Fig. 4, the current ( ) *di t* can be found from (1):

$$i\_d(t) \equiv \frac{p(t)}{V\_d} = \frac{V\_{ac}^2}{R\_c V\_d} (1 - \cos 2\alpha t) = I\_d + i\_{d2} \tag{3}$$

The AC component *<sup>d</sup>*<sup>2</sup> *i* is approximately regarded flowing through the capacitor:

$$C\_d \frac{d\Delta\upsilon\_d(t)}{dt} = -\frac{V\_{ac}^2}{R\_c V\_d} \cos 2\alpha t \tag{4}$$

Then the voltage ripple ( ) *<sup>d</sup>* Δ*v t* can be found by integrating the above equation:

$$
\Delta v\_d(t) = \frac{1}{C\_d} \int -\frac{V\_{ac}^2}{R\_e V\_d} \cos 2\alpha t dt = \frac{1}{2\alpha C\_d V\_d} \frac{V\_{ac}^2}{R\_e} \sin 2\alpha t = \frac{V\_d}{2\alpha C\_d} \frac{1}{R\_d} \sin 2\alpha t \tag{5}
$$

From (5) one can get the peak to peak value of output ripple voltage:

$$
\Delta \mathbf{v}\_d = \frac{V\_d}{\text{ao } \mathbf{C}\_d R\_d} \tag{6}
$$

#### **4.2 Three-phase SMRs**

260 Electrical Generation and Distribution Systems and Power Quality Disturbances

Fig. 4 shows the conceptual configuration of a single-phase SMR. The AC source input

regulated to be sinusoidal and kept in phase with *ac v* , then the ideal SMR is similar to an emulated resistor with the effective resistance of *Re* viewing from the utility grid. In reality, the double line frequency output voltage ripple always exists for an actual SMR with finite value of output filtering capacitor. This ripple may contaminate to distort the current command, and hence to worsen the power quality control performance. The output power

22 2 2

*m m ac ac*

*V V V V p tP t t t R R R R*

*ee e e*

( ) sin (1 cos2 ) cos2 <sup>2</sup>

ωω

== = − = −

*d ac*

where *Pd* and *Pac*2 respectively denote the output DC and the double-frequency power components. From the average power invariant property in (1), one can obtain the following

2

DC/DC converter cell

> Control scheme

*d d ac e V R*

By neglecting the capacitor ESR *cr* in Fig. 4, the current ( ) *di t* can be found from (1): 2

( ) ( ) (1 cos2 ) *ac d d d*

*p t <sup>V</sup> i t tIi*

≅ = − =+

<sup>2</sup> ( ) cos2 *d ac*

*dv t V C t dt R V*

*e d*

ω

ω

*d ed*

The AC component *<sup>d</sup>*<sup>2</sup> *i* is approximately regarded flowing through the capacitor:

*V RV*

*d*

− *cr*

*Si Li Di*

= *PP dac* = *PP od*

 ω

. If the AC input current *ac i* can be

 ω

*p t*( )

*V R* <sup>=</sup> (2)

2

<sup>Δ</sup> = − (4)

*iD*

*Cd*

*Rd*

*id*

(1)

*vd* +

−

(3)

**4. Operation principle and some key issues of SMR** 

ω

2

*V V tPP*

= − Δ+

ω

+

*<sup>i</sup> ac* = *ii*

*<sup>i</sup>* = *vv ac*

*vac*

*iL*

*Re td* )(

*vd*

voltage is expressed as *ac m* sin 2 sin *ac vV t V t* = =

*p*( )*t* of the SMR shown in Fig. 4 can be expressed as:

*ac*

equivalent resistance transfer relationship:

*ac i*

*vac*

−

+

2 2

cos2

*d e*

*R R*

Fig. 4. Conceptual configuration of a single-phase SMR

*d ac*

**4.1 Single-phase SMRs** 

#### **4.2.1 Three-Phase Single-Switch (3P1SW) SMR**

For a well-regulated three-phase single-switch (3P1SW) DCM SMR shown in Fig. 5, it can be regarded as a loss-free emulated resistor *Re* viewing from the phase AC source with line drawn current having dominant 5th and 7th harmonics (Chai et al, 2010). Hence, the threephase line drawn instantaneous power can be approximately expressed as:

$$\begin{aligned} p\_{w} &= v\_{wi}\dot{i}\_{s} + v\_{hi}\dot{i}\_{b} + v\_{ci}\dot{i}\_{c} = \frac{V\_{i}^{2}\sin\alpha t}{R\_{\epsilon}}[\sin\alpha t - \frac{1}{5}\sin 5\alpha t - \frac{1}{7}\sin 7\alpha t] + \\ &\frac{V\_{w}^{2}\sin(\alpha t - 2\pi \ / \ 3)}{R\_{\epsilon}}[\sin(\alpha t - 2\pi \ / \ 3) - \frac{1}{5}\sin 5\left(\alpha t - 2\pi \ / \ 3\right) - \frac{1}{7}\sin 7\left(\alpha t - 2\pi \ / \ 3\right)] + \\ &\frac{V\_{w}^{2}\sin(\alpha t + 2\pi \ / \ 3)}{R\_{\epsilon}}[\sin(\alpha t + 2\pi \ / \ 3) - \frac{1}{5}\sin 5\left(\alpha t + 2\pi \ / \ 3\right) - \frac{1}{7}\sin 7\left(\alpha t + 2\pi \ / \ 3\right)] \\ &= \frac{3V\_{w}^{2}}{2R\_{\epsilon}} - \frac{3V\_{w}^{2}}{35R\_{\epsilon}}\cos 6\alpha t \stackrel{\Delta}{=} P\_{w} + \delta p\_{w}. \end{aligned} \tag{7}$$

where *Pac* = average AC power, *ac* δ *p* = ripple AC power. By neglecting all power losses, one has *P P o d* = , i.e.,

$$P\_{ac} = \frac{\Re V\_{w}^{2}}{2R\_{c}} = \frac{V\_{d}^{2}}{R\_{d}}\tag{8}$$

Fig. 5. Conceptual configuration of a three-phase DCM SMR

Then from (7) and (8), the AC charging current flowing the output filtering capacitor is:

$$C\_d \frac{dv\_d}{dt} = -\frac{2V\_d}{35R\_d} \cos 6\alpha t \tag{9}$$

Some Basic Issues and Applications of

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 263

Fig. 6. Key issues of a DSP-based single-phase standard boost SMR

AC input voltage: 110V 10% /60Hz *Vac* = ± .

type of SMR are made according to the given specifications.

ω

 π

Switching frequency: 25kHz *sf* = .

η

**5.1.2 Design of circuit components** 

Efficiency:

a. Boosting inductor

ω

current ripple is treated at 0.5

2 sin *ac ac vVt* Δ

The system variables and specifications of the established SMR are given as follows:

≥ 90% . Power factor: 0.95 *PF* ≥ (Lagging).

DC output: *Vdc* = 300V ~ 350V ( ≥ ×× = 110V 1.1 2 171V ), *Pdc* = 1500W .

The design of energy storage inductor, output filtering capacitor and power devices for this

Some assumptions are made in performing the inductor design: (i) continuous conduction mode (CCM); (ii) all constituted components are ideal; (iii) *v V dc dc* = = 350V ; (iv)

, ,min 110V 0.9 *Vac* = × <sup>=</sup> 99V , ,min ,min <sup>ˆ</sup>*V V ac* = = 2 140V *ac* ; (v) the inductor

*t* = , since at which the current ripple is maximum.

Thus one can derive the peak-to-peak output voltage ripple:

$$
\Delta v\_d = \frac{\Delta V\_d}{105 \,\mu \text{R}\_d \text{C}\_d} \tag{10}
$$

#### **4.2.2 Three-phase three-switch and six-switch SMRs**

For the Vienna SMR and three-phase six-switch standard SMR with ideal current mode control, the three-phase line drawn currents will be balanced without harmonics. Hence, from (7) one can find that the DC output voltage ripple will be nearly zero.

#### **4.3 Some key issues of SMR**

Taking the DSP-based single-phase standard boost SMR as an example, some key issues are indicated in Fig. 6. In power circuit, the ripples and ratings of the constituted components must be derived, and accordingly the components are properly designed and implemented. Some typical examples can be referred to (Li & Liaw, 2003; Chai & Liaw, 2007; Y.C. Chang & Liaw, 2009a; H.C. Chang & Liaw, 2009).

As to the control scheme, the sensed inductor current and output voltage should be filtered. The feedback controller must first be properly designed considring the desired perfromance and the effects of comtaiminated noises in sensed variables. For satisfying more strict control requirements, in addition to the basic feedback controls, the robust tracking error cancellation controls (Chai & Liaw, 2007; Y.C. Chang & Liaw, 2009a) can further be added. In making DSP-based digital control, the sampling rates are selected according to the achievable loop dynamic response. Other issues may include: (a) random switching to yield spread harmonic spectral distribution (Li & Liaw, 2004b; Chai & Liaw, 2008; Y.C. Chang & Liaw, 2011); (b) the effects of DC-link ripples on the motor drive operating performance (Chai & Liaw, 2007, 2009; Chai et al, 2010); (c) rating enlargement via parallel connection of transformers (Y.C. Chang & Liaw, 2009b) and SMR modules (Li & Liaw, 2004a).

#### **5. Comparative evaluation of three single-phase boost SMRs**

Three single-phase boost SMRs are comparatively evalued their prominences experimentally in serving as front-end AC/DC converters of a PMSM drive. For completeness, the traditional diode rectifier is also included as a reference.

#### **5.1 Standard single-phase boost SMR**

#### **5.1.1 System configuration**

The power circuit and control scheme of the developed SMR are shown in Fig. 6, wherein the two robust controllers are removed. This control system belongs to multi-loop configuration consisting of inner RC-CCPWM scheme and outer voltage loop. The low-pass filtering cut-off frequencies for the sensed current and voltage are respectively set as 12Hz *ci f* = and 600Hz *cv f* = . And the digital control sampling rates of the two loops are chosen as 25kHz *si s f f* = = and 2.5kHz *sv f* = .

*dv V C t dt R* = −

<sup>2</sup> cos6 35 *d d*

ω

(9)

Δ = (10)

*d*

2 105

ω*R C*

For the Vienna SMR and three-phase six-switch standard SMR with ideal current mode control, the three-phase line drawn currents will be balanced without harmonics. Hence,

Taking the DSP-based single-phase standard boost SMR as an example, some key issues are indicated in Fig. 6. In power circuit, the ripples and ratings of the constituted components must be derived, and accordingly the components are properly designed and implemented. Some typical examples can be referred to (Li & Liaw, 2003; Chai & Liaw, 2007; Y.C. Chang &

As to the control scheme, the sensed inductor current and output voltage should be filtered. The feedback controller must first be properly designed considring the desired perfromance and the effects of comtaiminated noises in sensed variables. For satisfying more strict control requirements, in addition to the basic feedback controls, the robust tracking error cancellation controls (Chai & Liaw, 2007; Y.C. Chang & Liaw, 2009a) can further be added. In making DSP-based digital control, the sampling rates are selected according to the achievable loop dynamic response. Other issues may include: (a) random switching to yield spread harmonic spectral distribution (Li & Liaw, 2004b; Chai & Liaw, 2008; Y.C. Chang & Liaw, 2011); (b) the effects of DC-link ripples on the motor drive operating performance (Chai & Liaw, 2007, 2009; Chai et al, 2010); (c) rating enlargement via parallel connection of

Three single-phase boost SMRs are comparatively evalued their prominences experimentally in serving as front-end AC/DC converters of a PMSM drive. For

The power circuit and control scheme of the developed SMR are shown in Fig. 6, wherein the two robust controllers are removed. This control system belongs to multi-loop configuration consisting of inner RC-CCPWM scheme and outer voltage loop. The low-pass filtering cut-off frequencies for the sensed current and voltage are respectively set as 12Hz *ci f* = and 600Hz *cv f* = . And the digital control sampling rates of the two loops are

transformers (Y.C. Chang & Liaw, 2009b) and SMR modules (Li & Liaw, 2004a).

**5. Comparative evaluation of three single-phase boost SMRs** 

completeness, the traditional diode rectifier is also included as a reference.

*d*

*V*

*d d*

Then from (7) and (8), the AC charging current flowing the output filtering capacitor is:

*d*

*v*

from (7) one can find that the DC output voltage ripple will be nearly zero.

*d*

Thus one can derive the peak-to-peak output voltage ripple:

**4.2.2 Three-phase three-switch and six-switch SMRs** 

**4.3 Some key issues of SMR** 

Liaw, 2009a; H.C. Chang & Liaw, 2009).

**5.1 Standard single-phase boost SMR** 

chosen as 25kHz *si s f f* = = and 2.5kHz *sv f* = .

**5.1.1 System configuration** 

Fig. 6. Key issues of a DSP-based single-phase standard boost SMR

The system variables and specifications of the established SMR are given as follows: AC input voltage: 110V 10% /60Hz *Vac* = ± . DC output: *Vdc* = 300V ~ 350V ( ≥ ×× = 110V 1.1 2 171V ), *Pdc* = 1500W .

Switching frequency: 25kHz *sf* = . Efficiency: η≥ 90% . Power factor: 0.95 *PF* ≥ (Lagging).

#### **5.1.2 Design of circuit components**

The design of energy storage inductor, output filtering capacitor and power devices for this type of SMR are made according to the given specifications.

a. Boosting inductor

Some assumptions are made in performing the inductor design: (i) continuous conduction mode (CCM); (ii) all constituted components are ideal; (iii) *v V dc dc* = = 350V ; (iv) 2 sin *ac ac vVt* Δ ω , ,min 110V 0.9 *Vac* = × <sup>=</sup> 99V , ,min ,min <sup>ˆ</sup>*V V ac* = = 2 140V *ac* ; (v) the inductor current ripple is treated at 0.5 ω π*t* = , since at which the current ripple is maximum.

Some Basic Issues and Applications of

4.0 *KPi* = is set.

gain ' ( ) ( )/ ( ) *LG s j i s s* = Δ ω

scheme. Hence finally,

to determine the integral gain.

 ε*L is*= *j*

ω

Fig. 7. System configuration in current loop gain measurement

20.0

0

Magnitude (dB)


Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 265

*dc ac cont tri*

The parameters of the developed SMR shown in Fig. 6 are set as: *Vdc* = 300V , *Ki* = 0.04V/A , 25kHz *sf* = , *L* = 4.14mH and 25kV/sec *tri dv dt* = . Using the given data, the upper value of the *KPi* can be found from (17) to be 8.625 *K K Pi Pi* < = ( 0 *ac v* = is set here). Accordingly

In making the determination of integral gain, the magnitude frequency response of the loop

as shown in Fig. 7, wherein *Vinj* denotes an injected swept sine signal. Fig. 8 shows the measured magnitude frequency response of the loop gain. The measurement conditions are set as: (i) , *vinj peak* = 10mV ; (ii) swept sine frequency range is from 400Hz to 11kHz; (iii) the

200 *RL* = Ω ; (v) rms *vac* = 110V ; (vi) the current feedback controllers are set as 4 *KPi* = and 45000 *KIi* = . The measured result in Fig. 8 indicates that the crossover frequency is 1.47kHz / 2 *c s f f* = < , which is reasonable for a ramp-comparison current-controlled PWM

<sup>45000</sup> ( ) <sup>4</sup> *Ii*

If the measurement of loop-gain frequency response is not convenient, one can also use the derived small-signal dynamic model (Chai & Liaw, 2007), or using trail-and-error approach

400Hz 11kHz

Frequency (Hz)

1.47kHz

1kHz

Fig. 8. Measured magnitude frequency response of current loop gain

*s s*

voltage loop is opened, and the current command is set as \* <sup>ˆ</sup> *L L ac II v* = × with <sup>ˆ</sup>

*ci Pi <sup>K</sup> Gs K*

<sup>−</sup> = < (17)

is measured using the HP 3563A control systems analyzer

= + =+ (18)

*IL* = 8A ; (iv)

*Pi i dv V v dv K K dt L dt*

The maximum inductor current occurred at 0.5 ω π*t* = can be calculated as

$$\left(\hat{\mathbf{i}}\_{\perp}\right)\_{\text{max}} = \frac{P\_{\text{dc}}}{\hat{V}\_{\text{ac,min}}\eta} \times 2 = \frac{1500}{110 \times \sqrt{2} \times 0.9 \times 0.9} \times 2 = 23.81 \text{A} \tag{11}$$

Let the inductor current ripple be:

$$
\Delta i\_L = \frac{\hat{V}\_{\text{ac,min}} DT\_s}{L} \le 0.1 \left(\hat{l}\_L\right)\_{\text{max}} = 2.38 \,\text{A} \tag{12}
$$

The instantaneous duty ratio at 0.5 ω π*t* = can be found as:

$$D = \frac{V\_{dc} - \hat{V}\_{ac,\text{min}}}{V\_{dc}} = \frac{350 - 140}{350} = 0.6\tag{13}$$

Hence from (12) and (13), the condition of boosting inductance *L* is obtained as:

$$L \geq \frac{\hat{V}\_{\rm ac, min} D}{f\_s \Delta i\_L} = 1.41 \,\text{mH} \tag{14}$$

The inductor *L* is formed by serially connected two available inductors *L*1 and *L*<sup>2</sup> . The measured inductances using HIOKI 3532-50 LCR meter are *L*<sup>1</sup> = (2.03mH, ESR = 210m Ω at 60Hz, and 1.978mH, ESR= 5.68 Ω at 25kHz) and *L*<sup>2</sup> = (2.11mH, ESR= 196m Ω at 60Hz, and 1.92mH, ESR= 62 Ω at 25kHz). Hence *LL L* = +1 2 =4.14mH, which is suited here.

#### b. Output capacitor

By choosing the output filtering capacitor *Cd* = 2200 F/450V μ , the peak-to-peak output voltage ripple can be found as:

$$
\Delta V\_{dc} = \frac{V\_{dc}}{\alpha \text{q} \, R\_L \, \text{C}\_d} = \frac{P\_{dc}}{\alpha \text{q} \, \text{C}\_d V\_{dc}} = \frac{1500}{2\pi \times 60 \times 2200 \times 10^{-6} \times 350} = 5.17 \, \text{V} \tag{15}
$$

#### c. Power semiconductor devices

The maximum current of the main switch S and the diode D is max ˆ( ) 0.5 25A *L L i i* + Δ= , which is calculated from (11) and (12), and their maximum voltage is 350V. Accordingly, the MOSFET IXFK44N80P (IXYS) (800V, ID= 44A (continuous), IDM = 100A (pulsed)) and the fast diode DSEP60-06A (IXYS) (600V, average current IFAVM = 60A) are chosen for implementing the main switch S and all diodes respectively.

#### **5.1.3 Control schemes**

*Current controller:*  he current feedback controller ( ) *G s ci* in Fig. 6 is chosen to be PI-type:

$$\mathcal{G}\_{cl}(\mathbf{s}) = \mathcal{K}\_{N} + \frac{\mathcal{K}\_{N}}{\mathbf{s}} \tag{16}$$

The upper limit of the P-gain is first determined based on large-signal stability at switching frequency:

ω

<sup>1500</sup> ˆ( ) <sup>2</sup> 2 23.81A <sup>ˆ</sup> 110 2 0.9 0.9

= ×= × =

 π

max

×××

<sup>ˆ</sup> <sup>ˆ</sup> 0.1( ) 2.38A *ac s*

,min <sup>ˆ</sup> 350 140 0.6 350

1.41mH *ac*

μ

2 60 2200 10 350

*RC CV* <sup>−</sup> Δ= = = <sup>=</sup> ×× × × (15)

6

<sup>1500</sup> 5.17V

= + (16)

The inductor *L* is formed by serially connected two available inductors *L*1 and *L*<sup>2</sup> . The measured inductances using HIOKI 3532-50 LCR meter are *L*<sup>1</sup> = (2.03mH, ESR = 210m Ω at 60Hz, and 1.978mH, ESR= 5.68 Ω at 25kHz) and *L*<sup>2</sup> = (2.11mH, ESR= 196m Ω at 60Hz, and

*t* = can be found as:

*t* = can be calculated as

Δ= ≤ = (12)

<sup>−</sup> <sup>−</sup> = == (13)

Δ (14)

, the peak-to-peak output

(11)

The maximum inductor current occurred at 0.5

*<sup>P</sup> <sup>i</sup> V*

max

*L*

Let the inductor current ripple be:

b. Output capacitor

voltage ripple can be found as:

*dc*

c. Power semiconductor devices

**5.1.3 Control schemes**  *Current controller:* 

frequency:

The instantaneous duty ratio at 0.5

,min

ω

*D*

η

,min

*L L V DT i i L*

> π

*dc ac dc*

*V*

Hence from (12) and (13), the condition of boosting inductance *L* is obtained as:

1.92mH, ESR= 62 Ω at 25kHz). Hence *LL L* = +1 2 =4.14mH, which is suited here.

,min <sup>ˆ</sup>

*s L V D*

> π

The maximum current of the main switch S and the diode D is max ˆ( ) 0.5 25A *L L i i* + Δ= , which is calculated from (11) and (12), and their maximum voltage is 350V. Accordingly, the MOSFET IXFK44N80P (IXYS) (800V, ID= 44A (continuous), IDM = 100A (pulsed)) and the fast diode DSEP60-06A (IXYS) (600V, average current IFAVM = 60A) are chosen for

> ( ) *Ii ci Pi <sup>K</sup> Gs K*

The upper limit of the P-gain is first determined based on large-signal stability at switching

*s*

*f i* ≥ =

*V V*

*L*

By choosing the output filtering capacitor *Cd* = 2200 F/450V

*dc dc*

*L d d dc*

1 1

implementing the main switch S and all diodes respectively.

he current feedback controller ( ) *G s ci* in Fig. 6 is chosen to be PI-type:

*V P <sup>V</sup>* ωω

*ac*

*dc*

$$\frac{d\upsilon\_{\rm out}}{dt} = K\_{p\dot{q}} K\_i \frac{\left\| V\_{dc} - \left| \upsilon\_{ac} \right| \right\|}{L} < \frac{d\upsilon\_{\rm tri}}{dt} \tag{17}$$

The parameters of the developed SMR shown in Fig. 6 are set as: *Vdc* = 300V , *Ki* = 0.04V/A , 25kHz *sf* = , *L* = 4.14mH and 25kV/sec *tri dv dt* = . Using the given data, the upper value of the *KPi* can be found from (17) to be 8.625 *K K Pi Pi* < = ( 0 *ac v* = is set here). Accordingly 4.0 *KPi* = is set.

In making the determination of integral gain, the magnitude frequency response of the loop gain ' ( ) ( )/ ( ) *LG s j i s s* = Δ ω ε *L is*= *j*ω is measured using the HP 3563A control systems analyzer as shown in Fig. 7, wherein *Vinj* denotes an injected swept sine signal. Fig. 8 shows the measured magnitude frequency response of the loop gain. The measurement conditions are set as: (i) , *vinj peak* = 10mV ; (ii) swept sine frequency range is from 400Hz to 11kHz; (iii) the voltage loop is opened, and the current command is set as \* <sup>ˆ</sup> *L L ac II v* = × with <sup>ˆ</sup> *IL* = 8A ; (iv) 200 *RL* = Ω ; (v) rms *vac* = 110V ; (vi) the current feedback controllers are set as 4 *KPi* = and 45000 *KIi* = . The measured result in Fig. 8 indicates that the crossover frequency is 1.47kHz / 2 *c s f f* = < , which is reasonable for a ramp-comparison current-controlled PWM scheme. Hence finally,

$$\mathcal{G}\_{cl}(\mathbf{s}) = K\_{p\_l} + \frac{K\_{li}}{s} = \mathbf{4} + \frac{\mathbf{4}5000}{s} \tag{18}$$

If the measurement of loop-gain frequency response is not convenient, one can also use the derived small-signal dynamic model (Chai & Liaw, 2007), or using trail-and-error approach to determine the integral gain.

Fig. 7. System configuration in current loop gain measurement

Fig. 8. Measured magnitude frequency response of current loop gain

*Voltage controller:* 

Although the quantitative controller design can be achieved (Y.C. Chang & Liaw, 2009a), the PI voltage feedback controller is chosen trial-and-error here to be:

$$\mathcal{L}\_{cv}(\mathbf{s}) = K\_{p\_{\mathcal{V}}} + \frac{K\_{lv}}{\mathbf{s}} = \mathbf{8} + \frac{\mathbf{200}}{\mathbf{s}} \tag{19}$$

Some Basic Issues and Applications of

**5.2 Bridgeless boost SMR 5.2.1 System configuration** 

**5.2.2 Circuit design** 

**5.2.3 Control schemes** 

**5.2.4 Experimental results** 

2 lists the measured efficiencies

Finally:

Switch-Mode Rectifiers on Motor Drives and Electric Vehicle Chargers 267

Fig. 10 shows the bridgeless boost SMR, its control scheme is identical to those shown in Fig. 6 with the two switches being respectively operated in positive and negative half cycles. Although the efficiency of bridgeless SMR can be slightly increased, it possesses the common mode EMI problem due to the large parasitic capacitance between the output and ground, which provides a relatively low impedance path. To reduce this problem, the boosting

The specifications are identical to those listed above. The two inductors *L*1 and *L*2 in Sec.

*Current controller:* Following the similar process introduced in Sec. 5.1.3 one can get 8.625 *K K Pi Pi* < = . Hence, 3.0 *KPi* = is set and the integral gain is chosen via trial-and-error.

<sup>2000</sup> ( ) <sup>3</sup> *Ii*

<sup>200</sup> ( ) <sup>8</sup> *Iv*

The measured key waveforms are almost identical to Fig. 9 and are not repeated here. Table

The power circuit and control scheme of the CFPP isolated boost SMR are shown in Figs. 11(a) and 11(b). In making the analysis, some assumptions are made: (i) all circuit

*s s*

*s s*

*Vdc Cdc RL*

= + =+ (20)

= + =+ (21)

, *THDi* of *ac i* and PF at two loads. From Tables 1 and 2

*Pdc*

inductor is divided into two equal inductors, and they are placed at AC source side.

5.1.2 are used here as the two bridgeless boost SMR inductors, i.e., 1 2 *LL L* = = 0.5 .

<sup>1</sup> *S* <sup>2</sup> *S*

Fig. 10. Schematic and control scheme of the developed bridgeless boost SMR

*ci Pi <sup>K</sup> Gs K*

*cv Pv <sup>K</sup> Gs K*

one can find the slight higher efficiencies being yielded by the bridgeless SMR.

*Voltage controller:* The PI voltage feedback controller is chosen to be:

η

**5.3 Current-Fed Push-Pull (CFPP) isolated boost SMR** 

**5.3.1 System configuration and operation** 

*iac*

*Pac*

*iL* 0.5*<sup>L</sup>*

0.5*L*

*ac v*

#### **5.1.4 Experimental results**

Let *Vac* =110 V /60Hz and *Vdc* = 300V , the measured efficiencies η , *THDi* of *ac i* and PF at ( *RL* = 400Ω , *Pdc* =227.7W ) and ( *RL* = 200Ω , *Pdc* =473.6W ) are summarized in Table 1. And the measured ( \* *Li* , *Li*′ ) and ( *ac v* , *ac i* ) under ( *RL* = 200Ω , *Pdc* =473.6W ) are shown in Figs. 9(a) and 9(b). The results indicate that the input current *ac i* is nearly sinusoidal and kept almost in phase with the utility voltage *ac v* . Good line drawn power quality can also be observed from Table 1.


Table 1. Measured steady-state characteristics of the standard boost SMR under two loads

Fig. 9. Measured results of the standard boost SMR at *RL* = 200Ω : (a) ( \* *Li* , *Li*′ ); (b) ( *ac v* , *ac i* )
