**5.2 Bridgeless boost SMR**

266 Electrical Generation and Distribution Systems and Power Quality Disturbances

Although the quantitative controller design can be achieved (Y.C. Chang & Liaw, 2009a), the

<sup>200</sup> ( ) <sup>8</sup> *Iv*

( *RL* = 400Ω , *Pdc* =227.7W ) and ( *RL* = 200Ω , *Pdc* =473.6W ) are summarized in Table 1. And

and 9(b). The results indicate that the input current *ac i* is nearly sinusoidal and kept almost in phase with the utility voltage *ac v* . Good line drawn power quality can also be observed

> Resistive load ( *RL* = 400Ω )

*Vac* 110V/60Hz 110V/60Hz *Pac* 241.6W 502.2W *Vdc* 300.8V 300.2V *Pdc* 227.7W 473.6W

 94.25% 94.31% *THDi* 6.61% 6.11% *PF* (Lagging) 0.992 0.994 Table 1. Measured steady-state characteristics of the standard boost SMR under two loads

*s s*

*Li* , *Li*′ ) and ( *ac v* , *ac i* ) under ( *RL* = 200Ω , *Pdc* =473.6W ) are shown in Figs. 9(a)

= + =+ (19)

η

Resistive load ( *RL* = 200Ω )

100V

*Li* , *Li*′ ); (b) ( *ac v* , *ac i* )

6.25A

*ac* 20A *i*

1ms

5ms

*ac v*

(a)

(b)

Fig. 9. Measured results of the standard boost SMR at *RL* = 200Ω : (a) ( \*

, *THDi* of *ac i* and PF at

PI voltage feedback controller is chosen trial-and-error here to be:

Let *Vac* =110 V /60Hz and *Vdc* = 300V , the measured efficiencies

Load cases

*Li*′ \*

*Li*

*cv Pv <sup>K</sup> Gs K*

*Voltage controller:* 

the measured ( \*

from Table 1.

Variables

η

**5.1.4 Experimental results** 

#### **5.2.1 System configuration**

Fig. 10 shows the bridgeless boost SMR, its control scheme is identical to those shown in Fig. 6 with the two switches being respectively operated in positive and negative half cycles. Although the efficiency of bridgeless SMR can be slightly increased, it possesses the common mode EMI problem due to the large parasitic capacitance between the output and ground, which provides a relatively low impedance path. To reduce this problem, the boosting inductor is divided into two equal inductors, and they are placed at AC source side.

### **5.2.2 Circuit design**

The specifications are identical to those listed above. The two inductors *L*1 and *L*2 in Sec. 5.1.2 are used here as the two bridgeless boost SMR inductors, i.e., 1 2 *LL L* = = 0.5 .

Fig. 10. Schematic and control scheme of the developed bridgeless boost SMR

#### **5.2.3 Control schemes**

*Current controller:* Following the similar process introduced in Sec. 5.1.3 one can get 8.625 *K K Pi Pi* < = . Hence, 3.0 *KPi* = is set and the integral gain is chosen via trial-and-error. Finally:

$$\mathcal{G}\_{cl}(\mathbf{s}) = \mathcal{K}\_{P\mathbf{i}} + \frac{\mathcal{K}\_{li}}{s} = \mathbf{3} + \frac{\mathbf{2000}}{s} \tag{20}$$

*Voltage controller:* The PI voltage feedback controller is chosen to be:

$$\mathcal{L}\_{cv}(s) = K\_{p\_{\mathcal{V}}} + \frac{K\_{lv}}{s} = 8 + \frac{200}{s} \tag{21}$$

#### **5.2.4 Experimental results**

The measured key waveforms are almost identical to Fig. 9 and are not repeated here. Table 2 lists the measured efficiencies η , *THDi* of *ac i* and PF at two loads. From Tables 1 and 2 one can find the slight higher efficiencies being yielded by the bridgeless SMR.
