**3. Properties of the CRC**

In this section, we give two properties of the CRC. These properties are useful in the CRC implementation. Before giving these properties, we define some variables. Let *A x*ð Þ and *B x*ð Þ be the polynomials. Let *g x*ð Þ be the cyclic generator polynomial. CRC*g x*ð Þ½ � *A x*ð Þ is defined as the remainder when *A x*ð Þ is divided by *g x*ð Þ. The two properties are listed as follows.

**Property 1**.

$$\mathbf{CRC}\_{\mathbf{g}(\mathbf{x})}[A(\mathbf{x})B(\mathbf{x})] = \mathbf{CRC}\_{\mathbf{g}(\mathbf{x})} \left[ \mathbf{CRC}\_{\mathbf{g}(\mathbf{x})}[A(\mathbf{x})] \mathbf{CRC}\_{\mathbf{g}(\mathbf{x})}[B(\mathbf{x})] \right] \tag{8}$$

Property 1 implies that CRC*g x*ð Þ½ � *A x*ð Þ*B x*ð Þ can be obtained by computing the CRC of *A x*ð Þ and *B x*ð Þ independently.

*Moving Broadband Mobile Communications Forward - Intelligent Technologies for 5G…*

#### **Property 2.**

$$\text{CRC}\_{\mathbf{g}(\mathbf{x})}[A(\mathbf{x}) + B(\mathbf{x})] = \text{CRC}\_{\mathbf{g}(\mathbf{x})}[A(\mathbf{x})] + \text{CRC}\_{\mathbf{g}(\mathbf{x})}[B(\mathbf{x})].\tag{9}$$

Property 2 implies that CRC*g x*ð Þ½ � *A x*ð Þþ *B x*ð Þ can be obtained by computing the CRC of *A x*ð Þ and *B x*ð Þ independently.

The proof of the property 1 and the property 2 can be found in Refs. [10, 11]. It is omitted for brevity. *g x*ð Þ in the expression of CRC*g x*ð Þ½ � *A x*ð Þ is clear from the context. As a consequence, *g x*ð Þ in the expression of CRC*g x*ð Þ½ � *A x*ð Þ is omitted in the following.

## **4. Overview of the CRC implementation**

In this section, we give an overview of the CRC implementation. In the following, the received transport block after the hard decision *e* is used as an example. The implementation is easily generalized to other cases.

#### **4.1 CRC implementation by direct calculation**

In this scheme, the CRC of *e* is directly calculated by the division of polynomial using modulo-2 arithmetic.

**Figure 2** illustrates an example. The dividend is equal to *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>4</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 and the divisor is equal to *<sup>x</sup>*<sup>2</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1. The division of polynomial begins by putting *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>4</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> below *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*4. Subtracting and bringing down the next term give us the intermediate variable *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>*. This process is repeated until the degree of the intermediate variable is less than 2. Finally, we obtain that the quotient is equal to *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 and the remainder is equal to *<sup>x</sup>*. That is,

$$\text{CRC}\left[\mathbf{x}^{\text{S}} + \mathbf{x}^{\text{A}} + \mathbf{x} + \mathbf{1}\right] = \mathbf{x} \tag{10}$$

processed on every clock cycle. Multiple bits can be processed on every clock cycle to speed the CRC calculation. For example, another CRC implementation for *g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 is shown in **Figure 4** [14, 15]. The parallelism of this CRC implementation is 3 and thus three bits are processed on every clock cycle. From **Figures 3** and **4**, it is clear that parallelism comes at the expense of the increased

In this scheme, *e* is segmented into multiple blocks and the CRC of each block is

The size of *<sup>e</sup><sup>M</sup>*�<sup>1</sup> is *<sup>n</sup>* and the size of *<sup>e</sup> <sup>j</sup>* is *<sup>m</sup>*, where 0<sup>≤</sup> *<sup>j</sup>*<sup>≤</sup> *<sup>M</sup>* � 2. Note that *<sup>L</sup>* <sup>þ</sup> *<sup>N</sup>*

<sup>¼</sup> CRC CRC *<sup>e</sup>*<sup>0</sup> � �CRC *<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>*þ*<sup>n</sup>* h i <sup>þ</sup> … <sup>þ</sup> CRC *<sup>e</sup><sup>M</sup>*�<sup>2</sup> � �CRC *xn* ½ � h i <sup>þ</sup> CRC *<sup>e</sup><sup>M</sup>*�<sup>1</sup> � � <sup>¼</sup> CRC CRC *<sup>e</sup>*<sup>0</sup> � �CRC *<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>* h i <sup>þ</sup> … <sup>þ</sup> CRC *<sup>e</sup><sup>M</sup>*�<sup>2</sup> � � h iCRC *<sup>x</sup><sup>n</sup>* ½ � h i <sup>þ</sup> CRC *<sup>e</sup><sup>M</sup>*�<sup>1</sup> � �

The above expression explains how CRC½ � *e* is obtained. The detail is shown in **Figure 5**. CRC *<sup>x</sup><sup>m</sup>* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* ½ �, … , CRC *<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>* � � and CRC *xn* ½ � do not depend on the transport block size and can be precomputed. Since *n* is in the range 0, ½ � *m* � 1 ,

*<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>3</sup> *<sup>m</sup>*þ*<sup>n</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>3</sup>

, … , *e<sup>M</sup>*�<sup>1</sup> (11)

*<sup>x</sup><sup>n</sup>*þ*<sup>m</sup>* <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>2</sup>

*xn* <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>1</sup>

(12)

obtained by parallel processing. *e* is segmented into multiple blocks [16]:

*e*0, *e*<sup>1</sup>

is equal to *n* þ *m M*ð Þ � 1 . As a consequence, *e* can be expressed as

*<sup>x</sup><sup>n</sup>* <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>1</sup> h i

circuit complexity.

**Figure 3.**

**Figure 4.**

*CRC implementation for g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> <sup>1</sup>*.*

*A Brief Overview of CRC Implementation for 5G NR DOI: http://dx.doi.org/10.5772/intechopen.91790*

*CRC implementation for g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> <sup>1</sup>*.*

**4.2 CRC implementation by parallel processing**

*<sup>e</sup>* <sup>¼</sup> *<sup>e</sup>*<sup>0</sup>*x*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>*þ*<sup>n</sup>* <sup>þ</sup> *<sup>e</sup>*<sup>1</sup>

CRC½ �¼ *<sup>e</sup>* CRC *<sup>e</sup>*<sup>0</sup>*x*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>*þ*<sup>n</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>2</sup>

variables that need to be precomputed include

The CRC of *e* is given by

**73**

The division of polynomial using modulo-2 arithmetic is a computationally intensive operation. In the worst case, it requires a shift operation and an XOR logic operation for each bit of *e*. As a consequence, this scheme is rarely used in actual systems. In order to solve the problem of the direct calculation, many schemes have been proposed in the literatures.

For example, the CRC implementation for *g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 is shown in **Figure 3** [12, 13]. The parallelism of this CRC implementation is 1 and thus one bit is

$$\frac{\left(\lambda^3 + \lambda + 1\right)\left(\lambda^5 + \lambda^4 + \lambda^3 + \lambda^2\right)}{\left(\lambda^5 + \lambda^4 + \lambda^3\right)}$$

$$\frac{\lambda^5 + \lambda^4 + \lambda^3}{\left(\lambda^3 + \lambda^2 + \lambda^2\right)}$$

$$\frac{\lambda^3 + \lambda^2 + \lambda}{\lambda^2}$$

$$\frac{\lambda^2 + \lambda + 1}{\lambda}$$

**Figure 2.** *The division of polynomial using modulo-2 arithmetic.* *A Brief Overview of CRC Implementation for 5G NR DOI: http://dx.doi.org/10.5772/intechopen.91790*

#### **Figure 3.**

**Property 2.**

the following.

CRC of *A x*ð Þ and *B x*ð Þ independently.

**4. Overview of the CRC implementation**

**4.1 CRC implementation by direct calculation**

to *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 and the remainder is equal to *<sup>x</sup>*. That is,

using modulo-2 arithmetic.

been proposed in the literatures.

*The division of polynomial using modulo-2 arithmetic.*

**Figure 2.**

**72**

CRC*g x*ð Þ½ �¼ *A x*ð Þþ *B x*ð Þ CRC*g x*ð Þ½ �þ *A x*ð Þ CRC*g x*ð Þ½ � *B x*ð Þ *:* (9)

Property 2 implies that CRC*g x*ð Þ½ � *A x*ð Þþ *B x*ð Þ can be obtained by computing the

The proof of the property 1 and the property 2 can be found in Refs. [10, 11]. It

is omitted for brevity. *g x*ð Þ in the expression of CRC*g x*ð Þ½ � *A x*ð Þ is clear from the context. As a consequence, *g x*ð Þ in the expression of CRC*g x*ð Þ½ � *A x*ð Þ is omitted in

*Moving Broadband Mobile Communications Forward - Intelligent Technologies for 5G…*

In this section, we give an overview of the CRC implementation. In the following, the received transport block after the hard decision *e* is used as an

In this scheme, the CRC of *e* is directly calculated by the division of polynomial

CRC *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>4</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> <sup>1</sup> <sup>¼</sup> *<sup>x</sup>* (10)

**Figure 2** illustrates an example. The dividend is equal to *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>4</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 and the divisor is equal to *<sup>x</sup>*<sup>2</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1. The division of polynomial begins by putting *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>4</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> below *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*4. Subtracting and bringing down the next term give us the intermediate variable *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>*. This process is repeated until the degree of the intermediate variable is less than 2. Finally, we obtain that the quotient is equal

The division of polynomial using modulo-2 arithmetic is a computationally intensive operation. In the worst case, it requires a shift operation and an XOR logic operation for each bit of *e*. As a consequence, this scheme is rarely used in actual systems. In order to solve the problem of the direct calculation, many schemes have

For example, the CRC implementation for *g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 is shown in **Figure 3** [12, 13]. The parallelism of this CRC implementation is 1 and thus one bit is

example. The implementation is easily generalized to other cases.

*CRC implementation for g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> <sup>1</sup>*.*

**Figure 4.** *CRC implementation for g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> <sup>1</sup>*.*

processed on every clock cycle. Multiple bits can be processed on every clock cycle to speed the CRC calculation. For example, another CRC implementation for *g x*ð Þ¼ *<sup>x</sup>*<sup>5</sup> <sup>þ</sup> *<sup>x</sup>*<sup>3</sup> <sup>þ</sup> *<sup>x</sup>* <sup>þ</sup> 1 is shown in **Figure 4** [14, 15]. The parallelism of this CRC implementation is 3 and thus three bits are processed on every clock cycle. From **Figures 3** and **4**, it is clear that parallelism comes at the expense of the increased circuit complexity.

#### **4.2 CRC implementation by parallel processing**

In this scheme, *e* is segmented into multiple blocks and the CRC of each block is obtained by parallel processing. *e* is segmented into multiple blocks [16]:

$$e^0, e^1, \dots, e^{M-1} \tag{11}$$

The size of *<sup>e</sup><sup>M</sup>*�<sup>1</sup> is *<sup>n</sup>* and the size of *<sup>e</sup> <sup>j</sup>* is *<sup>m</sup>*, where 0<sup>≤</sup> *<sup>j</sup>*<sup>≤</sup> *<sup>M</sup>* � 2. Note that *<sup>L</sup>* <sup>þ</sup> *<sup>N</sup>* is equal to *n* þ *m M*ð Þ � 1 . As a consequence, *e* can be expressed as

$$\mathbf{e} = \mathbf{e}^0 \mathbf{x}^{(M-2)m+n} + \mathbf{e}^1 \mathbf{x}^{(M-3)m+n} + \dots + \mathbf{e}^{M-3} \mathbf{x}^{n+m} + \mathbf{e}^{M-2} \mathbf{x}^n + \mathbf{e}^{M-1}$$

The CRC of *e* is given by

$$\begin{aligned} \text{CRC}[\mathbf{e}] &= \text{CRC}\left[\mathbf{e}^{0}\mathbf{x}^{(M-2)m+n} + \dots + \mathbf{e}^{M-2}\mathbf{x}^{n} + \mathbf{e}^{M-1}\right] \\ &= \text{CRC}\left[\text{CRE}\left[\mathbf{e}^{0}\right]\text{CRE}\left[\mathbf{x}^{(M-2)m+n}\right] + \dots + \text{CRC}\left[\mathbf{e}^{M-2}\right]\text{CRE}[\mathbf{x}^{n}]\right] + \text{CRC}\left[\mathbf{e}^{M-1}\right] \\ &= \text{CRE}\left[\left[\text{CRE}\left[\mathbf{e}^{0}\right]\text{CRE}\left[\mathbf{x}^{(M-2)m}\right] + \dots + \text{CRC}\left[\mathbf{e}^{M-2}\right]\right]\text{CRC}[\mathbf{x}^{n}]\right] + \text{CRC}\left[\mathbf{e}^{M-1}\right] \end{aligned} \tag{12}$$

The above expression explains how CRC½ � *e* is obtained. The detail is shown in **Figure 5**. CRC *<sup>x</sup><sup>m</sup>* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* ½ �, … , CRC *<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>* � � and CRC *xn* ½ � do not depend on the transport block size and can be precomputed. Since *n* is in the range 0, ½ � *m* � 1 , variables that need to be precomputed include

*<sup>T</sup>*<sup>1</sup> <sup>¼</sup> CRC *<sup>e</sup>*<sup>0</sup>*x*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup>*<sup>1</sup>*p*�<sup>1</sup> h i

*A Brief Overview of CRC Implementation for 5G NR DOI: http://dx.doi.org/10.5772/intechopen.91790*

*Te*þ<sup>2</sup> <sup>¼</sup> CRC *Te*þ1*x<sup>n</sup>* ½ �þ CRC *<sup>e</sup><sup>M</sup>*�<sup>1</sup> � �

…

*m* þ *p* � 2.

expression

**Figure 6.**

**75**

*CRC implementation by serial processing.*

*<sup>T</sup>*<sup>2</sup> <sup>¼</sup> CRC *<sup>e</sup>px*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup>*<sup>2</sup>*p*�<sup>1</sup> h i <sup>þ</sup> CRC *<sup>T</sup>*1*xmp* ½ �

*Te* <sup>¼</sup> CRC *<sup>e</sup>*ð Þ *<sup>e</sup>*�<sup>1</sup> *px*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup>ep*�<sup>1</sup> h i <sup>þ</sup> CRC *Te*�1*xmp* ½ �

the range 0, ½ � *m* � 1 , variables that need to be precomputed include

*Te*þ<sup>1</sup> <sup>¼</sup> CRC *<sup>e</sup>epx*ð Þ *<sup>M</sup>*�*ep*�<sup>2</sup> *<sup>m</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>2</sup> h i <sup>þ</sup> CRC *Tex*ð Þ *<sup>M</sup>*�*eP*�<sup>1</sup> *<sup>m</sup>* h i

where *e* ¼ ⌊ð Þ *M* � 1 *=P*⌋. The above expression explains how CRC½ � *e* is calculated. The detail is shown in **Figure 6**. CRC *xm* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* ½ �, … , CRC *<sup>x</sup>*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* � � and CRC *xn* ½ � do not depend on the transport block size and can be precomputed. Since *n* is in

CRC *<sup>x</sup>*<sup>1</sup> � �, CRC *<sup>x</sup>*<sup>2</sup> � �, … , CRC *<sup>x</sup><sup>m</sup>*�<sup>1</sup> � �, CRC *<sup>x</sup><sup>m</sup>* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* � �, … , CRC *<sup>x</sup>*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* h i (19)

As a consequence, the number of variables that needs to be precomputed is

It is clear that the memory that needs to store the variables increases with the transport block size. To reduce the memory, CRC *<sup>x</sup>α<sup>m</sup>* ½ �can be recursively calculated by using CRC *xm* ½ � [17]. That is, CRC *<sup>x</sup>α<sup>m</sup>* ½ � is recursively obtained by the following

CRC *<sup>x</sup>α<sup>m</sup>* ½ �¼ CRC CRC *<sup>x</sup>*ð Þ *<sup>α</sup>*�<sup>1</sup> *<sup>m</sup>* h iCRC *xm* ½ � h i (20)

(18)

**Figure 5.** *CRC implementation by parallel processing.*

$$\text{CRC}[\mathbf{x}^1], \text{CRC}[\mathbf{x}^2], \dots, \text{CRC}[\mathbf{x}^{m-1}], \text{CRC}[\mathbf{x}^m], \text{CRC}[\mathbf{x}^{2m}], \dots, \text{CRC}[\mathbf{x}^{(M-2)m}] \quad \text{(13)}$$

As a consequence, the number of variables that needs to be precomputed is *m* þ *M* � 3.

It is clear that the memory that needs to store the variables increases with the transport block size. To reduce the memory, CRC *<sup>x</sup>α<sup>m</sup>* ½ � can be recursively calculated by using CRC *xm* ½ � [17]. That is, CRC *<sup>x</sup>α<sup>m</sup>* ½ � is recursively obtained by the following expression

$$\text{CRC}[\mathbf{x}^{am}] = \text{CRC}\left[\text{CRC}\left[\mathbf{x}^{(a-1)m}\right]\text{CRC}[\mathbf{x}^{m}]\right] \tag{14}$$

In this way, the variables that need to be precomputed include

$$\text{CRC}[\boldsymbol{x}^1], \text{CRC}[\boldsymbol{x}^2], \dots, \text{CRC}[\boldsymbol{x}^{m-1}], \text{CRC}[\boldsymbol{x}^m] \tag{15}$$

As a consequence, the number of variables that needs to be precomputed is *m*.

#### **4.3 CRC implementation by serial processing**

In this scheme, *e* is segmented into multiple blocks and the CRC of each block is obtained by serial processing. *e* is segmented into multiple blocks [18]:

$$\left(e^0, e^1, \dots, e^{M-1}\right) \tag{16}$$

The size of *<sup>e</sup><sup>M</sup>*�<sup>1</sup> is *<sup>n</sup>* and the size of *<sup>e</sup> <sup>j</sup>* is *<sup>m</sup>*, where 0<sup>≤</sup> *<sup>j</sup>*<sup>≤</sup> *<sup>M</sup>* � 2. Note that *<sup>L</sup>* <sup>þ</sup> *<sup>N</sup>* is equal to *n* þ *m M*ð Þ � 1 . *e* can be expressed as

$$\mathbf{e} = \mathbf{e}^{0} \boldsymbol{\pi}^{(M-2)m+n} + \mathbf{e}^{1} \boldsymbol{\pi}^{(M-3)m+n} + \dots + \mathbf{e}^{M-3} \boldsymbol{\pi}^{n+m} + \mathbf{e}^{M-2} \boldsymbol{\pi}^{n} + \mathbf{e}^{M-1} \tag{17}$$

The CRC of *e* is given by

*A Brief Overview of CRC Implementation for 5G NR DOI: http://dx.doi.org/10.5772/intechopen.91790*

$$\begin{aligned} T\_1 &= \text{CRC} \left[ \mathbf{e}^0 \mathbf{x}^{(p-1)m} + \dots + \mathbf{e}^{1p-1} \right] \\\\ T\_2 &= \text{CRC} \left[ \mathbf{e}^p \mathbf{x}^{(p-1)m} + \dots + \mathbf{e}^{2p-1} \right] + \text{CRC} [T\_1 \mathbf{x}^{mp}] \\\\ &\dots \\\\ T\_\epsilon &= \text{CRC} \left[ \mathbf{e}^{(\epsilon-1)p} \mathbf{x}^{(p-1)m} + \dots + \mathbf{e}^{p-1} \right] + \text{CRC} [T\_{\epsilon-1} \mathbf{x}^{mp}] \\\\ T\_{\epsilon+1} &= \text{CRC} \left[ \mathbf{e}^p \mathbf{x}^{(M-\epsilon p-2)m} + \dots + \mathbf{e}^{M-2} \right] + \text{CRC} \left[ T\_\epsilon \mathbf{x}^{(M-\epsilon p-1)m} \right] \\\\ T\_{\epsilon+2} &= \text{CRC} [T\_{\epsilon+1} \mathbf{x}^n] + \text{CRC} [\mathbf{e}^{M-1}] \end{aligned} \tag{18}$$

where *e* ¼ ⌊ð Þ *M* � 1 *=P*⌋. The above expression explains how CRC½ � *e* is calculated. The detail is shown in **Figure 6**. CRC *xm* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* ½ �, … , CRC *<sup>x</sup>*ð Þ *<sup>p</sup>*�<sup>1</sup> *<sup>m</sup>* � � and CRC *xn* ½ � do not depend on the transport block size and can be precomputed. Since *n* is in the range 0, ½ � *m* � 1 , variables that need to be precomputed include

$$\text{CRC}[\boldsymbol{x}^1], \text{CRC}[\boldsymbol{x}^2], \dots, \text{CRC}[\boldsymbol{x}^{m-1}], \text{CRC}[\boldsymbol{x}^m], \text{CRC}[\boldsymbol{x}^{2m}], \dots, \text{CRC}[\boldsymbol{x}^{(p-1)m}] \quad \text{(19)}$$

As a consequence, the number of variables that needs to be precomputed is *m* þ *p* � 2.

It is clear that the memory that needs to store the variables increases with the transport block size. To reduce the memory, CRC *<sup>x</sup>α<sup>m</sup>* ½ �can be recursively calculated by using CRC *xm* ½ � [17]. That is, CRC *<sup>x</sup>α<sup>m</sup>* ½ � is recursively obtained by the following expression

$$\text{CRC}[\mathbf{x}^{\text{am}}] = \text{CRC}\left[\text{CRC}\left[\mathbf{x}^{(a-1)m}\right]\text{CRC}[\mathbf{x}^{m}]\right] \tag{20}$$

**Figure 6.** *CRC implementation by serial processing.*

CRC *<sup>x</sup>*<sup>1</sup> � �, CRC *<sup>x</sup>*<sup>2</sup> � �, … , CRC *xm*�<sup>1</sup> � �, CRC *xm* ½ �, CRC *<sup>x</sup>*<sup>2</sup>*<sup>m</sup>* � �, … , CRC *<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>* h i

*Moving Broadband Mobile Communications Forward - Intelligent Technologies for 5G…*

CRC *<sup>x</sup>α<sup>m</sup>* ½ �¼ CRC CRC *<sup>x</sup>*ð Þ *<sup>α</sup>*�<sup>1</sup> *<sup>m</sup>* h i

In this way, the variables that need to be precomputed include

obtained by serial processing. *e* is segmented into multiple blocks [18]:

*e*0, *e*<sup>1</sup>

*<sup>x</sup>*ð Þ *<sup>M</sup>*�<sup>3</sup> *<sup>m</sup>*þ*<sup>n</sup>* <sup>þ</sup> … <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>3</sup>

**4.3 CRC implementation by serial processing**

is equal to *n* þ *m M*ð Þ � 1 . *e* can be expressed as

*<sup>e</sup>* <sup>¼</sup> *<sup>e</sup>*<sup>0</sup>*x*ð Þ *<sup>M</sup>*�<sup>2</sup> *<sup>m</sup>*þ*<sup>n</sup>* <sup>þ</sup> *<sup>e</sup>*<sup>1</sup>

The CRC of *e* is given by

**74**

*m* þ *M* � 3.

**Figure 5.**

*CRC implementation by parallel processing.*

expression

As a consequence, the number of variables that needs to be precomputed is

It is clear that the memory that needs to store the variables increases with the transport block size. To reduce the memory, CRC *<sup>x</sup>α<sup>m</sup>* ½ � can be recursively calculated by using CRC *xm* ½ � [17]. That is, CRC *<sup>x</sup>α<sup>m</sup>* ½ � is recursively obtained by the following

As a consequence, the number of variables that needs to be precomputed is *m*.

In this scheme, *e* is segmented into multiple blocks and the CRC of each block is

The size of *<sup>e</sup><sup>M</sup>*�<sup>1</sup> is *<sup>n</sup>* and the size of *<sup>e</sup> <sup>j</sup>* is *<sup>m</sup>*, where 0<sup>≤</sup> *<sup>j</sup>*<sup>≤</sup> *<sup>M</sup>* � 2. Note that *<sup>L</sup>* <sup>þ</sup> *<sup>N</sup>*

CRC *xm* ½ �

, … , *e<sup>M</sup>*�<sup>1</sup> (16)

*<sup>x</sup><sup>n</sup>* <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>1</sup> (17)

*<sup>x</sup><sup>n</sup>*þ*<sup>m</sup>* <sup>þ</sup> *<sup>e</sup><sup>M</sup>*�<sup>2</sup>

h i

CRC *<sup>x</sup>*<sup>1</sup> � �, CRC *<sup>x</sup>*<sup>2</sup> � �, … , CRC *xm*�<sup>1</sup> � �, CRC *xm* ½ � (15)

(13)

(14)

*Moving Broadband Mobile Communications Forward - Intelligent Technologies for 5G…*

In this way, the variables that need to be precomputed include

$$\text{CRC}[\boldsymbol{\kappa}^1], \text{CRC}[\boldsymbol{\kappa}^2], \dots, \text{CRC}[\boldsymbol{\kappa}^{m-1}], \text{CRC}[\boldsymbol{\kappa}^m] \tag{21}$$

**Figure 7** [20]. The Sarwate algorithm uses a single table of 256 32-bit elements and reads the bits byte by byte. Modern processors usually access 32 bits or 64 bits at a time. As a consequence, the Sarwate algorithm is not efficient. Some schemes have

Kounavis and Berry propose the slicing-by-4 and slicing-by-8 algorithms based on the lookup table [20]. The detail and the proof of the algorithms can be found in [20]. The slicing-by-4 and slicing-by-8 algorithms are shown in **Figures 8** and **9** respectively [20]. The slicing-by-4 algorithm uses four tables of 256 32-bit elements and reads 32 bits at a time. The slicing-by-8 algorithm uses eight tables of 256 32-bit elements and reads 64 bits at a time. The performance of the slicing-by-4 and slicing-by-8 algorithms is improved compared to the Sarwate algorithm.

In 5G NR, the transport block consists of up to million bits and the code block consists of up to 8448 bits. Due to the difference in the size of the transport block and the code block, the scheme of the CRC processing suitable for the transport block and that suitable for the code block are different. This chapter gives an

1 Department of Wireless Product Research and Design Institute, ZTE Corporation,

2 State Key Laboratory of Mobile Network and Mobile Multimedia Technology,

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

been proposed in the literatures to solve this problem.

**4.5 The slicing-by-4 and slicing-by-8 algorithms**

*A Brief Overview of CRC Implementation for 5G NR DOI: http://dx.doi.org/10.5772/intechopen.91790*

overview of the CRC implementation in 5G NR.

The authors declare no conflict of interest.

**5. Conclusion**

**Conflict of interest**

**Author details**

Shenzhen, China

ZTE Corporation, Shenzhen, China

provided the original work is properly cited.

\*Address all correspondence to: wu.hao19@zte.com.cn

Hao Wu1,2

**77**

As a consequence, the number of variables that needs to be precomputed is *m*.

#### **4.4 The Sarwate algorithm**

Sarwate proposes an algorithm based on the lookup table [19]. The detail and the proof of the algorithm can be found in [19]. The Sarwate algorithm is shown in

#### **Figure 7.**

*The Sarwate algorithm.*

#### **Figure 8.**

*The slicing-by-4 algorithm.*

**Figure 9.** *The slicing-by-8 algorithm.* **Figure 7** [20]. The Sarwate algorithm uses a single table of 256 32-bit elements and reads the bits byte by byte. Modern processors usually access 32 bits or 64 bits at a time. As a consequence, the Sarwate algorithm is not efficient. Some schemes have been proposed in the literatures to solve this problem.
