4.2 QCA 4 � 4 multiplier

Multiplier plays an important role in DSP systems. In divers' DSP application, it is not needed to utilize all output bits of multiplier. As in most of the FIR implementation, the FIR output can also be obtained using only the MSB bits of the multiplier output [29]. In literature, there are various algorithms of multiplier such as array multiplier, parallel multiplier and booth multiplier [36–39], which consumed more area and could not meet the criteria of propagation delay. This problem has been overcome in this paper by making use of Vedic multiplier which is much faster with minimum propagation delay [40–43]. To design the QCA circuit, we have used the version of the circuit proposed in [44]. Figure 8 demonstrates the schematic of 4-bit Vedic multiplier architecture where A ¼ A3A<sup>2</sup> … A<sup>0</sup> and B ¼ B3B<sup>2</sup> … B<sup>0</sup> are the inputs and the outputs signal for the multiplication result are P ¼ P7P<sup>6</sup> … … P0. The implementation of this multiplier can be done by using four 2 � 2 Vedic multiplier blocks and three 4-bit adder blocks.

4.2.1 QCA 4-bit parallel adder

Figure 9.

85

Figure 8.

Block diagram of 4-bit Vedic multiplier.

DOI: http://dx.doi.org/10.5772/intechopen.90193

The 4-bit adder performs computing function of the FIR filter. Therefore, the half and the full adder are used to construct the 4-bit binary adder. The proposed

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

Proposed (a) logical diagram, (b) QCA layout and (c) timing graph of half adder circuit.

Figure 7. Proposed (a) logical diagram and (b) QCA layout of D flip-flop.

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology… DOI: http://dx.doi.org/10.5772/intechopen.90193

Figure 8. Block diagram of 4-bit Vedic multiplier.

4. QCA FIR implementation

4.1 QCA D flip-flop

of 0.15 μm<sup>2</sup>

Figure 7.

84

4.2 QCA 4 � 4 multiplier

• A D flip-flop to implement a simple delay

Advances in Quantum Communication and Information

• A multiplier to implement the coefficients

• An adder to sum the nodes at the end of each tap

the D flip-flop is represented by the following equation:

meaningful output comes on the sixth clock.

Vedic multiplier blocks and three 4-bit adder blocks.

Proposed (a) logical diagram and (b) QCA layout of D flip-flop.

The proposed QCA FIR filter consists of three principal components:

Flip-flop is a circuit that may be used to store state information ("0" or "1" logic value). Here, the structure of the proposed D flip-flop is illustrated in Figure 7a which includes three majority gates and one inverter gate. The logic equation of

Qð Þ<sup>t</sup> ¼ CLk:D þ CLk:Qð Þ <sup>t</sup>�<sup>1</sup>

Figure 7b illustrates the proposed QCA flip-flop. It includes 79 cells with an area

Multiplier plays an important role in DSP systems. In divers' DSP application, it is not needed to utilize all output bits of multiplier. As in most of the FIR implementation, the FIR output can also be obtained using only the MSB bits of the multiplier output [29]. In literature, there are various algorithms of multiplier such as array multiplier, parallel multiplier and booth multiplier [36–39], which consumed more area and could not meet the criteria of propagation delay. This problem has been overcome in this paper by making use of Vedic multiplier which is much faster with minimum propagation delay [40–43]. To design the QCA circuit, we have used the version of the circuit proposed in [44]. Figure 8 demonstrates the schematic of 4-bit Vedic multiplier architecture where A ¼ A3A<sup>2</sup> … A<sup>0</sup> and B ¼ B3B<sup>2</sup> … B<sup>0</sup> are the inputs and the outputs signal for the multiplication result are P ¼ P7P<sup>6</sup> … … P0. The implementation of this multiplier can be done by using four 2 � 2

. It takes five clock periods for the inputs to reach the output, and first

#### Figure 9.

Proposed (a) logical diagram, (b) QCA layout and (c) timing graph of half adder circuit.
