Applications and Technologies

Chapter 6

Abstract

processing systems

1. Introduction

79

and Abdellatif Mtibaa

Design of 4-Bit 4-Tap FIR Filter

Based on Quantum-Dot Cellular

a Realistic Clocking Scheme

Ismail Gassoumi, Lamjed Touil, Bouraoui Ouni

Automata (QCA) Technology with

The increasing demand for efficient signal processors necessitates the design of

digital finite duration impulse response FIR filter which occupies less area and consumes less power. FIR filters have simple, regular and scalable structures. This paper represents designing and implementation of a low-power 4-tap FIR filter based on quantum-dot cellular automata (QCA) by using a realistic clocking scheme. The QCADesigner software, as widely used in QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation result has been computed for the proposed circuit using accurate QCADesigner-E software. The proposed QCA FIR achieves about 97.74% reduction in power compared to previous existing designs. The outcome of this work can clearly open up a new window of opportunity for low-power signal

Keywords: QCA technology, QCA designer, FIR filter, low power, QCA pro

and speed metrics has become a challenge. On one side, several digital signal processing applications are based on complex algorithm which requires great computational power per silicon area. On the other side, there are stringent portability and energy requirements which further complicate the design task. Therefore, achieving the required computational throughput with minimum energy consumption has become the key design goal, as it contributes to the total power budget as well as reliability of target application. So far, VLSI industry has been successfully following Moore's law. Simultaneous reduction in critical dimensions and operating voltage of CMOS transistors yields higher speed and packaging density while decreasing the silicon area and power consumption [1]. However, this trend of successive transistor scaling cannot continue for long, as the CMOS technology is reaching its fundamental physical limits and entails many challenges [2–4]. Low-power digital design is being investigated at all levels of design abstraction.

Recently, the design of high-performance digital circuits meeting area, power
