1. Introduction

Recently, the design of high-performance digital circuits meeting area, power and speed metrics has become a challenge. On one side, several digital signal processing applications are based on complex algorithm which requires great computational power per silicon area. On the other side, there are stringent portability and energy requirements which further complicate the design task. Therefore, achieving the required computational throughput with minimum energy consumption has become the key design goal, as it contributes to the total power budget as well as reliability of target application. So far, VLSI industry has been successfully following Moore's law. Simultaneous reduction in critical dimensions and operating voltage of CMOS transistors yields higher speed and packaging density while decreasing the silicon area and power consumption [1]. However, this trend of successive transistor scaling cannot continue for long, as the CMOS technology is reaching its fundamental physical limits and entails many challenges [2–4]. Low-power digital design is being investigated at all levels of design abstraction.

At device level, a number of CMOS alternatives are summarized in International Technology Roadmap for Semiconductors (ITRS) report such as quantum-dot cellular automata (QCA), single-electron transistor (SET), carbon nanotube fieldeffect transistors (CNTFET) and resonant tunneling diodes (RTD) [5]. The use of (QCA) on the nanoscale has a promising future because of its ability to achieve high performance in terms of device density, clock frequency and power consumption [6–9]. Essentially, QCA offers potential advantages of ultralow-power dissipation. QCA is expected to achieve very high device density of 1012 device/cm<sup>2</sup> and switching speeds of 10 ps and a power dissipation of 100 W/cm<sup>2</sup> [10]. These features, which are not offered by CMOS devices, can open new opportunities to save power in mobile systems design. In addition, they can make the proposed QCA approach useful for signal and image processing systems applied on portable communication devices where real-time processing and low-power consumption are needed in today's world in order to extend battery life. Several attempts are made towards the cost-effective realization of QCA circuit in [11–19]. Whereas QCA technology has advantages over CMOS technology, various limitations are identified. Its include placing long lines of cells among clocking zones which leads to thermal fluctuation issue and increases delay of the circuit. Recently, a universal, scalable, and efficient (USE) clocking scheme [20] is a proposed technique to overcome the mentioned limitations. This scheme can design feedback paths with different loop sizes. It is regular and flexible enough to allow placement and routing, besides avoiding thermodynamic effects due to long wires. On the other hand, for designing several digital signal processors (DSP), finite impulse response (FIR) filter is widely used as a critical component. For their guaranteed linear phase and stability, the FIR filter is used for the conception of very highly efficient hardware circuits. Theses circuits perform the key operation in various recent mobile computing and portable multimedia applications. We denote highefficiency video coding (HEVC), channel equalization, speech processing, software-defined radio (SDR) and others. Indeed, an efficient FIR filter design essentially improves the performance of a complex DSP system. This fact pushed designers to search for new methods to grant low-power consumption for FIR filter [21–28]. QCA logic design circuit is stimulated by its applications in low-power electronic design. It has lately attracted significant attention. All these above factors motivate us to investigate a new architecture around QCA by using USE clocking scheme, which can efficiently perform FIR operation.

y nð Þ¼ <sup>X</sup> N�1

where H (z) is the transfer function of the filter, given by

is the input data at time instant ð Þ n � k . The z transform of the data output is

DOI: http://dx.doi.org/10.5772/intechopen.90193

3. QCA review

Transposed direct form FIR filter architecture.

Figure 1.

81

k¼0

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

H Zð Þ¼ <sup>X</sup>

N

k¼0

Several architectures have been proposed in the last recent years. A filter can be implemented in direct form (DF) or transposed direct form (TDF) [29]. The transposed form and the direct form of a FIR filter are equivalent. It's easy to prove that, in direct form, the word length of each delay element is equal to the word length of the input signal. However, in the transposed form, each delay element has a longer word length than that in the direct form. The transposed structure reduces the critical path delay, but it uses more hardware. DF FIR filter is area-efficient, while the TDF filter is delay-efficient. In this paper, the architecture of the proposed FIR filter is presented. It is based on the transposed direct form FIR filter structure as shown in Figure 1. This structure comprises adders, D flip-flops, and multipliers.

The QCA approach, introduced in 1993 by Lent et al. [6], is able to replace devices based on field-effect transistor (FET) on nanoscale. This nanotechnology was conceived based on some of Landauer's ideas regarding energy-efficient and robust digital devices [30]. It consists of an array of cells. Each cell contains four quantum dots at the corner of a square which can hold a single electron per dot. Only two electrons diametrically opposite are injected into a cell due to Coulomb interaction [31]. Through Coulombic effects, two possible polarizations (labeled �1 and 1) can be shaped. These polarizations are represented by binary "0" and binary "1" as shown in Figure 2. Figure 3 shows the propagation of logic "0" and logic "1," respectively, from

where N represents the length of the filter, hk is the Kth coefficient, and x nð Þ � k

hkx nð Þ � k (1)

hkZ�<sup>k</sup> (3)

Y zð Þ¼ H zð Þ:X zð Þ (2)

The main concern of this paper is to present a new design for FIR filter based on QCA technology which yields significant reduction in terms of power. This paper is organized as follows. Section 2 presents the background of FIR filter structures. Section 3 indulges the preliminaries of QCA technology. Section 4 discusses the FIR filter power optimization by QCA technology. Section 5 shows the discussions and results of the proposed FIR filter-based technology. Finally, conclusions are drawn in Section 6.

## 2. Background of FIR filter structures

FIR filters are important building blocks among the various digital signal processing applications. Recently, due to the popularity of the portable batterypowered wireless communication systems, low-power and high-performance digital filter designs become more and more important.

An nth order FIR filter performs N-point linear convolution of input sequence with filter coefficients for new input sample. The transfer function of the linear invariant (LTI) FIR filter can be expressed as the following equation:

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology… DOI: http://dx.doi.org/10.5772/intechopen.90193

$$\mathbf{y}(\mathbf{n}) = \sum\_{k=0}^{N-1} h\_k \mathbf{x}(n-k) \tag{1}$$

where N represents the length of the filter, hk is the Kth coefficient, and x nð Þ � k is the input data at time instant ð Þ n � k .

The z transform of the data output is

At device level, a number of CMOS alternatives are summarized in International Technology Roadmap for Semiconductors (ITRS) report such as quantum-dot cellular automata (QCA), single-electron transistor (SET), carbon nanotube fieldeffect transistors (CNTFET) and resonant tunneling diodes (RTD) [5]. The use of (QCA) on the nanoscale has a promising future because of its ability to achieve high performance in terms of device density, clock frequency and power consumption [6–9]. Essentially, QCA offers potential advantages of ultralow-power dissipation. QCA is expected to achieve very high device density of 1012 device/cm<sup>2</sup> and switching speeds of 10 ps and a power dissipation of 100 W/cm<sup>2</sup> [10]. These features, which are not offered by CMOS devices, can open new opportunities to save power in mobile systems design. In addition, they can make the proposed QCA approach useful for signal and image processing systems applied on portable communication devices where real-time processing and low-power consumption are needed in today's world in order to extend battery life. Several attempts are made towards the cost-effective realization of QCA circuit in [11–19]. Whereas QCA technology has advantages over CMOS technology, various limitations are identified. Its include placing long lines of cells among clocking zones which leads to thermal fluctuation issue and increases delay of the circuit. Recently, a universal, scalable, and efficient (USE) clocking scheme [20] is a proposed technique to overcome the mentioned limitations. This scheme can design feedback paths with different loop sizes. It is regular and flexible enough to allow placement and routing, besides avoiding thermodynamic effects due to long wires. On the other hand, for designing several digital signal processors (DSP), finite impulse response (FIR) filter is widely used as a critical component. For their guaranteed linear phase and stability, the FIR filter is used for the conception of very highly efficient hardware circuits. Theses circuits perform the key operation in various recent mobile computing and portable multimedia applications. We denote highefficiency video coding (HEVC), channel equalization, speech processing, software-defined radio (SDR) and others. Indeed, an efficient FIR filter design essentially improves the performance of a complex DSP system. This fact pushed designers to search for new methods to grant low-power consumption for FIR filter [21–28]. QCA logic design circuit is stimulated by its applications in low-power electronic design. It has lately attracted significant attention. All these above factors motivate us to investigate a new architecture around QCA by using USE clocking

Advances in Quantum Communication and Information

scheme, which can efficiently perform FIR operation.

2. Background of FIR filter structures

digital filter designs become more and more important.

invariant (LTI) FIR filter can be expressed as the following equation:

in Section 6.

80

The main concern of this paper is to present a new design for FIR filter based on QCA technology which yields significant reduction in terms of power. This paper is organized as follows. Section 2 presents the background of FIR filter structures. Section 3 indulges the preliminaries of QCA technology. Section 4 discusses the FIR filter power optimization by QCA technology. Section 5 shows the discussions and results of the proposed FIR filter-based technology. Finally, conclusions are drawn

FIR filters are important building blocks among the various digital signal processing applications. Recently, due to the popularity of the portable batterypowered wireless communication systems, low-power and high-performance

An nth order FIR filter performs N-point linear convolution of input sequence with filter coefficients for new input sample. The transfer function of the linear

$$Y(\mathbf{z}) = H(\mathbf{z}) . X(\mathbf{z}) \tag{2}$$

where H (z) is the transfer function of the filter, given by

$$H(Z) = \sum\_{k=0}^{N} h\_k Z^{-k} \tag{3}$$

Several architectures have been proposed in the last recent years. A filter can be implemented in direct form (DF) or transposed direct form (TDF) [29]. The transposed form and the direct form of a FIR filter are equivalent. It's easy to prove that, in direct form, the word length of each delay element is equal to the word length of the input signal. However, in the transposed form, each delay element has a longer word length than that in the direct form. The transposed structure reduces the critical path delay, but it uses more hardware. DF FIR filter is area-efficient, while the TDF filter is delay-efficient. In this paper, the architecture of the proposed FIR filter is presented. It is based on the transposed direct form FIR filter structure as shown in Figure 1. This structure comprises adders, D flip-flops, and multipliers.

Figure 1. Transposed direct form FIR filter architecture.

### 3. QCA review

The QCA approach, introduced in 1993 by Lent et al. [6], is able to replace devices based on field-effect transistor (FET) on nanoscale. This nanotechnology was conceived based on some of Landauer's ideas regarding energy-efficient and robust digital devices [30]. It consists of an array of cells. Each cell contains four quantum dots at the corner of a square which can hold a single electron per dot. Only two electrons diametrically opposite are injected into a cell due to Coulomb interaction [31]. Through Coulombic effects, two possible polarizations (labeled �1 and 1) can be shaped. These polarizations are represented by binary "0" and binary "1" as shown in Figure 2. Figure 3 shows the propagation of logic "0" and logic "1," respectively, from

adiabatic cell operation which enables QCA circuits with high energy efficiency [34]. Generally, QCA clocking is presented with four different phases which are switch, hold, release and relax as illustrated in Figure 5. During the switch phase, which actual computations are occurred, the barriers are raised, and a cell is affected by the polarization of its adjacent cells, and a distinctive polarity is obtained. During the hold phase, the barriers are high, and the polarization of the cell is retained. During the release phase, the barriers are lowered, and the cell loses

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

Over recent years, various clocking schemes have been proposed, but they have introduced some difficulties such as long paths for feedbacks [35]. Recently, USE clocking scheme is a proposed technique for clocking and timing of the QCA circuits. It may be implemented using actual fabrication technologies of integrated circuits. This scheme can design feedback paths with different loop sizes, and its routing is flexible [20]. It defines a grid of clock zones, which are consecutively numbered from 1 to 4 as depicted in Figure 6. This grid ensures the correct

arrangement for the clock zones. Much information about the clocking circuitry are

the polarity. During the relax phase, the cell is non-polarized [35].

DOI: http://dx.doi.org/10.5772/intechopen.90193

mentioned in [20].

Figure 5. QCA clock zones.

Figure 6. QCA USE structure.

83

Figure 2.

Two different polarizations of quantum-dot cell.

Figure 4. Standard gates: Inverter gate (a) and majority gate (b, c).

input to the output in QCA binary wires due to the Coulombic repulsion. Generally, in neighboring cells, the coulombic interaction between electrons is used to implement many logic functions which are controlled by the clocking mechanism [32].

A majority and inverter gates are the fundamental logic gates in the QCA implementations which are composed of some QCA cells as shown in Figure 4 [7, 33]. Furthermore, the majority gate acts as an AND gate and OR gate just by setting one input permanently to 0 or 1. It has a logical function that can be expressed by Eq. (4):

$$\text{MV}\,\left(\mathbf{a}, \mathbf{b}, \mathbf{c}\right) = \mathbf{AB} + \mathbf{BC} + \mathbf{AC} \,\tag{4}$$

### 3.1 QCA clocking

The clocking system is an important factor for the dynamics of QCA. Its principal functions are the synchronization of data flows and the implementation of

## Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology… DOI: http://dx.doi.org/10.5772/intechopen.90193

adiabatic cell operation which enables QCA circuits with high energy efficiency [34]. Generally, QCA clocking is presented with four different phases which are switch, hold, release and relax as illustrated in Figure 5. During the switch phase, which actual computations are occurred, the barriers are raised, and a cell is affected by the polarization of its adjacent cells, and a distinctive polarity is obtained. During the hold phase, the barriers are high, and the polarization of the cell is retained. During the release phase, the barriers are lowered, and the cell loses the polarity. During the relax phase, the cell is non-polarized [35].

Over recent years, various clocking schemes have been proposed, but they have introduced some difficulties such as long paths for feedbacks [35]. Recently, USE clocking scheme is a proposed technique for clocking and timing of the QCA circuits. It may be implemented using actual fabrication technologies of integrated circuits. This scheme can design feedback paths with different loop sizes, and its routing is flexible [20]. It defines a grid of clock zones, which are consecutively numbered from 1 to 4 as depicted in Figure 6. This grid ensures the correct arrangement for the clock zones. Much information about the clocking circuitry are mentioned in [20].

Figure 5. QCA clock zones.

input to the output in QCA binary wires due to the Coulombic repulsion. Generally, in neighboring cells, the coulombic interaction between electrons is used to implement

The clocking system is an important factor for the dynamics of QCA. Its princi-

pal functions are the synchronization of data flows and the implementation of

MV a, b, c ð Þ¼ AB þ BC þ AC (4)

many logic functions which are controlled by the clocking mechanism [32]. A majority and inverter gates are the fundamental logic gates in the QCA implementations which are composed of some QCA cells as shown in Figure 4 [7, 33]. Furthermore, the majority gate acts as an AND gate and OR gate just by setting one input permanently to 0 or 1. It has a logical function that can be expressed by Eq. (4):

Standard gates: Inverter gate (a) and majority gate (b, c).

3.1 QCA clocking

82

Figure 2.

Figure 3. QCA binary wires.

Figure 4.

Two different polarizations of quantum-dot cell.

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Figure 6. QCA USE structure.
