4.3 QCA adder

The proposed 2 2 multiplier takes only 1683 QCA cells with a region of

Advances in Quantum Communication and Information

expected operation is correctly achieved with 60 clock zones delay as depicted in

Parameter Value Number of samples 12,800 Convergence tolerance 0.001000 Radius of effect 65,000000 (nm) Relative permittivity 12,900,000 Clock low 3800000e-023 Clock high 9800000e-022 Clock shift 0,000000e+000 Clock amplitude factor 2,000,000 Layer separation 11,500,000 Maximum iterations per sample 100

.The simulated result of the proposed Vedic multiplier confirms that the

8.42 μm2

Figure 13.

Table 1.

88

Figure 13.

Bistable approximation parameter model.

The QCA implementation of 2 2 multiplier.

Since the FIR output can be obtained using only the MSB bits of the Vedic multiplier output, for the proposed structure of FIR filter, we need a 4-bit QCA adder. The same 4-bit adder designed above is used in this subsection (Table 1).

## 5. Results and discussions

The complete QCA FIR design is implemented using the functional units discussed in the previous section. The implementation and the simulation of the proposed hardware designs are achieved by using QCADesigner 2.0.3 tool [45]. The coherence vector simulation engine is used for this purpose. Table 2 depicts the simulation parameters. In the first step, the sub-module schematic and layout is completed and verified by functional simulations.

These designs have been implemented using a free and a regular USE clock scheme. In addition, we have successfully demonstrated that sub-module design of FIR unit properly satisfies all logic and timing constraints by using the 4 4 USE grid with a square dimension of 5 5 QCA cells. In this direction, with a welldefined methodology and regular timing zones, this design is a standard candidate for fabrication. We note that our proposed entire system requires a huge number of QCA cells mostly due to the long wires necessary to delay compensation. Since the proposed FIR circuit based on QCA technology has started to bloom, we have only compared the full adder module with regular standard scheme circuits. Table 2 shows a comparison of the proposed full adder with some existing designs [35, 46]. The proposed full adder has 1.13, 56.9 and 11% improvements, respectively, in terms of cell count, area occupation and circuit latency as compared to that reported in [35].

In QCA technology, the power consumption of any circuit depends on the number of majority and inverter gates [47]. Therefore, this technology reduces more power than CMOS technology. The consumption of FIR unit in QCA-18 nm technology is valuing 1.6 mW. This value is carried out using QCADesigner-E software [48].

However, the QCA FIR circuit requires 97.74% lesser power consumption than the previous existing designs [49]. In addition, the proposed design of FIR filter can operate at a higher frequency (upper than 1 GHz) than the conventional solution, and it can be useful for future digital signal processing applications for providing excellent processing speed. The overall performance of the proposed QCA design is therefore superior to the existing techniques in terms of power consumption. In this way, we think that this work forms an essential step in the building of QCA circuits for low-power design in this area.

Influence of temperature variations on the polarization of the proposed design has also been investigated. Figure 14 illustrates the effect of polarization on output of FIR circuit due to temperature variations. QCADesigner tool is used to observe this effect. By increasing temperature the AOP of any output cell of the QCA circuit


Table 2. Comparison of various full adders.

References

2007;12(1):38-50

98(12):2169-2184

IEEE. 2002;88(1):78-81

[1] Dennard RH, Gaensslen FH, Yu HN, Rideovt VL, Bassous E, Leblanc AR. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE Solid-State Circuits Society Newsletter.

DOI: http://dx.doi.org/10.5772/intechopen.90193

quantum-dot cellular automata. In: Technical Proceedings of the

Show, vol. 2. 2003. p. 160163

2009. pp. 68-72

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

2010. pp. 953-957

6172-6182

2001-2003

Nanotechnology Conference and Trade

[11] Lamjed T, Ismail G, Radhouane L, Bouraoui O. Efficient design of BinDCT in quantum-dot cellular automata (QCA) technology. IET Image Processing. 2018;12(6):1020-1030

[12] Kim SW, Swartzlander EE. Parallel multipliers for quantum-dot cellular automata. In: Nanotechnology Materials and Devices Conference; Traverse City.

Multipliers with coplanar crossings for quantum-dot cellular automata. In: Conference on Nanotechnology; Seoul.

[14] Balali M, Rezai A, Balali H, Rabiei F, Emadi S. Towards coplanar quantumdot cellular automata adders based on efficient three-input XOR gate. Results

[15] Sasamal TN, Singh AK, Mohan A. Efficient design of reversible alu in quantum-dot cellular automata. Int J Light Electron Optics. 2016;15:

[16] Sasamal TN, Singh AK, Ghanekar U. Design of non-restoring binary array divider in majority logic-based QCA. Electronics Letters. 2016;52(24):

[17] Kianpour M, Nadooshan RS. A novel modular decoder implementation in quantum-dot cellular automata (QCA).

[18] Kianpour M, Nadooshan RS. A novel quantum dot cellular automata X-bit x 32-bit SRAM. In: IEEE Transactions on

In: International Conference on Nanoscience Technology and Societal Implications (NSTSI). 2011. pp. 1-5

[13] Kim SW, Swartzlander EE.

in Physics. 2017;7:1989-1995

[2] Bernstein K, Cavin RK, Porod W, Seabaugh A, Welser J. Device and architecture outlook for beyond CMOS switches. Proceedings of the IEEE. 2010;

[3] Bondy PK. Moore's law governs the silicon revolution. Proceedings of the

[4] Haron NZ, Hamdioui S. Why is CMOS scaling coming to an END? In: 3rd IEEE International Design and Test Workshop (IDT); 2008, pp. 98-103

[5] International Technology Roadmap for Semiconductors, Process Integration Devices and Structures (PIDS). Available

from: http://www.itrs.net/Links/ 2011ITRS/Home2011.htm, 2011 Edition

[6] Lent CS, Tougaw PD, Porod W, Bernstein GH. Quantum cellular automata. Nanotechnology. 1993;4:

[7] Angizi S, Sarmadi S, Sayedsalehi S, Navi K. Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata.

Microelectronics Journal. 2015;46:43-51

[8] Azghadi MR, Kavehie O, Navi K. A novel design for quantum-dot cellular automata cells and full adders. arXiv preprint arXiv:1204.2048; 2012

[9] Berzon D, Fountain TJ. A memory design in QCAs using the SQUARES formalism. In: Great Lakes Symposium

[10] Walus K, Vetteth A, Jullien G, Dimitrov V. Ram design using

on VLSI. 1999. pp. 166-169

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Figure 14. Effect of polarization on output of FIR filter due to temperature.

is decreased. Therefore, between 1 K and 7 K, the FIR circuit works efficiently. Over 7 K, the circuit falls down radically and produces incompatible outputs.
