6. Conclusion

Design of low-power high-speed FIR filter is always a challenge for DSP applications. In this article, a novel design of FIR filter architecture in the QCA technology has been presented. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 software. The proposed QCA FIR achieves up to 1 GHz frequency and consumes 1.6 mW power. By comparison of previous designs and the proposed design, it could be concluded that the proposed design has appropriate features and performance. Therefore, this work will provide better silicon area utilization, maximization of clock speed and very low-power consumption than traditional VLSI technology. It should be an important step towards highperformance and low-power design in this field. Future extensions, such as various applications based on this QCA FIR unit, could be investigated.
