4. QCA FIR implementation

The proposed QCA FIR filter consists of three principal components:


#### 4.1 QCA D flip-flop

Flip-flop is a circuit that may be used to store state information ("0" or "1" logic value). Here, the structure of the proposed D flip-flop is illustrated in Figure 7a which includes three majority gates and one inverter gate. The logic equation of the D flip-flop is represented by the following equation:

$$Q\_{(t)} = \mathbf{CLk.D} + \mathbf{CLk.Q\_{(t-1)}}$$

Figure 7b illustrates the proposed QCA flip-flop. It includes 79 cells with an area of 0.15 μm<sup>2</sup> . It takes five clock periods for the inputs to reach the output, and first meaningful output comes on the sixth clock.
