4.2.2 QCA 2 2 vedic multiplier

The block diagram of 2 2 bit Vedic multiplier is shown in Figure 12. Firstly, B0 is multiplied with A0; the generated partial product is considered as an LSB of final product.

Secondly, B0 is multiplied with A1,and B1 is multiplied with A0. To add the generated partial products (B0\*A1+ A0\*B1), a QCA half adder is required, which generates a 2-bit result (Carry and S1), in which S1 is considered as the second bit of the final product and Carry is saved as pre-carry for the next step.

Finally, B1 is multiplied with A1, and the overall product term will be obtained for 2 2 Vedic multiplier. Here, four majority gates and two half adder circuits are

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

used, and the output will be four bits (s0, s1, s2 and s3).

Figure 12. 2 2 block diagram.

87

Figure 11.

Proposed QCA layouts of 4-bit parallel binary full adder.

DOI: http://dx.doi.org/10.5772/intechopen.90193

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology… DOI: http://dx.doi.org/10.5772/intechopen.90193

Figure 11. Proposed QCA layouts of 4-bit parallel binary full adder.

Finally, B1 is multiplied with A1, and the overall product term will be obtained for 2 2 Vedic multiplier. Here, four majority gates and two half adder circuits are used, and the output will be four bits (s0, s1, s2 and s3).

half adder is composed by three majority gates and one inverter gate. Figure 9 shows the block diagram and the QCA layout of the proposed half adder. It consists

Proposed (a) logical diagram, (b) QCA layouts and (c) simulation result of full adder circuit.

parallel adder layout in size of 4-bit is depicted in Figure 11. It is designed by cascading one-half adder and three 1-bit adders. In this way, the carry out (Cout) is then transmitted to the carry in (Cin) of the next higher-order bit. The final outcome creates a sum of 4 bits plus a carry out (Cout 4). This design uses 2735 cells

path length of 61 clock zones which is designated by a blue dashed line.

the final product and Carry is saved as pre-carry for the next step.

sum and carry outputs. In addition, the proposed full adder consists of three majority gates and two inverters. Figure 10 depicts the block diagram and the QCA layout of the proposed full adder. For the proposed QCA full adder, the required number

The block diagram of 2 2 bit Vedic multiplier is shown in Figure 12. Firstly, B0 is multiplied with A0; the generated partial product is considered as an LSB of

Secondly, B0 is multiplied with A1,and B1 is multiplied with A0. To add the generated partial products (B0\*A1+ A0\*B1), a QCA half adder is required, which generates a 2-bit result (Carry and S1), in which S1 is considered as the second bit of

. It needs 16 clock phases to generate the

. It requires 16 clock phases. The

. This circuit has a critical

of 232 cells covering an area of 0.76 μm<sup>2</sup>

4.2.2 QCA 2 2 vedic multiplier

final product.

86

Figure 10.

cells is 349, and the required area is 0.76 μm<sup>2</sup>

Advances in Quantum Communication and Information

in its structure. It consists of a circuit area of 11.46 μm<sup>2</sup>

The proposed 2 2 multiplier takes only 1683 QCA cells with a region of 8.42 μm2 .The simulated result of the proposed Vedic multiplier confirms that the expected operation is correctly achieved with 60 clock zones delay as depicted in Figure 13.

4.3 QCA adder

reported in [35].

software [48].

Full adder [35] Full adder [46] Proposed full adder

Comparison of various full adders.

Table 2.

89

for low-power design in this area.

5. Results and discussions

DOI: http://dx.doi.org/10.5772/intechopen.90193

completed and verified by functional simulations.

Since the FIR output can be obtained using only the MSB bits of the Vedic multiplier output, for the proposed structure of FIR filter, we need a 4-bit QCA adder. The same 4-bit adder designed above is used in this subsection (Table 1).

Design of 4-Bit 4-Tap FIR Filter Based on Quantum-Dot Cellular Automata (QCA) Technology…

The complete QCA FIR design is implemented using the functional units discussed in the previous section. The implementation and the simulation of the proposed hardware designs are achieved by using QCADesigner 2.0.3 tool [45]. The coherence vector simulation engine is used for this purpose. Table 2 depicts the simulation parameters. In the first step, the sub-module schematic and layout is

These designs have been implemented using a free and a regular USE clock scheme. In addition, we have successfully demonstrated that sub-module design of FIR unit properly satisfies all logic and timing constraints by using the 4 4 USE grid with a square dimension of 5 5 QCA cells. In this direction, with a welldefined methodology and regular timing zones, this design is a standard candidate for fabrication. We note that our proposed entire system requires a huge number of QCA cells mostly due to the long wires necessary to delay compensation. Since the proposed FIR circuit based on QCA technology has started to bloom, we have only compared the full adder module with regular standard scheme circuits. Table 2 shows a comparison of the proposed full adder with some existing designs [35, 46]. The proposed full adder has 1.13, 56.9 and 11% improvements, respectively, in terms of cell count, area occupation and circuit latency as compared to that

In QCA technology, the power consumption of any circuit depends on the number of majority and inverter gates [47]. Therefore, this technology reduces more power than CMOS technology. The consumption of FIR unit in QCA-18 nm technology is valuing 1.6 mW. This value is carried out using QCADesigner-E

However, the QCA FIR circuit requires 97.74% lesser power consumption than the previous existing designs [49]. In addition, the proposed design of FIR filter can operate at a higher frequency (upper than 1 GHz) than the conventional solution, and it can be useful for future digital signal processing applications for providing excellent processing speed. The overall performance of the proposed QCA design is therefore superior to the existing techniques in terms of power consumption. In this way, we think that this work forms an essential step in the building of QCA circuits

Influence of temperature variations on the polarization of the proposed design has also been investigated. Figure 14 illustrates the effect of polarization on output of FIR circuit due to temperature variations. QCADesigner tool is used to observe this effect. By increasing temperature the AOP of any output cell of the QCA circuit

> 1.764 0.77 0.76

) Clock no. cycle

18 18 16

Design Cell count Area (μm2

353 324 349

Figure 13. The QCA implementation of 2 2 multiplier.

