4.2.1 QCA 4-bit parallel adder

The 4-bit adder performs computing function of the FIR filter. Therefore, the half and the full adder are used to construct the 4-bit binary adder. The proposed

Figure 10. Proposed (a) logical diagram, (b) QCA layouts and (c) simulation result of full adder circuit.

half adder is composed by three majority gates and one inverter gate. Figure 9 shows the block diagram and the QCA layout of the proposed half adder. It consists of 232 cells covering an area of 0.76 μm<sup>2</sup> . It needs 16 clock phases to generate the sum and carry outputs. In addition, the proposed full adder consists of three majority gates and two inverters. Figure 10 depicts the block diagram and the QCA layout of the proposed full adder. For the proposed QCA full adder, the required number cells is 349, and the required area is 0.76 μm<sup>2</sup> . It requires 16 clock phases. The parallel adder layout in size of 4-bit is depicted in Figure 11. It is designed by cascading one-half adder and three 1-bit adders. In this way, the carry out (Cout) is then transmitted to the carry in (Cin) of the next higher-order bit. The final outcome creates a sum of 4 bits plus a carry out (Cout 4). This design uses 2735 cells in its structure. It consists of a circuit area of 11.46 μm<sup>2</sup> . This circuit has a critical path length of 61 clock zones which is designated by a blue dashed line.
