**1. Introduction**

During the last decades, demands for increased performance of electronic devices have led to an extraordinary course of miniaturization of Complementary Metal Oxide Semiconductor (CMOS) devices. As this scaling law may soon reach its limit, researchers in modern microelectronics try to find solutions to extend Moore's law by using more conventional principles. Two major areas of research have been envisaged. The first aims to find solutions that will rely on the exiting existing technology and physical principles but on a smaller scale. As such, bottom-up nanoscale structures, such as semiconducting nanowires, carbon nanotubes or graphene, have been proposed as potential candidates for complementing Si technology. The second explores new concepts, which rely on introduction of novel functions, such as the development of on-chip optical interconnects or the introduction of spintronic devices in which not only the electron charge but also the electron spin that can carry information. On-chip optical interconnects imply integration of all the optical devices with the silicon microelectronic devices on silicon chips and they require an efficient Si-based optical source. In addition to the development of new generations of high-performance computation and communication systems, an integrated efficient optical source on silicon allows to bridge the gap between the microelectronic and optoelectronic industries. A Si-based optical source would allow developing silicon photonics and its diffusion toward extended new markets. It would also allow opening new possibilities with a strong economic potential by developing cost-effective devices intended for a large public diffusion. To date, numerous

approaches have been proposed to realize silicon-integrated optical sources, such as porous Si, epitaxial semiconducting silicides, Er-doped Si, Si nanocrystals or Ge/Si self-assembled quantum dots. However, all above approaches are challenged by the lack of enough gain to surpass materials losses to achieve net gain for laser action.

Semiconductor diode lasers are conventionally based on direct band gap materials due to the efficient radiative recombination of direct gap transitions. As discrete devices, direct gap III-V semiconductor lasers have achieved great success in many important applications, from telecommunications to DVD players. On the other hand, indirect semiconductors such as Si and Ge are traditionally considered unsuitable for laser diodes because the radiative recombination through indirect transition is inefficient as a result of a phonon-assisted process. However, compared to Si, pure Ge displays unique optical properties, the direct (Γ) valley of its conduction band is only 0.14 eV above the indirect (L) valleys at room temperature while it is larger than 2 eV in Si. In addition, while Si cannot be used for photodetector due to its transparency at near infrared wavelength band, Ge has strong direct band gap absorption below 1.55 μm and high-speed Ge photodetectors have been demonstrated. Of particular interest, it has been shown that application of a tensile strain in Ge allows lowering the energy difference between the Γ zone center valley and the indirect L valley. The tensile strain also lifts the degeneracy between heavy hole and light hole valence bands. On the other hand, n-type doping of Ge leads to a more efficient population of the zone center Γ valley and thus enhances optical recombination at the Brillouin zone center. The combination of both effects is expected to lead to significant optical gains at room temperature and to the demonstration of a laser.

Tensile strain can be induced in Ge via several approaches: applying external mechanical stress, growing Ge on a larger lattice parameter substrate, such as InGaAs or GeSn buffer layers, or use of thermal mismatch between Ge and Si. In the frame of this chapter, we have chosen to study tensile-strained and n-doped Ge layers epitaxially grown on Si. The motivation of our study is that this system is compatible with the mainstream Si technology. Concerning to the n-doping process, while in CVD, PH3 molecules are currently used as a precursor for n-doping, by means of MBE we could implement a specific doping cell using a GaP decomposition source to produce diphosphorus (P2) which has a higher sticking coefficient than tetrahedral white phosphorus (P4 molecules).

#### **1.1 The Moore's law or the scaling-down law**

Integrated circuits (ICs, also known as microchips or microcircuits) have been a major driving force to revolutionize electronic technology in the past few decades. ICs are nowadays used in almost all electronic equipment and devices and are the foundation of the current generation of computers. An IC is a miniaturized electronic circuit consisting of active devices, i.e., transistors and diodes, as well as interconnects elements or passive components (resistance and capacity). Among all these semiconductors, silicon (Si) is absolutely the most important and widely used material in the IC and semiconductor industry owing to its superior properties and low fabrication cost. Before 2005, silicon IC had been developed in an extraordinary pace for almost four decades, known as Moore's law that the number of transistors in an integrated circuit doubles roughly every 18 months [1]. Upon the increase of the number of transistors, each transistor also gets smaller, faster and cheaper. The scalability is the main reason of the tremendous success of many Si IC based technologies, such as Si complimentary metal-oxide-semiconductor (CMOS) technology, which is used to fabricate the central processing unit (CPU) of modern computers. The scalability of Si-CMOS technology is not only about the shrinkage of the dimensions of the devices, but also a number of other factors for maintaining

**71**

**Figure 1.**

*Relative delay vs. process technology node from 2008 ITRS [5].*

*New Material for Si-Based Light Source Application for CMOS Technology*

[4], which effectively breaks off traditional scaling in CMOS.

the power density while boosting the performance. For an ideal constant-field scaling [2], upon the shrinkage of all the physical dimensions by α (scaling factor), the depletion depth d also has to be shrunk by α to assure the device works properly. The reduction of the depletion depth requires the increase of doping Nd and the decrease of the applied voltage V by a same factor α since d ≈ √NdV [3]. A direct consequence of the scaling is the increased circuit density by α2, which dramatically reduces the manufacturing costs. A second important result is the increase of the circuit speed due to both the reduced transit time in transistors and the capacitance in RC delay. However, the applied voltage is found to be impossible to scale by α as continuously shrinking the dimensions because of constraints on the threshold bias in order to avoid rising standby power in the "off" state. Eventually, the applied voltage cannot be scaled anymore, which, unfortunately, already occurred a couple of years ago. This results in the increase of the electric field with the scaling, leading to the increase of the power density of the circuit. It has been shown that the passive power density becomes dominant below the device dimension of 130–65 nm regime

In order to further increase the clock frequency without the help of the scaling, the entire architecture should be re-examined. In today's CMOS technology, the intrinsic speed of the transistor is beyond the speed in any other components of the circuit. The intrinsic frequency of a commercial logic circuit transistor is in the order of 102 GHz [5], while other technologies can easily achieve even higher speed, such as SiGe transistors at 500 GHz [6]. Therefore, the speed bottleneck of the ICs results from propagation delay in the passive components, which is dominated by RC (resistance capacitance) delay. Thus, design a new interconnects system in ICs becomes the key to further enhancement of the speed. A couple of approaches have been investigated to replace the predominant aluminum (for electrical conduction) and silicon oxide (SiO2, for electrical insulation) interconnects including the use of copper and low-k dielectric materials (such as doped SiO2 or polymeric dielectrics)

Among all these attempts, the optical interconnect design implemented by silicon photonics is extremely promising and can be the potentially ultimate solution to this problem. As shown in **Figure 1**, according to the 2008 International Technology Roadmap for Semiconductors (ITRS) [5], with continued technology node scaling, the relative delay for logic devices and local interconnects decreases. However, global interconnects, especially global interconnects without repeaters, show a dramatic increase in delay time. All of these arguments show that the onchip interconnects are one of the major challenges for the future IC industry.

*DOI: http://dx.doi.org/10.5772/intechopen.84994*

to reduce the RC product.

#### *New Material for Si-Based Light Source Application for CMOS Technology DOI: http://dx.doi.org/10.5772/intechopen.84994*

*Silicon Materials*

approaches have been proposed to realize silicon-integrated optical sources, such as porous Si, epitaxial semiconducting silicides, Er-doped Si, Si nanocrystals or Ge/Si self-assembled quantum dots. However, all above approaches are challenged by the lack of enough gain to surpass materials losses to achieve net gain for laser action. Semiconductor diode lasers are conventionally based on direct band gap materials due to the efficient radiative recombination of direct gap transitions. As discrete devices, direct gap III-V semiconductor lasers have achieved great success in many important applications, from telecommunications to DVD players. On the other hand, indirect semiconductors such as Si and Ge are traditionally considered unsuitable for laser diodes because the radiative recombination through indirect transition is inefficient as a result of a phonon-assisted process. However, compared to Si, pure Ge displays unique optical properties, the direct (Γ) valley of its conduction band is only 0.14 eV above the indirect (L) valleys at room temperature while it is larger than 2 eV in Si. In addition, while Si cannot be used for photodetector due to its transparency at near infrared wavelength band, Ge has strong direct band gap absorption below 1.55 μm and high-speed Ge photodetectors have been demonstrated. Of particular interest, it has been shown that application of a tensile strain in Ge allows lowering the energy difference between the Γ zone center valley and the indirect L valley. The tensile strain also lifts the degeneracy between heavy hole and light hole valence bands. On the other hand, n-type doping of Ge leads to a more efficient population of the zone center Γ valley and thus enhances optical recombination at the Brillouin zone center. The combination of both effects is expected to lead to significant optical gains at room temperature and to the demonstration of a laser. Tensile strain can be induced in Ge via several approaches: applying external mechanical stress, growing Ge on a larger lattice parameter substrate, such as InGaAs or GeSn buffer layers, or use of thermal mismatch between Ge and Si. In the frame of this chapter, we have chosen to study tensile-strained and n-doped Ge layers epitaxially grown on Si. The motivation of our study is that this system is compatible with the mainstream Si technology. Concerning to the n-doping process, while in CVD, PH3 molecules are currently used as a precursor for n-doping, by means of MBE we could implement a specific doping cell using a GaP decomposition source to produce diphosphorus (P2) which has a higher sticking coefficient

than tetrahedral white phosphorus (P4 molecules).

Integrated circuits (ICs, also known as microchips or microcircuits) have been a major driving force to revolutionize electronic technology in the past few decades. ICs are nowadays used in almost all electronic equipment and devices and are the foundation of the current generation of computers. An IC is a miniaturized electronic circuit consisting of active devices, i.e., transistors and diodes, as well as interconnects elements or passive components (resistance and capacity). Among all these semiconductors, silicon (Si) is absolutely the most important and widely used material in the IC and semiconductor industry owing to its superior properties and low fabrication cost. Before 2005, silicon IC had been developed in an extraordinary pace for almost four decades, known as Moore's law that the number of transistors in an integrated circuit doubles roughly every 18 months [1]. Upon the increase of the number of transistors, each transistor also gets smaller, faster and cheaper. The scalability is the main reason of the tremendous success of many Si IC based technologies, such as Si complimentary metal-oxide-semiconductor (CMOS) technology, which is used to fabricate the central processing unit (CPU) of modern computers. The scalability of Si-CMOS technology is not only about the shrinkage of the dimensions of the devices, but also a number of other factors for maintaining

**1.1 The Moore's law or the scaling-down law**

**70**

the power density while boosting the performance. For an ideal constant-field scaling [2], upon the shrinkage of all the physical dimensions by α (scaling factor), the depletion depth d also has to be shrunk by α to assure the device works properly. The reduction of the depletion depth requires the increase of doping Nd and the decrease of the applied voltage V by a same factor α since d ≈ √NdV [3]. A direct consequence of the scaling is the increased circuit density by α2, which dramatically reduces the manufacturing costs. A second important result is the increase of the circuit speed due to both the reduced transit time in transistors and the capacitance in RC delay. However, the applied voltage is found to be impossible to scale by α as continuously shrinking the dimensions because of constraints on the threshold bias in order to avoid rising standby power in the "off" state. Eventually, the applied voltage cannot be scaled anymore, which, unfortunately, already occurred a couple of years ago. This results in the increase of the electric field with the scaling, leading to the increase of the power density of the circuit. It has been shown that the passive power density becomes dominant below the device dimension of 130–65 nm regime [4], which effectively breaks off traditional scaling in CMOS.

In order to further increase the clock frequency without the help of the scaling, the entire architecture should be re-examined. In today's CMOS technology, the intrinsic speed of the transistor is beyond the speed in any other components of the circuit. The intrinsic frequency of a commercial logic circuit transistor is in the order of 102 GHz [5], while other technologies can easily achieve even higher speed, such as SiGe transistors at 500 GHz [6]. Therefore, the speed bottleneck of the ICs results from propagation delay in the passive components, which is dominated by RC (resistance capacitance) delay. Thus, design a new interconnects system in ICs becomes the key to further enhancement of the speed. A couple of approaches have been investigated to replace the predominant aluminum (for electrical conduction) and silicon oxide (SiO2, for electrical insulation) interconnects including the use of copper and low-k dielectric materials (such as doped SiO2 or polymeric dielectrics) to reduce the RC product.

Among all these attempts, the optical interconnect design implemented by silicon photonics is extremely promising and can be the potentially ultimate solution to this problem. As shown in **Figure 1**, according to the 2008 International Technology Roadmap for Semiconductors (ITRS) [5], with continued technology node scaling, the relative delay for logic devices and local interconnects decreases. However, global interconnects, especially global interconnects without repeaters, show a dramatic increase in delay time. All of these arguments show that the onchip interconnects are one of the major challenges for the future IC industry.

**Figure 1.** *Relative delay vs. process technology node from 2008 ITRS [5].*

## **1.2 Silicon photonics**
