4. Software-defined radio (SDR)

Software-defined radio (SDR) [14] is a wireless communication device that employs software to perform most of the operations that are traditionally done by hardware in conventional radio circuits. Similar to the first radio receivers, SDR uses the same hardware for antenna and RF amplifiers. Unlike traditional radios that are based upon hardware to perform modulation and demodulation, softwaredefined radios are dependent on software to achieve filtering, modulation and demodulation. The IF signal is sampled and converted to digital signal that can be manipulated using software. Common modules between traditional radio and SDR include the antenna and the D/A and A/D converters. Some SDR implementations are freely available using field-programmable gate arrays (FPGA) [15].

### 5. Overview of 10-Mbps Ethernet

The core protocol of the Internet is the Ethernet protocol, which is based upon serial digital communications. This section provides an overview on the 10-Mbps Ethernet standard. The composition of Ethernet frames (at the MAC sub-layer) and the generation of differential signals at the physical interface (Phy) layer can be implemented on different hardware types as well as FPGA through hardware description language (HDL) code. For 10-Mbps Ethernet, Manchester encoding is utilised, where every bit of information is encoded as a transition from 1 to 0 or from 0 to 1.This is advantageous for the synchronisation between the sender and the receiver and for the recovery of the transmission clock. This encoding method prohibits sending consecutive zeros or ones, which appear as constant DC signal in a conventional RZ encoding. Since every bit of information is composed of two voltage levels, the reference clock is at 20 MHz (double the baud rate).

To identify the beginning of an Ethernet frame, a special pattern of bits is sent, which consists of preamble and a start of frame delimiter (SFD). The preamble and SFD are sent prior to the actual data. The pattern '10' is repeatedly sent, such that a total of 62 bits of 101010 are followed by 11. The last byte (SFD) is 10101011. In hexadecimal, the preamble is 7 bytes of 0x55 followed by a single SFD byte of 0xD5. The first byte that is sent is 0x55, whereas the byte 0xD5 is sent last. The leftmost bytes are sent first, of which the rightmost bits (LSB) are sent first. This is why the first byte in the preamble 10101010 is sent from right to left, as 0x55, i.e., the first bit to be transmitted, is 0. Data are usually transferred from an FPGA to the Ethernet port through a physical interface. Taking into consideration the mediaindependent interface (MII) standard, where the Phy interface communicates nibbles (4 bits) at a time, the SFD 10101011 byte is sent as 0xD and 0x5, since the

#### Telecommunications Protocols Fundamentals DOI: http://dx.doi.org/10.5772/intechopen.86338

lower nibble 0xD (in binary, 1011) is sent first starting by 1 (rightmost bit). The reference clocks are 2.5 and 25 MHz for 10-Mbps and 100-Mbps Ethernet, respectively. Reduced MII (RMII) and serial MII (SMII) are two reduced versions of MII, where 2-bit and 1-bit bus widths are used for the Phy, respectively. Compared to the 10-Mbps MII, the gigabit MII (GMII) communicates through 8-bit width bus with a reference clock of 125 MHz. However, the 10-Gbit MII (XGMII) standard deals with 32 bits of data at a time.

Some implementations of Ethernet on FPGA depend upon finite state machines (FSM) programmed in HDL, such as VHDL. Several open-source codes [13] offer Ethernet implementations in VHDL or Verilog.
