**2.4 Closed-loop IFOVC**

Both faster current control loop and speed control loop outputs [12] provide the reference voltages (Vsd, Vsq) and hence (Va, Vb, Vc) to SVM to get the stable operation of MC drive as shown in **Figure 6**.

**59**

**Figure 7.**

*Matrix Converter for More Electric Aircraft DOI: http://dx.doi.org/10.5772/intechopen.81056*

technique.

through the resistor.

**3. Regeneration detecting techniques**

**3.1 Power comparison (PC) technique**

of unidirectional switch (UDS), as in Eq. (1),

or equal to unity under all operating conditions.

*Block diagram of the power comparison (PC) technique for IPC method.*

Two novel techniques [18] are used to identify regeneration when step is applied to reverse the MC drive. These are (1) power comparison technique (PC) and (2) input voltage reference (IVR) technique. These techniques are responsible for generating pulses for regeneration control circuit (RCC) or electrical braking circuit (EBC) whenever regeneration is detected in the MC drive. In PC, output power is used as reference; hence, it is called PC technique similarly in IVR technique, the voltage across the small input filter capacitor and output power both are used as reference; hence, it is called IVR technique. The IVR technique is similar to and derived from conventional dynamic braking

To calculate the absolute value of output power of MC drive to achieve power comparison (PC) technique, the torque producing current (i\*sq) and measured rotor speed (ωre) are sensed. **Figure 7** shows the gate drive signal, which is generated for RCC of input power clamp (IPC) method. Here power dissipation through a resistor in the regeneration control circuit (RCC) is directly proportional to the duty cycle

Pdis ∝ D (1)

where D = duty cycle of the unidirectional switch and Pdis = power dissipation

Pmb = Tme ωmre (2)

The gate drive signals for RCC switches are generated by using field programmable gate array (FPGA) with digital signal processor (DSP). Here FPGA that receives input parameters (ωre, Te, i\*sq) from sensors is fed into DSP, which does all mathematical calculations to generate gate drive signal as shown in **Figure 7**, and again fed back to FPGA that is sending gate drive signal to the gate drive of UDS. The duty of UDS/BDS is linearly varying with respect to output negative

where Tme = electromagnetic torque and ωmre = speed of MC drive.

The duty cycle calculation requires the maximum electrical braking power (Pmb) to be calculated, as shown in Eq. (2). The duty cycle of the switches is then less than

**Figure 6.** *Closed-loop indirect field-oriented vector control (IFOVC) scheme.*

*Aerospace Engineering*

drive are converted into stationary reference frame (isα, isβ) and then viewed as two "dc" quantities (isd, isq). The direct axis or real axis component is responsible for the field producing current (isd) and is ideally maintained constant up to the motor synchronous speed. If d-axis is aligned with rotor flux vector (Ψ*r*), the system is said to be field oriented. The q-axis component is responsible for torque producing current (isq). These two vectors are orthogonal to each other so that the field current and

Both faster current control loop and speed control loop outputs [12] provide the reference voltages (Vsd, Vsq) and hence (Va, Vb, Vc) to SVM to get the stable opera-

torque current can be controlled independently [16–17].

*Closed-loop indirect field-oriented vector control (IFOVC) scheme.*

**2.4 Closed-loop IFOVC**

*Field orientation: Ψr is aligned with d-axis.*

**Figure 5.**

tion of MC drive as shown in **Figure 6**.

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**Figure 6.**
