**4. Measurements on test MIM capacitors and discussion**

MIM capacitors having the same structure to be used for the actuation pads of the RF MEMS switches have been realized, to study the charging mechanisms related to the materials used

Characterization and Modeling of Charging Effects in Dielectrics

Fig. 14. MIM structures used for the characterization.

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 245

Fig. 12. Bi-polar scheme imposed for the actuation of the switch S1.

for the device actuation. It is worth noting that the MIM is only an approximation of the real actuation, because in this case no residual air gap has to be considered between dielectric and metal bridge. For this reason the MIM should suffer for charging and de-charging effects different with respect to those measured on the real device for both time and kind of processes. On the other hand, it is important to know the properties of the material itself, because it will affect the operation of the device. The scheme and related equivalent circuit of the measurement setup used for characterizing the MIM is shown in Fig. 13. In Fig. 14 the two structures used for the MIM devices are also shown.

Fig. 13. Equivalent circuit for the measurement setup of the MIM Capacitors. A power supply provides the voltage Vg and the current I, both functions of the time t following a slow ramp. The device under test is a MIM simulating the actuation pad structure, schematized as a capacitor Ca with a high bulk resistance Ra in parallel with respect to Ca.

From the analysis of Fig. 13, the equations governing the voltages and currents on the equivalent lumped components can be written as:

$$\begin{aligned} I(t) &= I\_{Ca}(t) + I\_{Ra}(t) = C\_a \frac{dV\_{Ca}(t)}{dt} + \frac{V\_{Ca}(t)}{R\_a} = \frac{-V\_{Ca}(t) + V\_{\mathcal{g}}(t)}{R\_{cable}} \\ V\_{Ca}(t) &= V\_{\mathcal{g}}(t) - R\_{cable}I(t) \\ \frac{dV\_{Ca}(t)}{dt} &= \frac{dV\_{\mathcal{g}}(t)}{dt} - R\_{cable}\frac{dI(t)}{dt} \end{aligned} \tag{1}$$

for the device actuation. It is worth noting that the MIM is only an approximation of the real actuation, because in this case no residual air gap has to be considered between dielectric and metal bridge. For this reason the MIM should suffer for charging and de-charging effects different with respect to those measured on the real device for both time and kind of processes. On the other hand, it is important to know the properties of the material itself, because it will affect the operation of the device. The scheme and related equivalent circuit of the measurement setup used for characterizing the MIM is shown in Fig. 13. In Fig. 14 the

Fig. 13. Equivalent circuit for the measurement setup of the MIM Capacitors. A power supply provides the voltage Vg and the current I, both functions of the time t following a slow ramp. The device under test is a MIM simulating the actuation pad structure, schematized as a capacitor Ca with a high bulk resistance Ra in parallel with respect to Ca. From the analysis of Fig. 13, the equations governing the voltages and currents on the

() () () () () () ()

*Ca Ca Ca g*

*dV t V t V t Vt*

*dt R R*

*a cable*

(1)

Fig. 12. Bi-polar scheme imposed for the actuation of the switch S1.

two structures used for the MIM devices are also shown.

equivalent lumped components can be written as:

() () ()

*dV t dV t dI t <sup>R</sup> dt dt dt*

*Ca g cable Ca g*

*V t V t R It*

*It I t I t C*

*Ca Ra a*

( ) ( ) ( )

*cable*

Fig. 14. MIM structures used for the characterization.

Characterization and Modeling of Charging Effects in Dielectrics

PECVD

PECVD Oxide LF

PECVD

PECVD

1 BE: P TE: Al 1%Si

3 BE: P TE: Al 1%Si

4 BE: P TE: Al 1%Si

5 BE: P TE: Al 1%Si

7 BE: Al 1%Si+ Ti+TiN TE: Cr /Au

9 BE: Al 1%Si+ Ti+TiN TE: Cr /Au

10 BE: Al 1%Si+ Ti+TiN TE: Cr /Au

11 BE: Al 1%Si+ Ti+TiN TE: Cr /Au

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 247

Wafer # Dielectric Thick. [nm] 2% Sample # *VB* [volt] Charge

Nitride 98 C2 > 100 Few volt

TEOS 203 C1 > 100 Few volt

LTO 114 C6 100 Few volt

Nitride HF 100 C2 75 Few volt

LTO 114 C6 62 10-20 volt

Top 78 C2 47 ?

Nitride HF 100 C1 ? > 10 volt

Nitride LF 87 C6 35 > 10 volt

Table 1. Full list of the measured devices. The wafer #, with the bottom electrode (BE) and the top electrode (TE) are given, with the dielectric and deposition technique. P is for Polysilicon. The thickness is in nm 2%. The breakdown voltage *VB* is also shown, when it was possible to measure it. Charge injection is almost immediately recorded in many cases. HF

and LF stand for high frequency and low frequency of deposition respectively.

Injection

C3 > 100 Few volt C3 > 100 Few volt C4 > 100 Few volt C5 > 100 Few volt

C2 > 100 Few volt C5 > 100 Few volt

C3 < 40 ? C5 < 40 ?

C6 45 > 10 volt

From the above equations, it turns out that the measured value of *I(t)* when imposing *Vg(t)* will be given by using the following relation:

$$\left(1 + \frac{R\_{cable}}{R\_a}\right) I(t) = \mathbf{C}\_a \frac{d V\_{\rm g}(t)}{dt} + \frac{1}{R\_a} V\_{\rm g}(t) - \mathbf{C}\_a R\_{cable} \frac{d I(t)}{dt} \approx I(t) \tag{2}$$

The last assumption is valid when, as it can be reasonably assumed, *Rcable<<Ra*.

From the analysis of the measurements, it will be evident that when the dielectric material of the MIM behaves as an almost ideal dielectric, only the first term on the right hand of the above equation is important, and mainly a capacitive contribution is measured, as expected. Actually, the imposed ramp and the measured current will vary maintaining a constant ratio. On the other hand, because of the non-ideal response of the obtained dielectric material, a parallel resistance has to be included, to account, since the very beginning, for some free charges, and for the asymmetry in the capacitor itself, which has two parallel plates not equal between them for both dimensions and conductivity. So far, a capacitive response is obtained, strictly speaking, only at low voltage levels, and a small charge injection is immediately recorded, evidenced by a linear contribution typical of the second term in Eq. (2). An almost negligible contribution is also given by the last term of the same equation, being the derivative of the current very small and the resistance of the cable small too. The Poole-Frenkel effect, which should dominate the charging processes in the exploited dielectrics, begins to be evident when sufficiently high voltages are imposed after the first ramp, i.e. when *Vg* is in the order of tens of volt, and the recorded current suddenly increases. In this range, the response of the measured current follows a high-voltage law, while it is almost linear for lower values of *Vg*.

After some critical value of *Vg*, the picture given by Eq. (2) has to be strongly modified accounting for the change of both the conductivity and the polarization, which should influence at least the value of *Ra*.

In particular, the term describing the current flowing in *Ra* should be better identified by the formula suggested in [61] and [63] for high voltages. Moreover, we can map the time variable *t* into the applied voltage *Vg*, as the measurements are performed by using an *I* Vs *Vg* plot and, since the voltage is imposed by means of a linear ramp, we can also define *r*=*dVg/dt*=*const.*

In the region of non-linear response for the current Vs voltage, the trend looks like coherent with conclusions in [61], where a dependence on *Vg <sup>2</sup>* is expected, following also the conclusions in [63]. This will transform Eq. (2) in:

$$I(V\_g) = \mathbf{C}\_a \frac{dV\_g}{dt} + f(V\_g) - \mathbf{C}\_a R\_{cable} \frac{d\mathbf{l}}{dV\_g} \frac{dV\_g}{dt} = \mathbf{C}\_a \left(\mathbf{1} - R\_{cable} \frac{d\mathbf{l}}{dV\_g}\right) r + f(V\_g) \tag{3}$$

Which is valid until the breakdown occurs in the MIM structure, and *f(Vg)* is a function involving the applied voltage, which is linear like in Eq. (2) until a high voltage dependence is required, as mentioned in [61] and [63]. Because of the charging effect and of the current induced by the Poole-Frenkel effect, Eq. (3) has to be corrected again when a second ramp is applied before the dielectric is naturally de-charged, and the effect will be a current decrease at the same voltage level experienced during the previous ramp. In this case, the Poole-Frenkel current (linked to the current density by *IPF(Vg)=AJPF(Vg)* ) has to be included, having a sign which is opposite with respect to *I(Vg)*.


Table 1. Full list of the measured devices. The wafer #, with the bottom electrode (BE) and the top electrode (TE) are given, with the dielectric and deposition technique. P is for Polysilicon. The thickness is in nm 2%. The breakdown voltage *VB* is also shown, when it was possible to measure it. Charge injection is almost immediately recorded in many cases. HF and LF stand for high frequency and low frequency of deposition respectively.

246 Microelectromechanical Systems and Devices

From the above equations, it turns out that the measured value of *I(t)* when imposing *Vg(t)*

( ) <sup>1</sup> ( ) 1 () ( ) ( ) *<sup>g</sup> cable <sup>a</sup> g a cable*

From the analysis of the measurements, it will be evident that when the dielectric material of the MIM behaves as an almost ideal dielectric, only the first term on the right hand of the above equation is important, and mainly a capacitive contribution is measured, as expected. Actually, the imposed ramp and the measured current will vary maintaining a constant ratio. On the other hand, because of the non-ideal response of the obtained dielectric material, a parallel resistance has to be included, to account, since the very beginning, for some free charges, and for the asymmetry in the capacitor itself, which has two parallel plates not equal between them for both dimensions and conductivity. So far, a capacitive response is obtained, strictly speaking, only at low voltage levels, and a small charge injection is immediately recorded, evidenced by a linear contribution typical of the second term in Eq. (2). An almost negligible contribution is also given by the last term of the same equation, being the derivative of the current very small and the resistance of the cable small too. The Poole-Frenkel effect, which should dominate the charging processes in the exploited dielectrics, begins to be evident when sufficiently high voltages are imposed after the first ramp, i.e. when *Vg* is in the order of tens of volt, and the recorded current suddenly increases. In this range, the response of the measured current follows a high-voltage law,

After some critical value of *Vg*, the picture given by Eq. (2) has to be strongly modified accounting for the change of both the conductivity and the polarization, which should

In particular, the term describing the current flowing in *Ra* should be better identified by the formula suggested in [61] and [63] for high voltages. Moreover, we can map the time variable *t* into the applied voltage *Vg*, as the measurements are performed by using an *I* Vs *Vg* plot and, since the voltage is imposed by means of a linear ramp, we can also define

In the region of non-linear response for the current Vs voltage, the trend looks like coherent

() () 1 ( ) *g g g a g a cable a cable g*

Which is valid until the breakdown occurs in the MIM structure, and *f(Vg)* is a function involving the applied voltage, which is linear like in Eq. (2) until a high voltage dependence is required, as mentioned in [61] and [63]. Because of the charging effect and of the current induced by the Poole-Frenkel effect, Eq. (3) has to be corrected again when a second ramp is applied before the dielectric is naturally de-charged, and the effect will be a current decrease at the same voltage level experienced during the previous ramp. In this case, the Poole-Frenkel current (linked to the current density by *IPF(Vg)=AJPF(Vg)* ) has to be included,

*dV dI dV dI IV C f V CR C R r fV dt dV dt dV*

*g g*

*<sup>2</sup>* is expected, following also the

(3)

*<sup>R</sup> dV t dI t It C V t CR It R dt R dt*

(2)

*a a*

The last assumption is valid when, as it can be reasonably assumed, *Rcable<<Ra*.

will be given by using the following relation:

while it is almost linear for lower values of *Vg*.

with conclusions in [61], where a dependence on *Vg*

conclusions in [63]. This will transform Eq. (2) in:

having a sign which is opposite with respect to *I(Vg)*.

influence at least the value of *Ra*.

*r*=*dVg/dt*=*const.*

Characterization and Modeling of Charging Effects in Dielectrics

10-13

has been measured in other samples too.

10-12

10-11

1x10-10

Current [A]

1x10-9

1x10-8

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 249

W3C1

Fig. 16. I vs V for sample C1 in wafer #3 (W3C1, TEOS). A second ramp has been imposed after one minute, with clear evidence for the sample charging. The same behavior is exhibited by the other TEOS devices. The measurement has been repeated almost one day after the first one (21 hours later). In this case, the initial conditions are not yet restored, as it

with respect to the external DC field due to the actuation voltage. As a result, the sample experiences a decrease in the current flowing through the device. More in detail, the response of the dielectric is characterized, when the second ramp is applied, by a negative current for a relatively long time (40 sec ca. for a bias sweep rate of 50 mV/sec). This finding can be explained in terms of the additional contribution of the interface states, providing an increase in the number of charges. Actually, the trapping mechanism does not allow the injection of further charges, whereas the interface states can provide such an additional current, always opposite with respect to that induced by the external DC bias. This behavior has not been experienced 21 hours after because this long time allows the natural discharging process of the interface states. On the other hand, in almost one day, the trapped bulk charges had not the time for a full restoring of the initial conditions. In fact, during the third ramp a further positive shift of the voltage necessary for the onset of the charging process has been measured, in spite of the long time passed between the second and the third ramp. The contribution of the electric field generated by the trapped charges and by the interface states is also evidenced in the plot of Fig. 17 for wafer #1, but a bi-polar actuation scheme has been adopted, instead of the uni-polar one used for the previous measurement. The results in Fig. 17 have been interpreted as it follows: from 0 to 80 V, during the first ramp, the dielectric is charged. From 80 V to 0 it is like to impose a second ramp (negative or positive slope it does not matter) and the current is down-shifted. In the third ramp it looks like to have the dielectric fully de-charged because of the second ramp, as the current response is symmetric with respect to the first ramp. During the fourth ramp, the current is increased in absolute value, with a peak probably due to a "frozen" charge. After that, the fifth ramp gives a response qualitatively similar to the previous plot, but higher values are recorded because the residual current is in the same sense with respect to the imposed one. It is worth noting that the measurements have been re-normalized to the first quadrant, as negative currents correspond to negative voltages. The findings in Fig. 17 have been

0 10 20 30 40 50 60 70 80 90 100

Voltage (V)

W3C1 Second Ramp

W3C1 Third Ramp 21 hours later

Several wafers have been characterized, with repeated structures like those shown in Fig. 14. Actually, TEOS, LTO and Nitride (Si3N4) deposited following different methods have been obtained. Top and bottom electrodes have been changed too. The material and structural parameters are summarized in the following Table 1. Ramps of 0.05 and 0.1 V/s have been imposed. In particular, Wafer from #1 to #5 emulate the structure of the actuation pads, while from wafer #7 to #11 the situation of the underpass in the area of the bridge is proposed. A selection of the measurements performed on the samples is given in the following figures. The findings in Fig. 16 have been interpreted as the contribution of the electric field generated by: (i) trapped charges, and (ii) interface states. Both effects contribute in the opposite way

Fig. 15. I vs V for wafer #1 (W1). The same response (a) is obtained for different samples (C2, C3, C4, C5) having the same geometry and dielectric (nitride, Si3N4). Small differences can be seen only at low voltage and current values in (b) and can be attributed to the technological reliability. Actually, a charge injection is anyhow measurable, as the current response is not flat as a function of the applied voltage.

Several wafers have been characterized, with repeated structures like those shown in Fig. 14. Actually, TEOS, LTO and Nitride (Si3N4) deposited following different methods have been obtained. Top and bottom electrodes have been changed too. The material and structural parameters are summarized in the following Table 1. Ramps of 0.05 and 0.1 V/s have been imposed. In particular, Wafer from #1 to #5 emulate the structure of the actuation pads, while from wafer #7 to #11 the situation of the underpass in the area of the bridge is proposed. A selection of the measurements performed on the samples is given in the following figures. The findings in Fig. 16 have been interpreted as the contribution of the electric field generated by: (i) trapped charges, and (ii) interface states. Both effects contribute in the opposite way

> W1C5 W1C4 W1C3 W1C2

0 10 20 30 40 50 60 70

Voltage [V]

0 5 10 15 20 25 30

Voltage [V]

(b) Fig. 15. I vs V for wafer #1 (W1). The same response (a) is obtained for different samples (C2, C3, C4, C5) having the same geometry and dielectric (nitride, Si3N4). Small differences can

technological reliability. Actually, a charge injection is anyhow measurable, as the current

be seen only at low voltage and current values in (b) and can be attributed to the

(a)

 W1C5 W1C4 W1C3 W1C2

0.0

0.0

5.0x10-11

response is not flat as a function of the applied voltage.

1.0x10-10

Current [A]

1.5x10-10

2.0x10-10

2.0x10-9

4.0x10-9

Current [A]

6.0x10-9

8.0x10-9

Fig. 16. I vs V for sample C1 in wafer #3 (W3C1, TEOS). A second ramp has been imposed after one minute, with clear evidence for the sample charging. The same behavior is exhibited by the other TEOS devices. The measurement has been repeated almost one day after the first one (21 hours later). In this case, the initial conditions are not yet restored, as it has been measured in other samples too.

with respect to the external DC field due to the actuation voltage. As a result, the sample experiences a decrease in the current flowing through the device. More in detail, the response of the dielectric is characterized, when the second ramp is applied, by a negative current for a relatively long time (40 sec ca. for a bias sweep rate of 50 mV/sec). This finding can be explained in terms of the additional contribution of the interface states, providing an increase in the number of charges. Actually, the trapping mechanism does not allow the injection of further charges, whereas the interface states can provide such an additional current, always opposite with respect to that induced by the external DC bias. This behavior has not been experienced 21 hours after because this long time allows the natural discharging process of the interface states. On the other hand, in almost one day, the trapped bulk charges had not the time for a full restoring of the initial conditions. In fact, during the third ramp a further positive shift of the voltage necessary for the onset of the charging process has been measured, in spite of the long time passed between the second and the third ramp.

The contribution of the electric field generated by the trapped charges and by the interface states is also evidenced in the plot of Fig. 17 for wafer #1, but a bi-polar actuation scheme has been adopted, instead of the uni-polar one used for the previous measurement. The results in Fig. 17 have been interpreted as it follows: from 0 to 80 V, during the first ramp, the dielectric is charged. From 80 V to 0 it is like to impose a second ramp (negative or positive slope it does not matter) and the current is down-shifted. In the third ramp it looks like to have the dielectric fully de-charged because of the second ramp, as the current response is symmetric with respect to the first ramp. During the fourth ramp, the current is increased in absolute value, with a peak probably due to a "frozen" charge. After that, the fifth ramp gives a response qualitatively similar to the previous plot, but higher values are recorded because the residual current is in the same sense with respect to the imposed one. It is worth noting that the measurements have been re-normalized to the first quadrant, as negative currents correspond to negative voltages. The findings in Fig. 17 have been

Characterization and Modeling of Charging Effects in Dielectrics

5.0x10-10 1.0x10-9 1.5x10-9 2.0x10-9 2.5x10-9 3.0x10-9 3.5x10-9 4.0x10-9 4.5x10-9

1.0x10-10

2.0x10-10

Current [A]

3.0x10-10

4.0x10-10

Current [A]

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 251

interpreted again as the contribution of the electric field generated by the trapped charges and by the interface states, but in this case the field is in the same way with respect to the external one. Moreover, LPCVD Si3N4 shows a better response in terms of charge injection, because it happens at higher voltage values with respect to SiO2. When the second ramp is imposed (Fig. 17) the absolute value of the current is higher with respect to the first one. At this stage, a decharging effect is experienced, and the new charging process is evidenced at about 60 V, like in the first ramp, when it occurred at -60 V. It means that when a bi-polar scheme for the actuation is imposed, a fast de-charging is experienced, similarly to what occurs in the case of RF MEMS switches. In Fig. 18, the results for a TEOS based MIM in wafer #3 are shown. Looking at Fig. 18, a peak similar to the application of a negative bias experienced by the Si3N4 in the previous measurements (but less pronounced) is recorded also for TEOS during

W4C6

0 10 20 30 40 50 60 70 80

Voltage [V]

 W4C6 Second Ramp W4C6 Third Ramp

0 10 20 30 40 50

Voltage [V]

(b) Fig. 19. The sample C6 of wafer #4 (W4C6, LTO) was measured by repeating the ramp three times (a). The charging process is enhanced, but the effect is less important the third time, thus suggesting the possibility for a saturation of the charge injected in the sample, which is not visible in (b), being the voltage below the threshold for the onset of the charging effect.

(a)

W4C6

 W4C6 Second Ramp W4C6 Third Ramp

Fig. 17. The sample C3 from wafer #1 (W1C3, Si3N4) has been subjected to voltage ramps going forth and back up to a maximum value of 80 V. As a result, a down shift of the current response is obtained by applying a voltage from 0 to 80 V and back from 80 V to 0. Then, an almost symmetric response is obtained when a negative bias is imposed. A completely different trend is measured by decreasing the applied voltage to 0, and finally a current increase is experienced going again to 80 V. Similar responses have been obtained for other samples.

Fig. 18. The sample C1 of wafer #3 (TEOS) was measured by imposing a full cycle from positive to negative values and back to zero as it was in the data of Fig. 17.

**W1C3 from 0 V to 80 V W1C3 from 80 V to 0 V W1C3 from 0 V to -80 V W1C3 from -80 V to 0 V W1C3 from 0 V to 80 V**


Voltage [V]


Voltage [V]

Fig. 18. The sample C1 of wafer #3 (TEOS) was measured by imposing a full cycle from

positive to negative values and back to zero as it was in the data of Fig. 17.

Fig. 17. The sample C3 from wafer #1 (W1C3, Si3N4) has been subjected to voltage ramps going forth and back up to a maximum value of 80 V. As a result, a down shift of the current response is obtained by applying a voltage from 0 to 80 V and back from 80 V to 0.

A completely different trend is measured by decreasing the applied voltage to 0, and finally a current increase is experienced going again to 80 V. Similar responses have been obtained

> W3C1 from 0 V to 100 V W3C1 from 100 V to 0 V W3C1 from 0 V to -100 V W3C1 from -100 V to 0 V

Then, an almost symmetric response is obtained when a negative bias is imposed.

10-11

10-14

10-13

10-12

10-11

1x10-10

Current [A]

1x10-9

1x10-8

1x10-7

1x10-10

1x10-9

Current [A]

for other samples.

1x10-8

1x10-7

interpreted again as the contribution of the electric field generated by the trapped charges and by the interface states, but in this case the field is in the same way with respect to the external one. Moreover, LPCVD Si3N4 shows a better response in terms of charge injection, because it happens at higher voltage values with respect to SiO2. When the second ramp is imposed (Fig. 17) the absolute value of the current is higher with respect to the first one. At this stage, a decharging effect is experienced, and the new charging process is evidenced at about 60 V, like in the first ramp, when it occurred at -60 V. It means that when a bi-polar scheme for the actuation is imposed, a fast de-charging is experienced, similarly to what occurs in the case of RF MEMS switches. In Fig. 18, the results for a TEOS based MIM in wafer #3 are shown.

Looking at Fig. 18, a peak similar to the application of a negative bias experienced by the Si3N4 in the previous measurements (but less pronounced) is recorded also for TEOS during

Fig. 19. The sample C6 of wafer #4 (W4C6, LTO) was measured by repeating the ramp three times (a). The charging process is enhanced, but the effect is less important the third time, thus suggesting the possibility for a saturation of the charge injected in the sample, which is not visible in (b), being the voltage below the threshold for the onset of the charging effect.

Characterization and Modeling of Charging Effects in Dielectrics

10-14

0.0

1.0x10-10

2.0x10-10

3.0x10-10

4.0x10-10

Current [A]

5.0x10-10

the film preparation, reducing the contribution of free charges.

6.0x10-10 W7C6

10-12

1x10-10

Current [A]

1x10-8

1x10-6

1x10-4

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 253

 W5C2 Ramp 1 W5C2 Ramp 2 W5C2 Ramp 3 W5C2 Ramp 4


Voltage [V]

0 10 20 30 40 50

Voltage [V]

Fig. 22. I vs V for sample C6 in wafer #7 (W7C6, LTO). In this case the same structure present in the centre of the bridge is realized, with a multilayer as a bottom electrode and gold as the top one. Actually, an up-shift of the current is measured. As in the case of wafer #5 in Fig. 20, we were very close to the breakdown, around 62 volt, and this could change

the general characteristics of the sample when the second ramp is used.

Fig. 21. I vs V for wafer #5, sample 2 (W5C2, PECVD Nitride HF). It is worth noting that there is not serious current reversal as it happened to TEOS. Actually, the difference with respect to the results for TEOS could be due to a higher densification temperature during

W7C6 Second Ramp

the first ramp (0 - 100 V), probably due to the same proposed effect of "charge freezing" for the previous material. A negative current is obtained by means of the second ramp (100 - 0 V), increasing the absolute value. When *Vg* is low and the capacitor is almost de-charged, current is injected in the opposite way, changing the slope with respect to the first ramp. During the fourth ramp (-100 - 0 V) the sample is de-charged again and the charge is newly injected at low voltage values. Ramps have been imposed again on an LTO based MIM from wafer #4, and plots in Fig. 19 and 20 give evidence for charging mechanisms when always the positive voltage is applied in successive ramps. As expected, the charging process is enhanced, but the effect is less important the third time, thus suggesting the possibility for a saturation of the charge injected in the sample.

For the wafer #5 and #7 the measured current increases with respect to the first ramp, as it is shown from Fig. 20 to Fig. 22.

In the case of PECVD Oxide LF Top in wafer #9 the response is the same recorded for wafers from #1 to #5. As a further characterization, one sample was subjected to DC cycling in a way analogous to that used for real RF MEMS switches. Specifically, the sample C2 belonging to Wafer #1, was measured after imposing a uni-polar train of 104 pulses with amplitude *Vg*=50 V, having a pulse-width τ=250 ms and a period T=500 ms. Since the data obtained on this wafer are superimposed for all the measured samples, we used one C3 device, exactly equal to C2, as a reference structure. The result was an almost ideal dielectric response for low voltage values, i.e. a constant value for the current as a function of the applied voltage. The C3 structure, which was not "stressed" in the same way, behaves exactly as it was in the previous measurements, with a linear response of the current as a function of the voltage, starting from the very beginning. We believe that the above treatment was useful for helping the recombination of charges left free from the technological processes at the interface metaldielectric, which were sensitive to the voltage gradient experienced during the application of the train of pulses, and especially to the sudden gradient imposed in correspondence of the trailing and leading edge of the pulses. The result is presented in Fig. 23.

Fig. 20. Wafer #5 (PECVD Nitride HF). Shift of the current by using the same ramp and maximum value of the applied voltage, Vmax, in two successive measurements separated by one minute ca. After the first ramp the nature of the dielectric was dramatically changed, thus exhibiting an up-shift of the measured current. The second time we are almost at the breakdown voltage, around 70 V.

the first ramp (0 - 100 V), probably due to the same proposed effect of "charge freezing" for the previous material. A negative current is obtained by means of the second ramp (100 - 0 V), increasing the absolute value. When *Vg* is low and the capacitor is almost de-charged, current is injected in the opposite way, changing the slope with respect to the first ramp. During the fourth ramp (-100 - 0 V) the sample is de-charged again and the charge is newly injected at low voltage values. Ramps have been imposed again on an LTO based MIM from wafer #4, and plots in Fig. 19 and 20 give evidence for charging mechanisms when always the positive voltage is applied in successive ramps. As expected, the charging process is enhanced, but the effect is less important the third time, thus suggesting the possibility for a

For the wafer #5 and #7 the measured current increases with respect to the first ramp, as it is

In the case of PECVD Oxide LF Top in wafer #9 the response is the same recorded for wafers from #1 to #5. As a further characterization, one sample was subjected to DC cycling in a way analogous to that used for real RF MEMS switches. Specifically, the sample C2 belonging to Wafer #1, was measured after imposing a uni-polar train of 104 pulses with amplitude *Vg*=50 V, having a pulse-width τ=250 ms and a period T=500 ms. Since the data obtained on this wafer are superimposed for all the measured samples, we used one C3 device, exactly equal to C2, as a reference structure. The result was an almost ideal dielectric response for low voltage values, i.e. a constant value for the current as a function of the applied voltage. The C3 structure, which was not "stressed" in the same way, behaves exactly as it was in the previous measurements, with a linear response of the current as a function of the voltage, starting from the very beginning. We believe that the above treatment was useful for helping the recombination of charges left free from the technological processes at the interface metaldielectric, which were sensitive to the voltage gradient experienced during the application of the train of pulses, and especially to the sudden gradient imposed in correspondence of the

0 10 20 30 40 50 60 70

Fig. 20. Wafer #5 (PECVD Nitride HF). Shift of the current by using the same ramp and maximum value of the applied voltage, Vmax, in two successive measurements separated by one minute ca. After the first ramp the nature of the dielectric was dramatically changed, thus exhibiting an up-shift of the measured current. The second time we are almost at the

Voltage [V]

 W5 First Ramp W5 Second Ramp

trailing and leading edge of the pulses. The result is presented in Fig. 23.

10-12

1x10-10

1x10-8

Current [A]

breakdown voltage, around 70 V.

1x10-6

1x10-4

1x10-2

saturation of the charge injected in the sample.

shown from Fig. 20 to Fig. 22.

Fig. 21. I vs V for wafer #5, sample 2 (W5C2, PECVD Nitride HF). It is worth noting that there is not serious current reversal as it happened to TEOS. Actually, the difference with respect to the results for TEOS could be due to a higher densification temperature during the film preparation, reducing the contribution of free charges.

Fig. 22. I vs V for sample C6 in wafer #7 (W7C6, LTO). In this case the same structure present in the centre of the bridge is realized, with a multilayer as a bottom electrode and gold as the top one. Actually, an up-shift of the current is measured. As in the case of wafer #5 in Fig. 20, we were very close to the breakdown, around 62 volt, and this could change the general characteristics of the sample when the second ramp is used.

Characterization and Modeling of Charging Effects in Dielectrics

and a thin non-ideal dielectric layer.

restoring of the initial conditions.

obtained also by using this treatment.

coming out from the technological process.

1.0x10-10

2.0x10-10

Current [A]

3.0x10-10

4.0x10-10

exerted by the probes.

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 255

The breakdown is not critical for structures with Poly-silicon electrodes. Usually VB 100 volt is measured. On the other hand the dielectric looks like not ideal, because a linear response of the current vs the applied voltage is recorded already at low voltage levels, thus demonstrating a not negligible resistive contribution of the bulk of the capacitor. Another possible mechanism for conduction could be due to the presence of Poly-silicon: the dielectric interface can probably be considered as a sort of MOS with a poly-silicon p-doped

Charging of the samples is obtained when successive ramps are applied, as evidenced from the shift of the I vs V characteristics when the measurement is repeated, in times shorter or in the order of one minute, in the same direction (positive or negative voltages). Moreover, the de-charging is very slow, and also after one day there is not a complete spontaneous

Partial de-charging occurs when ramping the sample with positive and negative voltages, and re-combination of the charges is obtained, but the initial conditions are never re-

The measured trend of the current is never ideal for the exploited samples, and a linear response is always obtained as a function of the applied voltage, while a constant value is expected for an almost ideal dielectric material. So far, the second term in Eq. (2) is always present. By cycling one sample with pulses as high as 50 V such a response is flattened, maybe due to the re-combination of residual charges belonging to defects of the material

In the structures measured on wafer #7 to #11 some criticality in the measurements is evidenced, because of the small thickness of the metal contact, due to the pressure to be

In the case of the sample C3 belonging to wafer #1, with Si3N4, a linear fit has been superimposed to the I vs V curve to evaluate the resistance of the sample. The result is presented in Fig. 24, from which it turns out a slope of 0.410-11 -1, i.e. Ra=2.51011 .

> W1C3 FIT

Fig. 24. Linear Fit to evaluate the resistance offered by the MIM material, namely Si3N4,

before the onset of the Poole-Frenkel effect. A slope of 0.410-11 -1 is obtained.

0 10 20 30 40 50 60

Voltage [V]

Fig. 23. Comparison between the I vs V curves of a sample in wafer #1 (Nitride) before (reference sample C3) and after (sample C2) imposing 104 cycles of a DC train at 50 V.

From the analysis of data plotted in Fig. 22 and in Fig. 23, it turns out that the response with poly-silicon is still affected by charge injection also after the described processing for Vg>5 V, thus giving evidence for a residual contribution coming directly from the interface between doped poly-silicon and dielectric. In fact, the recorded curves are different with respect to the behaviour of MIMs manufactured by using top and bottom metal electrodes, because the poly-silicon electrodes are always characterized by a ramp behaviour in the first region. It is also worth noting that by using a DC train with a voltage value less than that needed for the charge injection onset (60 V), no shift is recorded (see Fig. 22).

From the I vs V plots and from data recorded in Table 1, we can draw the following general conclusions:

W1C3

0 20 40 60 80

Voltage [V]

W1C2 after 10e4 Cycling

012345

Voltage [V]

(b)

From the analysis of data plotted in Fig. 22 and in Fig. 23, it turns out that the response with poly-silicon is still affected by charge injection also after the described processing for Vg>5 V, thus giving evidence for a residual contribution coming directly from the interface between doped poly-silicon and dielectric. In fact, the recorded curves are different with respect to the behaviour of MIMs manufactured by using top and bottom metal electrodes, because the poly-silicon electrodes are always characterized by a ramp behaviour in the first region. It is also worth noting that by using a DC train with a voltage value less than that

From the I vs V plots and from data recorded in Table 1, we can draw the following general

Fig. 23. Comparison between the I vs V curves of a sample in wafer #1 (Nitride) before (reference sample C3) and after (sample C2) imposing 104 cycles of a DC train at 50 V.

needed for the charge injection onset (60 V), no shift is recorded (see Fig. 22).

(a)

W1C3

W1C2 after 10e4 Cycling

10-11

1.0x10-11

1.2x10-11

1.4x10-11

1.6x10-11

Current [A]

conclusions:

1.8x10-11

2.0x10-11

1x10-10

1x10-9

Current [A]

1x10-8

1x10-7

The breakdown is not critical for structures with Poly-silicon electrodes. Usually VB 100 volt is measured. On the other hand the dielectric looks like not ideal, because a linear response of the current vs the applied voltage is recorded already at low voltage levels, thus demonstrating a not negligible resistive contribution of the bulk of the capacitor. Another possible mechanism for conduction could be due to the presence of Poly-silicon: the dielectric interface can probably be considered as a sort of MOS with a poly-silicon p-doped and a thin non-ideal dielectric layer.

Charging of the samples is obtained when successive ramps are applied, as evidenced from the shift of the I vs V characteristics when the measurement is repeated, in times shorter or in the order of one minute, in the same direction (positive or negative voltages). Moreover, the de-charging is very slow, and also after one day there is not a complete spontaneous restoring of the initial conditions.

Partial de-charging occurs when ramping the sample with positive and negative voltages, and re-combination of the charges is obtained, but the initial conditions are never reobtained also by using this treatment.

The measured trend of the current is never ideal for the exploited samples, and a linear response is always obtained as a function of the applied voltage, while a constant value is expected for an almost ideal dielectric material. So far, the second term in Eq. (2) is always present. By cycling one sample with pulses as high as 50 V such a response is flattened, maybe due to the re-combination of residual charges belonging to defects of the material coming out from the technological process.

In the structures measured on wafer #7 to #11 some criticality in the measurements is evidenced, because of the small thickness of the metal contact, due to the pressure to be exerted by the probes.

In the case of the sample C3 belonging to wafer #1, with Si3N4, a linear fit has been superimposed to the I vs V curve to evaluate the resistance of the sample. The result is presented in Fig. 24, from which it turns out a slope of 0.410-11 -1, i.e. Ra=2.51011 .

Fig. 24. Linear Fit to evaluate the resistance offered by the MIM material, namely Si3N4, before the onset of the Poole-Frenkel effect. A slope of 0.410-11 -1 is obtained.

Characterization and Modeling of Charging Effects in Dielectrics

to the simple quadratic law in [61].

polarization is given by

for the Actuation of RF MEMS Ohmic Series and Capacitive Shunt Switches 257

Actually, in Figure 25, the linear fit is compared with the quadratic one, obtained by means of the formula f(Vg) = 0.410-11Vg+0.510-13(Vg-25)2.5. This result is a correction with respect

As a final comparison, the sample C4 in wafer #1 has been subjected to a measurement I vs V and fitted following the law (*Vg*-25)2.5. The result is shown in Fig. 26, where the displacement

On the time scale of interest to the RF-MEMS capacitive switches response (i.e. greater than 1 μsec) an electric field can interact with the dielectric film in two primary ways. These are: (i) the re-orientation of defects having an electric dipole moment, such as complex defects, and (ii) the translational motion of charge carriers, which usually involve simple defects such as vacancies, ionic interstitials and defect electronic species. These processes give rise to the dipolar (PD) and the intrinsic space charge (PSC-i) polarization mechanisms, respectively. Moreover, when the dielectric is in contact with conducting electrodes charges are injected through the trap assisted tunneling and/or the Poole-Frenkel effect [69] giving rise to extrinsic space charge polarization (PSC-e) whose polarity is opposite with respect to the other two cases. In RF-MEMS capacitive switches during the actuation all the polarization mechanisms occur simultaneously and the macroscopic

Now, from elementary physics it is known that the electric displacement *D*, defined as the

field and *P* the dielectric material polarization. The resulting polarization *P* may be further

a) An almost instantaneous polarization due to the displacement of the electrons with respect to the nuclei. The time constant of the process is about 10-16 sec and defines the high

b) A delayed time dependent polarization *P*(*t*), which determines the dielectric charging in MEMS, starting from zero at *t*=0, due to the orientation of dipoles and the distribution of free charges in the dielectric, the dipolar and space charge polarization respectively. Moreover the growth of these polarization components may be described in the form of *Pt P jj j* <sup>0</sup> <sup>1</sup> *<sup>f</sup> <sup>t</sup>* . The index *j* refers to each polarization mechanisms, and *fj*(*t*) are

> *t*

stretch factor. If *β*=1 the charging/discharging process is governed by the Debye law. In disordered systems like the amorphous oxides, which possess a degree of disorder, *β*<1 and

In the case of a MEMS switch that operates under the waveforms in Fig. 4, the dielectric is subjected to charging when the bridge is in the DOWN position and discharging in the UP position, independently of the ON or OFF functionality of the device. More specifically, when a uni-polar pulse train is applied (Fig. 4 (a)) then the device is subjected to contact-less

the charging/discharging process is described by the stretched exponential law.

total charge density on the electrodes, will be given by *D EP* <sup>0</sup>

divided into two parts according to the time constant response [70]:

frequency dielectric constant that is related to the refractive index.

exponential decay functions of the form exp

*P PP P tot D SC i SC e* (4)

, where *E* is the applied

. Here *τ* is the process time and *β* the

due to charging is evidenced, and it has to be attributed to the Poole-Frenkel Effect.

**5. Dielectric polarization and Poole-Frenkel effect in RF MEMS and MIM** 

Fig. 25. Linear and quadratic fit for the measured current vs the applied voltage when the sample C3 belonging to wafer #1 (W1C3, Si3N4) is biased. Up to 25-30 V a linear dependence is obtained, while an almost quadratic law is found for Vg>25 V.

Fig. 26. Measurement of the C4 sample belonging to wafer #1. The red curve is for the first ramp imposed to the sample, and the green one is the response after the second ramp, one minute after the first one. The azure and blue curves refer to the linear and quadratic response respectively (low and high voltage values). The green curve is shifted due to the onset of the Poole-Frenkel effect, which lowers the current response at the same voltage.

Considering the area of the MIM A=(44010-6)2 m2 and the thickness d=0.110-6 m, the resistivity of the material will be =ARa/d=4.841011 m, or =2.0710-12 -1m-1, thus confirming the high resistivity of the material, but a non-ideal response in terms of dielectric behavior [67].

 W1C3 FITlinear FITquad

Fig. 25. Linear and quadratic fit for the measured current vs the applied voltage when the sample C3 belonging to wafer #1 (W1C3, Si3N4) is biased. Up to 25-30 V a linear dependence

W1C4

 W1C4 after 1 min W1C4 linear fit W1C4 quadratic fit

2.0x10-10

is obtained, while an almost quadratic law is found for Vg>25 V.

0.0

2.0x10-10

4.0x10-10

6.0x10-10

Current [A]

behavior [67].

8.0x10-10

1.0x10-9

4.0x10-10

6.0x10-10

Current [A]

8.0x10-10

1.0x10-9

0 10 20 30 40 50 60 70 80 90 100

0 10 20 30 40 50 60

Voltage [V]

Fig. 26. Measurement of the C4 sample belonging to wafer #1. The red curve is for the first ramp imposed to the sample, and the green one is the response after the second ramp, one minute after the first one. The azure and blue curves refer to the linear and quadratic response respectively (low and high voltage values). The green curve is shifted due to the onset of the Poole-Frenkel effect, which lowers the current response at the same voltage.

Considering the area of the MIM A=(44010-6)2 m2 and the thickness d=0.110-6 m, the resistivity of the material will be =ARa/d=4.841011 m, or =2.0710-12 -1m-1, thus confirming the high resistivity of the material, but a non-ideal response in terms of dielectric

Voltage [V]

Actually, in Figure 25, the linear fit is compared with the quadratic one, obtained by means of the formula f(Vg) = 0.410-11Vg+0.510-13(Vg-25)2.5. This result is a correction with respect to the simple quadratic law in [61].

As a final comparison, the sample C4 in wafer #1 has been subjected to a measurement I vs V and fitted following the law (*Vg*-25)2.5. The result is shown in Fig. 26, where the displacement due to charging is evidenced, and it has to be attributed to the Poole-Frenkel Effect.
