**Active Matrix Driving and Circuit Simulation**

## Makoto Watanabe

*Sony Mobile Display Corporation Japan* 

### **1. Introduction**

This chapter explains the principle of active matrix driving which is the most popular driving method used in current liquid crystal displays (LCDs). It then discusses issues that designers must overcome to avoid the malfunctioning and introduces a liquid crystal model for conducting circuit simulations to optimize the circuit parameters efficiently.

#### **1.1 Equivalent circuit of a pixel in LCDs**

The equivalent circuit of a pixel operated by active matrix driving is shown in Fig. 1.

Data lines are connected to a data driver for generating the signal pulses for the picture data. Scan lines are connected to a scan driver for generating the scan pulses which enable the addressing driving. Vsig and Vg are applied to the data lines and scan lines, respectively. The thin film transistor (TFT) has three terminals of MOS transistors, and each terminal gate, drain, and source is connected to a scan line, a data line, and a pixel electrode, respectively. Cgs means the parasitic capacitance between the gate and source terminal in the TFT. Liquid crystal is injected into the gap between the pixel electrode and the counter backplane electrode, and it forms a liquid crystal cell capacitance (Clc). Clc is a variable capacitor that changes value according to the applied voltage between the pixel electrode and a counter backplane electrode. The voltage of the pixel electrode and counter backplane electrode are denoted by Vpix and Vcom, respectively. The storage capacitor is denoted Csc, and it is connected in parallel to Clc. Its function is to hold charges on a pixel electrode while the TFT is switched off.

#### **1.2 Timing chart for each signal pulse**

Fig. 2 shows the wave forms applied to each bus line and electrode. The period during which the pixel electrode voltage (Vpix) is higher than the counter electrode voltage (Vcom) is called the "plus frame" (Fig.2 (a)), whereas the period during which Vpix is lower than Vcom is called the "minus frame" (Fig.2 (b)). The plus and minus frames are switched every frame period (Tf).

When the voltage of the gate terminal connecting to the scan line rise to a high level, the resistance between the drain and source terminals becomes very low (Ron). As a result, electrical charges flow into the pixel electrode from the data line till the voltage of the pixel electrode achieves the voltage of the data line during the writing time (Tw). This process is called the "Charge Process". When the voltage of the scan line starts to drop, the pixel electrode voltage shows a negative shift ∆Vfd because of the coupling with the gate terminal

Active Matrix Driving and Circuit Simulation 107

same. As stated above, there are three stages (a) Charge Process (b) Hold Process (c) Coupling Process. In the following, the operation and key design points of the circuit are

Let us begin by explaining the relationships among the frame time (Tf), hold time (Th) and write time (Tw). The frame time (Tf) is generally taken to be 1/60 (sec) for historical reasons. For an application which cannot be allowed to have a flicker malfunction, however, the frame time is usually set to less than 1/60 (sec). The reason why flicker malfunction occurs will be explained later. In Fig. 2, ∆t is called the "write time margin" and it means the offset time between the scan line pulse and the data line pulse. (Tw+∆t)=Tf/N is satisfied if there are N scan lines. For instance, Tw+∆t=7.3μ(sec) in the case of high-definition TVs which have 1125 scan lines with Tf=1/120(sec)≅8.3m(sec). The write time margin (∆t) is usually designed to be around 2μ(sec), although it depends on the expected amount of pulse decay. Consequently, Tw is about 5μ(sec). Strictly speaking, the hold time (Th) should be of the difference between the frame time (Tf) and (Tw+∆t). However, considering that Tw+∆t is on the order of microseconds, the hold time (Th) can

When TFT behaves just as an electrical switch, it operates in the linear region of the MOS transistor (Vds<Vgs-Vth). Vds is the voltage between the drain and source terminal, Vgs is the voltage between the gate and source terminal, and Vth is the threshold voltage of the TFT. In the linear region, the current between the drain and source terminal (Ids) can be

*<sup>W</sup> I C V VV ds ox gs th ds <sup>L</sup>*

Here μ is mobility, Cox is the gate insulator capacitance per unit, and L and W are the channel length and width. Therefore, the resistance while the TFT is switched on (Ron) can

> *Vds* <sup>1</sup> *Ron <sup>I</sup> <sup>W</sup> ds C VV ox gs th <sup>L</sup>*

As shown in Fig. 2, the source voltage of the TFT during a plus frame is higher than that during a minus frame. In other words, Vgs is smaller in a plus frame than in a minus frame. Therefore, according to Eq.(2), Ron becomes higher in a plus frame than in a minus frame.

*RC C C* ( ) *on on gs sc lc*

general, the TFT and the voltage applied to bus lines are designed so as to satisfy

The charge time (Tw) should be sufficiently long compared with the time constant

Referring to the equivalent circuit in Fig. 1, the time constant (

(1)

(3)

(2)

*on* ) for charging to the pixel

*on* . In

explained in detail.

**1.2.1 Charge process** 

described as (Sze, 1981)

electrode can be described as

be expressed as

Tw=3 *on* ~6*on* .

be approximated to be the frame time (Tf).

Fig. 1. Equivalent circuit of LCD panel operated with active matrix driving

Fig. 2. Timing chart for each signal pulse applied to bus lines and electrodes

via the gate-source capacitance of TFT (Cgs) . This process is called the "Coupling Process". ∆Vfd is generally called the feed-through voltage. When the voltage of the scan line becomes low, the resistance between the drain and source terminal becomes very high (Roff) . Ideally charges on the pixel electrode are kept for a hold time (Th) until TFT is switched on at the beginning of the next frame and the pixel electrode voltage keeps constant value. However some amount of current leaks out between the drain and source terminal, and in turn, the charges on the pixel electrode decreases gradually during the hold time (Th). This process is called the "Hold Process". The counter electrode voltage (Vcom) is just set to be the central value between the pixel electrode voltages in the plus and minus frames. By setting Vcom in this manner, we can obtain a constant transmittance that does not depend upon the frame; that is, we can get a flicker-free image since the applied voltages in both frames are the

Fig. 1. Equivalent circuit of LCD panel operated with active matrix driving

Fig. 2. Timing chart for each signal pulse applied to bus lines and electrodes

via the gate-source capacitance of TFT (Cgs) . This process is called the "Coupling Process". ∆Vfd is generally called the feed-through voltage. When the voltage of the scan line becomes low, the resistance between the drain and source terminal becomes very high (Roff) . Ideally charges on the pixel electrode are kept for a hold time (Th) until TFT is switched on at the beginning of the next frame and the pixel electrode voltage keeps constant value. However some amount of current leaks out between the drain and source terminal, and in turn, the charges on the pixel electrode decreases gradually during the hold time (Th). This process is called the "Hold Process". The counter electrode voltage (Vcom) is just set to be the central value between the pixel electrode voltages in the plus and minus frames. By setting Vcom in this manner, we can obtain a constant transmittance that does not depend upon the frame; that is, we can get a flicker-free image since the applied voltages in both frames are the same. As stated above, there are three stages (a) Charge Process (b) Hold Process (c) Coupling Process. In the following, the operation and key design points of the circuit are explained in detail.

Let us begin by explaining the relationships among the frame time (Tf), hold time (Th) and write time (Tw). The frame time (Tf) is generally taken to be 1/60 (sec) for historical reasons. For an application which cannot be allowed to have a flicker malfunction, however, the frame time is usually set to less than 1/60 (sec). The reason why flicker malfunction occurs will be explained later. In Fig. 2, ∆t is called the "write time margin" and it means the offset time between the scan line pulse and the data line pulse. (Tw+∆t)=Tf/N is satisfied if there are N scan lines. For instance, Tw+∆t=7.3μ(sec) in the case of high-definition TVs which have 1125 scan lines with Tf=1/120(sec)≅8.3m(sec). The write time margin (∆t) is usually designed to be around 2μ(sec), although it depends on the expected amount of pulse decay. Consequently, Tw is about 5μ(sec). Strictly speaking, the hold time (Th) should be of the difference between the frame time (Tf) and (Tw+∆t). However, considering that Tw+∆t is on the order of microseconds, the hold time (Th) can be approximated to be the frame time (Tf).

#### **1.2.1 Charge process**

When TFT behaves just as an electrical switch, it operates in the linear region of the MOS transistor (Vds<Vgs-Vth). Vds is the voltage between the drain and source terminal, Vgs is the voltage between the gate and source terminal, and Vth is the threshold voltage of the TFT. In the linear region, the current between the drain and source terminal (Ids) can be described as (Sze, 1981)

$$I\_{ds} = \mu C\_{ox} \left(\frac{W}{L}\right) \left(V\_{\mathcal{GS}} - V\_{\text{fl}}\right) V\_{ds} \tag{1}$$

Here μ is mobility, Cox is the gate insulator capacitance per unit, and L and W are the channel length and width. Therefore, the resistance while the TFT is switched on (Ron) can be expressed as

$$R\_{\rm ON} = \frac{V\_{\rm ds}}{I\_{\rm ds}} = \frac{1}{\mu \mathcal{C}\_{\rm ox} \left(\frac{\mathcal{W}}{L}\right) \left(V\_{\mathcal{S}^S} - V\_{\rm th}\right)}\tag{2}$$

As shown in Fig. 2, the source voltage of the TFT during a plus frame is higher than that during a minus frame. In other words, Vgs is smaller in a plus frame than in a minus frame. Therefore, according to Eq.(2), Ron becomes higher in a plus frame than in a minus frame. Referring to the equivalent circuit in Fig. 1, the time constant ( *on* ) for charging to the pixel electrode can be described as

$$
\tau\_{\rm om} = R\_{\rm om} (\mathbf{C}\_{\rm gs} + \mathbf{C}\_{\rm lc} + \mathbf{C}\_{\rm sc}) \tag{3}
$$

The charge time (Tw) should be sufficiently long compared with the time constant *on* . In general, the TFT and the voltage applied to bus lines are designed so as to satisfy Tw=3 *on* ~6*on* .

Active Matrix Driving and Circuit Simulation 109

The second factor is the capacitance between the gate and source terminal (Cgs), which depends on the state (on or off) of the TFT. Fig. 4. shows a cross-sectional view of a general a-Si TFT. While TFT is the on-state (Fig.4 (a)), a conducting channel forms at the bottom of the a-Si layer and a capacitance between the channel and gate electrode (Con) has been generated. Half of Con can be regarded as Cgs in the on-state of TFT. A conducting channel does not form while TFT is the off-state (Fig.4 (b)). Therefore, Cgs during the off-state is the same as the capacitance between the source and gate electrode (Coff). Fig. 5 shows the

dependence of Cgs on Vgs.

Fig. 4. Gate–source capacitance (On state / Off state)

Fig. 5. Dependence of Cgs on the applied voltage

The cut-off voltage which TFT changes form on-state to off-state is Vgs=Vth.

plus frame is smaller than it is in a minus frame since Con/2 is bigger than Coff.

The equation for ΔVfd is updated by taking this behavior into account. In Eq. (6), ΔVfd in a

*(C / 2)(V (V V )) on gon PIX C ((V V ) V ) off th goff PIX th Vfd C /2 C C C C C on lc sc off lc sc*

(6)

#### **1.2.2 Hold process**

The TFT switching-off resistance (Roff) cannot be expressed with a simple equation like Ron since it has complicated physical mechanisms (Jacunski, 1999). We note that ambient light dramatically decreases Roff. Referring to the equivalent circuit in Fig.1, the time constant ( *OFF* ) for holding charges on the pixel electrode can be described as

$$
\tau\_{\rm off} = \mathbb{R}\_{\rm off} \left( \mathbb{C}\_{\mathcal{S}^S} + \mathbb{C}\_{\rm lc} + \mathbb{C}\_{\rm SC} \right) \tag{4}
$$

The time constant *OFF* should be sufficiently long compared with the hold time (Th).

#### **1.2.3 Coupling process**

When the voltage for the scan line falls from the high level (Vgon) to the low-level (Vgoff), the pixel electrode voltage shifts by the coupling with the parasitic capacitance (Cgs) between the gate and the source terminal of the TFT. This voltage shift of the pixel electrode is called the feed-through voltage (ΔVfd), and it can be expressed as

$$
\Delta V\_{fd} = \frac{C\_{\mathcal{GS}}}{C\_{\mathcal{GS}} + C\_{lc} + C\_{\text{sc}}} \left( V\_{\mathcal{S}^{\text{on}}} - V\_{\text{goff}} \right) \tag{5}
$$

As discussed earlier, ΔVfd should be a constant independent of any conditions since it uniquely determines the voltage for the counter backplane electrode. This is important in that we can get high-quality flicker free images and get high reliability without residual DC voltages in the liquid crystal cell. ΔVfd, however, depends on various factors, such as Clc, Cgs, and pulse wave distortions.

The first factor is the liquid crystal capacitance (Clc) dependences on the voltage between the pixel and counter electrode. As this voltage increases, the electric field across the liquid crystal cell gets reinforced and the liquid crystal molecule tends to reorient itself along the electric field direction. Consequently, the capacitance of the liquid crystal cell (Clc) increases as shown in Fig. 3. From Eq.(5), ΔVfd changes in accordance with the value of Clc.

Fig. 3. Clc dependences on the applied voltage to liquid crystal

The TFT switching-off resistance (Roff) cannot be expressed with a simple equation like Ron since it has complicated physical mechanisms (Jacunski, 1999). We note that ambient light dramatically decreases Roff. Referring to the equivalent circuit in Fig.1, the time constant

When the voltage for the scan line falls from the high level (Vgon) to the low-level (Vgoff), the pixel electrode voltage shifts by the coupling with the parasitic capacitance (Cgs) between the gate and the source terminal of the TFT. This voltage shift of the pixel electrode

> *Cgs Vfd C CC V V gon goff gs sc lc*

As discussed earlier, ΔVfd should be a constant independent of any conditions since it uniquely determines the voltage for the counter backplane electrode. This is important in that we can get high-quality flicker free images and get high reliability without residual DC voltages in the liquid crystal cell. ΔVfd, however, depends on various factors, such as Clc,

The first factor is the liquid crystal capacitance (Clc) dependences on the voltage between the pixel and counter electrode. As this voltage increases, the electric field across the liquid crystal cell gets reinforced and the liquid crystal molecule tends to reorient itself along the electric field direction. Consequently, the capacitance of the liquid crystal cell (Clc) increases

as shown in Fig. 3. From Eq.(5), ΔVfd changes in accordance with the value of Clc.

Fig. 3. Clc dependences on the applied voltage to liquid crystal

(4)

(5)

should be sufficiently long compared with the hold time (Th).

) for holding charges on the pixel electrode can be described as

is called the feed-through voltage (ΔVfd), and it can be expressed as

 () *off off lc RC C C gs sc* 

**1.2.2 Hold process** 

The time constant *OFF*

**1.2.3 Coupling process** 

Cgs, and pulse wave distortions.

( *OFF* 

The second factor is the capacitance between the gate and source terminal (Cgs), which depends on the state (on or off) of the TFT. Fig. 4. shows a cross-sectional view of a general a-Si TFT. While TFT is the on-state (Fig.4 (a)), a conducting channel forms at the bottom of the a-Si layer and a capacitance between the channel and gate electrode (Con) has been generated. Half of Con can be regarded as Cgs in the on-state of TFT. A conducting channel does not form while TFT is the off-state (Fig.4 (b)). Therefore, Cgs during the off-state is the same as the capacitance between the source and gate electrode (Coff). Fig. 5 shows the dependence of Cgs on Vgs.

Fig. 4. Gate–source capacitance (On state / Off state)

Fig. 5. Dependence of Cgs on the applied voltage

The cut-off voltage which TFT changes form on-state to off-state is Vgs=Vth. The equation for ΔVfd is updated by taking this behavior into account. In Eq. (6), ΔVfd in a plus frame is smaller than it is in a minus frame since Con/2 is bigger than Coff.

$$
\Delta V\_{fd} = \frac{(\text{C}\_{\text{on}\text{I}} \text{ } / \text{ } \text{2})(V\_{\text{gon}\text{I}} - (V\_{\text{PlX}} + V\_{\text{fl}}))}{\text{C}\_{\text{on}\text{I}} \text{ } / \text{2} + \text{C}\_{\text{l}\text{c}} + \text{C}\_{\text{SC}}} + \frac{\text{C}\_{\text{off}}((V\_{\text{PlX}} + V\_{\text{fl}}) - V\_{\text{goff}})}{\text{C}\_{\text{off}} + \text{C}\_{\text{l}\text{c}} + \text{C}\_{\text{SC}}} \tag{6}
$$

Active Matrix Driving and Circuit Simulation 111

which same pixel polarities are aligned in a checker pattern (Fig.7 (a)) and normally white mode which has the maximum transmittance with no applied voltage (Fig.7 (b)). It will, however, be very easy for readers to apply them to other types of active matrix LCDs.

When a checker pattern of gray and black is displayed in background, as shown in Fig.8 (a),

Fig. 7. Driving method assumed in the example

we see an unexpected gradational change vertically (Fig.8 (b)).

**2.1 Shading** 

Fig. 8. Shading

The third factor is the influence of a scan pulse distortion on ΔVfd. The scan pulse significantly decays at pixels farther away from the scan driver. Such a decay could cause problems especially in larger displays (Watanabe, 1996). Fig. 6(a) shows the feed through voltage (ΔVfd) under the condition that the scan pulse does not decay. Fig.6 (b) shows the feed through voltage (ΔVfd) under the condition that the scan pulse decays.

Fig. 6. Influence of a scan pulse distortion on the feed through voltage

When the scan pulse decays, it takes a finite amount of time Δt for the TFT to switch off. During Δt, current Ids(t) continues to flow from a data line to the pixel electrode. Therefore, ΔVfd is modified to Eq. (7).

$$
\Delta V\_{fd\\_d} = \Delta V\_{fd} - \frac{1}{C\_{\mathcal{S}^\text{S}} + C\_{lc} + C\_{\text{SC}}} \left[ \overset{\Delta t}{0} I\_{ds} \text{(t)} dt \tag{7}
$$

According to Eq.(7), the effective feed through voltage ΔVfd\_d is smaller in a minus frame than in a plus frame because the cut-off voltage becomes lower and Δt becomes longer in a minus frame than in a plus frame.

#### **2. Display quality problems**

This section discusses some issues LCD designers must overcome in order to avoid such as shading, cross-talk (vertical / horizontal), flicker malfunctions, low response time and charge leakage in liquid crystal cells.

Even though active matrix driving is a dramatic improvement upon passive matrix driving (Pochi, 1999), the above malfunctions remains in the specific displayed patterns, so-called "killer pattern".

Here we explain what these modes of malfunction are, why they appear, and how to suppress them. This information would be very useful for designers not only in optimizing the design parameters but also in analyzing problems they may encounter. These problems tend to be apparent especially in large and high-resolution LCDs. In the example illustrated in the following explanation, we assume that the treated LCDs are of the dot inversion type

The third factor is the influence of a scan pulse distortion on ΔVfd. The scan pulse significantly decays at pixels farther away from the scan driver. Such a decay could cause problems especially in larger displays (Watanabe, 1996). Fig. 6(a) shows the feed through voltage (ΔVfd) under the condition that the scan pulse does not decay. Fig.6 (b) shows the

feed through voltage (ΔVfd) under the condition that the scan pulse decays.

Fig. 6. Influence of a scan pulse distortion on the feed through voltage

ΔVfd is modified to Eq. (7).

minus frame than in a plus frame.

**2. Display quality problems** 

charge leakage in liquid crystal cells.

"killer pattern".

When the scan pulse decays, it takes a finite amount of time Δt for the TFT to switch off. During Δt, current Ids(t) continues to flow from a data line to the pixel electrode. Therefore,

> <sup>1</sup> ( ) \_ <sup>0</sup> *<sup>t</sup> V V I t dt fd d fd C CC ds gs sc lc*

According to Eq.(7), the effective feed through voltage ΔVfd\_d is smaller in a minus frame than in a plus frame because the cut-off voltage becomes lower and Δt becomes longer in a

This section discusses some issues LCD designers must overcome in order to avoid such as shading, cross-talk (vertical / horizontal), flicker malfunctions, low response time and

Even though active matrix driving is a dramatic improvement upon passive matrix driving (Pochi, 1999), the above malfunctions remains in the specific displayed patterns, so-called

Here we explain what these modes of malfunction are, why they appear, and how to suppress them. This information would be very useful for designers not only in optimizing the design parameters but also in analyzing problems they may encounter. These problems tend to be apparent especially in large and high-resolution LCDs. In the example illustrated in the following explanation, we assume that the treated LCDs are of the dot inversion type

(7)

which same pixel polarities are aligned in a checker pattern (Fig.7 (a)) and normally white mode which has the maximum transmittance with no applied voltage (Fig.7 (b)). It will, however, be very easy for readers to apply them to other types of active matrix LCDs.

Fig. 7. Driving method assumed in the example

## **2.1 Shading**

When a checker pattern of gray and black is displayed in background, as shown in Fig.8 (a), we see an unexpected gradational change vertically (Fig.8 (b)).

Active Matrix Driving and Circuit Simulation 113

Fig. 10. Pixel voltage modulation by data lines via parasitic capacitances

vertical crosstalk is the same as that for the shading (Fig.9).

in the pixel B and decreases by δV in the pixel C.

of the background.

of shading (Eq. (8)).

When a white window is displayed in the middle of the display area on a background composes of a gray tone and black checker pattern as shown in Fig.11 (a), we see an unexpected brightness in the area above and below the window (Fig.11 (b)). The area above the window becomes darker and the area below the window becomes lighter than the tone

To explain the mechanism causing such vertical crosstalk, we will assume that the shading phenomenon discussed earlier can be ignored. However, readers should be aware that shading and vertical crosstalk can coexist on the same screen. The circuit model to explain

Fig. 12 (a) shows the voltage fluctuation in the data line and the pixel electrode voltage at point A in Fig. 11. Fig. 12 (b) shows the voltage fluctuation in the data line and the pixel electrode at points B and C in Fig. 11. Note that there is a white window below B and above C. In a pixel at B and C, the symmetrical relationship between the fluctuation of the data line and that of the adjacent data line disappears, when the period for drawing the widow starts or ends. Consequently, the pixel electrode voltage is modulated via the parasitic capacitance Cdp. The modulated voltage δV can be expressed by using the same equation as in the case

The brightness difference between pixels B and C can be explained as follows. The voltage of pixel B is affected by drawing the window after the charge process is completed in this frame. Meanwhile the voltage of the pixel C is affected before the charge process is completed in this frame. Therefore the voltage across the liquid crystal cell increases by δV

The mechanism causing this phenomenon arises from the parasitic capacitance Cdp between the data line, or adjacent data line, and the pixel electrode (see Fig. 9). Here, we shall discuss the voltage modulation of a pixel electrode by the data line voltage (Vsig) and adjacent data line voltage (Vsiga) via the parasitic capacitance Cdp.

Fig. 9. Circuit model for the shading phenomenon

Fig.10 (a) shows the fluctuation in the data line voltage and Fig. 10 (b) shows the voltages of pixel electrodes located at A, B and C in Fig.8. At the moment when the frame changes from odd(even) to even(odd), the symmetry between the fluctuation in a data line and that of the adjacent data line is offset by the value of ΔVsig. Consequently, the voltage of the pixel electrode is modulated via Cdp. The modulated voltage of a pixel electrode δV can be expressed as

$$
\delta V = \frac{2C\_{dp}}{C\_{tot}} \Delta V\_{sig} \tag{8}
$$

Here Ctot means the total of the capacitances connected to the pixel electrode. The voltages of the pixels in the upper area of display (such as Pixel A), is updated immediately after modulation at the moment of a frame switching. In contrast, pixels in the lower area of display (such as Pixel C) remain influenced by the modulation remains for a long time up to one frame. Therefore, the average voltage across a liquid crystal cell is higher in Pixel C than in Pixels A and B and a lower transmittance is obtained in the case of the normally white mode of LCDs. To reduce the shading level, designers should try to decrease the parasitic capacitance Cdp or to increase Ctot , for example, by using larger Csc in the pixel design process.

#### **2.2 Vertical crosstalk**

There is a variety of modes for a vertical crosstalk (Watanabe, 1997). Here we will describe the coupling mode between a pixel electrode and a data line: this sort of crosstalk will be a critical issue when very high-resolution LCDs become available.

The mechanism causing this phenomenon arises from the parasitic capacitance Cdp between the data line, or adjacent data line, and the pixel electrode (see Fig. 9). Here, we shall discuss the voltage modulation of a pixel electrode by the data line voltage (Vsig) and

Fig.10 (a) shows the fluctuation in the data line voltage and Fig. 10 (b) shows the voltages of pixel electrodes located at A, B and C in Fig.8. At the moment when the frame changes from odd(even) to even(odd), the symmetry between the fluctuation in a data line and that of the adjacent data line is offset by the value of ΔVsig. Consequently, the voltage of the pixel electrode is modulated via Cdp. The modulated voltage of a pixel electrode δV can be

<sup>2</sup>*Cdp V Vsig Ctot*

Here Ctot means the total of the capacitances connected to the pixel electrode. The voltages of the pixels in the upper area of display (such as Pixel A), is updated immediately after modulation at the moment of a frame switching. In contrast, pixels in the lower area of display (such as Pixel C) remain influenced by the modulation remains for a long time up to one frame. Therefore, the average voltage across a liquid crystal cell is higher in Pixel C than in Pixels A and B and a lower transmittance is obtained in the case of the normally white mode of LCDs. To reduce the shading level, designers should try to decrease the parasitic capacitance Cdp or to increase Ctot , for example, by using larger Csc in the pixel design

There is a variety of modes for a vertical crosstalk (Watanabe, 1997). Here we will describe the coupling mode between a pixel electrode and a data line: this sort of crosstalk will be a

critical issue when very high-resolution LCDs become available.

(8)

adjacent data line voltage (Vsiga) via the parasitic capacitance Cdp.

Fig. 9. Circuit model for the shading phenomenon

expressed as

process.

**2.2 Vertical crosstalk** 

Fig. 10. Pixel voltage modulation by data lines via parasitic capacitances

When a white window is displayed in the middle of the display area on a background composes of a gray tone and black checker pattern as shown in Fig.11 (a), we see an unexpected brightness in the area above and below the window (Fig.11 (b)). The area above the window becomes darker and the area below the window becomes lighter than the tone of the background.

To explain the mechanism causing such vertical crosstalk, we will assume that the shading phenomenon discussed earlier can be ignored. However, readers should be aware that shading and vertical crosstalk can coexist on the same screen. The circuit model to explain vertical crosstalk is the same as that for the shading (Fig.9).

Fig. 12 (a) shows the voltage fluctuation in the data line and the pixel electrode voltage at point A in Fig. 11. Fig. 12 (b) shows the voltage fluctuation in the data line and the pixel electrode at points B and C in Fig. 11. Note that there is a white window below B and above C. In a pixel at B and C, the symmetrical relationship between the fluctuation of the data line and that of the adjacent data line disappears, when the period for drawing the widow starts or ends. Consequently, the pixel electrode voltage is modulated via the parasitic capacitance Cdp. The modulated voltage δV can be expressed by using the same equation as in the case of shading (Eq. (8)).

The brightness difference between pixels B and C can be explained as follows. The voltage of pixel B is affected by drawing the window after the charge process is completed in this frame. Meanwhile the voltage of the pixel C is affected before the charge process is completed in this frame. Therefore the voltage across the liquid crystal cell increases by δV in the pixel B and decreases by δV in the pixel C.

Active Matrix Driving and Circuit Simulation 115

Window drawing period

(a) Pixel A

*VSIG* 

*VSIG V*

Fig. 12. Pixel voltage modulation by data lines via parasitic capacitances

for drawing the window than in the other periods. ΔVcom and *com*

1

(b) Pixel B (above window), Pixel C (below window)

voltage, as shown in Fig.15 (b). We can see the level of the modulation is lower in the period

() () *V CV com <sup>C</sup> d i com sig i comtot <sup>i</sup>*

Here Rcom means the total resistance of the counter electrode, and Ccomtot means the total

Referring to Fig. 16, if the wave for the counter electrode has not been restored to the DC level (Vcom) during the write time (Tw), an unexpected voltage will be applied to a liquid crystal cell Vlc' (>Vlc). The situation in pixel A is similar to Fig.16 (a) since the counter electrode voltage is not so modulated during pixel A's write time. Meanwhile the situation in a pixel B is similar to Fig.16 (b) since the counter electrode voltage is too modulated during pixel B's write time. As a result, we can see horizontal crosstalk since the effective voltage across the liquid crystal cell is bigger in pixel B than in pixel A. The best way to suppress the horizontal crosstalk is to decrease the counter electrode resistance. It is,

however, difficult since optical properties such as transparency are often sacrificed.

*<sup>V</sup> VSIG*

*VSIG*

in Fig. 15(b) can be

Vcom

Vcom

Vcom

*VSIG*

(9)

*com com R Ccomtot* (10)

*VSIG*

*VSIG*

*VSIG*

approximately expressed as

Vsig

Vsiga

Vsig

Vsiga

Pixel B

Pixel C

Pixel A

*VSIG*

*VSIG*

capacitance connected to the counter electrode.

Fig. 11. Vertical crosstalk

To reduce vertical crosstalk, as is done in shading, designers should try to decrease the parasitic capacitance Cdp or increase Ctot, for example, by using a larger Csc in a pixel design process.

#### **2.3 Horizontal crosstalk**

When a white window is displayed in the middle of a display area with a background consisting of a striped pattern with gray tones and black as shown in Fig. 13(a), we see the brightness difference in the left and the right areas of the window compared with other area (Fig.13 (b)).

Here we should consider that the tones in the right and left area of the window are rather closed to the expected value compared with the tone in the other area.

Now let us explain the mechanism causing the horizontal crosstalk. Several models of the horizontal crosstalk have been proposed (Kimura, 1994). One of the circuit models is shown in Fig.14. The DC voltage Vcom is provided to a backplane counter electrode at the edge of the display area, which means there are no supply points for Vcom in the display area. Each node of this resistance network in the counter electrode is unintentionally connected to the data line via the parasitic capacitance Cd-com. The voltage of the counter electrode is thus modulated by the fluctuation of the data line voltage (Vsig).

Fig. 15 (a) shows the fluctuation in the voltage of all data lines in Fig. 13. The numbers on the left of the waves correspond to those assigned to the data lines in Fig. 13. The combination of the voltage fluctuations for all data lines modulates the counter electrode

To reduce vertical crosstalk, as is done in shading, designers should try to decrease the parasitic capacitance Cdp or increase Ctot, for example, by using a larger Csc in a pixel

When a white window is displayed in the middle of a display area with a background consisting of a striped pattern with gray tones and black as shown in Fig. 13(a), we see the brightness difference in the left and the right areas of the window compared with other area

Here we should consider that the tones in the right and left area of the window are rather

Now let us explain the mechanism causing the horizontal crosstalk. Several models of the horizontal crosstalk have been proposed (Kimura, 1994). One of the circuit models is shown in Fig.14. The DC voltage Vcom is provided to a backplane counter electrode at the edge of the display area, which means there are no supply points for Vcom in the display area. Each node of this resistance network in the counter electrode is unintentionally connected to the data line via the parasitic capacitance Cd-com. The voltage of the counter electrode is thus

Fig. 15 (a) shows the fluctuation in the voltage of all data lines in Fig. 13. The numbers on the left of the waves correspond to those assigned to the data lines in Fig. 13. The combination of the voltage fluctuations for all data lines modulates the counter electrode

closed to the expected value compared with the tone in the other area.

modulated by the fluctuation of the data line voltage (Vsig).

Fig. 11. Vertical crosstalk

**2.3 Horizontal crosstalk** 

design process.

(Fig.13 (b)).

(b) Pixel B (above window), Pixel C (below window)

Fig. 12. Pixel voltage modulation by data lines via parasitic capacitances

voltage, as shown in Fig.15 (b). We can see the level of the modulation is lower in the period for drawing the window than in the other periods. ΔVcom and *com* in Fig. 15(b) can be approximately expressed as

$$
\Delta V\_{com} = \frac{1}{C\_{comtot}} \sum\_{\text{I}} C\_{d(i)-com} \Delta V\_{sig(i)} \tag{9}
$$

$$
\pi\_{\text{com}} = R\_{\text{com}} C\_{\text{comtot}} \tag{10}
$$

Here Rcom means the total resistance of the counter electrode, and Ccomtot means the total capacitance connected to the counter electrode.

Referring to Fig. 16, if the wave for the counter electrode has not been restored to the DC level (Vcom) during the write time (Tw), an unexpected voltage will be applied to a liquid crystal cell Vlc' (>Vlc). The situation in pixel A is similar to Fig.16 (a) since the counter electrode voltage is not so modulated during pixel A's write time. Meanwhile the situation in a pixel B is similar to Fig.16 (b) since the counter electrode voltage is too modulated during pixel B's write time. As a result, we can see horizontal crosstalk since the effective voltage across the liquid crystal cell is bigger in pixel B than in pixel A. The best way to suppress the horizontal crosstalk is to decrease the counter electrode resistance. It is, however, difficult since optical properties such as transparency are often sacrificed.

Active Matrix Driving and Circuit Simulation 117

Fig. 15. Counter electrode voltage modulation by data lines via parasitic capacitances

Fig. 16. Change in effective voltages across a liquid crystal cell resulting from counter

electrode voltage modulation.

Fig. 13. Horizontal crosstalk

Fig. 14. Circuit model for horizontal crosstalk

Fig. 13. Horizontal crosstalk

Fig. 14. Circuit model for horizontal crosstalk

Fig. 16. Change in effective voltages across a liquid crystal cell resulting from counter electrode voltage modulation.

Active Matrix Driving and Circuit Simulation 119

Fig. 18. Adjustment of the counter electrode voltage (Vcom) to suppress flicker (V+ = V-)

## **2.4 Flicker**

When a gray tone and black checker pattern is displayed in the background as shown in Fig. 17 (a), we sometimes can see the flicker caused by the brightness differences between odd frames and even frames (Fig17 (b)). Note that all the gray tone dots with gray tone have the same polarity during one frame.

When a gray tone and black checker pattern is displayed in the background as shown in Fig. 17 (a), we sometimes can see the flicker caused by the brightness differences between odd frames and even frames (Fig17 (b)). Note that all the gray tone dots with gray tone have the

**2.4 Flicker** 

Fig. 17. Flicker

same polarity during one frame.

Fig. 18. Adjustment of the counter electrode voltage (Vcom) to suppress flicker (V+ = V-)

Active Matrix Driving and Circuit Simulation 121

If the response time of LCDs is not sufficiently short, the outline of the moving object on the screen blurs, as shown in Fig. 20. Although the properties of the liquid crystal material and cell structures are the dominant factors determining the response time (Wittek, 2008), the

Moving object Moving object

High response time Low response time

Fig. 21 shows the effect of a storage capacitor (Csc) reducing the response time of LCDs. If Csc is not sufficiently large (solid line), the response time is much longer than the case of the ideal operation (dashed line). In the worst case, the transmittance cannot achieve the

> 1st Frame

Fig. 21. Dependence of the response time on storage capacitance (Csc)

Transmittance

2nd Frame

16 msec Time

3rd Frame

Low response time

(low Csc)

4th Frame

**2.5 Low response time** 

influence of the circuit parameters is not negligible.

Fig. 20. Influence of response time on displayed image

expected level even in the saturated state.

Ideal (large enough Csc)

Fig. 19. Brightness fluctuation due to mis-adjustment of the counter electrode voltage(Vcom)

Ideally, the counter electrode voltage (Vcom) should be set so that the voltage between the pixel electrode and the counter electrode *V V pix com* is the same from one frame to the next (V+=V- in Fig.18). In so doing, we cannot see any flicker since the voltage across a liquid crystal cell stays constant value. However, as discussed earlier, it is too difficult to adjust Vcom such that V+=V- under any condition since the feed-through voltage ∆Vfd depends on several factors: variation of Clc, Cgs, pulse distortion, and so on. If the voltage in each frame is not same (V+≠V-), a brightness fluctuation can be seen, as shown in Fig. 19. It is often said that the human eyes cannot perceive flicker of more than 50Hz. Therefore, making a frame rate much higher than 100Hz is one of the effective means to suppress flicker.

## **2.5 Low response time**

120 Features of Liquid Crystal Display Materials and Processes

Fig. 19. Brightness fluctuation due to mis-adjustment of the counter electrode voltage(Vcom) Ideally, the counter electrode voltage (Vcom) should be set so that the voltage between the pixel electrode and the counter electrode *V V pix com* is the same from one frame to the next (V+=V- in Fig.18). In so doing, we cannot see any flicker since the voltage across a liquid crystal cell stays constant value. However, as discussed earlier, it is too difficult to adjust Vcom such that V+=V- under any condition since the feed-through voltage ∆Vfd depends on several factors: variation of Clc, Cgs, pulse distortion, and so on. If the voltage in each frame is not same (V+≠V-), a brightness fluctuation can be seen, as shown in Fig. 19. It is often said that the human eyes cannot perceive flicker of more than 50Hz. Therefore, making a frame rate much higher than 100Hz is one of the effective means to

suppress flicker.

If the response time of LCDs is not sufficiently short, the outline of the moving object on the screen blurs, as shown in Fig. 20. Although the properties of the liquid crystal material and cell structures are the dominant factors determining the response time (Wittek, 2008), the influence of the circuit parameters is not negligible.

High response time Low response time

Fig. 20. Influence of response time on displayed image

Fig. 21 shows the effect of a storage capacitor (Csc) reducing the response time of LCDs. If Csc is not sufficiently large (solid line), the response time is much longer than the case of the ideal operation (dashed line). In the worst case, the transmittance cannot achieve the expected level even in the saturated state.

Fig. 21. Dependence of the response time on storage capacitance (Csc)

Active Matrix Driving and Circuit Simulation 123

An actual liquid crystal cell has a parasitic resistance because it includes many impurity

Therefore, even if the TFT works as an ideal switch, that is, the switching-off resistance (Roff) is infinite, the charge on the electrode cannot be kept during the hold process because

Here, we discuss the requirements of the circuit parameters in order to reduce the above influence. Fig. 23(a) shows the equivalent circuit for a pixel during the hold process with the assumption that the TFT is an ideal switch with an infinite resistance. The liquid crystal cell is composed of two electrodes with an area S and with a gap d, as shown in Fig. 23(b). The liquid crystal is injected into the gap between two electrodes. Clc, Rlc and Csc denote liquid crystal capacitance, parasitic resistance, and storage capacitance, respectively. Referring to Fig. 23(b), Rlc and Clc can be described as *R (d / S) LC* , *C (S / d) LC 0 r* . Here, ρ and, εr mean the resistivity and, permittivity of the liquid crystal material, and ε0 means the

The decay time constant (τ) for the voltage between two electrodes (Vcell) in Fig. 23(a) can

*C C R C C RC 1 <sup>1</sup>*

To keep the charge during the hold process, τ should be sufficiently long compared with the

*LC LC SC LC LC 0 r*

*0 r*

*SC*

Fig. 23. Charge leakage model with a parasitic resistance in the liquid crystal cell

*LC 0 r C Th <sup>1</sup> <sup>C</sup>*

Given Th = 16 (msec), **ε0** = 8.854x1012(F/m), **εr**=10, **ρ**=1010(Ω・cm), we find that Csc/Clc

*SC SC*

*SC*

*LC <sup>C</sup> 1 Th C* 

*LC LC*

(14)

(15)

(13)

*C C* 

ions. The resistivity of liquid crystal is normally on the order of 1010~1013(Ω・cm).

**2.6 Charge leakage in liquid crystal cells** 

vacuum permittivity.

hold time (Th) in Fig. 2.

Eq. (14) can be transformed into

should be designed to be more than 0.2.

be described as

of the parasitic resistance in the liquid crystal cell.

Now let us explain the mechanism of the low response time, as stated above using Fig. 22. In order to display the black pattern, V0 is applied to the liquid crystal capacitor and the storage capacitor (Csc). Here we should note that the liquid crystal capacitance (Clc0) is smaller just after the period of the charging process explained in section 1.2.1 because a white pattern was displayed in the previous frame and a finite amount of time is necessary to rotate the liquid crystal. The total accumulated charge (q0) on Csc and Clc0 can be described as

$$q\_0 = \left(\mathbf{C}\_{SC} + \mathbf{C}\_{LC0}\right) V\_0 \tag{11}$$

After that, during the hold process, the liquid crystal tries to align itself parallel to the electric field and the liquid crystal capacitance becomes larger (Clc1), as shown in Fig. 3. Because the total charge on the electrodes is constant (q0), the applied voltage between the electrodes (V1) can be described as

$$V\_1 = \frac{q\_0}{\mathcal{C}\_{SC} + \mathcal{C}\_{LC1}} V\_0 = \frac{\mathcal{C}\_{SC} + \mathcal{C}\_{LC0}}{\mathcal{C}\_{SC} + \mathcal{C}\_{LC1}} V\_0 = \frac{1 + \left(\mathcal{C}\_{LC0} \,/\, \mathcal{C}\_{SC}\right)}{1 + \left(\mathcal{C}\_{LC1} \,/\, \mathcal{C}\_{SC}\right)} V\_0 \tag{12}$$

In Eq. (12), we can see that V1 is smaller (larger) than V0 when Clc1 is larger (smaller) than Clc0. This means that the voltage applied to the liquid crystal cell drops (rises) until the pixel electrode is recharged in the next frame when the liquid crystal capacitance for the previous pattern is smaller (larger) than that for the latter pattern. Eq. (12) also shows that Csc should be sufficiently large compared with Clc0 and Clc1 in order to reduce the response time. This problem is especially evident in the ferroelectric liquid crystal, which has a large spontaneous polarization on its own.

Fig. 22. Applied voltage drop caused by the liquid crystal response

*qCCV 0 SC LC0 0* (11)

 

*V*<sup>0</sup> 1 0 *V V* ( )

(12)

Now let us explain the mechanism of the low response time, as stated above using Fig. 22. In order to display the black pattern, V0 is applied to the liquid crystal capacitor and the storage capacitor (Csc). Here we should note that the liquid crystal capacitance (Clc0) is smaller just after the period of the charging process explained in section 1.2.1 because a white pattern was displayed in the previous frame and a finite amount of time is necessary to rotate the liquid crystal. The total accumulated charge (q0) on Csc and Clc0 can be

After that, during the hold process, the liquid crystal tries to align itself parallel to the electric field and the liquid crystal capacitance becomes larger (Clc1), as shown in Fig. 3. Because the total charge on the electrodes is constant (q0), the applied voltage between the

> *0 SC LC0 LC0 SC 10 0 0 SC LC1 SC LC1 LC1 SC <sup>q</sup> C C 1 C /C VV V V C C C C 1 C /C*

In Eq. (12), we can see that V1 is smaller (larger) than V0 when Clc1 is larger (smaller) than Clc0. This means that the voltage applied to the liquid crystal cell drops (rises) until the pixel electrode is recharged in the next frame when the liquid crystal capacitance for the previous pattern is smaller (larger) than that for the latter pattern. Eq. (12) also shows that Csc should be sufficiently large compared with Clc0 and Clc1 in order to reduce the response time. This problem is especially evident in the ferroelectric liquid crystal, which

Csc Clc0 Csc Clc1

Fig. 22. Applied voltage drop caused by the liquid crystal response

Just after charging process During hold process

described as

electrodes (V1) can be described as

has a large spontaneous polarization on its own.

#### **2.6 Charge leakage in liquid crystal cells**

An actual liquid crystal cell has a parasitic resistance because it includes many impurity ions. The resistivity of liquid crystal is normally on the order of 1010~1013(Ω・cm).

Therefore, even if the TFT works as an ideal switch, that is, the switching-off resistance (Roff) is infinite, the charge on the electrode cannot be kept during the hold process because of the parasitic resistance in the liquid crystal cell.

Here, we discuss the requirements of the circuit parameters in order to reduce the above influence. Fig. 23(a) shows the equivalent circuit for a pixel during the hold process with the assumption that the TFT is an ideal switch with an infinite resistance. The liquid crystal cell is composed of two electrodes with an area S and with a gap d, as shown in Fig. 23(b). The liquid crystal is injected into the gap between two electrodes. Clc, Rlc and Csc denote liquid crystal capacitance, parasitic resistance, and storage capacitance, respectively. Referring to Fig. 23(b), Rlc and Clc can be described as *R (d / S) LC* , *C (S / d) LC 0 r* . Here, ρ and, εr mean the resistivity and, permittivity of the liquid crystal material, and ε0 means the vacuum permittivity.

The decay time constant (τ) for the voltage between two electrodes (Vcell) in Fig. 23(a) can be described as

$$\mathbf{r} = \mathbf{R}\_{LC} \left( \mathbf{C}\_{LC} + \mathbf{C}\_{SC} \right) = \mathbf{R}\_{LC} \mathbf{C}\_{LC} \left( \mathbf{1} + \frac{\mathbf{C}\_{SC}}{\mathbf{C}\_{LC}} \right) = \mathbf{e}\_0 \mathbf{e}\_r \mathbf{p} \left( \mathbf{1} + \frac{\mathbf{C}\_{SC}}{\mathbf{C}\_{LC}} \right) \tag{13}$$

To keep the charge during the hold process, τ should be sufficiently long compared with the hold time (Th) in Fig. 2.

$$
\pi = \varepsilon\_0 \varepsilon\_r \rho \left( 1 + \frac{C\_{SC}}{C\_{LC}} \right) \gg Th \tag{14}
$$

Eq. (14) can be transformed into

$$\frac{C\_{SC}}{C\_{LC}} \approx \frac{Th}{\varepsilon\_0 \varepsilon\_r \rho} - 1\tag{15}$$

Given Th = 16 (msec), **ε0** = 8.854x1012(F/m), **εr**=10, **ρ**=1010(Ω・cm), we find that Csc/Clc should be designed to be more than 0.2.

Fig. 23. Charge leakage model with a parasitic resistance in the liquid crystal cell

Active Matrix Driving and Circuit Simulation 125

between two electrodes and the cell gap in Fig.24. After solving for x(t) from this circuit, the

2 ( ) *Kd V xt <sup>i</sup> <sup>c</sup>* .

effective voltage Vi at time t is calculated as

Fig. 24. Schematic diagram of liquid crystal cell

Fig. 25. Macro-model for liquid crystal cell

## **3. Design optimization by circuit simulation**

A circuit simulation is a great tool for efficiently optimizing the design parameters given the complicated trade-off relationship among the electrical characteristics of displays. Although commercial circuit simulators can also be used for some design work, their device models are not detailed enough to have sufficient accuracy for liquid crystal capacitor and TFT since there are some important properties which are not considered in the implemented models into commercial simulator. To solve this problem, we have developed our own device models for a liquid crystal capacitor (Watanabe, 2007) and TFT (Ishihara, 2008) including the photo-leak effect. This section introduces the liquid crystal capacitor model as a representative. Moreover the Appendix provides codes written in VerilogA for implementing our device model into a circuit simulator.

## **3.1 Liquid crystal capacitor model**

To make competitive products, the optical and electrical characteristics of LCDs should simultaneously be optimized to the highest level. Liquid crystal cells behave as a non-liner history-dependent capacitors from the electrical point of view, and as light valves, the transmittance of which can be varied with an applied voltage from the optical point of view. The following presents a macro-model for liquid crystal cells that includes these electrical and optical behaviors. We have enhanced Smet's approach (Smet, 2004) to improve the accuracy.

## **3.1.1 Modeling of a liquid crystal cell**

The average orientation of liquid crystal molecule is assumed to be represented by onedimensional variable 'x' as shown in Fig.24. In practice, three kinds of torques are in play (See Fig. 24).


Since the moment of inertia of a liquid crystal molecule is small, it can be neglected. The equilibrium of torques in Fig. 24 states that:

$$
\sigma E^2 = \mathbf{K}\mathbf{x} + \gamma \frac{d\mathbf{x}}{dt} \tag{16}
$$

This is well-known first-order system with time constant /*K* and 2 ( ) ( ) *<sup>c</sup> Vext x t <sup>t</sup> K d* . Eq. (16) can be solved with the low pass filter circuit shown in Fig.

25. The resistance Rd and the capacitance Cd should be determined so that their product corresponds to the time constant / *K* . Note that the magnitude of the electric field E in the cell is described as Vext/d. Here, Vext and d are respectively the applied voltage

A circuit simulation is a great tool for efficiently optimizing the design parameters given the complicated trade-off relationship among the electrical characteristics of displays. Although commercial circuit simulators can also be used for some design work, their device models are not detailed enough to have sufficient accuracy for liquid crystal capacitor and TFT since there are some important properties which are not considered in the implemented models into commercial simulator. To solve this problem, we have developed our own device models for a liquid crystal capacitor (Watanabe, 2007) and TFT (Ishihara, 2008) including the photo-leak effect. This section introduces the liquid crystal capacitor model as a representative. Moreover the Appendix provides codes written in VerilogA for

To make competitive products, the optical and electrical characteristics of LCDs should simultaneously be optimized to the highest level. Liquid crystal cells behave as a non-liner history-dependent capacitors from the electrical point of view, and as light valves, the transmittance of which can be varied with an applied voltage from the optical point of view. The following presents a macro-model for liquid crystal cells that includes these electrical and optical behaviors. We have enhanced Smet's approach (Smet, 2004) to improve the

The average orientation of liquid crystal molecule is assumed to be represented by onedimensional variable 'x' as shown in Fig.24. In practice, three kinds of torques are in play

This torque aligns the molecules parallel to the field E. It is proportional to <sup>2</sup> *E* .

alignment layer). This torque is assumed to follow Hooke's law.

This torque pulls the molecules back to their resting position x=0 (parallel to the

This torque hinders any movement and is proportional to the velocity at which the

Since the moment of inertia of a liquid crystal molecule is small, it can be neglected. The

<sup>2</sup> *dx cE Kx*

This is well-known first-order system with time constant /*K* and

25. The resistance Rd and the capacitance Cd should be determined so that their product corresponds to the time constant / *K* . Note that the magnitude of the electric field E in the cell is described as Vext/d. Here, Vext and d are respectively the applied voltage

*dt* (16)

. Eq. (16) can be solved with the low pass filter circuit shown in Fig.

**3. Design optimization by circuit simulation** 

implementing our device model into a circuit simulator.

**3.1 Liquid crystal capacitor model** 

**3.1.1 Modeling of a liquid crystal cell** 

1. The elastic torque *F Kx elas* (K: constant)

2. The electrical torque <sup>2</sup> *F cE elec* (c: constant)

3. The viscosity torque *dx Fvis dt* (γ: constant)

equilibrium of torques in Fig. 24 states that:

accuracy.

(See Fig. 24).

molecule move.

2 ( ) ( ) *<sup>c</sup> Vext x t <sup>t</sup> K d* 

between two electrodes and the cell gap in Fig.24. After solving for x(t) from this circuit, the effective voltage Vi at time t is calculated as 2 ( ) *Kd V xt <sup>i</sup> <sup>c</sup>* .

Fig. 24. Schematic diagram of liquid crystal cell

Fig. 25. Macro-model for liquid crystal cell

Active Matrix Driving and Circuit Simulation 127

*a a1\_ <sup>f</sup> ,a a2\_ <sup>f</sup> 1 2* (for fall process) This additional routine enables individual control of the rise and fall behaviors. The

We verified the macro-model by comparing its results with experimental data. Fig. 26 compares modeled and experimental data for the static behavior. The experimental data is for a twisted-nematic liquid crystal cell with a 3.5μm gap. The model exhibits good agreement with the experimental data in both its transmittance and dielectric constant

VerilogA code for the above macro model is in Appendix.

Fig. 26. Comparison of static behaviors of experimental data and model

Fig. 27 compares modelled and experimental data for the dynamic behavior for externally applied voltages. The transient behavior from low voltage to high voltage (rising process) is shown in Fig. 27 (a), and from high voltage to low voltage (falling process) in Fig. 27 (b). The transient behavior of the dielectric constant is not shown here because no measuring procedure has been established for it. We assumed that the dynamic parameters for the transmittance and dielectric constant are the same when this model is used in the actual

design for the liquid crystal cell, though this assumption cannot be verified directly.

Else

**3.1.2 Model evaluation** 

characteristics.

The static behaviors for the capacitance and transmittance of liquid crystal cells can be expressed empirically with Eq. (17) and Eq. (19) as function of the effective applied voltage Vi.

$$\mathbf{C}(V\_{\hat{I}}) = \mathbf{C}\_{\perp} + \frac{2}{\pi} \left( \mathbf{C}\_{\parallel} - \mathbf{C}\_{\perp} \right) \arctan \left[ \frac{\alpha + \left( a^2 + 8 \right)^2}{2} \right] \tag{17}$$

$$\alpha = \frac{V\_{\bar{l}} - V\_{\text{fcf}}}{V\_{\text{mcf}}} \tag{18}$$

$$T(V\_{\hat{\mathbf{y}}}) = T\_{\min} + (1 - T\_{\min}) \tanh\left[\frac{\mathbb{R} + \left(\mathbb{R}^2 + \eta^2\right)^{1/2}}{2}\right] \tag{19}$$

$$\beta = \frac{V\_{\bar{I}} - V\_{\text{to}}}{V\_{\text{moo}}} \tag{20}$$

C∥, C�, δ, Vtc, Vmc, in Eq.(17) and Tmin, η, Vto, Vmo in Eq.(19) are treated as model parameters extracted from experimental results.

To improve accuracy, we have modified the form of the time constant (τ) in the equation proposed by Smet by considering the following points.

First, we should improve the accuracy for the external applied voltage dependency. Generally, the response time of liquid crystal depends on the external applied voltage (Vext). We got the following expression for time constant (τ) after further investigating of the relationship between the electric torque(Felec) and the applied voltage(Vext) (Watanabe, 2007).

$$
\pi = \frac{1}{a\_1 + a\_2 V\_{ext}^m} \tag{21}
$$

Here *a ,a 1 2* and m are model parameters. Basically, m takes a value around 2.

The second point is to give the parameter to rise and fall process individualy. A rise (fall) process is defined as the case that the orientation angle x of the liquid crystal molecule is increasing (decreasing). The time constant for each process does not generally coincide. To implement this factor into our model, the parameters in Eq. (21) are selected after the voltage for both terminals of Rd are compared: If

$$\frac{c}{K} \left( \frac{V\_{\text{ext}}}{d} \right)^2 \ge \varkappa(t)$$

Then

$$a\_1 = a1\\_r, a\_2 = a2\\_r \quad \text{(for rise process)}$$

Else

126 Features of Liquid Crystal Display Materials and Processes

The static behaviors for the capacitance and transmittance of liquid crystal cells can be expressed empirically with Eq. (17) and Eq. (19) as function of the effective applied voltage

*1/2 2 2 <sup>a</sup> <sup>2</sup> C(V ) C C C arctan <sup>i</sup> <sup>2</sup>*

*V V <sup>i</sup> tc Vmc*

*V V <sup>i</sup> to Vmo*

C∥, C�, δ, Vtc, Vmc, in Eq.(17) and Tmin, η, Vto, Vmo in Eq.(19) are treated as model

To improve accuracy, we have modified the form of the time constant (τ) in the equation

First, we should improve the accuracy for the external applied voltage dependency. Generally, the response time of liquid crystal depends on the external applied voltage (Vext). We got the following expression for time constant (τ) after further investigating of the relationship

> *1 <sup>m</sup> a aV 1 2 ext*

*2 <sup>c</sup> Vext x(t) K d* 

*1 2* (for rise process)

between the electric torque(Felec) and the applied voltage(Vext) (Watanabe, 2007).

*a a1\_ r ,a a2\_ r*

*1 2* and m are model parameters. Basically, m takes a value around 2. The second point is to give the parameter to rise and fall process individualy. A rise (fall) process is defined as the case that the orientation angle x of the liquid crystal molecule is increasing (decreasing). The time constant for each process does not generally coincide. To implement this factor into our model, the parameters in Eq. (21) are selected after the

*T(V ) T (1 T )tanh i min min <sup>2</sup>*

parameters extracted from experimental results.

voltage for both terminals of Rd are compared:

proposed by Smet by considering the following points.

 *1/2 2 2*

(17)

(18)

(20)

(21)

(19)

Vi.

Here *a ,a*

If

Then

$$a\_1 = a1\_{-}f, a\_2 = a2\_{-}f \quad \text{(for fall process)}$$

This additional routine enables individual control of the rise and fall behaviors. The VerilogA code for the above macro model is in Appendix.

#### **3.1.2 Model evaluation**

We verified the macro-model by comparing its results with experimental data. Fig. 26 compares modeled and experimental data for the static behavior. The experimental data is for a twisted-nematic liquid crystal cell with a 3.5μm gap. The model exhibits good agreement with the experimental data in both its transmittance and dielectric constant characteristics.

Fig. 26. Comparison of static behaviors of experimental data and model

Fig. 27 compares modelled and experimental data for the dynamic behavior for externally applied voltages. The transient behavior from low voltage to high voltage (rising process) is shown in Fig. 27 (a), and from high voltage to low voltage (falling process) in Fig. 27 (b). The transient behavior of the dielectric constant is not shown here because no measuring procedure has been established for it. We assumed that the dynamic parameters for the transmittance and dielectric constant are the same when this model is used in the actual design for the liquid crystal cell, though this assumption cannot be verified directly.

Active Matrix Driving and Circuit Simulation 129

analog begin @(initial\_step) begin

qlc = 0; vi\_c = vini \* vini; vi\_t = vini \* vini; end // vin = V(a,b); vv = vin \* vin; //

cdiff = (2/`m\_pi) \* (cp - cv);

// For Capacitance // if (vin >= vi\_c) begin //rising a1c = a1c\_r; a2c = a2c\_r; mc = mc\_r; end else begin //falling a1c = a1c\_f; a2c = a2c\_f; mc = mc\_f; end

rdc = 1/(a1c + a2c \* pow(vi\_c, mc) ); I(vc) <+ ddt(cdc \* V(vc)); I(vc) <+ (V(vc)-vv)/rdc; vi\_c = V(vc); vrms\_c = sqrt(vi\_c + 0.01); alpha = (vrms\_c - vtc)/vmc;

rdt = 1/(a1t + a2t \* pow(vi\_t, mt) ); I(vt) <+ ddt(cdt \* V(vt)); I(vt) <+ (V(vt)-vv)/rdt; vi\_t = V(vt); vrms\_t = sqrt(vi\_t + 0.01); beta = (vrms\_t - vto)/vmo;

// Description for device behavior

trans = 100\*(1-(1-tmin)\*tanh((beta+sqrt(beta \* beta + eta \* eta))/2));

//

// if (vin >= vi\_t) begin //rising a1t = a1t\_r; a2t = a2t\_r; mt = mt\_r; end else begin //falling a1t = a1t\_f; a2t = a2t\_f; mt = mt\_f; end

//

// qlc = cap \* vin; I(a,b) <+ ddt(qlc);

end endmodule

// For Transmittance

cap = scale \* area \* (cv + cdiff \* atan((alpha+sqrt(alpha \* alpha + delta \* delta ))/2));

**List 1. VerilogA code for Liquid Crystal Macro Model** 

**5. Appendix** 

// M.Watanabe //

//

//

//

//

//

//

//

//

//

//

real qlc, cdiff; //

`include "discipline.h" `include "constants.h"

module lccap(a,b); inout a,b; electrical a,b; // // Internal nodes electrical vc, vt; //

// For Capacitance parameter real cv = 8.82; parameter real cp = 27.1; parameter real vtc = 0.88; parameter real vmc = 0.88; parameter real delta = 0.1;

// For Transmittance parameter real tmin= 8.7e-4; parameter real vto = 1.1; parameter real vmo = 0.54; parameter real eta = 0.24;

// For Capacitance parameter real a1c\_r = 0.014; parameter real a2c\_r = 0.05; parameter real a1c\_f = 0.014; parameter real a2c\_f = 0.05; parameter real cdc = 1e-3; parameter real mc\_r = 2.4; parameter real mc\_f = 2.05;

// For Transmittance parameter real a1t\_r = 0.020; parameter real a2t\_r = 0.02; parameter real a1t\_f = 0.0205; parameter real a2t\_f = 0.025; parameter real cdt = 1e-3; parameter real mt\_r = 2.4; parameter real mt\_f = 2.05;

// Geometrical Parameters

real a1c, a2c, a1t, a2t, cap, rdc, rdt; real trans,alpha,beta;

real vi\_c, vrms\_c, vv, qi\_c, vin, vi\_t, vrms\_t, qi\_t, mc, mt ;

parameter real area = 1; parameter real vini = 0; parameter real scale =1;

// Parameters for Static behavior

// Parameters for Dynamic behavior

// Liquid Crystal Cell Macro Model ver1.0

`define m\_pi (3.14159265358979323846)

Fig. 27. Comparison of dynamic behaviors of experimental data and modelled

In Fig.27, the model exhibits good agreement with the experimental data except for the following points.


## **4. Conclusion**

Thanks to its individual control of each pixel, active matrix driving is definitely superior to passive driving in its capability to display higher quality pictures. Even in an active matrix driving, however, some malfunctions such as shading, crosstalk and flicker become apparent on screen when a specific picture pattern is displayed. In this chapter, we made the mechanism behind such malfunctions and some of the key design parameters. Readers may find the complicated trade-off relationship among key design parameters and a difficulty in optimizing the parameters simultaneously. A circuit simulator would be very useful for designers to optimize the design parameters more efficiently. However, general commercial circuit simulators often do not have enough device models such as liquid crystal cell capacitors, TFTs supporting the ambient light effects, and so on. Therefore, for the sake of accurate circuit simulations, LCD designers must aggressively develop device models and continuously improve them. In this chapter, we described a macro model for a liquid crystal cell capacitor as a representative model for making accurate designs. The current trend of developing larger and higher resolution of LCDs will spur a need for accurate circuit simulation technologies since there will be less margin for each design parameter.

## **5. Appendix**

128 Features of Liquid Crystal Display Materials and Processes

Fig. 27. Comparison of dynamic behaviors of experimental data and modelled

1. The bounce around 5msec in 3.30v → 0v in Fig.27 (b)

applied voltage around 1v, as can be seen in Fig.26.

and in the initial state in Fig.27 (b)

following points.

**4. Conclusion** 

In Fig.27, the model exhibits good agreement with the experimental data except for the

This phenomenon is well known as the back-flow of liquid crystal molecule (Doom, 1975). This shape of the curve could not be expressed in principle since Eq.(19) is monotonous function. A new model supporting this phenomenon should be developed. 2. The disagreement between model and experiment after ample time elapses in Fig. 27(a)

The origin of this disagreement is considered to be measurement error, since the modelled transmittances after an ample time has passed in Fig. 27(a) and at the initial time in Fig. 27(b) do not coincide with the static measurements ones in Fig. 26. It is hard to improve the measurement accuracy because the transmittance is very sensitive to the

Thanks to its individual control of each pixel, active matrix driving is definitely superior to passive driving in its capability to display higher quality pictures. Even in an active matrix driving, however, some malfunctions such as shading, crosstalk and flicker become apparent on screen when a specific picture pattern is displayed. In this chapter, we made the mechanism behind such malfunctions and some of the key design parameters. Readers may find the complicated trade-off relationship among key design parameters and a difficulty in optimizing the parameters simultaneously. A circuit simulator would be very useful for designers to optimize the design parameters more efficiently. However, general commercial circuit simulators often do not have enough device models such as liquid crystal cell capacitors, TFTs supporting the ambient light effects, and so on. Therefore, for the sake of accurate circuit simulations, LCD designers must aggressively develop device models and continuously improve them. In this chapter, we described a macro model for a liquid crystal cell capacitor as a representative model for making accurate designs. The current trend of developing larger and higher resolution of LCDs will spur a need for accurate circuit

simulation technologies since there will be less margin for each design parameter.

#### **List 1. VerilogA code for Liquid Crystal Macro Model**


endmodule

**7** 

Jian-Chiun Liou

*Taiwan* 

*Industrial Technology Research Institute* 

**Intelligent and Green Energy LED Backlighting** 

As modem society has been reshaped rapidly into the multimedia information society, large size of display devices is required. Thin-film-transistor liquid- crystal-displays (TFT-LCDs) are one of the most popular display devices from small to large size. TFT-LCDs need backlight source, because they are not a self luminance device. Backlight for LCDs is becoming more important with growth of the LCD size. Up to now, multiple fluorescent lamps such as cold cathode fluorescent lamp (CCFL), external electrode fluorescent lamp (EEFL) and flat fluorescent lamp (FFL) are generally used as LCD backlight source. Since, the conventional backlight of LCDs illuminates at the full luminance regardless of the images to be displayed, it wasted power and contrast ratio is row due to the light leakage in

Recently, as the luminance efficiency of light emitting diode (LED) has been improved and the cost of LED is going down, the LED is the substitutive solution for the backlight source. Moreover, since LED has many advantages such as long lifetime, wide color gamut, fast response, and so on, LEDs are expected to replace the conventional fluorescent lamps for backlight source of LCD in near future. Although, LED backlight driving systems have been developed and introduced to the market, further reduction of power consumption and cost reduction are still demanded to be widely used as backlight source. In segmented dimming and local dimming methods which have usually adapted to CCFL and LED backlight source, the whole backlight is divided into several segmented and block, backlight scaling is adapted to each segmented and block, respectively. The more division of backlight, the more power saving can be achieved. Therefore, local dimming method can save power consumption more effectively than segmented dimming one. Especially, segmented dimming method has limitation of power saving when the image is bright vertically. Therefore, local dimming is the best way to have local dimming effects. However, local dimming method results in huge increase in the number of drivers needed for large number of division. To compromise between segmented dimming and local dimming methods, a new LED backlight system for LCD TVs which involves the time division X-Y segmented driving method that utilizes row and column switches to control the individual division

Even though the refresh time of an LCD panel is as fast as a CRT display, there are still some problems to be solved before this LCD panel can be implemented to be a time-multiplexed

**1. Introduction** 

dark state.

screen is proposed.

**Techniques of Stereo Liquid Crystal Displays** 

#### **6. References**

