**3. Digital multiplexer**

Digital multiplexer [6–8] or data selector is a logic circuit that has several input lines and a single output line. It also consists of data selector switch which is used to select the inputs and permit the data into the device to output.

**21**

**Figure 17.**

**Figure 16.**

**Figure 15.**

*Circuit diagram of four-in-one multiplexer.*

*Circuit symbol and selector switch pattern of four-in-one multiplexer.*

*Logic symbol and switching pattern of eight-in-one multiplexer.*

*Multiplexing*

*DOI: http://dx.doi.org/10.5772/intechopen.85866*

### **Figure 15.**

*Multiplexing*

**Figure 13.**

**Figure 14.**

By means of an appropriate symbol detector, the frequency domain signals are converted to N parallel streams, and each stream is converted to a binary stream. A sequential stream combining all binary stream acts as an estimate of the original

• OFDM is computationally efficient to deploy the modulation and demodula-

• OFDM signal is robust and more tolerant in multipath propagation environ-

• OFDM system gives good protection against co-channel interference and impul-

• OFDM system uses pilot subcarriers to prevent the frequency and phase shift

Digital multiplexer [6–8] or data selector is a logic circuit that has several input lines and a single output line. It also consists of data selector switch which is used to

select the inputs and permit the data into the device to output.

OFDM system has also certain limitations rather than the abovementioned potential capabilities. High peak-to-average power ratios (PAPR) of transmitted signal are the major drawback of the OFDM signal. OFDM is very sensitive to carrier frequency offset and hence becomes difficult to synchronize during sharing of

• OFDM is more resistant to frequency selective fading than single carrier

tion techniques through IFFT and FFT, respectively.

binary stream at the transmitter side.

*OFDM simple block diagram of OFDM receiver.*

*OFDM transmitter simple block diagram.*

*2.6.4 Significance of the OFDM system*

ment to delay spread.

transmission systems.

sive parasitic noise.

subcarriers different transmitters.

**3. Digital multiplexer**

errors.

**20**

*Circuit diagram of four-in-one multiplexer.*


### **Figure 16.**

*Circuit symbol and selector switch pattern of four-in-one multiplexer.*

**Figure 17.** *Logic symbol and switching pattern of eight-in-one multiplexer.*

### **Figure 18.**

*Logic diagram of eight-in-one multiplexer.*

### **3.1 Four-in-one multiplexer**

The logic symbol and circuit for a four-input multiplexer are shown in **Figure 15**.

Here D0, D1, D2, and D3 are data input lines. S0 and S1 are data selector or logic switches. When S0 = S1 = 0, then the two inputs of the first AND gate become actively high because the selectors S0 and S1 are inverted using NOT gate and given to this gate. Thus the data from D0 line is outputted through this AND gate. At that time the other gates are in 0 output position. Similarly when S0 = 1 and S1 = 0, then the two inputs of the AND gate 2 become actively high; thus, data from D1 is transmitted through gate 2 as output, and all other gates are in 0 output position. In this manner D2 and D3 are inputted to consecutive switch positions. Here an OR gate is used to combine these four output lines as a single output (**Figure 16**).

### **3.2 Eight-in-one multiplexer**

The logic symbol and data selector of eight-in-one multiplexer is shown in **Figure 17**.

If input is 2, then one data selector switch is needed; if input is 4, then two selector switches are needed; if input is 8, then three selector switches are needed; if input is 16, then four selector switches are needed; and so on.

**23**

**Figure 19.**

*Circuit diagram of one-to-eight demultiplexer.*

*Multiplexing*

*3.2.1 Working*

*DOI: http://dx.doi.org/10.5772/intechopen.85866*

in the next consecutive switch positions.

74,157—2 input data selector/MUX. 74,151—8 input data selector/MUX. 74,150—16 input data selector/MUX.

*3.2.2 Application of MUX*

• Function generators

• Digital counters

**4. Demultiplexers**

• Seven-segment display unit

• Parallel-to-serial conversion

Important TTL multiplexer IC's are as follows:

In an eight-in-one multiplexer (**Figure 18**), eight data input lines such as D0, D1, D2, D3, D4, D5, D6, and D7, data selector S0, S1, and S2. In this circuit these inputs are fed to eight AND gates, and the outputs of the AND gates are combined by using an OR gate.

When the three selector switches are actively low, then the three inputs of the first AND gate become actively high because the selector outputs are NOTed and given to the first AND gate. Thus the data from D0 line is outputted through the first AND gate, and all other AND gates are in 0 output position. When S0 = 1, S1 = 0, and S2 = 0, then the three input terminals of the second AND gate become actively high, and D1 is outputted through this gate. At that time all other gates are in 0 output position. In that manner D2, D3, D4, D5, D6, and D7 data are outputted

Demultiplexer [6] is a logic circuit that performs the reverse multiplexer function. Demultiplexer receives signal from a single line (serial input) and transmits these information into multiple output lines and parallel output lines (**Figure 19**).

In an eight-in-one multiplexer (**Figure 18**), eight data input lines such as D0, D1, D2, D3, D4, D5, D6, and D7, data selector S0, S1, and S2. In this circuit these inputs are fed to eight AND gates, and the outputs of the AND gates are combined by using an OR gate.
