**4.4 Performance analysis**

Performance analysis is a must to compare the performance of the proposed implementation with existing methods. The performance is compared on the basis of area and operating frequency. Till date various researchers have worked on FPGAbased implementations of AES algorithm; some of them have optimized speed and

**137**

**Table 2.**

**Figure 26.**

*Performance comparison of the proposed system with previous work.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform*

**Logic utilization Used Available % utilization** Number of slice registers 121 126,800 0.00095 Number of slice LUTs 4782 63,400 7 Number of bonded IOBs 25 210 11

**Sr. No. Authors Slices Operating freq. (MHz)** Proposed work 121 1102.536 [3] 1464 — [4] 161 886.64 [7] 5493 277.4 [8] 3376 — [9] 150 90 [10] 201 70 [12] 1403 160.875 [15] 1746 — [19] 1853 140.390 [21] 6279 119.954

*Simulation result (a) Original image, (b) Encrypted image, and (c) Decrypted image.*

*DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Design utilization summary**

*Design utilization summary.*

**Table 1.**

**Figure 25.** *Detailed RTL schematic of AES algorithm.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform DOI: http://dx.doi.org/10.5772/intechopen.82434*


#### **Table 1.**

*Computer and Network Security*

**4. Experimental results**

**Figure 25** shows detailed RTL schematic of the proposed implementation of

The design is synthesized using Xilinx XST synthesizer. In the proposed design, an optimized and synthesizable very high speed integrated circuit (VHSIC) hardware description language (VHDL) code for the implementation of image as well as 128-bit data encryption is developed so as to utilize less area and increase the speed.

From the synthesis results of the proposed design, it is clear that this system utilizes only 121 slice registers, and its maximum operating frequency is 1102.536 MHz.

By substituting the values in Eq. (1), throughput of the systems is 14.1125 Gbps.

**Figure 26** shows simulation result when an image is applied as an input.

Performance analysis is a must to compare the performance of the proposed implementation with existing methods. The performance is compared on the basis of area and operating frequency. Till date various researchers have worked on FPGAbased implementations of AES algorithm; some of them have optimized speed and

<sup>128</sup> bits <sup>×</sup> Clock frequency \_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_ Cycles per Encrypted block (1)

**Table 1** shows design utilization summary of the proposed design.

(Throughput) of the system=

The throughput of the system is calculated using the following formula:

**4.1 RTL schematic**

**4.2 Synthesis result**

**4.3 Simulation result**

**4.4 Performance analysis**

AES algorithm.

**136**

**Figure 25.**

*Detailed RTL schematic of AES algorithm.*

*Design utilization summary.*

#### **Figure 26.**

*Simulation result (a) Original image, (b) Encrypted image, and (c) Decrypted image.*


#### **Table 2.**

*Performance comparison of the proposed system with previous work.*

some have optimized area. In the proposed system, both area and speed are optimized. **Table 2** shows performance comparison of the proposed system with previous work.
