**4.2 Synthesis result**

The design is synthesized using Xilinx XST synthesizer. In the proposed design, an optimized and synthesizable very high speed integrated circuit (VHSIC) hardware description language (VHDL) code for the implementation of image as well as 128-bit data encryption is developed so as to utilize less area and increase the speed. **Table 1** shows design utilization summary of the proposed design.

From the synthesis results of the proposed design, it is clear that this system utilizes only 121 slice registers, and its maximum operating frequency is 1102.536 MHz. The throughput of the system is calculated using the following formula:

is only 121 slice registers, and its maximum operating frequency is 1102.536 MHz, the throughput of the system is calculated using the following formula:

$$\text{\(Throught\) of the system} = \frac{128 \text{ bits} \times \text{Clock frequency}}{\text{Cycles per Encrypted block}} \tag{1}$$

By substituting the values in Eq. (1), throughput of the systems is 14.1125 Gbps.
