**4. FPGA implementation of security scheme applied to CDMA**

In this section, FPGA implementation of new scheme applied to CDMA, the new VHDL code package to implement A mod n operations, synthesis report and behavioral simulation results will be presented.

from the modular exponentiation are reduced using binary exponentiation and

To perform the x = X mod N calculation where X has a large operand length of b bits say b = 1024 bits and N is modulus of small operand length of b1 bits say b1 = 8

The principle used to develop the package is as follows:

*A New Cross-Layer FPGA-Based Security Scheme for Wireless Networks*

2. The b1 least significant bits of the b bits of X are chosen;

(Eq. (9)) forms the basis for the x = X mod N calculation.

3. The integer equivalent, x1 of the chosen b1 bits is determined;

4. The residue, x = X mod N is obtained from the following equation;

<sup>x</sup> <sup>¼</sup> x1 <sup>þ</sup> 2b1�<sup>1</sup> � <sup>N</sup> �

In order to verify the performance of the proposed architecture, a VHDL programme was written and implemented on a Xilinx Virtex-4 FPGA chip (device: xc4vlx 200, package: ff 1513, speed grade � 11) [22]. Sixteen (16) randomly generated integers were fed into the FPGA. For this value, the number of bonded IOBs is 760 out of 960 resulting to 79% resource used. The behavioral simulation results for array {39,870, 45,378, 87,654, 20,087, 35,689, 16,592, 564, 276,509, 89,732, 56,287, 4527, 89,065, 4321, 7654, 5489, 512} using moduli set {111, 115, 119} are displayed in [15]. In [15], the complete synthesis report showing device utilization summary is presented. Due to the additional implementation of orthogonal signaling compared to the implementation in [15], the following parameters are different compared to

5. If the residue, x is greater than the modulus, N the process is iterated until the

Based on this new algorithm which implements modular exponentiation without the use of the Montgomery algorithm, the entire physical layer security scheme

X

<sup>2</sup>b1�<sup>1</sup> (9)

the RNS.

bits, the following steps are used:

*DOI: http://dx.doi.org/10.5772/intechopen.82390*

1. X is converted to binary equivalent;

residue is less than the modulus.

**4.3 Behavioral simulation and synthesis report**

The device utilization summary is as follows:

• Number of slice flip flops: 60 out of 178,176 0%

• Number of four input LUTs: 7452 out of 178,176 4%

• Total REAL time to Router completion: 24 min 7 s.

• Pin delays less than 1.00 ns: 21928 out of 30,651 71.5%.

• Total REAL time to place and route (PAR) completion: 24 min 41 s.

• Number of slices: 5411 out of 89,088 6%

could fit into a single FPGA chip.

results displayed in [15]:

**23**
