*3.3.1 Software utilized*

For implementing the proposed design, MATLAB 2013a and Xilinx ISE Design Suite are used. MATLAB is used for generating the keys and also to get the results in terms of images, whereas Xilinx ISE Design Suite is used to get the synthesis result, RTL schematic, and throughput of this implementation.

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*3.3.2 Hardware utilized*

*Implementation of shift row.*

**Figure 13.**

the following features:

a. Xilinx Artix-7 FPGA XC7A100T-1CSG324C

c. 4860 Kbits of fast block RAM

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform*

Nexys-4 DDR development board is used for implementation. This board has

b.15,850 logic slices, each with four 6-input LUTs and 8 flip-flops

*DOI: http://dx.doi.org/10.5772/intechopen.82434*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Figure 13.** *Implementation of shift row.*

*3.3.2 Hardware utilized*

Nexys-4 DDR development board is used for implementation. This board has the following features:

a. Xilinx Artix-7 FPGA XC7A100T-1CSG324C


*Computer and Network Security*

**128**

**Figure 12.**

*Implementation of s-box.*

**3.3 Tools utilized**

*3.3.1 Software utilized*

**Figure 23** shows implementation of inverse shift row. **Figure 24** shows implementation of inverse s-box.

RTL schematic, and throughput of this implementation.

For implementing the proposed design, MATLAB 2013a and Xilinx ISE Design Suite are used. MATLAB is used for generating the keys and also to get the results in terms of images, whereas Xilinx ISE Design Suite is used to get the synthesis result,

#### **Figure 14.** *Implementation of mix column.*

d.Six clock management tiles, each with phase-locked loop (PLL)

**131**

**Figure 16.**

*Implementation of multiplication block.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform*

j. Digilent USB-JTAG port for FPGA programming and communication

*DOI: http://dx.doi.org/10.5772/intechopen.82434*

k.MicroSD card connector

**Figure 15.**

*Implementation of group.*

m. USB-UART Bridge

n.10/100 Ethernet PHY

o.PWM audio output

p.3-axis accelerometer

q. 16 user switches

l. Ships with rugged plastic case and USB cable


*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Figure 15.** *Implementation of group.*

*Computer and Network Security*

**130**

**Figure 14.**

*Implementation of mix column.*

e. 240 DSP slices

h.128 MiB DDR2

i. Serial Flash

d.Six clock management tiles, each with phase-locked loop (PLL)

f. Internal clock speeds exceeding 450 MHz

g.On-chip analog-to-digital converter (XADC)


**Figure 16.** *Implementation of multiplication block.*

#### **Figure 17.** *System generator-based model of inverse round function.*

**133**

**Figure 20.**

*Implementation of group.*

**Figure 19.** *Inverse mix column.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform*

*DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Figure 18.** *Inverse round0.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Figure 19.** *Inverse mix column.*

*Computer and Network Security*

**132**

**Figure 18.** *Inverse round0.*

**Figure 17.**

*System generator-based model of inverse round function.*

**Figure 20.** *Implementation of group.*

#### **Figure 21.**

*Implementation of multiplication block.*

**Figure 22.** *Implementation of multipliers.*

**135**

r. 16 user LEDs

**Figure 24.**

s. Two tri-color LEDs

*Implementation of inverse s-box.*

t. PDM microphone

u.Temperature sensor

v. Two 4-digit 7-segment displays

x.PMOD for XADC signals

y. 12-bit VGA output

z. Four PMOD ports

w. USB HID Host for mice, keyboards, and memory sticks

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform*

*DOI: http://dx.doi.org/10.5772/intechopen.82434*

**Figure 23.** *Implementation of inverse shift row.*

*High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform DOI: http://dx.doi.org/10.5772/intechopen.82434*

### **Figure 24.**

*Computer and Network Security*

*Implementation of multiplication block.*

**Figure 21.**

**Figure 22.**

*Implementation of multipliers.*

**134**

**Figure 23.**

*Implementation of inverse shift row.*

*Implementation of inverse s-box.*

