**4.1 FPGA implementation of new scheme applied to CDMA**

Code division multiple access (CDMA) enables several users to transmit messages simultaneously over the same channel bandwidth in such a way that each transmitter/ receiver user pair has its own distinct signature code for transmitting over the common channel bandwidth. This distinct signature is ensured by using spread spectrum techniques whereby the message from each user is transmitted using orthogonal waveforms. In orthogonal signaling, the residues are mapped to orthogonal waveforms which constitute the CDMA signal [20]. The orthogonal waveforms used in this research are Walsh functions.

Considering an (8, 8, 2) multi-level cryptosystem for illustrative purposes, the mapping process will involve M = 28 = 256 orthogonal waveforms. Using the dynamic range of (�128, 126), a set of M = 28 = 256 orthogonal waveforms is required to completely represent all the integers or symbols. Based on this, the corresponding Hadamard matrix obtained from the procedure elaborated in [21] is as follows:

$$\begin{aligned} \mathbf{H\_{256}} &= \begin{array}{cc} \mathbf{H\_{128}} & \otimes \mathbf{H\_{128}} \\ &= \begin{pmatrix} \mathbf{H\_{128}} & \mathbf{H\_{128}} \\ \mathbf{H\_{128}} & \overline{\mathbf{H\_{128}}} \end{pmatrix} \end{aligned} $$

The H256 matrix is a large matrix comprising of 256 rows and 256 columns. The Hadamard matrix results into a multi–dimensional array. Multi–dimensional arrays are arrays with more than one index. Multi–dimensional arrays are not allowed for hardware synthesis. One way around this is to declare two one–dimensional array types. This approach is easier to use and more representative of actual hardware. The VHDL code used to declare the two one–dimensional array types is shown in **Figure 6** [22].

The other operations in the hardware Walsh function generator implementation are trivial since they involve modulo–2 addition with built–in operators in VHDL code to handle such operations.

#### **4.2 New VHDL code package**

In this research, a new algorithm is presented which implements modular exponentiation without the use of the Montgomery algorithm. A package is developed in the VHDL code to extract residues similarly to the X mod N operation for any randomly generated data. Meanwhile, the large operand lengths which resulted

#### **Figure 6.** *VHDL code for synthesizable 256* � *256 Hadamard matrix.*

*A New Cross-Layer FPGA-Based Security Scheme for Wireless Networks DOI: http://dx.doi.org/10.5772/intechopen.82390*

from the modular exponentiation are reduced using binary exponentiation and the RNS.

The principle used to develop the package is as follows:

To perform the x = X mod N calculation where X has a large operand length of b bits say b = 1024 bits and N is modulus of small operand length of b1 bits say b1 = 8 bits, the following steps are used:

1. X is converted to binary equivalent;

**4. FPGA implementation of security scheme applied to CDMA**

**4.1 FPGA implementation of new scheme applied to CDMA**

behavioral simulation results will be presented.

*Computer and Network Security*

waveforms used in this research are Walsh functions.

as follows:

**Figure 6** [22].

**Figure 6.**

**22**

code to handle such operations.

**4.2 New VHDL code package**

*VHDL code for synthesizable 256* � *256 Hadamard matrix.*

VHDL code package to implement A mod n operations, synthesis report and

In this section, FPGA implementation of new scheme applied to CDMA, the new

Code division multiple access (CDMA) enables several users to transmit messages simultaneously over the same channel bandwidth in such a way that each transmitter/ receiver user pair has its own distinct signature code for transmitting over the common channel bandwidth. This distinct signature is ensured by using spread spectrum techniques whereby the message from each user is transmitted using orthogonal waveforms. In orthogonal signaling, the residues are mapped to orthogonal waveforms which constitute the CDMA signal [20]. The orthogonal

Considering an (8, 8, 2) multi-level cryptosystem for illustrative purposes, the

mapping process will involve M = 28 = 256 orthogonal waveforms. Using the dynamic range of (�128, 126), a set of M = 28 = 256 orthogonal waveforms is required to completely represent all the integers or symbols. Based on this, the corresponding Hadamard matrix obtained from the procedure elaborated in [21] is

H256 ¼ H128 ⊗ H128

<sup>¼</sup> H128 H128 H128 H128

The H256 matrix is a large matrix comprising of 256 rows and 256 columns. The Hadamard matrix results into a multi–dimensional array. Multi–dimensional arrays are arrays with more than one index. Multi–dimensional arrays are not allowed for hardware synthesis. One way around this is to declare two one–dimensional array types. This approach is easier to use and more representative of actual hardware. The VHDL code used to declare the two one–dimensional array types is shown in

The other operations in the hardware Walsh function generator implementation are trivial since they involve modulo–2 addition with built–in operators in VHDL

In this research, a new algorithm is presented which implements modular exponentiation without the use of the Montgomery algorithm. A package is developed in the VHDL code to extract residues similarly to the X mod N operation for any randomly generated data. Meanwhile, the large operand lengths which resulted

!


4. The residue, x = X mod N is obtained from the following equation;

$$\mathbf{x} = \mathbf{x}\_1 + \left(\mathbf{2}^{\mathbf{b}\_1 - 1} - \mathbf{N}\right) \times \frac{\mathbf{X}}{\mathbf{2}^{\mathbf{b}\_1 - 1}}\tag{9}$$

5. If the residue, x is greater than the modulus, N the process is iterated until the residue is less than the modulus.

(Eq. (9)) forms the basis for the x = X mod N calculation.

Based on this new algorithm which implements modular exponentiation without the use of the Montgomery algorithm, the entire physical layer security scheme could fit into a single FPGA chip.

#### **4.3 Behavioral simulation and synthesis report**

In order to verify the performance of the proposed architecture, a VHDL programme was written and implemented on a Xilinx Virtex-4 FPGA chip (device: xc4vlx 200, package: ff 1513, speed grade � 11) [22]. Sixteen (16) randomly generated integers were fed into the FPGA. For this value, the number of bonded IOBs is 760 out of 960 resulting to 79% resource used. The behavioral simulation results for array {39,870, 45,378, 87,654, 20,087, 35,689, 16,592, 564, 276,509, 89,732, 56,287, 4527, 89,065, 4321, 7654, 5489, 512} using moduli set {111, 115, 119} are displayed in [15].

In [15], the complete synthesis report showing device utilization summary is presented. Due to the additional implementation of orthogonal signaling compared to the implementation in [15], the following parameters are different compared to results displayed in [15]:

The device utilization summary is as follows:

