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## Meet the editor

Prof. George Dekoulis received his PhD in Space Engineering and Communications from Lancaster University, UK, in 2007. He was awarded a 1st Class BEng (Hons) degree in Communications Engineering from De Montfort University, UK, in 2001. He has received several awards from STFC, UK and EPSRC, UK, and the "IET Hudswell International Research Scholarship". He is currently a professor at the Aerospace Engineering Institute

(AEI), Cyprus. He is founder of the IEEE Aerospace and Electronic Systems Society (AESS) – Cyprus and was the General Chair of IEEE Aerospace Engineering Innovations 2019 (IEEE AEI 2019) Symposium, 20-23 April 2019, Limassol, Cyprus. He has previously worked as a professor in aerospace engineering at various departments, such as space and planetary physics, aeronautical and space engineering, professional flight, robotics/mechatronics and mechanical engineering, computer science and engineering and electrical and electronics engineering. His research is focused on the design of reconfigurable aerospace engineering systems.

Contents

*and Luis Cisneros-Villalobos*

*by Yongbo Liao*

Algorithms

*and Pullakura Rajesh Kumar*

5G Communications

**Preface XI**

**Chapter 1 1**

**Chapter 2 25**

**Chapter 3 39**

**Chapter 4 57**

**Chapter 5 85**

Real-Time Echo State Network Based on FPGA and Its Applications

Flexible Baseband Modulator Architecture for Multi-Waveform

An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems

VLSI Implementation of Medical Image Fusion Using DWT-PCA

*by Felipe A.P. de Figueiredo and Fabbryccio A.C.M. Cardoso*

*by Mário Lopes Ferreira and João Canas Ferreira*

*by Surya Prasada Rao Borra, Rajesh K. Panakala* 

Real-Time FPGA-Based Systems to Remote Monitoring *by J. Guadalupe Velásquez-Aguilar, Outmane Oubram* 

### Contents


Preface

This Edited Volume is a collection of reviewed and relevant research chapters, concerning the developments within the Field Programmable Gate Arrays (FPGAs) II area of study. The book includes scholarly contributions by various authors and edited by a group of experts pertinent to Computer and Information Science. Each contribution comes as a separate chapter complete in itself but directly related to

The book is divided in one section which includes chapters dealing with the topics: Real-Time FPGA-Based Systems to Remote Monitoring, Real-Time Echo State Network Based on FPGA and Its Applications, Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications, An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems, and VLSI Implementation of Medical

**George Dekoulis**

Cyprus

Aerospace Engineering Institute,

The target audience comprises scholars and specialists in the field.

the book's topics and objectives.

Image Fusion Using DWT-PCA Algorithms.

## Preface

This Edited Volume is a collection of reviewed and relevant research chapters, concerning the developments within the Field Programmable Gate Arrays (FPGAs) II area of study. The book includes scholarly contributions by various authors and edited by a group of experts pertinent to Computer and Information Science. Each contribution comes as a separate chapter complete in itself but directly related to the book's topics and objectives.

The book is divided in one section which includes chapters dealing with the topics: Real-Time FPGA-Based Systems to Remote Monitoring, Real-Time Echo State Network Based on FPGA and Its Applications, Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications, An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems, and VLSI Implementation of Medical Image Fusion Using DWT-PCA Algorithms.

The target audience comprises scholars and specialists in the field.

**George Dekoulis** Aerospace Engineering Institute, Cyprus

**1**

**Chapter 1**

**Abstract**

**1. Introduction**

which are all analog [1].

Real-Time FPGA-Based Systems to

Some industrial and laboratory applications such as control, monitoring, test and measurements, and automation require real-time systems for their development. Embedded systems for acquisition and processing often require the participation of the embedded operating system and therefore are necessary techniques that can accelerate software execution. The latest field-programmable gate arrays' (FPGA) technology has blurred the distinction between hardware and software with embedded processors that allow the development of Systems-on-a-Chip (SoC) running on operating systems. The widespread adoption of wireless technologies such as Bluetooth, ZigBee, and Wi-Fi in the last years has facilitated the use of these technologies to the development of real-time monitoring applications that combined with FPGA devices which has the advantages of low cost, flexibility, and

*J. Guadalupe Velásquez-Aguilar, Outmane Oubram* 

Remote Monitoring

scalability as compared with other commercial systems.

monitoring tasks, hardware is used in a loop (**Figure 1**).

**Keywords:** real-time monitoring, wireless FPGA-based controllers

In many of the industrial and laboratory systems, especially in control and

In the diagram shown above, information about the physical environment is obtained through sensors that respond to a physical stimulus (light, heat, pressure, magnetism, acceleration, stress) and that are designed so that the information acquired is transformed into an electrical signal proportional to the changes. Frequently, the electrical signal obtained from the sensor has noise or interference, so signal conditioning is necessary, which is achieved through some processing operations such as amplification, linearization, compensation, and filtering. Analog-to-digital converters (ADC) are used to sample and hold charge, thereby converting the analog circuit current/voltage into a digital value. Without encoding, sensors are useful in analog control systems, but for the use in digital control and monitoring systems, encoding is critical. Real-time embedded systems therefore require digital encoding of all sensor inputs, with the exception of subsystems,

One of the main tasks of embedded systems is the processing and interpretation of information that arrives from the outside. An embedded system is a combination of hardware and software that is specifically designed for a particular function. In most cases, an embedded system is used to replace an application specific

*and Luis Cisneros-Villalobos*

#### **Chapter 1**

### Real-Time FPGA-Based Systems to Remote Monitoring

*J. Guadalupe Velásquez-Aguilar, Outmane Oubram and Luis Cisneros-Villalobos*

#### **Abstract**

Some industrial and laboratory applications such as control, monitoring, test and measurements, and automation require real-time systems for their development. Embedded systems for acquisition and processing often require the participation of the embedded operating system and therefore are necessary techniques that can accelerate software execution. The latest field-programmable gate arrays' (FPGA) technology has blurred the distinction between hardware and software with embedded processors that allow the development of Systems-on-a-Chip (SoC) running on operating systems. The widespread adoption of wireless technologies such as Bluetooth, ZigBee, and Wi-Fi in the last years has facilitated the use of these technologies to the development of real-time monitoring applications that combined with FPGA devices which has the advantages of low cost, flexibility, and scalability as compared with other commercial systems.

**Keywords:** real-time monitoring, wireless FPGA-based controllers

#### **1. Introduction**

In many of the industrial and laboratory systems, especially in control and monitoring tasks, hardware is used in a loop (**Figure 1**).

In the diagram shown above, information about the physical environment is obtained through sensors that respond to a physical stimulus (light, heat, pressure, magnetism, acceleration, stress) and that are designed so that the information acquired is transformed into an electrical signal proportional to the changes. Frequently, the electrical signal obtained from the sensor has noise or interference, so signal conditioning is necessary, which is achieved through some processing operations such as amplification, linearization, compensation, and filtering. Analog-to-digital converters (ADC) are used to sample and hold charge, thereby converting the analog circuit current/voltage into a digital value. Without encoding, sensors are useful in analog control systems, but for the use in digital control and monitoring systems, encoding is critical. Real-time embedded systems therefore require digital encoding of all sensor inputs, with the exception of subsystems, which are all analog [1].

One of the main tasks of embedded systems is the processing and interpretation of information that arrives from the outside. An embedded system is a combination of hardware and software that is specifically designed for a particular function. In most cases, an embedded system is used to replace an application specific

**Figure 1.** *Real-time processing system hardware in the loop.*

electronics in consumer products. By doing so, most of the systems functionality is encapsulated in the firmware that runs the system, and it is possible to change and upgrade the system by changing the firmware, while keeping the hardware same [2]. When embedded systems are board-based, it is fairly straightforward to select the proper components, integrate them with software, and ship the product.

In the mid-1990s, the development of embedded systems evolved with the concept of ASIC technology, changing the philosophy of systems based on a chipset to a concept System-on-a-Chip (SoC) based on embedded cores. The term SoC defines an integrated circuit (IC) designed by joining multiple independent VLSI models to provide full functionality for an application. Each model is predesigned with complex functions known as cores that serve to a variety of applications. Cores can use a library of components designed by intellectual property (IP) companies or by self in house. The chip used for the system may contain combinations of cores that are generally available in the form of a synthesizable high-level description language (HDL), as Verilog/VHDL, or optimized transistor-level design. Some examples of core-based SoC include high-end microprocessors, GPS positioning for autonomous vehicles, smartphone, and even PC-on-a-Chip [3].

Nowadays, embedded systems are made on SoC. The SoC can include several heterogeneous subsystems, including specific hardware components and sophisticated interconnects (**Figure 2**).

Often in systems used in industrial and laboratory applications for control, monitoring, testing and measurement, and automation, data acquisition (DAQ ) subsystem is the first stage. The main purpose of DAQ is to measure physical phenomena, converting the analog signal into a digital signal, and then send or save the data collected for further analysis. An important point to consider is the problems of output conversion into a digital format, as well as to high accuracy and speed conversion methods used. In addition, if the application requires simultaneously capturing several signals, the DAQ must be of the multichannel type and will need a central processor, which will control the channeling and organization of data acquisition for further displays or its use in control systems. The methods to be used in multichannel data acquisition depend on the control and measurement tasks and directly influence the structure and functionalities of the DAQ. In a modern system, the measurement and control sensors can be set up in different ways; the most used are:

**3**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

• Methods that use time-division channeling, which perform sensor multiplex-

• Methods using space-division channeling, based on simultaneous data acquisi-

In both cases, access to information at any time depends on the control and

Commercial DAQ cards are differentiated by their viabilities such as sampling frequency, scale of acquired signal, power, and requirements but are generally high in cost, and they need a PC at the collection site. Embedded systems to data acquisition often require the participation of the embedded operating system. The modern onboard FPGA can not only overcome the deficiency of the microcontroller unit (MCU) or the digital signal processor (DSP) and meet the requirements of system for real-time and synchronization but also for embedded applications using SoC FPGA platforms with the high level coordination, versatility, and full-stacked operative system [6].

At present, the most used standard protocols in communication in wireless sensor networks (WSN) are IEEE 802.15.1 Bluetooth, IEEE 802.15.4, IEEE 802.15.4/a

ZigBee, and IEEE 802.11 Wi-Fi. The following describes these protocols:

IEEE 802.15.1 protocol is an economical and secure wireless communication standard, used to exchange information between devices through a short-range radio

ing, that is, the time is shared by each sensor in the data acquisition.

*Embedded system architecture. In addition to hardware, a SoC includes classic application software- and hardware-dependent software that must be co-designed with hardware interfaces. The API hides hardware* 

tion from all the sensors.

*details such as interrupt controllers or memory and I/O systems [4].*

**2. Wireless communications standard protocols**

measurement tasks used [5].

**Figure 2.**

**2.1 Bluetooth technology**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

**Figure 2.**

*Field Programmable Gate Arrays (FPGAs) II*

*Real-time processing system hardware in the loop.*

electronics in consumer products. By doing so, most of the systems functionality is encapsulated in the firmware that runs the system, and it is possible to change and upgrade the system by changing the firmware, while keeping the hardware same [2]. When embedded systems are board-based, it is fairly straightforward to select the proper components, integrate them with software, and ship the product. In the mid-1990s, the development of embedded systems evolved with the concept of ASIC technology, changing the philosophy of systems based on a chipset to a concept System-on-a-Chip (SoC) based on embedded cores. The term SoC defines an integrated circuit (IC) designed by joining multiple independent VLSI models to provide full functionality for an application. Each model is predesigned with complex functions known as cores that serve to a variety of applications. Cores can use a library of components designed by intellectual property (IP) companies or by self in house. The chip used for the system may contain combinations of cores that are generally available in the form of a synthesizable high-level description language (HDL), as Verilog/VHDL, or optimized transistor-level design. Some examples of core-based SoC include high-end microprocessors, GPS positioning for

Nowadays, embedded systems are made on SoC. The SoC can include several heterogeneous subsystems, including specific hardware components and sophisti-

Often in systems used in industrial and laboratory applications for control, monitoring, testing and measurement, and automation, data acquisition (DAQ ) subsystem is the first stage. The main purpose of DAQ is to measure physical phenomena, converting the analog signal into a digital signal, and then send or save the data collected for further analysis. An important point to consider is the problems of output conversion into a digital format, as well as to high accuracy and speed conversion methods used. In addition, if the application requires simultaneously capturing several signals, the DAQ must be of the multichannel type and will need a central processor, which will control the channeling and organization of data acquisition for further displays or its use in control systems. The methods to be used in multichannel data acquisition depend on the control and measurement tasks and directly influence the structure and functionalities of the DAQ. In a modern system, the measurement and control sensors can be set up in different

autonomous vehicles, smartphone, and even PC-on-a-Chip [3].

cated interconnects (**Figure 2**).

**Figure 1.**

ways; the most used are:

**2**

*Embedded system architecture. In addition to hardware, a SoC includes classic application software- and hardware-dependent software that must be co-designed with hardware interfaces. The API hides hardware details such as interrupt controllers or memory and I/O systems [4].*


In both cases, access to information at any time depends on the control and measurement tasks used [5].

Commercial DAQ cards are differentiated by their viabilities such as sampling frequency, scale of acquired signal, power, and requirements but are generally high in cost, and they need a PC at the collection site. Embedded systems to data acquisition often require the participation of the embedded operating system. The modern onboard FPGA can not only overcome the deficiency of the microcontroller unit (MCU) or the digital signal processor (DSP) and meet the requirements of system for real-time and synchronization but also for embedded applications using SoC FPGA platforms with the high level coordination, versatility, and full-stacked operative system [6].

#### **2. Wireless communications standard protocols**

At present, the most used standard protocols in communication in wireless sensor networks (WSN) are IEEE 802.15.1 Bluetooth, IEEE 802.15.4, IEEE 802.15.4/a ZigBee, and IEEE 802.11 Wi-Fi. The following describes these protocols:

#### **2.1 Bluetooth technology**

IEEE 802.15.1 protocol is an economical and secure wireless communication standard, used to exchange information between devices through a short-range radio

**Figure 3.**

*Bluetooth frequency bands and RF channels. Each RF channel is ordered in channel number n as follows: f = 2402 + n MHz, where n = 0, …, 78 (BR/EDR) and f = 2402 + n\*2 MHz, with n = 0, …, 39 (LE).*

frequency; it was invented in 1994 by a group of engineers of the Ericsson Company. The original idea of Bluetooth was to eliminate the need for a cable connection between devices by connecting them over short distances (up to 100 m). Bluetooth operates with industrial, scientific, and medical frequencies (ISM), from 2.4 to 2.4835 GHz starting at 2.402 GHz. Bluetooth devices can be configured to operate in two ways:


Since its appearance, Bluetooth protocol has continuously evolved, so there are several versions that are differentiated with a number. Bluetooth versions 1.0–3.0 are known as Bluetooth Classic category and originally supported a maximum data rate of 721 kbps. This is referred to as Basic Rate (BR). The Bluetooth 2.0 EDR specification added support for data rates up to 2.1 Mbps. This is referred to as Enhanced Data Rate (EDR). The Bluetooth 3.0 High Speed (HS) specification enhanced it even further to 24 Mbps. Bluetooth Low Energy (BLE) is a new category that include versions 4.0 and 5.0. Geared toward applications requiring low power consumption, BLE returns to a lower data throughput of 1 Mbps using the GFSK modulation scheme. The Bluetooth 4.0 specification did not add any additional data rates; it only reduced the current consumption to enable low-energy devices. In Bluetooth 5.0, in addition to low power consumption, four different data rates are offered to accommodate a variety of transmission ranges: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps. The lower data rate of 125 kbps was added to compensate for the increase in transmission range [9].

Bluetooth module generally consists of four components: radio transceiver, baseband/link controller, link manager, and a host controller interface (HCI) [8]. HCI is the interface to access the Bluetooth module setup from the host. Bluetooth communication is based on the following two network topologies:


**5**

beacon transmission.

protocol stack [12].

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

*Bluetooth network topologies. (a) Piconet. (b) Scatternet.*

**2.2 ZigBee technology**

**Figure 4.**

to extend the number of Bluetooth devices that can communicate with each other. They allow more than seven devices to communicate with each other [10].

ZigBee, also known as IEEE 802.15.4, was initially conceived in 1998, standardized in 2003, and finally revised in 2006; it is a low power standard for short-range communications between wireless devices. ZigBee is classified as a wireless personal area network (WPAN). ZigBee devices operate in one of three bands: 868 MHz (Europe), 915 MHz (North America), and 2.4 GHz (worldwide). The 2.4 GHz band is the most used by the ZigBee transceivers and uses offset quadrature phase-shift keying (OQPSK) modulation stream. This type of modulation, which is a derivation of traditional QPSK, is used for requiring less transmission power and achieving the same or better performance than similar ones. OQPSK modulation combined with the use of a 5 MHz channel bandwidth allows devices to reach a data rate of up to 250 kbits/s efficiently [11]. The IEEE 802.15.4 has three different operation modes (**Figure 5**):

1.Personal area network coordinator (ZigBee coordinator, ZC): It is the principal controller of the PAN. This device identifies the network, and in it the configurations that allow other devices to be associated are made. ZC function is to act as ZigBee Router (ZR) once the network is formed. ZC is a full-functional device (FFD) that implements the full protocol stack; it can operate with or without beacon mode. The beacon mode of operation is used when data packets must be sent within an allowable delay, such as in monitoring and control applications. The beaconless mode is suitable for applications where data is only sent when an event occurs, that is, there is no continuity in sending information such as motion detection. In a cluster-tree network, all ZRs will receive beacons from their parents and send their own beacons to synchronize the nodes that belong to their clusters.

2.Local Coordinator (ZigBee Router, ZR): This device must be associated with a ZC or with another ZR previously associated with a network, because it does not create its own network. ZR is a full-functional device (FFD) that implements the full protocol stack. This device participates in multi-hop routing of message in mesh and cluster-tree networks (in the latter case they are also called cluster heads (CHs)). ZR provides synchronization services through

3.End device (ZigBee end device, ZED): It is a device that does not implement the previous functionalities and should associate with a ZC or ZR before interacting with the network. In ZigBee, it is just a sensor/actuator node; it can be a reduced function device (RFD) that implements a reduced subset of the

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

**Figure 4.** *Bluetooth network topologies. (a) Piconet. (b) Scatternet.*

to extend the number of Bluetooth devices that can communicate with each other. They allow more than seven devices to communicate with each other [10].

#### **2.2 ZigBee technology**

*Field Programmable Gate Arrays (FPGAs) II*

hop per second.

**Figure 3.**

for the increase in transmission range [9].

frequency; it was invented in 1994 by a group of engineers of the Ericsson Company. The original idea of Bluetooth was to eliminate the need for a cable connection between devices by connecting them over short distances (up to 100 m). Bluetooth operates with industrial, scientific, and medical frequencies (ISM), from 2.4 to 2.4835 GHz starting at 2.402 GHz. Bluetooth devices can be configured to operate in two ways:

*Bluetooth frequency bands and RF channels. Each RF channel is ordered in channel number n as follows: f = 2402 + n MHz, where n = 0, …, 78 (BR/EDR) and f = 2402 + n\*2 MHz, with n = 0, …, 39 (LE).*

1.Basic and Enhanced Data Rates (BR/EDR) transmissions, where 79 radio

2.Low Energy (LE) mode, where only 40 RF channels with 2 MHz spacing are available and adaptive frequency hopping (AFH) is used (**Figure 3**) [7, 8].

Since its appearance, Bluetooth protocol has continuously evolved, so there are several versions that are differentiated with a number. Bluetooth versions 1.0–3.0 are known as Bluetooth Classic category and originally supported a maximum data rate of 721 kbps. This is referred to as Basic Rate (BR). The Bluetooth 2.0 EDR specification added support for data rates up to 2.1 Mbps. This is referred to as Enhanced Data Rate (EDR). The Bluetooth 3.0 High Speed (HS) specification enhanced it even further to 24 Mbps. Bluetooth Low Energy (BLE) is a new category that include versions 4.0 and 5.0. Geared toward applications requiring low power consumption, BLE returns to a lower data throughput of 1 Mbps using the GFSK modulation scheme. The Bluetooth 4.0 specification did not add any additional data rates; it only reduced the current consumption to enable low-energy devices. In Bluetooth 5.0, in addition to low power consumption, four different data rates are offered to accommodate a variety of transmission ranges: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps. The lower data rate of 125 kbps was added to compensate

Bluetooth module generally consists of four components: radio transceiver, baseband/link controller, link manager, and a host controller interface (HCI) [8]. HCI is the interface to access the Bluetooth module setup from the host. Bluetooth

2. Scatternet (combination or two or more piconets) (**Figure 4b**): It is formed when two or more piconets come together by sharing a device. Scatternets help

1.Piconet: It consists of one master and up to seven slaves (**Figure 4a**).

communication is based on the following two network topologies:

frequency (RF) channels with 1 MHz spacing are used. This configuration uses frequency-hopping spread spectrum (FHSS) scheme, at a nominal rate of 1600

**4**

ZigBee, also known as IEEE 802.15.4, was initially conceived in 1998, standardized in 2003, and finally revised in 2006; it is a low power standard for short-range communications between wireless devices. ZigBee is classified as a wireless personal area network (WPAN). ZigBee devices operate in one of three bands: 868 MHz (Europe), 915 MHz (North America), and 2.4 GHz (worldwide). The 2.4 GHz band is the most used by the ZigBee transceivers and uses offset quadrature phase-shift keying (OQPSK) modulation stream. This type of modulation, which is a derivation of traditional QPSK, is used for requiring less transmission power and achieving the same or better performance than similar ones. OQPSK modulation combined with the use of a 5 MHz channel bandwidth allows devices to reach a data rate of up to 250 kbits/s efficiently [11]. The IEEE 802.15.4 has three different operation modes (**Figure 5**):


#### **Figure 5.**

*ZigBee network topologies. (a) Star topology contains a unique node that operates as ZC, which establishes the PAN identifier. The identifier should not be used by any other ZigBee network in the vicinity. Also in the star topology, the communication is centralized, so each device (FFD or RFD) joining the network and willing to communicate with other devices must send its data to the ZC, which sends it to the adequate destination. (b) Mesh topology includes a ZC that identifies the entire network. Communication in this topology is decentralized, so each node can communicate directly with any other node within its radio. (c) In cluster tree topology, there is a single routing path between any pair of nodes, and there is a distributed synchronization mechanism (IEEE 802.15.4 beacon-enabled mode). There is only one ZC that identifies the entire network and one ZR per cluster. Any of the FFDs can act as a ZR that provides synchronization services to other devices and ZRs [13].*

It is important to consider some operational considerations that may be presented by topologies for traditional wireless sensor networks (WSN). If you choose to use the star topology, you should keep in mind (a) that the sensor node selected as ZC will quickly consume its battery and (b) that the coverage of an IEEE 802.15.4/ZigBee cluster is very limited when addressing a large-scale WSN, leading to a scalability problem. On the other hand, the mesh topology enables enhanced networking, but it induces additional complexity to provide end-to-end connectivity between all nodes in the network. Therefore, unlike the star topology, the mesh topology can be more energy efficient, since the communication process does not depend on a particular node [14].

#### **2.3 Wi-fi technology**

Wi-Fi is the name given by the Wi-Fi Alliance [15] to the IEEE 802.11 suite of standards. 802.11 defined the initial standard for wireless local area networks (WLANs).

The evolution of Wi-Fi technology has focused on increasing speed, lower latency, and better user experiences in a multitude of environments and with a variety of device types. Wi-Fi Alliance has introduced generational names to devices and product descriptions. The latest generation of Wi-Fi devices, based on the 802.11ax standard, is known as Wi-Fi devices 6. If the device contains 802.11 ac, 5 GHz technology is known as Wi-Fi 5, or if the device uses technology 802.11n, 2.4 GHz is known as Wi-Fi 4 [16]. Generations of Wi-Fi prior to Wi-Fi 4 will not be assigned names. Most of devices available in the market today are identified as Wi-Fi 5.

**7**

**Figure 7.**

*"star topology" used in wired networks.*

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

Wi-Fi is a physical layer/link interface, as is Ethernet. A wireless station (STA) can be a personal computer (PC), a laptop, a personal digital assistant (PDA), or phone. When two or more STAs are connected wirelessly, they form a Basic Service

*BSS controlled by a single coordination function (CF). The CF determines when a STA transmits and when it* 

Wi-Fi has two different operation modes: infrastructure mode and ad hoc mode.

1.Ad hoc mode: Wireless stations communicate directly with one another, with a peer-to-peer network model. A BSS operating in ad hoc mode is isolated, that is, there is no connection to other Wi-Fi or wired LAN networks. The utility of this network is in situations that demand a quick setup in places where there is

2.Infrastructure mode: This mode requires the BSS to contain a wireless access point (AP). An AP is an STA with additional functionality that allows extending access to wired networks for clients of a wireless network. Any wireless device that tries to join the BSS must first be associated with the AP. A distribution system (DS) is generated when an AP provides access to its associated STAs. The DS can allow communication between APs as shown in **Figure 7**.

*All wireless communication to or from an associated STA goes through an AP. This type of setup is similar to the* 

Set (BSS) (**Figure 6**). This is the basic component of a Wi-Fi network [17].

Each one uses the BSS, but they yield different network topologies.

no network infrastructure.

**Figure 6.**

*receives.*

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

#### **Figure 6.**

*Field Programmable Gate Arrays (FPGAs) II*

It is important to consider some operational considerations that may be presented by topologies for traditional wireless sensor networks (WSN). If you choose to use the star topology, you should keep in mind (a) that the sensor node selected as ZC will quickly consume its battery and (b) that the coverage of an IEEE 802.15.4/ZigBee cluster is very limited when addressing a large-scale WSN, leading to a scalability problem. On the other hand, the mesh topology enables enhanced networking, but it induces additional complexity to provide end-to-end connectivity between all nodes in the network. Therefore, unlike the star topology, the mesh topology can be more energy efficient, since the communication process does not

*ZigBee network topologies. (a) Star topology contains a unique node that operates as ZC, which establishes the PAN identifier. The identifier should not be used by any other ZigBee network in the vicinity. Also in the star topology, the communication is centralized, so each device (FFD or RFD) joining the network and willing to communicate with other devices must send its data to the ZC, which sends it to the adequate destination. (b) Mesh topology includes a ZC that identifies the entire network. Communication in this topology is decentralized, so each node can communicate directly with any other node within its radio. (c) In cluster tree topology, there is a single routing path between any pair of nodes, and there is a distributed synchronization mechanism (IEEE 802.15.4 beacon-enabled mode). There is only one ZC that identifies the entire network and one ZR per cluster. Any of the FFDs can act as a ZR that provides synchronization services to other devices and ZRs [13].*

Wi-Fi is the name given by the Wi-Fi Alliance [15] to the IEEE 802.11 suite of standards. 802.11 defined the initial standard for wireless local area networks

The evolution of Wi-Fi technology has focused on increasing speed, lower latency, and better user experiences in a multitude of environments and with a variety of device types. Wi-Fi Alliance has introduced generational names to devices and product descriptions. The latest generation of Wi-Fi devices, based on the 802.11ax standard, is known as Wi-Fi devices 6. If the device contains 802.11 ac, 5 GHz technology is known as Wi-Fi 5, or if the device uses technology 802.11n, 2.4 GHz is known as Wi-Fi 4 [16]. Generations of Wi-Fi prior to Wi-Fi 4 will not be assigned names. Most of devices available in the market today are identified as Wi-Fi 5.

**6**

depend on a particular node [14].

**2.3 Wi-fi technology**

(WLANs).

**Figure 5.**

*BSS controlled by a single coordination function (CF). The CF determines when a STA transmits and when it receives.*

Wi-Fi is a physical layer/link interface, as is Ethernet. A wireless station (STA) can be a personal computer (PC), a laptop, a personal digital assistant (PDA), or phone. When two or more STAs are connected wirelessly, they form a Basic Service Set (BSS) (**Figure 6**). This is the basic component of a Wi-Fi network [17].

Wi-Fi has two different operation modes: infrastructure mode and ad hoc mode. Each one uses the BSS, but they yield different network topologies.


#### **Figure 7.**

*All wireless communication to or from an associated STA goes through an AP. This type of setup is similar to the "star topology" used in wired networks.*

#### *2.3.1 Services specified by IEEE 802.11*

The IEEE 802.11 standard does not define any specific implementations. Instead, nine services are specified that all implementations must provide; these are:

#### *2.3.1.1 Station services (SS)*

*Authentication* - The STA must identify itself to the AP before it can access network services.

*De-authentication* - This service voids an existing authentication.

*Privacy* - An STA must be able to encrypt the frame to protect the message content to be transmitted, so that only the recipient can read it.

*MAC service data unit (MSDU) delivery* - An MSDU is a data frame that must be transmitted to the proper destination.

#### *2.3.1.2 Distribution system services (DSS)*

A STA that functions as an AP must implement the following services:

*Association* - This service establishes an AP/STA mapping after mutually agreeable authentication has taken place between the two wireless stations. A STA can only associate with one AP at a time.

*Re-association* - This service allows you to change the current association from one AP to another AP.

*Disassociation* - This service voids a current association.

*Distribution* - This service handles delivery of MSDUs within the distribution system.

*Integration* - This service is the bridge function between wireless and wired networks. MSDU handles the delivery of between the distribution system and a wired LAN [17].

#### **3. Hardware description**

The elements used for the realization of the proposed system are shown in **Figure 8**. The platform is composed of four components: the FPGA board that includes A/D converter and three wireless interface Bluetooth, XBee (ZigBee protocol-based), and Wi-Fi module. The wireless modules provide the FPGA device the capacity to communicate with other system or the Internet.

**9**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

**3.1 Analog/digital converter**

*bipolar and SLP active sleep mode [19].*

**3.2 FPGA device**

**Figure 9.**

**3.3 Wireless modules**

*3.3.1 XBee Pro S1*

The A/D converter chip used is the integrated circuit (IC) LTC2308, Linear Technology, whose characteristics are low noise and power consumption, up to 500 Kbps, 8-channel, 12-bit, and SPI/MICROWIRE compatible serial interface. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40 MHz [18]. **Figure 9** shows the block diagram of ADC.

*(a) Block diagram LTC2308 device. Eight analog input and operation modes can be programmed by a 6-bit DIN word through SDI terminal. (b) Timing with a long pulse. The configuration signals are S/D can be single-ended/differential-bit; O/S can be odd/sing-bit; S1 and S0 addressing select bit; UNI can be unipolar/*

*Cyclone V FPGA*. The Intel FPGA Cyclone V SE 5CSEMA4U23C6N device has Dual ARM Cortex-A9 MPCore with Core Sight System on Chip (SoC), integrated circuit Cyclone V SE FPGA, with 40 K logic elements, maximum CPU clock frequency 925 MHz, 224 18×19 multipliers, and 5761 kb embedded memory (**Figure 10**).

The Digi XBee series modules implement the IEEE 802.15.4 radio and ZigBee networking protocol for its physical layer and MAC. Outdoor transmission distances to 0–90 meters depending on power output and environmental characteristics. XBee devices work in ISM 2.4 GHz frequency bands having a serial interface data

**Figure 8.** *Hardware components used for the real-time monitoring system.*

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

#### **Figure 9.**

*Field Programmable Gate Arrays (FPGAs) II*

*2.3.1 Services specified by IEEE 802.11*

transmitted to the proper destination.

*2.3.1.2 Distribution system services (DSS)*

only associate with one AP at a time.

one AP to another AP.

**3. Hardware description**

system.

*2.3.1.1 Station services (SS)*

network services.

The IEEE 802.11 standard does not define any specific implementations. Instead,

nine services are specified that all implementations must provide; these are:

*De-authentication* - This service voids an existing authentication.

content to be transmitted, so that only the recipient can read it.

*Disassociation* - This service voids a current association.

the capacity to communicate with other system or the Internet.

*Authentication* - The STA must identify itself to the AP before it can access

*Privacy* - An STA must be able to encrypt the frame to protect the message

A STA that functions as an AP must implement the following services:

*MAC service data unit (MSDU) delivery* - An MSDU is a data frame that must be

*Association* - This service establishes an AP/STA mapping after mutually agreeable authentication has taken place between the two wireless stations. A STA can

*Re-association* - This service allows you to change the current association from

*Distribution* - This service handles delivery of MSDUs within the distribution

The elements used for the realization of the proposed system are shown in **Figure 8**. The platform is composed of four components: the FPGA board that includes A/D converter and three wireless interface Bluetooth, XBee (ZigBee protocol-based), and Wi-Fi module. The wireless modules provide the FPGA device

*Integration* - This service is the bridge function between wireless and wired networks. MSDU handles the delivery of between the distribution system and a wired LAN [17].

**8**

**Figure 8.**

*Hardware components used for the real-time monitoring system.*

*(a) Block diagram LTC2308 device. Eight analog input and operation modes can be programmed by a 6-bit DIN word through SDI terminal. (b) Timing with a long pulse. The configuration signals are S/D can be single-ended/differential-bit; O/S can be odd/sing-bit; S1 and S0 addressing select bit; UNI can be unipolar/ bipolar and SLP active sleep mode [19].*

#### **3.1 Analog/digital converter**

The A/D converter chip used is the integrated circuit (IC) LTC2308, Linear Technology, whose characteristics are low noise and power consumption, up to 500 Kbps, 8-channel, 12-bit, and SPI/MICROWIRE compatible serial interface. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40 MHz [18]. **Figure 9** shows the block diagram of ADC.

#### **3.2 FPGA device**

*Cyclone V FPGA*. The Intel FPGA Cyclone V SE 5CSEMA4U23C6N device has Dual ARM Cortex-A9 MPCore with Core Sight System on Chip (SoC), integrated circuit Cyclone V SE FPGA, with 40 K logic elements, maximum CPU clock frequency 925 MHz, 224 18×19 multipliers, and 5761 kb embedded memory (**Figure 10**).

#### **3.3 Wireless modules**

#### *3.3.1 XBee Pro S1*

The Digi XBee series modules implement the IEEE 802.15.4 radio and ZigBee networking protocol for its physical layer and MAC. Outdoor transmission distances to 0–90 meters depending on power output and environmental characteristics. XBee devices work in ISM 2.4 GHz frequency bands having a serial interface data


#### **Figure 10.**

*Cyclone V SoC device block diagram is composed of two distinct portions: A dual-core ARM cortex-A9 hard processor system (HPS) and an FPGA. The cortex-A9 processor has two 32-bit CPUs and associated subsystems on the Intel Cyclone V SoC chip, where hardware circuits can be implemented, which reduce the size of the board and increase the performance of the developed system [20].*

rate from 1200 bps to 250Kbps. The following are the supported network topologies: point-to-point, point-to-multipoint, and peer-to-peer.

#### *3.3.2 HC-06 Bluetooth 2.0 EDR module*

This module is a serial interface converter to Bluetooth adapter. HC-06 has a 2.4GHz digital wireless transceiver, low power consumption, an EDR module, the change range of modulation depth: 2Mbps–3Mbps, and standard HCI Port (UART or USB), and it can work at the low voltage (3.1–4.2 V). The module can be set by AT commands and have two modes, master and slave, but the mode cannot be switched during the process of communication. Serial baud rate is 1200–1,382,400 bps [21].

#### *3.3.3 ESP8266 Wi-Fi module.*

This module implements TCP/IP and full 802.11 b/g/n (support 2.4 GHz, up to 72.2 Mbps) WLAN MAC protocol. It can perform either as a stand-alone application or as the slave to a host MCU, so it supports Basic Service Set (BSS) STA and SoftAP operations under the distributed control function (DCF). ESP8266 includes a CPU Tensilica L106 32-bit processor, and it has peripheral interfaces: UART, SDIO, SPI, I2C, I2S, and IR. Power management is handled with minimum host interaction to minimize active duty period. ESP8266EX can be applied to any microcontroller design as a Wi-Fi adaptor through SPI/SDIO or UART interfaces [22].

#### **4. System architectures**

The design of an FPGA-based remote monitoring system architectures is show in **Figure 11**. The resultant design is implemented in VHDL and block diagrams; it is validated in co-simulation environment, and finally, it is tested in a real-time application to monitoring an electric signal.

There are three important features to consider before starting the development system: first, the nature of the feedback signal. If the sensor which measures the variable to be monitored has an analog nature, it is necessary to use an analog-todigital converter (ADC) which has an output with a fixed bit width. Second: in order to avoid performing arithmetic operations between signals of different bit

**11**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

width wireless interface.

**Figure 11.**

**4.1 A/D converter controller**

of 1 bit per SCLK cycle [23].

sponding to SPI controller.

**4.2 FIFO architecture**

width, it is strongly recommended that the operations have the same bit width as the measured variable. Finally, the system output must be congruent with the bus

*Block diagram of architectures implemented on FPGA. This module comprises five blocks: ADC controller,* 

*FIFO memory, Wi-fi, UART drivers, and a finite state machine (FSM).*

The ADC LTC2308 operates on a 12-cycle operational frame, as shown in **Figure 9b**. ADC has four wires to control and communicate with the FPGA: SCLK, CS, DIN, and DOUT. The SCLK and CS signals are used to control the ADC. SCLK is the signal clock for the ADC. The CS signal serves as chip select for the ADC chip. The DIN and DOUT wires are used for transferring addresses and data between the two chips (ADC and FPGA). The FPGA uses the DIN connection to provide the address (3 bits in length) of the next channel requested for conversion. The DOUT connection is used by the ADC to send the digital value (12 bits long) of the converted signal to the FPGA. Both DIN and DOUT are sent in a serial manner at a rate

In the case of our working example, SPI controller was developed to control the conversion process. A long CONVST pulse is used. **Figure 9b** shows time diagram to programming ADC. According to the diagram, "the conversions are initiated by a rising edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, a 6-bit input word (DIN) at the SDI input configures the MUX and programs various modes of operation. As the DIN bits are shifted in, data from the previous conversion is shifted out on SDO. After the 6 bits of the DIN word have been shifted in, the ADC begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out" [19]. **Figure 12** shows the block diagram architecture corre-

A dual-clock First-In First-Out (FIFO) buffer was used to cross data between the two different clock domains: sampling frequency A/D converter (from 1 to 25 MHz) and transmission rate (from 9600 to 921,600 bps), **Figure 13**. In the systems' clock frequency domain, the serialized outputs are continuously stored in 12 bits shift

#### **Figure 11.**

*Field Programmable Gate Arrays (FPGAs) II*

rate from 1200 bps to 250Kbps. The following are the supported network topolo-

*Cyclone V SoC device block diagram is composed of two distinct portions: A dual-core ARM cortex-A9 hard processor system (HPS) and an FPGA. The cortex-A9 processor has two 32-bit CPUs and associated subsystems on the Intel Cyclone V SoC chip, where hardware circuits can be implemented, which reduce the size of the* 

This module is a serial interface converter to Bluetooth adapter. HC-06 has a 2.4GHz digital wireless transceiver, low power consumption, an EDR module, the change range of modulation depth: 2Mbps–3Mbps, and standard HCI Port (UART or USB), and it can work at the low voltage (3.1–4.2 V). The module can be set by AT commands and have two modes, master and slave, but the mode cannot be switched during the process of communication. Serial baud rate is

This module implements TCP/IP and full 802.11 b/g/n (support 2.4 GHz, up to 72.2 Mbps) WLAN MAC protocol. It can perform either as a stand-alone application or as the slave to a host MCU, so it supports Basic Service Set (BSS) STA and SoftAP operations under the distributed control function (DCF). ESP8266 includes a CPU Tensilica L106 32-bit processor, and it has peripheral interfaces: UART, SDIO, SPI, I2C, I2S, and IR. Power management is handled with minimum host interaction to minimize active duty period. ESP8266EX can be applied to any microcontroller

The design of an FPGA-based remote monitoring system architectures is show in **Figure 11**. The resultant design is implemented in VHDL and block diagrams; it is validated in co-simulation environment, and finally, it is tested in a real-time

There are three important features to consider before starting the development system: first, the nature of the feedback signal. If the sensor which measures the variable to be monitored has an analog nature, it is necessary to use an analog-todigital converter (ADC) which has an output with a fixed bit width. Second: in order to avoid performing arithmetic operations between signals of different bit

design as a Wi-Fi adaptor through SPI/SDIO or UART interfaces [22].

gies: point-to-point, point-to-multipoint, and peer-to-peer.

*board and increase the performance of the developed system [20].*

*3.3.2 HC-06 Bluetooth 2.0 EDR module*

1200–1,382,400 bps [21].

**Figure 10.**

*3.3.3 ESP8266 Wi-Fi module.*

**4. System architectures**

application to monitoring an electric signal.

**10**

*Block diagram of architectures implemented on FPGA. This module comprises five blocks: ADC controller, FIFO memory, Wi-fi, UART drivers, and a finite state machine (FSM).*

width, it is strongly recommended that the operations have the same bit width as the measured variable. Finally, the system output must be congruent with the bus width wireless interface.

#### **4.1 A/D converter controller**

The ADC LTC2308 operates on a 12-cycle operational frame, as shown in **Figure 9b**. ADC has four wires to control and communicate with the FPGA: SCLK, CS, DIN, and DOUT. The SCLK and CS signals are used to control the ADC. SCLK is the signal clock for the ADC. The CS signal serves as chip select for the ADC chip. The DIN and DOUT wires are used for transferring addresses and data between the two chips (ADC and FPGA). The FPGA uses the DIN connection to provide the address (3 bits in length) of the next channel requested for conversion. The DOUT connection is used by the ADC to send the digital value (12 bits long) of the converted signal to the FPGA. Both DIN and DOUT are sent in a serial manner at a rate of 1 bit per SCLK cycle [23].

In the case of our working example, SPI controller was developed to control the conversion process. A long CONVST pulse is used. **Figure 9b** shows time diagram to programming ADC. According to the diagram, "the conversions are initiated by a rising edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, a 6-bit input word (DIN) at the SDI input configures the MUX and programs various modes of operation. As the DIN bits are shifted in, data from the previous conversion is shifted out on SDO. After the 6 bits of the DIN word have been shifted in, the ADC begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out" [19]. **Figure 12** shows the block diagram architecture corresponding to SPI controller.

#### **4.2 FIFO architecture**

A dual-clock First-In First-Out (FIFO) buffer was used to cross data between the two different clock domains: sampling frequency A/D converter (from 1 to 25 MHz) and transmission rate (from 9600 to 921,600 bps), **Figure 13**. In the systems' clock frequency domain, the serialized outputs are continuously stored in 12 bits shift

#### **Figure 12.**

*SPI controller architecture. (a) 12 bits a/D conversion general architecture. (b) ADC\_Core architecture. (c) ADC\_Nano architecture generates signal control to ADC. The 4-bit counter counts 16 cycles in high for the acquisition of the signal and 16 cycles in low for the sending of the 12 output bits parallel to the configuration instruction for the next sample. The control ADC architecture is based on shift register.*

register, before they will be sent to FIFO buffer. The finite state machine (FSM) FIFO, in the system controller, wait until collected data of the last active channel will be sent through wireless module, before starting a new acquisition.

**13**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

**Code 1. FIFO\_LOGIC.vhd** [24].

*of 12-bit and 16 words is used to store data.*

the design.

**Figure 13.**

The following source code corresponds to the FIFO\_LOGIC and RAM entities of

*Dual-clock FIFO architecture. Two counters are used to addressing the data to read and write operations. RAM* 

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

#### **Figure 13.**

*Field Programmable Gate Arrays (FPGAs) II*

**12**

**Figure 12.**

register, before they will be sent to FIFO buffer. The finite state machine (FSM) FIFO, in the system controller, wait until collected data of the last active channel

*SPI controller architecture. (a) 12 bits a/D conversion general architecture. (b) ADC\_Core architecture. (c) ADC\_Nano architecture generates signal control to ADC. The 4-bit counter counts 16 cycles in high for the acquisition of the signal and 16 cycles in low for the sending of the 12 output bits parallel to the configuration* 

will be sent through wireless module, before starting a new acquisition.

*instruction for the next sample. The control ADC architecture is based on shift register.*

*Dual-clock FIFO architecture. Two counters are used to addressing the data to read and write operations. RAM of 12-bit and 16 words is used to store data.*

The following source code corresponds to the FIFO\_LOGIC and RAM entities of the design.

#### **Code 1. FIFO\_LOGIC.vhd** [24].

#### **Code 2. RAM\_16.vhd.**

#### **4.3 UART driver**

Serial communications depend on the two UART devices (the FPGA architecture and the wireless module) to be configured with compatible settings: baud rate, parity, control (start and stop bits), and data bits (**Figure 14**).

In this system, a general port input/output (GPIO) is used to send serial data. Subsystem architecture (**Figure 15**) is used to set the baud rate in the output. UART interface will read out the data when it is filled in the FIFO and send to the host

*UART data packet has data format structure: Data bits, parity, and stop bits. In the graph, the data 0x9B (decimal number "155," ASCII character "ø") is transmitted through the wireless module with format: 8-N-1 [25].*

**15**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

displayed in the host with software application.

**Code 3. DIVISOR\_8333.vhd.**

**Figure 15.**

*PARIDAD.*

through the wireless link (Bluetooth or XBee modules), and finally the data can be

*UART driver diagram. Serial transmission uses baud rate module (DIVISOR\_8333). MAQUINAFSM together with MUXSALIDA sends data from FIFO to serial data in the transmission format. The parity is verified with*  *Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

#### **Figure 15.**

*Field Programmable Gate Arrays (FPGAs) II*

**Code 2. RAM\_16.vhd.**

**14**

**Figure 14.**

**4.3 UART driver**

Serial communications depend on the two UART devices (the FPGA architecture

In this system, a general port input/output (GPIO) is used to send serial data. Subsystem architecture (**Figure 15**) is used to set the baud rate in the output. UART interface will read out the data when it is filled in the FIFO and send to the host

and the wireless module) to be configured with compatible settings: baud rate,

*UART data packet has data format structure: Data bits, parity, and stop bits. In the graph, the data 0x9B (decimal number "155," ASCII character "ø") is transmitted through the wireless module with format: 8-N-1 [25].*

parity, control (start and stop bits), and data bits (**Figure 14**).

*UART driver diagram. Serial transmission uses baud rate module (DIVISOR\_8333). MAQUINAFSM together with MUXSALIDA sends data from FIFO to serial data in the transmission format. The parity is verified with PARIDAD.*

through the wireless link (Bluetooth or XBee modules), and finally the data can be displayed in the host with software application.

**Code 3. DIVISOR\_8333.vhd.**

#### **Code 4. MUX\_SALIDA.vhd.**

#### **Code 5. MAQUINA\_FSM.vhd.**

**17**

can be used.

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

**Code 6. PARIDAD.vhd.**

**4.4 Bluetooth and XBee modules**

The wireless modules are configured through AT commands. Command strings have the form ATxx (where xx is the name of a setting). The mode for both is slave to receive data from UART driver architecture. Bluetooth can be set to baud rate from 9600 to 921,600 bps. XBee can be set to baud rate from 9600 to 250,000 bps. Terminal software like Tera Term [26] can be used to have an initial configuration of the devices. Any USB to TTL converter, for example, PL2303HX device or similar,

In the case of Bluetooth, the module only needs to be connected to the Rx of module to Tx of USB-TTL converter and Tx of module. It is necessary to connect ground and Vcc. HC-06 module is permanently configured to be slaved, and it

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

*Field Programmable Gate Arrays (FPGAs) II*

**Code 4. MUX\_SALIDA.vhd.**

**Code 5. MAQUINA\_FSM.vhd.**

**16**

#### **Code 6. PARIDAD.vhd.**

#### **4.4 Bluetooth and XBee modules**

The wireless modules are configured through AT commands. Command strings have the form ATxx (where xx is the name of a setting). The mode for both is slave to receive data from UART driver architecture. Bluetooth can be set to baud rate from 9600 to 921,600 bps. XBee can be set to baud rate from 9600 to 250,000 bps. Terminal software like Tera Term [26] can be used to have an initial configuration of the devices. Any USB to TTL converter, for example, PL2303HX device or similar, can be used.

In the case of Bluetooth, the module only needs to be connected to the Rx of module to Tx of USB-TTL converter and Tx of module. It is necessary to connect ground and Vcc. HC-06 module is permanently configured to be slaved, and it

is always in AT mode when not paired to any other device. AT commands can be founded in datasheets [27].

XBee configuration needs a test utility (XCTU) to enable users to interact with radio frequency (RF) devices through a graphical interface. The application includes built-in tools that make it easy to set up, configure, and test RF devices. The software can be downloaded from the Internet [28].

#### **4.5 Wi-fi driver**

ESP8266 Wi-Fi module is used to transmit the sensor data wirelessly to the Wi-Fi modem at the other end with Internet connection. ESP8266 can be initialized using a set of AT commands. Initialization process includes (a) verifying the communication between ESP8266 module and FPGA architecture (RST command) and (b) searching for a Wi-Fi network within its range and connecting to it, with the required credentials (CWJAP command). Sending process includes (a) setting the Wi-Fi module as a TCP/IP client (CIPSTART command); (b) transmitting data involves communication with cloud server using IP address (CIPSEND command). Address IP of the server is required to access the data from personal computing devices such laptop, tablet, and smartphone. **Figure 16** shows the AT command sequence and a block of Wi-Fi architecture:

#### **Figure 16.**

*AT command sequence. (a) Flow diagram of WEB connection [27]. (b) Block WI-FI driver module. (c) Code for AT command definition inside FPGA; green letters are comments about hexadecimal data.*

**19**

**Figure 18.**

**Figure 17.**

*oscilloscope.*

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

the corresponding practical wave and storage wave.

**5. Experimental results on graphical user interface (GUI)**

An analog signal is generated by the function generator to test the system, and the final data sent to the PC or WEB page is observed. **Figures 17**, **18** and **19** show

The GUI (**Figure 18**) was made using Java Eclipse Oxygen [29] and serial communication libraries (jSerialComm). jSerialComm is a Java library designed to provide a platform-independent way to access standard serial ports without requiring external

*Measurements of real signal sent to the host and WEB page. The signal has an offset = 3.98Vdc and 8.06Vpp and frequency of 60 Hz with harmonics of 3rd, 5th, 7th, and 9th. This signal is obtained from digital* 

*Data received from the remote DAQ system (Bluetooth or XBee module) using GUI development. Each cycle is* 

*represented by 133 samples (sampling frequency = 8 kHz). The UART baud rate is 115,200 bps.*

### **5. Experimental results on graphical user interface (GUI)**

An analog signal is generated by the function generator to test the system, and the final data sent to the PC or WEB page is observed. **Figures 17**, **18** and **19** show the corresponding practical wave and storage wave.

The GUI (**Figure 18**) was made using Java Eclipse Oxygen [29] and serial communication libraries (jSerialComm). jSerialComm is a Java library designed to provide a platform-independent way to access standard serial ports without requiring external

#### **Figure 17.**

*Field Programmable Gate Arrays (FPGAs) II*

The software can be downloaded from the Internet [28].

sequence and a block of Wi-Fi architecture:

founded in datasheets [27].

**4.5 Wi-fi driver**

is always in AT mode when not paired to any other device. AT commands can be

XBee configuration needs a test utility (XCTU) to enable users to interact with radio frequency (RF) devices through a graphical interface. The application includes built-in tools that make it easy to set up, configure, and test RF devices.

ESP8266 Wi-Fi module is used to transmit the sensor data wirelessly to the Wi-Fi modem at the other end with Internet connection. ESP8266 can be initialized using a set of AT commands. Initialization process includes (a) verifying the communication between ESP8266 module and FPGA architecture (RST command) and (b) searching for a Wi-Fi network within its range and connecting to it, with the required credentials (CWJAP command). Sending process includes (a) setting the Wi-Fi module as a TCP/IP client (CIPSTART command); (b) transmitting data involves communication with cloud server using IP address (CIPSEND command). Address IP of the server is required to access the data from personal computing devices such laptop, tablet, and smartphone. **Figure 16** shows the AT command

*AT command sequence. (a) Flow diagram of WEB connection [27]. (b) Block WI-FI driver module. (c) Code* 

*for AT command definition inside FPGA; green letters are comments about hexadecimal data.*

**18**

**Figure 16.**

*Measurements of real signal sent to the host and WEB page. The signal has an offset = 3.98Vdc and 8.06Vpp and frequency of 60 Hz with harmonics of 3rd, 5th, 7th, and 9th. This signal is obtained from digital oscilloscope.*

#### **Figure 18.**

*Data received from the remote DAQ system (Bluetooth or XBee module) using GUI development. Each cycle is represented by 133 samples (sampling frequency = 8 kHz). The UART baud rate is 115,200 bps.*

#### **Figure 19.**

*Data sent to WEB page through Wi-fi module. The WEB page was made on a XAMPP package that includes apache WEB server, MySQL, and PHP [31].*

libraries, native code, or any other tools. It is meant as an alternative to Rx-Tx and the (deprecated) Java Communications API, with increased ease of use, an enhanced support for timeouts, and the ability to open multiple ports simultaneously [30].

#### **6. Conclusions**

This chapter described a data acquisition system based on FPGA. Several architectures to ADC controller, UART communication, FIFO memory, and Wi-Fi configuration process were made to develop the system. Experiments show that the system can convert the analog signals to digital signal and send to host computer to Java GUI or WEB page in real-time. The data can be acquired by using custom sampling frequency and baud rate. The entire system is designed to be simple, stable, and low cost.

**21**

**Author details**

México

J. Guadalupe Velásquez-Aguilar\*, Outmane Oubram and Luis Cisneros-Villalobos

Engineering, Autonomous University of the State of Morelos, Cuernavaca, Morelos,

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

Faculty of Chemical Sciences and Engineering, Department of Electrical

\*Address all correspondence to: jgpeva@uaem.mx

provided the original work is properly cited.

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

*Field Programmable Gate Arrays (FPGAs) II*

libraries, native code, or any other tools. It is meant as an alternative to Rx-Tx and the (deprecated) Java Communications API, with increased ease of use, an enhanced support for timeouts, and the ability to open multiple ports simultaneously [30].

*Data sent to WEB page through Wi-fi module. The WEB page was made on a XAMPP package that includes* 

This chapter described a data acquisition system based on FPGA. Several architectures to ADC controller, UART communication, FIFO memory, and Wi-Fi configuration process were made to develop the system. Experiments show that the system can convert the analog signals to digital signal and send to host computer to Java GUI or WEB page in real-time. The data can be acquired by using custom sampling frequency and baud rate. The entire system is designed to be simple,

**20**

**6. Conclusions**

*apache WEB server, MySQL, and PHP [31].*

**Figure 19.**

stable, and low cost.

### **Author details**

J. Guadalupe Velásquez-Aguilar\*, Outmane Oubram and Luis Cisneros-Villalobos Faculty of Chemical Sciences and Engineering, Department of Electrical Engineering, Autonomous University of the State of Morelos, Cuernavaca, Morelos, México

\*Address all correspondence to: jgpeva@uaem.mx

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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[4] Jerraya AA, Mint WW. Hardware/ software interface codesign for embedded systems. Computer, IEEE. 2005;**38**:63-69

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**23**

*Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

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net/projects/xampp/

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[19] LTC2308 Datasheets, Linear Technology Corporation, 2007

[20] Cyclone V. Hard Processor System Technical Reference Manual, Intel FPGA; 2018. cv\_5v4 | 2019.06.14

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elec4200/vhdlmods.pdf

900-Manual.pdf

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en.pdf

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[16] Wi-Fi Alliance. Generational Wi-Fi User Guide. Available from: https://www.wi-fi.org/file/ generational-wi-fi-user-guide

[17] Rabbit Web site. An Introduction to Wi-Fi. Available *Real-Time FPGA-Based Systems to Remote Monitoring DOI: http://dx.doi.org/10.5772/intechopen.89629*

from: http://ftp1.digi.com/support/ documentation/0190170\_b.pdf

[18] Terasic, DE0-Nano-SoC User Manual. Available from: https:// media.digikey.com/pdf/Data%20 Sheets/Terasic%20Technologies/ DE0-Nano-SoC\_UM.pdf

[19] LTC2308 Datasheets, Linear Technology Corporation, 2007

[20] Cyclone V. Hard Processor System Technical Reference Manual, Intel FPGA; 2018. cv\_5v4 | 2019.06.14

[21] HC-06 Datasheets, Guangzhou HC Information Technology Co. Ltd. 2011. Available from: https://www. olimex.com/Products/Components/ RF/BLUETOOTH-SERIAL-HC-06/ resources/hc06.pdf

[22] Espressif. ESP8285 Datasheet. Available from: https://www. espressif.com/sites/default/files/ documentation/0a-esp8285\_datasheet\_ en.pdf

[23] Altera, Using the DE0-Nano ADC Controller. Available from: ftp://ftp. intel.com/Pub/fpgaup/.../Using\_DE0- Nano\_ADC.pdf

[24] Stroud CE. First-In First-Out (FIFO) Control Logic VHDL Modeling Example, ECE Department, Auburn University. Available from: http:// www.eng.auburn.edu/~strouce/class/ elec4200/vhdlmods.pdf

[25] Digi International Inc. XBee-PRO 900/ DigiMesh 900 OEM RF Modules. Available from: https://www.sparkfun. com/datasheets/Wireless/Zigbee/XBee-900-Manual.pdf

[26] Available from: https://tera-term. en.lo4d.com/windows

[27] Espressif. ESP8266 AT Command Examples. 2017. Available from: https:// espressif.com/sites/default/files/.../4besp8266\_at\_command\_examples\_en.pdf

[28] Available from: https://www. digi.com/products/iot-platform/ xctu#productsupport-utilities

[29] Available from: https://www.eclipse. org/

[30] Available from: https://fazecast. github.io/jSerialComm/

[31] Available from: https://sourceforge. net/projects/xampp/

**22**

*Field Programmable Gate Arrays (FPGAs) II*

[1] Siewert S, Pratt J, editors. Real-time embedded components and system with linux and RTOS. Mercury Learning and Information LLC; 2016. 483 p. ISBN:

[9] Symmetry Electronics, Bluetooth 1.0 vs 2.0,vs 3.0 vs 4.0 vs 5.0—How They Compare. Available from: https://www. semiconductorstore.com/blog/2018/ Bluetooth-1-0-vs-2-0-vs-3-0-vs-4-0 vs-5-0-How-They-Differ-Symmetry-

[10] Gupta NK, editor. Inside Bluetooth Low Energy. Artech House; 2016. 458 p.

[11] National Instruments. The Basic of ZigBee Transmitter Testing. Available

[13] Cunha A, Koubâa A, Severino R,

implementation\_of\_the\_ieee\_802\_15\_4\_ zigbee\_protocol\_stack\_on\_tinyos/381/

[15] Available from: https://www.wi-fi.org

[16] Wi-Fi Alliance. Generational Wi-Fi User Guide. Available from: https://www.wi-fi.org/file/ generational-wi-fi-user-guide

Introduction to Wi-Fi. Available

[14] Tennina S et al. editors. IEEE 802.15.4 and ZigBee as enabling Technologies for Low-Power Wireless Systems with Quality-of-Service Constraints. Springer; 2013. 173 p. DOI:

10.1007/978-3-642-37368-8

[17] Rabbit Web site. An

Alves M. Open-ZB: An opensource implementation of the IEEE 802.15.4/ZigBee protocol stack on TinyOS. Available from: https:// www.cister.isep.ipp.pt/docs/ open\_zb\_\_an\_open\_source\_

[12] Jaiswal L, Kaur J, Singh G. Performance analysis of backoff exponent behaviour at MAC layer in ZigBee sensor networks. International Journal of Computer Applications.

Blog/3147

ISBN: 978-1630810894

from: www.ni.com

2012;**57**(22)

view.pdf

[2] Mohit A editor. Embedded system design: Introduction to SoC system architecture. Learning Bytes Publishing; 2016. 214 p. ISBN: 978-0997297201

[3] Rajsuman R editor. System-on-a-Chip: Design and Test. Artech House; 2000. 294 p. ISBN: 978-1580531078

[4] Jerraya AA, Mint WW. Hardware/ software interface codesign for embedded systems. Computer, IEEE.

[5] Kirianaki N, Yurish S, Shpak N, Deynega V. Data Acquisition and Signal Processing for Smart Sensors. John Wiley & Sons Ltd; 2002. 291 p. ISBN:

[6] Velásquez-Aguilar JG, Aquino-Roblero F, Limón-Mendoza M, Cisneros-Villalobos L,

Zamudio-Lara A. Multi-channel data acquisition and wireless

communication FPGA-based system, to real-time remote monitoring. In: 2017 International Conference on Mechatronics, Electronics and Automotive Engineering (ICMEAE); 21-24 November 2017; Cuernavaca, México. IEEE; 2017. pp. 181-186

[7] Collotta M, Pau G, Salerno VM, Scatá G, editors. Wireless Sensor Networks to Improve Road Monitoring. IntechOpen; 2012. pp. 323-346. DOI:

[8] National Instruments. Introduction to Bluetooth Device Testing: From Theory to Transmitter and Receiver Measurements. Available from: http:// download.ni.com/evaluation/rf/ intro\_to\_bluetooth\_test.pdf

10.5772/48505.ch15

**References**

978-1942270041

2005;**38**:63-69

0-470843179

**Chapter 2**

*Yongbo Liao*

**Abstract**

Applications

Real-Time Echo State Network

In this chapter, a hardware processing architecture of real-time echo state network based on field-programmable gate array (FPGA) is proposed, which solves the problem that it is difficult to obtain the output weight of the network in real time. The design of this architecture strictly follows the reservoir calculation (RC) theory, and its five components are established in FPGA: input module, reservoir module, output module, training module, and system switch module. This paper implements the architecture in Altera FPGA chip and verifies it through the application of pattern recognition, waveform generation, and multiple-input multiple-output (MIMO) channel prediction. Experimental results show that the hardwareimplemented real-time echo state network can identify the duty cycle of different input signals, generate floating-point waveforms, and predict the MIMO channel by training. In this paper, a real-time echo state network based on field programmable gate array is proposed, which has the advantages of fast computation speed, less

**Keywords:** FPGA, ESN, pattern recognition, waveform generation, MIMO channel

Echo state network [1] simplifies training tasks into linear regression tasks. It mainly solves the problems of large consumption of Recurrent Neural Network (RNN) training resources, long running time, and slow convergence. There are many studies on the applications of echo state network, such as wind power ramp time prediction [2, 3], medical image recognition classification [4], water flow prediction [5], etc. There are also many studies on the structure of the echo state network, such as the dynamic reservoirs that increase their stochastic properties [6] or delay characteristics [7], correlation entropy replaces traditional error function [8], change calculation model [9, 10], etc. Less research work on hardware platform implementation of neural networks, such as [11] proposed a software framework for simulating RNN circuits, [12, 13] proposed FPGA/software framework; however these frameworks are always trained in software such as MATLAB, which not be strictly said to be hardware implementation. The FPGA-based real-time echo state network structure proposed in this chapter trains the output weights on the FPGA platform without calculating the relevant parameters by means of software. In

Based on FPGA and Its

resource consumption, and ideal simple task execution.

prediction, real-time, training, testing

**1. Introduction**

**25**

#### **Chapter 2**

### Real-Time Echo State Network Based on FPGA and Its Applications

*Yongbo Liao*

#### **Abstract**

In this chapter, a hardware processing architecture of real-time echo state network based on field-programmable gate array (FPGA) is proposed, which solves the problem that it is difficult to obtain the output weight of the network in real time. The design of this architecture strictly follows the reservoir calculation (RC) theory, and its five components are established in FPGA: input module, reservoir module, output module, training module, and system switch module. This paper implements the architecture in Altera FPGA chip and verifies it through the application of pattern recognition, waveform generation, and multiple-input multiple-output (MIMO) channel prediction. Experimental results show that the hardwareimplemented real-time echo state network can identify the duty cycle of different input signals, generate floating-point waveforms, and predict the MIMO channel by training. In this paper, a real-time echo state network based on field programmable gate array is proposed, which has the advantages of fast computation speed, less resource consumption, and ideal simple task execution.

**Keywords:** FPGA, ESN, pattern recognition, waveform generation, MIMO channel prediction, real-time, training, testing

#### **1. Introduction**

Echo state network [1] simplifies training tasks into linear regression tasks. It mainly solves the problems of large consumption of Recurrent Neural Network (RNN) training resources, long running time, and slow convergence. There are many studies on the applications of echo state network, such as wind power ramp time prediction [2, 3], medical image recognition classification [4], water flow prediction [5], etc. There are also many studies on the structure of the echo state network, such as the dynamic reservoirs that increase their stochastic properties [6] or delay characteristics [7], correlation entropy replaces traditional error function [8], change calculation model [9, 10], etc. Less research work on hardware platform implementation of neural networks, such as [11] proposed a software framework for simulating RNN circuits, [12, 13] proposed FPGA/software framework; however these frameworks are always trained in software such as MATLAB, which not be strictly said to be hardware implementation. The FPGA-based real-time echo state network structure proposed in this chapter trains the output weights on the FPGA platform without calculating the relevant parameters by means of software. In

order to verify the performance of the proposed architecture, two types of benchmark tasks were performed: the output signal which was a binary signal [14] and a floating point number signal and a MIMO channel prediction task [15].

#### **2. Theory and model**

This section describes the mathematical model of the echo state network. The structural model is shown in **Figure 1**. Let the model have *K* input units whose vector form is

$$u(n) = \left(u\_1(n), u\_2(n), \dots, \dots, u\_K(n)\right)^T \tag{1}$$

*N* reservoir units, the vector form is

$$\boldsymbol{\mathfrak{x}}(n) = \left(\boldsymbol{\mathfrak{x}}\_1, \boldsymbol{\mathfrak{x}}\_2, \dots, \boldsymbol{\mathfrak{x}}\_N\right)^T \tag{2}$$

function of the intermediate unit, mainly using the S function, but sometimes a

where (*u*(*n* + 1),*x*(*n* + 1)) represents the juxtaposition of the input and the intermediate state vector, as shown in the input layer to the output layer of the dashed arrow in **Figure 1**, in some applications, such as [16], where the data stream does not exist. That is, the output is calculated directly using the intermediate state value. The output transfer function is usually *f*out = tanh or *f*out = 1, depending on whether the output unit is nonlinear or linear. The output weight *W*out is calculated

*<sup>W</sup>out* <sup>¼</sup> *Yt*arg*etX<sup>T</sup> XX<sup>T</sup>* <sup>þ</sup> *<sup>α</sup>*<sup>2</sup>

where *I* ∈ *R<sup>N</sup>*�*<sup>N</sup>* is the identity matrix, α is the regularization factor, *R*∈ *R<sup>N</sup>*�*<sup>N</sup>* is the set matrix of ð Þ *u n*ð Þ <sup>þ</sup> <sup>1</sup> *;*ð Þ *x n*ð Þ <sup>þ</sup> <sup>1</sup> , *<sup>Y</sup>*target is the ideal output set matrix, and ð Þ• ‐<sup>1</sup>

Real-time FPGA echo state network execution structure maps Eqs. (6)–(8) to six modules, which are input module, reservoir module, output module, training module, system switch module, and random number generator, as shown in **Figure 2**. The input module is a two-input single-output module, and the input is a random input weight Win generated by a random number generator and an external signal *u*(*n* + 1), performing a *W* in *u*(*n* + 1) multiplication operation, and encoding the input signal to form a data signal that can be calculated by the reservoir module. The reservoir module is a five-input single-output module that strictly performs the remainder of Eq. (6), the input including the encoded external signal from the input module, reservoir initial state value (this input is the state value of the previous clock reservoir module output as the operation progresses), network expected output, reservoir interconnection weights generated by the random number generator, and feedback. Connecting the weight, output high-dimensional state signal, the

*y n*ð Þ¼ <sup>þ</sup> <sup>1</sup> *<sup>f</sup> out <sup>W</sup>out* ð Þ ð Þ *u n*ð Þ <sup>þ</sup> <sup>1</sup> *; x n*ð Þ <sup>þ</sup> <sup>1</sup> (7)

*I* �<sup>1</sup> (8)

linear network *f* = 1 is also used. Output calculation is based on

*Real-Time Echo State Network Based on FPGA and Its Applications*

*DOI: http://dx.doi.org/10.5772/intechopen.88820*

**3. Real-time FPGA echo state network structure**

according to the following formula:

specific circuit is shown in **Figure 3**.

*Real-time FPGA echo state network structure diagram.*

**Figure 2.**

**27**

is the matrix inversion.

*L* output units whose vector form is

$$\mathbf{y}(n) = \begin{pmatrix} \mathbf{y}\_1, \mathbf{y}\_2, \dots, \mathbf{y}\_L \end{pmatrix}^T \tag{3}$$

where (•)*T* is the transpose, n is the discrete time, and the input/reservoir/ output connection weight is represented by a weight matrix of size N � K/N � N/L�(K + N), i.e.

$$\mathcal{W}^{in} = \left(w^{i,n}\_{i,j}\right), \mathcal{W} = \left(w\_{i,j}\right), \mathcal{W}^{out} = \left(w^{out}\_{ij}\right) \tag{4}$$

The output unit can select whether to feed back to the intermediate unit and the connection weight is represented by a feedback weight matrix of size N � L:

$$\boldsymbol{W}^{\text{back}} = \left(\boldsymbol{w}\_{\vec{\boldsymbol{\eta}}}^{\text{back}}\right) \tag{5}$$

Intermediate cell status updates according to the formula

$$\mathbf{x}(n+1) = f\left(\mathbf{W}^{in}u(n+1) + \mathbf{W}\mathbf{x}(n) + \mathbf{W}^{back}y\_{\text{target}}(n)\right) \tag{6}$$

where u(n + 1) is the external given input at time n + 1, such as Eq. (1); ytarget(n) is the ideal output at time n, in the form of Eq. (2); and f represents the transfer

**Figure 1.** *The basic structure of the echo state network. The arrows indicate the flow of data.*

order to verify the performance of the proposed architecture, two types of benchmark tasks were performed: the output signal which was a binary signal [14] and a

This section describes the mathematical model of the echo state network. The structural model is shown in **Figure 1**. Let the model have *K* input units whose

*u n*ð Þ¼ ð Þ *u*1ð Þ *n ; u*2ð Þ *n* ⋯⋯⋯*uK*ð Þ *n*

*x n*ð Þ¼ ð Þ *x*1*; x*2⋯⋯⋯*xN*

*y n*ð Þ¼ *y*1*; y*2⋯⋯⋯*yL*

where (•)*T* is the transpose, n is the discrete time, and the input/reservoir/ output connection weight is represented by a weight matrix of size N � K/N �

*, W* ¼ *wi,j*

*<sup>W</sup>*back <sup>¼</sup> *<sup>w</sup>back*

*x n*ð Þ¼ <sup>þ</sup> <sup>1</sup> *f Winu n*ð Þþ <sup>þ</sup> <sup>1</sup> *Wx n*ð Þþ *<sup>W</sup>backyt*arg*et*ð Þ *<sup>n</sup>*

where u(n + 1) is the external given input at time n + 1, such as Eq. (1); ytarget(n) is the ideal output at time n, in the form of Eq. (2); and f represents the transfer

connection weight is represented by a feedback weight matrix of size N � L:

The output unit can select whether to feed back to the intermediate unit and the

*ij* 

*,Wout* <sup>¼</sup> *<sup>w</sup>out*

*<sup>T</sup>* (1)

(4)

(5)

(6)

*<sup>T</sup>* (2)

*<sup>T</sup>* (3)

*ij* 

floating point number signal and a MIMO channel prediction task [15].

**2. Theory and model**

*N* reservoir units, the vector form is

*Field Programmable Gate Arrays (FPGAs) II*

*L* output units whose vector form is

*<sup>W</sup>in* <sup>¼</sup> *<sup>w</sup>i,n*

*i,j* 

Intermediate cell status updates according to the formula

*The basic structure of the echo state network. The arrows indicate the flow of data.*

vector form is

N/L�(K + N), i.e.

**Figure 1.**

**26**

function of the intermediate unit, mainly using the S function, but sometimes a linear network *f* = 1 is also used. Output calculation is based on

$$\mathcal{Y}(n+1) = f\_{out}(\mathcal{W}^{out}(\mu(n+1), \mathfrak{x}(n+1)))\tag{7}$$

where (*u*(*n* + 1),*x*(*n* + 1)) represents the juxtaposition of the input and the intermediate state vector, as shown in the input layer to the output layer of the dashed arrow in **Figure 1**, in some applications, such as [16], where the data stream does not exist. That is, the output is calculated directly using the intermediate state value. The output transfer function is usually *f*out = tanh or *f*out = 1, depending on whether the output unit is nonlinear or linear. The output weight *W*out is calculated according to the following formula:

$$\mathcal{W}^{out} = Y\_{\text{target}} \mathbf{X}^T \left(\mathbf{X}\mathbf{X}^T + a^2 I\right)^{-1} \tag{8}$$

where *I* ∈ *R<sup>N</sup>*�*<sup>N</sup>* is the identity matrix, α is the regularization factor, *R*∈ *R<sup>N</sup>*�*<sup>N</sup>* is the set matrix of ð Þ *u n*ð Þ <sup>þ</sup> <sup>1</sup> *;*ð Þ *x n*ð Þ <sup>þ</sup> <sup>1</sup> , *<sup>Y</sup>*target is the ideal output set matrix, and ð Þ• ‐<sup>1</sup> is the matrix inversion.

#### **3. Real-time FPGA echo state network structure**

Real-time FPGA echo state network execution structure maps Eqs. (6)–(8) to six modules, which are input module, reservoir module, output module, training module, system switch module, and random number generator, as shown in **Figure 2**. The input module is a two-input single-output module, and the input is a random input weight Win generated by a random number generator and an external signal *u*(*n* + 1), performing a *W* in *u*(*n* + 1) multiplication operation, and encoding the input signal to form a data signal that can be calculated by the reservoir module. The reservoir module is a five-input single-output module that strictly performs the remainder of Eq. (6), the input including the encoded external signal from the input module, reservoir initial state value (this input is the state value of the previous clock reservoir module output as the operation progresses), network expected output, reservoir interconnection weights generated by the random number generator, and feedback. Connecting the weight, output high-dimensional state signal, the specific circuit is shown in **Figure 3**.

**Figure 2.** *Real-time FPGA echo state network structure diagram.*

signals, providing a logic cell array that can be configured as a given function via a bitstream file. Its basic digital logic, the smallest programmable logic unit, is the logic gate. Therefore, FPGAs are the best device for performing echo state networks. The architecture is all implemented in the FPGA. On the one hand, the dynamic reservoir (i.e., the middle layer) is established. On the other hand, how to obtain the real-time output weights when the input signal is the digital signal "0" or

The dataflow and training process of the real-time FPGA echo state network

Given: Input and target output sequence *u*(*n*) and *y*target(*n*), n ¼ 1⋯⋯*T*. Objective: The teacher signal input/output training acquires *W*out and acquires

The random number generator module generates an input, a reservoir, and a feedback weight of the echo state network and sends the input and feedback weights

The reservoir module receives the encoded signal sent by the input module, loads the target output signal, acquires the feature value, and sends it to the output

The training module loads the input signal, the target output signal, and the characteristic value sent by the reservoir module; calculates the output weight; sends the result to the output module; and determines whether to stop training

The output module loads the input signal and calculates the network output according to the characteristic value sent by the reservoir module and the output weight sent by the training module and sends the network output value to the

The system switch module loads the target output signal and the network output signal to determine whether the match is matched and sends the judgment result back to the training module. If it matches, it sends back *S* = 0; if it does not match, it

Repeat steps 2–6 until the judgment result of the system switch module is to stop

A total of two types of benchmark task experiments were performed: the output signal was a binary signal and a floating point number signal and a multiple-input multiple-output channel prediction task experiment. The programming language is Verilog HDL, the chip uses Altera Stratix III FPGA, and the integrated place and

The pattern recognition reference task with different duty cycles is very similar to the memory resistance based on reservoir calculation (RC) in [14]. The mode signals with different duty cycles are shown in **Figure 5**. The input signal of the echo

This is followed by the regular echo state network function, which only performs input, reservoir, and output modules and outputs network prediction values.

The input module loads the input signal, encodes the input signal, and sends it to

to the input module, and the reservoir weight is sent to the reservoir module.

"1" is established.

Proceed as follows:

the reservoir module.

sends back *S* = 1;

**29**

training, that is, *S* = 0.

**4. Experiment and analysis**

route are implemented in QUARTUS II.

**4.1 Different duty cycle signal pattern recognition**

module and the training module.

structure will be briefly described as follows:

*DOI: http://dx.doi.org/10.5772/intechopen.88820*

the network output signal by loading the input signal.

*Real-Time Echo State Network Based on FPGA and Its Applications*

according to the signal sent by the system switch module.

system switch module and outputs the actual network value.

(**Figure 3** circuit is the circuit that outputs the reservoir state x1, other state circuits are similar). The output module is a three-input single-output module, the input is an external input signal, the state value is obtained by the reservoir module calculation, and the output connection weight is calculated by the training module. The output is the final acquired network output. The function is to perform simple multiplication and addition on the input data and decode the result to form an output signal. The training module is a three-input single-output module, the input is an externally given desired output, a status signal is generated by the reservoir module, and an enable signal *S* is sent by the system switch module, When *S* = 0, the module stops working. When *S* = 1, the module works, and the output is the core parameter output connection weight of the echo state network. The function is expressed as Eq. (8). The specific implementation mechanism is shown in **Figure 4** (in Eq. (8)), *Yt*arg*etX<sup>T</sup>* <sup>¼</sup> ð Þ *ait* , *XX<sup>T</sup>* <sup>þ</sup> *<sup>α</sup>*<sup>2</sup>*<sup>I</sup>* <sup>¼</sup> *dtj* , *XX<sup>T</sup>* <sup>þ</sup> *<sup>α</sup>*<sup>2</sup>*<sup>I</sup>* ‐<sup>1</sup> <sup>¼</sup> *btj* , *<sup>W</sup>out* <sup>¼</sup> *cij* ; then, the output weight *<sup>W</sup>out* <sup>¼</sup> *cij* is obtained; The system switch module is a two-input single-output module. The input is a network output signal and a desired output signal. The output is an enable signal for controlling the operation of the training module. Its function is mainly to judge the network performance. When the network output signal matches the expected output signal or the difference is within the receiving range, the output *S* = 0 and the other cases continue to output *S* = 1. A random number generator is used to generate inputs, reservoirs, and feedback weights.

The following sections detail how to train a real-time FPGA echo state network. As is well known, FPGAs implement digital systems that primarily process digital

#### *Real-Time Echo State Network Based on FPGA and Its Applications DOI: http://dx.doi.org/10.5772/intechopen.88820*

signals, providing a logic cell array that can be configured as a given function via a bitstream file. Its basic digital logic, the smallest programmable logic unit, is the logic gate. Therefore, FPGAs are the best device for performing echo state networks. The architecture is all implemented in the FPGA. On the one hand, the dynamic reservoir (i.e., the middle layer) is established. On the other hand, how to obtain the real-time output weights when the input signal is the digital signal "0" or "1" is established.

The dataflow and training process of the real-time FPGA echo state network structure will be briefly described as follows:

Given: Input and target output sequence *u*(*n*) and *y*target(*n*), n ¼ 1⋯⋯*T*. Objective: The teacher signal input/output training acquires *W*out and acquires

the network output signal by loading the input signal.

Proceed as follows:

The random number generator module generates an input, a reservoir, and a feedback weight of the echo state network and sends the input and feedback weights to the input module, and the reservoir weight is sent to the reservoir module.

The input module loads the input signal, encodes the input signal, and sends it to the reservoir module.

The reservoir module receives the encoded signal sent by the input module, loads the target output signal, acquires the feature value, and sends it to the output module and the training module.

The training module loads the input signal, the target output signal, and the characteristic value sent by the reservoir module; calculates the output weight; sends the result to the output module; and determines whether to stop training according to the signal sent by the system switch module.

The output module loads the input signal and calculates the network output according to the characteristic value sent by the reservoir module and the output weight sent by the training module and sends the network output value to the system switch module and outputs the actual network value.

The system switch module loads the target output signal and the network output signal to determine whether the match is matched and sends the judgment result back to the training module. If it matches, it sends back *S* = 0; if it does not match, it sends back *S* = 1;

Repeat steps 2–6 until the judgment result of the system switch module is to stop training, that is, *S* = 0.

This is followed by the regular echo state network function, which only performs input, reservoir, and output modules and outputs network prediction values.

#### **4. Experiment and analysis**

A total of two types of benchmark task experiments were performed: the output signal was a binary signal and a floating point number signal and a multiple-input multiple-output channel prediction task experiment. The programming language is Verilog HDL, the chip uses Altera Stratix III FPGA, and the integrated place and route are implemented in QUARTUS II.

#### **4.1 Different duty cycle signal pattern recognition**

The pattern recognition reference task with different duty cycles is very similar to the memory resistance based on reservoir calculation (RC) in [14]. The mode signals with different duty cycles are shown in **Figure 5**. The input signal of the echo

(**Figure 3** circuit is the circuit that outputs the reservoir state x1, other state circuits are similar). The output module is a three-input single-output module, the input is an external input signal, the state value is obtained by the reservoir module calculation, and the output connection weight is calculated by the training module. The output is the final acquired network output. The function is to perform simple multiplication and addition on the input data and decode the result to form an output signal. The training module is a three-input single-output module, the input is an externally given desired output, a status signal is generated by the reservoir module, and an enable signal *S* is sent by the system switch module, When *S* = 0, the module stops working. When *S* = 1, the module works, and the output is the core parameter output connection weight of the echo state network. The function is expressed as Eq. (8). The specific implementation mechanism is shown in **Figure 4** (in Eq. (8)), *Yt*arg*etX<sup>T</sup>* <sup>¼</sup> ð Þ *ait* ,

*Training module. Subscript z represents the zth unit of input, reservoir, and output.*

, *<sup>W</sup>out* <sup>¼</sup> *cij*

The following sections detail how to train a real-time FPGA echo state network. As is well known, FPGAs implement digital systems that primarily process digital

ule. The input is a network output signal and a desired output signal. The output is an enable signal for controlling the operation of the training module. Its function is mainly to judge the network performance. When the network output signal matches the expected output signal or the difference is within the receiving range, the output *S* = 0 and the other cases continue to output *S* = 1. A random number generator is used to

is obtained; The system switch module is a two-input single-output mod-

; then, the output weight

*XX<sup>T</sup>* <sup>þ</sup> *<sup>α</sup>*<sup>2</sup>*<sup>I</sup>* <sup>¼</sup> *dtj*

*<sup>W</sup>out* <sup>¼</sup> *cij*

**28**

**Figure 3.** *Reservoir module.*

*Field Programmable Gate Arrays (FPGAs) II*

**Figure 4.**

, *XX<sup>T</sup>* <sup>þ</sup> *<sup>α</sup>*<sup>2</sup>*<sup>I</sup>* ‐<sup>1</sup> <sup>¼</sup> *btj*

generate inputs, reservoirs, and feedback weights.


performed in MATLAB when the echo state network is proposed in [1]. The ideal sine wave signal is given by the equation *yt*arg*et*ðÞ¼ *t* sin ð Þ *t=*8 . There is no input in this experiment, so set *Win* to 0; W and *Wback* are matrices formed by random numbers, and the basic unit of the echo state network is the standard S unit (i.e., the activation function is S function tanh), and the training result is shown in **Figure 8**. In the process of generating sine wave training, the ideal output signal (*Yt*arg*et*) is a floating point number, so the actual output signal (Yr), the normalized root mean square error signal (*E*), and the output weight signal (Wout1, Wout2, Wout3, Wout4) are all floating point numbers. The training error is calculated in the system switch module, and *E* = 3D0228E7h is calculated according to the normalized root

*Real-Time Echo State Network Based on FPGA and Its Applications*

output weights Wout1, Wout2, Wout3, and Wout4 of the training module are BDFEDD9Dh, 3CB22AA8h, 3CA0BDD8h, and 3F55E542h, respectively. The waveform shown in **Figure 9** is acquired by the SignalTap II logic analyzer and is a floating-point sine wave generated for the trained echo state network. The Altera floating-point IP core was used in the experiment to set up the echo state network. As shown in **Figure 10**, the top is the *Y* target signal, the middle is the actual output *y* signal of the network, and the bottom is the error waveform of the network

Recurrent neural networks have been widely used in MIMO systems [17–23]. Echo state networks are a way to train recurrent neural networks. They have faster convergence characteristics, and more efficient tracking channel state changes than other traditional training methods. For a 2 � 2 multiple-input multiple-output system with a binary phase shift keying (BPSK) modulator, as shown in **Figure 11**, the zero-forcing equalizer used in the receiver section can reduce symbol interference (ISI) due to the precise channel. It is estimated that the zero-forcing equalization can be improved by the degraded radio channel, and therefore the proposed

The matrix equation of the MIMO system shown in **Figure 11** is given as

*x*2 � �

þ

*n*1 *n*2

� � (9)

<sup>¼</sup> *<sup>h</sup>*<sup>11</sup> *<sup>h</sup>*<sup>12</sup> *<sup>h</sup>*<sup>21</sup> *<sup>h</sup>*<sup>22</sup> � � *<sup>x</sup>*<sup>1</sup>

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

*yt*arg*et* ð Þ ð Þ� *<sup>n</sup> y n*ð Þ <sup>2</sup> *<sup>N</sup>*�var *<sup>y</sup>* ð Þ *<sup>t</sup>*arg*et* <sup>s</sup>

. The optimized

P*<sup>N</sup> n*¼1

mean square error calculation equation *E* ¼

*DOI: http://dx.doi.org/10.5772/intechopen.88820*

expected output and the actual output.

architecture is used for MIMO channel prediction.

*y*1 *y*2 � �

**4.3 MIMO channel prediction**

**Figure 8.**

**Figure 9.**

**31**

*Sine wave generation training.*

*Echo state network generating floating point sine wave.*

#### **Figure 5.**

*Different duty cycle pattern recognition training.*

state network is *U*, the expected output is *Y* target, and the actual output signal is Yr; Wo1 and Wo2 are output weights, and B is the bias signal. The second line (signal Y\_target) represents the expected response of the first line (signal U). When the duty cycle of the input signal is less than 50%, the signal Y\_target should converge to 0 and should converge to 1 for a duty cycle greater than 50%. As shown in **Figure 5**, the online training echo state network in the FPGA obtains Wo1, Wo2, and B, and their values are 00Eh, 00Ah, and FC1h, respectively. After the output weight is obtained, different duty cycle mode signals are loaded into the trained echo state network, and the result is as shown in **Figure 6**. The output signal (Yr) changes between a duty cycle of the input signal (U) greater than 50% and less than 50%.

**Figure 7** is a graph showing the percentage of the total number of nerve cells implemented in the FPGA logic and FPGA and the error curve. It can be seen that the logic utilization is less than 60% until the number of neurons is 512 units. When the number of nerves exceeds 16 units, the error between the actual output signal and the ideal output is zero. Therefore, the circuit resources proposed in this paper consume less, and the convergence speed is faster.

#### **4.2 Sine wave generator**

Here we test how to train the echo state network to generate a sine wave signal, which is a floating point number, which is very similar to the simple sine wave test


**Figure 6.**

*Echo state network test results.*

**Figure 7.** *Relationship between neuron number and logic utilization and error curve.*

*Real-Time Echo State Network Based on FPGA and Its Applications DOI: http://dx.doi.org/10.5772/intechopen.88820*

performed in MATLAB when the echo state network is proposed in [1]. The ideal sine wave signal is given by the equation *yt*arg*et*ðÞ¼ *t* sin ð Þ *t=*8 . There is no input in this experiment, so set *Win* to 0; W and *Wback* are matrices formed by random numbers, and the basic unit of the echo state network is the standard S unit (i.e., the activation function is S function tanh), and the training result is shown in **Figure 8**. In the process of generating sine wave training, the ideal output signal (*Yt*arg*et*) is a floating point number, so the actual output signal (Yr), the normalized root mean square error signal (*E*), and the output weight signal (Wout1, Wout2, Wout3, Wout4) are all floating point numbers. The training error is calculated in the system switch module, and *E* = 3D0228E7h is calculated according to the normalized root

mean square error calculation equation *E* ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi P*<sup>N</sup> n*¼1 *yt*arg*et* ð Þ ð Þ� *<sup>n</sup> y n*ð Þ <sup>2</sup> *<sup>N</sup>*�var *<sup>y</sup>* ð Þ *<sup>t</sup>*arg*et* <sup>s</sup> . The optimized

output weights Wout1, Wout2, Wout3, and Wout4 of the training module are BDFEDD9Dh, 3CB22AA8h, 3CA0BDD8h, and 3F55E542h, respectively. The waveform shown in **Figure 9** is acquired by the SignalTap II logic analyzer and is a floating-point sine wave generated for the trained echo state network. The Altera floating-point IP core was used in the experiment to set up the echo state network. As shown in **Figure 10**, the top is the *Y* target signal, the middle is the actual output *y* signal of the network, and the bottom is the error waveform of the network expected output and the actual output.

#### **4.3 MIMO channel prediction**

Recurrent neural networks have been widely used in MIMO systems [17–23]. Echo state networks are a way to train recurrent neural networks. They have faster convergence characteristics, and more efficient tracking channel state changes than other traditional training methods. For a 2 � 2 multiple-input multiple-output system with a binary phase shift keying (BPSK) modulator, as shown in **Figure 11**, the zero-forcing equalizer used in the receiver section can reduce symbol interference (ISI) due to the precise channel. It is estimated that the zero-forcing equalization can be improved by the degraded radio channel, and therefore the proposed architecture is used for MIMO channel prediction.

The matrix equation of the MIMO system shown in **Figure 11** is given as

$$
\begin{bmatrix} \mathcal{Y}\_1 \\ \mathcal{Y}\_2 \end{bmatrix} = \begin{bmatrix} h\_{11} & h\_{12} \\ h\_{21} & h\_{22} \end{bmatrix} \begin{bmatrix} \mathcal{X}\_1 \\ \mathcal{X}\_2 \end{bmatrix} + \begin{bmatrix} n\_1 \\ n\_2 \end{bmatrix} \tag{9}
$$


#### **Figure 8.**

state network is *U*, the expected output is *Y* target, and the actual output signal is Yr; Wo1 and Wo2 are output weights, and B is the bias signal. The second line (signal Y\_target) represents the expected response of the first line (signal U). When the duty cycle of the input signal is less than 50%, the signal Y\_target should converge to 0 and should converge to 1 for a duty cycle greater than 50%. As shown in **Figure 5**, the online training echo state network in the FPGA obtains Wo1, Wo2, and B, and their values are 00Eh, 00Ah, and FC1h, respectively. After the output weight is obtained, different duty cycle mode signals are loaded into the trained echo state network, and the result is as shown in **Figure 6**. The output signal (Yr) changes between a duty

**Figure 7** is a graph showing the percentage of the total number of nerve cells implemented in the FPGA logic and FPGA and the error curve. It can be seen that the logic utilization is less than 60% until the number of neurons is 512 units. When the number of nerves exceeds 16 units, the error between the actual output signal and the ideal output is zero. Therefore, the circuit resources proposed in this paper

Here we test how to train the echo state network to generate a sine wave signal, which is a floating point number, which is very similar to the simple sine wave test

cycle of the input signal (U) greater than 50% and less than 50%.

consume less, and the convergence speed is faster.

*Relationship between neuron number and logic utilization and error curve.*

**4.2 Sine wave generator**

*Echo state network test results.*

**Figure 6.**

**Figure 7.**

**30**

**Figure 5.**

*Different duty cycle pattern recognition training.*

*Field Programmable Gate Arrays (FPGAs) II*

*Sine wave generation training.*

**Figure 9.**

*Echo state network generating floating point sine wave.*

**Figure 10.** *Target signal (ytarget), actual signal (y), and error curve (number of neurons is 8).*

**Figure 11.** *2* � *2 MIMO system.*

The system can be represented as a compact form *Y* = HX + *n*, where *Y* is a 2 � 1 received signal vector, *H* is a 2 � 2 channel coefficient matrix, *X* is a 2 � 1 propagation vector, and *n* is a 2 � 1 additive white Gaussian noise vector. The channel is considered to be a Rayleigh decay with a mean of 0 and a variance of 0.5. At the receiving end, the zero-forcing equalization performs the prediction of the propagated signal, and the equation is

$$
\hat{X} = \left(H^H H\right)^{-1} H Y \tag{10}
$$

network module (ch\_test). In the transmitting module (fx), the signals x1r, x2r and x1i, x2i are the real and imaginary parts of the MIMO system input signals X1 and X2, respectively, and h11r, h12r, h21r, h22r and h11i, h12i, h21i, h22i are, respectively, MIMO channels. The real and imaginary parts of the coefficient, y1r, y2r and y1i, y2i are the real and imaginary parts of the received signal, respectively. In the receiving module (rx), a11, a12, a21, a22 and b11, b12, b21, b22 are the real and imaginary parts of the channel prediction coefficients, and the output is calculated by the echo state network module (ch\_test), c1, c2, and d1. d2 is the real and imaginary part of *X*^, respectively, corresponding to the demodulated signal X, and

the signal "detu" is the demodulation scale factor of c1, c2, d1 and d2.

**Figure 12.**

**Figure 13.**

**Figure 14.**

**33**

*RTL circuit diagram obtained by FPGA synthesis.*

*Echo state network for 2 2 MIMO systems.*

*DOI: http://dx.doi.org/10.5772/intechopen.88820*

*Echo state network channel prediction strategy structure diagram.*

*Real-Time Echo State Network Based on FPGA and Its Applications*

where *HHH* �<sup>1</sup> *H* represents the pseudo inverse of *H*. The predicted *X*^ loaded BPSK demodulator recovers the original information.

In order to dynamically update the channel state at each step, an echo state network is added to the 2 � 2 MIMO system in **Figure 11**. The system structure diagram after adding the echo state network is shown in **Figure 12**. The echo state network channel prediction strategy is shown in **Figure 13**. The channel coefficients are trained in the echo state network channel prediction. Once the training is completed, the echo state network channel prediction can automatically generate the predicted channel coefficients, and the predicted channel coefficients are loaded into the zero-forcing equalization, thereby completing the MIMO channel prediction.

**Figure 14** shows the RTL level circuit diagram generated by the FPGA. The system mainly includes a transmitter (fx), a receiver (rx), and an echo state

*Real-Time Echo State Network Based on FPGA and Its Applications DOI: http://dx.doi.org/10.5772/intechopen.88820*

#### **Figure 12.**

*Echo state network for 2 2 MIMO systems.*

#### **Figure 13.**

The system can be represented as a compact form *Y* = HX + *n*, where *Y* is a 2 � 1 received signal vector, *H* is a 2 � 2 channel coefficient matrix, *X* is a 2 � 1 propagation vector, and *n* is a 2 � 1 additive white Gaussian noise vector. The channel is considered to be a Rayleigh decay with a mean of 0 and a variance of 0.5. At the receiving end, the zero-forcing equalization performs the prediction of the propa-

*<sup>X</sup>*^ <sup>¼</sup> *<sup>H</sup>HH* �<sup>1</sup>

In order to dynamically update the channel state at each step, an echo state network is added to the 2 � 2 MIMO system in **Figure 11**. The system structure diagram after adding the echo state network is shown in **Figure 12**. The echo state network channel prediction strategy is shown in **Figure 13**. The channel coefficients are trained in the echo state network channel prediction. Once the training is completed, the echo state network channel prediction can automatically generate the predicted channel coefficients, and the predicted channel coefficients are loaded into the zero-forcing equalization, thereby completing the MIMO channel prediction. **Figure 14** shows the RTL level circuit diagram generated by the FPGA. The system mainly includes a transmitter (fx), a receiver (rx), and an echo state

*H* represents the pseudo inverse of *H*. The predicted *X*^ loaded

*HY* (10)

gated signal, and the equation is

BPSK demodulator recovers the original information.

*Target signal (ytarget), actual signal (y), and error curve (number of neurons is 8).*

*Field Programmable Gate Arrays (FPGAs) II*

where *HHH* �<sup>1</sup>

**Figure 10.**

**Figure 11.** *2* � *2 MIMO system.*

**32**

*Echo state network channel prediction strategy structure diagram.*

**Figure 14.** *RTL circuit diagram obtained by FPGA synthesis.*

network module (ch\_test). In the transmitting module (fx), the signals x1r, x2r and x1i, x2i are the real and imaginary parts of the MIMO system input signals X1 and X2, respectively, and h11r, h12r, h21r, h22r and h11i, h12i, h21i, h22i are, respectively, MIMO channels. The real and imaginary parts of the coefficient, y1r, y2r and y1i, y2i are the real and imaginary parts of the received signal, respectively. In the receiving module (rx), a11, a12, a21, a22 and b11, b12, b21, b22 are the real and imaginary parts of the channel prediction coefficients, and the output is calculated by the echo state network module (ch\_test), c1, c2, and d1. d2 is the real and imaginary part of *X*^, respectively, corresponding to the demodulated signal X, and the signal "detu" is the demodulation scale factor of c1, c2, d1 and d2.


experimental results, the echo state network is faster, the resources are less occupied, and the simple task execution is ideal. In future research work, the proposed FPGA real-time echo state network will be used in more complex 5G-based wireless

*Real-Time Echo State Network Based on FPGA and Its Applications*

*DOI: http://dx.doi.org/10.5772/intechopen.88820*

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

Electronic Science and Technology of China, Chengdu, China

\*Address all correspondence to: lyb@uestc.edu.com

provided the original work is properly cited.

MIMO-OFDM systems.

**Author details**

Yongbo Liao

**35**

**Figure 15.**

*Real-time waveforms for channel prediction in MIMO systems and echo state networks.*


#### **Figure 16.**

*C3 partial enlargement result.*

The designed MIMO system is downloaded to the FPGA chip through a bitstream file, and the waveform result is obtained by a SignalTap II logic analyzer, as shown in **Figure 15**. It can be seen from the waveform diagram that the signal waveforms of the C1 and C2 parts are completely identical. In the C1 portion, the signals in1 and in2 correspond to x1r and x2r, respectively, and in the C2 portion, the signals oute1 and oute2 correspond to the real part of the signal X. X1r, x2r, and x1i, x2i are the real and imaginary parts before demodulation of the demodulated signal, respectively.

In order to be able to explain the C3 part, the C3 part is enlarged here (see **Figure 16**). As can be seen from the C3 section, the received signals Y1 and Y2 and the estimated channel matrix are all changed. However, zero-forcing equalization can still predict values x1r, x2r, and C through the echo state network. After the processing is completed, BPSK demodulation signals "oute1" and "oute2" are obtained.

#### **5. Conclusion**

The real-time FPGA echo state network structure is proposed and studied. The input weight and the reservoir weight are randomly determined before training, and the output weight is calculated in real time in the FPGA by training the echo state network. In the above two benchmark experiments (pattern recognition and waveform generation) and MIMO channel prediction experiments, the proposed hardware architecture can recognize the duty cycle of different input signals, generate floating point waveforms, and predict channel coefficients. From the

*Real-Time Echo State Network Based on FPGA and Its Applications DOI: http://dx.doi.org/10.5772/intechopen.88820*

experimental results, the echo state network is faster, the resources are less occupied, and the simple task execution is ideal. In future research work, the proposed FPGA real-time echo state network will be used in more complex 5G-based wireless MIMO-OFDM systems.

### **Author details**

Yongbo Liao

The designed MIMO system is downloaded to the FPGA chip through a bitstream file, and the waveform result is obtained by a SignalTap II logic analyzer, as shown in **Figure 15**. It can be seen from the waveform diagram that the signal waveforms of the C1 and C2 parts are completely identical. In the C1 portion, the signals in1 and in2 correspond to x1r and x2r, respectively, and in the C2 portion, the signals oute1 and oute2 correspond to the real part of the signal X. X1r, x2r, and x1i, x2i are the real and imaginary parts before demodulation of the demodulated signal, respectively. In order to be able to explain the C3 part, the C3 part is enlarged here (see **Figure 16**). As can be seen from the C3 section, the received signals Y1 and Y2 and the estimated channel matrix are all changed. However, zero-forcing equalization can still predict values x1r, x2r, and C through the echo state network. After the processing is

completed, BPSK demodulation signals "oute1" and "oute2" are obtained.

*Real-time waveforms for channel prediction in MIMO systems and echo state networks.*

*Field Programmable Gate Arrays (FPGAs) II*

The real-time FPGA echo state network structure is proposed and studied. The input weight and the reservoir weight are randomly determined before training, and the output weight is calculated in real time in the FPGA by training the echo state network. In the above two benchmark experiments (pattern recognition and waveform generation) and MIMO channel prediction experiments, the proposed hardware architecture can recognize the duty cycle of different input signals, generate floating point waveforms, and predict channel coefficients. From the

**5. Conclusion**

**34**

**Figure 15.**

**Figure 16.**

*C3 partial enlargement result.*

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China

\*Address all correspondence to: lyb@uestc.edu.com

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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[22] Lukoševičius M. A Practical Guide to Applying Echo State Networks.

[23] Dorado-Moreno M, Cornejo-Bueno L, Gutiérrez PA, et al. Robust estimation

of wind power ramp events with reservoir computing. Renewable Energy. 2017;**111**:428-437

**12**(6):658-662

**90**(2):440-450

322-331

[10] Schrauwen B, D'Haene M, Verstraeten D, et al. Compact hardware liquid state machines on FPGA for realtime speech recognition. Neural Networks the Official Journal of the International Neural Network Society. 2008;**21**(2–3):511

[11] Alomar ML, Canals V, Martinez-Moll V, et al. Low-cost hardware implementation of reservoir computers. In: International Workshop on Power and Timing Modeling, Optimization and Simulation. IEEE; 2014. pp. 1-5

[12] Jaeger H. Tutorial on Training Recurrent Neural Networks, Covering BPPT, RTRL, EKF and the Echo State Network Approach - First revision. 2002. 7 p

[13] Sun X, Li T, Li Q, et al. Deep belief echo-state network and its application to time series prediction. Knowledge-Based Systems. 2017;**130**(15):17-29

[14] Yi Y, Liao Y, Wang B, et al. FPGA based spike-time dependent encoder and reservoir design in neuromorphic computing processors. Microprocessors and Microsystems. 2016;**46**(PB):175-183

[15] Jaeger H, Haas H. Harnessing nonlinearity: Predicting chaotic systems and saving energy in wireless communication. Science. 2004; **304**(5667):78-80

[16] Kulkarni MS, Teuscher C. Memristor-based reservoir computing. In: IEEE/ACM International Symposium on Nanoscale Architectures. ACM; 2012. pp. 226-232

*Real-Time Echo State Network Based on FPGA and Its Applications DOI: http://dx.doi.org/10.5772/intechopen.88820*

[17] Zhang L, Zhang X. MIMO channel estimation and equalization using threelayer neural networks with feedback. Journal of Tsinghua University Natural Science Edition (English Edition). 2007; **12**(6):658-662

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[1] Jaeger H. The "Echo State" Approach to Analysing and Training Recurrent Neural Networks. German National Research Center for Information

*Field Programmable Gate Arrays (FPGAs) II*

[9] Li D, Min H, Wang J. Chaotic time series prediction based on a novel robust echo state network. IEEE Transactions on Neural Networks and Learning Systems. 2012;**23**(5):787-799

Verstraeten D, et al. Compact hardware liquid state machines on FPGA for real-

[10] Schrauwen B, D'Haene M,

time speech recognition. Neural Networks the Official Journal of the International Neural Network Society.

[11] Alomar ML, Canals V, Martinez-Moll V, et al. Low-cost hardware implementation of reservoir computers. In: International Workshop on Power and Timing Modeling, Optimization and Simulation. IEEE;

[12] Jaeger H. Tutorial on Training Recurrent Neural Networks, Covering BPPT, RTRL, EKF and the Echo State Network Approach - First revision.

[13] Sun X, Li T, Li Q, et al. Deep belief echo-state network and its application to time series prediction. Knowledge-Based Systems. 2017;**130**(15):17-29

[14] Yi Y, Liao Y, Wang B, et al. FPGA based spike-time dependent encoder and reservoir design in neuromorphic computing processors. Microprocessors and Microsystems. 2016;**46**(PB):175-183

[15] Jaeger H, Haas H. Harnessing nonlinearity: Predicting chaotic systems

and saving energy in wireless communication. Science. 2004;

[16] Kulkarni MS, Teuscher C.

Memristor-based reservoir computing. In: IEEE/ACM International Symposium on Nanoscale Architectures. ACM; 2012.

**304**(5667):78-80

pp. 226-232

2008;**21**(2–3):511

2014. pp. 1-5

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[2] Dorado-Moreno M, Cornejo-Bueno L, Gutiérrez PA, et al. Robust estimation

[3] Escalona-Morán MA, Soriano MC, Fischer I, et al. Electrocardiogram classification using reservoir computing with logistic regression. IEEE Journal of Biomedical and Health Informatics.

[4] Bezerra SGTA, Andrade CBD, Valença MJS. Using reservoir computing and trend information for short-term streamflow forecasting. In: Artificial Neural Networks and Machine Learning —ICANN 2016. Springer International

[5] Basterrech S, Rubino G. Echo state queuing networks: A combination of reservoir computing and random neural

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[8] Lun SX, Yao XS, Qi HY, et al. A novel model of leaky integrator echo state network for time-series prediction. Neurocomputing. 2015;**159**(1):58-66

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[23] Dorado-Moreno M, Cornejo-Bueno L, Gutiérrez PA, et al. Robust estimation of wind power ramp events with reservoir computing. Renewable Energy. 2017;**111**:428-437

**Chapter 3**

**Abstract**

carrier aggregation

**1. Introduction**

**39**

Flexible Baseband Modulator

5G Communications

*Mário Lopes Ferreira and João Canas Ferreira*

Architecture for Multi-Waveform

The fifth-generation (5G) revolution represents more than a mere performance enhancement of previous generations: it will deeply transform the way humans and/or machines interact, enabling a heterogeneous expansion in the number of use cases and services. Crucial to the realization of this revolution is the design of hardware components characterized by high degrees of flexibility, versatility and resource/power efficiency. This chapter proposes a field-programmable gate array (FPGA)-oriented baseband processing architecture suitable for fast-changing communication environments such as 4G/5G waveform coexistence, noncontiguous carrier aggregation (CA) or centralized cloud radio access network (C-RAN) processing. The proposed architecture supports three 5G waveform candidates and is shown to be upgradable, resource-efficient and cost-effective. Through hardware virtualization, enabled by dynamic partial reconfiguration (DPR), the design space exploration of our architecture exceeds the hardware resources available on the Zynq xc7z020 device. Moreover, dynamic frequency scaling (DFS) enables the runtime adjustment of processing throughput and power reductions by up to 88%.

The combined resource overhead for DPR and DFS is very low, and the reconfiguration latency stays two orders of magnitude below the control plane

baseband processing, OFDM, FBMC, UFMC, waveform coexistence,

for 5G systems will be far more complex than in the current generation.

**Keywords:** FPGA, reconfigurable computing, dynamic partial reconfiguration,

The fifth-generation (5G) cellular network technology will have a tremendous impact on society by optimizing existing telecommunication services and applications and enabling solutions in new application fields, such as transportation, education or medical science. The scope of the anticipated changes is clear from the three main types of 5G use cases and services defined by the International Telecommunication Union (ITU): enhanced mobile broadband (eMBB), ultrareliable and low-latency communications (URLLC) and massive machine-type communications (mMTC) [1]. Therefore, the handling of the physical layer (PHY)

latency requirements proposed for 5G communications.

#### **Chapter 3**

## Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications

*Mário Lopes Ferreira and João Canas Ferreira*

#### **Abstract**

The fifth-generation (5G) revolution represents more than a mere performance enhancement of previous generations: it will deeply transform the way humans and/or machines interact, enabling a heterogeneous expansion in the number of use cases and services. Crucial to the realization of this revolution is the design of hardware components characterized by high degrees of flexibility, versatility and resource/power efficiency. This chapter proposes a field-programmable gate array (FPGA)-oriented baseband processing architecture suitable for fast-changing communication environments such as 4G/5G waveform coexistence, noncontiguous carrier aggregation (CA) or centralized cloud radio access network (C-RAN) processing. The proposed architecture supports three 5G waveform candidates and is shown to be upgradable, resource-efficient and cost-effective. Through hardware virtualization, enabled by dynamic partial reconfiguration (DPR), the design space exploration of our architecture exceeds the hardware resources available on the Zynq xc7z020 device. Moreover, dynamic frequency scaling (DFS) enables the runtime adjustment of processing throughput and power reductions by up to 88%. The combined resource overhead for DPR and DFS is very low, and the reconfiguration latency stays two orders of magnitude below the control plane latency requirements proposed for 5G communications.

**Keywords:** FPGA, reconfigurable computing, dynamic partial reconfiguration, baseband processing, OFDM, FBMC, UFMC, waveform coexistence, carrier aggregation

#### **1. Introduction**

The fifth-generation (5G) cellular network technology will have a tremendous impact on society by optimizing existing telecommunication services and applications and enabling solutions in new application fields, such as transportation, education or medical science. The scope of the anticipated changes is clear from the three main types of 5G use cases and services defined by the International Telecommunication Union (ITU): enhanced mobile broadband (eMBB), ultrareliable and low-latency communications (URLLC) and massive machine-type communications (mMTC) [1]. Therefore, the handling of the physical layer (PHY) for 5G systems will be far more complex than in the current generation.

*Orthogonal frequency-division multiplexing* (OFDM) is the preferred waveform in 4G standards, and the 3GPP Release 15 [2] recently defined it as the multiple access scheme for the 5G New Radio (NR) PHY, especially due its high frequency selectivity, flexibility, efficient hardware implementation by FFT/IFFT modules, and good Multiple-Input Multiple-Output (MIMO) compatibility [3]. However, the spectrum of OFDM symbols presents large side lobes that cause high out-of-band (OOB) emissions. Moreover, the interference between adjacent time-domain symbols is mitigated by adding redundancy to each symbol, which reduces spectral efficiency. Together, these characteristics may make 5G requirements in certain communication scenarios hard to achieve, which has led to the proposal of other waveforms [4]. The most popular ones are *filter bank multicarrier* modulation (FBMC), *Universal Filtered Multicarrier* modulation (UFMC), Filtered OFDM (f-OFDM) and *generalized frequency-division multiplexing* (GFDM). Different waveforms imply different baseband processing operations. Especially for sub-6 GHz spectrum bands, the *coexistence* of multiple numerologies and waveforms and the close interworking between 5G and current systems is likely to occur in the near future [5].

which combines two reconfiguration techniques: (a) DPR to dynamically change the baseband processing mode of operation (e.g. FFT size, modulation scheme and CP length) and (b) DFS to adapt the clock frequency of the digital up-converter and the baseband processor. The design supports two waveforms (OFDM and WCDMA) and several 3G/4G standards and modes of operation. Compared with a static multimode design, the DPR-based design achieves a reduction in the number of used slices, DSP blocks (DSPs) and block RAMs (BRAMs). However, the comparison is not accurate as the static design uses parallel and independent processing chains for each standard, ignoring potential optimization from the reutilization of

*Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications*

CoPR, an automated framework for DPR-based adaptive systems on a Xilinx Zynq device, is described in [12]. An illustrative case study is presented, where a reconfigurable multistandard baseband OFDM transmitter is designed. The design supports three standards (IEEE 802.11, IEEE 802.16 and IEEE 802.22) and contains two reconfigurable partitions (RPs): one to implement the digital modulation scheme and the other for the OFDM processing datapath. The paper only reports reconfiguration time results and does not provide figures for power consumption or

An ARM-FPGA-based platform is also used in [13]. Several processes run on the ARM processor and retrieve communication environment information, which is employed by a configuration controller to reconfigure an OFDM baseband processing modulator. An OFDM transmitter supporting Wi-Fi and WiMAX is implemented on Zynq's programmable logic (PL) with four RPs used for scrambling, interleaving, FEC encoding and IFFT. Results for resource utilization and DPR latency are discussed, together with power consumption measurements. However, the sampling period used for the measurements is of the order of magnitude of the reconfiguration times (milliseconds) and, therefore, not suitable for

The Zynq is also used in [14], which presents a HW/SW codesign for CR systems combining parameter reconfiguration and DPR. Only DPR latency and RP

Pham et al. [15] present a reconfigurable multistandard OFDM transceiver supporting IEEE 802.11, IEEE 802.16 and IEEE 802.22 on a Xilinx Virtex-6 FPGA. The modulator uses a single RP, whereas the demodulator explores a mixture of DPR-based and static multimode modules. The authors put more weight on the whole architecture and only provide data about reconfiguration times and

All works mentioned target 3G/4G standards and waveforms. From a system perspective, they focus primarily on the enhanced flexibility DPR can offer, with less attention paid to the global impact of this technique on the design of the hardware infrastructure. Additionally, no architecture with multiple and independent processors suitable for noncontiguous spectrum aggregation is studied.

This section describes the implementation of pipelined datapaths for three different waveforms (OFDM, FBMC and UFMC) and respective variants. Each variant is defined by the values assigned to the parameters of the design. The possible sets of values are sometimes called "numerologies" in the literature. In this case study, two sets of parameter values for each waveform are considered, as described in the

accurate real-time measurements at the time scale of interest.

**3. Implementation of datapaths for baseband processing**

remainder of this section and summarized in **Tables 1**–**3**.

common modules.

the amount of resources of each RP.

*DOI: http://dx.doi.org/10.5772/intechopen.91297*

resources are reported.

bitstream size.

**41**

The expansion of wireless communication caused by 5G systems and services raises concerns about the inefficient use of the electromagnetic spectrum. In addition, to expand spectrum utilization to frequency bands above 6 GHz, a more efficient spectral utilization of heavily used bands must be achieved. To tackle this issue, future baseband processor designs should support *dynamic spectrum access* (DSA) [6] and *carrier aggregation* (CA) schemes.

In summary, baseband processing infrastructures for 5G systems must be (1) *flexible*, to adapt their operation for different communication setups (i.e. waveforms and their parameterization); (2) *scalable*, to tune performance and capacity according to communication demands; (3) resource and power *efficient*, for costeffectiveness and reduced environmental impact [7]; (4) *forward compatible*, to easily integrate the support for new services and requirements, extending system lifetime. Modern field-programmable gate arrays (FPGAs) represent an implementation platform that favors the design of systems with the characteristics mentioned. The intrinsic FPGA reconfigurability can be enhanced by means of *dynamic partial reconfiguration* (DPR), i.e. by reconfiguring modules of the design without halting the system. The hardware virtualization allowed by DPR enhances system flexibility, feature wealth, upgradability and cost-effectiveness [8]. This chapter discusses how DPR and *dynamic frequency scaling* (DFS) can be combined to produce a dynamically reconfigurable baseband processing architecture for multimode, multi-waveform coexistence and dynamic spectrum aggregation.

After a brief summary of the state of the art in Section 2, the implementation of datapaths for baseband processing of three waveforms (OFDM, FBMC and UFMC) is described in Section 3. The implementation of a dynamically reconfigurable baseband modulator that combines these datapaths is described in Section 4, together with a discussion of the results. Some final remarks are presented in Section 5.

#### **2. Summary of the state of the art**

Application of DPR to baseband processing in wireless communications started with the adoption of small-scale and relatively simple functional elements such as FIR filters, constellation mappers or channel encoders [9, 10]. Possibly the first multi-waveform flexible PHY architecture was proposed by He et al. [11]. It is a software-defined radio (SDR) architecture implemented on a Xilinx Virtex-5 FPGA,

#### *Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications DOI: http://dx.doi.org/10.5772/intechopen.91297*

which combines two reconfiguration techniques: (a) DPR to dynamically change the baseband processing mode of operation (e.g. FFT size, modulation scheme and CP length) and (b) DFS to adapt the clock frequency of the digital up-converter and the baseband processor. The design supports two waveforms (OFDM and WCDMA) and several 3G/4G standards and modes of operation. Compared with a static multimode design, the DPR-based design achieves a reduction in the number of used slices, DSP blocks (DSPs) and block RAMs (BRAMs). However, the comparison is not accurate as the static design uses parallel and independent processing chains for each standard, ignoring potential optimization from the reutilization of common modules.

CoPR, an automated framework for DPR-based adaptive systems on a Xilinx Zynq device, is described in [12]. An illustrative case study is presented, where a reconfigurable multistandard baseband OFDM transmitter is designed. The design supports three standards (IEEE 802.11, IEEE 802.16 and IEEE 802.22) and contains two reconfigurable partitions (RPs): one to implement the digital modulation scheme and the other for the OFDM processing datapath. The paper only reports reconfiguration time results and does not provide figures for power consumption or the amount of resources of each RP.

An ARM-FPGA-based platform is also used in [13]. Several processes run on the ARM processor and retrieve communication environment information, which is employed by a configuration controller to reconfigure an OFDM baseband processing modulator. An OFDM transmitter supporting Wi-Fi and WiMAX is implemented on Zynq's programmable logic (PL) with four RPs used for scrambling, interleaving, FEC encoding and IFFT. Results for resource utilization and DPR latency are discussed, together with power consumption measurements. However, the sampling period used for the measurements is of the order of magnitude of the reconfiguration times (milliseconds) and, therefore, not suitable for accurate real-time measurements at the time scale of interest.

The Zynq is also used in [14], which presents a HW/SW codesign for CR systems combining parameter reconfiguration and DPR. Only DPR latency and RP resources are reported.

Pham et al. [15] present a reconfigurable multistandard OFDM transceiver supporting IEEE 802.11, IEEE 802.16 and IEEE 802.22 on a Xilinx Virtex-6 FPGA. The modulator uses a single RP, whereas the demodulator explores a mixture of DPR-based and static multimode modules. The authors put more weight on the whole architecture and only provide data about reconfiguration times and bitstream size.

All works mentioned target 3G/4G standards and waveforms. From a system perspective, they focus primarily on the enhanced flexibility DPR can offer, with less attention paid to the global impact of this technique on the design of the hardware infrastructure. Additionally, no architecture with multiple and independent processors suitable for noncontiguous spectrum aggregation is studied.

#### **3. Implementation of datapaths for baseband processing**

This section describes the implementation of pipelined datapaths for three different waveforms (OFDM, FBMC and UFMC) and respective variants. Each variant is defined by the values assigned to the parameters of the design. The possible sets of values are sometimes called "numerologies" in the literature. In this case study, two sets of parameter values for each waveform are considered, as described in the remainder of this section and summarized in **Tables 1**–**3**.

*Orthogonal frequency-division multiplexing* (OFDM) is the preferred waveform in 4G standards, and the 3GPP Release 15 [2] recently defined it as the multiple access scheme for the 5G New Radio (NR) PHY, especially due its high frequency selectivity, flexibility, efficient hardware implementation by FFT/IFFT modules, and good Multiple-Input Multiple-Output (MIMO) compatibility [3]. However, the spectrum of OFDM symbols presents large side lobes that cause high out-of-band (OOB) emissions. Moreover, the interference between adjacent time-domain symbols is mitigated by adding redundancy to each symbol, which reduces spectral efficiency. Together, these characteristics may make 5G requirements in certain communication scenarios hard to achieve, which has led to the proposal of other waveforms [4]. The most popular ones are *filter bank multicarrier* modulation (FBMC), *Universal Filtered Multicarrier* modulation (UFMC), Filtered OFDM (f-OFDM) and *generalized frequency-division multiplexing* (GFDM). Different waveforms imply different baseband processing operations. Especially for sub-6 GHz spectrum bands, the *coexistence* of multiple numerologies and waveforms and the close interworking between 5G and current systems is likely to occur in the near future [5].

The expansion of wireless communication caused by 5G systems and services raises concerns about the inefficient use of the electromagnetic spectrum. In addition, to expand spectrum utilization to frequency bands above 6 GHz, a more efficient spectral utilization of heavily used bands must be achieved. To tackle this issue, future baseband processor designs should support *dynamic spectrum access*

In summary, baseband processing infrastructures for 5G systems must be (1) *flexible*, to adapt their operation for different communication setups (i.e. waveforms and their parameterization); (2) *scalable*, to tune performance and capacity according to communication demands; (3) resource and power *efficient*, for costeffectiveness and reduced environmental impact [7]; (4) *forward compatible*, to easily integrate the support for new services and requirements, extending system lifetime. Modern field-programmable gate arrays (FPGAs) represent an implementation platform that favors the design of systems with the characteristics mentioned. The intrinsic FPGA reconfigurability can be enhanced by means of *dynamic partial reconfiguration* (DPR), i.e. by reconfiguring modules of the design without halting the system. The hardware virtualization allowed by DPR enhances system flexibility, feature wealth, upgradability and cost-effectiveness [8]. This chapter discusses how DPR and *dynamic frequency scaling* (DFS) can be combined to produce a dynamically reconfigurable baseband processing architecture for multimode,

After a brief summary of the state of the art in Section 2, the implementation of datapaths for baseband processing of three waveforms (OFDM, FBMC and UFMC) is described in Section 3. The implementation of a dynamically reconfigurable baseband modulator that combines these datapaths is described in Section 4, together with a discussion of the results. Some final remarks are presented in

Application of DPR to baseband processing in wireless communications started with the adoption of small-scale and relatively simple functional elements such as FIR filters, constellation mappers or channel encoders [9, 10]. Possibly the first multi-waveform flexible PHY architecture was proposed by He et al. [11]. It is a software-defined radio (SDR) architecture implemented on a Xilinx Virtex-5 FPGA,

(DSA) [6] and *carrier aggregation* (CA) schemes.

*Field Programmable Gate Arrays (FPGAs) II*

multi-waveform coexistence and dynamic spectrum aggregation.

Section 5.

**40**

**2. Summary of the state of the art**


implemented with an M:1 multiplexer: a log <sup>2</sup>*M*-bit input signal selects a complex value out of the *M* prestored constants that form the constellation. In the implementation used for this work, Gray mapping and average power normalization are

*Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications*

After digital modulation, the *subcarrier mapping* module is responsible for mapping the *A* input active subcarriers to the central bins of an *N*-element array and zeroing the centre bin (the DC null subcarrier). The remaining *N* � *A* � 1 bins correspond to null subcarriers that serve as guard bands. As the IFFT DC bin is at index 0, an IFFT shift operation is performed on the *N*-element array. The resulting vector is then fed to the IFFT core. Here, it is assumed that the *A* active subcarriers include both data and pilot subcarriers and that the higher levels of the communication system provide them in their correct relative locations. The main modules required for *subcarrier mapping* are a double buffer and a control unit. The double buffer is implemented with a dual-port RAM, with each half storing *N* complex samples. This allows for simultaneous reading and writing of consecutive *A*-element arrays without any data conflicts: while one buffer is used for input (writing), the other is used for output (reading). The read/write access to the double buffer is managed by a control unit that receives and correctly maps the data to the correct IFFT input bin. The index mapping scheme implemented by the control unit com-

The IFFT module implements a Cooley-Tukey Mixed-Radix algorithm using a pipelined single-delay feedback architecture as in [16]. The IFFT module has several processing stages which are comprised of shift registers, ROM memories, complex multipliers and arithmetic blocks (called "butterflies"). Information on the internal structures of Radix-22 and Radix-2 butterflies can be found in [17, 18]. Apart from processing elements, the IFFT module also includes blocks for input data reordering and bit-reversed reordering of intermediate results, which are performed with

The IFFT module produces time-domain OFDM symbols. The next module in the datapath is responsible for *cyclic prefix (CP) insertion*. It receives a data array of size *N* (corresponding to a time-domain OFDM symbol) and stores it in memory. Then, the module starts to read and output the last *LCP + W* memory positions. The cyclic prefix extension by *W* samples allows for the following weighted overlap and add (*WOLA*) operation. After outputting the last *LCP + W* memory positions, the CP insertion unit continues by reading and outputting the complete OFDM symbol from the beginning. Thus, the output of this module is an extended ODFM symbol with *N* þ *LCP* þ *W* complex samples. Its main hardware elements are an *N*-elements dual-port RAM and a unit for controlling write/read memory operations. The final module performs the *WOLA* operation. It can be divided into two stages: first, OFDM symbols are multiplied by a window (*windowing*), and then the symbol's tail is overlapped and added with next symbol's head (*overlap-and-add*). The windowing operation is implemented using two multipliers (to handle the real and imaginary parts) and a ROM memory with prestored non-unitary raised-cosine window coefficients. In turn, the overlap-and-add operation is implemented with a finite-state machine (FSM) and arrays of registers to temporarily store each sym-

The conceptual structure of the FBMC baseband modulator implemented for this work is shown in **Figure 2**. The *OQAM mapper* consists of two stages: first, the incoming data is QAM-modulated; then, the resulting in-phase and quadrature components are decoupled and alternately transmitted on successive subcarriers

considered in the definition of the constellation point values.

*DOI: http://dx.doi.org/10.5772/intechopen.91297*

bines subcarrier mapping and IFFT shifting.

RAM-based double buffers.

bol's head and tail.

**43**

**3.2 Baseband datapath for FBMC**

**Table 1.**

*Parameter values supported by the OFDM datapath.*


#### **Table 2.**

*Parameter values supported by the FBMC datapath.*


**Table 3.**

*Parameter values supported by the UFMC datapath.*

#### **3.1 Baseband datapath for OFDM**

OFDM is the main reference among multicarrier modulation waveforms; it is used in a wide range of standards such as DSL, DVB-T, DVB-C, Wi-Fi (IEEE 802.11), WiMAX (IEEE 802.16) and 3GPP LTE. The conceptual structure of an OFDM modulator is illustrated in **Figure 1**.

With exception of the inverse FFT (IFFT), the tasks required for a modulator involve only simple arithmetic, data selection and reordering. The first module is the QAM mapper. For a general *M*-ary QAM case, the module is simply

**Figure 1.** *OFDM baseband modulation. GB, zero-valued guard bands.*

#### *Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications DOI: http://dx.doi.org/10.5772/intechopen.91297*

implemented with an M:1 multiplexer: a log <sup>2</sup>*M*-bit input signal selects a complex value out of the *M* prestored constants that form the constellation. In the implementation used for this work, Gray mapping and average power normalization are considered in the definition of the constellation point values.

After digital modulation, the *subcarrier mapping* module is responsible for mapping the *A* input active subcarriers to the central bins of an *N*-element array and zeroing the centre bin (the DC null subcarrier). The remaining *N* � *A* � 1 bins correspond to null subcarriers that serve as guard bands. As the IFFT DC bin is at index 0, an IFFT shift operation is performed on the *N*-element array. The resulting vector is then fed to the IFFT core. Here, it is assumed that the *A* active subcarriers include both data and pilot subcarriers and that the higher levels of the communication system provide them in their correct relative locations. The main modules required for *subcarrier mapping* are a double buffer and a control unit. The double buffer is implemented with a dual-port RAM, with each half storing *N* complex samples. This allows for simultaneous reading and writing of consecutive *A*-element arrays without any data conflicts: while one buffer is used for input (writing), the other is used for output (reading). The read/write access to the double buffer is managed by a control unit that receives and correctly maps the data to the correct IFFT input bin. The index mapping scheme implemented by the control unit combines subcarrier mapping and IFFT shifting.

The IFFT module implements a Cooley-Tukey Mixed-Radix algorithm using a pipelined single-delay feedback architecture as in [16]. The IFFT module has several processing stages which are comprised of shift registers, ROM memories, complex multipliers and arithmetic blocks (called "butterflies"). Information on the internal structures of Radix-22 and Radix-2 butterflies can be found in [17, 18]. Apart from processing elements, the IFFT module also includes blocks for input data reordering and bit-reversed reordering of intermediate results, which are performed with RAM-based double buffers.

The IFFT module produces time-domain OFDM symbols. The next module in the datapath is responsible for *cyclic prefix (CP) insertion*. It receives a data array of size *N* (corresponding to a time-domain OFDM symbol) and stores it in memory. Then, the module starts to read and output the last *LCP + W* memory positions. The cyclic prefix extension by *W* samples allows for the following weighted overlap and add (*WOLA*) operation. After outputting the last *LCP + W* memory positions, the CP insertion unit continues by reading and outputting the complete OFDM symbol from the beginning. Thus, the output of this module is an extended ODFM symbol with *N* þ *LCP* þ *W* complex samples. Its main hardware elements are an *N*-elements dual-port RAM and a unit for controlling write/read memory operations.

The final module performs the *WOLA* operation. It can be divided into two stages: first, OFDM symbols are multiplied by a window (*windowing*), and then the symbol's tail is overlapped and added with next symbol's head (*overlap-and-add*). The windowing operation is implemented using two multipliers (to handle the real and imaginary parts) and a ROM memory with prestored non-unitary raised-cosine window coefficients. In turn, the overlap-and-add operation is implemented with a finite-state machine (FSM) and arrays of registers to temporarily store each symbol's head and tail.

#### **3.2 Baseband datapath for FBMC**

The conceptual structure of the FBMC baseband modulator implemented for this work is shown in **Figure 2**. The *OQAM mapper* consists of two stages: first, the incoming data is QAM-modulated; then, the resulting in-phase and quadrature components are decoupled and alternately transmitted on successive subcarriers

**3.1 Baseband datapath for OFDM**

*Parameter values supported by the UFMC datapath.*

*Parameter values supported by the OFDM datapath.*

*Field Programmable Gate Arrays (FPGAs) II*

*Parameter values supported by the FBMC datapath.*

**Table 1.**

**Table 2.**

**Table 3.**

**Figure 1.**

**42**

OFDM modulator is illustrated in **Figure 1**.

*OFDM baseband modulation. GB, zero-valued guard bands.*

OFDM is the main reference among multicarrier modulation waveforms; it is used in a wide range of standards such as DSL, DVB-T, DVB-C, Wi-Fi (IEEE 802.11), WiMAX (IEEE 802.16) and 3GPP LTE. The conceptual structure of an

**Parameter Mode 1 Mode 2** # subcarriers, *N* (IFFT size) 512 1024 length of cyclic prefix, *LCP* 40 (1st slot symbol) 80 (1st slot symbol)
