**5.5 Charge sense amplifier**

The schematic of the CSA is shown in the **Figure 16(a)**. The schematic of the operational amplifier (OPAMP) used in the CSA is shown in **Figure 16(b)**. The OPAMP comprises a differential pair and a load that is driven by a two-stage buffer, initiated by a start-up circuit. The driver consists of two diode-connected load inverters as input and output stages. The output stage is driven by a start-up circuit to initialize the operation and provide ~1 loop gain positive feedback bias to the n-type load of the differential amplifier such that gate voltage follows source voltage. A buffer is also included at the output nodes A and B to increase the speed of the amplifier.

The experimental results of open-loop experiments of the OPAMP are shown in **Figure 17** for dual-gate self-aligned IGZO TFTs of minimum channel length of L = 5 μm. The maximum gain for the 5 μm design is 43.2 dB with a phase margin of 52°. Both parameters are critical for stable closed-loop operation of an OPAMP. The

**135**

**Figure 17.**

The footprint of the CSA is 0.28 mm2

**5.6 Analog to digital converter**

be decreased to 0.07 mm2

**Figure 16.**

*TFTs used in the CSA in (a).*

*AMOLED Displays with In-Pixel Photodetector DOI: http://dx.doi.org/10.5772/intechopen.93016*

obtained bandwidth (BW) is 1.4 kHz, and gain-bandwidth reaches 205 kHz. These specs are compared to other publications in the state-of-the-art **Table 1** using TFTs.

*Experimental bode plots of the OPAMP using dual-gate self-aligned IGZO technology for L = 5 μm.*

*Schematic of (a) charge sense amplifier (CSA) and (b) the OPAMP schematic using dual-gate self-aligned* 

a bezel width of 5.5 mm (L = 5 μm) and 1.3 mm (L = 3 μm) [27] for a 50 μm pixel size.

The successive approximation C-2C architecture is selected as ADC architecture, due to the low power dissipation and the 0.1% uniformity of metal-insulator-metal capacitors across large-area thin-film wafers. The schematic of the ADC is shown in **Figure 18**. The comparator is the most critical building block of the ADC for speed

with the capacitors. The footprint of the CSA can

if 3 μm design is implemented. These footprints will result in

**Figure 15.** *Microphotos of the (a) ADC and (b) L = 3 μm CSA on flexible substrate.*

*AMOLED Displays with In-Pixel Photodetector DOI: http://dx.doi.org/10.5772/intechopen.93016*

#### **Figure 16.**

*Liquid Crystals and Display Technology*

**134**

**Figure 15.**

*Microphotos of the (a) ADC and (b) L = 3 μm CSA on flexible substrate.*

the ITZO dual-gate TFT exhibits a median of 250.4 μA. Although the ION of the ITZO TFT is 5 times larger, the normalized spread of ION to the median over the wafer is double (15.4% for ITZO and 8.8% for IGZO). Threshold voltage is also extracted from the same measurements, yielding 1.16 V (and σVt = 242 mV) for ITZO and 1.77 V (and σVt = 94 mV) for IGZO TFTs. The 480/20 TFT is the largest footprint TFT used in the implemented designs. In **Figure 15**, microphotos of the

*(a) Cross section of dual-gate self-aligned metal-oxide technology on flexible polyimide substrate and (b) extracted on-current (ION) from experimental data of 480/20 (μm/μm) dual-gate self-aligned ITZO (red)* 

The schematic of the CSA is shown in the **Figure 16(a)**. The schematic of the operational amplifier (OPAMP) used in the CSA is shown in **Figure 16(b)**. The OPAMP comprises a differential pair and a load that is driven by a two-stage buffer, initiated by a start-up circuit. The driver consists of two diode-connected load inverters as input and output stages. The output stage is driven by a start-up circuit to initialize the operation and provide ~1 loop gain positive feedback bias to the n-type load of the differential amplifier such that gate voltage follows source voltage. A buffer is also included at the output nodes A and B to increase the speed of the amplifier. The experimental results of open-loop experiments of the OPAMP are shown in **Figure 17** for dual-gate self-aligned IGZO TFTs of minimum channel length of L = 5 μm. The maximum gain for the 5 μm design is 43.2 dB with a phase margin of 52°. Both parameters are critical for stable closed-loop operation of an OPAMP. The

(a) ADC and (b) the L = 3 μm CSA are shown.

**5.5 Charge sense amplifier**

**Figure 14.**

*and IGZO (orange) TFTs.*

*Schematic of (a) charge sense amplifier (CSA) and (b) the OPAMP schematic using dual-gate self-aligned TFTs used in the CSA in (a).*

**Figure 17.** *Experimental bode plots of the OPAMP using dual-gate self-aligned IGZO technology for L = 5 μm.*

obtained bandwidth (BW) is 1.4 kHz, and gain-bandwidth reaches 205 kHz. These specs are compared to other publications in the state-of-the-art **Table 1** using TFTs. The footprint of the CSA is 0.28 mm2 with the capacitors. The footprint of the CSA can be decreased to 0.07 mm2 if 3 μm design is implemented. These footprints will result in a bezel width of 5.5 mm (L = 5 μm) and 1.3 mm (L = 3 μm) [27] for a 50 μm pixel size.

#### **5.6 Analog to digital converter**

The successive approximation C-2C architecture is selected as ADC architecture, due to the low power dissipation and the 0.1% uniformity of metal-insulator-metal capacitors across large-area thin-film wafers. The schematic of the ADC is shown in **Figure 18**. The comparator is the most critical building block of the ADC for speed

#### *Liquid Crystals and Display Technology*


#### **Table 1.**

*In-Ga-Zn-O-TFT differential amplifier comparison.*

#### **Figure 18.**

*The implemented SADG TFT ADC block diagram driven with offset compensation.*

and accuracy. To improve the accuracy of the comparator, open-loop offset cancelation [28] is used. The response of a L = 5 μm dual-gate self-aligned TFT-based comparator at 10 kHz for two inputs ΔVin = 0 and 10 mV is shown in **Figure 19**. The offset of the comparator is minimized to less than 10 mV using open-loop cancelation, even though the Vt variation of the TFTs is one order larger.

The experimental results of the reconstructed samples from a sinusoidal analog wave applied at the input of the IGZO ADC are shown in **Figure 20(a)**. The IGZO ADC achieves 6-bit resolution at a sampling speed of 133 S/s at 15 V power supply using a L = 20 μm comparator. The clock speed of the IGZO ADC is at 2 kHz matching the bandwidth of the comparator, and 15 clocks are required to complete the conversion. Two options are available to increase the sampling speed of the ADC as set by the specification for 1–2 fps fingerprint readout: channel length downscaling and/or change of TFT technology or change of ADC architecture to flash but then for 6-bit the area might increase dramatically due to the multiple resistors needed and 64 comparators.

The minimum length of the TFTs of the measured ADC is L = 20 μm. The length of the TFT of the comparator of the ADC defines the speed of the circuit.

**137**

**Figure 20.**

**Figure 19.**

*10 kHz.*

In **Figure 19** the response of the L = 5 μm comparator is shown validating 10 kHz operation, 5 times faster compared to the 20 μm comparator used in the ADC. This

*(a) The applied analog input of 2.061 Hz sinewave signal to the ADC and the reconstructed output points from the digital output of the ADC at a clock frequency of 2 kHz for IGZO and (b) the applied analog input of* 

*Measured comparator output with auto-zero offset cancelation for designs using TFTs of minimum L = 5 μm at* 

indicates that 5 μm comparator can increase the sampling speed by 5 times. Another option to enable a larger increase of the ADC speed is to introduce ITZO TFT for the ADC. ITZO TFT exhibits 5 times larger ION which leads to faster

*15.625 Hz sinewave to the 15 kHz clocked ITZO ADC and the reconstructed output.*

*AMOLED Displays with In-Pixel Photodetector DOI: http://dx.doi.org/10.5772/intechopen.93016*

#### **Figure 19.**

*Liquid Crystals and Display Technology*

*In-Ga-Zn-O-TFT differential amplifier comparison.*

pm (o

*\* Estimated.*

**Table 1.**

Area (mm2

**136**

and 64 comparators.

**Figure 18.**

*The implemented SADG TFT ADC block diagram driven with offset compensation.*

ation, even though the Vt variation of the TFTs is one order larger.

and accuracy. To improve the accuracy of the comparator, open-loop offset cancelation [28] is used. The response of a L = 5 μm dual-gate self-aligned TFT-based comparator at 10 kHz for two inputs ΔVin = 0 and 10 mV is shown in **Figure 19**. The offset of the comparator is minimized to less than 10 mV using open-loop cancel-

The experimental results of the reconstructed samples from a sinusoidal analog wave applied at the input of the IGZO ADC are shown in **Figure 20(a)**. The IGZO ADC achieves 6-bit resolution at a sampling speed of 133 S/s at 15 V power supply using a L = 20 μm comparator. The clock speed of the IGZO ADC is at 2 kHz matching the bandwidth of the comparator, and 15 clocks are required to complete the conversion. Two options are available to increase the sampling speed of the ADC as set by the specification for 1–2 fps fingerprint readout: channel length downscaling and/or change of TFT technology or change of ADC architecture to flash but then for 6-bit the area might increase dramatically due to the multiple resistors needed

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The minimum length of the TFTs of the measured ADC is L = 20 μm. The length of the TFT of the comparator of the ADC defines the speed of the circuit.

*Measured comparator output with auto-zero offset cancelation for designs using TFTs of minimum L = 5 μm at 10 kHz.*

#### **Figure 20.**

*(a) The applied analog input of 2.061 Hz sinewave signal to the ADC and the reconstructed output points from the digital output of the ADC at a clock frequency of 2 kHz for IGZO and (b) the applied analog input of 15.625 Hz sinewave to the 15 kHz clocked ITZO ADC and the reconstructed output.*

In **Figure 19** the response of the L = 5 μm comparator is shown validating 10 kHz operation, 5 times faster compared to the 20 μm comparator used in the ADC. This indicates that 5 μm comparator can increase the sampling speed by 5 times.

Another option to enable a larger increase of the ADC speed is to introduce ITZO TFT for the ADC. ITZO TFT exhibits 5 times larger ION which leads to faster responses [**Figure 20(b)**]. The ITZO ADC achieves a similar bit resolution of the applied sinusoidal wave at 1 kS/s sampling speed and at 10 V supply voltage. Combining both ITZO and downscaling of the length of the TFTs of the comparator will lead to sampling speeds above 4 kS/s as required for the in-panel readout system of 1 fps. The power dissipation of the ITZO ADC is at 550 μW at 10 V power supply and at 110 μW at 15 V power supply for the IGZO implementation.

In conclusion, TFT-based in-panel analog circuits for 1 fps readout of a fingerprint or palmprints array is presented in this paragraph. The circuit blocks can be integrated side-by-side to the flat panel display with integrated sensor array. Two analog blocks are discussed, being an analog to digital converter and charge sense amplifier. ADCs and CSA downscaling to 5 μm including a 500% ION boost of the ITZO TFTs enable the 4 kS/s operation specifications for the in-panel readout circuits. The use of complementary technologies such as LTPS or LTPO would result an increased performance for important parameters such as the gain-bandwidth and the resolution and speed of the ADC. This will enable a better optimized system for this application.
