**1. Introduction**

Nowadays, with the tremendous increase of distributed energy generation (DEG), the concept of power quality (PQ) has become a growing concern for grid operators around the world [1–4]. Many research teams working on this topic are developing small or large-scale DEG laboratories (**Figure 1**) [3–9] as well as algorithms for critical situations is the grid emulator. This grid emulator is also used to confirm the compliance with standards and different grid codes [10–13].

This chapter covers one of the functionalities of the grid emulator, which is the line impedance emulation. Indeed, line impedance deviation can be caused by several circumstances, such as, a remote grid fault, or a connection disconnection of a large load in the distribution network [14].

**Figure 1.** *Example of a microgrid including line impedance emulators.*

The line impedance variation is able to considerably affect reactive power sharing between parallel loads [15, 16], and it can also induce operation instability in case of standalone microgrid [17, 19]. In addition, line impedance value has an influence on the quality of voltage and line current in the point of common coupling of the microgrid [19]. In another hand, tests introducing line impedance variation are used for the compliance with many relevant standards especially those dealing with anti-islanding.

This chapter explains in details the steps of the line impedance emulator design based on power converters. Regarding line impedance emulation algorithm, reference voltage values are deduced in view of the phase shift with the input AC grid voltage, according to the equipment under test (EUT) active and reactive power. Presented emulator guarantee flexible tests with decoupled variation range of impedance component.

This chapter first outlines modeling of line impedance emulator, followed by a description of the control methodology for the overall, simulation results and experimental validation are then developed.

## **2. Line impedance emulator presentation**

The line impedance emulator is installed between the grid and the EUT and used for the emulation of variable line impedance. The structure of the studied line impedance emulator system is shown in **Figure 2**. It incorporates two power converters joined by dc-link capacitor: an EUT side converter (EsC) and a grid side converter (GsC). The GsC and the EsC are AC/DC and DC/AC converters, respectively. To mitigate switching harmonics, an LCL filter is employed at the output of the EsC. The EsC control aims to maintain the voltage through the LCL filter capacitor *Vc*(*abc*) equal to the programmed references. The GsC has the intention of regulating the system power factor (PF) and the voltage at the DC bus *Vdc*. As presented in **Figure 2**, the line impedance emulator output *Vout*(*abc*) is equal to *Vc*(*abc*), while its output *Vin*(*abc*) is considered comparable to the grid voltage *Vg*(*abc*).

voltages and currents. The next step is to control of the GsC. The objective of this control is voltage at the DC bus regulation. In parallel with these steps, the impedance emulation algorithm provides the capacitor voltage references *Vc*(*a,b,c*)

*Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation*

according to programmed impedance. Once *Vdc* is equal to its reference and the

**Figure 4** summarizes the different steps of the line impedance emulator design. As mentioned, the first step consists in modeling the two power converters of the line impedance emulator giving the system equations and transfer functions. After that, the operator selects the appropriate control converters control in terms of dynamic response, THD value, steady state error and sensitivity to perturbation and parametric variation. In this chapter, the control of the line impedance emulator converters employed resonant controllers and PI regulators. This choice is due to

control of the EsC. The desired line impedance is consequently achieved.

*\** are generated, the operator proceeds to the

capacitor voltage references *Vc*(*a,b,c*)

*Line impedance emulator process flowchart.*

**Figure 2.**

**Figure 3.**

**133**

*Power converter-based three-phase line impedance emulator.*

*DOI: http://dx.doi.org/10.5772/intechopen.90081*

*\**

The flowchart of the line impedance emulator process is given by **Figure 3**. The first step of this flowchart consists in initializing the different functions and the microcontroller peripherals such as the ADC, Timers and the General Purpose Input/Output (GPIO) as well as the analog-to-digital conversion of the measured

*Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation DOI: http://dx.doi.org/10.5772/intechopen.90081*

#### **Figure 2.**

The line impedance variation is able to considerably affect reactive power sharing between parallel loads [15, 16], and it can also induce operation instability in case of standalone microgrid [17, 19]. In addition, line impedance value has an influence on the quality of voltage and line current in the point of common coupling of the microgrid [19]. In another hand, tests introducing line impedance variation are used for the compliance with many relevant standards especially those dealing

This chapter explains in details the steps of the line impedance emulator design based on power converters. Regarding line impedance emulation algorithm, reference voltage values are deduced in view of the phase shift with the input AC grid voltage, according to the equipment under test (EUT) active and reactive power. Presented emulator guarantee flexible tests with decoupled variation range of

This chapter first outlines modeling of line impedance emulator, followed by a

The line impedance emulator is installed between the grid and the EUT and used

description of the control methodology for the overall, simulation results and

for the emulation of variable line impedance. The structure of the studied line impedance emulator system is shown in **Figure 2**. It incorporates two power converters joined by dc-link capacitor: an EUT side converter (EsC) and a grid side converter (GsC). The GsC and the EsC are AC/DC and DC/AC converters, respectively. To mitigate switching harmonics, an LCL filter is employed at the output of the EsC. The EsC control aims to maintain the voltage through the LCL filter capacitor *Vc*(*abc*) equal to the programmed references. The GsC has the intention of regulating the system power factor (PF) and the voltage at the DC bus *Vdc*. As presented in **Figure 2**, the line impedance emulator output *Vout*(*abc*) is equal to *Vc*(*abc*), while its output *Vin*(*abc*) is considered comparable to the grid voltage *Vg*(*abc*). The flowchart of the line impedance emulator process is given by **Figure 3**. The first step of this flowchart consists in initializing the different functions and the microcontroller peripherals such as the ADC, Timers and the General Purpose Input/Output (GPIO) as well as the analog-to-digital conversion of the measured

with anti-islanding.

**Figure 1.**

impedance component.

**132**

experimental validation are then developed.

*Example of a microgrid including line impedance emulators.*

*Numerical Modeling and Computer Simulation*

**2. Line impedance emulator presentation**

*Power converter-based three-phase line impedance emulator.*

#### **Figure 3.**

*Line impedance emulator process flowchart.*

voltages and currents. The next step is to control of the GsC. The objective of this control is voltage at the DC bus regulation. In parallel with these steps, the impedance emulation algorithm provides the capacitor voltage references *Vc*(*a,b,c*) *\** according to programmed impedance. Once *Vdc* is equal to its reference and the capacitor voltage references *Vc*(*a,b,c*) *\** are generated, the operator proceeds to the control of the EsC. The desired line impedance is consequently achieved.

**Figure 4** summarizes the different steps of the line impedance emulator design. As mentioned, the first step consists in modeling the two power converters of the line impedance emulator giving the system equations and transfer functions. After that, the operator selects the appropriate control converters control in terms of dynamic response, THD value, steady state error and sensitivity to perturbation and parametric variation. In this chapter, the control of the line impedance emulator converters employed resonant controllers and PI regulators. This choice is due to

**Figure 4.** *Methodology of the design of a line impedance emulator.*

their simple use (tuning parameters and implementation), while ensuring simultaneously acceptable dynamic response, THD value and steady state error. Then, based on the obtained system transfer functions, the control parameters are deduced. After that, the operator should select the appropriate line impedance emulator algorithm. In this chapter, two impedance emulator algorithms will be presented. The next step of the design methodology consists in simulating the whole system including the power converters, the control strategy and the line impedance emulation algorithm. When the simulation results verify the proper system operation, the control will be implemented on a digital board. The last step of the design methodology consists in the experimental validation of the line impedance emulator.
