**Figure 7.**

their simple use (tuning parameters and implementation), while ensuring simultaneously acceptable dynamic response, THD value and steady state error. Then, based on the obtained system transfer functions, the control parameters are deduced. After that, the operator should select the appropriate line impedance emulator algorithm. In this chapter, two impedance emulator algorithms will be presented. The next step of the design methodology consists in simulating the whole system including the power converters, the control strategy and the line impedance emulation algorithm. When the simulation results verify the proper system operation, the control will be implemented on a digital board. The last step of the design methodology consists in

The GsC power circuit single phase representation is depicted on **Figure 5**, where *Lg* denotes the grid impedance. According to this figure, the GsC electric

*Ui* ¼ *Vg* � *Lg*

The EsC power circuit single phase representation is given by **Figure 6**. Based on this Figure, the equations related to the EsC are given by Eq. (2), Eq. (3), Eq. (4) and Eq. (5). The obtained single phase simplified block diagram of the LCL-EsC is

*dig*

*dt* (1)

the experimental validation of the line impedance emulator.

equation in the *abc* reference frame is given by Eq. (1).

**3. Line impedance emulator modeling**

*Methodology of the design of a line impedance emulator.*

*Numerical Modeling and Computer Simulation*

depicted on **Figure 7**.

**Figure 5.** *GsC power circuit.*

**134**

**Figure 4.**

*LCL-EsC simplified block diagram.*

$$i\_1 = \frac{V\_i - V\_c}{sL\_1} \tag{2}$$

$$
\dot{\imath}\_1 = \dot{\imath}\_2 + \dot{\imath}\_c \tag{3}
$$

$$\mathbf{V}\_c = \frac{\dot{\mathbf{i}}\_c}{s\mathbf{C}\_f} \tag{4}$$

$$i\_2 = \frac{V\_c - V\_E}{sL\_2} \tag{5}$$
