*4.2.2 Tuning of the gain of the current i1*

The simplified internal current regulation loop block diagram is given by **Figure 13**.

Hence, the transfer function of the closed-loop system *Ti*1(*s*) is given by Eq. (23).

$$T\_{i1}(s) = \frac{i\_1(s)}{i\_1^\*(s)} = \frac{1}{\frac{L}{G}s + 1} = \frac{1}{1 + \tau\_c s} \quad \text{where} \quad \tau\_c = \frac{L\_1}{G} \tag{23}$$

*G* is chosen so that the real part of the inverse of the closed-loop time constant (1/*τc*) is greater than the stability margin chosen for the synthesis of the voltage external loop in order to ensure that the internal loop is faster than the external one.

## **5. Line impedance emulation algorithms**

In this section, two methods of the line impedance emulator algorithm synthesis are presented: the trigonometric functions-based algorithm and the voltage drop-based algorithm.

#### **5.1 Trigonometric functions-based algorithm**

The impedance emulation conception is based on the phasor diagram depicted on **Figure 14** According to this Figure, the apparent power *S* is expressed as in Eq. (24).

$$\mathcal{S} = V\_{\mathcal{S}} I^\* = V\_{\mathcal{S}} \left( \frac{V\_{\mathcal{S}} - V\_c}{Z} \right)^\* = \frac{V\_{\mathcal{S}}}{Z} \mathcal{e}^{j\theta} - \frac{V\_{\mathcal{S}} V\_c}{Z} \mathcal{e}^{j(\theta + \delta)} \tag{24}$$

According to **Figure 14**, the reactive power *Q* and active power *P* are given by Eqs. (25) and (26), respectively. These equations allow the deduction of tanδ and the voltage magnitude *Vout* given, respectively, by Eqs. (27) and (28). On the other hand, the *Q* and *P* can be also written as a function of *αβ* output current and voltage components as shown in Eqs. (29) and (30), respectively.

$$Q = \frac{V\_{\text{g}}}{R^2 + X^2} \left[ -RV\_c \sin \delta + X \left( V\_{\text{g}} - V\_c \cos \delta \right) \right] \tag{25}$$

$$P = \frac{V\_g}{R^2 + X^2} \left[ R \left( V\_g - V\_c \cos \delta \right) + X V\_c \sin \delta \right] \tag{26}$$

$$
tan\delta = \frac{PX - QR}{V\_g^2 - (PX + QR)}\tag{27}$$

$$V\_c = \frac{PX - QR}{V\_\mathcal{g}\sin\delta} \tag{28}$$

$$Q = \frac{3}{2} \left( V\_{c\beta} i\_{2a} + V\_{ca} i\_{2\beta} \right) \tag{29}$$

$$P = \frac{\mathfrak{Z}}{2} \left( V\_{ca} i\_{2a} + V\_{c\beta} i\_{2\beta} \right) \tag{30}$$

**6. Simulation and discussion**

*Reference voltage according to fixed line impedance.*

*Voltage drop line impedance emulator principle.*

*Line impedance emulator algorithm-based trigonometric functions.*

*DOI: http://dx.doi.org/10.5772/intechopen.90081*

impedances.

**141**

**Figure 15.**

**Figure 16.**

**Figure 17.**

Simulation tests were performed under PSIM software. The proposed control was applied to a 20kVA line impedance emulator. **Table 1** gives the line impedance emulator parameters. In **Figure 18** is presented the *Vdc* response to a step reference of 100 V. Based on this result, the steady state error of the *Vdc* voltage becomes null in the steady state, which prove that this voltage is well regulated. **Figure 19** shows that the voltage *Vc*(*abc*) is well regulated in both transient and steady state operation even reference magnitude change at 0.9 s. To show the voltage drop-based line impedance emulation algorithm performances, a control scenario is presented in **Figure 20**. This scenario consists in imposing in the interval [0, 1 s] equivalent real impedance in series with *L*<sup>2</sup> and in the interval [1 s, 1.5 s] the line impedance emulator is activated. **Figure 21** shows results for a line impedance Z characterized by *X* = 1.5 Ω and *R* = 1 Ω in case of real and emulated impedance. As shown in this

*Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation*

figure, the same current value is generated for real and programmed line

**Figure 15** shows the trigonometric-based line impedance emulation algorithm. The first step consists in measuring the grid voltage *Vg(a,b,c)* and computing its RMS value. From the obtained value, we compute the phase shifting *δ* relatively to the grid voltage. After that, the emulated impedance is computed based on the previous equations.

#### **5.2 Voltage drop-based algorithm**

This algorithm is based on a voltage drop *Vv* that matches with the emulated line impedance Z as shown in **Figure 16** This voltage is a function of programmed inductance and resistance variations as presented in Eq. (31). The voltage dropbased line impedance emulator algorithm is presented in **Figure 17**.

$$V\_v = Z\dot{\mathbf{z}}\_2 = (\mathbf{R} + j\mathbf{X})\dot{\mathbf{z}}\_2$$

**Figure 14.** *Line impedance and phasor diagram.*

*Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation DOI: http://dx.doi.org/10.5772/intechopen.90081*

#### **Figure 15.**

**5.1 Trigonometric functions-based algorithm**

*Numerical Modeling and Computer Simulation*

*<sup>S</sup>* <sup>¼</sup> *Vg <sup>I</sup>* <sup>∗</sup> <sup>¼</sup> *Vg*

*<sup>Q</sup>* <sup>¼</sup> *Vg*

*<sup>P</sup>* <sup>¼</sup> *Vg*

**5.2 Voltage drop-based algorithm**

**Figure 14.**

**140**

*Line impedance and phasor diagram.*

components as shown in Eqs. (29) and (30), respectively.

Eq. (24).

The impedance emulation conception is based on the phasor diagram depicted on **Figure 14** According to this Figure, the apparent power *S* is expressed as in

According to **Figure 14**, the reactive power *Q* and active power *P* are given by Eqs. (25) and (26), respectively. These equations allow the deduction of tanδ and the voltage magnitude *Vout* given, respectively, by Eqs. (27) and (28). On the other hand, the *Q* and *P* can be also written as a function of *αβ* output current and voltage

> *tan<sup>δ</sup>* <sup>¼</sup> *PX* � *QR V*2

*<sup>Q</sup>* <sup>¼</sup> <sup>3</sup> 2

*<sup>P</sup>* <sup>¼</sup> <sup>3</sup>

*Vc* <sup>¼</sup> *PX* � *QR*

*Vcβi*2*<sup>α</sup>* þ *Vcαi*2*<sup>β</sup>*

<sup>2</sup> *Vcαi*2*<sup>α</sup>* <sup>þ</sup> *Vcβi*2*<sup>β</sup>*

**Figure 15** shows the trigonometric-based line impedance emulation algorithm. The first step consists in measuring the grid voltage *Vg(a,b,c)* and computing its RMS value. From the obtained value, we compute the phase shifting *δ* relatively to the grid voltage. After that, the emulated impedance is computed based on the previous equations.

This algorithm is based on a voltage drop *Vv* that matches with the emulated line

*Vv* ¼ *Zi*<sup>2</sup> ¼ ð Þ *R* þ *jX i*<sup>2</sup>

impedance Z as shown in **Figure 16** This voltage is a function of programmed inductance and resistance variations as presented in Eq. (31). The voltage drop-

based line impedance emulator algorithm is presented in **Figure 17**.

<sup>¼</sup> *Vg* 2 *Z e*

*<sup>j</sup><sup>θ</sup>* � *VgVc <sup>Z</sup> <sup>e</sup>*

*<sup>R</sup>*<sup>2</sup> <sup>þ</sup> *<sup>X</sup>*<sup>2</sup> �*RVc* sin *<sup>δ</sup>* <sup>þ</sup> *X Vg* � *Vc* cos *<sup>δ</sup>* (25)

*<sup>R</sup>*<sup>2</sup> <sup>þ</sup> *<sup>X</sup>*<sup>2</sup> *R Vg* � *Vc* cos *<sup>δ</sup>* <sup>þ</sup> *XVc* sin *<sup>δ</sup>* (26)

*<sup>g</sup>* � ð Þ *PX* <sup>þ</sup> *QR* (27)

*Vg* sin *<sup>δ</sup>* (28)

(29)

(30)

*<sup>j</sup>*ð Þ *<sup>θ</sup>*þ*<sup>δ</sup>* (24)

*Vg* � *Vc Z* <sup>∗</sup>

*Line impedance emulator algorithm-based trigonometric functions.*

**Figure 16.** *Voltage drop line impedance emulator principle.*

**Figure 17.**

*Reference voltage according to fixed line impedance.*

## **6. Simulation and discussion**

Simulation tests were performed under PSIM software. The proposed control was applied to a 20kVA line impedance emulator. **Table 1** gives the line impedance emulator parameters. In **Figure 18** is presented the *Vdc* response to a step reference of 100 V. Based on this result, the steady state error of the *Vdc* voltage becomes null in the steady state, which prove that this voltage is well regulated. **Figure 19** shows that the voltage *Vc*(*abc*) is well regulated in both transient and steady state operation even reference magnitude change at 0.9 s. To show the voltage drop-based line impedance emulation algorithm performances, a control scenario is presented in **Figure 20**. This scenario consists in imposing in the interval [0, 1 s] equivalent real impedance in series with *L*<sup>2</sup> and in the interval [1 s, 1.5 s] the line impedance emulator is activated. **Figure 21** shows results for a line impedance Z characterized by *X* = 1.5 Ω and *R* = 1 Ω in case of real and emulated impedance. As shown in this figure, the same current value is generated for real and programmed line impedances.

