**3. Integration of porous low-k dielectric materials in Cu interconnects**

As Cu metallization replaced Al metallization in BEOL interconnects, the fabrication process was also switched to damascene approach from metal etching approach because the Cu etching formation compounds are hardly volatile at low temperature or the etch rate is relatively slow [39]. In the damascene pattering process, a dielectric is firstly etched, and then a Cu metallization is filled and polished. To prevent Cu diffusion and improve the adhesion with the dielectric layer, a barrier is required to surround the Cu wire [40, 41].

Dual-damascene patterning process is widely used to fabricate BEOL interconnects. In this method, both trench and via are patterned in a dielectric film simultaneously, and Cu metallization is filled into both trench and via. Compared to single-damascene patterning process, this method can reduce the processing step of Cu metallization. According to the order of via and trench pattering, dual-damascene patterning process has two types: "Via first" and "Trench first" processes [42, 43]. Generally, "Via first" dual-damascene process is widely used, plotted in **Figure 2**.

#### **Figure 2.**

*Via first dual-damascene patterning process: (A) Dielectrics (SiN/SiCN, SiCOH, SiO2) deposition. (B) Via-1 lithography and RIE. (C) ARC plug. (D) M-2 trench lithography and RIE. (E) Etching stop layer opening. (F) Metal barrier and Cu seed deposition. (G) Electroplating Cu deposition. (H) Cu CMP.*

*Porous Low-Dielectric-Constant Material for Semiconductor Microelectronics DOI: http://dx.doi.org/10.5772/intechopen.81577*

During the fabrication of BEOL interconnects, the used porous low-*k* dielectric material as an interconnecting insulator undergoes dielectric deposition, photoresist, etching, stripping, Cu metallization deposition, and chemical mechanical polishing (CMP) processes. Plasma damage, moisture/chemicals adsorption, Cu diffusion, and mechanical stress occurred on the porous low-*k* dielectric materials. These issues would reduce the electrical characteristics and reliability of the porous low-*k* dielectric materials. The mechanism and the resulting effect will be discussed in the following section.

In order to reduce the plasma-induced damage and pattern small features, the metal hardmask method and the multilayer resist method, as plotted in **Figures 3** and **4**, respectively, are proposed since 32 nm technology node [44–46]. In the metal hardmask process, the resist is stripped prior to the trench and via etching into the porous low-*k* ILD; therefore, resist-stripping process-induced damage can be minimal. However, the polymer may remain on the sidewalls of the trenches during the trench etching step. The remaining polymer must be removed without damaging the porous low-*k* dielectric material. Additionally, the stress in the metal layer must be minimized to avoid pattern deformation after the etching process. Metal residues can form on the etched surfaces and block etching of the porous low*k* dielectric material.

In the advanced technology nodes, the multilayer resist method is preferred because it has an advantage to pattern small features. However, the porous low-*k* dielectric material is fully exposed to the resist strips. In order to avoid

#### **Figure 3.**

**3. Integration of porous low-k dielectric materials in Cu interconnects**

As Cu metallization replaced Al metallization in BEOL interconnects, the fabrication process was also switched to damascene approach from metal etching approach because the Cu etching formation compounds are hardly volatile at low temperature or the etch rate is relatively slow [39]. In the damascene pattering process, a dielectric is firstly etched, and then a Cu metallization is filled and polished. To prevent Cu diffusion and improve the adhesion with the dielectric

Dual-damascene patterning process is widely used to fabricate BEOL intercon-

simultaneously, and Cu metallization is filled into both trench and via. Compared to single-damascene patterning process, this method can reduce the processing step of Cu metallization. According to the order of via and trench pattering, dual-damascene patterning process has two types: "Via first" and "Trench first" processes [42, 43]. Generally, "Via first" dual-damascene process is widely used, plotted in **Figure 2**.

*Via first dual-damascene patterning process: (A) Dielectrics (SiN/SiCN, SiCOH, SiO2) deposition. (B) Via-1 lithography and RIE. (C) ARC plug. (D) M-2 trench lithography and RIE. (E) Etching stop layer opening.*

*(F) Metal barrier and Cu seed deposition. (G) Electroplating Cu deposition. (H) Cu CMP.*

nects. In this method, both trench and via are patterned in a dielectric film

layer, a barrier is required to surround the Cu wire [40, 41].

**Table 2.**

**Figure 2.**

**174**

*Properties of various dielectric materials.*

*Nanofluid Flow in Porous Media*

*Metal hardmask dual-damascene patterning process: (A) TiN, ARC, and resist deposition. (B) M-2 metal hardmask RIE. (C) M-2 trench lithography. (D) Via-1 lithography. (E) Via-1 RIE. (F) M-2 oxide hardmask RIE. (G) M-2/Via-1 RIE and M-1 capping layer RIE. (H) M-2/Via-1 Cu metallization.*

material, the bandgap was determined to be between 8.0 and 10.0 eV, depending on the low-*k* dielectric types and the characterization techniques [48–50]. If the carbon content in the low-*k* dielectric film is not incorporated in the matrix network but primarily exists as terminal methyl groups, its bandgap is similar to that of SiO2 film. However, if the carbon content is present in the network bonds by forming Si-C-Si bridging structure, the bandgap value would drop dramatically. As porosity is introduced into the SiOCH low-*k* dielectric material, the bandgap of porous SiOCH low-*k* dielectrics (*k* = 2.0–3.3) is in the range between 7.5 and 10 eV [51]. The effect of porosity on the bandgap of porous SiOCH low-*k* dielectrics is not pronounced. More investigation about bandgap determination for porous low-*k* dielectric mate-

*Porous Low-Dielectric-Constant Material for Semiconductor Microelectronics*

*DOI: http://dx.doi.org/10.5772/intechopen.81577*

The conduction mechanisms of low-*k* dielectric materials are commonly described by Schottky emission (SE), Poole-Frenkel (PF) emission, and Fowler-Nordheim (FN) tunneling [52–54], as shown in the following Eqs. (3)–(5):

> *<sup>ϕ</sup>SE* � ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi *qE=*4*πε*0*ε<sup>r</sup>*

*kT* " # (3)

*kT* " # (4)

3*=*2 <sup>3</sup>*qhE* " # (5)

p

*<sup>ϕ</sup>*PF � ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi *qE=*4*πε*0*ε<sup>r</sup>*

<sup>2</sup>*m*<sup>∗</sup> <sup>p</sup> ð Þ *<sup>q</sup>ϕFN*

p

<sup>T</sup><sup>2</sup> exp �*<sup>q</sup>*

JFN � E2 exp �8*<sup>π</sup>* ffiffiffiffiffiffiffiffi

where *J* is current density, *A*\* is Richardson constant,*T* is temperature, *q* is the elementary charge, φ is barrier height, *E* is electric field, ε<sup>o</sup> is permittivity of free space, ε<sup>r</sup> is dielectric constant, *m*\* is effective electron mass, and h is Planck's

SE and PF emissions are field-enhanced thermal excitation conduction models. The excited electrons enter the conduction band from the low-*k* interface and the trap states with coulomb potentials for SE and PF emissions, respectively. FN tunneling conduction is caused by electrons tunneling from the metal Fermi energy or trapping sites in the material itself into the low-*k* dielectric conduction band. SE and PF emission currents are associated with the field and temperature. The former exhibits a strong temperature dependency. However, FN tunneling current exhibits a strong field dependency and is independent of temperature. Generally, PF emission is more likely the dominant conduction mechanism in low-*k* dielectric materials, especially at low fields. At high field, the dominant conduction mechanism

In the integrated interconnects, the barrier height at both the low-*k*/metal and the low-*k*/Si interfaces is around 4 eV, and the barrier height at the etching-stop layer/metal interface is less than 2.0 eV [57]. Therefore, the interface-controlled SE

JSE � E exp �*q*

rials is required.

constant.

• Schottky emission (SE)

• Poole-Frenkel (PF) emission

• Fowler-Nordheim (FN) tunneling

transfers to FN tunneling [55, 56].

emission occurs.

**177**

JSE <sup>¼</sup> <sup>A</sup><sup>∗</sup>

**Figure 4.**

*Multilayer resist dual-damascene process: (A) ARC and resist coating. (B) Via-1 lithography. (C) Via-1 RIE. (D) Multilayer resist coating and M-2 trench lithography. (E) LTO and OPL RIE. (F) M-2 trench RIE. (G) OPL strip and M-1 capping layer RIE. (H) M-2/Via-1 Cu metallization.*

plasma-induced damage on the porous low-*k* dielectric material, low-plasmadamage resist-stripping process is required for the multilayer resist method.
