Memristor Introduction and System Models

**3**

crossbar based analog counterparts.

complexity.

**Chapter 1**

Design

*Alex James*

Introductory Chapter: Challenges

**1. Introduction: what makes memristors attractive for neural networks?**

Another major design use case for memristor is the crossbar arrangement of the memristors. The memristors are arranged in a crossbar architecture, with each memristor being able to be accessed with rows and columns. The memristors are programmed using the transistor switch control, or selector switch control often referred to as ITIM or 1S1M configuration [6, 7]. Multiple transistors are usually required in the practical control circuits and depending on the complexity of the task such as the need to access multiple conductance states, the design aspects become complicated [8]. Nonetheless, a single crossbar can emulate a single dot product matrix computation that is required for weighted summation of inputs in a neural network layer. From a design perspective, at a higher level the simplification of multiply and accumulate operation is simplified, and it can reduce the design

The neuro-memristive system requires architectural level combinations of crossbars and memristor neurons, and be able to fabricate along with CMOS devices. Usually, sensors, control circuits and memories, would be required for the neural network to be scaled to a large network. The larger the network or deeper the number of layers in the neural network, the complexity of implementing increases. Large crossbar arrays suffer from the sneak path currents and non-idealities of the devices, which introduces errors in the dot-product computations, that propagate from one layer to another. While to some extent these errors can be compensated with learning algorithms, they do not fully compensate for the changes in real-time conditions. Online learning is possibly a way to compensate for real-time errors, however, online learning systems are not easy to realise for analog circuits and often consume a large amount of area on-chip and power. For digital implementations, in general, online learning circuits consume larger area and higher delays, than the

The ability of the memristors to change its conductance i.e. behaves like a resistor, and yet be able to remain in that conductive state, be able to change the state based on a control voltage makes it resemble like a neuron. The spiking neurons in the brain respond to the stimuli in different ways. The continuous application of stimuli and the changing response of the neuron to this is related to learning. In the same way, by application of voltage pulses of certain amplitude and frequency can cause a change in conductance state, reflecting as changing the amplitude of the current outputs through a memristor [1–3]. The voltage pulse trains below a threshold voltage for a given conductance state produces a current signal output that follows the input voltages reflecting learning ability. As such this idea can be translated to

in Neuro-Memristive Circuit

emulate spiking neurons with memristors [4, 5].

#### **Chapter 1**

## Introductory Chapter: Challenges in Neuro-Memristive Circuit Design

*Alex James*

#### **1. Introduction: what makes memristors attractive for neural networks?**

The ability of the memristors to change its conductance i.e. behaves like a resistor, and yet be able to remain in that conductive state, be able to change the state based on a control voltage makes it resemble like a neuron. The spiking neurons in the brain respond to the stimuli in different ways. The continuous application of stimuli and the changing response of the neuron to this is related to learning. In the same way, by application of voltage pulses of certain amplitude and frequency can cause a change in conductance state, reflecting as changing the amplitude of the current outputs through a memristor [1–3]. The voltage pulse trains below a threshold voltage for a given conductance state produces a current signal output that follows the input voltages reflecting learning ability. As such this idea can be translated to emulate spiking neurons with memristors [4, 5].

Another major design use case for memristor is the crossbar arrangement of the memristors. The memristors are arranged in a crossbar architecture, with each memristor being able to be accessed with rows and columns. The memristors are programmed using the transistor switch control, or selector switch control often referred to as ITIM or 1S1M configuration [6, 7]. Multiple transistors are usually required in the practical control circuits and depending on the complexity of the task such as the need to access multiple conductance states, the design aspects become complicated [8]. Nonetheless, a single crossbar can emulate a single dot product matrix computation that is required for weighted summation of inputs in a neural network layer. From a design perspective, at a higher level the simplification of multiply and accumulate operation is simplified, and it can reduce the design complexity.

The neuro-memristive system requires architectural level combinations of crossbars and memristor neurons, and be able to fabricate along with CMOS devices. Usually, sensors, control circuits and memories, would be required for the neural network to be scaled to a large network. The larger the network or deeper the number of layers in the neural network, the complexity of implementing increases. Large crossbar arrays suffer from the sneak path currents and non-idealities of the devices, which introduces errors in the dot-product computations, that propagate from one layer to another. While to some extent these errors can be compensated with learning algorithms, they do not fully compensate for the changes in real-time conditions. Online learning is possibly a way to compensate for real-time errors, however, online learning systems are not easy to realise for analog circuits and often consume a large amount of area on-chip and power. For digital implementations, in general, online learning circuits consume larger area and higher delays, than the crossbar based analog counterparts.

#### **2. Main challenges**

#### **2.1 Modelling issues**

Modelling realistic memristors devices is a challenging task [3]. There have been arguments for and against the existence of "ideal" memristor devices, based on electrical, physical, chemical and philosophical arguments [9, 10]. From a neural circuit design perspective, the arguments on the existence of such idealistic devices are practically not relevant. The more important question for the circuit designer is the accurate modelling of the practical device that can be either used as a spiking neuron or can be used in a crossbar.

When the models can incorporate into a simulator, it is important that the models represent accurately the true behaviour of the device and also are fast in terms of computation [3]. The ability for the models to be easily integrated into SPICE like simulators, that can enable simulations of millions of neurons are important for building neural networks [11]. Currently, the simulations with memristor models are extremely slow for deep neural networks, and often require the use of scripting languages such as Python to get around this issue.

#### **2.2 Lack of design tools**

There is limited availability of physical design kits (PDK) for use in standard design tools such as provided by Cadence [12], Mentor Graphics [13], Silvaco [14] etc. The support for memristor PDK suitable for integration with CMOS is largely an open problem. The accuracy of the design files is not comparable with CMOS processes, and the variability data is not very well disclosed. The design tools that can accurately translate the realistic memristor devices are not very common and is an active topic of study.

#### **2.3 Reliability issues of memristors**

The memristor devices suffer from a range of reliability issues. Some of the main issues include:

Ageing – the devices when switched ON and OFF for a long period of time suffer from the loss of conductance state. This creates a major problem in analog dot product computations with crossbar architecture. Ageing has better tolerance to binary neural networks [15, 16].

Noise – the electrical and thermal noise can play with the changes in output response of the memristors, which can interact with the design of the neurons. The exact interplay of the device noise within different configurations of the network is largely an open question [17].

Variability – the variability of the conductance due to process and fabrication challenges can create design challenges for the crossbars. The neural network design has shown to be tolerant to large variations in conductance [18–20]. The signal integrity and electromagnetics issues related to packaging also need to be taken into account in this challenge.

#### **2.4 Complexity issues for programming memristors**

Programming the memristors requires applying a series of voltage pulses for a sustained period of time until the conductance of the memristor changes to the desired value. The state changes are based on the magnitude of the voltages applied. The issue with the realistic design is the voltage control across several memristors is

**5**

*Introductory Chapter: Challenges in Neuro-Memristive Circuit Design*

not an easy task. The memristors in crossbar are prone to non-idealities and often faced with variable threshold voltages. This makes the design of the programing logic complex [21, 22]. The ability to program memristor devices in parallel with low cost on the power, and area on-chip, is a challenging program, especially if the

There are several types of neural networks. Many designs have multiple layers and they involve convolution layers that involve dendrite logic [24]. This makes the architecture design complex for generalisation. While crossbar-based designs can be used for a large number of neural network architectures, optimising the design for hardware is a totally different problem [6, 25]. The architectural changes need to be aligned with the circuit design challenges, especially, when the design constraints are with chasing accuracy and system-level performance metrics. The architectural designs also need to take care of a wide range of generalisation issues including those related to hardware-software co-design, and system of chip solutions [25].

Scaling the CMOS circuits, and improving the packing density of the memristors are not a well-studied problem. There have been several suggestions on using 3D technologies and using vertical devices for very-large-scale integration [26, 27]. The main challenge in this regard has been the variability of the devices that prevent the large-scale 3D integration of crossbar-based designs. There are yet not fullproof solutions to scaling up in density and scaling up in size. The best architecture level scale-up is the use of modular designs that make use of several small crossbars to create larger ones [28, 29]. However, these designs are yet to be fully tested in a

There are several types of neurons in the human brain [30–40]. The cognition is a result of interactions between varied types of neurons in the cortex. Most neural networks inspire from the cortical neural networks and often are oversimplifications of the biological networks. The exact form of how intelligence over a life-time of human are not very well understood to completely build an equivalent machine intelligence. At best what we have achieved today in neuro-chips is weak intelligence, being able to implement some specific functionality of the human brain, that too not in its entirety. The journey of hardware AI research is its very early stages, with a scalable design similar to the human brain practically limited by the chemistry of how neurons work. The organic nature of the brain offers several advantages over the silicon neuron. The electrical models are many, but they all tend to be bulky and complex when implemented in silicon. Having a functionally complex neuron with simplistic implementation complexity is a major challenge in

While these challenges exist, the practical use of neural networks build with crossbar and that using memristive spiking neurons are many. Several problems having a few sets of sensors such as in biomedical sensing applications only need

*DOI: http://dx.doi.org/10.5772/intechopen.91969*

design is for analog neural networks [23].

**2.5 Architectural challenges**

**2.6 Scaling and 3D integration**

realistic commercial application.

the system design of memristive neural networks.

**3. Discussions and future outlook**

**2.7 Neuron model**

#### *Introductory Chapter: Challenges in Neuro-Memristive Circuit Design DOI: http://dx.doi.org/10.5772/intechopen.91969*

not an easy task. The memristors in crossbar are prone to non-idealities and often faced with variable threshold voltages. This makes the design of the programing logic complex [21, 22]. The ability to program memristor devices in parallel with low cost on the power, and area on-chip, is a challenging program, especially if the design is for analog neural networks [23].

#### **2.5 Architectural challenges**

*Memristors - Circuits and Applications of Memristor Devices*

Modelling realistic memristors devices is a challenging task [3]. There have been

When the models can incorporate into a simulator, it is important that the models represent accurately the true behaviour of the device and also are fast in terms of computation [3]. The ability for the models to be easily integrated into SPICE like simulators, that can enable simulations of millions of neurons are important for building neural networks [11]. Currently, the simulations with memristor models are extremely slow for deep neural networks, and often require the use of scripting

There is limited availability of physical design kits (PDK) for use in standard design tools such as provided by Cadence [12], Mentor Graphics [13], Silvaco [14] etc. The support for memristor PDK suitable for integration with CMOS is largely an open problem. The accuracy of the design files is not comparable with CMOS processes, and the variability data is not very well disclosed. The design tools that can accurately translate the realistic memristor devices are not very common and is

The memristor devices suffer from a range of reliability issues. Some of the main

Ageing – the devices when switched ON and OFF for a long period of time suffer from the loss of conductance state. This creates a major problem in analog dot product computations with crossbar architecture. Ageing has better tolerance to

Noise – the electrical and thermal noise can play with the changes in output response of the memristors, which can interact with the design of the neurons. The exact interplay of the device noise within different configurations of the network is

Variability – the variability of the conductance due to process and fabrication challenges can create design challenges for the crossbars. The neural network design has shown to be tolerant to large variations in conductance [18–20]. The signal integrity and electromagnetics issues related to packaging also need to be taken into

Programming the memristors requires applying a series of voltage pulses for a sustained period of time until the conductance of the memristor changes to the desired value. The state changes are based on the magnitude of the voltages applied. The issue with the realistic design is the voltage control across several memristors is

arguments for and against the existence of "ideal" memristor devices, based on electrical, physical, chemical and philosophical arguments [9, 10]. From a neural circuit design perspective, the arguments on the existence of such idealistic devices are practically not relevant. The more important question for the circuit designer is the accurate modelling of the practical device that can be either used as a spiking

**2. Main challenges**

**2.1 Modelling issues**

neuron or can be used in a crossbar.

**2.2 Lack of design tools**

an active topic of study.

issues include:

**2.3 Reliability issues of memristors**

binary neural networks [15, 16].

largely an open question [17].

account in this challenge.

**2.4 Complexity issues for programming memristors**

languages such as Python to get around this issue.

**4**

There are several types of neural networks. Many designs have multiple layers and they involve convolution layers that involve dendrite logic [24]. This makes the architecture design complex for generalisation. While crossbar-based designs can be used for a large number of neural network architectures, optimising the design for hardware is a totally different problem [6, 25]. The architectural changes need to be aligned with the circuit design challenges, especially, when the design constraints are with chasing accuracy and system-level performance metrics. The architectural designs also need to take care of a wide range of generalisation issues including those related to hardware-software co-design, and system of chip solutions [25].

#### **2.6 Scaling and 3D integration**

Scaling the CMOS circuits, and improving the packing density of the memristors are not a well-studied problem. There have been several suggestions on using 3D technologies and using vertical devices for very-large-scale integration [26, 27]. The main challenge in this regard has been the variability of the devices that prevent the large-scale 3D integration of crossbar-based designs. There are yet not fullproof solutions to scaling up in density and scaling up in size. The best architecture level scale-up is the use of modular designs that make use of several small crossbars to create larger ones [28, 29]. However, these designs are yet to be fully tested in a realistic commercial application.

#### **2.7 Neuron model**

There are several types of neurons in the human brain [30–40]. The cognition is a result of interactions between varied types of neurons in the cortex. Most neural networks inspire from the cortical neural networks and often are oversimplifications of the biological networks. The exact form of how intelligence over a life-time of human are not very well understood to completely build an equivalent machine intelligence. At best what we have achieved today in neuro-chips is weak intelligence, being able to implement some specific functionality of the human brain, that too not in its entirety. The journey of hardware AI research is its very early stages, with a scalable design similar to the human brain practically limited by the chemistry of how neurons work. The organic nature of the brain offers several advantages over the silicon neuron. The electrical models are many, but they all tend to be bulky and complex when implemented in silicon. Having a functionally complex neuron with simplistic implementation complexity is a major challenge in the system design of memristive neural networks.

#### **3. Discussions and future outlook**

While these challenges exist, the practical use of neural networks build with crossbar and that using memristive spiking neurons are many. Several problems having a few sets of sensors such as in biomedical sensing applications only need smaller neural networks to make the sensor intelligent. Likewise, many time-series based prediction problems use one-dimensional data that again only need simple recurrent neural networks.

The practical implementation of large scale networks is required to match the neural network scale and size of the human brain [41–46]. Packing billions of neurons into a single chip is a major challenge, that requires to match the energy benchmarks and complexity. Current circuit implementations fail to match up with the energy benchmarks of the human brain, mainly as the scaling of power supply on chips are practically limited by electrical design and device constraints. In addition to this, packaging and electromagnetic effects also play a major role in building systems with neural chips. The precision engineering of these chips for reliable use is important for long term acceptability in higher intelligence tasks. Further, the data processing with the neurochips can be prone to adversarial attacks, which means the system needs to be made secure using dedicated cryptographic coprocessors. Going further, it will be also important to see the applications of these neurochips in human-machine interfaces, and for building connected and collective intelligence solutions.

Ageing is a time-dependent process, where the conductance of the memristors changes over a period of time and use [15, 16, 47–49]. The more the memristors are used, i.e., writing and reading, the ability to keep the expected conductance levels diminishes. This is wearing out the phenomenon that the memristor devices face due to continuous electrical stress on the devices impacting the chemistry and physics of the device. Over a period of time, the multiple conductance states get combined, or disappeared, making the reliability of programming memristors challenging. This makes fine-tuning as an essential part of memristor programming and test stages. Any changes in the conductance values introduce undesirable errors in the output of the crossbar arrays, which is far from expected ideal behaviour. This is a serious issue when the multiple conductance states are extensively used for building analog neural networks with crossbar arrays. The conductance of the memristors is equated to weights in the analog neural network, and hence if a conductance state goes missing it makes the training more complicated. Additional, rules need to be framed to the pre-trained network models to further adjust the weight values to achieve convergence. Learning and self-tuning in this sense is an online process for analog neural networks with memristor crossbar arrays. Nonetheless, the advantages of the analog neural networks with crossbar outweigh the digital-only counterpart, for smart sensor integration and edge AI computing [50–59].

When the noise gets added to the signals at input, in-network layers or outputs of the analog neural network, it introduces errors in the layers of the neural networks. The noise can originate in different ways, such as due to thermal effects, electromagnetic effects, or through external sources. Noise is typically seen as a problem in circuits, however, with neural networks this may have some advantages to offer, such as with avoiding overfitting during training. The role of noise in the human brain is immense and it plays some major role in the way intelligence and perception is shaped [60, 61].

#### **4. Conclusions**

There are several open challenges in neuro-memristive circuit design. The design challenges go from classical circuit analysis to computer-aided design issues. The major bottleneck with creating a billion-neuron chip is the limitations imposed at the device and at architecture levels. There are yet no practical tools that can help address all the design challenges in a systematic way. Unlike software tools, where

**7**

**Author details**

\*Address all correspondence to: apj@ieee.org

provided the original work is properly cited.

Indian Institute of Information Technology and Management, Kerala, Trivandrum,

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

Alex James

India

*Introductory Chapter: Challenges in Neuro-Memristive Circuit Design*

debugging is a well-detailed topic of study, the neuro-memristive hardware design is not easy to debug due to a variety of non-idealities of crossbar and memristor devices. There have been several proofs of concepts of circuit designs and a growing body of literature on architectures that aim to address these very challenges. However, there is a long way to go before many of these designs can be put for commercial use on a large scale. The digital designs of neural networks are much more feasible than analog neural networks at this point in time. In the future, it is expected that analog neural networks will have a much more important role to play in making sensors smarter and make intelligent computing energy-efficient.

*DOI: http://dx.doi.org/10.5772/intechopen.91969*

#### *Introductory Chapter: Challenges in Neuro-Memristive Circuit Design DOI: http://dx.doi.org/10.5772/intechopen.91969*

*Memristors - Circuits and Applications of Memristor Devices*

recurrent neural networks.

intelligence solutions.

perception is shaped [60, 61].

**4. Conclusions**

smaller neural networks to make the sensor intelligent. Likewise, many time-series based prediction problems use one-dimensional data that again only need simple

The practical implementation of large scale networks is required to match the neural network scale and size of the human brain [41–46]. Packing billions of neurons into a single chip is a major challenge, that requires to match the energy benchmarks and complexity. Current circuit implementations fail to match up with the energy benchmarks of the human brain, mainly as the scaling of power supply on chips are practically limited by electrical design and device constraints. In addition to this, packaging and electromagnetic effects also play a major role in building systems with neural chips. The precision engineering of these chips for reliable use is important for long term acceptability in higher intelligence tasks. Further, the data processing with the neurochips can be prone to adversarial attacks, which means the system needs to be made secure using dedicated cryptographic coprocessors. Going further, it will be also important to see the applications of these neurochips in human-machine interfaces, and for building connected and collective

Ageing is a time-dependent process, where the conductance of the memristors changes over a period of time and use [15, 16, 47–49]. The more the memristors are used, i.e., writing and reading, the ability to keep the expected conductance levels diminishes. This is wearing out the phenomenon that the memristor devices face due to continuous electrical stress on the devices impacting the chemistry and physics of the device. Over a period of time, the multiple conductance states get combined, or disappeared, making the reliability of programming memristors challenging. This makes fine-tuning as an essential part of memristor programming and test stages. Any changes in the conductance values introduce undesirable errors in the output of the crossbar arrays, which is far from expected ideal behaviour. This is a serious issue when the multiple conductance states are extensively used for building analog neural networks with crossbar arrays. The conductance of the memristors is equated to weights in the analog neural network, and hence if a conductance state goes missing it makes the training more complicated. Additional, rules need to be framed to the pre-trained network models to further adjust the weight values to achieve convergence. Learning and self-tuning in this sense is an online process for analog neural networks with memristor crossbar arrays. Nonetheless, the advantages of the analog neural networks with crossbar outweigh the digital-only

counterpart, for smart sensor integration and edge AI computing [50–59].

When the noise gets added to the signals at input, in-network layers or outputs of the analog neural network, it introduces errors in the layers of the neural networks. The noise can originate in different ways, such as due to thermal effects, electromagnetic effects, or through external sources. Noise is typically seen as a problem in circuits, however, with neural networks this may have some advantages to offer, such as with avoiding overfitting during training. The role of noise in the human brain is immense and it plays some major role in the way intelligence and

There are several open challenges in neuro-memristive circuit design. The design challenges go from classical circuit analysis to computer-aided design issues. The major bottleneck with creating a billion-neuron chip is the limitations imposed at the device and at architecture levels. There are yet no practical tools that can help address all the design challenges in a systematic way. Unlike software tools, where

**6**

debugging is a well-detailed topic of study, the neuro-memristive hardware design is not easy to debug due to a variety of non-idealities of crossbar and memristor devices. There have been several proofs of concepts of circuit designs and a growing body of literature on architectures that aim to address these very challenges. However, there is a long way to go before many of these designs can be put for commercial use on a large scale. The digital designs of neural networks are much more feasible than analog neural networks at this point in time. In the future, it is expected that analog neural networks will have a much more important role to play in making sensors smarter and make intelligent computing energy-efficient.

### **Author details**

Alex James Indian Institute of Information Technology and Management, Kerala, Trivandrum, India

\*Address all correspondence to: apj@ieee.org

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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**11**

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discrimination sensitivity. The Journal of Neuroscience. 2011;**31**(49):17971-17981

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Advanced Electronic Materials.

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Jha SK. Input-aware flow-based computing on memristor crossbars with applications to edge detection. IEEE Journal on Emerging and Selected

Topics in Circuits and Systems.

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[57] Chakraborty D, Raj S, Fernandes SL,

2016;**2**(9):1600090

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Advanced Electronic Materials. 2016;**2**(9):1600090

*Memristors - Circuits and Applications of Memristor Devices*

[44] Navarrete A, van Schaik CP, Isler K.

[45] Tomasi D, Wang GJ, Volkow ND. Energetic cost of brain functional connectivity. Proceedings of the National Academy of Sciences. 2013;**110**(33):13642-13647

[46] Bélanger M, Allaman I, Magistretti PJ. Brain energy metabolism: Focus on astrocyte-neuron metabolic cooperation. Cell Metabolism.

[47] Kumar S, Wang Z, Huang X, Kumari N, Davila N, Strachan JP, et al. Oxygen migration during resistance switching and failure of hafnium oxide memristors. Applied Physics Letters.

[48] Valov I, Kozicki M. Non-volatile memories: Organic memristors come of age. Nature Materials.

[49] Lohn AJ, Mickel PR, Aimone JB, Debenedictis EP, Marinella MJ. Memristors as synapses in artificial neural networks: Biomimicry beyond weight change. In: Cybersecurity Systems for Human Cognition

Augmentation. Cham: Springer; 2014.

[50] Kozma R, Pino RE, Pazienza GE. Are memristors the future of AI? In: Advances in Neuromorphic Memristor Science and Applications. Dordrecht:

[51] Wang Z, Li C, Lin P, Rao M, Nie Y, Song W, et al. In situ training of feedforward and recurrent convolutional memristor networks. Nature Machine Intelligence. 2019;**1**(9):434-442

[52] Jeong DS, Kim KM, Kim S, Choi BJ, Hwang CS. Memristors for energyefficient new computing paradigms.

Springer; 2012. pp. 9-14

2011;**14**(6):724-738

2017;**110**(10):103503

2017;**16**(12):1170-1172

pp. 135-150

Energetics and the evolution of human brain size. Nature. 2011;**480**(7375):91-93

[35] Jolivet R, Kobayashi R, Rauch A, Naud R, Shinomoto S, Gerstner W. A benchmark test for a quantitative assessment of simple neuron models. Journal of Neuroscience Methods.

[36] Druckmann S, Banitt Y, Gidon AA, Schürmann F, Markram H, Segev I. A novel multiple objective optimization

Magnusson AK, Brette R. Fitting neuron models to spike trains. Frontiers in

[38] Coombes S, Thul R, Wedgwood KC.

[39] Gerstner W, Kistler WM, Naud R, Paninski L. Neuronal Dynamics: From Single Neurons to Networks and Models of Cognition. 1st Edn. Cambridge University Press; 2014. p. 590

[40] Makino T. A discrete-event neural network simulator for general neuron models. Neural Computing and Applications. 2003;**11**(3-4):210-223

[41] Prieto A, Prieto B, Ortigosa EM, Ros E, Pelayo F, Ortega J, et al. Neural networks: An overview of early research, current frameworks and new challenges. Neurocomputing.

[42] Hecht-Nielsen R. Neurocomputing:

[43] Zhu XH, Qiao H, Du F, Xiong Q, Liu X, Zhang X, et al. Quantitative imaging of energy expenditure in human brain. NeuroImage.

Picking the human brain. IEEE Spectrum. 1988;**25**(3):36-41

2016;**214**:242-268

2012;**60**(4):2107-2117

Nonsmooth dynamics in spiking neuron models. Physica D: Nonlinear Phenomena. 2012;**241**(22):2042-2057

2008;**169**(2):417-424

framework for constraining conductance-based neuron models by experimental data. Frontiers in

[37] Rossant C, Goodman DF, Fontaine B, Platkiewicz J,

Neuroscience. 2007;**1**:1

Neuroscience. 2011;**5**:9

**10**

discrimination sensitivity. The Journal of Neuroscience. 2011;**31**(49):17971-17981

[53] Li C, Wang Z, Rao M, Belkin D, Song W, Jiang H, et al. Long shortterm memory networks in memristor crossbar arrays. Nature Machine Intelligence. 2019;**1**(1):49-57

[54] Vourkas I, Sirakoulis GC. Memristor-Based Nanoelectronic Computing Circuits and Architectures. Cham: Springer International Publishing; 2016

[55] Zhang X, Huang A, Hu Q, Xiao Z, Chu PK. Neuromorphic computing with memristor crossbar. Physica Status Solidi. 2018;**215**(13):1700875

[56] Jiang W, Xie B, Liu CC, Shi Y. Integrating memristors and CMOS for better AI. Nature Electronics. 2019;**2**(9):376-377

[57] Chakraborty D, Raj S, Fernandes SL, Jha SK. Input-aware flow-based computing on memristor crossbars with applications to edge detection. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2019;**9**(3):580-591

[58] Versace M, Chandler B. The brain of a new machine. IEEE Spectrum. 2010;**47**(12):30-37

[59] Vourkas I, Stathis D, Sirakoulis GC. Massively parallel analog computing: Ariadne's thread was made of memristors. IEEE Transactions on Emerging Topics in Computing. 2015;**6**(1):145-155

[60] Fraiman D, Chialvo DR. What kind of noise is brain noise: Anomalous scaling behavior of the resting brain activity fluctuations. Frontiers in Physiology. 2012;**3**:307

[61] Bernasconi F, De Lucia M, Tzovara A, Manuel AL, Murray MM, Spierer L. Noise in brain activity engenders perception and influences

**13**

**Chapter 2**

**Abstract**

Memristor Synapses for

ristor synapse in forms of crossbar arrays.

memristive systems

**1. Introduction**

Neuromorphic Computing

*Sanghyeon Choi, Seonggil Ham and Gunuk Wang*

Neuromorphic computing, which imitates the principle behind biological synapses with a high degree of parallelism, has recently emerged as a promising candidate for novel and sustainable computing technologies. The first step toward realizing a massively parallel neuromorphic system is to develop an artificial synapse capable of emulating synapse functionality, such as analog modulation, with ultralow power consumption and robust controllability. We begin this chapter with a simple description of neuromorphic systems and memristor synapses. Further, we introduce and evaluate the state-of-the-art neuromorphic hardware technology in terms of novel functional materials and device architectures toward the implementation of fully neuromorphic computers, which have been extensively explored in recent years. Finally, we briefly describe artificial neural networks based on mem-

**Keywords:** memristor, artificial synapse, neuromorphic, bio-inspired,

Modern computers and electronics, such as smartphones and supercomputers, have been developed in accordance with Moore's law [1], which implies improvement in cost, speed, and power consumption by scaling down devices. However, the fundamental physical limits and increased fabrication costs pose a hindrance to sustainable development of computing technology [2, 3]. Moreover, with the advent of the big data era, unstructured data and data complexity explosively increases, imposing constraints on the conventional computing technology owing to the von Neumann bottleneck [4, 5]. Neuromorphic systems [6, 7], which mimic the nervous system in the brain, have recently become known as strong candidates to overcome these technical and economic limitations owing to their proficiency in cognitive and data-intensive tasks, together with their low power consumption. To successfully implement these neuromorphic systems, it is of utmost importance to research and develop artificial synapses capable of synapse functions, high reliability, low energy consumption, etc. [8, 9]. In the plethora of possible devices, memristors have gained the spotlight because of their desirable characteristics as artificial synapses [10–12], including device speed [13], footprint [14], low energy consumption [15], and analog switching [16, 17]. In this chapter, we introduce the basic concepts of neuromorphic systems and memristor synapses. We also describe diverse examples for state-of-the-art artificial synapses in terms of novel functional materials and device architecture. We then briefly review the implemented neuromorphic systems based on memristor synapses.

#### **Chapter 2**

## Memristor Synapses for Neuromorphic Computing

*Sanghyeon Choi, Seonggil Ham and Gunuk Wang*

#### **Abstract**

Neuromorphic computing, which imitates the principle behind biological synapses with a high degree of parallelism, has recently emerged as a promising candidate for novel and sustainable computing technologies. The first step toward realizing a massively parallel neuromorphic system is to develop an artificial synapse capable of emulating synapse functionality, such as analog modulation, with ultralow power consumption and robust controllability. We begin this chapter with a simple description of neuromorphic systems and memristor synapses. Further, we introduce and evaluate the state-of-the-art neuromorphic hardware technology in terms of novel functional materials and device architectures toward the implementation of fully neuromorphic computers, which have been extensively explored in recent years. Finally, we briefly describe artificial neural networks based on memristor synapse in forms of crossbar arrays.

**Keywords:** memristor, artificial synapse, neuromorphic, bio-inspired, memristive systems

#### **1. Introduction**

Modern computers and electronics, such as smartphones and supercomputers, have been developed in accordance with Moore's law [1], which implies improvement in cost, speed, and power consumption by scaling down devices. However, the fundamental physical limits and increased fabrication costs pose a hindrance to sustainable development of computing technology [2, 3]. Moreover, with the advent of the big data era, unstructured data and data complexity explosively increases, imposing constraints on the conventional computing technology owing to the von Neumann bottleneck [4, 5]. Neuromorphic systems [6, 7], which mimic the nervous system in the brain, have recently become known as strong candidates to overcome these technical and economic limitations owing to their proficiency in cognitive and data-intensive tasks, together with their low power consumption. To successfully implement these neuromorphic systems, it is of utmost importance to research and develop artificial synapses capable of synapse functions, high reliability, low energy consumption, etc. [8, 9]. In the plethora of possible devices, memristors have gained the spotlight because of their desirable characteristics as artificial synapses [10–12], including device speed [13], footprint [14], low energy consumption [15], and analog switching [16, 17].

In this chapter, we introduce the basic concepts of neuromorphic systems and memristor synapses. We also describe diverse examples for state-of-the-art artificial synapses in terms of novel functional materials and device architecture. We then briefly review the implemented neuromorphic systems based on memristor synapses.

#### **2. Neuromorphic systems and memristor synapses**

#### **2.1 Neuromorphic systems**

Conventional computing architecture, that is, von Neumann architecture, forms the groundwork for modern computing technologies [3, 18]. Despite tremendous growth in computing performance, classical architecture currently suffers from the von Neumann bottleneck, which results from data movements between the processor and the memory unit [4, 5]. The memory wall issue, causing high power consumption and low speed, hinders the continuous development of computing technologies [4, 5, 9]. Moreover, artificial neural network (ANN) algorithms, such as deep learning [19], deal with image classification [20, 21], sound recognition [22, 23], specific complex tasks (e.g., the AlphaGo [24]) and so on. Although the ANN algorithms have exhibited superior performance over the conventional computing technologies, they are, at present, constructed on the von Neumann architecture; hence, considerable time and energy resources are required for their operation [8, 9]. Neuromorphic architecture [6, 7], a bio-inspired computing architecture, is one of the most promising candidates to resolve these problems. The neuromorphic systems take advantage of the cerebral nervous system, which consists of a massive parallel connectivity between the neurons (i.e., processor) and the synapses (i.e., memory), indicating the absence of the von Neumann bottleneck [8, 9]. **Figure 1** shows the shift of the computing architecture from von Neumann architecture (**Figure 1a**) to neuromorphic architecture (**Figure 1b**). The von Neumann architecture shows that the processor and memory are separate, leading to the von Neumann bottleneck. In contrast, in the case of neuromorphic architecture, the neurons and synapses are combined, alleviating the bottleneck issue. The neurons are uncomplicated computing units, the synapses are local memory units, and the communication channels (red line) connect numerous neurons and synapses. It should be noted that the practical purpose of neuromorphic systems is not to replace the von Neumann architecture completely, but to supplement the conventional architecture to make up its leeway, especially for intelligent tasks such as image recognition and natural language processing.

#### **Figure 1.**

*(a) Conventional computing architecture (von Neumann architecture). Data transfer is performed through the bus (memory wall). (b) Neuromorphic architecture. In contrast to von Neumann architecture, von Neumann bottleneck does not exist.*

**15**

to Ag+

Ag+

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

all-encompassed characteristics so far.

**2.3 Switching mechanisms**

electrolyte layer. The Ag+

Memristors that consist of a storage layer inserted between the top and bottom electrodes can undergo dynamic reconfiguration within the storage layer with the application of electrical stimuli, resulting in resistance modulation referred to as memory effect [16, 17]. The changed resistance state can be retained even after electrical inputs are removed, and memristors are based on the history of applied electrical stimuli. These capabilities lead to analog switching, which resembles biological synapses where the strength (or synaptic weight) can increase or decrease depending on the applied action potential [25, 26]. When neuromorphic architecture is implemented on the conventional computing architecture, the synaptic weights are stored in the memory unit and are continuously read into the processor unit to transfer information to post-neurons. In other words, practically, the von Neumann bottleneck still remains challenged. However, in case of memristor synapse-based neuromorphic systems, the synapses can not only store a specific weight but also naturally transmit information into post-neurons, overcoming the von Neumann bottleneck and improving system efficiency [8, 9]. In addition to analog switching, memristors have exhibited desirable device properties, including nanoscale footprint [14], long endurance and retention [17, 27], nanosecond switching speed [13, 15], and low power consumption [15]. Owing to these characteristics, memristors have emerged as promising candidates for artificial synapses. However, it should be noted that no specific material/device system has shown

Depending on their storage layer and electrode, memristors can be broadly classified into two categories: cation-based devices and anion-based devices. It is widely believed that cation-based devices are based on migration of metallic cations (see **Figure 2a**) [17, 28]. They employ electrochemically active materials such as Ag or Cu as an electrode [29–32]. The counter electrode is usually an electrochemically inert material, such as Pt, Au, or W, and the storage layer consists of a solidelectrolyte like Ta2O5, SiO2, or Cu2S. For example, when a positive voltage is applied to an Ag top electrode, the atoms from this electrode are electrochemically oxidized

cations because of anodic reaction, which are then dissolved into a solid-

the counter electrode (e.g., Pt) depending on electric field. At the Pt electrode, the

 cations are electrochemically reduced to Ag atoms because of cathodic reaction and are deposited on its surface. Thus, conductive filaments grow toward the Ag top electrode, and eventually the filaments bridge the anode and the cathode, indicating that the device switches into ON state (low resistance state) as shown in **Figure 2a**. In contrast, when a negative voltage is applied to the Ag top electrode, the Ag filament begins to dissolve anodically, starting from the interface of the Ag top electrode/Ag filament, which results in OFF state (high resistance state). Owing to this process, cation-based devices are referred to as electrochemical metallization memories and conductive bridging random access memories. It should be noted that the initial formation of conductive filaments is called the electroforming

Anion-based devices usually require the initial electroforming process and are switched depending on the O2<sup>−</sup> anions (or positively charged oxygen vacancy V) induced into the storage layer by soft-breakdown (see **Figure 2b**). These devices consist of a sub-stoichiometric storage layer made of HfOx [33, 34], TaOx [35, 36], WOx [37, 38], etc. When a positive forming voltage is applied to the top electrode,

process, which needs a voltage higher than a switching voltage.

cations migrate across the solid-electrolyte layer toward

**2.2 Memristor synapses**

#### **2.2 Memristor synapses**

*Memristors - Circuits and Applications of Memristor Devices*

**2.1 Neuromorphic systems**

**2. Neuromorphic systems and memristor synapses**

as image recognition and natural language processing.

*(a) Conventional computing architecture (von Neumann architecture). Data transfer is performed through the bus (memory wall). (b) Neuromorphic architecture. In contrast to von Neumann architecture, von Neumann* 

Conventional computing architecture, that is, von Neumann architecture, forms the groundwork for modern computing technologies [3, 18]. Despite tremendous growth in computing performance, classical architecture currently suffers from the von Neumann bottleneck, which results from data movements between the processor and the memory unit [4, 5]. The memory wall issue, causing high power consumption and low speed, hinders the continuous development of computing technologies [4, 5, 9]. Moreover, artificial neural network (ANN) algorithms, such as deep learning [19], deal with image classification [20, 21], sound recognition [22, 23], specific complex tasks (e.g., the AlphaGo [24]) and so on. Although the ANN algorithms have exhibited superior performance over the conventional computing technologies, they are, at present, constructed on the von Neumann architecture; hence, considerable time and energy resources are required for their operation [8, 9]. Neuromorphic architecture [6, 7], a bio-inspired computing architecture, is one of the most promising candidates to resolve these problems. The neuromorphic systems take advantage of the cerebral nervous system, which consists of a massive parallel connectivity between the neurons (i.e., processor) and the synapses (i.e., memory), indicating the absence of the von Neumann bottleneck [8, 9]. **Figure 1** shows the shift of the computing architecture from von Neumann architecture (**Figure 1a**) to neuromorphic architecture (**Figure 1b**). The von Neumann architecture shows that the processor and memory are separate, leading to the von Neumann bottleneck. In contrast, in the case of neuromorphic architecture, the neurons and synapses are combined, alleviating the bottleneck issue. The neurons are uncomplicated computing units, the synapses are local memory units, and the communication channels (red line) connect numerous neurons and synapses. It should be noted that the practical purpose of neuromorphic systems is not to replace the von Neumann architecture completely, but to supplement the conventional architecture to make up its leeway, especially for intelligent tasks such

**14**

**Figure 1.**

*bottleneck does not exist.*

Memristors that consist of a storage layer inserted between the top and bottom electrodes can undergo dynamic reconfiguration within the storage layer with the application of electrical stimuli, resulting in resistance modulation referred to as memory effect [16, 17]. The changed resistance state can be retained even after electrical inputs are removed, and memristors are based on the history of applied electrical stimuli. These capabilities lead to analog switching, which resembles biological synapses where the strength (or synaptic weight) can increase or decrease depending on the applied action potential [25, 26]. When neuromorphic architecture is implemented on the conventional computing architecture, the synaptic weights are stored in the memory unit and are continuously read into the processor unit to transfer information to post-neurons. In other words, practically, the von Neumann bottleneck still remains challenged. However, in case of memristor synapse-based neuromorphic systems, the synapses can not only store a specific weight but also naturally transmit information into post-neurons, overcoming the von Neumann bottleneck and improving system efficiency [8, 9]. In addition to analog switching, memristors have exhibited desirable device properties, including nanoscale footprint [14], long endurance and retention [17, 27], nanosecond switching speed [13, 15], and low power consumption [15]. Owing to these characteristics, memristors have emerged as promising candidates for artificial synapses. However, it should be noted that no specific material/device system has shown all-encompassed characteristics so far.

#### **2.3 Switching mechanisms**

Depending on their storage layer and electrode, memristors can be broadly classified into two categories: cation-based devices and anion-based devices. It is widely believed that cation-based devices are based on migration of metallic cations (see **Figure 2a**) [17, 28]. They employ electrochemically active materials such as Ag or Cu as an electrode [29–32]. The counter electrode is usually an electrochemically inert material, such as Pt, Au, or W, and the storage layer consists of a solidelectrolyte like Ta2O5, SiO2, or Cu2S. For example, when a positive voltage is applied to an Ag top electrode, the atoms from this electrode are electrochemically oxidized to Ag+ cations because of anodic reaction, which are then dissolved into a solidelectrolyte layer. The Ag+ cations migrate across the solid-electrolyte layer toward the counter electrode (e.g., Pt) depending on electric field. At the Pt electrode, the Ag+ cations are electrochemically reduced to Ag atoms because of cathodic reaction and are deposited on its surface. Thus, conductive filaments grow toward the Ag top electrode, and eventually the filaments bridge the anode and the cathode, indicating that the device switches into ON state (low resistance state) as shown in **Figure 2a**. In contrast, when a negative voltage is applied to the Ag top electrode, the Ag filament begins to dissolve anodically, starting from the interface of the Ag top electrode/Ag filament, which results in OFF state (high resistance state). Owing to this process, cation-based devices are referred to as electrochemical metallization memories and conductive bridging random access memories. It should be noted that the initial formation of conductive filaments is called the electroforming process, which needs a voltage higher than a switching voltage.

Anion-based devices usually require the initial electroforming process and are switched depending on the O2<sup>−</sup> anions (or positively charged oxygen vacancy V) induced into the storage layer by soft-breakdown (see **Figure 2b**). These devices consist of a sub-stoichiometric storage layer made of HfOx [33, 34], TaOx [35, 36], WOx [37, 38], etc. When a positive forming voltage is applied to the top electrode,

**Figure 2.**

*(a) Cation-based devices: Through electrochemical reaction, metal cations M+ migrate toward the counter electrode and form conductive filaments between the top and bottom electrodes. (b) Anion-based devices: During electroforming, the soft-breakdown leads to O<sup>2</sup><sup>−</sup> ions (oxygen vacancies V), and the oxygen vacancies form conductive filaments between the top and bottom electrodes.*

the induced O2<sup>−</sup> ions migrate toward it. This anion motion causes a change in the valence state of the cation to keep the charge neutral; hence, these devices are also referred to as valance change memories. Throughout the process, the oxygen vacancies continue to form conductive filaments in the storage layer. When the filaments bridge the top and bottom electrodes, current flows through the filaments, with the result that the device switches to ON state. Contrastingly, when a negative voltage is applied to the top electrode, the O2<sup>−</sup> ions either recombine with oxygen vacancies present in the filaments or oxidize the cation precipitates, with the result that the device switches to OFF state. Thus, memristors could be understood to some extent based on cation- and anion-based mechanisms. However, identifying the precise mechanism of a specific device is a challenge because of the presence of mingled mechanisms and different driving forces or locations. Therefore, further studies are necessary for a deeper understanding of the switching mechanism.

#### **2.4 Desirable properties of memristor synapses**

Various properties of memristor synapses that affect the performance of neuromorphic computing need to be discussed in detail. Among them, representative characteristics such as the linearity in weight update, multilevel states, dynamic range (ON/OFF ratio), variation, retention, endurance, and footprint will be addressed in this section as they can substantially affect computing achievements [8, 35]. The linearity of the weight update indicates the linear relationship between synaptic weight change (∆w) and programming pulse. In other words, the conductance of the memristor synapse changes linearly in accordance with the number of programming pulses, which is associated with the mapping of weight in the algorithms for conductance in memristor synapses. Hence, the linearity of weight update affects the performance (e.g., accuracy). Notably, most memristor synapses

**17**

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

to achieve highly efficient computing.

*respectively. Copyright (2017, 2010) American Chemical Society.*

**Figure 3.**

learned information under a specific area [8].

**functional materials**

[7–12, 35, 39–55].

show a nonlinear weight update, where the conductance change gradually saturates, as shown in **Figure 3**. Hence, the nonlinearity of weight update should be improved

*(a, b) Nonlinearity of weight update. Current abruptly changes in initial pulses and gradually saturates. Most memristors exhibit a nonlinear relationship. All figures are reproduced with permission from Ref [39, 10],* 

Furthermore, it is efficient to improve the characteristics of memristor synapses depending on individual neuromorphic networks, because a desirable memristor synapse capable of being employed into neuromorphic systems is yet to be reported. Supervised learning-based networks [35, 40–44], for example, are less vulnerable to cycle-to-cycle and device-to-device variations. This is because memristor synapses are updated according to calculated errors under known target values. By contrast, the networks based on unsupervised learning [39, 45–47] are directly affected by the variation owing to unknown target values. Therefore, memristor synapses need to be designed or selected depending on individual neuromorphic networks.

**3. Artificial synapses in terms of device architecture and novel** 

Memristors for synaptic devices with two-terminal (e.g., vertical/planar-type and gap-type) and three-terminal (e.g., field-effect transistor and lateral coupling type) structures are manufactured by well-established processing technologies

In the case of a two-terminal structure, when different voltages are applied to each of the two electrodes, resulting in current flow through the insulator, varying the conductance of the device enables emulation of biological synapse functions such as synapse plasticity [10–12, 16, 35, 48]. In particular, the crossbar array of

The resolution capability of storage is influenced by multilevel states and dynamic ranges because numerous conductance states can distinguishably store individual pixels of input patterns. Moreover, variations, including cycle-to-cycle and device-to-device variations, could degrade neuromorphic computing, particularly in large-scale systems. However, considering that neuromorphic computing exhibits the fault-tolerant property, neuromorphic architectures could be immune to the variation to some extent, and this is supported by several papers [8, 35, 52]. In addition, memristor synapses are repeatedly updated during the training process and should retain the trained weights (i.e., final conductance). Subsequently, the larger the endurance cycles and retention time, the better are the achievements of the neuromorphic network. Last but not least, it is desirable that device's footprint is below sub-10 nm because high density leads to more synaptic devices that store

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

**Figure 3.**

*Memristors - Circuits and Applications of Memristor Devices*

the induced O2<sup>−</sup> ions migrate toward it. This anion motion causes a change in the valence state of the cation to keep the charge neutral; hence, these devices are also referred to as valance change memories. Throughout the process, the oxygen vacancies continue to form conductive filaments in the storage layer. When the filaments bridge the top and bottom electrodes, current flows through the filaments, with the result that the device switches to ON state. Contrastingly, when a negative voltage is applied to the top electrode, the O2<sup>−</sup> ions either recombine with oxygen vacancies present in the filaments or oxidize the cation precipitates, with the result that the device switches to OFF state. Thus, memristors could be understood to some extent based on cation- and anion-based mechanisms. However, identifying the precise mechanism of a specific device is a challenge because of the presence of mingled mechanisms and different driving forces or locations. Therefore, further studies are

*electrode and form conductive filaments between the top and bottom electrodes. (b) Anion-based devices: During electroforming, the soft-breakdown leads to O<sup>2</sup><sup>−</sup> ions (oxygen vacancies V), and the oxygen vacancies* 

 *migrate toward the counter* 

Various properties of memristor synapses that affect the performance of neuromorphic computing need to be discussed in detail. Among them, representative characteristics such as the linearity in weight update, multilevel states, dynamic range (ON/OFF ratio), variation, retention, endurance, and footprint will be addressed in this section as they can substantially affect computing achievements [8, 35]. The linearity of the weight update indicates the linear relationship between synaptic weight change (∆w) and programming pulse. In other words, the conductance of the memristor synapse changes linearly in accordance with the number of programming pulses, which is associated with the mapping of weight in the algorithms for conductance in memristor synapses. Hence, the linearity of weight update affects the performance (e.g., accuracy). Notably, most memristor synapses

necessary for a deeper understanding of the switching mechanism.

*(a) Cation-based devices: Through electrochemical reaction, metal cations M+*

*form conductive filaments between the top and bottom electrodes.*

**2.4 Desirable properties of memristor synapses**

**16**

**Figure 2.**

*(a, b) Nonlinearity of weight update. Current abruptly changes in initial pulses and gradually saturates. Most memristors exhibit a nonlinear relationship. All figures are reproduced with permission from Ref [39, 10], respectively. Copyright (2017, 2010) American Chemical Society.*

show a nonlinear weight update, where the conductance change gradually saturates, as shown in **Figure 3**. Hence, the nonlinearity of weight update should be improved to achieve highly efficient computing.

The resolution capability of storage is influenced by multilevel states and dynamic ranges because numerous conductance states can distinguishably store individual pixels of input patterns. Moreover, variations, including cycle-to-cycle and device-to-device variations, could degrade neuromorphic computing, particularly in large-scale systems. However, considering that neuromorphic computing exhibits the fault-tolerant property, neuromorphic architectures could be immune to the variation to some extent, and this is supported by several papers [8, 35, 52]. In addition, memristor synapses are repeatedly updated during the training process and should retain the trained weights (i.e., final conductance). Subsequently, the larger the endurance cycles and retention time, the better are the achievements of the neuromorphic network. Last but not least, it is desirable that device's footprint is below sub-10 nm because high density leads to more synaptic devices that store learned information under a specific area [8].

Furthermore, it is efficient to improve the characteristics of memristor synapses depending on individual neuromorphic networks, because a desirable memristor synapse capable of being employed into neuromorphic systems is yet to be reported. Supervised learning-based networks [35, 40–44], for example, are less vulnerable to cycle-to-cycle and device-to-device variations. This is because memristor synapses are updated according to calculated errors under known target values. By contrast, the networks based on unsupervised learning [39, 45–47] are directly affected by the variation owing to unknown target values. Therefore, memristor synapses need to be designed or selected depending on individual neuromorphic networks.

#### **3. Artificial synapses in terms of device architecture and novel functional materials**

Memristors for synaptic devices with two-terminal (e.g., vertical/planar-type and gap-type) and three-terminal (e.g., field-effect transistor and lateral coupling type) structures are manufactured by well-established processing technologies [7–12, 35, 39–55].

In the case of a two-terminal structure, when different voltages are applied to each of the two electrodes, resulting in current flow through the insulator, varying the conductance of the device enables emulation of biological synapse functions such as synapse plasticity [10–12, 16, 35, 48]. In particular, the crossbar array of

two-terminal devices has received attention because of its characteristics relevant to synaptic devices, such as scalability for high density, simple fabrication process, low cost of fabrication, parallel connection structure, low power, fault-tolerance, and compactness. Thus, they are expected to provide an appropriate structure to support synaptic electronics. The type of two-terminal memristors that are being reffered to as the artificial synapses includes resistive random-access memory, phase change memory, conductive bridge memory, and spin-based memory. Although two-terminal devices are attracting much attention because of their ease of implementation of crossbar arrays, a two-terminal device, as a matter of fact, requires a select device to eliminate the sneak path that occurs in a crossbar array configuration. Additionally, it is difficult to imitate complex synaptic functions such as hetero-synaptic plasticity (e.g., modulatory input-dependent plasticity).

Three-terminal structures (e.g., field effect transistor memory and floating/gate transistor memory) with tunable conductance of channels between the source and the drain are also considered as synaptic devices [49–51]. The gate electrode acts as the pre-synapse, transferring the stimulus to the insulating layer, indicating the cleft of the synapse, and modulates the conductance of the channel representing the synaptic strength. Although the three-terminal structure is more complicated than the two-terminal structure and is disadvantageous in terms of density, the terminal for the signal transmission process and the learning terminal are separated such that simultaneous signal processing is possible, and complex synapse functions such as hetero-synaptic plasticity can be mimicked. Moreover, they do not require an additional selector device to reduce sneak current in an integrated array architecture.

Recently, going beyond simply implementing a synapse function, researchers have demonstrated advanced concepts of synapse device functions, including selfrectification, photo-assisted synaptic plasticity and neuromodulation to achieve more delicate imitation of the human brain and learning-and energy-efficiency in neurocomputing.

In [35], Choi et al. fabricated a self-rectifying memristor synapse through a twoterminal structure (Pt/TaOy/nanoporous TaOx/Ta), which is capable of suppressing unwanted leakage pathways and then a 16 x 16 crossbar array using only the devices without an additional selector (see **Figure 4a** and **b**). The mechanism of memristive switching and synaptic functions, including long-term potentiation (LTP), STDP (spike-timing dependent plasticity), and long-term depression (LTD) were caused by the migration of O2<sup>−</sup> ions with oxygen vacancies V by applied electric field in the TaOx. In addition, the asymmetric interface contacts of Pt/TaOy and TaOx/Ta prevent the undesired signal by performing the self-rectification function without the selector.

In [51], Huh et al. reported a synapse device that performs the neuromodulator function of a barristor structure using 2D material as shown in **Figure 4c**. The three-terminal device consisted of a vertically integrated monolithic tungsten oxide memristor, and a variable-barrier tungsten selenide/graphene Schottky diode, termed as a "synaptic barrister." This synaptic barristor could implement fundamental synaptic functions, including short-term plasticity (STP), paired pulse facilitation (PPF), LTP, and LTD, with external gate controllability, termed as a neuromodulator in bio-synapse. This architecture potentially offers considerable power-saving benefits while significantly tuning the synaptic weights and intrinsically modifying the synaptic plasticity, in comparison with conventional two-neuronal-based synaptic architectures.

In [52], Ham et al. fabricated an organo-lead halide perovskite (OHP)-based photonic synapse in which the synaptic plasticity is modified by both electrical pulses and light illumination. The switching mechanism originates from the presence of a conductive filament by iodine-vacancy mediator, with its switching states controlled by electric-field domination (see **Figure 4d**). Using diverse electrical stimuli and

**19**

**Figure 4.**

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

relative timing between the input pulses, essential synaptic functionalities such as STP, LTP, and LTD were successfully demonstrated. In addition, owing to the accelerated migration of the iodine vacancy inherently existing in the coated OHP film under light illumination, the OHP synaptic device exhibits light-tunable synaptic functionalities with very low programming inputs (≈0.1 V) as shown in **Figure 4d**. The ability of high-order tuning of the photo-assisted synaptic plasticity in an artificial synapse can offer significant improvements in the processing time, low-power recognition,

*(c and d) are reproduced with permission from Ref [52]. Copyright (2018) John Wiley and Sons.*

*(a) Schematic of a self-rectifying memristor with a Pt/TaOy/nanoporous TaOx/Ta and cross-sectional image of a memristor synapse. (b) I-V curves of the self-rectifying memristor synapse. (a, b) are reproduced with permission from Ref [35] under a Creative Commons Attribution 4.0 International License. (c) Schematics of the suggested mechanism of how a conductive switching filament is formed by the iodine vacancy migration in the presence of light. (d) Synaptic potentiation and depression behavior of the OHP-based synaptic device.* 

and learning capability in a neuro-inspired computing system (**Figure 4e**). In [12], Wang et al. designed a diffusive memristor for STP synapses and threshold neurons. The devices contain a switching layer doped with Ag nanoclusters (MgOx:Ag, SiOxNy:Ag, and HfOx:Ag) using the co-sputtering method. The switching mechanism is based on the growth and relaxation of Ag nanoclusters depending on whether the voltage pulse is applied, which was experimentally verified by in-situ high-resolution transmission electron microscopy (HRTEM). The designed device mimicked STP under PPF and PPD. Moreover, the device was used as a threshold neuron along with drift memristor synapse based on TaOx to emulate STDP learning rule. Because the conductance of the device gradually increases according to applied voltage and then abruptly decreases under no applied voltage, the device can be used as a threshold neuron. The results give a potential application for simple artificial neurons as compared with CMOS artificial neurons [53, 54].

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

#### **Figure 4.**

*Memristors - Circuits and Applications of Memristor Devices*

(e.g., modulatory input-dependent plasticity).

two-neuronal-based synaptic architectures.

two-terminal devices has received attention because of its characteristics relevant to synaptic devices, such as scalability for high density, simple fabrication process, low cost of fabrication, parallel connection structure, low power, fault-tolerance, and compactness. Thus, they are expected to provide an appropriate structure to support synaptic electronics. The type of two-terminal memristors that are being reffered to as the artificial synapses includes resistive random-access memory, phase change memory, conductive bridge memory, and spin-based memory. Although two-terminal devices are attracting much attention because of their ease of implementation of crossbar arrays, a two-terminal device, as a matter of fact, requires a select device to eliminate the sneak path that occurs in a crossbar array configuration. Additionally, it is difficult to imitate complex synaptic functions such as hetero-synaptic plasticity

Three-terminal structures (e.g., field effect transistor memory and floating/gate transistor memory) with tunable conductance of channels between the source and the drain are also considered as synaptic devices [49–51]. The gate electrode acts as the pre-synapse, transferring the stimulus to the insulating layer, indicating the cleft of the synapse, and modulates the conductance of the channel representing the synaptic strength. Although the three-terminal structure is more complicated than the two-terminal structure and is disadvantageous in terms of density, the terminal for the signal transmission process and the learning terminal are separated such that simultaneous signal processing is possible, and complex synapse functions such as hetero-synaptic plasticity can be mimicked. Moreover, they do not require an additional selector device to reduce sneak current in an integrated array architecture. Recently, going beyond simply implementing a synapse function, researchers have demonstrated advanced concepts of synapse device functions, including selfrectification, photo-assisted synaptic plasticity and neuromodulation to achieve more delicate imitation of the human brain and learning-and energy-efficiency in

In [35], Choi et al. fabricated a self-rectifying memristor synapse through a twoterminal structure (Pt/TaOy/nanoporous TaOx/Ta), which is capable of suppressing unwanted leakage pathways and then a 16 x 16 crossbar array using only the devices without an additional selector (see **Figure 4a** and **b**). The mechanism of memristive switching and synaptic functions, including long-term potentiation (LTP), STDP (spike-timing dependent plasticity), and long-term depression (LTD) were caused by the migration of O2<sup>−</sup> ions with oxygen vacancies V by applied electric field in the TaOx. In addition, the asymmetric interface contacts of Pt/TaOy and TaOx/Ta prevent the undesired signal by performing the self-rectification function without the selector. In [51], Huh et al. reported a synapse device that performs the neuromodulator function of a barristor structure using 2D material as shown in **Figure 4c**. The three-terminal device consisted of a vertically integrated monolithic tungsten oxide memristor, and a variable-barrier tungsten selenide/graphene Schottky diode, termed as a "synaptic barrister." This synaptic barristor could implement fundamental synaptic functions, including short-term plasticity (STP), paired pulse facilitation (PPF), LTP, and LTD, with external gate controllability, termed as a neuromodulator in bio-synapse. This architecture potentially offers considerable power-saving benefits while significantly tuning the synaptic weights and intrinsically modifying the synaptic plasticity, in comparison with conventional

In [52], Ham et al. fabricated an organo-lead halide perovskite (OHP)-based photonic synapse in which the synaptic plasticity is modified by both electrical pulses and light illumination. The switching mechanism originates from the presence of a conductive filament by iodine-vacancy mediator, with its switching states controlled by electric-field domination (see **Figure 4d**). Using diverse electrical stimuli and

**18**

neurocomputing.

*(a) Schematic of a self-rectifying memristor with a Pt/TaOy/nanoporous TaOx/Ta and cross-sectional image of a memristor synapse. (b) I-V curves of the self-rectifying memristor synapse. (a, b) are reproduced with permission from Ref [35] under a Creative Commons Attribution 4.0 International License. (c) Schematics of the suggested mechanism of how a conductive switching filament is formed by the iodine vacancy migration in the presence of light. (d) Synaptic potentiation and depression behavior of the OHP-based synaptic device. (c and d) are reproduced with permission from Ref [52]. Copyright (2018) John Wiley and Sons.*

relative timing between the input pulses, essential synaptic functionalities such as STP, LTP, and LTD were successfully demonstrated. In addition, owing to the accelerated migration of the iodine vacancy inherently existing in the coated OHP film under light illumination, the OHP synaptic device exhibits light-tunable synaptic functionalities with very low programming inputs (≈0.1 V) as shown in **Figure 4d**. The ability of high-order tuning of the photo-assisted synaptic plasticity in an artificial synapse can offer significant improvements in the processing time, low-power recognition, and learning capability in a neuro-inspired computing system (**Figure 4e**).

In [12], Wang et al. designed a diffusive memristor for STP synapses and threshold neurons. The devices contain a switching layer doped with Ag nanoclusters (MgOx:Ag, SiOxNy:Ag, and HfOx:Ag) using the co-sputtering method. The switching mechanism is based on the growth and relaxation of Ag nanoclusters depending on whether the voltage pulse is applied, which was experimentally verified by in-situ high-resolution transmission electron microscopy (HRTEM). The designed device mimicked STP under PPF and PPD. Moreover, the device was used as a threshold neuron along with drift memristor synapse based on TaOx to emulate STDP learning rule. Because the conductance of the device gradually increases according to applied voltage and then abruptly decreases under no applied voltage, the device can be used as a threshold neuron. The results give a potential application for simple artificial neurons as compared with CMOS artificial neurons [53, 54].

#### **4. Neuromorphic systems based on crossbar array of memristor synapses**

Prezioso et al. experimentally demonstrated neuromorphic networks based on memristor synapses (see [55]). In their paper, Al2O3/TiO2−x memristor was used to fabricate a 12 × 12 crossbar array to implement a single-layer network [56]. The single-layer network architecture was schematically described as shown in **Figure 5a**, where 10 input neurons and 3 output neurons are fully linked by 10 × 3 = 30 synaptic weights (*Wi,j*). Notably, this ANN architecture naturally corresponds to a crossbar array [9, 35]. Input voltages (*Vi = 1…9*) assigned from pixels of the 3 × 3 input images (see **Figure 5b**) were applied to each input neuron. After being applied into the network, the input voltages were individually weighted depending on each synaptic weight. Note that *V10* is a bias voltage to control the degree of activation of the output neurons. The output neurons received each weighted voltage through linked weights and then integrated the weighted voltages (∑*Wi,jVj*), where *j* and *i* represent the input (*j* = 1–9) and output (*i* = 1–3) neurons respectively. The output neurons converted each integrated voltage into output (*fi*) ranging from −1 to 1 according to the nonlinear activation function: *fi* = tanh(*βIi*), where *β* adjusts the nonlinearity of the activation function and *Ii* = ∑*Wi,jVj*. The activation function can be considered as the threshold firing function in a biological neuron. The synaptic weights were represented by a pair of adjacent memristors (*Wi,j* = *Gi,j <sup>+</sup>* − *Gi,j* <sup>−</sup>) for the effectiveness of weight update. The number of selected memristor synapses in 12 × 12 array were 30 × 2 = 60, due to a pair of memristors (**Figure 5c**). When the network was under the training process, as shown in **Figure 5d** and **e**, memristor synapses between input and output neurons were updated based on the Manhattan update rule, which is classified as supervised learning: ∆*Wi,j* = *η*sgn∑[(*ti*(n) − *fi*(n)) × d*f*/d*I* × *Vj*(n)],

#### **Figure 5.**

*(a) Input voltages corresponding to an input image (Vi = 1…9) and a bias voltage (V10). These voltages are fed into the single-layer network where 10 input neurons and 3 output neurons are linked by synaptic weights. (b) The "z," "v," and "n" input images. Aside from ideal images, other images contain one noise pixel. (c) The schematic of implemented 10 × 6 crossbar array, a pair of adjacent memristors provide one synaptic weight. (d) When an image (e.g., "z") is fed into network, pixels for black give VR (read voltage) to the network, otherwise, −VR is applied into the network. (e) An instance of weight update according to Manhattan update rule. The synaptic weights corresponding to sign + should be increased, so that the memristors representing G1,1<sup>+</sup> , G1,2<sup>+</sup> , G1,5<sup>+</sup> , G1,6<sup>+</sup> , and G1,9<sup>+</sup> are applied by set voltage. All figures are reproduced with permission from Ref [55]. Copyright (2015) Springer Nature.*

**21**

**Figure 6.**

*Copyright (2017) American Chemical Society.*

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

demonstration using crossbar arrays.

[∑*(Gi,j*

where *η* is the learning rate, *ti*(n) is the target value, *fi*(n) is the output value, and n is the nth input image. After the training process was complete, the memristor synapses retained their final conductance, and the test process was performed without weight update (see **Figure 5d**). From the test process, the neuromorphic network exhibited perfect classification for the first time in 21 epochs (note that one epoch indicates one training process). Although simple and few input images were used to train/test the neuromorphic network, this work greatly contributed to neuromorphic systems based on memristor synapses in terms of experimental

It should be noted that the circuit that acquires sgn[ *fi*(n)] = sgn[∑*Wi,jVj*] *=* sgn

tial amplifier [43, 57]. Then, the output value is compared with the target value by circuits using a comparator. According to calculated ∆Wi,j, programming memristors of the array, for example, could be performed as shown in **Figure 6** [39]. The test board contains four digital-to-analog converters (DACs) providing voltage pulses through the DACs. The DACs 1–4 represent the chosen bottom line, the unchosen bottom line, the chosen top line, and the unchosen top line, respectively. Using matrix switches (Switch 1 and 2), individual memristor is assigned to the corresponding DAC. The multiplexer (MUX) is operated to obtain currents that flow through memristors in the array by delivering the currents into the analog-to-digital converter (ADC). The ADC obtains the applied voltage of the resistor (1 kΩ), and the voltage is changed into the current. The arrows of **Figure 6** represent the current flowing through a chosen memristor in case of write, erase, and read processes. Notably, there are non-idealities such as sneak currents and wire resistance in array-level, which could degrade the performance of neuromorphic computing [35, 44, 58–60]. The sneak currents affect learning accuracy and epochs because of undesired information, especially large-scale array. In **Figure 6**, in order to avoid sneak currents during read process, unchosen rows and columns are grounded [39]. Moreover, wire resistance consumes input voltages, so that memristors far from points of input voltage could be applied by smaller voltage than input voltage.

*Circuit scheme for write, erase, and read processes. The figure is reproduced with permission from Ref [39].* 

*<sup>+</sup>* − *Gi,j*)*Vj*] could be implemented by a virtual ground circuit and a differen-

#### *Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

*Memristors - Circuits and Applications of Memristor Devices*

**synapses**

of adjacent memristors (*Wi,j* = *Gi,j*

**4. Neuromorphic systems based on crossbar array of memristor** 

*<sup>+</sup>* − *Gi,j*

The number of selected memristor synapses in 12 × 12 array were 30 × 2 = 60, due to a pair of memristors (**Figure 5c**). When the network was under the training process, as shown in **Figure 5d** and **e**, memristor synapses between input and output neurons were updated based on the Manhattan update rule, which is classified as supervised learning: ∆*Wi,j* = *η*sgn∑[(*ti*(n) − *fi*(n)) × d*f*/d*I* × *Vj*(n)],

*(a) Input voltages corresponding to an input image (Vi = 1…9) and a bias voltage (V10). These voltages are fed into the single-layer network where 10 input neurons and 3 output neurons are linked by synaptic weights. (b) The "z," "v," and "n" input images. Aside from ideal images, other images contain one noise pixel. (c) The schematic of implemented 10 × 6 crossbar array, a pair of adjacent memristors provide one synaptic weight. (d) When an image (e.g., "z") is fed into network, pixels for black give VR (read voltage) to the network, otherwise, −VR is applied into the network. (e) An instance of weight update according to Manhattan update rule. The synaptic weights corresponding to sign + should be increased, so that* 

*, and G1,9<sup>+</sup>*

<sup>−</sup>) for the effectiveness of weight update.

 *are applied by set voltage. All figures are* 

Prezioso et al. experimentally demonstrated neuromorphic networks based on memristor synapses (see [55]). In their paper, Al2O3/TiO2−x memristor was used to fabricate a 12 × 12 crossbar array to implement a single-layer network [56]. The single-layer network architecture was schematically described as shown in **Figure 5a**, where 10 input neurons and 3 output neurons are fully linked by 10 × 3 = 30 synaptic weights (*Wi,j*). Notably, this ANN architecture naturally corresponds to a crossbar array [9, 35]. Input voltages (*Vi = 1…9*) assigned from pixels of the 3 × 3 input images (see **Figure 5b**) were applied to each input neuron. After being applied into the network, the input voltages were individually weighted depending on each synaptic weight. Note that *V10* is a bias voltage to control the degree of activation of the output neurons. The output neurons received each weighted voltage through linked weights and then integrated the weighted voltages (∑*Wi,jVj*), where *j* and *i* represent the input (*j* = 1–9) and output (*i* = 1–3) neurons respectively. The output neurons converted each integrated voltage into output (*fi*) ranging from −1 to 1 according to the nonlinear activation function: *fi* = tanh(*βIi*), where *β* adjusts the nonlinearity of the activation function and *Ii* = ∑*Wi,jVj*. The activation function can be considered as the threshold firing function in a biological neuron. The synaptic weights were represented by a pair

**20**

**Figure 5.**

*the memristors representing G1,1<sup>+</sup>*

*, G1,2<sup>+</sup> , G1,5<sup>+</sup> , G1,6<sup>+</sup>*

*reproduced with permission from Ref [55]. Copyright (2015) Springer Nature.*

where *η* is the learning rate, *ti*(n) is the target value, *fi*(n) is the output value, and n is the nth input image. After the training process was complete, the memristor synapses retained their final conductance, and the test process was performed without weight update (see **Figure 5d**). From the test process, the neuromorphic network exhibited perfect classification for the first time in 21 epochs (note that one epoch indicates one training process). Although simple and few input images were used to train/test the neuromorphic network, this work greatly contributed to neuromorphic systems based on memristor synapses in terms of experimental demonstration using crossbar arrays.

It should be noted that the circuit that acquires sgn[ *fi*(n)] = sgn[∑*Wi,jVj*] *=* sgn [∑*(Gi,j <sup>+</sup>* − *Gi,j*)*Vj*] could be implemented by a virtual ground circuit and a differential amplifier [43, 57]. Then, the output value is compared with the target value by circuits using a comparator. According to calculated ∆Wi,j, programming memristors of the array, for example, could be performed as shown in **Figure 6** [39]. The test board contains four digital-to-analog converters (DACs) providing voltage pulses through the DACs. The DACs 1–4 represent the chosen bottom line, the unchosen bottom line, the chosen top line, and the unchosen top line, respectively. Using matrix switches (Switch 1 and 2), individual memristor is assigned to the corresponding DAC. The multiplexer (MUX) is operated to obtain currents that flow through memristors in the array by delivering the currents into the analog-to-digital converter (ADC). The ADC obtains the applied voltage of the resistor (1 kΩ), and the voltage is changed into the current. The arrows of **Figure 6** represent the current flowing through a chosen memristor in case of write, erase, and read processes. Notably, there are non-idealities such as sneak currents and wire resistance in array-level, which could degrade the performance of neuromorphic computing [35, 44, 58–60]. The sneak currents affect learning accuracy and epochs because of undesired information, especially large-scale array. In **Figure 6**, in order to avoid sneak currents during read process, unchosen rows and columns are grounded [39]. Moreover, wire resistance consumes input voltages, so that memristors far from points of input voltage could be applied by smaller voltage than input voltage.

#### **Figure 6.**

*Circuit scheme for write, erase, and read processes. The figure is reproduced with permission from Ref [39]. Copyright (2017) American Chemical Society.*

This influences output currents, leading to degradation of learning performance. The non-idealities in array-level could be overcome by device functions [35, 44], operational scheme [39, 58–60], or learning algorithms [35, 40–44] to some degree.

#### **5. Conclusion**

Neuromorphic systems are one of the most promising candidates to deal with the von Neumann bottleneck caused by the memory wall between memory and process units. Using memristor synapses simply classified into cation- and anionbased devices can resolve this bottleneck owing to their storage and transmittance capabilities. To obtain higher performance of neuromorphic systems, representative characteristics, including the linearity of weight update, large multilevel states and dynamic range (ON/OFF ratio), variation and endurance, and retention need to be improved. In this context, different memristor synapses based on novel materials and device structures were introduced. Finally, we have briefly explained neuromorphic networks based on crossbar arrays of memristor synapses, and the network demonstrated perfect classification after 21 epochs. We believe that this chapter offers a deep understanding of the field of memristor synapses.

#### **Acknowledgements**

This work was supported by the National Research Foundation of Korea (NRF-2016R1C1B2007330 and NRF-2019R1A2C2003704), KU-KIST Research Fund, Samsung Electronics, and a Korea University Future Research Grant.

#### **Conflict of interest**

The authors declare no competing interests.

#### **Author details**

Sanghyeon Choi, Seonggil Ham and Gunuk Wang\* KU-KIST Graduate School of Converging Science and Technology, Korea University, Seoul, Republic of Korea

\*Address all correspondence to: gunukwang@korea.ac.kr

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

**23**

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

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[12] Wang Z, Joshi S, Savel'ev SE, Jiang H, Midya R, Lin P, et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nature Materials. 2017;**16**:101. DOI:

Nanotechnology. 2011;**22**:485203. DOI: 10.1088/0957-4484/22/48/485203

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10.1109/LED.2016.2530942

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nmat3070

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[2] Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP. Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE. 2001;**89**:259-288. DOI:

[3] International Technology Roadmap for Semiconductors 2.0 (ITRS). Beyond CMOS [Internet]. 2015. Available from: http://www.itrs2.net/ [Accessed:

[4] Backus J. Can Programming be Liberated from the von Neumann Style?: A Functional Style and its Algebra of Programs. Pennsylvania Plaza, New York: ACM; 2007. DOI:

[5] Sally A. Reflections on the memory wall. In: Conference on Computing Frontiers; 14-16 April 2004; Italy. New York: ACM; 2004. p. 162

10.1145/1283920.1283933

[6] Mead C. Neuromorphic

10.1109/5.58356

2013;**24**:382001. DOI:

electronic systems. Proceedings of the IEEE. 1990;**78**:1629-1636. DOI:

[7] Kuzum D, Yu S, Wong HP. Synaptic electronics: Materials, devices and applications. Nanotechnology.

10.1088/0957-4484/24/38/382001

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s41928-017-0006-8

**References**

10.1126/science.1079567

10.1109/5.915374

January 29, 2019]

*Memristor Synapses for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.85301*

#### **References**

*Memristors - Circuits and Applications of Memristor Devices*

This influences output currents, leading to degradation of learning performance. The non-idealities in array-level could be overcome by device functions [35, 44], operational scheme [39, 58–60], or learning algorithms [35, 40–44] to some degree.

Neuromorphic systems are one of the most promising candidates to deal with the von Neumann bottleneck caused by the memory wall between memory and process units. Using memristor synapses simply classified into cation- and anionbased devices can resolve this bottleneck owing to their storage and transmittance capabilities. To obtain higher performance of neuromorphic systems, representative characteristics, including the linearity of weight update, large multilevel states and dynamic range (ON/OFF ratio), variation and endurance, and retention need to be improved. In this context, different memristor synapses based on novel materials and device structures were introduced. Finally, we have briefly explained neuromorphic networks based on crossbar arrays of memristor synapses, and the network demonstrated perfect classification after 21 epochs. We believe that this

This work was supported by the National Research Foundation of Korea (NRF-2016R1C1B2007330 and NRF-2019R1A2C2003704), KU-KIST Research Fund,

chapter offers a deep understanding of the field of memristor synapses.

Samsung Electronics, and a Korea University Future Research Grant.

**22**

**Author details**

**5. Conclusion**

**Acknowledgements**

**Conflict of interest**

provided the original work is properly cited.

University, Seoul, Republic of Korea

Sanghyeon Choi, Seonggil Ham and Gunuk Wang\*

The authors declare no competing interests.

\*Address all correspondence to: gunukwang@korea.ac.kr

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

KU-KIST Graduate School of Converging Science and Technology, Korea

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**24**

*Memristors - Circuits and Applications of Memristor Devices*

underlie memory formation. Science. 2018;**360**:430-435. DOI: 10.1126/

[26] Whitlock JR, Heynen AJ, Shuler MG, Bear MF. Learning induces longterm potentiation in the hippocampus. Science. 2006;**313**:1093-1097. DOI:

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[28] Prakash A, Jana D, Maikap S. TaOxbased resistive switching memories: Prospective and challenges. Nanoscale Research Letters. 2013;**8**:418. DOI:

[29] Sun H, Liu Q, Li C, Long S, Lv H, Bi C, et al. Direct observation of

[30] Liu Q, Long S, Lv H, Wang W, Niu J, Huo Z, et al. Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode. ACS Nano. 2010;**4**:6162-6168.

conversion between threshold switching and memory switching induced by conductive filament morphology. Advanced Functional Materials. 2014;**24**:5679-5686. DOI: 10.1002/

science.aas9204

10.1126/science.1128134

10.1063/1.3294625

adfm.201401304

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10.1038/ncomms5232

adfm.201001520

[31] Yang Y, Gao P, Li L, Pan X, Tappertzhofen S, Choi S, et al.

[32] Wu S, Tsuruoka T, Terabe K, Hasegawa T, Hill JP, Ariga K, et al. A polymer-electrolyte-based atomic switch. Advanced Functional

Electrochemical dynamics of nanoscale metallic inclusions in dielectrics. Nature Communications. 2014;**5**:4232. DOI:

Materials. 2011;**21**:93-99. DOI: 10.1002/

10.1186/1556-276X-8-418

Nature Nanotechnology. 2013;**8**:13. DOI:

[18] Von Neumann J. The principles of large-scale computing machines. IEEE Annals of the History of Computing. 1988;**10**:243-256. DOI: 10.1109/

[19] LeCun Y, Bengio Y, Hinton G. Deep

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[21] Russakovsky O, Deng J, Su H, Krause J, Satheesh S, Ma S, et al. Imagenet large scale visual recognition challenge. International Journal of Computer Vision. 2015;**115**:211-252. DOI: 10.1007/s11263-015-0816-y

[22] Collobert R, Weston J. A unified architecture for natural language processing: Deep neural networks with multitask learning. In: Proceedings of the 25th International Conference on Machine learning; 05-09 July 2008; Helsinki, Finland. New York, ACM;

[23] Hinton G, Deng L, Yu D, Dahl GE, Mohamed AR, Jaitly N, et al. Deep neural networks for acoustic modeling in speech recognition: The shared views of four research groups. IEEE Signal Processing Magazine. 2012;**29**:82-97. DOI: 10.1109/MSP.2012.2205597

[24] Silver D, Huang A, Maddison CJ, Guez A, Sifre L, Van Den Driessche G, et al. Mastering the game of go with deep neural networks and tree search. Nature. 2016;**529**:484. DOI: 10.1038/nature16961

[25] Choi J-H, Sim S-E, Kim J-I, Choi DI, Oh J, Ye S, et al. Interregional synaptic maps among engram cells

learning. Nature. 2015;**521**:436

10.1038/nnano.2012.240

MAHC.1981.10025

DOI: 10.1145/3065386

2008. pp. 160-167

2017;**11**:2814-2822. DOI: 10.1021/ acsnano.6b07894

[47] Jeong Y, Lee J, Moon J, Shin JH, Lu WD. K-means data clustering with memristor networks. Nano Letters. 2018;**18**:4447-4453. DOI: 10.1021/acs. nanolett.8b01526

[48] Wang L, Wang Z, Zhao W, Hu B, Xie L, Yi M, et al. Controllable multiple depression in a graphene oxide artificial synapse. Advanced Electronic Materials. 2017;**3**:1600244. DOI: 10.1002/ aelm.201600244

[49] Yang CS, Shang DS, Liu N, Shi G, Shen X, Yu RC, et al. A synaptic transistor based on quasi-2D molybdenum oxide. Advanced Materials. 2017;**29**:1700906. DOI: 10.1002/adma.201700906

[50] Zhu LQ, Wan CJ, Guo LQ, Shi Y, Wan Q. Artificial synapse network on inorganic proton conductor for neuromorphic systems. Nature Communications. 2014;**5**:3158. DOI: 10.1038/ncomms4158

[51] Huh W, Jang S, Lee JY, Lee D, Lee D, Lee JM, et al. Synaptic barristor based on phase-engineered 2D heterostructures. Advanced Materials. 2018;**30**:1801447. DOI: 10.1002/ adma.201801447

[52] Ham S, Choi S, Cho H, Na SI, Wang G. Photonic organolead halide Perovskite artificial synapse capable of accelerated learning at low power inspired by dopamine-facilitated synaptic activity. Advanced Functional Materials. 2019;**29**:1806646. DOI: 10.1002/adfm.201806646

[53] Payvand M, Rofeh J, Sodhi A, Theogarajan L. A CMOS-memristive self-learning neural network for pattern classification applications. In: Proceedings 2014 IEEE/ACM International Symposium on Nanoscale Architectures; 8-10 July 2014; France.

Paris: ACM; 2014. pp. 92-97. DOI: 10.1109/NANOARCH.2014.6880486 **Chapter 3**

Behavior

*and Kamel Besbes*

**Abstract**

and simplicity.

**1. Introduction**

**27**

Coexistence of Bipolar and

Unipolar Memristor Switching

*Sami Ghedira, Faten Ouaja Rziga, Khaoula Mbarek*

electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical

The memristor has been theoretically investigated as one of the fundamental

characteristics are not yet fully understood. The nonlinear characteristics and the ability to examine large-scale amounts of storing data of this device reveal an interesting development in emerging electronic systems. Research on memristor modeling based on SPICE tools has grown rapidly. This leads us to study the behavior of such devices. Our aim is to simulate different types of memristor behavior. The adjustment of the model is based on the implementation of several parameters, which enables the switching of this device. In this chapter, we prove the flexibility and the correlation of memristor model with different memristive characterization data, by applying different voltage bias, sinusoidal and with a repetitive sweeping. Moreover, we demonstrate the memristor behavior as four types of switching. This includes bipolar switching, unipolar switching, bipolar switching with forgetting effect, and a reversible process between bipolar and unipolar switching. In order to validate this study, we compare our simulation results with experimental data and we prove a good agreement. The SPICE model used in our simulations shows a special advantage for its flexibility

**Keywords:** memristor, I-V characteristics, SPICE model, switching behavior,

Significant interest has been focused on the development of memristor-based systems. It has been first developed on symmetry consideration by Prof. Leon Chua in 1971 [1, 2]. In addition, it has been admitted physically by the HP Labs Team in 2008 [3]. This device does have a great potential to be the future memory cell, due to the small feature size and ability to retain the content (nonvolatile). The identity of such device is obvious on the *I-V* characteristics, i.e., its "pinched hysteresis loop." Thus, the choice of the model and the structure are necessary to achieve

hysteresis loop, bipolar behavior, unipolar behavior

[54] Ebong IE, Mazumder P. CMOS and memristor-based neural network design for position detection. Proceedings of the IEEE. 2012;**100**:2050-2060. DOI: 10.1109/JPROC.2011.2173089

[55] Prezioso M, Merrikh-Bayat F, Hoskins B, Adam G, Likharev KK, Strukov DB. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature. 2015;**521**:61. DOI: 10.1038/ nature14441

[56] Hertz J, Krogh A, Palmer RG, editors. Introduction to the Theory of Neural Computation. Florida: CRC Press; 1991. DOI: 10.1119/1.17491

[57] Alibart F, Gao L, Hoskins BD, Strukov DB. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology. 2012;**23**:075201. DOI: 10.1088/0957-4484/23/7/075201

[58] Liu B, Li H, Chen Y, Li X, Huang T, Wu Q, et al. Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. In: Proceedings 2014 IEEE/ ACM International Conference on Computer-Aided Design. IEEE Press; 2014. pp. 63-70. DOI: 10.1109/ ICCAD.2014.7001330

[59] Mittal S. A Survey of ReRAM-based architectures for processing-in-memory and neural networks. Machine Learning and Knowledge Extraction. 2018;**1**: 75-114. DOI: 10.3390/make1010005

[60] Li Y, Wang Z, Midya R, Xia Q, Yang JJ. Review of memristor devices in neuromorphic computing: materials sciences and device challenges. Journal of Physics D: Applied Physics. 2018;**51**:503002. DOI: 10.1088/1361-6463/aade3f

#### **Chapter 3**

*Memristors - Circuits and Applications of Memristor Devices*

Paris: ACM; 2014. pp. 92-97. DOI: 10.1109/NANOARCH.2014.6880486

10.1109/JPROC.2011.2173089

nature14441

[55] Prezioso M, Merrikh-Bayat F, Hoskins B, Adam G, Likharev KK, Strukov DB. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature. 2015;**521**:61. DOI: 10.1038/

[56] Hertz J, Krogh A, Palmer RG, editors. Introduction to the Theory of Neural Computation. Florida: CRC Press; 1991. DOI: 10.1119/1.17491

[57] Alibart F, Gao L, Hoskins BD, Strukov DB. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology. 2012;**23**:075201. DOI: 10.1088/0957-4484/23/7/075201

[58] Liu B, Li H, Chen Y, Li X, Huang T, Wu Q, et al. Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. In: Proceedings 2014 IEEE/ ACM International Conference on Computer-Aided Design. IEEE Press; 2014. pp. 63-70. DOI: 10.1109/

[59] Mittal S. A Survey of ReRAM-based architectures for processing-in-memory and neural networks. Machine Learning and Knowledge Extraction. 2018;**1**: 75-114. DOI: 10.3390/make1010005

[60] Li Y, Wang Z, Midya R, Xia Q, Yang JJ. Review of memristor devices in neuromorphic computing:

materials sciences and device challenges. Journal of Physics D: Applied Physics. 2018;**51**:503002. DOI:

10.1088/1361-6463/aade3f

ICCAD.2014.7001330

[54] Ebong IE, Mazumder P. CMOS and memristor-based neural network design for position detection. Proceedings of the IEEE. 2012;**100**:2050-2060. DOI:

2017;**11**:2814-2822. DOI: 10.1021/

[47] Jeong Y, Lee J, Moon J, Shin JH, Lu WD. K-means data clustering with memristor networks. Nano Letters. 2018;**18**:4447-4453. DOI: 10.1021/acs.

[48] Wang L, Wang Z, Zhao W, Hu B, Xie L, Yi M, et al. Controllable multiple depression in a graphene oxide artificial synapse. Advanced Electronic Materials.

2017;**3**:1600244. DOI: 10.1002/

10.1002/adma.201700906

10.1038/ncomms4158

adma.201801447

[49] Yang CS, Shang DS, Liu N, Shi G, Shen X, Yu RC, et al. A synaptic transistor based on quasi-2D molybdenum oxide. Advanced Materials. 2017;**29**:1700906. DOI:

[50] Zhu LQ, Wan CJ, Guo LQ, Shi Y, Wan Q. Artificial synapse network on inorganic proton conductor for neuromorphic systems. Nature Communications. 2014;**5**:3158. DOI:

[51] Huh W, Jang S, Lee JY, Lee D, Lee D, Lee JM, et al. Synaptic barristor based on phase-engineered 2D

heterostructures. Advanced Materials. 2018;**30**:1801447. DOI: 10.1002/

[52] Ham S, Choi S, Cho H, Na SI, Wang G. Photonic organolead halide Perovskite artificial synapse capable of accelerated learning at low power inspired by dopamine-facilitated synaptic activity. Advanced Functional Materials. 2019;**29**:1806646. DOI:

[53] Payvand M, Rofeh J, Sodhi A, Theogarajan L. A CMOS-memristive self-learning neural network for pattern classification applications. In: Proceedings 2014 IEEE/ACM International Symposium on Nanoscale Architectures; 8-10 July 2014; France.

10.1002/adfm.201806646

acsnano.6b07894

nanolett.8b01526

aelm.201600244

**26**

## Coexistence of Bipolar and Unipolar Memristor Switching Behavior

*Sami Ghedira, Faten Ouaja Rziga, Khaoula Mbarek and Kamel Besbes*

#### **Abstract**

The memristor has been theoretically investigated as one of the fundamental electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical characteristics are not yet fully understood. The nonlinear characteristics and the ability to examine large-scale amounts of storing data of this device reveal an interesting development in emerging electronic systems. Research on memristor modeling based on SPICE tools has grown rapidly. This leads us to study the behavior of such devices. Our aim is to simulate different types of memristor behavior. The adjustment of the model is based on the implementation of several parameters, which enables the switching of this device. In this chapter, we prove the flexibility and the correlation of memristor model with different memristive characterization data, by applying different voltage bias, sinusoidal and with a repetitive sweeping. Moreover, we demonstrate the memristor behavior as four types of switching. This includes bipolar switching, unipolar switching, bipolar switching with forgetting effect, and a reversible process between bipolar and unipolar switching. In order to validate this study, we compare our simulation results with experimental data and we prove a good agreement. The SPICE model used in our simulations shows a special advantage for its flexibility and simplicity.

**Keywords:** memristor, I-V characteristics, SPICE model, switching behavior, hysteresis loop, bipolar behavior, unipolar behavior

#### **1. Introduction**

Significant interest has been focused on the development of memristor-based systems. It has been first developed on symmetry consideration by Prof. Leon Chua in 1971 [1, 2]. In addition, it has been admitted physically by the HP Labs Team in 2008 [3]. This device does have a great potential to be the future memory cell, due to the small feature size and ability to retain the content (nonvolatile). The identity of such device is obvious on the *I-V* characteristics, i.e., its "pinched hysteresis loop." Thus, the choice of the model and the structure are necessary to achieve

better endurance and performance. Hence, the correlation of one model to other memristive devices is an interesting development to further research.

electrodes. One of the TiO2 layers of width w is doped with oxygen vacancies. The second, undoped layer of width *w*-*D* has insulating properties. As a result of complex processes in the device, the width w of the doped layer varies by applying a voltage or current to the electrodes of the memristor, and there will be dramatic changes in resistance. Therefore, the boundary, defined as the state variable *x* = *w*/*D*, between the two layers moves simultaneously. The well-known characteristic of the memristor is shown in **Figure 1(b)**, the pinched hysteresis loop, which indicates the switching behavior of memristive devices. An application of a positive bias voltage to the electrodes of the device leads to the switching between Off and On states, and this switching is labeled SET. A RESET switching corresponds to the exchange between On and Off states. As current flows through the device, the cross section between the regions moves. As a result, the doped and the undoped regions have resistance Ron and Roff when each of them reaches the (D-w) and the full-length D, respectively. Also, the width w of the doped region of the memristor increases by applying a positive voltage bias, which causes the total resistance of the device to decrease. The same process is carried out by applying a negative voltage to the opposite side of the device. Moreover, there are two methods of the behavior of resistive switching for memristors: static and dynamic switching.

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

The characteristic of a static switching behavior is obtained with a slow sweep of

In dynamic switching, voltage pulses are applied to the device and the current

A comprehensive mathematical illustration of a SPICE memristor model has been reported in [11], which will be used later on for our simulation results. This model can illustrate the static and dynamic switching behavior, which will be studied in the next section. Thus, this model is based on the assumption that the switching behavior of the memristor is small or fast, below or above a threshold voltage VSET or VRESET, respectively, which is considered as the minimum voltage required to impose a change on the physical structure and thus the memristance of the device. This assumption is encapsulated in the use of the multiple implemented

I tðÞ¼ *<sup>a</sup>*1*x*ð Þ<sup>t</sup> sinh bV t ð Þ ð Þ *, V*ð Þ<sup>t</sup> *<sup>&</sup>gt;* <sup>0</sup>

The relationship between the memristor voltage and the memristor current is given by Eq. (1), and it comprises three main parameters: *a*1, *a*2, and *b*. These parameters are responsible for the modeling of the nonlinear phenomenon of the pinched hysteresis loop. *a*<sup>1</sup> and *a*<sup>2</sup> are the magnitude parameters that vary according to the polarity of the input voltage; it is also related to the thickness of the dielectric layer of the memristor. Meanwhile, *b* is defined as the control parameter, which refers to the amount of oxygen deficiencies presented in the device, and it controls the conductivity of the device. The main voltage equation is defined by the relation

*a*2*x*ð Þt sinh bV t ð Þ ð Þ *, V*ð Þt *<* 0

(1)

the voltage applied to the terminals of the device between the minimum and

maximum values eligible (typically a triangular signal).

rises under the constant voltage bias during the pulsing interval.

parameters, which are included in the set of equations below:

**2.1 Static characteristics**

**2.2 Dynamic characteristics**

*g*(*t*) defined below:

**29**

In the literature, memristor models studied in [3–10] have been published for basic mathematical functioning properties of the memristor, which have been proposed by HP Labs in [3]. Other models [11–14] focus on extracting the *I-V* characteristic of the model with other mathematical method using boundary conditions. They differ in complexity, materials, and accuracy. Thus, since our interest is in the behavior of the memristor, we choose to explore and investigate a simple SPICE model, which has been proposed by the present authors in [11]. The main differences are displayed in the implementation of parameters such as the state variable of the device. However, so far, no SPICE model could be correlated to several characterizations data of memristive devices. Our goal is to use a memristor model to analyze its functioning for different voltage bias. We study the dynamical behavior of memristor and we demonstrate that this model accounts for four different types of a memristor cited as the following: the bipolar behavior of memristor, the unipolar behavior, the bipolar with forgetting effect, and the reversible process between the bipolar and the unipolar behavior of memristor. Those types of memristor change under distinct stimulus such as sinusoidal, triangular, and repetitive DC sweeping voltage.

#### **2. Theoretical principles**

The wide variety in memristor structure and composition has led to the development of many different memristor modeling techniques. Some of them have been designed to represent a specific device for a specific type of application, such as AHaH [12], ANN [15, 16], Slime mold [17], and neuromorphic applications [5]. Implementation of the memristor could be generated on several tools of simulation, such as SPICE [18–25], Matlab [26–32], Verilog-A [33], and VHDL-AMS [34–37]. Resistive switching behavior is one of the fundamental properties showed in memristors; the well-known HP lab model of a memristor [3] shown in **Figure 1(a)** consists of a thin TiO2 double-layer of width D between a pair of platinum

**Figure 1.** *Physical model of memristor [3]. (a) Memristor thin film. (b) Memristor hysteresis loop.*

#### *Coexistence of Bipolar and Unipolar Memristor Switching Behavior DOI: http://dx.doi.org/10.5772/intechopen.85176*

electrodes. One of the TiO2 layers of width w is doped with oxygen vacancies. The second, undoped layer of width *w*-*D* has insulating properties. As a result of complex processes in the device, the width w of the doped layer varies by applying a voltage or current to the electrodes of the memristor, and there will be dramatic changes in resistance. Therefore, the boundary, defined as the state variable *x* = *w*/*D*, between the two layers moves simultaneously. The well-known characteristic of the memristor is shown in **Figure 1(b)**, the pinched hysteresis loop, which indicates the switching behavior of memristive devices. An application of a positive bias voltage to the electrodes of the device leads to the switching between Off and On states, and this switching is labeled SET. A RESET switching corresponds to the exchange between On and Off states. As current flows through the device, the cross section between the regions moves. As a result, the doped and the undoped regions have resistance Ron and Roff when each of them reaches the (D-w) and the full-length D, respectively. Also, the width w of the doped region of the memristor increases by applying a positive voltage bias, which causes the total resistance of the device to decrease. The same process is carried out by applying a negative voltage to the opposite side of the device. Moreover, there are two methods of the behavior of resistive switching for memristors: static and dynamic switching.

#### **2.1 Static characteristics**

better endurance and performance. Hence, the correlation of one model to other

In the literature, memristor models studied in [3–10] have been published for basic mathematical functioning properties of the memristor, which have been proposed by HP Labs in [3]. Other models [11–14] focus on extracting the *I-V* characteristic of the model with other mathematical method using boundary conditions. They differ in complexity, materials, and accuracy. Thus, since our interest is in the behavior of the memristor, we choose to explore and investigate a simple SPICE model, which has been proposed by the present authors in [11]. The main differences are displayed in the implementation of parameters such as the state variable of the device. However, so far, no SPICE model could be correlated to several characterizations data of memristive devices. Our goal is to use a memristor model to analyze its functioning for different voltage bias. We study the dynamical behavior of memristor and we demonstrate that this model accounts for four dif-

memristive devices is an interesting development to further research.

*Memristors - Circuits and Applications of Memristor Devices*

ferent types of a memristor cited as the following: the bipolar behavior of memristor, the unipolar behavior, the bipolar with forgetting effect, and the reversible process between the bipolar and the unipolar behavior of memristor. Those types of memristor change under distinct stimulus such as sinusoidal, trian-

The wide variety in memristor structure and composition has led to the development of many different memristor modeling techniques. Some of them have been designed to represent a specific device for a specific type of application, such as AHaH [12], ANN [15, 16], Slime mold [17], and neuromorphic applications [5]. Implementation of the memristor could be generated on several tools of simulation, such as SPICE [18–25], Matlab [26–32], Verilog-A [33], and VHDL-AMS [34–37]. Resistive switching behavior is one of the fundamental properties showed in memristors; the well-known HP lab model of a memristor [3] shown in **Figure 1(a)**

consists of a thin TiO2 double-layer of width D between a pair of platinum

*Physical model of memristor [3]. (a) Memristor thin film. (b) Memristor hysteresis loop.*

gular, and repetitive DC sweeping voltage.

**2. Theoretical principles**

**Figure 1.**

**28**

The characteristic of a static switching behavior is obtained with a slow sweep of the voltage applied to the terminals of the device between the minimum and maximum values eligible (typically a triangular signal).

#### **2.2 Dynamic characteristics**

In dynamic switching, voltage pulses are applied to the device and the current rises under the constant voltage bias during the pulsing interval.

A comprehensive mathematical illustration of a SPICE memristor model has been reported in [11], which will be used later on for our simulation results. This model can illustrate the static and dynamic switching behavior, which will be studied in the next section. Thus, this model is based on the assumption that the switching behavior of the memristor is small or fast, below or above a threshold voltage VSET or VRESET, respectively, which is considered as the minimum voltage required to impose a change on the physical structure and thus the memristance of the device. This assumption is encapsulated in the use of the multiple implemented parameters, which are included in the set of equations below:

$$\mathbf{I(t)} = \begin{cases} a\_1 \mathbf{x}(\mathbf{t}) \sinh \left( \mathbf{b} \mathbf{V(t)} \right), & V(\mathbf{t}) > \mathbf{0} \\ a\_2 \mathbf{x}(\mathbf{t}) \sinh \left( \mathbf{b} \mathbf{V(t)} \right), & V(\mathbf{t}) < \mathbf{0} \end{cases} \tag{1}$$

The relationship between the memristor voltage and the memristor current is given by Eq. (1), and it comprises three main parameters: *a*1, *a*2, and *b*. These parameters are responsible for the modeling of the nonlinear phenomenon of the pinched hysteresis loop. *a*<sup>1</sup> and *a*<sup>2</sup> are the magnitude parameters that vary according to the polarity of the input voltage; it is also related to the thickness of the dielectric layer of the memristor. Meanwhile, *b* is defined as the control parameter, which refers to the amount of oxygen deficiencies presented in the device, and it controls the conductivity of the device. The main voltage equation is defined by the relation *g*(*t*) defined below:

$$\mathbf{g(t)} = \begin{cases} A\_p \left( \mathbf{e^{V(t)}} - \mathbf{e^{V\_p}} \right), & V(\mathbf{t}) > V\_p \\\\ -A\_n \left( \mathbf{e^{-V(t)}} - \mathbf{e^{V\_n}} \right), & V(\mathbf{t}) < -V\_n \\\\ 0, & -V\_n \le V(\mathbf{t}) \le V\_p \end{cases} \tag{2}$$

demonstrates the basic *I-V* characteristics of a memristive device. In addition, it acts differently in the positive and negative regions of the applied voltage, and the implemented parameters of the device take account on this, which makes the analysis of the pinched hysteresis loop simple and coherent for the positive and the negative regions independently. Therefore, we analyze the fundamental fingerprint of the macromodel and its memristance switching behavior. In the simulation results of **Figure 2(a)**, we used a sinusoidal voltage 0.46 V with a frequency of 100 Hz, **Figure 2(b)** shows the resultant pinched hysteresis loop, which correlates the characterization data of the proposed model [11]. Thereby, our results agree well with the experimental results already published in [11], and we prove the linearity property of the device for a higher value of frequency. The next simulation results reveal the richness of memristor's switching behavior confirming the usefulness of the specific design approach. The effect of memristive switching is inspected by varying the implemented parameters of the model such as the magni-

This changes the operating regime so the memristance value may not remain constant and the memristor operates in different segments or takes different memristance values. This sudden jump of memristance is called "memristive

In this case, memristive switching depends on the bias of the applied voltage across the device, which is represented in **Figure 3(a)**, the curve of the state variable motion at memristor boundaries. We consider the memristor in an Off state, as an initial state of the device, switching the device to On state, requires a positive bias across the device. While switching it to Off state requires negative bias.

*(a) Curve of current and voltage applied to the terminals of the memristor. (b) Represents the resultant*

*(a) The state variable motion at memristor boundaries according to the applied voltage and (b) memristance*

*hysteresis loop at 100 Hz and 100 kHz where the deviates linear.*

tude of the voltage bias, the initial charge, and the state variable.

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

switching" or "resistive switching."

**Figure 2.**

**Figure 3.**

**31**

*behavior over time.*

Equation (2) incorporates the threshold voltage with *V*<sup>p</sup> and *V*<sup>n</sup> which refers to the positive and negative polarizations, respectively, which makes a change in the switching behavior for value below the external voltage of the memristor. *A*<sup>p</sup> and *A*<sup>n</sup> are fitting parameters that affect the conductivity of the device. Accurately, it controls the speed of the oxygen deficiencies motion. The demonstration of the linearity of the model is described by parameters included in the following equations:

$$\mathbf{f}(\mathbf{x}) = \begin{cases} \mathbf{e}^{-\mathbf{u}\_{\mathrm{p}}(\mathbf{x} - \mathbf{x}\_{\mathrm{p}})} \mathbf{w}\_{\mathrm{p}}(\mathbf{x}, \mathbf{x}\_{\mathrm{p}}), \mathbf{x} \ge \mathbf{x}\_{\mathrm{p}} \\ \mathbf{1}, & \mathbf{x} < \mathbf{x}\_{\mathrm{p}} \end{cases} \tag{3}$$

$$\mathbf{f}(\mathbf{x}) = \begin{cases} \mathbf{e}^{\mathbf{a}\_{\mathrm{n}}(\mathbf{x} + \mathbf{x}\_{\mathrm{n}} - 1)} \mathbf{w}\_{\mathrm{n}}(\mathbf{x}, \mathbf{x}\_{\mathrm{n}}), \mathbf{x} \le \mathbf{1} - \mathbf{x}\_{\mathrm{n}} \\\\ \mathbf{1}, & \mathbf{x} > \mathbf{1} - \mathbf{x}\_{\mathrm{n}} \end{cases} \tag{4}$$

The physical parameters *x*<sup>p</sup> and *x*<sup>n</sup> have been defined in Eqs. (3) and (4); it represents the value of the state variable, which is responsible for the linearity of the device. Fitting parameters *α*<sup>p</sup> and *α*<sup>n</sup> are also included in these equations; are responsible for the linearity of the device; and they determine the degree of motion including the amortization of the state variable. The parameters wn and wp are defined by Eqs. (5) and (6), respectively. Those functions are used to shape the intensity of the state variable dynamics, i.e., the rate of memristance change.

$$\mathbf{w}\_{\mathbf{p}}(\mathbf{x}, \mathbf{x}\_{\mathbf{p}}) = \frac{\mathbf{x}\_{\mathbf{p}} - \mathbf{x}}{\mathbf{1} - \mathbf{x}\_{\mathbf{p}}} + \mathbf{1} \tag{5}$$

$$\mathbf{w\_n(x, x\_n)} = \frac{\mathbf{x}}{1 - \mathbf{x\_n}} \tag{6}$$

Equation (7) represents the modeling function of the state variable. The fitting parameter *η* represents the direction of the movement of the state variable depending on the polarity of the input voltage. When *η* = 1, a positive voltage greater than the threshold voltage will increase the value of the state variable; and when *η* = �1, a positive voltage will decrease the value of the state variable.

$$\frac{d\mathbf{x}}{dt} = \eta \mathbf{g}(\mathbf{V}(\mathbf{t})) \mathbf{f}(\mathbf{x}(\mathbf{t})) \tag{7}$$

Each pair of the parameters indicates the variation in the positive and negative region of the polarization. These multiple parameters make it possible for this device to be adaptable to a variety of characterization data of memristive devices, which we will discuss in the next section.

#### **3. Analysis of the** *I-V* **characteristics**

In our previous work [38], we illustrated a methodology for a simple memristor model to automatically adjust other behaviors of memristive devices. It effectively

#### *Coexistence of Bipolar and Unipolar Memristor Switching Behavior DOI: http://dx.doi.org/10.5772/intechopen.85176*

demonstrates the basic *I-V* characteristics of a memristive device. In addition, it acts differently in the positive and negative regions of the applied voltage, and the implemented parameters of the device take account on this, which makes the analysis of the pinched hysteresis loop simple and coherent for the positive and the negative regions independently. Therefore, we analyze the fundamental fingerprint of the macromodel and its memristance switching behavior. In the simulation results of **Figure 2(a)**, we used a sinusoidal voltage 0.46 V with a frequency of 100 Hz, **Figure 2(b)** shows the resultant pinched hysteresis loop, which correlates the characterization data of the proposed model [11]. Thereby, our results agree well with the experimental results already published in [11], and we prove the linearity property of the device for a higher value of frequency. The next simulation results reveal the richness of memristor's switching behavior confirming the usefulness of the specific design approach. The effect of memristive switching is inspected by varying the implemented parameters of the model such as the magnitude of the voltage bias, the initial charge, and the state variable.

This changes the operating regime so the memristance value may not remain constant and the memristor operates in different segments or takes different memristance values. This sudden jump of memristance is called "memristive switching" or "resistive switching."

In this case, memristive switching depends on the bias of the applied voltage across the device, which is represented in **Figure 3(a)**, the curve of the state variable motion at memristor boundaries. We consider the memristor in an Off state, as an initial state of the device, switching the device to On state, requires a positive bias across the device. While switching it to Off state requires negative bias.

**Figure 2.**

g tðÞ¼

equations:

8 >>>><

*Memristors - Circuits and Applications of Memristor Devices*

>>>>:

f xð Þ¼

f xð Þ¼

(

wp x*;* xp

(

*Ap* eV tð Þ � <sup>e</sup>*Vp* � �

� *An* <sup>e</sup>�V tð Þ � <sup>e</sup>*Vn* � �

*, V*ð Þt *> Vp*

� �*, x*≥xp

1*, x <* xp

1*, x >* 1 � xn

<sup>e</sup><sup>α</sup>nð Þ <sup>x</sup>þxn�<sup>1</sup> wnð Þ <sup>x</sup>*;* xn *, x*≤<sup>1</sup> � xn

0*,* � *Vn* ≤*V*ð Þt ≤*Vp*

Equation (2) incorporates the threshold voltage with *V*<sup>p</sup> and *V*<sup>n</sup> which refers to the positive and negative polarizations, respectively, which makes a change in the switching behavior for value below the external voltage of the memristor. *A*<sup>p</sup> and *A*<sup>n</sup> are fitting parameters that affect the conductivity of the device. Accurately, it controls the speed of the oxygen deficiencies motion. The demonstration of the linearity of the model is described by parameters included in the following

e�αpð Þ <sup>x</sup>�xp wp x*;* xp

The physical parameters *x*<sup>p</sup> and *x*<sup>n</sup> have been defined in Eqs. (3) and (4); it represents the value of the state variable, which is responsible for the linearity of the device. Fitting parameters *α*<sup>p</sup> and *α*<sup>n</sup> are also included in these equations; are responsible for the linearity of the device; and they determine the degree of motion including the amortization of the state variable. The parameters wn and wp are defined by Eqs. (5) and (6), respectively. Those functions are used to shape the intensity of the state variable dynamics, i.e., the rate of memristance change.

� � <sup>¼</sup> xp � <sup>x</sup>

Equation (7) represents the modeling function of the state variable. The fitting

Each pair of the parameters indicates the variation in the positive and negative

In our previous work [38], we illustrated a methodology for a simple memristor model to automatically adjust other behaviors of memristive devices. It effectively

region of the polarization. These multiple parameters make it possible for this device to be adaptable to a variety of characterization data of memristive devices,

wnð Þ¼ x*;* xn

parameter *η* represents the direction of the movement of the state variable depending on the polarity of the input voltage. When *η* = 1, a positive voltage greater than the threshold voltage will increase the value of the state variable; and when *η* = �1, a positive voltage will decrease the value of the state variable.

dx

which we will discuss in the next section.

**3. Analysis of the** *I-V* **characteristics**

**30**

1 � xp

x 1 � xn

dt <sup>¼</sup> <sup>η</sup>gVt ð Þ ð Þ fxt ð Þ ð Þ (7)

þ 1 (5)

*, V*ð Þt *<* �*Vn*

(2)

(3)

(4)

(6)

*(a) Curve of current and voltage applied to the terminals of the memristor. (b) Represents the resultant hysteresis loop at 100 Hz and 100 kHz where the deviates linear.*

#### **Figure 3.**

*(a) The state variable motion at memristor boundaries according to the applied voltage and (b) memristance behavior over time.*

**Figure 3(b)** represents the curve of the memristance or the resistance of the memristor on the On and Off states. From this results, Ron and Roff's value estimated by 1.3 *k*Ω and 1.1 *k*Ω, respectively.

#### **4. Correlation of different memristive devices**

In this section, we present our simulation results, in which we implement the different values of parameters on PSPICE, to fit a set of memristive devices studied for different types of applications. Those results describe the static and dynamical characteristics of the model. Thus, we prove that the SPICE model fits well with the characterization data of memristors defined in [8, 15, 17, 25, 39–44]. The polarization voltages studied are either sinusoidal pulses or repetitive DC sweeping voltage to represent the different switching resistive levels of the memristor. The simulation results of the proposed model [11] shown in **Figure 4**, which indeed shows the characterization data of several memristive devices. In these simulation results, we adjust the different implement parameters on the SPICE model to fit the experimental results presented in [11]. Thus, it describes the *I*-*V* characteristics for devices defined in [8, 9, 40–43], which has been correlated by the SPICE model.


#### **4.1 Memristive device of the laboratory of slime mold**

We adjust the implemented parameters to find the appropriate shape of *I*-*V* characteristics of the Slime mold device [17] shown in **Figure 5**, our results fits well the experimental results described in [17]. The application of Slime mold is a group of bacteria that lives mainly in the soil, which has the ability to change its shape by sliding every 50 s (by extension and retraction). This outcome contributes to the development of bioelectronics circuits of self-growth. The *I*-*V* characteristics curve for a DC voltage and a repetitive sweeping and the curve of the resistance of the device shown in **Figure 5(a)**–**(c)**, respectively. These results present the functionality of this model by applying a repetitive DC sweeping voltage to present the various resistance switching states.

#### **4.2 Memristive device of Strachan of the HP laboratory**

Another memristive device based on TaO*<sup>x</sup>* was proposed by the team of HP Labs in [44]; we adjust the fitting parameters with the characterization data of this

device. The results are shown in **Figure 6**; it agrees with the experimental results

*(a) I-V curve of memristive device proposed by the State University of Boise [40], (b) I-V curve of memristive device proposed by the Tel Aviv University [41], (c) I-V curve of memristive device proposed by the University of Michigan in 2010 [8], (d) I-V curve of the device proposed by the State University of Iowa in 2010 [42], and (e) I-V curve of the device proposed by the University of Michigan [43] including the parameter values.*

represented in [44]. The *I-V* characteristic curve for a DC voltage and a repetitive sweeping and the curve of the resistance of the device are shown in **Figure 6(a)**–**(c)**, respectively. The simulation results present the functionality of this model by applying a repetitive DC sweeping voltage to present the several

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

resistance switching states.

**Figure 4.**

**33**

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior DOI: http://dx.doi.org/10.5772/intechopen.85176*

**Figure 4.**

**Figure 3(b)** represents the curve of the memristance or the resistance of the memristor on the On and Off states. From this results, Ron and Roff's value estimated

In this section, we present our simulation results, in which we implement the

a. **Figure 4(a)** describes the simulation results of the device published by the

c. **Figure 4(c)** describes the simulation results of the device published by the

d.**Figure 4(d)** describes the simulation results of the device published by the

e. **Figure 4(e)** describes the simulation results of the device published by the

We adjust the implemented parameters to find the appropriate shape of *I*-*V* characteristics of the Slime mold device [17] shown in **Figure 5**, our results fits well the experimental results described in [17]. The application of Slime mold is a group of bacteria that lives mainly in the soil, which has the ability to change its shape by sliding every 50 s (by extension and retraction). This outcome contributes to the development of bioelectronics circuits of self-growth. The *I*-*V* characteristics curve for a DC voltage and a repetitive sweeping and the curve of the resistance of the device shown in **Figure 5(a)**–**(c)**, respectively. These results present the functionality of this model by applying a repetitive DC sweeping voltage to present the

Another memristive device based on TaO*<sup>x</sup>* was proposed by the team of HP Labs

in [44]; we adjust the fitting parameters with the characterization data of this

b.**Figure 4(b)** describes the simulation results of the device published by the Tel

different values of parameters on PSPICE, to fit a set of memristive devices studied for different types of applications. Those results describe the static and dynamical characteristics of the model. Thus, we prove that the SPICE model fits well with the characterization data of memristors defined in [8, 15, 17, 25, 39–44]. The polarization voltages studied are either sinusoidal pulses or repetitive DC sweeping voltage to represent the different switching resistive levels of the memristor. The simulation results of the proposed model [11] shown in **Figure 4**, which indeed shows the characterization data of several memristive devices. In these simulation results, we adjust the different implement parameters on the SPICE model to fit the experimental results presented in [11]. Thus, it describes the *I*-*V* characteristics for devices defined in [8, 9, 40–43], which has been correlated

by 1.3 *k*Ω and 1.1 *k*Ω, respectively.

by the SPICE model.

State University of Boise in [40].

Aviv University in [9, 41].

University of Michigan in [8].

state University of Iowa in [42].

University of Michigan in [43].

various resistance switching states.

**32**

**4.1 Memristive device of the laboratory of slime mold**

**4.2 Memristive device of Strachan of the HP laboratory**

**4. Correlation of different memristive devices**

*Memristors - Circuits and Applications of Memristor Devices*

*(a) I-V curve of memristive device proposed by the State University of Boise [40], (b) I-V curve of memristive device proposed by the Tel Aviv University [41], (c) I-V curve of memristive device proposed by the University of Michigan in 2010 [8], (d) I-V curve of the device proposed by the State University of Iowa in 2010 [42], and (e) I-V curve of the device proposed by the University of Michigan [43] including the parameter values.*

device. The results are shown in **Figure 6**; it agrees with the experimental results represented in [44]. The *I-V* characteristic curve for a DC voltage and a repetitive sweeping and the curve of the resistance of the device are shown in **Figure 6(a)**–**(c)**, respectively. The simulation results present the functionality of this model by applying a repetitive DC sweeping voltage to present the several resistance switching states.

#### **4.3 Memristor of Nugent for AHaH applications**

Our model also fits well a learning AHaH application accomplished by Nugent in [12]. After the application of a sinusoidal signal to the memristor with amplitude 0.25 V for a period 10 *m*s, we found the resultant *I*-*V* characteristics shown in **Figure 7(a)**, which seems compatible with the *I*-*V* characterization profile and it fits well the experimental results revealed in [12]. This model works well for a repetitive DC sweeping voltage which is represented by the *I*-*V* characteristics curves and the curve of the resistance of the device shown in **Figure 7(b)**, **(c)**. The simulation results present the functionality of this model by applying a repetitive DC sweeping voltage to present the several resistance switching states.

**4.4 Memristive device of the University of Pittsburgh**

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

resistance switching states shown in **Figure 8(b)** and **(c)**.

**4.5 Memristive device for ANN learning application**

pulse of the excitation voltage positive and negative.

*xp = 0.32, xn = 0.1, <sup>α</sup><sup>p</sup> = 1, <sup>α</sup><sup>n</sup> = 5, Vp = 0.7, Vn = 0.75, Ap = 4 103*

*.*

*, a2 = 1.1 103*

**Figure 8.**

**Figure 9.**

**35**

*a1 = 0.17 103*

The device represented by Zhang in [39] is based on TaO*<sup>x</sup>* material. The simulation results of this device are represented in **Figure 8(a)** by applying a triangular voltage with a sweeping of the magnitude, 0.74 V for the positive region, and 1.25 V for the negative region. After adjustment of the parameters, we have a nonlinear *I*-*V* curve which seems to be compatible with the *I*-*V* characterization profile recorded in the experiments of HP labs in [39]. In addition, we proved the functioning of this device with a repetitive DC sweeping voltage to present several

Meanwhile, we also simulated the model with a square wave excitation shown in **Figure 9**. This excitation method is used as a learning method, which presents the behavior of this model as an artificial neural network ANN [15]. We follow the learning experience carried out in [16]. As shown in **Figure 9(c)**, the memristance of the device increases along with the applied voltage. However, this behavior response is different from the other previous excitation, and this depends on the type of excitation and the followed current. The current curve decreases with each

In conclusion, we notice that this SPICE model is a general model that can be applied in multiple domains. Furthermore, according to the simulation results of both devices Slime mold and HP Labs, we notice that the hysteresis loop of the memristor maintains its nonlinear shape even for a remarkable range of the values of the parameters. The speed of movement for the memristive devices of Slime mold and Nugent are faster compared to the other memristive devices since Ap and

*Simulation results compared to the simulation result of Zhang, the simulation value: <sup>η</sup> = 1, x0 = 55 <sup>10</sup><sup>4</sup>*

*Simulation results of the model adapted to learning application, the simulation value: η = 1, x0 = 0.11,*

*xp = 0.3, xn = 0.5, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = Vn = 1, Ap = An = 4, b = 0.5, a1 = a2 = 0.01.*

*,*

*,*

*, An = 500, b = 11 <sup>10</sup><sup>4</sup>*

#### **Figure 5.**

*Simulation results of the memristor model adapted to the* I*-*V *characteristics profile of Slime mold memristive device, the Simulation value: η = 1, x0 = 0.11, xp = 0.35, xn = 0.55, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = 0.1, Vn = 0.1, Ap = An = 4 10<sup>3</sup> , b = 2 10<sup>5</sup> , a1 = a2 = 17 10<sup>5</sup> .*

#### **Figure 6.**

*Simulation results of the model adapted to the I-V characteristics profile of the memristive device of Strachan, the simulation value: <sup>η</sup> = 1, x0 = 99 <sup>10</sup><sup>3</sup> , xp = 0.3, xn = 0.63, α<sup>p</sup> = 0.1, α<sup>n</sup> = 20, Vp = 0.49, Vn = 0.6, Ap = 400, An = 25, b = 1.3 <sup>10</sup><sup>3</sup> , a1 = 1.7, a2 = 1.2.*

#### **Figure 7.**

*Simulation results of the model adapted to the* I*-*V *characteristics profile of the memristive device of Nugent, the simulation value: <sup>η</sup> = 1, x0 = 1.1 <sup>10</sup><sup>4</sup> , xp = 0.3, xn = 0.8, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = 0.1, Vn = 0.13, Ap = An = 4 <sup>10</sup><sup>3</sup> , b = 6.5 <sup>10</sup><sup>2</sup> , a1 = a2 = 0.17.*

#### **4.4 Memristive device of the University of Pittsburgh**

The device represented by Zhang in [39] is based on TaO*<sup>x</sup>* material. The simulation results of this device are represented in **Figure 8(a)** by applying a triangular voltage with a sweeping of the magnitude, 0.74 V for the positive region, and 1.25 V for the negative region. After adjustment of the parameters, we have a nonlinear *I*-*V* curve which seems to be compatible with the *I*-*V* characterization profile recorded in the experiments of HP labs in [39]. In addition, we proved the functioning of this device with a repetitive DC sweeping voltage to present several resistance switching states shown in **Figure 8(b)** and **(c)**.

#### **4.5 Memristive device for ANN learning application**

Meanwhile, we also simulated the model with a square wave excitation shown in **Figure 9**. This excitation method is used as a learning method, which presents the behavior of this model as an artificial neural network ANN [15]. We follow the learning experience carried out in [16]. As shown in **Figure 9(c)**, the memristance of the device increases along with the applied voltage. However, this behavior response is different from the other previous excitation, and this depends on the type of excitation and the followed current. The current curve decreases with each pulse of the excitation voltage positive and negative.

In conclusion, we notice that this SPICE model is a general model that can be applied in multiple domains. Furthermore, according to the simulation results of both devices Slime mold and HP Labs, we notice that the hysteresis loop of the memristor maintains its nonlinear shape even for a remarkable range of the values of the parameters. The speed of movement for the memristive devices of Slime mold and Nugent are faster compared to the other memristive devices since Ap and

**Figure 8.**

**4.3 Memristor of Nugent for AHaH applications**

*Memristors - Circuits and Applications of Memristor Devices*

switching states.

**Figure 5.**

**Figure 6.**

**Figure 7.**

**34**

*Ap = An = 4 <sup>10</sup><sup>3</sup>*

*Ap = An = 4 10<sup>3</sup>*

*, b = 2 10<sup>5</sup>*

*the simulation value: <sup>η</sup> = 1, x0 = 99 <sup>10</sup><sup>3</sup>*

*the simulation value: <sup>η</sup> = 1, x0 = 1.1 <sup>10</sup><sup>4</sup>*

*, b = 6.5 <sup>10</sup><sup>2</sup>*

*Ap = 400, An = 25, b = 1.3 <sup>10</sup><sup>3</sup>*

*, a1 = a2 = 17 10<sup>5</sup>*

Our model also fits well a learning AHaH application accomplished by Nugent in [12]. After the application of a sinusoidal signal to the memristor with amplitude 0.25 V for a period 10 *m*s, we found the resultant *I*-*V* characteristics shown in **Figure 7(a)**, which seems compatible with the *I*-*V* characterization profile and it fits well the experimental results revealed in [12]. This model works well for a repetitive DC sweeping voltage which is represented by the *I*-*V* characteristics curves and the curve of the resistance of the device shown in **Figure 7(b)**, **(c)**. The simulation results present the functionality of this model by applying a repetitive DC sweeping voltage to present the several resistance

*Simulation results of the memristor model adapted to the* I*-*V *characteristics profile of Slime mold memristive device, the Simulation value: η = 1, x0 = 0.11, xp = 0.35, xn = 0.55, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = 0.1, Vn = 0.1,*

*Simulation results of the model adapted to the I-V characteristics profile of the memristive device of Strachan,*

*Simulation results of the model adapted to the* I*-*V *characteristics profile of the memristive device of Nugent,*

*, a1 = a2 = 0.17.*

*, a1 = 1.7, a2 = 1.2.*

*, xp = 0.3, xn = 0.63, α<sup>p</sup> = 0.1, α<sup>n</sup> = 20, Vp = 0.49, Vn = 0.6,*

*, xp = 0.3, xn = 0.8, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = 0.1, Vn = 0.13,*

*.*

*Simulation results compared to the simulation result of Zhang, the simulation value: <sup>η</sup> = 1, x0 = 55 <sup>10</sup><sup>4</sup> , xp = 0.32, xn = 0.1, <sup>α</sup><sup>p</sup> = 1, <sup>α</sup><sup>n</sup> = 5, Vp = 0.7, Vn = 0.75, Ap = 4 103 , An = 500, b = 11 <sup>10</sup><sup>4</sup> , a1 = 0.17 103 , a2 = 1.1 103 .*

#### **Figure 9.**

*Simulation results of the model adapted to learning application, the simulation value: η = 1, x0 = 0.11, xp = 0.3, xn = 0.5, α<sup>p</sup> = 1, α<sup>n</sup> = 5, Vp = Vn = 1, Ap = An = 4, b = 0.5, a1 = a2 = 0.01.*

An have higher values. Thus, the memristive devices of Slime mold and Zhang application have the lowest values of b, which decrease its conductivity. The ANN learning application presents another type of excitation, which largely affects the dynamic of the memristor's behavior. Thus, we will deal later with the use of different memristor switching behavior, we demonstrate not only bipolar, but also the unipolar switching behavior of memristors, which differs from bipolar memristors in the fact that only the magnitude of the voltage across the device determines the change in the resistance.

with current value I = 7 *m*A. Reversing the voltage polarity, the device switches to a reset value at v = 1.8 V with current value I = 4.5 *m*A. The attained pinched hysteresis *I-V* curves are shown in **Figure 10(b)**, **(c)**, which are the typical fingerprint of bipolar resistive switching. The corresponding resistance response is illustrated in **Figure 10(d)**, which was measured according to voltage sweeping with a maximum value of 1.2 *k*Ω and a lower value of 0.9 *k*Ω in the negative and positive voltage application respectively. In addition, **Figure 10(e)** confirms that hysteresis takes place in both *I-V* and *C-V* relationships of the device, and it shows a closed switching cycle in the bipolar switching behavior for a maximum value of 25 *m*S. Memristor behavior for a bipolar switching with forgetting effect is shown in **Figure 11**. An obvious overlap of the *I-V* curve is shown in **Figure 11(b)**, **(c)**, due to

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

the repetitive sweeping of the applied voltage. The sweeping voltage bias

forgetting effect.

**Figure 11.**

**Figure 12.**

**37**

*Memristor SPICE model response to a bipolar with forgetting effect.*

*Memristor SPICE model response to a unipolar behavior switching.*

the voltage polarity, the device switches to a reset value at v = 1.2 V with a maximum current value I = 5 *m*A. Also, it can be seen from these curves, an accumulation of the current on each pulse. The corresponding resistance response is illustrated in **Figure 11(d)**, which was measured according to voltage sweeping with a maximum value of 1.8 *k*Ω decreasing to a lower value of 0.3 *k*Ω in the positive voltage application, on the opposite side of the negative voltage

approaches a set value v = 1.2 V with a maximum current value I = 6 *m*A. Reversing

application the resistance response shows an increase from 0.3 to 0.9 *k*Ω. The curve in **Figure 11(e)** shows five switching cycles for a maximum value of 35 *m*S. This *C-V* curve shows that the memristance not only increases and decreases by a different polarity voltage, but it also can spontaneously decrease at the same time, even with no voltage applied, and this is a unique switching behavior of memristor. In fact, these curves show the operation of the model as a bipolar memristor with

Furthermore, the simulation results for the unipolar behavior of memristor are shown in **Figure 12**, which show that another switching behavior is characterized by the memory devices and also that the memristance of the device can increase and decrease by the same polarity of the voltage. For this type of memristor, we use a positive voltage excitation for a value of 2 V and maximum current value I = 17 *m*A, which is shown in the curve (**Figure 12(a)**), we notice a slight accumulation of the current on each pulse. The characteristics shown in **Figure 12(d)**, **(e)** describe the resistance and the conductance curve of the memristor. The resistance was

#### **5. Behavior of the SPICE model for different types of memristors**

Memristor models, in literature, have different responses, which are generated for four different types of a memristor, i.e., bipolar, bipolar with a forgetting effect, unipolar and reversible behavior between the bipolar, and the unipolar memristor. For our simulation results, we used a SPICE model that can not only describe the basic memory ability of memristor, but also be able to capture all of the four types of memristor switching behavior.

Models with bipolar switching [45, 46] distinguishable by the memristance which increases and decreases by different polarity voltages. Models with unipolar switching behavior [45, 46] are distinguishable by its memristance, which can increase and decrease by the same polarity voltage. The bipolar with forgetting effect [47, 48] is distinguishable by its memristance which increases and decreases by a different polarity voltage, but memristance can spontaneously decrease at the same time, even with no voltage applied. The reversible bipolar and unipolar switching behavior [49], here the memristor will behave like a bipolar memristor at first, but after a few iterations, it will turn to a unipolar memristor.

In the same context, we use different polarization voltages, either sinusoidal or repetitive DC sweeping voltage, exploited in order to present the different states of resistance of the memristor, and thus it shows the behavior of the four different types of a memristor. Those results reveal the richness of memristor's dynamical behavior confirming the usefulness of the specific model approach.

To verify the memristive characteristics and the coexistence of different switching behavior of our proposed model, we employed different excitations presented in the following figures of the rest of the paper. In fact, to characterize different types of memristors, we need to verify the behavior of the model for the well-known fundamental switching behavior in both bipolar and unipolar switching behavior. In this case, we have adapted our model according to the experimental results demonstrated in [50]. These observations are consistent and in very good qualitative agreement with the experimental results of the memristor switching behavior already published in [50].

In addition, **Figure 10** shows the dynamical characteristics of a bipolar memristor behavior. The sweeping voltage bias approaches a set value v = 1.8 V

**Figure 10.** *Memristor SPICE model response for a bipolar switching behavior.*

#### *Coexistence of Bipolar and Unipolar Memristor Switching Behavior DOI: http://dx.doi.org/10.5772/intechopen.85176*

An have higher values. Thus, the memristive devices of Slime mold and Zhang application have the lowest values of b, which decrease its conductivity. The ANN learning application presents another type of excitation, which largely affects the dynamic of the memristor's behavior. Thus, we will deal later with the use of different memristor switching behavior, we demonstrate not only bipolar, but also

the unipolar switching behavior of memristors, which differs from bipolar memristors in the fact that only the magnitude of the voltage across the device

**5. Behavior of the SPICE model for different types of memristors**

Memristor models, in literature, have different responses, which are generated for four different types of a memristor, i.e., bipolar, bipolar with a forgetting effect, unipolar and reversible behavior between the bipolar, and the unipolar memristor. For our simulation results, we used a SPICE model that can not only describe the basic memory ability of memristor, but also be able to capture all of the four types

Models with bipolar switching [45, 46] distinguishable by the memristance which increases and decreases by different polarity voltages. Models with unipolar switching behavior [45, 46] are distinguishable by its memristance, which can increase and decrease by the same polarity voltage. The bipolar with forgetting effect [47, 48] is distinguishable by its memristance which increases and decreases by a different polarity voltage, but memristance can spontaneously decrease at the same time, even with no voltage applied. The reversible bipolar and unipolar switching behavior [49], here the memristor will behave like a bipolar memristor at

In the same context, we use different polarization voltages, either sinusoidal or repetitive DC sweeping voltage, exploited in order to present the different states of resistance of the memristor, and thus it shows the behavior of the four different types of a memristor. Those results reveal the richness of memristor's dynamical

To verify the memristive characteristics and the coexistence of different switching behavior of our proposed model, we employed different excitations presented in the following figures of the rest of the paper. In fact, to characterize different types of memristors, we need to verify the behavior of the model for the well-known fundamental switching behavior in both bipolar and unipolar switching behavior. In this case, we have adapted our model according to the experimental results demonstrated in [50]. These observations are consistent and in very good qualitative agreement with the experimental results of the memristor switching

In addition, **Figure 10** shows the dynamical characteristics of a bipolar memristor behavior. The sweeping voltage bias approaches a set value v = 1.8 V

first, but after a few iterations, it will turn to a unipolar memristor.

behavior confirming the usefulness of the specific model approach.

determines the change in the resistance.

*Memristors - Circuits and Applications of Memristor Devices*

of memristor switching behavior.

behavior already published in [50].

*Memristor SPICE model response for a bipolar switching behavior.*

**Figure 10.**

**36**

with current value I = 7 *m*A. Reversing the voltage polarity, the device switches to a reset value at v = 1.8 V with current value I = 4.5 *m*A. The attained pinched hysteresis *I-V* curves are shown in **Figure 10(b)**, **(c)**, which are the typical fingerprint of bipolar resistive switching. The corresponding resistance response is illustrated in **Figure 10(d)**, which was measured according to voltage sweeping with a maximum value of 1.2 *k*Ω and a lower value of 0.9 *k*Ω in the negative and positive voltage application respectively. In addition, **Figure 10(e)** confirms that hysteresis takes place in both *I-V* and *C-V* relationships of the device, and it shows a closed switching cycle in the bipolar switching behavior for a maximum value of 25 *m*S.

Memristor behavior for a bipolar switching with forgetting effect is shown in **Figure 11**. An obvious overlap of the *I-V* curve is shown in **Figure 11(b)**, **(c)**, due to the repetitive sweeping of the applied voltage. The sweeping voltage bias approaches a set value v = 1.2 V with a maximum current value I = 6 *m*A. Reversing the voltage polarity, the device switches to a reset value at v = 1.2 V with a maximum current value I = 5 *m*A. Also, it can be seen from these curves, an accumulation of the current on each pulse. The corresponding resistance response is illustrated in **Figure 11(d)**, which was measured according to voltage sweeping with a maximum value of 1.8 *k*Ω decreasing to a lower value of 0.3 *k*Ω in the positive voltage application, on the opposite side of the negative voltage application the resistance response shows an increase from 0.3 to 0.9 *k*Ω. The curve in **Figure 11(e)** shows five switching cycles for a maximum value of 35 *m*S. This *C-V* curve shows that the memristance not only increases and decreases by a different polarity voltage, but it also can spontaneously decrease at the same time, even with no voltage applied, and this is a unique switching behavior of memristor. In fact, these curves show the operation of the model as a bipolar memristor with forgetting effect.

Furthermore, the simulation results for the unipolar behavior of memristor are shown in **Figure 12**, which show that another switching behavior is characterized by the memory devices and also that the memristance of the device can increase and decrease by the same polarity of the voltage. For this type of memristor, we use a positive voltage excitation for a value of 2 V and maximum current value I = 17 *m*A, which is shown in the curve (**Figure 12(a)**), we notice a slight accumulation of the current on each pulse. The characteristics shown in **Figure 12(d)**, **(e)** describe the resistance and the conductance curve of the memristor. The resistance was

**Figure 11.** *Memristor SPICE model response to a bipolar with forgetting effect.*

**Figure 12.** *Memristor SPICE model response to a unipolar behavior switching.*

measured with a maximum value of 2.8 *k*Ω decreasing to a lower value of 0.25 *k*Ω. However, the conductance curve (**Figure 12(e)**) shows three switching cycles related to voltage sweeping for a maximum value of 80 *m*S. In fact, this *C-V* curve shows that the conductance change in response to three positive pulses, it initially increases (during each pulse stimulus) and subsequently decays toward its original value (between stimuli).

memristors models with an average number of parameters, and for its flexibility,

*Coexistence of Bipolar and Unipolar Memristor Switching Behavior*

*DOI: http://dx.doi.org/10.5772/intechopen.85176*

The consideration of the SPICE memristor model as a simple and flexible model was proved to explain the memristor switching, not only processing the general memristor properties, but also catching the different types of memristor behavior: the bipolar, unipolar, the bipolar with forgetting effect, and the reversible process between the bipolar and the unipolar behavior. Our simulation results demonstrate that for the bipolar memristor, a regular hysteresis curve can be obtained. For the bipolar memristor with forgetting effect, an obvious overlap between the neighbor loops of the *I-V* curve, and for the unipolar memristor, a positive voltage is applied, but the conductance will increase only when the voltage is over 1 V. Also, for the reversible process between bipolar and unipolar behavior, the memristor firstly behaves as a bipolar switching, and its conductance increases and decreases according to the polarity of the voltage. However, after applying a second pulse, it will turn to behave as a unipolar switching. This chapter provides a practical memristor model that can be simulated with different types of stimulus, and further studies are aimed at integrating the memristor model into a computing design with complementary metal-oxide-semiconductor (CMOS) circuits that can perform the

\*, Khaoula Mbarek<sup>1</sup> and Kamel Besbes1,2

and low complexity.

necessary functions on a chip.

**Author details**

University of Monastir, Tunisia

, Faten Ouaja Rziga<sup>1</sup>

\*Address all correspondence to: faten\_ouaja@yahoo.fr

provided the original work is properly cited.

1 Micro-Optoelectronics and Nanostructures Laboratory, Faculty of Sciences,

2 Center for Research in Microelectronics and Nanotechnology, Technopole in

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

Sami Ghedira<sup>1</sup>

Sousse, Tunisia

**39**

**6. Conclusion**

In the end, we represent the results of memristor under a reversible state between the bipolar and the unipolar behavior in **Figure 13**. The sweeping voltage bias, shown in **Figure 13(a)**, approaches a set value v = 5 V with a maximum current value I = 60 *m*A. Reversing the voltage polarity, the device switches to a reset value at v = 5 V with a maximum current value I = 10 *m*A.

An obvious overlap of the *I-V* curve in **Figure 13(b), (c)** occurs due to the repetitive sweeping of the applied voltage. The corresponding resistance response is illustrated in **Figure 13(d),** which occurs in a different switching behavior; the rise and fall of the resistance exist but with a large gap between high and low values. The conductance curve in **Figure 13(e)** shows four switching cycles for a maximum value of 100 *m*S. This *C-V* curve shows that the first cycle of the switching behavior differs to the other cycles of the switching behavior of the memristor. In fact, the first cycle that can be seen from these curves shows bipolar operation, but after the second pulse, it automatically turned to a unipolar memristor behavior. These characteristic curves are shown, respectively, in **Figures 10**–**13**. The operation of the memristor model as a bipolar memristor behavior is shown in **Figure 10**. The response to a bipolar with forgetting effect is shown in **Figure 11**. The response to a unipolar memristor behavior is shown in **Figure 12**. And, the memristor model response to a reversible bipolar and unipolar behavior is shown in **Figure 13**. We can conclude that our simulation results are consistent and in very good qualitative agreement with the results already published in [15]. A detailed comparison between our work model and other popular memristor models (the Chua [1], the Strukov (HP) [3], Vourkas [45], and the Chen [15]) is shown in **Table 1**. We can notice that the SPICE model gets a special advantage on describing various

**Figure 13.** *Memristor SPICE model response to reversible bipolar and unipolar behavior.*


**Table 1.** *Comparing memristor models.* memristors models with an average number of parameters, and for its flexibility, and low complexity.

### **6. Conclusion**

measured with a maximum value of 2.8 *k*Ω decreasing to a lower value of 0.25 *k*Ω. However, the conductance curve (**Figure 12(e)**) shows three switching cycles related to voltage sweeping for a maximum value of 80 *m*S. In fact, this *C-V* curve shows that the conductance change in response to three positive pulses, it initially increases (during each pulse stimulus) and subsequently decays toward its original

In the end, we represent the results of memristor under a reversible state between the bipolar and the unipolar behavior in **Figure 13**. The sweeping voltage bias, shown in **Figure 13(a)**, approaches a set value v = 5 V with a maximum current value I = 60 *m*A. Reversing the voltage polarity, the device switches to a

An obvious overlap of the *I-V* curve in **Figure 13(b), (c)** occurs due to the repetitive sweeping of the applied voltage. The corresponding resistance response is illustrated in **Figure 13(d),** which occurs in a different switching behavior; the rise and fall of the resistance exist but with a large gap between high and low values. The conductance curve in **Figure 13(e)** shows four switching cycles for a maximum value of 100 *m*S. This *C-V* curve shows that the first cycle of the switching behavior differs to the other cycles of the switching behavior of the memristor. In fact, the first cycle that can be seen from these curves shows bipolar operation, but after the second pulse, it automatically turned to a unipolar memristor behavior. These characteristic curves are shown, respectively, in **Figures 10**–**13**. The operation of the memristor model as a bipolar memristor behavior is shown in **Figure 10**. The response to a bipolar with forgetting effect is shown in **Figure 11**. The response to a unipolar memristor behavior is shown in **Figure 12**. And, the memristor model response to a reversible bipolar and unipolar behavior is shown in **Figure 13**. We can conclude that our simulation results are consistent and in very good qualitative agreement with the results already published in [15]. A detailed comparison between our work model and other popular memristor models (the Chua [1], the Strukov (HP) [3], Vourkas [45], and the Chen [15]) is shown in **Table 1**. We can notice that the SPICE model gets a special advantage on describing various

reset value at v = 5 V with a maximum current value I = 10 *m*A.

*Memristors - Circuits and Applications of Memristor Devices*

*Memristor SPICE model response to reversible bipolar and unipolar behavior.*

**Low complexity**

Chua [1] Yes No Yes No Yes No No —

Chen [15] Yes Yes No Yes Yes Yes Yes 13 This work Yes Yes Yes Yes Yes Yes Yes 13

**Unipolar Bipolar Forgetting**

Yes No Yes No Yes No No 5

Yes Yes Yes No Yes No No 12

**effect**

**Reversible effect**

**Parameters**

**frequency**

**Mechanism High**

value (between stimuli).

**Figure 13.**

**Memristor models**

Strukov (HP) [3]

Vourkas [45]

**Table 1.**

**38**

*Comparing memristor models.*

The consideration of the SPICE memristor model as a simple and flexible model was proved to explain the memristor switching, not only processing the general memristor properties, but also catching the different types of memristor behavior: the bipolar, unipolar, the bipolar with forgetting effect, and the reversible process between the bipolar and the unipolar behavior. Our simulation results demonstrate that for the bipolar memristor, a regular hysteresis curve can be obtained. For the bipolar memristor with forgetting effect, an obvious overlap between the neighbor loops of the *I-V* curve, and for the unipolar memristor, a positive voltage is applied, but the conductance will increase only when the voltage is over 1 V. Also, for the reversible process between bipolar and unipolar behavior, the memristor firstly behaves as a bipolar switching, and its conductance increases and decreases according to the polarity of the voltage. However, after applying a second pulse, it will turn to behave as a unipolar switching. This chapter provides a practical memristor model that can be simulated with different types of stimulus, and further studies are aimed at integrating the memristor model into a computing design with complementary metal-oxide-semiconductor (CMOS) circuits that can perform the necessary functions on a chip.

### **Author details**

Sami Ghedira<sup>1</sup> , Faten Ouaja Rziga<sup>1</sup> \*, Khaoula Mbarek<sup>1</sup> and Kamel Besbes1,2

1 Micro-Optoelectronics and Nanostructures Laboratory, Faculty of Sciences, University of Monastir, Tunisia

2 Center for Research in Microelectronics and Nanotechnology, Technopole in Sousse, Tunisia

\*Address all correspondence to: faten\_ouaja@yahoo.fr

© 2019 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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[4] Yang JJ, Pickett MD, Li X, Ohlberg

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Nanotechnology. 2009;**20**(21):215201

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University of California; 2010

2010;**10**(4):1297-1301

nonlinear dopant drift.

2014;**22**(1):79-103

**40**

DA, Stewart DR, Williams RS. Memristive switching mechanism for metal/oxide/metal nanodevices. Nature Nanotechnology. 2008;**3**(7):429-433

oxide memristive switches.

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[26] Singh T. Hybrid Memristor-CMOS (MeMOS) based Logic Gates and Adder Circuits. arXiv preprint arXiv: 1506.06735. 2015

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Section 2

Applications

**43**
