3.1 Device structure

One particular advantage of G<sup>4</sup> FET is that standard SOI process without significant modification can be used to fabricate these devices. The carrier conduction through the channel is modulated using four independent gates. The conventional source and gates become junction gates (JG1 and JG2) to provide lateral JFET functionality and the top and bottom gates provide vertical MOS functionality. Figure 1 shows the 3-D schematic structure of a p-channel G<sup>4</sup> FET. It is evident that no specialized fabrication procedure is necessary for this device.
