Abstract

Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore's Law, researchers all over the world are looking for new devices with enhanced functionality. A plethora of promising emerging devices has been proposed in recent years. In order to leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. For the models to be of practical use, they have to enable fast and accurate simulation that rules out the possibility of numerically solving a system of partial differential equations to arrive at a solution. In this chapter, we show how different modeling approaches can be used to simulate three emerging semiconductor devices namely, silicon- oninsulator four gate transistor(G<sup>4</sup> FET), perimeter gated single photon avalanche diode (PG-SPAD) and insulator-metal transistor (IMT) device with volatile memristance. All the models have been verified against experimental /TCAD data and implemented in commercial circuit simulator.

Keywords: silicon-on-insulator (SOI), multiple-gate transistor, G<sup>4</sup> FET, semiconductor device, spline interpolation, macromodel, silicon photomultiplier, single photon avalanche diode, circuit design, insulator metal transition, IMT, compact model, SPICE, neuron, Mott transition

### 1. Introduction

Circuit simulation is an indispensable part of modern IC design. The significant cost of fabrication has driven researchers to verify the chip functionality through simulation before submitting the design for final fabrication. With the impending end of Moore's Law, researchers all over the world are now looking for new devices with enhanced functionality and a plethora of promising emerging devices has been proposed in recent years. To leverage the full potential of such devices, circuit designers need fast, reliable models for SPICE simulation to explore different applications. Most of these new devices have complex underlying physical mechanism rendering the model development an extremely challenging task. To be of practical

use, the model has to enable fast and accurate simulation, which rules out the possibility of numerically solving differential equations underlying the physics of semiconductor devices to arrive at a solution. In this chapter, we show how different approaches can be adopted to model three emerging semiconductor devices, namely silicon-on-insulator four-gate transistor (G4 FET), single-photon avalanche diode (SPAD), and insulator-metal transistor (IMT) device with volatile memristance.

## 2. Background

The amazing technological advancements in the semiconductor industries during last 60 years have largely shaped the modern world we live in. However, bulk silicon devices are now faced with some fundamental physical limits and innovative researchers and scientists all over the world have been diligently exploring new devices and computing paradigms to continue the breathtaking pace of technology advancement. The widespread use of a technology in circuit design is heavily dependent upon good SPICE models for CAD (computer-aided design) tools that are now ubiquitous in circuit design. Sophisticated models for existing semiconductor devices integrated with CAD tools have enabled designers worldwide to design innovative and reliable circuits which are in a large part responsible for the technology boom of the last several decades. In this chapter, we will be discussing three relatively new devices highlighting the works and challenges involved in model development and SPICE simulation.

The first device is SOI (silicon-on-insulator) four-gate transistor known as G4 FET. Here, we outline its operating mechanism, different approaches towards modeling and highlight two particular approaches, namely multivariate cubic spine interpolation model and MOS-JFET macromodel. The second device is a single photon avalanche diode (SPAD). We review and discuss the most recent developments in SPAD modeling with particular emphasis on a new class of SPAD known as PGSPAD (perimeter gated SPAD). The third device is insulator metal transition (IMT) device. Here, we focus on a very recent IMT model to demonstrate how proper simplification of device physics can lead to a suitable SPICE model facilitating circuit design.

#### 3. Silicon-on-insulator (SOI) four gate field effect transistor (G<sup>4</sup> FET)

G4 FET was first reported in 2002 [1]. It has four independent gates, two of which provide vertical MOS (metal-oxide-semiconductor) field-effect action whereas the other two gates provide lateral junction field effect transistor (JFET) functionality. The unique G<sup>4</sup> FET structure can be leveraged to design circuits for different analog, mixed-signal and digital applications with significantly reduced transistor counts. Some of these have already been experimentally demonstrated including LC oscillators and Schmitt trigger circuit with adjustable hysteresis using negative differential resistance [2], four quadrant analog multipliers [3], adjustable threshold inverters, real time reconfigurable logic gates and DRAM cell [4], and universal and programmable logic gate capable of highly efficient full adder design [5]. G<sup>4</sup> FET inspired multiple state electrostatically formed nanowires have already been used for threshold logic functions [6] and high-sensitivity gas sensing [7]. Another potential application is to leverage the tunable tent map shape characteristics of the voltage controlled G<sup>4</sup> NDR circuit [2] to build chaotic logic gates for hardware security applications [8, 9].
