**4.2 Core chip (CC)**

The same driver that pushes the advancement of SCFE circuits, generally referred to as low SWaP-C requirements, is behind the development of core-chips (CC) too.

As opposed to GaN used in SCFE, CCs are developed in GaAs thanks to its superior high frequency performance, and most of all the possibility to employ simultaneously enhancement and depletion mode transistor, which are the necessary for the digital logic on board CCs.

Essentially, a CC is a single MMIC that integrates the three functionalities that are required for signal conditioning and routing in modern TRMs, i.e. the phase

**37**

**Figure 22.**

*UWB Circuits and Sub-Systems for Aerospace, Defence and Security Applications*

shifter, the attenuator, and the single-pole double-throw (SPDT) switches used to select the transmit and receive mode operations. All these functionalities require a large number of control signals to set the state of the attenuator, the phase shifter and the TX or RX mode. Typically these states are set through a dozen or more separate controls and it is unfeasible to deliver them in parallel way (i.e. one interface pad for each control signal provided to the CC). A work-around for this problem consists in sending the control signal serially, and performing de-serialization on board. Such function requires circuits as Flip-Flop, latches, buffers and level shifters. Such circuits have a purely digital function, and are synthesized, as stated before, enhancement and depletion mode transistor, which are in Silicon based technology—having unfortunately a severe RF power and frequency limitationand also GaAs that on the contrary is very suitable for high frequency RF signal

Core chips come in, at least, two architectural variants. In the first, referred to separated architecture [15], the RF signal travels bi-directionally in the phase shifter and attenuator as depicted in **Figure 23a**. In the common-leg architecture, **Figure 23b**, the signal travels always in the same direction in both transmit and receive modes. More switches are required, at least three as opposed to the single T/R switch in separated architecture, to implements the correct routing of the single in Transmit and receive mode. Architecture (a) has the advantage of being more simple and compact, while architecture (b), although more complex, has the advantage of having amplifiers in the common leg (being mono-directional)

The physical implementation of a CC operating at X-band (9–11 GHz) is

*(a) Block diagram and (b) photograph of a realized SCFE operating around 22 GHz. Size is 49 mm2*

*.*

Finally, let us focus on the role of the Serial-to-Parallel converter (S2PC). At least 13 lines (commands) are necessary to set the state of the 6-BIT phase shifter (ΔΦ), 6-BIT Attenuator (ΔA) and SPDT switch for T/R mode setting. If the S2PC were not on board then 13 lines would have to be fed to the CC. With the insertion of the S2PC only one serial data line is necessary together with a clock line and an Enable command. Therefore only three command lines, plus a digital voltage supply line, as opposed to 13 or more. The S2PC is the very dense area depicted in **Figure 24**.

therefore improving noise figure, gain and linearity performance.

*DOI: http://dx.doi.org/10.5772/intechopen.87095*

conditioning.

reported in **Figure 24** [14].

### *UWB Circuits and Sub-Systems for Aerospace, Defence and Security Applications DOI: http://dx.doi.org/10.5772/intechopen.87095*

shifter, the attenuator, and the single-pole double-throw (SPDT) switches used to select the transmit and receive mode operations. All these functionalities require a large number of control signals to set the state of the attenuator, the phase shifter and the TX or RX mode. Typically these states are set through a dozen or more separate controls and it is unfeasible to deliver them in parallel way (i.e. one interface pad for each control signal provided to the CC). A work-around for this problem consists in sending the control signal serially, and performing de-serialization on board. Such function requires circuits as Flip-Flop, latches, buffers and level shifters. Such circuits have a purely digital function, and are synthesized, as stated before, enhancement and depletion mode transistor, which are in Silicon based technology—having unfortunately a severe RF power and frequency limitationand also GaAs that on the contrary is very suitable for high frequency RF signal conditioning.

Core chips come in, at least, two architectural variants. In the first, referred to separated architecture [15], the RF signal travels bi-directionally in the phase shifter and attenuator as depicted in **Figure 23a**. In the common-leg architecture, **Figure 23b**, the signal travels always in the same direction in both transmit and receive modes. More switches are required, at least three as opposed to the single T/R switch in separated architecture, to implements the correct routing of the single in Transmit and receive mode. Architecture (a) has the advantage of being more simple and compact, while architecture (b), although more complex, has the advantage of having amplifiers in the common leg (being mono-directional) therefore improving noise figure, gain and linearity performance.

The physical implementation of a CC operating at X-band (9–11 GHz) is reported in **Figure 24** [14].

Finally, let us focus on the role of the Serial-to-Parallel converter (S2PC). At least 13 lines (commands) are necessary to set the state of the 6-BIT phase shifter (ΔΦ), 6-BIT Attenuator (ΔA) and SPDT switch for T/R mode setting. If the S2PC were not on board then 13 lines would have to be fed to the CC. With the insertion of the S2PC only one serial data line is necessary together with a clock line and an Enable command. Therefore only three command lines, plus a digital voltage supply line, as opposed to 13 or more. The S2PC is the very dense area depicted in **Figure 24**.

**Figure 22.** *(a) Block diagram and (b) photograph of a realized SCFE operating around 22 GHz. Size is 49 mm2*

*.*

*UWB Technology - Circuits and Systems*

elements, and thus the performance of the array, is directly related to the physical size of the overall TRM that is adopted behind each elementary radiating element. Thus, the availability of highly integrated front ends with sensible smaller foot print and weight could be very useful for such systems, since it would allow the increase

Recently, with the advance of highly performing and reliable commercial GaN processes, the concept of single-chip front end (SCFE) was investigated as a pos-

Essentially, an SCFE is a single MMIC that integrates the three functionalities that are required for a half-duplex TRM, i.e. the HPA, the LNA, and the single-pole double-throw (SPDT) switch. GaN offers remarkable advantages in terms of reliability, robustness, heat dissipation and power handling capability, as compared to

The limiter inserted before the LNA, in **Figure 21**, is optional, and depends on

The same driver that pushes the advancement of SCFE circuits, generally referred to as low SWaP-C requirements, is behind the development of core-chips

As opposed to GaN used in SCFE, CCs are developed in GaAs thanks to its superior high frequency performance, and most of all the possibility to employ simultaneously enhancement and depletion mode transistor, which are the neces-

Essentially, a CC is a single MMIC that integrates the three functionalities that are required for signal conditioning and routing in modern TRMs, i.e. the phase

**Figure 22** depicts the schematic block diagram and implementation of a recently

of radiating elements density, leading to the performance maximization.

sible alternative to multichip TRMs.

sary for the digital logic on board CCs.

published SCFE [14].

**4.2 Core chip (CC)**

(CC) too.

**Figure 21.**

*Two MMIC compact TRM.*

GaAs counterparts for this specific application.

the maxim incident power and the LNA's robustness.

**36**

**Figure 23.** *Block diagram of separated architecture CC (a) and common-leg architecture (b).*

**Figure 24.** *Photograph of a realized CC operating around 10 GHz. Size is 15 mm2 .*
