3.1 Voltage sag

The grid is disturbed with a sag in the SST input. The sag appears with a voltage reduction of 30%Vgrid during a time of 0:05 s (between 0:15≤t ≤0:20). It is considered that there is a load of 400 kVA with a power factor of 0.85.


Table 7. SST nominal values.


#### Table 8.

Inductance and capacitance of each stage of the SST.


Table 9. Drivers of each stage of the SST. Solid-State Transformer for Energy Efficiency Enhancement DOI: http://dx.doi.org/10.5772/intechopen.84345

The deduction of each formulation is presented in [26], where iLi is the current flowing into the converter, Vgrid is the voltage of the grid, m represents the modulation index, Vrout is the MCHBC voltage output, Ri is the resistance of the input filter, Li is the inductance of the input filter, ECHVDC is the energy storage in the high-voltage DC link, VLVDC is the voltage in the low side of the transformer, VHVDC is the voltage in the high side of the transformer, f <sup>S</sup> is the switching frequency of the IGBTs, LDAB is leakage inductance of the transformer, PDAB is the power required by the system, ϕ is the phase angle between the high- and low-voltage side of the transformer, ECLVDC is the stored energy in the capacitor, Vf is the voltage inverter, Rf is the filter resistance, Lf is the filter inductance, Cf is the filter capacitance, iLf is the current flowing out the inverter, Vo is the load voltage, and the

Once the SST mathematical formulation is defined, the drivers for each stage are

In this section, the SST is tested under different conditions. The analysis starts

The grid is disturbed with a sag in the SST input. The sag appears with a voltage reduction of 30%Vgrid during a time of 0:05 s (between 0:15≤t ≤0:20). It is con-

Input voltage Output voltage Power output Voltage modulation index for each converter

MCHBC DABC ILP LA¼B¼<sup>C</sup> ¼ 41:9 mH ½ � LDAB ¼ 1:29 mH ½ � Lf ¼ 286 mH ½ � CHVDC ¼ 311 ½ � μF CLVDC ¼ 585 ½ � μF Cf ¼ 22 ½ � μH

Stage Control transfer functions MCHBC GCIrec <sup>¼</sup> �000;005;933 s�<sup>1</sup>

DABC GCDAB <sup>¼</sup> <sup>0</sup>, 001188 sþ<sup>1</sup>

ILP GCIINV <sup>¼</sup> <sup>0</sup>, 002376 sþ<sup>1</sup>

<sup>1276</sup>x10�<sup>9</sup> s2þ00;002;988 s

<sup>8739</sup>x10�<sup>6</sup> s2þ01;025 s

<sup>9021</sup>x10�<sup>7</sup> s2þ0;005;288 s

0;002;464 s

GCVrec <sup>¼</sup> <sup>0</sup>, 0495 sþ<sup>1</sup> 001;314 s2þ3699 s

GCVINV <sup>¼</sup> <sup>1</sup>

terms dq0 represent the frames after applying Park transformation.

by describing the features of the SST, which are given in Tables 7–9.

sidered that there is a load of 400 kVA with a power factor of 0.85.

13. 8 kV 440 V 800 kVA 0.85

designed. These are shown in Table 6 [26].

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3. Applications: energy enhancement

Inductance and capacitance of each stage of the SST.

3.1 Voltage sag

Table 7.

Table 8.

Table 9.

128

Drivers of each stage of the SST.

SST nominal values.

Figure 4 reveals that even though the network voltage decreases (consequently the current injected also decreases), both the current and voltage on the load side are not affected. It is also observed that during the time the sag lasts, the inrush current increases. This increment is due to the SST control that keeps constant the output power, as shown in Figure 5.

The sag produces a decrement in the high DC voltage. To regulate it, the voltage modulation index (control) decreases. Its behavior is shown in Figure 6.

Figure 4. Sag distortion waveform behavior: (a) grid voltage, (b) load voltage, (c) grid current, and (d) load current.

Figure 5. Sag distortion power behavior at the SST (a) input and (b) output.

Figure 6. Control response to sag disturbance: (a) HVDC and its reference and (b) modulation index.
