2.1 OLTC conventional controller

OLTCs are one of the main voltage regulators in distribution systems. A tap changer equipped with an automatic control system usually regulates the transformer's secondary voltage to maintain an acceptable voltage near the load center. The tap changer mechanically varies the tap position from zero (no voltage compensation) to Nmax (maximum voltage compensation). This allows for changing the transformer's turn ratio in discrete steps; each step adjustment may take 3–20 seconds. Figure 1 displays the schematic diagram of an OLTC, where the tap changer is placed on the primary side. The tap changer is usually installed on the high voltage side of the transformer (i.e., the primary side in Figure 1) because of the low current of that side. A reversing switch is employed to change the polarity of the tap winding for positive and negative voltage compensation. In steady state, the transformer model can be given by

$$V\_2 = \frac{V\_1}{a} - I\_2 Z\_T(a) \tag{1}$$

series impedance (referred to the secondary side). The tap changer allows a to vary linearly; thus it can be expressed in terms of the nominal turn ratio (i.e., a<sup>0</sup> ¼ 1:0):

where Δa is the change in a as a result of a step change in the tap position ni,

where ni is the present tap position and ni � 1 is the previous tap position. Δn is

where Tm denotes mechanical time delay which is required by the motor driver unit to change the tap position by only one step and b is the control signal that is

0 for t≤Td : e ¼ arbitrary

1 for t>Td : e ¼ 1 �1 for t>Td : e ¼ �1

where Td is the time delay introduced by the OLTC controller and e is the output

0 for j j ΔV ≤ DB 1 for ΔV>DB �1 for ΔV < � DB

The mechanical time delay (Tm) has a constant value; usually, it varies from 3 to 10 seconds, and ΔV is the voltage error. In some models of the OLTC, the controller

However, Td is usually variable and depends on the voltage error and the con-

DB

Td ¼ τ<sup>0</sup>

applied to the tap-changing mechanism (see Figure 2) and is given by

0 for t≤ Tm : b ¼ arbitrary 1 for t>Tm : b ¼ �1 �1 for t>Tm : b ¼ 1

the change in the tap position which is defined by

8 ><

>:

8 ><

>:

e ¼

The schematic diagram of the conventional discrete control of the OLTC.

8 ><

>:

Δn ¼

b ¼

of the hysteresis controller, that is,

time delay (Td) is considered constant:

troller's dead band DB [4]:

Figure 2.

55

which is given by

Voltage Regulation in Smart Grids

DOI: http://dx.doi.org/10.5772/intechopen.85108

a ¼ a<sup>0</sup> þ niΔa (2)

ni ¼ ni�<sup>1</sup> þ Δn (3)

Td ¼ τ<sup>0</sup> (7)

j j <sup>Δ</sup><sup>V</sup> (8)

(4)

(5)

(6)

where V1 and V2 are primary and secondary voltages, respectively, I2 is secondary current, a denotes the transformer's tap ratio, and ZT (a) is the transformer

Figure 1. Transformer with tap changer.

2. Background

One of the main objectives of electric utilities is to maintain the grid voltage within standard levels to guarantee customers'satisfaction. Many equipment are deployed in the grid, such as OLTCs and capacitor banks, to properly fulfill this objective. In general, voltage regulation in a smart grid can be classified as local or communication-assisted [3]. The local voltage regulation is referred to as the conventional control, where the reference values and measurements for voltage control are locally determined. In this section, the fundamentals of the conventional control

OLTCs are one of the main voltage regulators in distribution systems. A tap changer equipped with an automatic control system usually regulates the transformer's secondary voltage to maintain an acceptable voltage near the load center. The tap changer mechanically varies the tap position from zero (no voltage compensation) to Nmax (maximum voltage compensation). This allows for changing the transformer's turn ratio in discrete steps; each step adjustment may take 3–20 seconds. Figure 1 displays the schematic diagram of an OLTC, where the tap changer is placed on the primary side. The tap changer is usually installed on the high voltage side of the transformer (i.e., the primary side in Figure 1) because of the low current of that side. A reversing switch is employed to change the polarity of the tap winding for positive and negative voltage compensation. In steady state, the trans-

<sup>V</sup><sup>2</sup> <sup>¼</sup> <sup>V</sup><sup>1</sup>

where V1 and V2 are primary and secondary voltages, respectively, I2 is secondary current, a denotes the transformer's tap ratio, and ZT (a) is the transformer

<sup>a</sup> � <sup>I</sup>2ZTð Þ <sup>a</sup> (1)

of OLTC and inverter-interfaced DGs are explained.

2.1 OLTC conventional controller

Research Trends and Challenges in Smart Grids

former model can be given by

Figure 1.

54

Transformer with tap changer.

series impedance (referred to the secondary side). The tap changer allows a to vary linearly; thus it can be expressed in terms of the nominal turn ratio (i.e., a<sup>0</sup> ¼ 1:0):

$$
\mathfrak{a} = \mathfrak{a}\_0 + \mathfrak{n}\_i \Delta \mathfrak{a} \tag{2}
$$

where Δa is the change in a as a result of a step change in the tap position ni, which is given by

$$n\_i = n\_{i-1} + \Delta n \tag{3}$$

where ni is the present tap position and ni � 1 is the previous tap position. Δn is the change in the tap position which is defined by

$$
\Delta n = \begin{cases} \begin{array}{llll} 0 & \text{for} & t \le T\_m \ & : & b = arbitrary \\ \mathbf{1} & \text{for} & t > T\_m \ & : & b = -1 \\ -\mathbf{1} & \text{for} & t > T\_m \ & : & b = \mathbf{1} \end{array} \end{cases} \tag{4}$$

where Tm denotes mechanical time delay which is required by the motor driver unit to change the tap position by only one step and b is the control signal that is applied to the tap-changing mechanism (see Figure 2) and is given by

$$b = \begin{cases} \begin{array}{llll} 0 & \text{for} & t \leq T\_d \ & : & e = arbitrary \\ 1 & \text{for} & t > T\_d \ & : & e = 1 \\ -1 & \text{for} & t > T\_d \ & : & e = -1 \end{array} \end{cases} \tag{5}$$

where Td is the time delay introduced by the OLTC controller and e is the output of the hysteresis controller, that is,

$$e = \begin{cases} 0 & for \quad |\Delta V| \le DB \\ 1 & for \quad \Delta V > DB \\ -1 & for \quad \Delta V < -DB \end{cases} \tag{6}$$

The mechanical time delay (Tm) has a constant value; usually, it varies from 3 to 10 seconds, and ΔV is the voltage error. In some models of the OLTC, the controller time delay (Td) is considered constant:

$$T\_d = \tau\_0 \tag{7}$$

However, Td is usually variable and depends on the voltage error and the controller's dead band DB [4]:

$$T\_d = \tau\_0 \frac{DB}{|\Delta V|}\tag{8}$$

Figure 2. The schematic diagram of the conventional discrete control of the OLTC.

Td is inversely proportional to the voltage error ΔV to avoid unnecessary operation during transient voltages and temporary load disturbances. DB must be greater than Δa to ensure stability when the regulated voltage approaches the reference valueVref ; otherwise, the OLTC will suffer from hunting. Vref is typically between 0.95 p.u. and 1.0 p.u. since it determines the steady-state voltage near the load center (Vk).

### 2.2 Conventional voltage control of inverter-based DGs

Energy processing strategies for inverter-based DGs typically involve two cascaded loops: inner and outer. The inner loop is a current control loop, which regulates the DG inverter current in the d � q reference frame. The outer control loop, on the other hand, can fulfill different control objectives depending on the hosing grid, such as voltage regulation and power management control.

Figure 3 shows an inverter-based DG that is controlled in the current injection mode, which is the typical strategy adopted with RES. A DG inverter model in the d � q synchronous frame represents the dynamics of the interfacing LC filter [5], that is,

$$L\_f \frac{dI\_d}{dt} = -R\_f I\_d + V\_d - V\_{ad} + aL\_f I\_q \tag{9}$$

$$L\_f \frac{dI\_q}{dt} = -R\_f I\_q + V\_q - V\_{oq} - \alpha L\_f I\_d \tag{10}$$

$$\mathbf{C}\_{f}\frac{d\mathbf{V}\_{od}}{dt} = I\_{d} - I\_{od} + a\mathbf{C}\_{f}\mathbf{V}\mathbf{q}\tag{11}$$

$$\mathbf{C}\_{f}\frac{dV\_{oq}}{dt} = I\_{q} - I\_{oq} - a\mathbf{C}\_{f}Vod\tag{12}$$

$$
\rho = \frac{d\theta}{dt} \tag{13}
$$

inverter terminal voltage and DG voltage at the PCC, respectively; Rf , Lf , and Cf are the resistance, inductance, and capacitance of the DG interfacing filter, respec-

The current equations, that is, (9) and (10), are coupled through the ωLfIq and �ωLfId terms. For independent control of both the Id and Iqcurrents, the decoupled

dt ¼ �RfId <sup>þ</sup> <sup>V</sup><sup>0</sup>

dt ¼ �RfIq <sup>þ</sup> <sup>V</sup><sup>0</sup>

Equations (16) and (17) represent decoupled first-order differential equations for Id and Iq, respectively. Therefore, PI current controllers can be designed based on the transfer functions derived from (16) and (17). If the gains of the PI current

> Kip <sup>¼</sup> Lf τi

8 >><

>>:

<sup>d</sup> ð Þ<sup>s</sup> <sup>¼</sup> Iqð Þ<sup>s</sup> I ref

Idð Þs I ref

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

! r

� � q

þ i ref q � �<sup>2</sup>

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi M<sup>2</sup> <sup>d</sup> <sup>þ</sup> <sup>M</sup><sup>2</sup> q

i ref d � �<sup>2</sup> ,

Kii <sup>¼</sup> Rf τi

then the equivalent closed-loop transfer functions for the current loops can be

<sup>q</sup> ð Þ<sup>s</sup> <sup>¼</sup> <sup>1</sup>

where τ<sup>i</sup> is the time constant of the closed-loop system. The vector magnitude of

maximum allowable current, typically 20% greater than the rated current of the inverter [5], in order to provide overcurrent protection. The vector magnitude of

u. so that DG operates in a linear modulation region. Figure 3 shows the vector magnitude limiter, which implies a limit on the magnitude of j j M without a change

DG output power. In the synchronous d � q frame, the output active PG and reac-

PG ¼ 1:5 VodId þ VoqIq

QG ¼ 1:5 VoqId � VodIq

ref <sup>d</sup> and I

ref

� � (20)

� � (21)

<sup>d</sup> ¼ Vd � Vod þ ωLfIq (14)

<sup>q</sup> ¼ Vq � Voq � ωLfId (15)

<sup>d</sup> (16)

<sup>q</sup> (17)

<sup>τ</sup>is <sup>þ</sup> <sup>1</sup> (19)

should be limited according to the

should also be limited to j j M max ¼ 1:0 p.

<sup>q</sup> , is usually affiliated to the

<sup>d</sup> and

(18)

terms must be eliminated, which can be accomplished if new variables V<sup>0</sup>

V0

V0

Substituting from (14) and (15) into (9) and (10) yields.

Lf dId

Lf dIq

tively; and ω is the grid frequency.

DOI: http://dx.doi.org/10.5772/intechopen.85108

Voltage Regulation in Smart Grids

V0

<sup>q</sup>are defined by

controllers are selected as

given by

the reference current

the modulation index j j M ¼

tive QG powers are given by

57

in the phase angle between Md andMq.

Determination of the reference currents, I

where Idq and Iodq represent the d � qcomponents of the inverter output current and DG current at the PCC, respectively; Vdq and Vodq are the components of the

Figure 3. Power circuit and current control diagram for inverter-based DG.

Td is inversely proportional to the voltage error ΔV to avoid unnecessary oper-

Energy processing strategies for inverter-based DGs typically involve two cas-

Figure 3 shows an inverter-based DG that is controlled in the current injection mode, which is the typical strategy adopted with RES. A DG inverter model in the d � q synchronous frame represents the dynamics of the interfacing LC filter [5],

<sup>ω</sup> <sup>¼</sup> <sup>d</sup><sup>θ</sup>

where Idq and Iodq represent the d � qcomponents of the inverter output current and DG current at the PCC, respectively; Vdq and Vodq are the components of the

dt ¼ �RfId <sup>þ</sup> Vd � Vod <sup>þ</sup> <sup>ω</sup>LfIq (9)

dt ¼ �RfIq <sup>þ</sup> Vq � Voq � <sup>ω</sup>LfId (10)

dt <sup>¼</sup> Id � Iod <sup>þ</sup> <sup>ω</sup>CfVoq (11)

dt <sup>¼</sup> Iq � Ioq � <sup>ω</sup>CfVod (12)

dt (13)

caded loops: inner and outer. The inner loop is a current control loop, which regulates the DG inverter current in the d � q reference frame. The outer control loop, on the other hand, can fulfill different control objectives depending on the

hosing grid, such as voltage regulation and power management control.

ation during transient voltages and temporary load disturbances. DB must be greater than Δa to ensure stability when the regulated voltage approaches the reference valueVref ; otherwise, the OLTC will suffer from hunting. Vref is typically between 0.95 p.u. and 1.0 p.u. since it determines the steady-state voltage near the

2.2 Conventional voltage control of inverter-based DGs

Research Trends and Challenges in Smart Grids

Lf dId

Lf dIq

Power circuit and current control diagram for inverter-based DG.

Cf dVod

Cf dVoq

load center (Vk).

that is,

Figure 3.

56

inverter terminal voltage and DG voltage at the PCC, respectively; Rf , Lf , and Cf are the resistance, inductance, and capacitance of the DG interfacing filter, respectively; and ω is the grid frequency.

The current equations, that is, (9) and (10), are coupled through the ωLfIq and �ωLfId terms. For independent control of both the Id and Iqcurrents, the decoupled terms must be eliminated, which can be accomplished if new variables V<sup>0</sup> <sup>d</sup> and V0 <sup>q</sup>are defined by

$$V\_d' = V\_d - V\_{ad} + aL\_f I\_q \tag{14}$$

$$\mathbf{V}'\_{q} = \mathbf{V}\_{q} - \mathbf{V}\_{\alpha q} - \alpha \mathbf{L}\_{f} \mathbf{I}\_{d} \tag{15}$$

Substituting from (14) and (15) into (9) and (10) yields.

$$L\_f \frac{dI\_d}{dt} = -R\_f I\_d + V\_d' \tag{16}$$

$$L\_f \frac{dI\_q}{dt} = -R\_f I\_q + V\_q' \tag{17}$$

Equations (16) and (17) represent decoupled first-order differential equations for Id and Iq, respectively. Therefore, PI current controllers can be designed based on the transfer functions derived from (16) and (17). If the gains of the PI current controllers are selected as

$$\begin{cases} K\_{ip} = \frac{L\_f}{\tau\_i} \\ K\_{ii} = \frac{R\_f}{\tau\_i} \end{cases} \tag{18}$$

then the equivalent closed-loop transfer functions for the current loops can be given by

$$\frac{I\_d(s)}{I\_d^{\tau \circ \f}(s)} = \frac{I\_q(s)}{I\_q^{\tau \circ \f}(s)} = \frac{1}{\tau\_i s + 1} \tag{19}$$

where τ<sup>i</sup> is the time constant of the closed-loop system. The vector magnitude of the reference current ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi i ref d � �<sup>2</sup> þ i ref q � �<sup>2</sup> ! r should be limited according to the maximum allowable current, typically 20% greater than the rated current of the inverter [5], in order to provide overcurrent protection. The vector magnitude of the modulation index j j M ¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi M<sup>2</sup> <sup>d</sup> <sup>þ</sup> <sup>M</sup><sup>2</sup> q � � q should also be limited to j j M max ¼ 1:0 p. u. so that DG operates in a linear modulation region. Figure 3 shows the vector magnitude limiter, which implies a limit on the magnitude of j j M without a change in the phase angle between Md andMq.

Determination of the reference currents, I ref <sup>d</sup> and I ref <sup>q</sup> , is usually affiliated to the DG output power. In the synchronous d � q frame, the output active PG and reactive QG powers are given by

$$P\_G = \mathbf{1.5} (V\_{od} I\_d + V\_{oq} I\_q) \tag{20}$$

$$Q\_G = \mathbf{1.5} (V\_{aq}I\_d - V\_{ad}I\_q) \tag{21}$$

For decoupled control of the active and reactive powers, a phase-locked loop (PLL) should be used for aligning Vod with the output voltage of phase a so that Voq ¼ 0 [6]. To determine I ref <sup>d</sup> , a maximum power point tracking (MPPT) algorithm along with a DC link voltage controller is employed [7]. On the other hand, I ref <sup>d</sup> can be calculated, as in (22), to regulate the output reactive power, thus, providing voltage support.

$$I\_d^{r\notin} = \frac{Q\_G^{r\notin}}{1.5V\_{od}} \tag{22}$$

The power angle (δ) is very small; hence (23) can be approximated by

Therefore, the voltage rise caused by the DG, that is, ΔVG ¼ VG � V2, is

PRR þ QRX VG

where PG and QG are the DG output active and reactive powers, respectively, while PL and Q <sup>L</sup> are the load active and reactive powers, respectively. It can be seen from (25) that the highest overvoltage happens when the DG generates its maximum power during a light load condition. This problem is mainly associated with

Due to the intermittency of RES and PEVs, the conventional control schemes for OLTC and DGs fail to provide proper voltage regulation. This shortcoming can be compensated using communication-assisted voltage regulation schemes. In the literature, the communication-assisted schemes fall under two approaches: distributed and centralized [3]. Both approaches involve investment in communication links and remote terminal units. The distributed (intelligent) approach is considered to be an expert-based control or model-free approach, which coordinates a variety of voltage control devices with the goal of providing effective and

nonoptimal voltage regulation with fewer communication requirements [9]. On the other hand, the centralized approach relies on a central point that monitors the system status and optimizes the operation of voltage control equipment. Typically, a centralized optimization problem is solved to dispatch the reactive power of different voltage control equipment based on (i) load forecasting and (ii) generation monitoring. Several solutions have been proposed in the literature to provide optimal reactive power dispatch for DGs [10–12]. In this section, the role of PEVs in

Figure 5 represents a simplified multi-feeder distribution network connected to a substation through an OLTC. The test network has a photovoltaic (PV)-based DG and a PEV parking lot, which are connected at different feeder terminals. Following the derivation of (25), the per-unit voltage deviation for both DG and PEV busses

Xf <sup>1</sup>

Xf <sup>2</sup>

ΔVPV ≈ PPV � PL<sup>1</sup> ð ÞRf <sup>1</sup> þ QPV � QL<sup>1</sup>

QPV, QEV, and QL are DG, PEV, and load reactive powers, respectively.

when the DG generates its maximum power during light loads and

ΔVEV ≈ � PEV þ PL<sup>2</sup> ð ÞRf <sup>2</sup> � QEV þ QL<sup>2</sup>

where PPV, PEV, and PL are DG, PEV, and load active powers, respectively, and

Equation (26) shows that two worst-case scenarios may occur: (i) overvoltage,

(ii) undervoltage, during a peak load demand and low DG output. The integration

given by.

ΔVG ≈ IRR cosð Þþ φ IRX sin ð Þ¼ φ

DOI: http://dx.doi.org/10.5772/intechopen.85108

Voltage Regulation in Smart Grids

the excessive reverse power flow caused by the DG.

3. Communication-assisted voltage regulation

optimal voltage regulation is explained as in [13].

3.1 PEV impact on voltage regulation

can be approximated by

59

VG ≈V<sup>2</sup> þ IRR cosð Þþ φ IRX sin ð Þ φ (24)

<sup>¼</sup> ð Þ PG � PL <sup>R</sup> <sup>þ</sup> QG � <sup>Q</sup> <sup>L</sup> ð Þ<sup>X</sup> VG

(25)

(26)

where Qref <sup>G</sup> is the reference value of the DG reactive power which can be determined using an outer voltage control loop or received from a communicationassisted voltage regulation scheme [8].

### 2.3 DG contribution to voltage violation

Usually, distribution networks have unidirectional power flow from the substation to customers. This leads to a descending voltage profile which may only suffer from an undervoltage near the load center, a problem typically tackled using OLTC and capacitor banks. On the other hand, DG integration into distribution networks makes the power flow bi-directional; thus an overvoltage problem may also occur. To understand the impact of DGs on the system voltage, the simplified distribution network in Figure 4(a) is used, where a DG is connected at a load bus. In this figure, R and X are the feeder resistance and reactance, respectively; IR is the feeder current; V1, V2 are the primary and secondary voltage of the distribution transformer, respectively; and VG is the DG output voltage. The phasor diagram of the simplified distribution network is shown in Figure 4(b), in which δ is the power angle and φ is the phase shift between VG and IR.

Using the phasor diagram, the relation between the DG voltage and V2 can be formulated:

$$\begin{split} V\_G' &= \left[ V\_2 + I\_R R \cos \left( \wp \right) + I\_R X \sin \left( \wp \right) \right] \\ &= V\_G \cos \left( \delta \right) \end{split} \tag{23}$$

Figure 4. Simplified distribution network with DG. (a) Single-line diagram and (b) phasor diagram.

For decoupled control of the active and reactive powers, a phase-locked loop (PLL) should be used for aligning Vod with the output voltage of phase a so that

along with a DC link voltage controller is employed [7]. On the other hand, I

I ref <sup>d</sup> <sup>¼</sup> <sup>Q</sup>ref G 1:5Vod

be calculated, as in (22), to regulate the output reactive power, thus, providing

mined using an outer voltage control loop or received from a communication-

Usually, distribution networks have unidirectional power flow from the substation to customers. This leads to a descending voltage profile which may only suffer from an undervoltage near the load center, a problem typically tackled using OLTC and capacitor banks. On the other hand, DG integration into distribution networks makes the power flow bi-directional; thus an overvoltage problem may also occur. To understand the impact of DGs on the system voltage, the simplified distribution network in Figure 4(a) is used, where a DG is connected at a load bus. In this figure, R and X are the feeder resistance and reactance, respectively; IR is the feeder current; V1, V2 are the primary and secondary voltage of the distribution transformer, respectively; and VG is the DG output voltage. The phasor diagram of the simplified distribution network is shown in Figure 4(b), in which δ is the power

Using the phasor diagram, the relation between the DG voltage and V2 can be

<sup>G</sup> ¼ ½ � V<sup>2</sup> þ IRR cosð Þþ φ IRX sin ð Þ φ

<sup>G</sup> is the reference value of the DG reactive power which can be deter-

<sup>d</sup> , a maximum power point tracking (MPPT) algorithm

ref <sup>d</sup> can

(22)

(23)

ref

Voq ¼ 0 [6]. To determine I

Research Trends and Challenges in Smart Grids

assisted voltage regulation scheme [8].

2.3 DG contribution to voltage violation

angle and φ is the phase shift between VG and IR.

V0

¼ VG cosð Þδ

Simplified distribution network with DG. (a) Single-line diagram and (b) phasor diagram.

voltage support.

where Qref

formulated:

Figure 4.

58

The power angle (δ) is very small; hence (23) can be approximated by

$$V\_G \approx V\_2 + I\_R R \cos\left(\varphi\right) + I\_R X \sin\left(\varphi\right) \tag{24}$$

Therefore, the voltage rise caused by the DG, that is, ΔVG ¼ VG � V2, is given by.

$$
\Delta V\_G \approx I\_R R \cos \left(\rho\right) + I\_R X \sin \left(\rho\right) = \frac{P\_R R + Q\_R X}{V\_G} = \frac{(P\_G - P\_L)R + (Q\_G - Q\_L)X}{V\_G} \tag{25}
$$

where PG and QG are the DG output active and reactive powers, respectively, while PL and Q <sup>L</sup> are the load active and reactive powers, respectively. It can be seen from (25) that the highest overvoltage happens when the DG generates its maximum power during a light load condition. This problem is mainly associated with the excessive reverse power flow caused by the DG.
