Table 6. Description of each controller SST stage.

The deduction of each formulation is presented in [26], where iLi is the current flowing into the converter, Vgrid is the voltage of the grid, m represents the modulation index, Vrout is the MCHBC voltage output, Ri is the resistance of the input filter, Li is the inductance of the input filter, ECHVDC is the energy storage in the high-voltage DC link, VLVDC is the voltage in the low side of the transformer, VHVDC is the voltage in the high side of the transformer, f <sup>S</sup> is the switching frequency of the IGBTs, LDAB is leakage inductance of the transformer, PDAB is the power required by the system, ϕ is the phase angle between the high- and low-voltage side of the transformer, ECLVDC is the stored energy in the capacitor, Vf is the voltage inverter, Rf is the filter resistance, Lf is the filter inductance, Cf is the filter capacitance, iLf is the current flowing out the inverter, Vo is the load voltage, and the terms dq0 represent the frames after applying Park transformation.

Figure 4 reveals that even though the network voltage decreases (consequently the current injected also decreases), both the current and voltage on the load side are not affected. It is also observed that during the time the sag lasts, the inrush current increases. This increment is due to the SST control that keeps constant the

The sag produces a decrement in the high DC voltage. To regulate it, the voltage

Sag distortion waveform behavior: (a) grid voltage, (b) load voltage, (c) grid current, and (d) load current.

modulation index (control) decreases. Its behavior is shown in Figure 6.

output power, as shown in Figure 5.

DOI: http://dx.doi.org/10.5772/intechopen.84345

Solid-State Transformer for Energy Efficiency Enhancement

Figure 4.

Figure 5.

Figure 6.

129

Sag distortion power behavior at the SST (a) input and (b) output.

Control response to sag disturbance: (a) HVDC and its reference and (b) modulation index.

Once the SST mathematical formulation is defined, the drivers for each stage are designed. These are shown in Table 6 [26].
