**3. Simulation methodology**

the short channel effects (SCE) such as subthreshold leakage rise significantly and became a major concern in scaling FinFET architecture. As per international technology roadmap for semiconductor (ITRS 2015) prediction, the contacted gate pitch (CGP) in 7 nm node transistor would be ~42 nm, making a gate length of less than 15 nm [8]. Although the FinFET has gate wrapping around the channel, at these shorter dimensions, a much stronger gate control is required. Therefore, gate-all-around (GAA) architecture has emerged as an alternative to FinFET [9]. The gate in NW covered all over around silicon channel providing a stronger control, therefore preventing more unwanted leakages. However, reduction of effective width (Weff) in NW reduces the current driving capacity significantly. Although the drive current in NW can be increased by stacking multiple wires per fin, however, a taller fin device increases parasitic capacitances which may limit the benefit of scaling [10]. Though numerous studies have been carried out for analyzing the intrinsic and parasitic capacitance [11–14], however, there is still a requirement for an extensive analysis to model the GAA-NW's major parasitic components. Thus, this chapter deals with the capacitance model of a GAA-NW transistor as

To continue Moore's law, transistor sizes are scaled down to the 7 nm node (N7) and 5 nm node (N5) specifications [15, 16]. A contacted gate pitch (CGP) of 42 and 32 nm were used

(D7) and 5 nm (D5) was considered in all the N7 and N5 specifications [10]. Channel material for n-channel and p-channel GAA-NW was considered with Si and Si50Ge50, respectively. An epitaxial-shaped source (S) and drain (D) regions were used as contacts. The S/D regions were

**Figure 1.** Compact GAA-nanowire transistor with cross-sectional views. (a) Compact NW device. (b) Cross-sectional

) of 14 and 10 nm with a wire diameter of 7

for both n-channel and p-channel

well as the overall scaling performances at ring oscillator circuits.

in both the N7 and N5 devices. Gate length (L<sup>g</sup>

doped with an active doping concentration of 3 × 10<sup>20</sup>/cm<sup>3</sup>

**2. GAA-NW device**

76 Nanowires - Synthesis, Properties and Applications

views.

To estimate various parasitic capacitances in a GAA-NW and their impacts on overall scaling performances at a higher frequency, a TCAD-based compact model study was performed. **Figure 2** shows a flow diagram used to analyze the DC and AC performances of the scaled GAA-NW transistor.

A two-stacked GAA-NW transistor was implemented using the Sprocess module of TCAD tool Sentaurus [17]. Given a continuous channel in FinFET, the selective region was etched away to form a round-shaped NW channel [18]. The 7 nm width-based FinFET transformed into the 7 nm diameter-based GAA-NW. Then the diameter and the gate length of NW were scaled down further to 5 and 10 nm, respectively [10]. All the parameters for device simulation were considered similar to the default 7 nm FinFET model [17].

## **3.1. Subthreshold current estimation**

Electrical performances were estimated separately for both the off-state and for the on-state conditions. The Sdevice [19] simulation with Shockley-Read-Hall (SRH), auger, band-to-band tunneling (BTBT) recombination, bandgap narrowing, anisotropic density gradient, interface charge, mobility model with multivalley correction, thin inversion layer correction with highk dielectric and quantum correction for the inversion layer were used to obtain the properties such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). Then, these

**Figure 2.** Flow diagram describes the TACD-based compact model of GAA-NW.

intrinsic properties (SS and DIBL) for different gate lengths, wire diameters and vertical pitches were fitted into the BSIM-CMG model [20]. Thus the fitted model provided subthreshold characteristics of a NW used for circuit-level simulations.

#### **3.2. The drive current estimation**

To estimate the on-state drive current, the ballistic flow has been considered along with drift-diffusion currents. As the channel length in N7 and N5 devices was scaled down to the carrier's mean free path range [21], the total drive current in NW was considered to be quasi-ballistic in nature [21]. The scattering-free ideal ballistic current is defined by Eq. (1), where q is the electronic charge, Vinj is the carrier's injection velocity and Ninv is the number of inversion charges. Sband [22] simulation provided these pure ballistic current characteristics for the different wire diameter and applied voltages

$$\mathbf{I}\_{\rm gal} = \mathbf{q} \times \mathbf{V}\_{\rm inj} \times \mathbf{N}\_{\rm inv} \tag{1}$$

both the n-channel and p-channel FinFET (tensile for NMOS and compressive for PMOS) are

**0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95**

**(b)**

**Ballistic Ratio (BR)**

**5 10 15 20 25 30 35 40 45**

**n-channel FinFET, Fwidth=7nm**

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099

> **Relaxed +0.5GPa +1.0GPa +1.5GPa +2.0GPa**

79

**Gate Length (nm)**

**2.39E-05**

**quasi-ballist-D7 quasi-ballist-D5**

**Quasi-ballistic Current**

**1.57E-05**

**0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8**

**~ -35%**

**Gate voltage(V)**

Next, for both the D5 and D7 devices, Sband simulated results such as carrier's injection velocity (Vinj) and the number of inversion charges (Ninv) were multiplied with electronic charge (q)

The variations of pure ballistic current (IBal) with the gate voltages are plotted in **Figure 5(a)** and after multiplying with BR, the obtained Iquasi-ball is shown in **Figure 5(b)**. Then, these quasiballistic characteristics were fitted into the BSIM-CMG model by fitting the mobility and carrier's velocity equations similar to [10]. As well as the intrinsic capacitances, interface trap and

The final drive current was obtained after including the front end of the line/mid of the line (FEOL/MOL) R&C parasitics into the BSIM-CMG model file [20]. Then, SPICE simulation was performed with this fitted model to obtain high-frequency properties for a 15th-stage ring

> **0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05**

**Iquasi-ballistic (A)**

**Figure 5.** Ballistic characteristics: (a) simulated ideal ballistic currents for both the D7 and D5 n-channel GAA-NW, (b)

other device properties for each NW were fitted into the BSIM-CMG model.

**-21%**

**Relaxed -0.5GPa -1.0GPa -1.5GPa -2.0GPa**

**Figure 4.** BR variation on varying channel stress in both the n-channel and p-channel FinFET's.

shown in **Figure 4(a)** and **(b)** [23–26].

**0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00**

**(a)**

**Ballistic Ratio (BR)**

to obtain the IBal, as plotted in **Figure 5(a)** [10].

**0.65, 3.1E-05 0.65, 2.4E-05**

quasi-ballistic currents considering the extracted BR.

**ballistic current\_D7 ballistic current\_D5**

**0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8**

**(a) (b)**

**Ballistic Current** 

**Gate voltage(V)**

**0.0E+00**

**1.0E-05**

**IBal (A)**

**2.0E-05**

**3.0E-05**

**4.0E-05**

**5 10 15 20 25 30 35 40 45**

**p-channel FinFET, Fwidth=7nm**

**Gate Length (nm)**

The quasi-ballistic current is represented by Eq. (2). Quasi-ballistic current is the product of pure ballistic current times the ballistic ratio. The ballistic ratio (BR) is the ratio between actual saturation current and ideal ballistic currents.

$$\mathbf{I}\_{\text{quast-ballstate}} = \mathbf{I}\_{\text{bal}} \times \mathbf{BR} \tag{2}$$

The ballistic current is independent of gate lengths, but BR is strongly dependent on the gate length, wire diameter and channel stress [21]. The BR for D7 NW was assumed to be similar to a 7 nm width-based FinFET although the NW might have lower BR than FinFET; since it strongly depends on the body configuration of the device, this possible small error on BR was further screened by electrostatics and access resistance [10]. The BR for D5 device (**Figure 3**) was extrapolated because it is expected to have significantly lower BR than the D7, similar to [10]. The variations of BR with the applied channel stress and channel length reduction for

**Figure 3.** Ballistic ration (BR) considered for the 7 nm diameter (D7) based of LNW and extrapolated BR for the 5 nm diameter (D5) GAA-NW.

**Figure 4.** BR variation on varying channel stress in both the n-channel and p-channel FinFET's.

intrinsic properties (SS and DIBL) for different gate lengths, wire diameters and vertical pitches were fitted into the BSIM-CMG model [20]. Thus the fitted model provided subthreshold char-

To estimate the on-state drive current, the ballistic flow has been considered along with drift-diffusion currents. As the channel length in N7 and N5 devices was scaled down to the carrier's mean free path range [21], the total drive current in NW was considered to be quasi-ballistic in nature [21]. The scattering-free ideal ballistic current is defined by Eq. (1), where q is the electronic charge, Vinj is the carrier's injection velocity and Ninv is the number of inversion charges. Sband [22] simulation provided these pure ballistic current characteristics

IBal = q × Vinj × Ninv (1)

The quasi-ballistic current is represented by Eq. (2). Quasi-ballistic current is the product of pure ballistic current times the ballistic ratio. The ballistic ratio (BR) is the ratio between actual

Iquasi−ballistic = IBal × BR (2)

The ballistic current is independent of gate lengths, but BR is strongly dependent on the gate length, wire diameter and channel stress [21]. The BR for D7 NW was assumed to be similar to a 7 nm width-based FinFET although the NW might have lower BR than FinFET; since it strongly depends on the body configuration of the device, this possible small error on BR was further screened by electrostatics and access resistance [10]. The BR for D5 device (**Figure 3**) was extrapolated because it is expected to have significantly lower BR than the D7, similar to [10]. The variations of BR with the applied channel stress and channel length reduction for

> **0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00**

**Figure 3.** Ballistic ration (BR) considered for the 7 nm diameter (D7) based of LNW and extrapolated BR for the 5 nm

**Ballistic Ratio**

**14, 0.782**

**-17.6%**

**14, 0.646**

**BR estimation for D5 NW** 

**7nm FinFET 5nm NW Si n-NWFET**

**5 10 15 20 25 30 35 40 45**

**Gate Length (nm)**

acteristics of a NW used for circuit-level simulations.

for the different wire diameter and applied voltages

saturation current and ideal ballistic currents.

diameter (D5) GAA-NW.

**3.2. The drive current estimation**

78 Nanowires - Synthesis, Properties and Applications

both the n-channel and p-channel FinFET (tensile for NMOS and compressive for PMOS) are shown in **Figure 4(a)** and **(b)** [23–26].

Next, for both the D5 and D7 devices, Sband simulated results such as carrier's injection velocity (Vinj) and the number of inversion charges (Ninv) were multiplied with electronic charge (q) to obtain the IBal, as plotted in **Figure 5(a)** [10].

The variations of pure ballistic current (IBal) with the gate voltages are plotted in **Figure 5(a)** and after multiplying with BR, the obtained Iquasi-ball is shown in **Figure 5(b)**. Then, these quasiballistic characteristics were fitted into the BSIM-CMG model by fitting the mobility and carrier's velocity equations similar to [10]. As well as the intrinsic capacitances, interface trap and other device properties for each NW were fitted into the BSIM-CMG model.

The final drive current was obtained after including the front end of the line/mid of the line (FEOL/MOL) R&C parasitics into the BSIM-CMG model file [20]. Then, SPICE simulation was performed with this fitted model to obtain high-frequency properties for a 15th-stage ring

**Figure 5.** Ballistic characteristics: (a) simulated ideal ballistic currents for both the D7 and D5 n-channel GAA-NW, (b) quasi-ballistic currents considering the extracted BR.

oscillator (RO) inverter circuits [27]. The ring oscillator setup is discussed in Section 6. All the simulations were performed at a fixed saturation drive voltage of 0.65 V and targeted off-state current (Ioff) of 3.5 nA per fin.
