**4. Parasitic capacitance estimation**

In this section, various parasitic capacitances associated with the metal gate of the NW transistors are discussed. We start with a basic fin channel architecture and then the formation of vertical nanosheet and then finally a GAA-NW with a higher vertical pitch. The vertical stacking of GAA-NW is essential for higher drive currents, but then again, the area associated with the wrapping metal lines is also increased as the fin height is increased, thus by doing so expected stronger parasitic capacitances.

> plotted in **Figure 7(b)**. Thus it can be concluded that up to a certain fin height with higher vertical pitch, NW stacking improves SS compared to a continuous fin channel; however, SS benefit may be limited by the lowered active channel area along with the increased

> **Figure 7.** Electrostatics for all the structures shown in **Figure 6**: (a) sub-threshold slope (SS) variations, (b) change in

**1.00 1.20 1.40 1.60 1.80 2.00**

**Ion**

**(mA/µm)**

**I II III IV V VI VII VIII IX**

**Ion\_Sat@7nm dia (mA/µm)**

81

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099

**(Lg=14nm)**

**Drift-Diffusion currents @Vdd=0.65V**

**Structure**

To analyze the overall parasitic capacitances on increasing the fin height, a schematic model depicting gate and source contact lines of a NW is shown in **Figure 8**. This model represents half of the NW architecture as a simplified model for calculating major capacitances associated with gate-to-source sidewall only. Similarly, the gate-to-drain sidewall capacitances can be calculated by reflecting this model as gate and drain contact sidewalls. At this point, the model represents four different major capacitances Cp1, Cp2, Cp3 and Cp4. The capacitance Cp1 represents the

parasitic capacitances.

**SS\_Sat (mV/dec)**

**I II III IV V VI VII VIII IX**

**Figure 8.** The capacitance model representing various parasitic capacitances.

**(a) (b)**

**SS\_Sat@7nm SS\_Sat@5nm**

**constant SS**

**Structure**

**4.2. The capacitance model**

currents flows due to the change in channel area.

#### **4.1. Vertical pitch variation (fin to NW)**

The transition from fin channel to GAA channel enables much stronger gate control. The bottom region of the channel fin was released and covered with the gate dielectric layers, as shown in **Figure 6(I)**, as a result of making the channel gate-all-around vertical nanosheet. Next, the single nanosheet was gradually transformed into two isolated NWs. Subsequently the vertical pitch between two NWs was increased from 7 to 19 nm (**Figure 6(III)–(IX)**). The transition from a single NS to multiple NW improves the subthreshold slope (SS) characteristic due to a stronger control in all-around architecture. The variations of subthreshold slope (SS) for all these structures have been plotted in **Figure 7(a)**. The SS values are improved by shifting from **Figure 6(I)**–**(V)** but remain constant after **Figure 6(VI)–(IX)**. This is because, once a uniform metal layer is processed between two NWs, the work function fluctuations might be stabilized, thus providing a maximum SS improvement. However, the variations of active channel area in **Figure 6(I)–(IV)** also affect the drive currents. The deviation of Ion (drift-diffusion) for all the structures was

**Figure 6.** The channel regions cross-sectional view for GAA transistors: Fin to vertical nanosheet (NS) to higher pitch nanowires (NW).

**Figure 7.** Electrostatics for all the structures shown in **Figure 6**: (a) sub-threshold slope (SS) variations, (b) change in currents flows due to the change in channel area.

plotted in **Figure 7(b)**. Thus it can be concluded that up to a certain fin height with higher vertical pitch, NW stacking improves SS compared to a continuous fin channel; however, SS benefit may be limited by the lowered active channel area along with the increased parasitic capacitances.

#### **4.2. The capacitance model**

oscillator (RO) inverter circuits [27]. The ring oscillator setup is discussed in Section 6. All the simulations were performed at a fixed saturation drive voltage of 0.65 V and targeted off-state

In this section, various parasitic capacitances associated with the metal gate of the NW transistors are discussed. We start with a basic fin channel architecture and then the formation of vertical nanosheet and then finally a GAA-NW with a higher vertical pitch. The vertical stacking of GAA-NW is essential for higher drive currents, but then again, the area associated with the wrapping metal lines is also increased as the fin height is increased, thus by doing so

The transition from fin channel to GAA channel enables much stronger gate control. The bottom region of the channel fin was released and covered with the gate dielectric layers, as shown in **Figure 6(I)**, as a result of making the channel gate-all-around vertical nanosheet. Next, the single nanosheet was gradually transformed into two isolated NWs. Subsequently the vertical pitch between two NWs was increased from 7 to 19 nm (**Figure 6(III)–(IX)**). The transition from a single NS to multiple NW improves the subthreshold slope (SS) characteristic due to a stronger control in all-around architecture. The variations of subthreshold slope (SS) for all these structures have been plotted in **Figure 7(a)**. The SS values are improved by shifting from **Figure 6(I)**–**(V)** but remain constant after **Figure 6(VI)–(IX)**. This is because, once a uniform metal layer is processed between two NWs, the work function fluctuations might be stabilized, thus providing a maximum SS improvement. However, the variations of active channel area in **Figure 6(I)–(IV)** also affect the drive currents. The deviation of Ion (drift-diffusion) for all the structures was

**Figure 6.** The channel regions cross-sectional view for GAA transistors: Fin to vertical nanosheet (NS) to higher pitch

current (Ioff) of 3.5 nA per fin.

80 Nanowires - Synthesis, Properties and Applications

**4. Parasitic capacitance estimation**

expected stronger parasitic capacitances.

**4.1. Vertical pitch variation (fin to NW)**

nanowires (NW).

To analyze the overall parasitic capacitances on increasing the fin height, a schematic model depicting gate and source contact lines of a NW is shown in **Figure 8**. This model represents half of the NW architecture as a simplified model for calculating major capacitances associated with gate-to-source sidewall only. Similarly, the gate-to-drain sidewall capacitances can be calculated by reflecting this model as gate and drain contact sidewalls. At this point, the model represents four different major capacitances Cp1, Cp2, Cp3 and Cp4. The capacitance Cp1 represents the

**Figure 8.** The capacitance model representing various parasitic capacitances.

wire fringe capacitances between the gate sidewall and all the nanowire surfaces. The spacer between the source contact and gate contact line was considered to be (Tspacer) 5 nm; this narrow spacing forms a strong parallel palate capacitance between gate and source. Therefore, the Cp2 represents the major parasitic capacitance between source sidewall and gate sidewall. The Cp2 is expected strongly dependent on NW's vertical pitch. The Cp3 is a fringe capacitance between the top gate surface and the source contact sidewall. And, Cp4 is an overlap (around 2 nm) capacitance between the nanowire and gate metal line. As we have seen previously, achieving a better electrostatic control with higher drive performance, the multiple stacking with higher vertical pitches are essential. However, both of these requirements increase the fin height as well as the Cp2. These two conflicting points need to be carefully optimized in both the process variation and for the best electrical performances. Among these capacitances, the Cp2 has a major contribution on overall device performance; thus, a detailed calculation methodology of Cp2 is presented here.

**4.4. The capacitance values**

**I II III IV V VI VII VIII IX**

**Wire Fringe Capacitance, Cp1** 

**Structure**

trends to increase continuously with the vertical pitch.

**1.00E-18**

**2.00E-18**

**3.00E-18**

**Capacitance (F)**

**4.00E-18**

**5.00E-18**

**Cp3 Cp4**

**Figure 11.** Fringe capacitance Cp3 and overlap capacitance Cp4 plotted in the same axis.

**1.00E-18 1.30E-18 1.60E-18 1.90E-18 2.20E-18 2.50E-18 2.80E-18**

**(a)**

**Capacitance (F)**

The comprehensive model formula presented in papers [11, 12] is used to calculate all the parasitic capacitances. Considering the initial values from [12] the capacitances, Cp1, Cp2, Cp3 and Cp4 are plotted for all the architectures presented in **Figure 6**. **Figure 10(a)** shows the Cp1 variations with the vertical pitches. As per the active area shape changes in **Figures 6(I)–(IV)**, a continuous increase of wire fringe capacitance Cp1 was observed; however, it remains constant after **Figure 6(V)–(IX)** for the higher vertical pitches. The values of parallel plate capacitance Cp2 were calculated after considering the effective area of S/G sidewalls and have been plotted in **Figure 10(b)**. It was observed that, unlike CP1, the values of Cp2 experience a continuous rise with increasing the vertical pitch from **Figure 6(I)–(IX)**. The overlap capacitance Cp3 remains constant as the top surface of gate metal and source contact is similar for all the structures (**Figure 11**). Cp4 shows increases till **Figure 6(IV)** and then remains constant for **Figure 6(V)–(IX)** (similar to the trend of Cp1). Although the overlapped region of 2 nm was considerably minor, the values of Cp4 show marginally higher than the values of fringe capacitance Cp1. Among all these

**Figure 10.** Parasitic capacitance values: (a) the initial increasing trend of Cp1 but remains same after structure IV, (b) Cp2

**1.00E-17 1.20E-17 1.40E-17 1.60E-17 1.80E-17 2.00E-17**

**(b)**

**I II III IV V VI VII VIII IX**

**Gate Top Fringe Capacitance, Cp3; Overlap Capacitance, Cp4** 

**Structure**

**Capacitance (F)**

**I II III IV V VI VII VIII IX**

**Parallel Plate Capacitance, Cp2** 

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099 83

**Structure**

**Cp1**

#### **4.3. Parallel plate capacitance (Cp2)**

In calculating the values of Cp2, a conventional parallel plate capacitance formula (εA/d) was used, wherein d and ε are the spacer width and permittivity, respectively. However, the active area (A) was calculated by considering a special development. Area (A) is the average of AREAsource and AREAgate wherein the AREAsource is the cross-marked source sidewall region after excluding the wire diameters as shown in **Figure 9**. And AREAgate is the cross-marked gate sidewall regions after excluding wire regions as well as by drawing a new perimeter related to the spacer width (Tspacer = 5 nm). This is mainly to exclude the contributions of continuous electric flux shared by two parallel plates through the connected NWs. The NW with two different wire diameters (7 nm = D7 and 5 nm = D5) was varied for different vertical pitches. Values of all the capacitances are calculated and presented in the next section.

**Figure 9.** The cross-sectional side view of source and gate contacts regions for calculating the active area in Cp2.

**Figure 10.** Parasitic capacitance values: (a) the initial increasing trend of Cp1 but remains same after structure IV, (b) Cp2 trends to increase continuously with the vertical pitch.

#### **4.4. The capacitance values**

wire fringe capacitances between the gate sidewall and all the nanowire surfaces. The spacer between the source contact and gate contact line was considered to be (Tspacer) 5 nm; this narrow spacing forms a strong parallel palate capacitance between gate and source. Therefore, the Cp2 represents the major parasitic capacitance between source sidewall and gate sidewall. The Cp2 is expected strongly dependent on NW's vertical pitch. The Cp3 is a fringe capacitance between the top gate surface and the source contact sidewall. And, Cp4 is an overlap (around 2 nm) capacitance between the nanowire and gate metal line. As we have seen previously, achieving a better electrostatic control with higher drive performance, the multiple stacking with higher vertical pitches are essential. However, both of these requirements increase the fin height as well as the Cp2. These two conflicting points need to be carefully optimized in both the process variation and for the best electrical performances. Among these capacitances, the Cp2 has a major contribution on overall device performance; thus, a detailed calculation methodology of Cp2 is

In calculating the values of Cp2, a conventional parallel plate capacitance formula (εA/d) was used, wherein d and ε are the spacer width and permittivity, respectively. However, the active area (A) was calculated by considering a special development. Area (A) is the average of AREAsource and AREAgate wherein the AREAsource is the cross-marked source sidewall region after excluding the wire diameters as shown in **Figure 9**. And AREAgate is the cross-marked gate sidewall regions after excluding wire regions as well as by drawing a new perimeter related to the spacer width (Tspacer = 5 nm). This is mainly to exclude the contributions of continuous electric flux shared by two parallel plates through the connected NWs. The NW with two different wire diameters (7 nm = D7 and 5 nm = D5) was varied for different vertical pitches. Values of all the capacitances are calculated and presented in the

**Figure 9.** The cross-sectional side view of source and gate contacts regions for calculating the active area in Cp2.

presented here.

next section.

**4.3. Parallel plate capacitance (Cp2)**

82 Nanowires - Synthesis, Properties and Applications

The comprehensive model formula presented in papers [11, 12] is used to calculate all the parasitic capacitances. Considering the initial values from [12] the capacitances, Cp1, Cp2, Cp3 and Cp4 are plotted for all the architectures presented in **Figure 6**. **Figure 10(a)** shows the Cp1 variations with the vertical pitches. As per the active area shape changes in **Figures 6(I)–(IV)**, a continuous increase of wire fringe capacitance Cp1 was observed; however, it remains constant after **Figure 6(V)–(IX)** for the higher vertical pitches. The values of parallel plate capacitance Cp2 were calculated after considering the effective area of S/G sidewalls and have been plotted in **Figure 10(b)**. It was observed that, unlike CP1, the values of Cp2 experience a continuous rise with increasing the vertical pitch from **Figure 6(I)–(IX)**. The overlap capacitance Cp3 remains constant as the top surface of gate metal and source contact is similar for all the structures (**Figure 11**). Cp4 shows increases till **Figure 6(IV)** and then remains constant for **Figure 6(V)–(IX)** (similar to the trend of Cp1). Although the overlapped region of 2 nm was considerably minor, the values of Cp4 show marginally higher than the values of fringe capacitance Cp1. Among all these

**Figure 11.** Fringe capacitance Cp3 and overlap capacitance Cp4 plotted in the same axis.

capacitances, Cp2 witnessed the most significant parasitics which is strongly dependent on fin height (vertical pitch). The value of Cp2 in **Figure 6(IX)** experienced a 22% higher capacitance than in **Figure 6(I)**.

#### **5. Ring oscillator simulation**

To benchmark the power performance and area gain for both the 7 nm diameter (D7)- and the 5 nm diameter (D5)-based GAA-NW, ring oscillator-level circuit simulations were performed [10]. Considering an inverter-based ring oscillator (RO), the RC delay and active power consumption as well as leakage power loss were calculated for each device. The ring oscillator (RO) with a 15-stage inverter was simulated using the SPICE simulation setup [27]. All the inverter stages had a fan out three and loaded with an optimum back end of the line (BEOL) load [28]. A median value of interconnect wire length for the critical path was loaded as the BEOL load including all parasitics in each inverter stage (50 CGP long) [28]. Then, a minimum delay optimization technique for a critical path was used to optimize the benefits of scaling D5 NW with various device configurations such as tighter vertical pitches and reduced gate lengths. The schematic of RO chain setup is shown in **Figure 12(a)**.

**Figure 12(b)** shows two-stacked D7 and D5 NW devices. Moving from D7 to D5 NW provides a 26% reduction in Weff as well as a 2 nm reduction in fin height (with an equal vertical pitch of 14 nm). Reducing the wire diameter from D7 to D5 offers only 2 mV/decade and 4 mV/V SS and DIBL improvements [10]. However, reduction in Weff delivers a significant reduction in overall dive current (~35%) [10]. This reduction in drive current might be improved by reducing the NW's gate length from 14 to 10 nm as well as by stacking more numbers of NW per fin with a reduced vertical pitch. On the other hand, stacking multiple NW increases parasitic capacitances along with the fin height. In this section, we have discussed the benefit of scaling on power and speed performance for both the 7 nm node (D7/D5 @N7) and the 5 nm node (D5@N5) GAA-NW.

$$\mathbf{P}\_{\text{dyn}} = \oint \mathbf{C}\_{\text{self}} \mathbf{V}\_{\text{dd}}^{-2} \tag{3}$$

**5.1. Power-delay optimization at 7 nm node (N7) dimensions**

devices based on the values obtained in [10].

power than the D7 device (**Figure 14(b)**).

**5.2. Power-delay optimization at 5 nm node (N5) dimensions**

**D7\_Delay\_2NNW\_14NWP\_Lg=14nm D5\_Delay\_2NNW\_14NWP\_Lg=14nm**

**(a) (b)**

**Figure 13.** Performance at 42 nm CGP: (a) delay for D7 and D5, (b) power for both D7 and D5 NW.

**0.3 0.4 0.5 0.6 0.7 0.8 0.9 1**

**Delay @ N7** 

**Vdd (V)**

frequency.

**Delay (ps)**

For all the 7 nm node (N7) specifications, a 42 nm CGP and 14 nm gate length were considered [10]. The dynamic power consumptions in an oscillator circuit were calculated based on the formula presented by Eq. (3), where Ceff is the effective load capacitance, f is the operating frequency and Vdd is the drive voltage. The RC delay was calculated in both the D7 and D5

The change in ring oscillator performances (RC delay and power loss) with the variation of Vdd from 0.4 to 0.9 V is displayed in **Figure 13**. The optimum delay versus drive voltage variation has been presented in **Figure 13(a)**. **Figure 13(b)** shows the active power loss for both the D7 and the D5 devices. Nearly a 20% rise in delay was observed for the D5 device compared to the D7 device, largely due to the reduction of drive currents. This reduced drive current (active area) in D5 device at the same applied voltage consumes less active power than the D7 device. However, the actual benefit can be visualized by plotting the power-delay product (energy) and leakage power loss for both the devices at a targeted

**Figure 14(a)** shows a change in energy consumption with the variations of frequency for both the devices. While operating at the same frequency, a significant rise in energy consumption was observed for the D5 device in comparison to the D7 device. To achieve an equal drive current in the D5 device always require a higher drive voltage in comparison to the D7 device, therefore consuming more energy leading to overall degraded performances. Besides that, while operating at the same frequency, the D5 device consumes more leakage

Although the electrostatics were improved marginally by reducing the nanowire's diameter, the overall performance was degraded at the same gate length. Therefore, in order to

**Active power (µW)**

**0.3 0.4 0.5 0.6 0.7 0.8 0.9 1**

**Vdd (V)**

**Dynamic Power @ N7**

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099 85

**D7\_Power\_2NNW\_14NWP D5\_Delay\_2NNW\_14NWP**

**@ Lg=14nm**

**Figure 12.** Ring oscillator testbench: (a) the inverter chain with FO three (b) cross-sectional NW showing the wire diameters and various specifications.

## **5.1. Power-delay optimization at 7 nm node (N7) dimensions**

capacitances, Cp2 witnessed the most significant parasitics which is strongly dependent on fin height (vertical pitch). The value of Cp2 in **Figure 6(IX)** experienced a 22% higher

To benchmark the power performance and area gain for both the 7 nm diameter (D7)- and the 5 nm diameter (D5)-based GAA-NW, ring oscillator-level circuit simulations were performed [10]. Considering an inverter-based ring oscillator (RO), the RC delay and active power consumption as well as leakage power loss were calculated for each device. The ring oscillator (RO) with a 15-stage inverter was simulated using the SPICE simulation setup [27]. All the inverter stages had a fan out three and loaded with an optimum back end of the line (BEOL) load [28]. A median value of interconnect wire length for the critical path was loaded as the BEOL load including all parasitics in each inverter stage (50 CGP long) [28]. Then, a minimum delay optimization technique for a critical path was used to optimize the benefits of scaling D5 NW with various device configurations such as tighter vertical pitches and reduced gate

**Figure 12(b)** shows two-stacked D7 and D5 NW devices. Moving from D7 to D5 NW provides a 26% reduction in Weff as well as a 2 nm reduction in fin height (with an equal vertical pitch of 14 nm). Reducing the wire diameter from D7 to D5 offers only 2 mV/decade and 4 mV/V SS and DIBL improvements [10]. However, reduction in Weff delivers a significant reduction in overall dive current (~35%) [10]. This reduction in drive current might be improved by reducing the NW's gate length from 14 to 10 nm as well as by stacking more numbers of NW per fin with a reduced vertical pitch. On the other hand, stacking multiple NW increases parasitic capacitances along with the fin height. In this section, we have discussed the benefit of scaling on power and speed performance for both the 7 nm node (D7/D5 @N7) and the 5 nm node

**Figure 12.** Ring oscillator testbench: (a) the inverter chain with FO three (b) cross-sectional NW showing the wire

(3)

lengths. The schematic of RO chain setup is shown in **Figure 12(a)**.

capacitance than in **Figure 6(I)**.

84 Nanowires - Synthesis, Properties and Applications

**5. Ring oscillator simulation**

(D5@N5) GAA-NW.

diameters and various specifications.

For all the 7 nm node (N7) specifications, a 42 nm CGP and 14 nm gate length were considered [10]. The dynamic power consumptions in an oscillator circuit were calculated based on the formula presented by Eq. (3), where Ceff is the effective load capacitance, f is the operating frequency and Vdd is the drive voltage. The RC delay was calculated in both the D7 and D5 devices based on the values obtained in [10].

The change in ring oscillator performances (RC delay and power loss) with the variation of Vdd from 0.4 to 0.9 V is displayed in **Figure 13**. The optimum delay versus drive voltage variation has been presented in **Figure 13(a)**. **Figure 13(b)** shows the active power loss for both the D7 and the D5 devices. Nearly a 20% rise in delay was observed for the D5 device compared to the D7 device, largely due to the reduction of drive currents. This reduced drive current (active area) in D5 device at the same applied voltage consumes less active power than the D7 device. However, the actual benefit can be visualized by plotting the power-delay product (energy) and leakage power loss for both the devices at a targeted frequency.

**Figure 14(a)** shows a change in energy consumption with the variations of frequency for both the devices. While operating at the same frequency, a significant rise in energy consumption was observed for the D5 device in comparison to the D7 device. To achieve an equal drive current in the D5 device always require a higher drive voltage in comparison to the D7 device, therefore consuming more energy leading to overall degraded performances. Besides that, while operating at the same frequency, the D5 device consumes more leakage power than the D7 device (**Figure 14(b)**).

#### **5.2. Power-delay optimization at 5 nm node (N5) dimensions**

Although the electrostatics were improved marginally by reducing the nanowire's diameter, the overall performance was degraded at the same gate length. Therefore, in order to

**Figure 13.** Performance at 42 nm CGP: (a) delay for D7 and D5, (b) power for both D7 and D5 NW.

**Figure 14.** Speed estimation for both the D7 and D5 NW with: (a) energy, (b) leakage power.

understand the overall benefit of scaling the wire diameter, we scaled the gate length from 14 to 10 nm. At the 10 nm gate length, the D5 showed a significant SS improvement compared to the D7 device (~10 mV/decade) [10]. A 10 nm gate length and 32 nm CGP were defined in D5 NW for the N5 specifications. Furthermore, the vertical pitch between two D5 NWs was reduced to 12 nm. To equalize the drive current, a four-stacked D5 NW at N5 specifications was compared with the two-stacked D7 NW at N7 specifications with increased BEOL load. In this case, the D5 shows an improved delay performance compared to the D7 device (**Figure 15(a)**). It should be noted that the D5 consumes more active power than the D7 device, as shown in **Figure 15(b)**. These minimal improvements in delay and power were further normalized by the energy versus speed performances, as shown in **Figure 16(a)**. **Figure 16(b)** shows the comparable leakage power characteristics for both the devices. Though, after considering taller fin in the D5 case, the power-delay product shows a comparable trend for low-frequency operation, however, it starts consuming more energy as it goes toward highfrequency operation. Now, with these NW configurations, a fin height in four-stacked D5

devices grows an additional 14 nm taller than a two-stacked D7 device adding an additional

**Figure 16.** Performance (D5@32 nm and D7@42 nm CGP): (a) energy consumed with intensifying frequency and (b)

**1.0 1.5 2.0 2.5 3.0 3.5**

**Leakage Power (nW)**

**20 25 30 35 40 45 50 55 60**

**Leakage Power\_D5@N5 D7\_Leakage\_14NWP\_2NNW@Lg=14nm D5\_Leakage\_12NWP\_4NNW@Lg=10nm**

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099 87

**Frequency (GHz)**

This flexibility shows the various aspects of scaling the D5 NW at a reduced wire pitch along with a greater number of NW (NNW) stacking. The overall performance benefits for a D5 device at N5 specifications and D7 device at N7 specifications were benchmarked with the variations in fin height. In the next section, we discussed the energy versus frequency for

A three-stacked D5 device delivers nearly equivalent drive currents with a two-stacked D7 device (only 6% loss) [10]. Subsequently, using D5 NW the drive current can be increased by stacking a greater number of wires per fin as the D5 may provide an area benefit with a 32 nm CGP. On the other hand, stacking more numbers of D5 NW will increase the parasitic capacitance (mainly Cp2) in comparison to the rise in gate capacitances (FEOL). The fin height variation with different NW stacking is shown in **Figure 17**. When moving from two-stacked to five-stacked NW D5 NW device, a 91% rise in drive current has been observed (18.03–34.44 μA), but this increases the total fin height by 90% (from 29 to 55 nm). On the other hand, moving from two-stacked to three-stacked D7 NW device (14 nm wire pitch) improves the drive currents by 30.5% (25.95–33.87 μA), but the fin height is increased by 45% (from 31 to 45 nm) only. The three-stacked D7 NW delivers almost equal drive currents with the five-stacked D5 NW at much lower fin height (33.87 and 34.44 μA). Thus, after considering all the parasitic impacts, a fair comparison is needed to observe the actual benefit of scaling wire

Optimizing the fin height in a NW transistor remains very sensitive to overall device design. Keeping this in mind, the total energy consumptions per device with increased fin height were plotted in **Figure 18** for both the D5 and D7 devices with multiple stacking. For both

parasitic capacitance as expected.

leakage power loss with the frequency deviations.

**5.3. Benchmarking D5 NW at N5 and D7 NW at N7**

**(a) (b)**

**Frequency (GHz)** 

**25 30 35 40 45 50 55 60**

**Energy is ~ equivalent**

**Energy\_D5@N5 D7\_Energy\_14PNW\_2NNW@Lg=14nm D5\_Energy\_12PNW\_4NNW@Lg=10nm**

different NW alignments.

**Energy (µW\*ps)**

diameter (D5).

**Figure 15.** Performances (D5@32 nm and D7@42 nm CGP): (a) delay versus Vdd, (b) power versus Vdd.

**Figure 16.** Performance (D5@32 nm and D7@42 nm CGP): (a) energy consumed with intensifying frequency and (b) leakage power loss with the frequency deviations.

devices grows an additional 14 nm taller than a two-stacked D7 device adding an additional parasitic capacitance as expected.

This flexibility shows the various aspects of scaling the D5 NW at a reduced wire pitch along with a greater number of NW (NNW) stacking. The overall performance benefits for a D5 device at N5 specifications and D7 device at N7 specifications were benchmarked with the variations in fin height. In the next section, we discussed the energy versus frequency for different NW alignments.

## **5.3. Benchmarking D5 NW at N5 and D7 NW at N7**

understand the overall benefit of scaling the wire diameter, we scaled the gate length from 14 to 10 nm. At the 10 nm gate length, the D5 showed a significant SS improvement compared to the D7 device (~10 mV/decade) [10]. A 10 nm gate length and 32 nm CGP were defined in D5 NW for the N5 specifications. Furthermore, the vertical pitch between two D5 NWs was reduced to 12 nm. To equalize the drive current, a four-stacked D5 NW at N5 specifications was compared with the two-stacked D7 NW at N7 specifications with increased BEOL load. In this case, the D5 shows an improved delay performance compared to the D7 device (**Figure 15(a)**). It should be noted that the D5 consumes more active power than the D7 device, as shown in **Figure 15(b)**. These minimal improvements in delay and power were further normalized by the energy versus speed performances, as shown in **Figure 16(a)**. **Figure 16(b)** shows the comparable leakage power characteristics for both the devices. Though, after considering taller fin in the D5 case, the power-delay product shows a comparable trend for low-frequency operation, however, it starts consuming more energy as it goes toward highfrequency operation. Now, with these NW configurations, a fin height in four-stacked D5

**(a) (b)**

**Figure 14.** Speed estimation for both the D7 and D5 NW with: (a) energy, (b) leakage power.

**30 50 70 90 110 130 150**

**Energy @ N7**

**D7\_Energy\_2NNW\_14NWP D5\_Energy\_2NNW\_14NWP**

86 Nanowires - Synthesis, Properties and Applications

**@ Lg=14nm**

**Frequency (GHz)** 

**(a) (b)**

**Figure 15.** Performances (D5@32 nm and D7@42 nm CGP): (a) delay versus Vdd, (b) power versus Vdd.

**0.3 0.4 0.5 0.6 0.7 0.8 0.9 1**

**Delay\_D5@N5**

**D7\_Delay\_14NWP\_2NNW@Lg=14nm D5\_Delay\_12NWP\_4NNW@Lg=10nm**

**Vdd (V)**

**0**

**Delay (ps)**

**50**

**100**

**Energy (µW\*ps)**

**150**

**200**

**1.0 1.5 2.0 2.5 3.0 3.5**

**Active power (µW)**

**Leakage Power (nW)**

**30 50 70 90 110 130 150**

**0.3 0.4 0.5 0.6 0.7 0.8 0.9 1**

**Dynamic Power\_D5@N5 D7\_Power\_14PNW\_2NNW@Lg=14nm D5\_Power\_12PNW\_4NNW@Lg=10nm**

**Vdd (V)**

**Leakage Power @ N7**

**D7\_Leakage\_Power D5\_Leakage\_Power**

**Frequency (GHz)** 

A three-stacked D5 device delivers nearly equivalent drive currents with a two-stacked D7 device (only 6% loss) [10]. Subsequently, using D5 NW the drive current can be increased by stacking a greater number of wires per fin as the D5 may provide an area benefit with a 32 nm CGP. On the other hand, stacking more numbers of D5 NW will increase the parasitic capacitance (mainly Cp2) in comparison to the rise in gate capacitances (FEOL). The fin height variation with different NW stacking is shown in **Figure 17**. When moving from two-stacked to five-stacked NW D5 NW device, a 91% rise in drive current has been observed (18.03–34.44 μA), but this increases the total fin height by 90% (from 29 to 55 nm). On the other hand, moving from two-stacked to three-stacked D7 NW device (14 nm wire pitch) improves the drive currents by 30.5% (25.95–33.87 μA), but the fin height is increased by 45% (from 31 to 45 nm) only. The three-stacked D7 NW delivers almost equal drive currents with the five-stacked D5 NW at much lower fin height (33.87 and 34.44 μA). Thus, after considering all the parasitic impacts, a fair comparison is needed to observe the actual benefit of scaling wire diameter (D5).

Optimizing the fin height in a NW transistor remains very sensitive to overall device design. Keeping this in mind, the total energy consumptions per device with increased fin height were plotted in **Figure 18** for both the D5 and D7 devices with multiple stacking. For both

The variations of speed (frequency) with increasing the fin height for both D7 and D5 devices are plotted in **Figure 19**. At an identical fin height, the D7 device always delivers higher speed than the D5 device. Hence, considering both the D7 and D5 NW transistors, the fin height was increased by stacking single wire to five multiple wires. Until a three-stacked design for both the D7 and D5 NWs, a linear rise in frequency with fin height was observed. However, the frequency gets saturated with increasing fin height beyond the three-stacked NW design. Further rise in fin height will start degrading the frequency performance. This is mainly caused by the rise in parasitic capacitances. Generally, the capacitance loaded with a transistor is the sum of both intrinsic gate capacitance and FEOL parasitic capacitances. Increasing the fin height increases the total area of gate metal stack positioned next to a source and a drain contact lines. This effect remains hidden in both the D7 and D5 NWs up to a certain fin height. At the same fin height, the D7 drives have slightly higher speed in comparison to the D5 device as it has lower parasitic influence. Furthermore, increasing the fin height started degrading the total speed performance of D5 device quite early. Hence multiple stacking is

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099 89

Along with the speed, the total energy consumption with different frequency operations is also plotted in **Figure 20**. The energy consumptions are largely affected by the escalation of parasitic capacitances. Due to that reason, it starts consuming more energy while raising the operating frequency. Moving from single NW to five-stacked NW experiences an exponential rise in energy loss in both the devices. Although the single-stacked D5 NW consumes 27% lower energy than the single-stacked D7 NW, it also provides 20% reduction in speed performance. This gap however is quickly normalized while operating at higher

**5 15 25 35 45 55 65 75 85 95 105**

**3NW**

**2NW**

**Figure 19.** Frequency variations with the fin height from single stacked to five stacked NW.

**D5@N5**

**4NW 5NW D7@N7**

**D7\_Lg=14, 16PNW D7\_Lg=14, 14PNW D7\_Lg=14, 12PNW D5\_Lg=10, 16PNW D5\_Lg=10, 14PNW D5\_Lg=10, 12PNW D5\_Lg=10, 10PNW**

**4NW 5NW**

**Fin Height (nm)**

also a major limiter for providing a higher speed.

**20**

**25**

**30**

**35**

**40**

**Frequency (GHz)**

**45**

**50**

**55**

**60**

**Figure 17.** The cross-sectional NWs schematic showing upswing in fin heights with multiple stacking of NWs.

the D7 and D5, a single-stacked NW to a five-stacked NW was considered. Along with the multiple stacking, three different vertical pitches (16, 14 and 12 nm) were varied for the D7 device and four different pitches (16, 14, 12 and 10 nm) for the D5 device. A continuous rise in energy consumptions was observed while going from single NW to multiple NW in both the D7 and D5 devices. The fin height has been reduced by reducing the NW vertical pitch, thus shrinking the energy loss. It was observed that the D7 NW always consumes higher energy than the D5 NW at specific fin height. However, with a lowered fin height, D5 NW delivers lower drive currents which further reduces the overall device speed.

**Figure 18.** Variations of energy with varying fin height from single stacked to five stacked NW.

The variations of speed (frequency) with increasing the fin height for both D7 and D5 devices are plotted in **Figure 19**. At an identical fin height, the D7 device always delivers higher speed than the D5 device. Hence, considering both the D7 and D5 NW transistors, the fin height was increased by stacking single wire to five multiple wires. Until a three-stacked design for both the D7 and D5 NWs, a linear rise in frequency with fin height was observed. However, the frequency gets saturated with increasing fin height beyond the three-stacked NW design. Further rise in fin height will start degrading the frequency performance. This is mainly caused by the rise in parasitic capacitances. Generally, the capacitance loaded with a transistor is the sum of both intrinsic gate capacitance and FEOL parasitic capacitances. Increasing the fin height increases the total area of gate metal stack positioned next to a source and a drain contact lines. This effect remains hidden in both the D7 and D5 NWs up to a certain fin height. At the same fin height, the D7 drives have slightly higher speed in comparison to the D5 device as it has lower parasitic influence. Furthermore, increasing the fin height started degrading the total speed performance of D5 device quite early. Hence multiple stacking is also a major limiter for providing a higher speed.

Along with the speed, the total energy consumption with different frequency operations is also plotted in **Figure 20**. The energy consumptions are largely affected by the escalation of parasitic capacitances. Due to that reason, it starts consuming more energy while raising the operating frequency. Moving from single NW to five-stacked NW experiences an exponential rise in energy loss in both the devices. Although the single-stacked D5 NW consumes 27% lower energy than the single-stacked D7 NW, it also provides 20% reduction in speed performance. This gap however is quickly normalized while operating at higher

the D7 and D5, a single-stacked NW to a five-stacked NW was considered. Along with the multiple stacking, three different vertical pitches (16, 14 and 12 nm) were varied for the D7 device and four different pitches (16, 14, 12 and 10 nm) for the D5 device. A continuous rise in energy consumptions was observed while going from single NW to multiple NW in both the D7 and D5 devices. The fin height has been reduced by reducing the NW vertical pitch, thus shrinking the energy loss. It was observed that the D7 NW always consumes higher energy than the D5 NW at specific fin height. However, with a lowered fin height, D5 NW delivers

**5 15 25 35 45 55 65 75 85 95 105**

**Fin Height (nm)**

**D5@N5**

**5NW**

**4NW**

**Figure 17.** The cross-sectional NWs schematic showing upswing in fin heights with multiple stacking of NWs.

**35 nm**

**10nm**

**D7\_2NW D5\_2NW D5\_3NW D5\_4NW**

**14nm**

**10nm**

**45 nm**

**D5\_10PNW\_Lg=10 D5\_12PNW\_Lg=10 D5\_14PNW\_Lg=10 D5\_16PNW\_Lg=10 D7\_12PNW\_Lg=14 D7\_14PNW\_Lg=14 D7\_16PNW\_Lg=14**

**5NW**

**10nm**

**10nm 10nm 10nm**

**10nm**

**55 nm**

**D5\_5NW**

**10nm**

**10nm**

**10nm**

**10nm**

**10nm**

lower drive currents which further reduces the overall device speed.

**D7@N7**

**Figure 18.** Variations of energy with varying fin height from single stacked to five stacked NW.

**14nm**

**14nm**

**14nm**

88 Nanowires - Synthesis, Properties and Applications

**45nm**

**10nm**

**Energy (µW\*ps)** 

**D7\_3NW**

**31nm 10nm**

**29 nm**

**10nm**

**Figure 19.** Frequency variations with the fin height from single stacked to five stacked NW.

**Acknowledgements**

**Author details**

**References**

114-117

2008. pp. 128-129

Authors would like to thank Doyong Jang, Marie Garcia Bardon and Praveen Raghavan of

[1] Moore GE. Cramming more components onto integrated circuits. Electronics. 1965;**38**(8):

[2] Mistry K, Armstrong M, Auth C, Cea S, Coan T, Ghani T, Hoffmann T, et al. Delaying forever: Uniaxial strained silicon transistors in a 90 nm CMOS technology. In: Symposium

[3] Auth C, Cappellani A, Chun JS, Dalis A, Davis A, Ghani T, Glass G, et al. 45 nm high-k+ metal gate strain-enhanced transistors. In: 2008 Symposium on VLSI Technology. IEEE;

[4] Auth C, Allen C, Blattner A, Bergstrom D, Brazier M, Bost M, Buehler M, et al. A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: 2012 Symposium

[5] Wu SY, Lin CY, Chiang MC, Liaw JJ, Cheng JY, Yang SH, Chang SZ, et al. An enhanced 16 nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications. In: 2014 IEEE

[6] Natarajan S, Agostinelli M, Akbar S, Bost M, Bowonder A, Chikarmane V, Chouksey S, et al. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped intercon-

[7] Auth C, Aliyarukunju A, Asoro M, Bergstrom D, Bhagwat V, Birdsall J, Bisnik N, et al. A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local

SRAM cell size. In: 2014 IEEE

Parasitic Capacitances on Scaling Lateral Nanowire http://dx.doi.org/10.5772/intechopen.81099 91

IMEC for their valuable and special training on compact modeling.

Uttam Kumar Das\* and Tarun Kanti Bhattacharyya

on VLSI Technology; 2004. pp. 50-51

\*Address all correspondence to: uttamece.jgec@gmail.com

Indian Institute of Technology Kharagpur, Kharagpur, India

on VLSI Technology (VLSIT). IEEE; 2012. pp. 131-132

nects, self-aligned double patterning and a 0.0588 μm2

International Electron Devices Meeting (IEDM); 2014. pp. 3-7

International Electron Devices Meeting (IEDM). IEEE; 2014. pp. 3-1

**Figure 20.** Energy versus frequency variations for both the D7 and D5 NW transistors.

frequency. Around 45–50 GHz operation, the D5 device requires four- to five-stacked NW and starts consuming more energy than the two- to three-stacked D7 NW. We have observed that the D5 NW at N5 specification consumes lower energy at the low-frequency operations, but it starts consuming higher energy than the D7 device at high-frequency operation. Multiple stacking increases both on currents as well as parasitic losses. Thus, the NW with shorter fin height should be considered to achieve the benefit of scaling at low-frequency performance.

## **6. Conclusion**

The GAA lateral nanowire is a promising candidate for scaling beyond the FinFET technology. It provides superior electrostatic benefits such as better SS and DIBL at the shortest gate length. However, it has a very complex process as well as huge impacts of parasitics. The study conducted here was mainly focused on the effects of all the parasitic capacitances on overall device performance with scaling beyond the 7 nm node dimensions targeting the 5 nm node technology. The TCAD study compared the electrostatic performance and compact modeling which shows a basic inverter operation connected as a ring oscillator. A capacitance model was discussed considering the major parasitic components and their impacts on advance dimensional scaling. The compact modeling showed that reducing the wire diameter improved the electrostatics marginally but degraded the overall performance. Therefore, a deep analytical and experimental study is required to conclude the overall scaling benefits of GAA-NW transistor.
