**2. GAA-NW device**

To continue Moore's law, transistor sizes are scaled down to the 7 nm node (N7) and 5 nm node (N5) specifications [15, 16]. A contacted gate pitch (CGP) of 42 and 32 nm were used in both the N7 and N5 devices. Gate length (L<sup>g</sup> ) of 14 and 10 nm with a wire diameter of 7 (D7) and 5 nm (D5) was considered in all the N7 and N5 specifications [10]. Channel material for n-channel and p-channel GAA-NW was considered with Si and Si50Ge50, respectively. An epitaxial-shaped source (S) and drain (D) regions were used as contacts. The S/D regions were doped with an active doping concentration of 3 × 10<sup>20</sup>/cm<sup>3</sup> for both n-channel and p-channel

**Figure 1.** Compact GAA-nanowire transistor with cross-sectional views. (a) Compact NW device. (b) Cross-sectional views.

devices with a specific contact resistivity of 5 × 10−<sup>9</sup> Ωcm2 . Gate dielectric of 0.5 nm oxide and 1.5 nm high-k (HfO2 ) layers was used. A gate spacer of 5 nm thickness was applied to both the gate-to-source and gate-to-drain regions (relative permittivity, ε<sup>r</sup> = 4.4). A midpoint work function value for metal gate was used in both the devices during initial simulation. Considering a fixed NW pitch (NWP) of 14 and 10 nm offset, the two-stacked-NW device creates a fin height of 31 and 29 nm, respectively. Other specifications and setup for each device were considered similar to the reference [10, 15]. The simulated compact NW is shown in **Figure 1(a)** and a cross-sectional view showing inside details in **Figure 1(b)**.
