**4. Applications in neuromorphic computing**

Recent implementations of emerging computing capabilities leverage on the capability offered by non-volatile memory (NVM) storage and information processing. Two main approaches have been proposed:


Energy efficiency benefits of array computing have also been demonstrated with various technologies (including spin-torque oscillators) in relatively small-scale circuits. For example, in [89], a data clustering algorithm mapped to a memristive array was demonstrated. In [90], the FPAA architecture was used to implement neuronal array-based sparse coding, applicable in the early stages of visual processing. Furthermore, integration of memristors and an FPAA circuit was demonstrated in small scale in [91]. Cognitive computing algorithms, which can be mapped to array processing/associative memory architectures, have also been described [92–94]. However, hardware architectures and design tools to realize these algorithms energyefficiently on a relevant scale do not currently exist.

The challenge in the application of memristor technology for large-scale memory-based computing architectures is the development of new physical device models for memristor devices and analyzes the adaptation of algorithms with respect to device variation and scalability. Since the discovery of memristive behavior at the nanoscale at Hewlett Packard laboratories in 2008, the scientific community has devoted a large deal of efforts to derive suitable models that capture the nonlinear dynamics of memristors. Pickett's model is a reference model that is well suited for describing the physical mechanisms at the origin of memristor dynamics. Simplified versions aiming at fitting the behavior of Pickett's model are the TEAM and V-TEAM models, Biolek's model and the boundary condition model for a comprehensive review [95]. It is worth noting that such models are not oriented toward nonlinear circuit synthesis. In order to effectively analyze the dynamic behavior of memristors, and also in view of their simulation and emulation, it is fundamental to develop circuit memristor models, that is, models obtained by interconnecting basic nonlinear blocks. This will be pursue along the lines of the general method for device modeling in [96] and exploiting recent techniques for the identification of switching and PWA (piece-wise-affine) systems.

In this respect, metal electrode ions injection has also been proposed as a possible mechanism for the onset of switching, which would indicate the establishing of a CB mechanism [81]. Nevertheless, proofs of the actual onset of a VCM are provided through the observation of switching with C-AFM measurements, where no top electrode is present: analyses have been conducted both on the top surface of the anodic oxide [49], and on a lateral device, where no

Memristive nanotubes were also produced on titanium [86–88]. In these cases, either longer anodizing times (hours) and/or higher voltages (up to 120 V) are required, and thicker oxides, some hundreds of nanometers thick, are achieved. Yet, the limited adherence and mechanical stability of these oxides compared with compact ones, and the higher thickness introduced,

Recent implementations of emerging computing capabilities leverage on the capability offered by non-volatile memory (NVM) storage and information processing. Two main approaches

• Hybrid logic/memory integration: the logic and the memory layers are implemented in two different substrates or levels, typically an Application Specific Integrated Circuit (ASIC) is developed to emulate artificial neuron functionality while memory layers are integrated either on a separate chip or occupy a separated area. The main advantage lies in the improved communication bandwidth between the different logic and memory layers. • Logic-in-memory: memory elements are distributed in a circuit to play a role in the realization of the logic operations, aiming both at ultra-low power and highly expressive logic circuits. Thus, general-purpose computation functions can be implemented by configuring non-volatile switches. NVMs are naturally suited for performing implication logic instead than standard logic. Recently, stateful logic operations, for which memristor devices work as gates and latches that use resistance as a physical state variable, have been demon-

Energy efficiency benefits of array computing have also been demonstrated with various technologies (including spin-torque oscillators) in relatively small-scale circuits. For example, in [89], a data clustering algorithm mapped to a memristive array was demonstrated. In [90], the FPAA architecture was used to implement neuronal array-based sparse coding, applicable in the early stages of visual processing. Furthermore, integration of memristors and an FPAA circuit was demonstrated in small scale in [91]. Cognitive computing algorithms, which can be mapped to array processing/associative memory architectures, have also been described [92–94]. However, hardware architectures and design tools to realize these algorithms energy-

The challenge in the application of memristor technology for large-scale memory-based computing architectures is the development of new physical device models for memristor devices

electrode metals are available [85].

have been proposed:

strated [89].

make them less appealing for real applications.

54 Advances in Memristor Neural Networks – Modeling and Applications

**4. Applications in neuromorphic computing**

efficiently on a relevant scale do not currently exist.

There is an increasing interest in the implementation of oscillators using nanoscale devices as memristors. As remarked in [97], a source of controllable chaotic behavior that can be implemented by a single scalable electronic device and incorporated into a neural-inspired circuit may be an essential component of future computational systems. In this framework, the memristor is required to display a quasi-static voltage-current characteristic with a negative differential resistance (NDR). Various classes of relaxation oscillators displaying a tunable range of periodic and chaotic self-oscillations have been implemented during recent years and their importance in neuromorphic applications, such as pattern recognition and signal processing tasks in real time, have been demonstrated. They can also be used as core devices with a rich variety of nonlinear dynamics within the framework of reservoir computing architectures. Work so far has been mainly based on experimental and phenomenological observations of oscillations and complex phenomena, while a circuit model and a clear analytic understanding of the underlying nonlinear dynamics and bifurcations is basically missing. Recently, a new method, named Flux-Charge Analysis Method (FCAM), has been developed to effectively analyze a wide class of nonlinear circuits containing ideal memristors in the flux-charge domain [98]. FCAM permits to bring back the dynamic analysis to that of a lower-order circuit, with respect to that in the standard voltage-current domain, using flux and charge as state variables. This enables to obtain a clear picture of the dynamical behavior displayed by memristor circuits. In particular, some peculiar aspects, such as the presence of invariant manifolds and the coexistence of different dynamics for the same set of (fixed) circuit parameters, are singled out. Also, it is possible to assess the presence of a new interesting phenomenon of bifurcations which emerge without changing the system parameters, namely, bifurcations due to changing the initial conditions for the state variables for a fixed set of circuit parameters (BWP) [99]. Using FCAM, the dynamics of classes of oscillators and chaotic circuits with ideal memristors have been deeply analyzed assessing the occurrence of Hopf and period-doubling BWPs and quite rich complex dynamics. In addition, it has been shown that FCAM can be combined with techniques, such as the harmonic balance method citare, to effectively analyze and control such BWPs. Moreover, by suitably exploiting BWPs, it turned out that different chaotic dynamics in a class of Chua's oscillators can be programmed by means of suitable current or voltage pulses [100]. Synchronization aspects in arrays of coupled oscillators have been analyzed as well [101].
