4. ASIC I/O

In ASIC I/O design, ESD protection is integral in the definition and methodology. In the following section, this will be discussed.

4.3. I/O and ESD power clamp integration

network, providing improved ESD robustness.

4.4. Ground-to-ground ESD networks

4.5. Master/slave ESD systems

Figure 2. Master/slave ESD system.

allocating for the power pins, the VDD pin location (Figure 1).

ground-to-ground ESD networks can be placed in the VSS pin location.

ASIC power busses around the complete chip (Figure 3).

ASIC methodologies establish requirements for the frequency of placement of "power cells" and "ground cells" to support the I/O and core circuitry [2–4, 7, 8, 11–15]. This provided a perfect opportunity for ESD protection, since an "ESD power clamp" can be placed in the area

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At one time, prior to the invention of ESD power clamps, it was just as empty areas; it was realized that the ESD power clamps can be placed in these regions. As the frequency of placement of the ESD power clamps increases, the series resistance loss of the power bus or ground bus decreases; this allows for a lower resistance path for the current to flow through the complete

ESD networks are required between ground power rails for every independent domain. In an ASIC system, analog and digital circuits are in separate power domains [7, 8, 11–18]. These domains must be interconnected through ground-to-ground ESD networks. These networks must be bidirectional to allow current to flow in both directions. These networks do not have to be symmetric (e.g., m diodes in one direction and n diodes in the opposite direction). These

In some ASIC embodiments, the ESD power clamps are integrated across the entire system. In this type of system, there is one "master," which triggers the set of ESD power clamps on all in parallel (Figure 2) [2, 3, 7, 8]. A "master ESD power clamp" contains the trigger network that then sends a signal to turn on all the "slave ESD power clamps." This system has the advantage of turning on all ESD power clamps in parallel across the entire ASIC system, significantly lowering the "on-resistance" of the single ESD power clamp. The disadvantage of this system is an ESD signal bus (from the master clamp to the slave clamps) must be distributed with the

#### 4.1. I/O and ESD integration

In the definition of an ASIC I/O, the off-chip driver (OCD), the receiver, and ESD circuitry are co-designed to integrate the networks into a common physical space [7]. This requires planning in the methodology to allocate the right percentage of area for each of these elements. Different methodologies are used depending on the foundry or corporation.

#### 4.2. I/O and ESD design integration and synthesis

In one methodology, the ASIC system supported different off-chip driver (OCD) sizes by adjusting the number of MOSFET fingers that were connected. The number of MOSFET fingers used was the maximum driver strength for the I/O library providing different impedance as well. There are many options on what can be done in this methodology.

For example, there can be a 20, 30, and 50 Ω impedance OCD circuit offering, by attaching a different number of MOSFET fingers in a given I/O cell. In one method, the residual MOSFET OCD fingers were grounded and used as a "grounded gate NMOS" ESD network. In this case, the residual MOSFET fingers act as a natural ESD protection and utilize the "unused" section of the OCD. The advantage of this method is that the unused portion of the I/O is utilized. In a second embodiment, instead of grounding the residual MOSFET fingers, a dummy inverter load was attached to keep the residual fingers "off" or in a low logic state. Using a dummy inverter, the MOSFET gates that are not grounded, and "turn-on" from MOSFET snapback at the same impedance state as the MOSFET OCD. In this fashion, both the active and residual elements work together for ESD protection [7, 8].

Figure 1. RC-triggered ESD power clamp.

### 4.3. I/O and ESD power clamp integration

4. ASIC I/O

52 Digital Systems

following section, this will be discussed.

4.2. I/O and ESD design integration and synthesis

elements work together for ESD protection [7, 8].

Figure 1. RC-triggered ESD power clamp.

4.1. I/O and ESD integration

In ASIC I/O design, ESD protection is integral in the definition and methodology. In the

In the definition of an ASIC I/O, the off-chip driver (OCD), the receiver, and ESD circuitry are co-designed to integrate the networks into a common physical space [7]. This requires planning in the methodology to allocate the right percentage of area for each of these elements.

In one methodology, the ASIC system supported different off-chip driver (OCD) sizes by adjusting the number of MOSFET fingers that were connected. The number of MOSFET fingers used was the maximum driver strength for the I/O library providing different impedance as well. There are many options on what can be done in this methodology.

For example, there can be a 20, 30, and 50 Ω impedance OCD circuit offering, by attaching a different number of MOSFET fingers in a given I/O cell. In one method, the residual MOSFET OCD fingers were grounded and used as a "grounded gate NMOS" ESD network. In this case, the residual MOSFET fingers act as a natural ESD protection and utilize the "unused" section of the OCD. The advantage of this method is that the unused portion of the I/O is utilized. In a second embodiment, instead of grounding the residual MOSFET fingers, a dummy inverter load was attached to keep the residual fingers "off" or in a low logic state. Using a dummy inverter, the MOSFET gates that are not grounded, and "turn-on" from MOSFET snapback at the same impedance state as the MOSFET OCD. In this fashion, both the active and residual

Different methodologies are used depending on the foundry or corporation.

ASIC methodologies establish requirements for the frequency of placement of "power cells" and "ground cells" to support the I/O and core circuitry [2–4, 7, 8, 11–15]. This provided a perfect opportunity for ESD protection, since an "ESD power clamp" can be placed in the area allocating for the power pins, the VDD pin location (Figure 1).

At one time, prior to the invention of ESD power clamps, it was just as empty areas; it was realized that the ESD power clamps can be placed in these regions. As the frequency of placement of the ESD power clamps increases, the series resistance loss of the power bus or ground bus decreases; this allows for a lower resistance path for the current to flow through the complete network, providing improved ESD robustness.

### 4.4. Ground-to-ground ESD networks

ESD networks are required between ground power rails for every independent domain. In an ASIC system, analog and digital circuits are in separate power domains [7, 8, 11–18]. These domains must be interconnected through ground-to-ground ESD networks. These networks must be bidirectional to allow current to flow in both directions. These networks do not have to be symmetric (e.g., m diodes in one direction and n diodes in the opposite direction). These ground-to-ground ESD networks can be placed in the VSS pin location.

#### 4.5. Master/slave ESD systems

In some ASIC embodiments, the ESD power clamps are integrated across the entire system. In this type of system, there is one "master," which triggers the set of ESD power clamps on all in parallel (Figure 2) [2, 3, 7, 8]. A "master ESD power clamp" contains the trigger network that then sends a signal to turn on all the "slave ESD power clamps." This system has the advantage of turning on all ESD power clamps in parallel across the entire ASIC system, significantly lowering the "on-resistance" of the single ESD power clamp. The disadvantage of this system is an ESD signal bus (from the master clamp to the slave clamps) must be distributed with the ASIC power busses around the complete chip (Figure 3).

Figure 2. Master/slave ESD system.

5.2.1. Fully populated I/O periphery

5.2.2. Partially populated I/O periphery

ments without full populated I/O cells.

5.2.3. Adjacency latch-up rules

and a decoupling capacitor [7–8].

Figure 4. I/O to I/O latch-up test structure.

In the case of a chip perimeter that is fully populated by I/O cells, concerns about latch-up events between adjacent I/O can be evaluated and tested (Figure 4). In this case, guard rings

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In the case of a chip perimeter that is not fully populated, concerns about latch-up events between I/O and adjacent cells can occur. In many ASIC systems, decoupling capacitors can be placed adjacent to an I/O cell. An n-well decoupling capacitor has a large n-well region that can serve as a cathode to a lateral pnpn formed by an adjacent PFET to form a pnpn. In this low populated system, new latch-up rules are needed to avoid CMOS latch-up in ASIC environ-

In some design methodologies, it is necessary to verify what the adjacent circuit is [11–15]. In a fully populated I/O ring, the adjacent circuit will be another I/O cell. In this case, it is well understood. But, in cases where it is not populated, additional rules may be required to avoid latch-up between adjacent circuits. The most common failure was latch-up between an I/O cell

can be placed between the I/O cells, and latch-up interaction can be quantified [7, 8].

Figure 3. Master/slave ESD system floor plan.

### 5. ASIC I/O and latch-up: guard ring integration

In ASIC design methodologies, the I/O must address both ESD and latch-up [11–15]. Latch-up of the ASIC I/O can occur with improper design of the outer guard rings and internal guard rings in a given ASIC I/O cell.

#### 5.1. I/O outer guard ring

In some ASIC methodologies, a guard ring is placed around the entire I/O cell region. This leads to a natural "frame" for the circuit. It serves as a source to collect internal current injected from inside the I/O circuit or external current being injected from outside the I/O circuit. In other methodologies, this outer guard ring is overlapped or integrated with the adjacent I/O cell; this is not detrimental and saves space [7, 8].

Additionally, even further methodologies, there is no "ring" around the entire circuit but only on the top and bottom. This can lead to I/O to I/O interaction, which is not desirable.

#### 5.2. I/O circuit to adjacent I/O circuit

In ASIC I/O design, ESD and latch-up problems can occur when the design is "fully populated" versus "partially populated." In digital applications, typically the design is fully populated and is "I/O limited." But, in some analog applications, in core-dominated designs, the core establishes the chip size (e.g., core-dominated design), leading to a partially populated periphery.

### 5.2.1. Fully populated I/O periphery

In the case of a chip perimeter that is fully populated by I/O cells, concerns about latch-up events between adjacent I/O can be evaluated and tested (Figure 4). In this case, guard rings can be placed between the I/O cells, and latch-up interaction can be quantified [7, 8].

### 5.2.2. Partially populated I/O periphery

In the case of a chip perimeter that is not fully populated, concerns about latch-up events between I/O and adjacent cells can occur. In many ASIC systems, decoupling capacitors can be placed adjacent to an I/O cell. An n-well decoupling capacitor has a large n-well region that can serve as a cathode to a lateral pnpn formed by an adjacent PFET to form a pnpn. In this low populated system, new latch-up rules are needed to avoid CMOS latch-up in ASIC environments without full populated I/O cells.

#### 5.2.3. Adjacency latch-up rules

5. ASIC I/O and latch-up: guard ring integration

cell; this is not detrimental and saves space [7, 8].

5.2. I/O circuit to adjacent I/O circuit

periphery.

rings in a given ASIC I/O cell.

Figure 3. Master/slave ESD system floor plan.

54 Digital Systems

5.1. I/O outer guard ring

In ASIC design methodologies, the I/O must address both ESD and latch-up [11–15]. Latch-up of the ASIC I/O can occur with improper design of the outer guard rings and internal guard

In some ASIC methodologies, a guard ring is placed around the entire I/O cell region. This leads to a natural "frame" for the circuit. It serves as a source to collect internal current injected from inside the I/O circuit or external current being injected from outside the I/O circuit. In other methodologies, this outer guard ring is overlapped or integrated with the adjacent I/O

Additionally, even further methodologies, there is no "ring" around the entire circuit but only

In ASIC I/O design, ESD and latch-up problems can occur when the design is "fully populated" versus "partially populated." In digital applications, typically the design is fully populated and is "I/O limited." But, in some analog applications, in core-dominated designs, the core establishes the chip size (e.g., core-dominated design), leading to a partially populated

on the top and bottom. This can lead to I/O to I/O interaction, which is not desirable.

In some design methodologies, it is necessary to verify what the adjacent circuit is [11–15]. In a fully populated I/O ring, the adjacent circuit will be another I/O cell. In this case, it is well understood. But, in cases where it is not populated, additional rules may be required to avoid latch-up between adjacent circuits. The most common failure was latch-up between an I/O cell and a decoupling capacitor [7–8].

Figure 4. I/O to I/O latch-up test structure.

### 5.3. ESD to I/O circuit

Proper isolation between the ESD circuit contained within the I/O cell and the I/O circuit itself is necessary to avoid CMOS latch-up. The I/O circuit may contain an NFET pull-down, a PFET pull-up, and ballasting resistor bank. This is achievable by proper guard rings around the ESD network and the choice of what elements are placed adjacent to the ESD device. Note that there are multiple elements in an I/O circuit, and the choice of what is placed adjacent to the ESD network has to be co-synthesized with the power bus placement for the I/O cell (e.g., bond pad, VDD, VSS, AVDD, and AVSS). Since the ESD network typically has an element for positive and negative polarity pulse events, both the VDD and the VSS must be local to the ESD network and likewise for the PFET and NFET OCD elements.

For negative polarity ESD events, the n-diffusion or n-well resistor banks will be in parallel with the ESD elements, and the adjacency to their respective guard rings is key to provide "current sharing" and avoid "current robbing" of the ESD event. It was found by matching the space between n-type elements, and the guard rings provided maximum ESD results.

#### 5.4. I/O to core circuitry

To avoid interaction between the I/O circuitry and the core circuitry, additional guard rings have been placed to isolate the I/O from the core circuits. The core circuits are very sensitive to CMOS latch-up since they have no guard rings surrounding the MOSFETs. To avoid latch-up issues between the I/O and core circuitry, additional requirements are established [5]:


#### 5.5. Core-to-core circuitry

Latch-up can occur between different core regions. This occurs when cores are placed adjacent to each other, where there is no design rule check, and when there is no history of the cores being adjacent in prior designs. An example is between a PFET-dominated core and a bank of decoupling capacitors with an n-well plate (Figure 5) [7, 8].

placed close together. To avoid latch-up and noise interaction between digital and analog circuits, large guard rings, moats, substrate contacts, and spaces are added. The space between the digital and analog cores can be significant and as large as 40 to 100 um. In these designs,

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In mixed signal (MS) and system-on-chip (SOC) ASIC designs, there are signal lines that transfer from the digital core to the analog core. The power grids and ground planes are physically isolated to improve noise isolation. Digital core driver circuits transmit signals to analog core receiver networks in the analog section of the semiconductor chip. With the

the power grids and grounds are also separated and spatially isolated [7, 8].

5.7. Internal ESD networks: digital to analog signals

Figure 6. Digital to analog integration with moa.

Figure 5. Latch-up between peripheral I/O and adjacent decoupling capacitors.

To avoid latch-up interaction between the circuitry of cores, additional guard rings, moats, substrate contacts, and space can be added in the design (Figure 6) [7, 8].

#### 5.6. Digital, analog, and RF core circuitry

Latch-up and noise can occur between digital, analog, and radio frequency (RF) cores placed on the same substrate in an ASIC design. This occurs when cores are placed adjacent to each other, where there is no design rule check, and when there is no history of the cores being Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development http://dx.doi.org/10.5772/intechopen.81033 57

Figure 5. Latch-up between peripheral I/O and adjacent decoupling capacitors.

Figure 6. Digital to analog integration with moa.

5.3. ESD to I/O circuit

56 Digital Systems

elements.

5.4. I/O to core circuitry

5.5. Core-to-core circuitry

Proper isolation between the ESD circuit contained within the I/O cell and the I/O circuit itself is necessary to avoid CMOS latch-up. The I/O circuit may contain an NFET pull-down, a PFET pull-up, and ballasting resistor bank. This is achievable by proper guard rings around the ESD network and the choice of what elements are placed adjacent to the ESD device. Note that there are multiple elements in an I/O circuit, and the choice of what is placed adjacent to the ESD network has to be co-synthesized with the power bus placement for the I/O cell (e.g., bond pad, VDD, VSS, AVDD, and AVSS). Since the ESD network typically has an element for positive and negative polarity pulse events, both the VDD and the VSS must be local to the ESD network and likewise for the PFET and NFET OCD

For negative polarity ESD events, the n-diffusion or n-well resistor banks will be in parallel with the ESD elements, and the adjacency to their respective guard rings is key to provide "current sharing" and avoid "current robbing" of the ESD event. It was found by matching the space between n-type elements, and the guard rings provided maximum ESD results.

To avoid interaction between the I/O circuitry and the core circuitry, additional guard rings have been placed to isolate the I/O from the core circuits. The core circuits are very sensitive to CMOS latch-up since they have no guard rings surrounding the MOSFETs. To avoid latch-up

issues between the I/O and core circuitry, additional requirements are established [5]:

• P+ substrate guard ring of specified width between I/O region and core circuitry

Latch-up can occur between different core regions. This occurs when cores are placed adjacent to each other, where there is no design rule check, and when there is no history of the cores being adjacent in prior designs. An example is between a PFET-dominated core and a bank of

To avoid latch-up interaction between the circuitry of cores, additional guard rings, moats,

Latch-up and noise can occur between digital, analog, and radio frequency (RF) cores placed on the same substrate in an ASIC design. This occurs when cores are placed adjacent to each other, where there is no design rule check, and when there is no history of the cores being

• Latch-up space design rule between PFET OCD circuit and core circuits • Latch-up space design rule between NFET OCD circuit and core circuits • N+ guard ring of specified width between I/O region and core circuitry

decoupling capacitors with an n-well plate (Figure 5) [7, 8].

5.6. Digital, analog, and RF core circuitry

substrate contacts, and space can be added in the design (Figure 6) [7, 8].

placed close together. To avoid latch-up and noise interaction between digital and analog circuits, large guard rings, moats, substrate contacts, and spaces are added. The space between the digital and analog cores can be significant and as large as 40 to 100 um. In these designs, the power grids and grounds are also separated and spatially isolated [7, 8].

#### 5.7. Internal ESD networks: digital to analog signals

In mixed signal (MS) and system-on-chip (SOC) ASIC designs, there are signal lines that transfer from the digital core to the analog core. The power grids and ground planes are physically isolated to improve noise isolation. Digital core driver circuits transmit signals to analog core receiver networks in the analog section of the semiconductor chip. With the separation of the digital and analog grounds, and physical space separation, overvoltage of the analog receiver can occur due to the voltage drops in the signal line and the ground connections (Figure 7).

One of the solutions is to place an "internal ESD network" on the internal signal line between the digital driver circuit and the analog receiver. This can be achieved by adding a resistor to the signal line and a grounded gate NMOS prior to the analog receiver (Figure 8).

A second solution is to place "third part" inverter stages and ground-to-ground connections between the digital and analog cores. This methodology has less performance or signal impact and is a more migratable solution (Figure 9) [7–8].

6. Array I/O versus peripheral I/O architectures

Figure 9. Third-party circuits between digital and analog cores.

6.1. Array I/O and ESD

6.2. Array I/O and latch-up

and performance, but alters the ESD and latch-up methods and needs.

system. The ESD robustness of the system can be "wiring limited."

• Wider guard rings around the I/O cell to capture carriers

surrounding circuitry (Figure 10). Solutions to avoid this issue are as follows:

In high pin count environments, the I/O networks can be distributed with the core of a semiconductor chip instead of the periphery. This is referred to as "array I/O" where the I/O cells are placed in an array fashion throughout the core. This has a large advantage for wiring,

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In an array I/O environment, the I/O and ESD are co-integrated into the same I/O cell within the semiconductor chip and ASIC core. A significant change in the ESD results is that the ESD failure distribution is dependent on the wire width from the bond pad to the I/O cell. In this fashion, a "transfer wire" extends from the bond pad to the I/O cell. The ESD failure mechanism can be the wiring itself and may limit the robustness of the system. The wiring choices on how to get from the bond pad to the ESD network are also key to the robustness of the ASIC

A key issue in an array I/O environment is the onset of latch-up [7, 8]. All the circuitry surrounding the I/O cell is core circuitry with no guard rings placed around them. Latch-up can occur from the injection of carriers into the substrate from the ESD network into the

Figure 7. Digital to analog core internal signal lines requiring internal ESD.

Figure 8. Internal ESD networks between cores.

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Figure 9. Third-party circuits between digital and analog cores.

### 6. Array I/O versus peripheral I/O architectures

In high pin count environments, the I/O networks can be distributed with the core of a semiconductor chip instead of the periphery. This is referred to as "array I/O" where the I/O cells are placed in an array fashion throughout the core. This has a large advantage for wiring, and performance, but alters the ESD and latch-up methods and needs.

#### 6.1. Array I/O and ESD

separation of the digital and analog grounds, and physical space separation, overvoltage of the analog receiver can occur due to the voltage drops in the signal line and the ground connec-

One of the solutions is to place an "internal ESD network" on the internal signal line between the digital driver circuit and the analog receiver. This can be achieved by adding a resistor to

A second solution is to place "third part" inverter stages and ground-to-ground connections between the digital and analog cores. This methodology has less performance or signal impact

the signal line and a grounded gate NMOS prior to the analog receiver (Figure 8).

and is a more migratable solution (Figure 9) [7–8].

Figure 7. Digital to analog core internal signal lines requiring internal ESD.

Figure 8. Internal ESD networks between cores.

tions (Figure 7).

58 Digital Systems

In an array I/O environment, the I/O and ESD are co-integrated into the same I/O cell within the semiconductor chip and ASIC core. A significant change in the ESD results is that the ESD failure distribution is dependent on the wire width from the bond pad to the I/O cell. In this fashion, a "transfer wire" extends from the bond pad to the I/O cell. The ESD failure mechanism can be the wiring itself and may limit the robustness of the system. The wiring choices on how to get from the bond pad to the ESD network are also key to the robustness of the ASIC system. The ESD robustness of the system can be "wiring limited."

#### 6.2. Array I/O and latch-up

A key issue in an array I/O environment is the onset of latch-up [7, 8]. All the circuitry surrounding the I/O cell is core circuitry with no guard rings placed around them. Latch-up can occur from the injection of carriers into the substrate from the ESD network into the surrounding circuitry (Figure 10). Solutions to avoid this issue are as follows:

• Wider guard rings around the I/O cell to capture carriers

7.3. FinFET

bipolar current gain in the FinFET technology [33].

8. Closing comments and summary

Acknowledgements

Author details

Steven H. Voldman

References

Presently, the FinFET device is being integrated into advanced sub-25 nm technologies [31–33]. With the FinFET structure, the layout and guard ring strategy will be influenced leading to different ESD layouts and designs. In the future, the direction may include both bulk and SOI FinFETs, which will respond differently for ESD and for latch-up. With the scaling of the FinFET structure, the shallow trench isolation (STI) will be scaled leading to higher parasitic

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Electrostatic discharge (ESD) has been a crucial issue in ASIC design flow and release and will continue to be an issue as semiconductor devices are scaled below 20 nm in both future and present-day nanotechnology era. As technologies migrate to sub-25 nm technology, ESD, latch-

I would like to thank the IBM ASIC I/O development team for the many years of collaboration and integration of ESD and latch-up solution into four generations of ASIC design methods. Special thanks to team lead Douglas Stout, James Pequignot, and Jeffrey Sloan. I would also like to thank the IBM Cadence™ software development of Susan Strang, Don Jordan, and C.N.

up, and EOS will be an issue for both bulk and SOI FinFET technologies.

Perez for implementing the ESD hierarchical parametrized cell system.

[1] Voldman S. ESD: Physics and Devices. Chichester: Wiley; 2004 [2] Voldman S. ESD: Circuits and Devices. Chichester: Wiley; 2005

[3] Voldman S. ESD: Circuits and Devices. 2nd ed. Wiley; 2015

[4] Dabral S, Maloney TJ. Basic ESD and I/O Design. West Sussex: Wiley; 1998

Address all correspondence to: voldman@ieee.org

IEEE Fellow, United States of America

Figure 10. An example of array I/O and latch-up propagation in the core circuitry.


### 7. Advanced technology nodes

Electrostatic discharge (ESD) will be an issue in ASIC technology as we evolve to new technologies, new devices, and 2.5D and 3D systems. These transitions will have a significant effect on ESD protection in the future.

#### 7.1. 2.5D and 3D ASIC systems

In today's applications, migration to 2.5D and 3D systems has begun. In 2.5D applications, there are a significant number of wire bonds that interconnect the stacked chips. This has implications to electrical overstress (EOS) and wire-bond reliability. In 3D applications, the introduction of through-silicon via (TSV) technology changes the interrelation of how current flows through the multi-chip design; this has an influence on power grid design, placement of the TSV structure, and ESD devices. ESD design may require co-design with the power and ground placement of the multi-chip ASIC system.

#### 7.2. Silicon on insulator (SOI)

Silicon on insulator (SOI) has been a mainstream technology since 2000 [1–3]. Microprocessors have been designed with excellent ESD protection levels in partially depleted SOI technology. From an ESD perspective, new SOI ESD structures were integrated, as well as addressing new SOI failure mechanisms, since these structures behaved differently than bulk ESD elements [29, 30].

### 7.3. FinFET

Presently, the FinFET device is being integrated into advanced sub-25 nm technologies [31–33]. With the FinFET structure, the layout and guard ring strategy will be influenced leading to different ESD layouts and designs. In the future, the direction may include both bulk and SOI FinFETs, which will respond differently for ESD and for latch-up. With the scaling of the FinFET structure, the shallow trench isolation (STI) will be scaled leading to higher parasitic bipolar current gain in the FinFET technology [33].

### 8. Closing comments and summary

Electrostatic discharge (ESD) has been a crucial issue in ASIC design flow and release and will continue to be an issue as semiconductor devices are scaled below 20 nm in both future and present-day nanotechnology era. As technologies migrate to sub-25 nm technology, ESD, latchup, and EOS will be an issue for both bulk and SOI FinFET technologies.

## Acknowledgements

• Different guard ring structures with higher efficiency of carrier capture (e.g., trench,

Figure 10. An example of array I/O and latch-up propagation in the core circuitry.

• Decreasing the n-well and p-well contact placement in the core circuitry adjacent to the

Electrostatic discharge (ESD) will be an issue in ASIC technology as we evolve to new technologies, new devices, and 2.5D and 3D systems. These transitions will have a significant effect on

In today's applications, migration to 2.5D and 3D systems has begun. In 2.5D applications, there are a significant number of wire bonds that interconnect the stacked chips. This has implications to electrical overstress (EOS) and wire-bond reliability. In 3D applications, the introduction of through-silicon via (TSV) technology changes the interrelation of how current flows through the multi-chip design; this has an influence on power grid design, placement of the TSV structure, and ESD devices. ESD design may require co-design with the power and

Silicon on insulator (SOI) has been a mainstream technology since 2000 [1–3]. Microprocessors have been designed with excellent ESD protection levels in partially depleted SOI technology. From an ESD perspective, new SOI ESD structures were integrated, as well as addressing new SOI failure

mechanisms, since these structures behaved differently than bulk ESD elements [29, 30].

moats, etc.)

7. Advanced technology nodes

ESD protection in the future.

7.1. 2.5D and 3D ASIC systems

7.2. Silicon on insulator (SOI)

ground placement of the multi-chip ASIC system.

I/O cell

60 Digital Systems

I would like to thank the IBM ASIC I/O development team for the many years of collaboration and integration of ESD and latch-up solution into four generations of ASIC design methods. Special thanks to team lead Douglas Stout, James Pequignot, and Jeffrey Sloan. I would also like to thank the IBM Cadence™ software development of Susan Strang, Don Jordan, and C.N. Perez for implementing the ESD hierarchical parametrized cell system.
