Author details

control of them become very complicated. However, in the authors' recent work [31], we have successfully realized adaptive filtering based on higher-order VBPFs/VBSFs, where we have derived a gradient descent method-based adaptive algorithm for arbitrary-order VBPFs/VBSFs in a simple form by means of frequency transformation in terms of the block diagram as well as the mathematical description. As a result, it is demonstrated in [31] that the use of higher-order VBPFs/VBSFs for adaptive filtering leads to higher output SNR than

Figure 10. Example of adaptive band-pass filtering: (a) using second-order VBPF, and (b) using high-order VBPF.

As stated above, adaptive band-pass/band-stop filtering based on high-order VBPFs/VSFs can be realized in a simple manner. However, there are still many open problems such as mathematical discussion of convergence of the adaptive algorithm, improvement of convergence speed, and suppression of large quantization errors that are generated due to the nature of high-order narrowband filters. Although the problem of quantization errors can be solved by means of the state-space-based VBPFs/VBSFs [64], further investigations are need to cope with

In addition to the ANFs and higher-order adaptive band-pass/band-stop filtering, many applications of other VDFs to adaptive filtering have been presented. In [65], adaptive filtering based on the cascade connection of second-order all-pass filters is proposed. This method is shown to be superior to the standard ANF-based methods for the detection of multiple sinusoids. Another

the use of ANFs.

38 Digital Systems

the other problems.

4.4. Other VDFs for adaptive filtering

Shunsuke Koshita\*, Masahide Abe and Masayuki Kawamata

\*Address all correspondence to: kosita@mk.ecei.tohoku.ac.jp

Department of Electronic Engineering, Graduate School of Engineering, Tohoku University, Sendai, Japan

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**Section 2**

**Digital Systems Hardware and Protection**


**Digital Systems Hardware and Protection**

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44 Digital Systems

**Chapter 3**

Provisional chapter

**Electrostatic Discharge Protection and Latch-Up Design**

DOI: 10.5772/intechopen.81033

Electrostatic discharge (ESD) has been an issue in devices, circuits, and systems for electronics for many decades, as early as the 1970s, and continued to be an issue until today. In this chapter, the issue of ESD protection design and methods for Application-Specific Integrated Circuits (ASICs) will be discussed. The chapter will discuss ESD design in an ASIC environment. The discussion will address ESD design layout, design rules and practices, and the method of integration of ESD protection into the ASIC design practice. Part of the methodology is the floor planning of an ASIC design, I/O library, integration of ESD into I/O cells, power distribution, and placement of power pads, in both array and peripheral design methodologies. As part of the ASIC I/O design, guard rings and latch-

Keywords: electrostatic discharge, latch-up, ASICs, ASIC I/O integration, ASIC power

Electrostatic discharge (ESD) design, practices, and methods are a fundamental to the implementation of an ASIC design environment [1–28]. The integration of ESD and latch-up in an ASIC environment is typically a top-down design flow. In the ASIC environment, the chip size, the number of I/O circuits, the bus location, placement of the I/O cells, and integration of the

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

ESD elements and power are all synthesized. The top-down design flow is as follows:

Electrostatic Discharge Protection and Latch-Up Design

**and Methodologies for ASIC Development**

and Methodologies for ASIC Development

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.81033

up interactions will be highlighted.

Steven H. Voldman

Steven H. Voldman

Abstract

distribution

• Functional definition • Technology decision

1. Introduction

#### **Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development** Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development

DOI: 10.5772/intechopen.81033

Steven H. Voldman Steven H. Voldman

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.81033

#### Abstract

Electrostatic discharge (ESD) has been an issue in devices, circuits, and systems for electronics for many decades, as early as the 1970s, and continued to be an issue until today. In this chapter, the issue of ESD protection design and methods for Application-Specific Integrated Circuits (ASICs) will be discussed. The chapter will discuss ESD design in an ASIC environment. The discussion will address ESD design layout, design rules and practices, and the method of integration of ESD protection into the ASIC design practice. Part of the methodology is the floor planning of an ASIC design, I/O library, integration of ESD into I/O cells, power distribution, and placement of power pads, in both array and peripheral design methodologies. As part of the ASIC I/O design, guard rings and latchup interactions will be highlighted.

Keywords: electrostatic discharge, latch-up, ASICs, ASIC I/O integration, ASIC power distribution

### 1. Introduction

Electrostatic discharge (ESD) design, practices, and methods are a fundamental to the implementation of an ASIC design environment [1–28]. The integration of ESD and latch-up in an ASIC environment is typically a top-down design flow. In the ASIC environment, the chip size, the number of I/O circuits, the bus location, placement of the I/O cells, and integration of the ESD elements and power are all synthesized. The top-down design flow is as follows:


© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


semiconductor (CMOS) technology. A first p-n diode element is formed in an n-well region where the p-anode is the p-diffusion implant of the p-channel MOSFET device and the n-cathode is the n-well region connected to the power supply VDD. This is sometimes referred to as the "up diode." A second p-n diode element is formed in a p-well or p-substrate region where the n-cathode is the n-diffusion implant of the n-channel MOSFET device or the n+/nwell implant, and the p-anode is the p-well region or p-substrate region connected to the power supply VSS. This is sometimes referred to as the "down diode." This circuit provides a "forward bias" ESD protection solution for positive and negative ESD pulse events to the two power rails VDD and VSS. An advantage of the dual-diode ESD network for ASIC environments is that it is easy to migrate from technology generation to technology generation and

Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development

http://dx.doi.org/10.5772/intechopen.81033

49

In an ASIC design methodology, the ESD network is integrated within the I/O library element. The I/O cell can contain a bond pad, guard rings, ESD network, receiver, and off-chip driver

The charged-device model (CDM) is an electrostatic discharge (ESD) test method that is part of the qualification of semiconductor components in an ASIC design system [6]. The CDM event is associated with the charging of the semiconductor component through different charging processes. Charging of the package can be achieved through direct contact charging or fieldinduced charging processes. The field-induced charging method is called the field-induced

Charged-device ESD solutions utilize an additional circuit element local to the receiver network. For CDM protection, an additional resistor and second dual diode are added, where the second stage element is adjacent to the MOSFET receiver. The purpose of the second stage element is to divert the electric charge in the substrate adjacent to the MOSFET receiver to the

In an ASIC environment, each generation attempts to squeeze in as many I/O circuits on the periphery, by reducing the width of the I/O cell, and compensate by increasing the height of the ASIC I/O cell [11–15]. With the long-narrow ASIC I/O cell, the receiver network is moved farther away from the bond pad and the first stage of the ESD network. As a result, the second

In an ASIC environment, there are rules and requirements that are established in the design methodology. These rules and requirements for ESD design, latch-up design layout, to application issues of placement of power, placement of grounds. Additionally, the power sequencing for power down and power up is specified in the methodology. These fundamental ASIC rules have

dual-diode stage is even more necessary to achieve excellent CDM ESD results.

bond pad without destruction of the receiver dielectric and circuitry.

is scalable.

(OCD) elements [2, 3, 7, 8].

2.2. Charged-device model

charged-device model (FI-CDM).

2.2.1. CDM and long-narrow ASIC I/O

3. ASIC requirements


### 2. Electrostatic discharge

Electrostatic discharge (ESD) is a common form of component-level failure from manufacturing, shipping, and handling in an ASIC environment [1–8]. Two of the tests used in the qualification and release process of an ASIC design system are the human body model (HBM) and the charged-device model (CDM) standards [1–8].

### 2.1. Human body model

The human body model (HBM) is the most widely established standard for the qualification and release of semiconductor components in the semiconductor industry [1–4, 6–8]. The HBM test is integrated into the qualification and release process of the quality and reliability teams for components in ASIC organizations, corporations, and foundries. The model was intended to represent the interaction of the electrical discharge of a human being, who is charged, with a component or an object. The charged source then touches a component or an object using a finger. The physical contact between the charged human being and the component or object allows for current transfer between the human being and the object.

HBM failure mechanisms typically are associated with failures on the ASIC peripheral circuitry of a semiconductor chip that are connected to signal pins. HBM ESD networks are used to establish an alternative current path to avoid failure of the ASIC peripheral circuitry. HBM failures can also occur on the power rails due to inadequate bus widths and ESD power clamps between the power rails. HBM failures can occur in both passive and active semiconductor components. The failure signature is typically isolated to a single device or a few elements in a given current path where the current exceeded the power to failure of the circuit elements. ESD circuits are designed to be responsive to HBM pulse widths; specifically, the RC-triggered ESD power clamp is a vulnerable ESD circuit.

An example of an ESD protection network is known as a dual-diode network [1–4, 7, 8]. The dual-diode ESD network is a commonly used network for complementary metal-oxide semiconductor (CMOS) technology. A first p-n diode element is formed in an n-well region where the p-anode is the p-diffusion implant of the p-channel MOSFET device and the n-cathode is the n-well region connected to the power supply VDD. This is sometimes referred to as the "up diode." A second p-n diode element is formed in a p-well or p-substrate region where the n-cathode is the n-diffusion implant of the n-channel MOSFET device or the n+/nwell implant, and the p-anode is the p-well region or p-substrate region connected to the power supply VSS. This is sometimes referred to as the "down diode." This circuit provides a "forward bias" ESD protection solution for positive and negative ESD pulse events to the two power rails VDD and VSS. An advantage of the dual-diode ESD network for ASIC environments is that it is easy to migrate from technology generation to technology generation and is scalable.

In an ASIC design methodology, the ESD network is integrated within the I/O library element. The I/O cell can contain a bond pad, guard rings, ESD network, receiver, and off-chip driver (OCD) elements [2, 3, 7, 8].

### 2.2. Charged-device model

• I/O definition with ESD network and guard ring definition

• Power pads and number of ESD power clamps required

• Core function placement

• Core to core ESD networks

• Core to core guard rings • I/O to core guard rings

2. Electrostatic discharge

2.1. Human body model

charged-device model (CDM) standards [1–8].

power clamp is a vulnerable ESD circuit.

• Number of I/O • I/O placement

48 Digital Systems

• Power pad definition with ESD power clamp and guard ring definition

Electrostatic discharge (ESD) is a common form of component-level failure from manufacturing, shipping, and handling in an ASIC environment [1–8]. Two of the tests used in the qualification and release process of an ASIC design system are the human body model (HBM) and the

The human body model (HBM) is the most widely established standard for the qualification and release of semiconductor components in the semiconductor industry [1–4, 6–8]. The HBM test is integrated into the qualification and release process of the quality and reliability teams for components in ASIC organizations, corporations, and foundries. The model was intended to represent the interaction of the electrical discharge of a human being, who is charged, with a component or an object. The charged source then touches a component or an object using a finger. The physical contact between the charged human being and the component or object

HBM failure mechanisms typically are associated with failures on the ASIC peripheral circuitry of a semiconductor chip that are connected to signal pins. HBM ESD networks are used to establish an alternative current path to avoid failure of the ASIC peripheral circuitry. HBM failures can also occur on the power rails due to inadequate bus widths and ESD power clamps between the power rails. HBM failures can occur in both passive and active semiconductor components. The failure signature is typically isolated to a single device or a few elements in a given current path where the current exceeded the power to failure of the circuit elements. ESD circuits are designed to be responsive to HBM pulse widths; specifically, the RC-triggered ESD

An example of an ESD protection network is known as a dual-diode network [1–4, 7, 8]. The dual-diode ESD network is a commonly used network for complementary metal-oxide

allows for current transfer between the human being and the object.

The charged-device model (CDM) is an electrostatic discharge (ESD) test method that is part of the qualification of semiconductor components in an ASIC design system [6]. The CDM event is associated with the charging of the semiconductor component through different charging processes. Charging of the package can be achieved through direct contact charging or fieldinduced charging processes. The field-induced charging method is called the field-induced charged-device model (FI-CDM).

Charged-device ESD solutions utilize an additional circuit element local to the receiver network. For CDM protection, an additional resistor and second dual diode are added, where the second stage element is adjacent to the MOSFET receiver. The purpose of the second stage element is to divert the electric charge in the substrate adjacent to the MOSFET receiver to the bond pad without destruction of the receiver dielectric and circuitry.

### 2.2.1. CDM and long-narrow ASIC I/O

In an ASIC environment, each generation attempts to squeeze in as many I/O circuits on the periphery, by reducing the width of the I/O cell, and compensate by increasing the height of the ASIC I/O cell [11–15]. With the long-narrow ASIC I/O cell, the receiver network is moved farther away from the bond pad and the first stage of the ESD network. As a result, the second dual-diode stage is even more necessary to achieve excellent CDM ESD results.

### 3. ASIC requirements

In an ASIC environment, there are rules and requirements that are established in the design methodology. These rules and requirements for ESD design, latch-up design layout, to application issues of placement of power, placement of grounds. Additionally, the power sequencing for power down and power up is specified in the methodology. These fundamental ASIC rules have a significant influence on the ESD circuits, ESD design methodology, and ESD circuit placement. Additionally, the ASIC system must achieve latch-up specification objectives.

3.3.2. Power-up: sequence dependent

ASIC system can define the sequencing requirements for the power and the signal pins. Some ASIC systems can have a sequence-dependent power up and shutdown. In these systems, the

Electrostatic Discharge Protection and Latch-Up Design and Methodologies for ASIC Development

http://dx.doi.org/10.5772/intechopen.81033

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ASIC system can define the sequencing requirements for the power and the signal pins. Some ASIC systems require sequence-independent power up and shutdown. In these systems, the ESD networks are not to be "on" during power-up or power down. In this case, the ESD networks must not be forward biased in power up or power down. As a result, new sequence-independent ESD networks that do not forward bias were required. A sequenceindependent ESD network was implemented into a 0.5-um ASIC system with significant

ASIC methodologies establish requirements for the frequency of placement of "power cells" and "ground cells" to support the I/O and core circuitry. For example, some corporations stated that their ASIC system must be a power cell for every fourth or fifth I/O location. This provided a significant opportunity for ESD protection, since an "ESD power clamp" can be placed in the area allocating for the VDD and VSS power pins. As the frequency of placement of the ESD power clamps increases, the series resistance loss of the power bus or ground bus decreases; this allows for a lower resistance path for the current to flow through the complete

As ASIC technology transitions to advanced technology nodes, the application frequency is increased. From an ESD perspective, the expectation from ASICs is that the capacitance loading of the ESD network must be reduced to not impact the frequency bandwidth of the I/O networks. This can be achieved through semiconductor process modification, layout and design, and reduction of the size of the ESD networks. Through ESD novelty and innovation, the frequency bandwidth of signal inputs can be realized without reduction of ESD reliability

An additional concern is the input leakage requirements and IDD limitations. Input leakage can be minimized through proper design of ESD networks through process, circuit topology, and layout innovations. A larger concern is the ESD power clamps on the VDD power supply. It is critical to limit the number of ESD power clamps to not impact the IDD leakage limit for

ESD networks are not to be "on" during power up or power down.

3.3.3. Power-up: sequence independent and hot plugging

success with a floating well control network [2, 3, 9].

network, providing improved ESD robustness [2, 3, 7, 8].

3.3.5. Frequency bandwidth

3.3.6. Input leakage and IDD limitations

concern.

the application.

3.3.4. Power distribution and placement requirements

### 3.1. ESD protection-level requirements

In a release of an ASIC system, there are qualification expectations of ESD protection levels. Each ASIC I/O cell is tested for ESD and CDM test processes, and the entire I/O library is to achieve above the desired protection levels for qualification. In the past, the desired protection levels for HBM and CDM were >4000 V HBM and > 500 V CDM; with technology scaling, these objectives have been changed to lower levels.

### 3.1.1. ESD design rules

ESD design rules of the physical dimensions of the ESD networks are typically contained within the technology design manual. The ASIC library is required to fulfill the technology ESD design manual rule set. The ESD design rules provide the circuit, layout, and physical dimensions.

#### 3.2. Latch-up requirements

Latch-up requirements are also needed for the qualification of an ASIC design system [5]. The latch-up requirements used in all corporations and foundries are in the JEDEC latch-up specification and test method.

#### 3.2.1. Latch-up design rules

As ASIC systems became more complex with integration of system on chips (SOC), the number of latch-up design rules has increased. Historically, latch-up rules consisted of four rules—(1) the distance between a PFET and its corresponding n-well contact, (2) the distance between an NFET and its closest substrate contact, (3) spacing of PFET to n-well edge, and lastly (4) spacing of NFET to n-well edge [5]. With scaling, there were many additional rules established between ESD and I/O, I/O to I/O, PFET to core logic, and NFET to core logic. With complexity, more guard rings were added to isolate the different regions of an ASIC implementation.

#### 3.3. ASIC application requirements

In the definition of an ASIC system, there are many application rules and requirements that are established. These include area requirements, power distribution, and power sequencing.

#### 3.3.1. Area requirements

In an ASIC system, there is a given chip area specified for the I/O circuitry [9–15]. This is planned as a certain percentage of the total chip area. Additionally, the ESD networks also can only be a certain defined percentage of the I/O cell. Typically, the ESD area desired is less than 20–25% of the total I/O cell area.

### 3.3.2. Power-up: sequence dependent

a significant influence on the ESD circuits, ESD design methodology, and ESD circuit placement.

In a release of an ASIC system, there are qualification expectations of ESD protection levels. Each ASIC I/O cell is tested for ESD and CDM test processes, and the entire I/O library is to achieve above the desired protection levels for qualification. In the past, the desired protection levels for HBM and CDM were >4000 V HBM and > 500 V CDM; with technology scaling,

ESD design rules of the physical dimensions of the ESD networks are typically contained within the technology design manual. The ASIC library is required to fulfill the technology ESD design manual rule set. The ESD design rules provide the circuit, layout, and physical

Latch-up requirements are also needed for the qualification of an ASIC design system [5]. The latch-up requirements used in all corporations and foundries are in the JEDEC latch-up spec-

As ASIC systems became more complex with integration of system on chips (SOC), the number of latch-up design rules has increased. Historically, latch-up rules consisted of four rules—(1) the distance between a PFET and its corresponding n-well contact, (2) the distance between an NFET and its closest substrate contact, (3) spacing of PFET to n-well edge, and lastly (4) spacing of NFET to n-well edge [5]. With scaling, there were many additional rules established between ESD and I/O, I/O to I/O, PFET to core logic, and NFET to core logic. With complexity, more guard rings were added to isolate the different regions of an ASIC imple-

In the definition of an ASIC system, there are many application rules and requirements that are established. These include area requirements, power distribution, and power sequencing.

In an ASIC system, there is a given chip area specified for the I/O circuitry [9–15]. This is planned as a certain percentage of the total chip area. Additionally, the ESD networks also can only be a certain defined percentage of the I/O cell. Typically, the ESD area desired is less than

Additionally, the ASIC system must achieve latch-up specification objectives.

3.1. ESD protection-level requirements

3.1.1. ESD design rules

3.2. Latch-up requirements

ification and test method.

3.2.1. Latch-up design rules

3.3. ASIC application requirements

3.3.1. Area requirements

20–25% of the total I/O cell area.

dimensions.

50 Digital Systems

mentation.

these objectives have been changed to lower levels.

ASIC system can define the sequencing requirements for the power and the signal pins. Some ASIC systems can have a sequence-dependent power up and shutdown. In these systems, the ESD networks are not to be "on" during power up or power down.

### 3.3.3. Power-up: sequence independent and hot plugging

ASIC system can define the sequencing requirements for the power and the signal pins. Some ASIC systems require sequence-independent power up and shutdown. In these systems, the ESD networks are not to be "on" during power-up or power down. In this case, the ESD networks must not be forward biased in power up or power down. As a result, new sequence-independent ESD networks that do not forward bias were required. A sequenceindependent ESD network was implemented into a 0.5-um ASIC system with significant success with a floating well control network [2, 3, 9].

### 3.3.4. Power distribution and placement requirements

ASIC methodologies establish requirements for the frequency of placement of "power cells" and "ground cells" to support the I/O and core circuitry. For example, some corporations stated that their ASIC system must be a power cell for every fourth or fifth I/O location. This provided a significant opportunity for ESD protection, since an "ESD power clamp" can be placed in the area allocating for the VDD and VSS power pins. As the frequency of placement of the ESD power clamps increases, the series resistance loss of the power bus or ground bus decreases; this allows for a lower resistance path for the current to flow through the complete network, providing improved ESD robustness [2, 3, 7, 8].

#### 3.3.5. Frequency bandwidth

As ASIC technology transitions to advanced technology nodes, the application frequency is increased. From an ESD perspective, the expectation from ASICs is that the capacitance loading of the ESD network must be reduced to not impact the frequency bandwidth of the I/O networks. This can be achieved through semiconductor process modification, layout and design, and reduction of the size of the ESD networks. Through ESD novelty and innovation, the frequency bandwidth of signal inputs can be realized without reduction of ESD reliability concern.

### 3.3.6. Input leakage and IDD limitations

An additional concern is the input leakage requirements and IDD limitations. Input leakage can be minimized through proper design of ESD networks through process, circuit topology, and layout innovations. A larger concern is the ESD power clamps on the VDD power supply. It is critical to limit the number of ESD power clamps to not impact the IDD leakage limit for the application.
