**4. Software defined radio (SDR) and applications to satellite**

Traditional communications systems are designed for and constrained to a specific waveform(s) operating over predetermined frequencies, bandwidths, and signal modulation types. This paradigm works well when the requirements and constraints of the communication link and network protocol are well understood prior to design.

As a result, most radios in today's world have very dedicated uses. A car key fob is designed only to unlock or lock your car door, while a smart phone radio connects to the Internet through various wireless communication protocols. Although these examples vary in complexity of the hardware, they both cannot operate outside the confines of their physical layer implementation. Consequently, RF hardware with a narrow focus is not suitable for applications with a broader communication scope.

A single software defined radio (SDR) with a flexible RF front-end combined with modern computing power can be used for the above applications plus more. In addition, a radio with a flexible hardware and software architecture can also lead to more innovation in the communications industry. Because of the rapid development nature of software, an engineer or researcher can experiment with novel ideas and SDR waveforms that would not be achievable with a traditional radio.

SDR in the satellite communications industry has become a growing trend, particularly in the commercial and defense industries. In the following section, an overview of SDR will be given and applications of SDR in satellite communications will be discussed.

#### **4.1 Overview of SDR**

Before going into SDR basics, some of the SDR advantages are [6]:


<sup>6</sup> A cognitive radio (CR) is a radio that can be programmed and configured dynamically to use the best wireless channels in its vicinity to avoid user interference and congestion.

an SDR-CR can "borrow" the spectrum until the owner comes back. This technique has the potential to dramatically increase efficient use of radio frequency spectrum.


On the other hand, some of the disadvantages for SDR are:


<sup>7</sup> Application-specific integrated circuit (ASIC) is designed for specific purpose.

<sup>8</sup> Field Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a designer after manufacturing thus much more general purpose.

<sup>9</sup> The Joint Tactical Radio System (JTRS) aims to replace existing radios in the U.S. military with a single SDR to enable new frequencies and waveforms added via software or firmware upload.

#### *4.1.1 SDR basics*

The general definition for a SDR is *a radio with some or all its physical layer behavior defined through means of software* [7, 8]. SDRs are incredibly valuable devices as they allow the end user the ability to traverse the RF spectrum at variable sampling rates. The fundamental qualities that make up an SDR are the flexible specifications and the ability to transform the analog signal using digital signal processing (DSP).

A radio can be categorically separated into receivers and transmitters. For this section, the receiver implementation will be considered as it is generally more interesting and complex. A block diagram of an SDR receiver is shown below in **Figure 12**. The following sections will present the anatomy of the SDR that differentiates it from a traditionally designed radio.

#### *4.1.2 RF front-end*

The purpose of the RF front-end (RFFE) is to isolate the desired signal received by the antenna from interference signals. To achieve this, the signal of interest must be brought down to lower frequency for digital conversion while mitigating the side effects from filtering during the frequency conversion process. A flexible RFFE for SDR must be designed so that the frequency and bandwidth are controllable by software. Depending on the system requirements and the available RF component specifications, there are several ways to achieve this.

One of the most common RFFE designs for analog radios is the heterodyne receiver. A heterodyne receiver, shown in **Figure 13** below, works by mixing down the received signal from its carrier frequency to a lower intermediate frequency (IF). The signal at IF can now be more conveniently filtered, amplified, and processed. A super-heterodyne receiver uses a fixed IF that is lower than the carrier frequency but higher than the signal bandwidth and often uses two stages of down conversion to reduce the filtering requirements at each stage.

Another popular RF front-end architecture generally used for low-power applications is called zero-IF. A zero-IF receiver, shown in **Figure 14** below, uses a single mixing stage with the local oscillator (LO) set directly to the desired carrier frequency to convert directly to baseband in-phase and quadrature signals. Because mixers tend to have high power consumption and only low-pass filters are required, the simpler zero-IF provides improved power efficiency over a heterodyne architecture. However, the zero-IF implementation is more susceptible to IQ imbalances of the in-phase and quadrature oscillators, which will produce anomalies in the signal constellation. LO leakage may also self-mix through the RF ports creating a large DC bias. Both issues can be corrected using digital signal processing.

**Figure 12.** *A block diagram of an SDR.*

*Communication Subsystems for Satellite Design DOI: http://dx.doi.org/10.5772/intechopen.93010*

The analog-to-digital converter (ADC) is responsible for converting a continuous-time signal to a discrete-time one. To translate signals from the analog to digital domain, an ADC must perform two fundamental steps: sampling and quantization. Sampling is the process of reading voltages at discrete-time intervals. Quantization is the process of converting these voltage readings into binary outputs. ADC performance can be evaluated based on various parameters, such as: signal-to-noise ratio (SNR), dynamic range, bit resolution, sampling rate, and power dissipation. The ADC dictates the DSP limitations of the SDR. Generally, the sampling rate should be at least twice the desired bandwidth of your signal. The ADC should be chosen to match the capability of your processor and specifications of the signals of interest.

#### *4.1.3 Digital front-end (DFE)*

The two main functions of a digital front-end are sample rate conversion (SRC) and channelization. Once a signal has become digitally converted, the samples need to be further primed for digital processing. Operating the ADC at a fixed rate simplifies its clock generation; however, it may be necessary to convert the sampling rate to match the sampling rate required to demodulate certain waveforms. Most wireless signals generally operate with specific symbol or chip rates that are specified by their respective standard. Depending on the RFFE design and signal type, channelization may be required to select the channel of interest.

SRC represents a classic sampling theorem problem. Converting sampling rates can introduce undesirable effects such as aliasing, an effect that causes frequency components to overlap. SRC can be achieved digitally through the processes of decimation and interpolation. To mitigate aliasing, decimation is performed by using an anti-aliasing filter followed by subsampling, which is essentially removing samples at certain intervals. Interpolation is a method of calculating values to add values in between samples. Channelization works by using digital down conversion, the process of digitally mixing down a signal to baseband with a numerically controlled oscillator.

#### *4.1.4 Digital signal processing*

SDRs have an array of devices to choose from for the required DSP application, each with their own strengths and weaknesses. An SDR may integrate multiple processor types and partition the signal processing chain to optimize each processor. The following criteria should be considered when evaluating the various processor types: flexibility, modularity, and performance. The three digital hardware choices this section will consider are the general-purpose processor (GPP), digital signal processor (DSP), and the field programmable gate array (FPGA).

A GPP is the typical microprocessor designed to handle a wide variety of generic tasks that can be found in your everyday personal computer. They are generally designed to have large instruction sets and highly capable of implementing and performing complex arithmetic tasks such as modulation/demodulation, filtering, fixed/floating point math, and encoding/decoding. Some commonly used GPP architectures are x86/64 and Advanced RISC Machine (ARM). The advantage of using a GPP is the wide availability, flexibility, and ease of programmability. Several GPP-based SDRs, such as Universal Software Radio Peripheral (USRP) and the LimeSDR, operate by digitizing the baseband signal and performing the required digital signal processing on computers. These types of SDRs are popular among university researchers and hobbyists due to the relative ease of obtaining and developing their applications.

Because the GPP was designed with such a broad focus, latency, speed, and power efficiency may be a limiting factor depending on the application. Many wireless communication standards have strict real-time and large processing bandwidth requirements that most modern CPUs cannot meet due to processor architecture and operating system design. .

A DSP is a microprocessor optimized for digital signal processing applications with the ability to be programmed with high-level languages. Although a GPP can contain much of the same functionality, the DSP performs the same digital signal processing operations more quickly and efficiently due to its reduced instruction set computer (RISC) architecture and parallel processing. The reduced instruction set limits the essentials but contains optimizations for common DSP operations such as multiply accumulate (MAC), filtering, matrix operations, and fast Fourier transform (FFT). DSPs are commonly sold in two variants: optimized for power efficiency and optimized for performance; and are used in applications such as base stations and edge devices. Power consumption is also minimized by reducing the silicon footprint that would be in GPPs sophisticated cache and peripheral subsystems.

Although DSPs have been commonly deployed in the past decades, they serve as a middle ground between GPPs and FPGAs with regard to flexibility, performance and efficiency. Field-programmable gate array (FPGA) offers more parallelism, higher data rates, and better power efficiency than DSP, but is not well suited for control applications, such as implementing the network/protocol stack. This is due to the limited amount of memory in FPGA and for this reason it is often paired with GPP.

A FPGA is an array of programmable hardware logic blocks, such as general logic, memory, and multiplier blocks, that are wired together via a reconfigurable interconnect to generate an integrated circuit for several designs with the ability to quickly switch between configurations. FPGA configurations are programmed using hardware description language (HDL), which is also used for ASIC. Because a FPGA functionality is defined at the hardware level and can be implemented using parallelism, it can perform DSP algorithms at much higher rates than DSPs and GPPs. FPGA consumes more power and requires more space than ASICs but provides more programmability and flexibility than ASIC. A big consideration for using FPGAs for SDR is the domain knowledge requirement

*Communication Subsystems for Satellite Design DOI: http://dx.doi.org/10.5772/intechopen.93010*

for developers. Developing on FPGAs can be time consuming and require an extensive understanding of the target hardware architecture.

When the system requirements exceed the capabilities of a singular processor type, a comprehensive solution may include a combination of the above processor types. A common processing architecture in the defense industry comprises of a FPGA, DSP, and GPP. In this paradigm, the FPGA is responsible for high data rate signal processing tasks, such as sampling and filtering, the DSP handles demodulation and protocol, and the GPP performs control-related tasks, such as the user interface and algorithmic processing. Implementing such a system can become a complex management task to coordinate the processing flow; however, the system can benefit greatly by optimizing overall performance based on the strength of each processor.

#### **4.2 Applications of SDR to satellites**

For space applications, SDR has unique challenges such as extreme radiation and temperature environment, autonomous operational requirements, limitations on size, weight and power (SWAP), and the need for reduced development time and increased reliability in agile prototyping. In this section, recent applications of software defined radio to satellite, as well as the current status of radiation-hardened SDR components, are presented.

#### *4.2.1 NASA STRS*

Recognizing early on that a standard and open architecture is needed to encourage reuse and portability of software, NASA developed an open architecture specification for space and ground SDRs called the Space Telecommunications Radio System (STRS) [9]. From this standard, several compliant systems have been built and demonstrated in radios on the International Space Station (ISS) and several ground stations. It was also the intention of NASA that the STRS architecture should be used as baseline for many future NASA space communications technologies.

In a nutshell, the STRS standard consists of hardware, configurable hardware design, and software architectures with accompanying description, guidance, and requirements. The three main hardware functionalities are connected by the Hardware Interface Description10 (HID) and described and shown in **Figure 15** below:


<sup>10</sup> In a HID, the hardware architecture requirements are written so that the hardware provider defines the functional modules of the system and publishes the functions and interfaces for each module and for the entire STRS platform [Wikipedia].

**Figure 15.**

*NASA STRS' three main hardware functionalities.*

In STRS terminology, software includes source code, object code, executables, etc. implemented on a processor. As shown in **Figure 16**, the STRS software architecture uses three primary interfaces: the STRS APIs, STRS hardware abstraction layer11 (HAL) specification, and the Portable Operating System Interface12 (POSIX®). The STRS APIs provide the interfaces that allow applications to be instantiated and use platform services.

Configurable hardware designs are the items and designs, such as hardware description language (HDL) source, loadable files, data tables, etc., implemented in a configurable hardware device such as a FPGA.

STRS encourages the development of applications that are modular, portable, reconfigurable, and reusable. The STRS software, configurable hardware design, metadata, documentation for STRS applications, STRS devices, and operating environments (OEs) are submitted to NASA STRS Application Repository to allow applications to be reused in the future with appropriate release agreements.

#### *4.2.2 SDR applications in CubeSats*

CubeSats13 are increasingly popular spacecraft platforms for mission-oriented experiments that can be accomplished via quick prototyping and launches [10–12].

<sup>11</sup> Hardware abstraction layer (HAL) is a layer of programming that allows a computer operating system to interact with a hardware device at a general or abstract level rather than at a detailed hardware level [Wikipedia].

<sup>12</sup> The Portable Operating System Interface (POSIX) is a family of standards specified by the IEEE Computer Society for maintaining compatibility between operating systems. POSIX defines the application programming interface (API) for software compatibility with variants of Unix and other operating systems [Wikipedia].

<sup>13</sup> CubeSats are a class of Small Satellites (SmallSats) weighing between 1 kg and 10 kgs that use standard size and form factor of 1 U (one unit) of 10 cm x 10 cm x 10 cm. A standard 3 U CubeSat (10 cm x 10 cm x 34 cm, 5 and 6 kg) has been demonstrated to support real mission, and larger CubeSats (6 U, 12 U, and 24 U) are developed.

*Communication Subsystems for Satellite Design DOI: http://dx.doi.org/10.5772/intechopen.93010*


#### **Figure 16.**

*STRS software architecture layers.*

This short development timeline is due to the use of commercial-off-the-shelf (COTS) technology that typically has limited resilience to the space environment. Therefore, CubeSat usage has largely been limited to experiments or applications where high availability is not the main objective.

In general, SDR technology will allow for on-orbit flexibility via reconfigurability of data management, protocols, multiple access methods, waveforms, and data protection. SDR processing requirements are inherently scaled to the application. The availability of modular, high-performance sequential and parallel processors that are resilient to radiation upsets allows the tailoring of hardware architectures to the application and to the CubeSat platform. This is especially suitable for missions that require the flexibility to support multiple TT&C and mission data from multiple satellites and ground stations [13–15].

Given the provided mission flexibility, implementing an SDR on a CubeSat could significantly increase the required processing capacity and thus the size, weight, power and cost (SWAP-C) of the SDR implementation. Consequently, most current CubeSat SDR design and implementation are still customized depending on the mission requirements. In [16], some of the current COTS SDR hardware and software platforms such as GomSpace, Ettus Research USRP, EPIQ Solutions, Lime Microsystems, FunCube, and RTL SDR are described and categorized in decreasing cost and mass to illustrate the heterogeneous nature of SDR in CubeSat applications. Also described are a number of space and ground segment systems built to be (or have been) launched using these COTS SDRs or components thereof. What would be needed is a standard for CubeSat SDR similar to NASA STRS to ensure that hardware and software reuse can be incorporated into future CubeSat developments.

#### *4.2.3 SDR applications in emitter location from space*

A pioneering commercial application of SDR in space is the HawkEye 360 (HE360) system [17] that was launched on 3 December 2018. HE360 system consists of three identical spacecrafts and their primary payload is a SDR with custom RF front-end along with VHF Ku-band antennas. This Pathfinder mission14 was to enable onboard reception and geolocation of different types of terrestrial RF signals using signal processing technique to combine received data from all three payloads15.

One commercial application of this mission is the detection and geolocation of a maritime vessel's automatic identification system (AIS), which broadcasts the locations generated by GPS-enabled receiver. The locations generated by AIS can be disabled or spoofed, therefore not reliable. Another application would be to allow regulators, telecommunications companies, and broadcasters to globally monitor spectrum usage and identify areas of interference. The system can also be used to help large area search and rescue operations by quickly locating activated emergency beacons.

The SDR developed for the Pathfinder payload consists of an embedded processor system and three baseband processors. The baseband processor was built around the Analog Devices 9361 (AD9361) System on Chip (SoC) product, which is a highly integrated RF transceiver that combines high-speed ADCs and DACs, RF amplifiers, filtering, switching plus more. The HE360 payload supported up to three receiver channels (one AD9361 per channel) that can be simultaneously processed on separate frequencies. In addition, the signal processing subsystem takes advantage of open-source software and firmware code to allow system development to proceed without knowing the final space hardware. GNURadio16 was selected for being a free and open-source toolkit for SDR and widely used in small space projects for ground software processing.

#### *4.2.4 Radiation hardening and its current status on SDR hardware*

In space, most semiconductor electronic components are susceptible to radiation damage, thus radiation-hardened (or rad-hard) components are required and normally developed based on their COTS equivalents with variations in design and manufacturing17 to reduce the susceptibility to radiation. Consequently, rad-hard components tend to lag behind most recent COTS developments. Depending on mission requirements, rad-hard products are typically selected and tested using popular metrics such as total ionizing dose18 (TID), and single event effects19 (SEEs).

<sup>14</sup> A Pathfinder mission is usually a demonstration to prove that a system can successfully achieve a specific objective before a full mission can deploy.

<sup>15</sup> By comparing time-of-arrival (TOA) and frequency-of-arrival (FOA) measurements between pairs of receivers, the position of a signal can be computed.

<sup>16</sup> GNU is a recursive acronym for "GNUs Not Unix!" chosen because GNU's design is Unix-like but differs from Unix by being free software and containing no Unix code.

<sup>17</sup> Design trade-offs choosing more better radiation tolerance integrated circuit technology, low-power Schottky vs. Emitter Couple Logic (ECL) vs. bipolar over CMOS. Rad-hard chips are often manufactured on insulating substrates (silicon on insulator, silicon on sapphire, silicon carbide, gallium nitride) instead of the usual semiconductor wafers. Shielding the package against radioactivity to reduce exposure of the bare device.

<sup>18</sup> TID causes slow gradual degradation of the device's performance and is measured in rads.

<sup>19</sup> SEEs are caused by a single energy particle and can be (a) non-destructive Single Event Upset (SEU) causing transient pulses in logic or support circuitry or as bitflips in memory cells or registers, (b) potentially destructive Single Event Latch-up (SEL) that may be cleared by a power reset, and (c) destructive Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR), which is irreversible.

*Communication Subsystems for Satellite Design DOI: http://dx.doi.org/10.5772/intechopen.93010*

Per US DoD MIL-PRF-38535 J standard [18], an ideal integrated circuit for space applications is the qualified manufacturing line20 (QML) Class V with radiation hardness assurance21 (RHA) level identified in the part specification. From the perspective of payload designer and developer, only Class V is space quality and should be the main factor for selecting SDR hardware components.

The FPGA is perhaps the most important component of an SDR and has a long history for manufactured QML class V parts where rad-hard Xilinx and Actel (now Microsemi) FPGAs were studied [19]. Currently, Xilinx is the major player for space-qualified QML level V products used in actual payloads with many more devices under development. The rad-hard DSP products also follow the QML process, with Texas Instrument (TI) currently taking the lead for in-flight payloads with many offerings in space-qualified RF components in addition to DSP. Similarly, space-qualified GPP follows the same QML path as FPGA and DSP, and the current on-flight rad-hard GPPs based on the following architecture are [20].


#### **5. Summary and conclusions**

In the first section of this chapter, an overview of the satellite bus and payload subsystems are presented for command and data handling subsystem (C&DHS); communications subsystem (CS); electrical power subsystem (EPS); propulsion subsystem (PS); thermal control subsystem (TCS); attitude control subsystem (ACS) also known as guidance, navigation and control (GNC) subsystem; and structures and mechanics subsystem (S&MS). A significant portion is spent on describing the C&DHS and CS with much details on how they are related to other satellite subsystems for continuous operation.

There are distinctive functional separations between the satellite bus and payload that are discussed at a high level with some examples given; however, there are currently no existing standard on their interfaces due to legacy satellite design and development. Examples were given for mission-specific sensing and communications payloads, showing that pretty much all mission payloads are very customized in design in legacy systems.

The second section of this chapter covers software defined radio (SDR) as a new technology with an overview and how SDR is being applied to satellite design and development in both space and ground segments. There has been a NASA standard for SDR that has been used for traditional and large satellites and shown to have some advantages over non-SDR approach.

However, recent rapid developments of Small Satellites (SmallSats), which CubeSat is a subset of, have resulted in an explosion of SDR applications to build

<sup>20</sup> For QML microcircuits, the manufacturer is required to develop a program plan that meets or exceeds the performance detailed in these appendices of MIL-PRF-38535 J standard.

<sup>21</sup> RHA is quantified in terms of the radiation level in Total Ionizing Dose or TID.

Pathfinder missions that can lead to successful follow-on projects. There remains to be a standard to be defined for SDR for this CubeSat application. Regardless, SDR is providing a path forward to a common framework that may enable a more generic building block for a future concept called Software Defined Satellite that will change missions based on a software upload.

Since SDR is becoming an important part of a satellite, radiation hardening of the relevant SDR components is described in some detail. The area is evolving slowly despite fast changing technology due to the additional design and manufacturing steps taken to ensure minimum effects of radiation on microelectronics. The selection of the appropriate rad-hard FPGA, DSP, and GPP components should be an important factor in design trade-offs when SDR is being considered for future missions.
