**4.1 Architecture of analog DFR system**

**Figure 8** demonstrates the architecture of our analog DFR system, as published in [43, 44]. During the operation, the high dimensional projection within the reservoir layer, as illustrated in **Figure 9**, is the key module to separate input patterns into different categories [26]. For instance, with low dimensional spaces, two different objects cannot be linearly separated by a single cut-off line, as shown in **Figure 9a**. However, by projecting input patterns onto higher dimensional spaces, from twodimensional to three-dimensional, the separability of the system changes accordingly. As demonstrated in **Figure 9b**, the same objects are linearly separated by a single cut-off plane without changing their original *xy* position. Our analog DFR chip was fabricated through the GF 130*nm* CMOS technology, as demonstrated in **Figure 10**.

In our analog DFR system, the dynamic behavior can be controlled by changing the total delay time within the feedback loop. Along the feedback loop, the total delay time, *T*, is separated into *N* intermediate neurons with an identical delayed time constant, τ*delay*, such that

$$
\pi\_{\text{delay}} = \frac{T}{N}.\tag{10}
$$

In the conventional reservoir computing system, represented by the echo state network (ESN), the memory within the reservoir layer fades in time due to the way that neurons are sparsely connected; such fading memory limits the performance of computation [20]. With the delay-feedback topology embedded, our analog DFR system not only reduces the implementation complexity but also overcomes the drawback of fading memory limitation. Such functionality enables the knowledge transfer processing technique, allowing new incoming input data to carry information from its previous states, as depicted in **Figure 11**. The expression of *Nth* output, *SN*, can be simplified as

$$S\_N = f\left[I\_P(\infty) + \sum\_{x=1}^N I\_{P-1}(\infty) \cdot A \, v^x\right],\tag{11}$$

where the function, *f*[ ], represent the nonlinear transformation of input signal; *Ip*(*x*) and *Ip*−1(*x*) indicate the current and previous input patterns, respectively; *Av* is the finite gain of the gain regulator within the reservoir layer.

## **4.2 Delay characteristic**

Along the feedback loop, the delay time constant, <sup>τ</sup>*delay*, can be controlled by the integration time over the membrane capacitor, which can be expressed as

$$
\pi\_{delay} = \mathbf{C}\_m \cdot \frac{V\_m}{T\_{cc}}.\tag{12}
$$

In general, the mathematical model of the delay time constant is represented by the values of resistance and capacitance. In the LIF delay neuron, the input impedance, *Rin*, is equivalent to \_\_\_ *Vm Iex* , thus, the delay time constant can be simplified as

$$
\pi\_{delay} = \mathbb{C}\_m \cdot R\_{in}.\tag{13}
$$

**19**

**Figure 10.**

*Die photo of our fabricated analog DFR chip.*

**Figure 9.**

**Figure 8.**

*Architecture of our analog DFR system.*

*spaces.*

*Opening the "Black Box" of Silicon Chip Design in Neuromorphic Computing*

The feedback loop, which is constructed by multiple LIF neurons, as illustrated in **Figure 12**. To enable the spiking signal propagation, the output spike train from the previous neuron is utilized as the clock signal to trigger its following neuron.

*(a) Nonlinear classification with low dimensional spaces and (b) linear classification with high dimensional* 

*DOI: http://dx.doi.org/10.5772/intechopen.83832*

*Opening the "Black Box" of Silicon Chip Design in Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.83832*

The feedback loop, which is constructed by multiple LIF neurons, as illustrated in **Figure 12**. To enable the spiking signal propagation, the output spike train from the previous neuron is utilized as the clock signal to trigger its following neuron.

**Figure 8.** *Architecture of our analog DFR system.*

**Figure 9.**

*Bio-Inspired Technology*

**4.1 Architecture of analog DFR system**

time constant, τ*delay*, such that

*SN* = *f*

**4.2 Delay characteristic**

ance, *Rin*, is equivalent to \_\_\_

gain of the gain regulator within the reservoir layer.

τ*delay* = *Cm* ∙ \_\_\_

*Vm Iex*

be simplified as

τ*delay* = \_\_*<sup>T</sup>*

computing. By employing the delayed feedback structure within the system, our analog DFR system processes the functionality of high dimensional projection and short-term dynamic memory, whereby the behavior of biological neuron is achieved.

**Figure 8** demonstrates the architecture of our analog DFR system, as published in [43, 44]. During the operation, the high dimensional projection within the reservoir layer, as illustrated in **Figure 9**, is the key module to separate input patterns into different categories [26]. For instance, with low dimensional spaces, two different objects cannot be linearly separated by a single cut-off line, as shown in **Figure 9a**. However, by projecting input patterns onto higher dimensional spaces, from twodimensional to three-dimensional, the separability of the system changes accordingly. As demonstrated in **Figure 9b**, the same objects are linearly separated by a single cut-off plane without changing their original *xy* position. Our analog DFR chip was fabricated through the GF 130*nm* CMOS technology, as demonstrated in **Figure 10**. In our analog DFR system, the dynamic behavior can be controlled by changing the total delay time within the feedback loop. Along the feedback loop, the total delay time, *T*, is separated into *N* intermediate neurons with an identical delayed

In the conventional reservoir computing system, represented by the echo state network (ESN), the memory within the reservoir layer fades in time due to the way that neurons are sparsely connected; such fading memory limits the performance of computation [20]. With the delay-feedback topology embedded, our analog DFR system not only reduces the implementation complexity but also overcomes the drawback of fading memory limitation. Such functionality enables the knowledge transfer processing technique, allowing new incoming input data to carry information from its previous states, as depicted in **Figure 11**. The expression of *Nth* output, *SN*, can

> [*Ip*(*x*) + ∑ *x*=1 *N*

integration time over the membrane capacitor, which can be expressed as

where the function, *f*[ ], represent the nonlinear transformation of input signal; *Ip*(*x*) and *Ip*−1(*x*) indicate the current and previous input patterns, respectively; *Av* is the finite

Along the feedback loop, the delay time constant, <sup>τ</sup>*delay*, can be controlled by the

In general, the mathematical model of the delay time constant is represented by the values of resistance and capacitance. In the LIF delay neuron, the input imped-

τ*delay* = *Cm* ∙ *Rin*. (13)

*Vm Iex*

, thus, the delay time constant can be simplified as

*IP*−1(*x*) ∙ *Av<sup>x</sup>*

*<sup>N</sup>*. (10)

], (11)

. (12)

**18**

*(a) Nonlinear classification with low dimensional spaces and (b) linear classification with high dimensional spaces.*

**Figure 10.** *Die photo of our fabricated analog DFR chip.*
