**4.3 Dynamic behavior**

In general, the phase portrait is used to visualize how solutions of a delay system would behave. In this experiment, measured phase portraits are plotted through two signals from the feedback loop where one of them is recorded with the time

**21**

minify the die area by 35% [57].

**5.1 Memristor**

device changes.

*Opening the "Black Box" of Silicon Chip Design in Neuromorphic Computing*

delay, as shown in **Figure 13**. As the total delay time within the feedback loop increases, the dynamic behavior of the system changes accordingly. As plotted in **Figure 13b**, the delayed signal repeatedly traces its initial path when the total delay time within the feedback loop maintains around 1 μs, indicating as the periodic. When the total delay time within the feedback increases to 1.4 μs, as shown in **Figure 13d**, the delayed signal diverges its initial path but still tracking its equilib-

To closely mimic functionalities of mammalian brains, electronic neurons and synapses in neural network designs need to be constructed in a network configuration, which demands extremely high data communication bandwidth between neurons and high connectivity neural network degree [45, 46]. However, these requirements are not achievable through the traditional von Neumann architecture or the two-dimensional (2D) IC design methodology. Recently, a novel 3D neuromorphic computing system that stacks the neuron and synapse vertically has been proposed as a promising solution with lower power consumption, higher data transferring rate, high network degree, and smaller design area [47, 48]. There are two 3D integration techniques that can be used in the hardware implementation of neuromorphic computing: (1) through-silicon via (TSV) 3D-IC and (2) monolithic 3D-IC. A well-known 3D integration technique is to use the TSV as vertical connection to bond two wafers. In this structure, a large capacitance that is formed by TSVs can be used to build the membrane capacitor, which is required in neuron firing behavior [49–51]. Unlike the TSV 3D-IC technique that uses separately fabrication processes, the monolithic 3D-IC technique is capable to integrate multiple layers of devices at a single wafer, thus, the monolithic 3D-IC technique is capable to provide

*DOI: http://dx.doi.org/10.5772/intechopen.83832*

rium point, indicating as the edge-of-chaotic.

**5. Three-dimensional neuromorphic computing**

a smaller design area with lower power consumption [52, 53].

**5.2 Memristor-based 3D neuromorphic computing**

In neural network designs, the electronic circuit model of synapses can be implemented by an emerging non-volatile device, namely the memristor, which is a class of the resistive random-access memory (RRAM). In general, the memristor device is constructed in a metal-insulator-metal (MIM) structure, as illustrated in **Figure 14a**. The resistance of a memristor device can be gradually changed between its low resistance state and high resistance state as the voltage across the memristor

Memristors are typically fabricated in a 2D crossbar structure [54], which can be

further extended to 3D space, as illustrated in **Figure 14c** and **d**, respectively.

In the field of ANN designs, a novel 3D neural network architecture, which combines memristors and the monolithic 3D-IC technique, has been proposed [55]. In this structure, neurons and memristor-based synaptic array are stacked vertically, as demonstrated in **Figure 15** [48]. As a non-volatile device, RRAM is capable save static power consumption with small implementation area while maintaining its weighted value. With the monolithic 3D-IC technique, the memristor-based 3D neuromorphic computing can potentially reduce the length of critical path by 3X [56], increase the scalability [52], decrease the power consumption by 50% as well as *Opening the "Black Box" of Silicon Chip Design in Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.83832*

delay, as shown in **Figure 13**. As the total delay time within the feedback loop increases, the dynamic behavior of the system changes accordingly. As plotted in **Figure 13b**, the delayed signal repeatedly traces its initial path when the total delay time within the feedback loop maintains around 1 μs, indicating as the periodic. When the total delay time within the feedback increases to 1.4 μs, as shown in **Figure 13d**, the delayed signal diverges its initial path but still tracking its equilibrium point, indicating as the edge-of-chaotic.
