**2.1. Phase-formation sequences**

There has been a lot of work reported on the solid-state interactions in the Ni/Ge system [1–5] but interactions in the Pd/Ge system have not been as extensively reported on [6–8]. The available reports agree on the second and the final phase NiGe formed in the Ni/Ge system, but there is some disagreement on the first phase. There is agreement that Pd<sup>2</sup> Ge is the first phase to be formed in the Pd/Ge system, the second and final phase to be formed is also agreed upon to be PdGe. These phases are generally reported to form sequentially [7, 9]. Our results [10, 11] for the phase-formation sequences, formation temperatures, and dominant diffusing species (DDS) during reactive diffusion in the Ni/Ge and Pd/Ge systems, obtained using in-situ (real-time) Rutherford Backscattering Spectrometry (RBS) and particle induced X-ray emission (PIXE) are summarized in **Table 1**.

We see from **Table 1** that in order to produce NiGe at an interface, the annealing temperature needs to be above 250°C. Below that temperature, Ni<sup>5</sup> Ge<sup>3</sup> is produced. We also see that PdGe needs to be formed above an annealing temperature of 180°C, below which Pd<sup>2</sup> Ge is formed. One positive aspect from these results in terms of device fabrication is that the two phases of interest, which are NiGe and PdGe, are the final phases to be formed in the Ni/Ge and Pd/Ge systems, respectively. What this means is that annealing at temperatures above 250°C and 180°C in the Ni/Ge and Pd/Ge systems respectively would effectively avoid the formation of the other phases of the systems.


**Table 1.** Summary of our results for the thin film couple phase-formation sequences, phase-formation temperatures, and dominant diffusing species during the respective phase growths in the Ni/Ge and Pd/Ge systems [10, 11].

### **2.2. NiGe contacts**

We present a review of some of the novel interface control processes developed for the fabrica-

There has been a lot of work reported on the solid-state interactions in the Ni/Ge system [1–5] but interactions in the Pd/Ge system have not been as extensively reported on [6–8]. The available reports agree on the second and the final phase NiGe formed in the Ni/Ge system,

phase to be formed in the Pd/Ge system, the second and final phase to be formed is also agreed upon to be PdGe. These phases are generally reported to form sequentially [7, 9]. Our results [10, 11] for the phase-formation sequences, formation temperatures, and dominant diffusing species (DDS) during reactive diffusion in the Ni/Ge and Pd/Ge systems, obtained using in-situ (real-time) Rutherford Backscattering Spectrometry (RBS) and particle induced

We see from **Table 1** that in order to produce NiGe at an interface, the annealing temperature needs

aspect from these results in terms of device fabrication is that the two phases of interest, which are NiGe and PdGe, are the final phases to be formed in the Ni/Ge and Pd/Ge systems, respectively. What this means is that annealing at temperatures above 250°C and 180°C in the Ni/Ge and Pd/Ge systems respectively would effectively avoid the formation of the other phases of the systems.

Ge, PdGe

2nd NiGe, PdGe

Ge 140–150°C

Ge 60% Pd and 40% Ge PdGe 65% Pd and 35% Ge

**Table 1.** Summary of our results for the thin film couple phase-formation sequences, phase-formation temperatures, and

dominant diffusing species during the respective phase growths in the Ni/Ge and Pd/Ge systems [10, 11].

Ge<sup>3</sup> 150°C

NiGe 250°C PdGe 180°C

Ge<sup>3</sup> Ni

Ge<sup>3</sup> , Pd<sup>2</sup> Ge

NiGe Ni is the DDS; Ge diffusion observed during the early stages of growth.

Ge<sup>3</sup>

Ge is the first

is produced. We also see that PdGe needs to

Ge is formed. One positive

but there is some disagreement on the first phase. There is agreement that Pd<sup>2</sup>

tion of NiGe/*n*-Ge and PdGe/*n*-Ge Schottky and ohmic contacts.

**2. Results and discussion**

70 Advanced Material and Device Applications with Germanium

**2.1. Phase-formation sequences**

X-ray emission (PIXE) are summarized in **Table 1**.

be formed above an annealing temperature of 180°C, below which Pd<sup>2</sup>

Ge<sup>3</sup>

Phase-formation sequence 1st Ni<sup>5</sup>

Pd<sup>2</sup>

Pd<sup>2</sup>

, NiGe, Pd<sup>2</sup>

to be above 250°C. Below that temperature, Ni<sup>5</sup>

Phases observed Ni<sup>5</sup>

Phase-formation temperatures Ni<sup>5</sup>

Diffusing species Ni<sup>5</sup>

### *2.2.1. Cyclically stacked NiGe contacts*

One of the concerns regarding NiGe contacts on *n*-type Ge substrates is that other phases of the Ni/Ge system apart from NiGe are formed below 250°C. Another concern is the reaction of the deposited Ni film and the Ge substrate, which increases the interface roughness. Suppression of this interface reaction by the use of cyclic stacking, as explained in Section 2.1.3 of the previous chapter, is advantageous in obtaining a flat interface between NiGe and the Ge substrates. This was done in an investigation carried out by Motoki [12]. The wafers used in this study were *n*-type Ge (100) with a doping density of 4.0 × 10<sup>16</sup> cm−3. These substrates were treated with HF after which sets of Ni/Ge (0.5 nm/1.3 nm) layers were cyclically stacked eight times using RF magnetron sputtering. The thickness of the layers corresponded to an atomic ratio between Ni and Ge of 1 to 1, as in the phase NiGe. As explained in Section 2.1.3 of the previous chapter, the concept behind this process is to suppress the interface reaction, upon annealing, between the deposited Ni and the Ge substrate, hence reducing the number of interface electron energy states. The samples configuration is illustrated in **Figure 1**.

Two samples of cyclically stacked Ni/Ge were produced, one with 8 Ni/Ge cycles (referred to as sets in the figures) and the other with 16 cycles. In order to see if cyclic stacking produces improved results, two other samples were prepared with Ni films of thickness 3.0 and 5.5 nm respectively on Ge substrates without cyclic stacking, for comparison. The four types of samples, including the cyclically stacked ones, were annealed in nitrogen (N<sup>2</sup> ) gas at annealing temperatures that ranged from 200 to 500°C for 1 min. Four-terminal sheet resistance measurements were carried out on the samples as explained in Section 2.3 of the previous chapter. **Figure 2** shows experimental results of the sheet resistivity (*ρsh*) of the films as a function of the annealing temperature. We see a large decrease in sheet resistivity for the sample with a 3.0 nm-thick Ni film and no cyclic stacking within the temperature range from 200 to around 300°C. This is attributed to the formation of the NiGe phase. When the annealing temperature is over 350°C, the sheet resistivity shows a large increase owing to thermal instability. In the sample with a 5.5 nm-thick Ni layer and no cyclic stacking, the temperature range of the NiGe thermal phase stability is wider than that for the

**Figure 1.** Cyclically stacked samples to suppress the interface reaction, upon annealing, between the deposited Ni and the Ge substrate.

semilogarithmic scale in the reverse bias directions (negative anode voltage region) are very small compared to those in the forward bias direction, showing that the contacts are rectify-

Interface Control Processes for Ni/Ge and Pd/Ge Schottky and Ohmic Contact Fabrication: Part Two

The height of the Schottky potential barrier, Φ*Bn* and the ideality *n*-factor were extracted from the I-V characteristics of the Schottky diodes at various annealing temperatures using the thermionic emission model, as explained in Section 1.1.4 of the previous chapter. Equations (11) and (12), of the previous chapter, were used to extract Φ*Bn* and the ideality *n*-factor respectively. The

for the sample with a 5.5 nm-thick Ni layer (no cyclic stacking) and the Ni/Ge cyclically stacked

It is seen in **Figure 4** that the determination of both Φ*Bn* and the ideality *n*-factor was repeated a number of times at each temperature, showing some experimental scattering errors, but the general trends are clear. The values of Φ*Bn* that are determined for the sample with a 5.5 nm Ni film and the cyclically stacked Ni/Ge sample, annealed up to 600°C were within 0.54–0.57 and 0.53–0.55 eV, respectively. The ideality factor showed values of less than 1.3 for the cyclically stacked sample. We see in **Figure 4** that in this sample, the ideality factor could be maintained at values lower than 1.2 up to a temperature of 500°C, and it increases slightly at 600°C. In the

**Figure 4.** Heights of the potential barrier and the ideality *n*-factors for the Schottky contacts with stacked NiGe and with

a 5.5 nm-thick Ni film, at various annealing temperatures [12].

sample with eight layers are shown in **Figure 4**, for annealing temperatures up to 600°C.

K2

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. The results

73

value of the effective Richardson constant, *A*\* used in this study was 133 A/cm<sup>2</sup>

ing, which is typical Schottky diode behavior.

**Figure 2.** Experimental results of the sheet resistivity (*ρsh*) of Ni/Ge films as a function of the annealing temperature [12].

**Figure 3.** Current-voltage characteristics of the cyclically stacked NiGe at various annealing temperature from 200 to 600°C [12].

sample with the 3.0 nm-thick Ni layer. On the other hand, for the samples with cyclic stacking, a reduction in *ρsh* was observed over 250°C, and the value became stable at annealing temperatures from 275 to around 500°C. This demonstrates that cyclic stacking produces improved results.

**Figure 3** shows the current-voltage characteristics of the cyclically stacked NiGe at various annealing temperature from 200 to 600°C. It is seen that the current density profile on a semilogarithmic scale in the reverse bias directions (negative anode voltage region) are very small compared to those in the forward bias direction, showing that the contacts are rectifying, which is typical Schottky diode behavior.

The height of the Schottky potential barrier, Φ*Bn* and the ideality *n*-factor were extracted from the I-V characteristics of the Schottky diodes at various annealing temperatures using the thermionic emission model, as explained in Section 1.1.4 of the previous chapter. Equations (11) and (12), of the previous chapter, were used to extract Φ*Bn* and the ideality *n*-factor respectively. The value of the effective Richardson constant, *A*\* used in this study was 133 A/cm<sup>2</sup> K2 . The results for the sample with a 5.5 nm-thick Ni layer (no cyclic stacking) and the Ni/Ge cyclically stacked sample with eight layers are shown in **Figure 4**, for annealing temperatures up to 600°C.

It is seen in **Figure 4** that the determination of both Φ*Bn* and the ideality *n*-factor was repeated a number of times at each temperature, showing some experimental scattering errors, but the general trends are clear. The values of Φ*Bn* that are determined for the sample with a 5.5 nm Ni film and the cyclically stacked Ni/Ge sample, annealed up to 600°C were within 0.54–0.57 and 0.53–0.55 eV, respectively. The ideality factor showed values of less than 1.3 for the cyclically stacked sample. We see in **Figure 4** that in this sample, the ideality factor could be maintained at values lower than 1.2 up to a temperature of 500°C, and it increases slightly at 600°C. In the

**Figure 3.** Current-voltage characteristics of the cyclically stacked NiGe at various annealing temperature from 200 to

**Figure 2.** Experimental results of the sheet resistivity (*ρsh*) of Ni/Ge films as a function of the annealing temperature [12].

72 Advanced Material and Device Applications with Germanium

sample with the 3.0 nm-thick Ni layer. On the other hand, for the samples with cyclic stacking, a reduction in *ρsh* was observed over 250°C, and the value became stable at annealing temperatures from 275 to around 500°C. This demonstrates that cyclic stacking produces improved results.

**Figure 3** shows the current-voltage characteristics of the cyclically stacked NiGe at various annealing temperature from 200 to 600°C. It is seen that the current density profile on a

600°C [12].

**Figure 4.** Heights of the potential barrier and the ideality *n*-factors for the Schottky contacts with stacked NiGe and with a 5.5 nm-thick Ni film, at various annealing temperatures [12].

sample with a 5.5 nm Ni film and no cyclic stacking, the values of the *n*-factor were very large for temperatures above 400°C, owing to thermal instability of NiGe films in this sample. This result is consistent with the sheet resistivity result presented in **Figure 2**. In **Figure 2**, we see that the sheet resistivity for this sample rises rapidly around 400°C.

### *2.2.2. Interface dopant incorporation*

A sample with 22 nm of Ni on an *n*-type Ge substrate and another with 30 nm of Ni<sup>3</sup> P on an *n*-type Ge were prepared by plasma deposition. **Figure 5** shows a schematic illustration of the two samples.

Current-voltage characteristics were obtained at various annealing temperatures (for 1 min) for the two samples in order to extract the Schottky potential barrier heights, ΦBn using the thermionic emission model. The results are shown in **Figure 6**.

The ideality *n*-factor for the sample with a 22-nm-thick Ni film was also determined and is presented in **Figure 6**. It can be seen in **Figure 6** that the determination of Φ*Bn* and the *n*-factor was repeated a number of times at each temperature, showing some experimental scattering error. It is clear that the values of Φ*Bn* for the Ni/*n*-Ge sample remained almost constant over the whole temperature range of annealing. It is however seen that the values of Φ*Bn* for the Ni<sup>3</sup> P/*n*-Ge sample gradually decreases with increased temperature and the lowest ΦBn value is achieved at 600°C, after which the value increases. The ideality factor of the Ni/*n*-Ge sample gradually increases but does not go above the value of 1.5.

Since we see from **Figure 6** that the values of Φ*Bn* for the Ni<sup>3</sup> P/*n*-Ge sample are the lowest at 600°C, we now focus on the current-voltage characteristics at this temperature alone for both the Ni/*n*-Ge and Ni<sup>3</sup> P/*n*-Ge samples, the results are shown in **Figure 7**.

We see in **Figure 7(a)** that the current density profiles on a semilogarithmic scale for the forward and reverse bias (negative voltage region) directions are symmetric about the zero anode voltage axis for the Ni<sup>3</sup> P/*n*-Ge sample, suggesting Ohmic characteristics. On the other hand, for the Ni/*n*-Ge samples, in the reverse bias direction, the current density is very small compared to that in the forward bias direction, showing that the contact is rectifying. In **Figure 7(b)**, the current density profile is presented on a linear scale. For the Ni<sup>3</sup> P/*n*-Ge sample, we get a straight line which confirms that this is an ohmic contact. The corresponding result for the Ni/*n*-Ge sample clearly shows that it is not an ohmic contact. It shows Schottky diode

characteristics as was illustrated schematically in **Figure 11** of the previous chapter. **Figure 8**

**Figure 6.** (a) Potential barrier heights at various annealing temperatures (for 1 min) for Ge Schottky contacts with a

P film and with a 22 nm-thick Ni film. (b) The ideality *n*-factor for the sample with a 22 nm-thick Ni film

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75

ited contact. **Figure 8(b)** shows a much thicker reaction region up to a depth of 77.8 nm below the original interface. We saw in **Figure 6** that ohmic behavior was not achieved for annealing temperatures that were less than 600°C. It appears that at 600°C, the P atoms penetrated enough into the *n*-Ge substrate to form an interface region inside the substrate which is heavily doped by P atoms. This facilitates for the ohmic characteristics observed

sets of Ni/Ge (0.5 nm/1.3 nm) layers were cyclically stacked seven times. **Figure 9** shows a

P was plasma deposited on an *n*-type Ge substrate after which

P (30 nm)/*n*-Ge

P in the as-depos-

shows a cross-sectional scanning electron microscope (SEM) image of the Ni<sup>3</sup>

The SEM micrograph in **Figure 8(a)** shows a regular thickness of Ni<sup>3</sup>

*2.2.3. Cyclically stacked NiGe contacts with interface dopant incorporation*

at 600°C.

30 nm-thick Ni<sup>3</sup>

at various annealing temperatures [12].

A thin 0.68 nm film of Ni<sup>3</sup>

schematic illustration of the sample.

contact in the as-deposited state, (a) and after annealing at 600°C for 1 min, (b).

**Figure 5.** Schematic illustration of a sample with 22 nm of Ni on an *n*-type Ge substrate and another with 30 nm of Ni<sup>3</sup> P on *n*-type Ge.

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sample with a 5.5 nm Ni film and no cyclic stacking, the values of the *n*-factor were very large for temperatures above 400°C, owing to thermal instability of NiGe films in this sample. This result is consistent with the sheet resistivity result presented in **Figure 2**. In **Figure 2**, we see

*n*-type Ge were prepared by plasma deposition. **Figure 5** shows a schematic illustration of the

Current-voltage characteristics were obtained at various annealing temperatures (for 1 min) for the two samples in order to extract the Schottky potential barrier heights, ΦBn using the

The ideality *n*-factor for the sample with a 22-nm-thick Ni film was also determined and is presented in **Figure 6**. It can be seen in **Figure 6** that the determination of Φ*Bn* and the *n*-factor was repeated a number of times at each temperature, showing some experimental scattering error. It is clear that the values of Φ*Bn* for the Ni/*n*-Ge sample remained almost constant over the whole temperature range of annealing. It is however seen that the values of Φ*Bn* for the

P/*n*-Ge sample gradually decreases with increased temperature and the lowest ΦBn value is achieved at 600°C, after which the value increases. The ideality factor of the Ni/*n*-Ge sample

600°C, we now focus on the current-voltage characteristics at this temperature alone for both

hand, for the Ni/*n*-Ge samples, in the reverse bias direction, the current density is very small compared to that in the forward bias direction, showing that the contact is rectifying. In

we get a straight line which confirms that this is an ohmic contact. The corresponding result for the Ni/*n*-Ge sample clearly shows that it is not an ohmic contact. It shows Schottky diode

**Figure 5.** Schematic illustration of a sample with 22 nm of Ni on an *n*-type Ge substrate and another with 30 nm of Ni<sup>3</sup>

**Figure 7(b)**, the current density profile is presented on a linear scale. For the Ni<sup>3</sup>

P/*n*-Ge sample, suggesting Ohmic characteristics. On the other

P/*n*-Ge samples, the results are shown in **Figure 7**. We see in **Figure 7(a)** that the current density profiles on a semilogarithmic scale for the forward and reverse bias (negative voltage region) directions are symmetric about the zero

P on an

P/*n*-Ge sample are the lowest at

P/*n*-Ge sample,

P

A sample with 22 nm of Ni on an *n*-type Ge substrate and another with 30 nm of Ni<sup>3</sup>

that the sheet resistivity for this sample rises rapidly around 400°C.

thermionic emission model. The results are shown in **Figure 6**.

gradually increases but does not go above the value of 1.5.

Since we see from **Figure 6** that the values of Φ*Bn* for the Ni<sup>3</sup>

*2.2.2. Interface dopant incorporation*

74 Advanced Material and Device Applications with Germanium

two samples.

Ni<sup>3</sup>

the Ni/*n*-Ge and Ni<sup>3</sup>

on *n*-type Ge.

anode voltage axis for the Ni<sup>3</sup>

**Figure 6.** (a) Potential barrier heights at various annealing temperatures (for 1 min) for Ge Schottky contacts with a 30 nm-thick Ni<sup>3</sup> P film and with a 22 nm-thick Ni film. (b) The ideality *n*-factor for the sample with a 22 nm-thick Ni film at various annealing temperatures [12].

characteristics as was illustrated schematically in **Figure 11** of the previous chapter. **Figure 8** shows a cross-sectional scanning electron microscope (SEM) image of the Ni<sup>3</sup> P (30 nm)/*n*-Ge contact in the as-deposited state, (a) and after annealing at 600°C for 1 min, (b).

The SEM micrograph in **Figure 8(a)** shows a regular thickness of Ni<sup>3</sup> P in the as-deposited contact. **Figure 8(b)** shows a much thicker reaction region up to a depth of 77.8 nm below the original interface. We saw in **Figure 6** that ohmic behavior was not achieved for annealing temperatures that were less than 600°C. It appears that at 600°C, the P atoms penetrated enough into the *n*-Ge substrate to form an interface region inside the substrate which is heavily doped by P atoms. This facilitates for the ohmic characteristics observed at 600°C.

### *2.2.3. Cyclically stacked NiGe contacts with interface dopant incorporation*

A thin 0.68 nm film of Ni<sup>3</sup> P was plasma deposited on an *n*-type Ge substrate after which sets of Ni/Ge (0.5 nm/1.3 nm) layers were cyclically stacked seven times. **Figure 9** shows a schematic illustration of the sample.

**Figure 7.** (a) Current density profile on a semilogarithmic scale for the forward and reverse bias directions for Ni/*n*-Ge and Ni<sup>3</sup> P/*n*-Ge samples. (b) Current density profile of the same samples on a linear scale [12].

that both contacts are rectifying. Despite the reduction in the barrier height seen in **Figure 10**,

**Figure 10.** Potential barrier heights extracted at various temperatures for cyclically stacked NiGe with and without a

**Figure 9.** Schematic illustration of sets of Ni/Ge (0.5 nm/1.3 nm) layers cyclically stacked seven times over a thin 0.68 nm

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A silicon film with a varying thickness, *x*, is deposited on an *n*-type Ge substrate after which sets of Ni/Ge (0.5 nm/1.3 nm) layers were cyclically stacked seven times. Samples were prepared in this way for four different values of the Si film thickness, which are: *x* = 0.1, 0.3, 0.6 and 1.0 nm. Another set of similar samples were prepared with the only difference being the introduction

The current-voltage characteristics for samples without P incorporation (w/op) and with P incorporation (w/p), annealed at a temperature of 400°C for 1 min, are shown in **Figure 13** for

It can be seen in **Figure 13** that ohmic characteristics are observed for the contact with P incorporation (w/p) and a silicon film thickness of 0.1 nm. Current-voltage characteristics

**Figure 12** shows a schematic illustration of the two types of sample configuration.

P film does not result in an ohmic contact in this case.

P film between the Si film and the sets of Ni/Ge (0.5 nm/1.3 nm) layers.

the incorporation of a Ni<sup>3</sup>

thin 0.68 nm film of Ni<sup>3</sup>

film of Ni<sup>3</sup>

of a 0.68-nm-thick Ni<sup>3</sup>

*2.2.4. Interface insertion of a silicon film*

P [12].

P on an *n*-Ge(100) substrate [12].

the different values of Si thickness, *x*.

**Figure 8.** (a) A cross-sectional scanning electron micrograph of an as-deposited Ni<sup>3</sup> P/*n*-Ge contact. (b) A micrograph similar to the one presented in (a) but after annealing at 600°C [12].

Current-voltage characteristics were obtained at various annealing temperatures for 1 min. The potential barrier heights, Φ*Bn* were extracted using the thermionic emission model, as explained earlier. The results are shown in **Figure 10**, and results for cyclically stacked NiGe without a thin 0.68 nm film of Ni<sup>3</sup> P are also included in **Figure 10** for comparison.

It is seen in **Figure 10** that the Ni<sup>3</sup> P film reduces the barrier height by about 0.51 at 500°C. We now focus on the current-voltage characteristics at the temperatures of 400 and 500°C for both the cyclically stacked samples with and without an Ni<sup>3</sup> P film. The results are shown in **Figure 11**.

The sample without an Ni<sup>3</sup> P film is used as a control to compare with the one with an Ni<sup>3</sup> P film, the results from this sample are therefore labeled as "control" in **Figure 11**. It can be seen Interface Control Processes for Ni/Ge and Pd/Ge Schottky and Ohmic Contact Fabrication: Part Two http://dx.doi.org/10.5772/intechopen.79318 77

**Figure 9.** Schematic illustration of sets of Ni/Ge (0.5 nm/1.3 nm) layers cyclically stacked seven times over a thin 0.68 nm film of Ni<sup>3</sup> P on an *n*-Ge(100) substrate [12].

**Figure 10.** Potential barrier heights extracted at various temperatures for cyclically stacked NiGe with and without a thin 0.68 nm film of Ni<sup>3</sup> P [12].

that both contacts are rectifying. Despite the reduction in the barrier height seen in **Figure 10**, the incorporation of a Ni<sup>3</sup> P film does not result in an ohmic contact in this case.

#### *2.2.4. Interface insertion of a silicon film*

**Figure 8.** (a) A cross-sectional scanning electron micrograph of an as-deposited Ni<sup>3</sup>

Current-voltage characteristics were obtained at various annealing temperatures for 1 min. The potential barrier heights, Φ*Bn* were extracted using the thermionic emission model, as explained earlier. The results are shown in **Figure 10**, and results for cyclically stacked NiGe

**Figure 7.** (a) Current density profile on a semilogarithmic scale for the forward and reverse bias directions for Ni/*n*-Ge

P/*n*-Ge samples. (b) Current density profile of the same samples on a linear scale [12].

now focus on the current-voltage characteristics at the temperatures of 400 and 500°C for both

film, the results from this sample are therefore labeled as "control" in **Figure 11**. It can be seen

P are also included in **Figure 10** for comparison.

P film is used as a control to compare with the one with an Ni<sup>3</sup>

P film reduces the barrier height by about 0.51 at 500°C. We

P film. The results are shown in **Figure 11**.

similar to the one presented in (a) but after annealing at 600°C [12].

76 Advanced Material and Device Applications with Germanium

the cyclically stacked samples with and without an Ni<sup>3</sup>

without a thin 0.68 nm film of Ni<sup>3</sup>

It is seen in **Figure 10** that the Ni<sup>3</sup>

The sample without an Ni<sup>3</sup>

and Ni<sup>3</sup>

P/*n*-Ge contact. (b) A micrograph

P

A silicon film with a varying thickness, *x*, is deposited on an *n*-type Ge substrate after which sets of Ni/Ge (0.5 nm/1.3 nm) layers were cyclically stacked seven times. Samples were prepared in this way for four different values of the Si film thickness, which are: *x* = 0.1, 0.3, 0.6 and 1.0 nm. Another set of similar samples were prepared with the only difference being the introduction of a 0.68-nm-thick Ni<sup>3</sup> P film between the Si film and the sets of Ni/Ge (0.5 nm/1.3 nm) layers. **Figure 12** shows a schematic illustration of the two types of sample configuration.

The current-voltage characteristics for samples without P incorporation (w/op) and with P incorporation (w/p), annealed at a temperature of 400°C for 1 min, are shown in **Figure 13** for the different values of Si thickness, *x*.

It can be seen in **Figure 13** that ohmic characteristics are observed for the contact with P incorporation (w/p) and a silicon film thickness of 0.1 nm. Current-voltage characteristics

**Figure 11.** Current-voltage characteristics at the temperatures of 400 and 500°C for both the cyclically stacked samples with and without an Ni<sup>3</sup> P film [12].

**Figure 13.** Current-voltage characteristics for samples without P incorporation (a) and with P incorporation (b), annealed

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**Figure 14.** (a) Barrier heights at various temperatures of annealing and varying thickness of the Si film inserted, without the incorporation of P atoms. (b) A plot of results similar to the ones in (a) but with the incorporation of P atoms [12].

at a temperature of 400°C for 1 min and different values of Si thickness, *x* [12].

**Figure 12.** Schematic illustration of two types of cyclically stacked sample configurations with the insertion of a silicon film.

were obtained for annealing temperatures between 200 and 600°C. The barrier heights were determined at these temperatures of annealing and are presented in **Figure 14**.

We see in **Figure 14** that a silicon thickness of 0.1 nm gives the lowest barrier height for both types of samples. However, ohmic characteristics are only observed when P is incorporated and at an annealing temperature of 400°C, as seen in **Figure 13**. An annealing temperature of 300°C with *x* = 0.1 nm gives characteristics that are nearly ohmic as indicated in **Figure 14**.

The four materials, Si, NiGe, *n*-type Ge, and P doped *n*-type Ge have different work functions. These four materials therefore have individual energy band structures with the respective Fermi levels being at different positions relative to the vacuum level. After a contact between any of these materials is made, the Fermi level becomes constant throughout the system at equilibrium, and the energy bands, which should have continuous characteristics, therefore bend.

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**Figure 13.** Current-voltage characteristics for samples without P incorporation (a) and with P incorporation (b), annealed at a temperature of 400°C for 1 min and different values of Si thickness, *x* [12].

**Figure 12.** Schematic illustration of two types of cyclically stacked sample configurations with the insertion of a silicon

**Figure 11.** Current-voltage characteristics at the temperatures of 400 and 500°C for both the cyclically stacked samples

were obtained for annealing temperatures between 200 and 600°C. The barrier heights were

We see in **Figure 14** that a silicon thickness of 0.1 nm gives the lowest barrier height for both types of samples. However, ohmic characteristics are only observed when P is incorporated and at an annealing temperature of 400°C, as seen in **Figure 13**. An annealing temperature of 300°C with *x* = 0.1 nm gives characteristics that are nearly ohmic as indicated in **Figure 14**.

The four materials, Si, NiGe, *n*-type Ge, and P doped *n*-type Ge have different work functions. These four materials therefore have individual energy band structures with the respective Fermi levels being at different positions relative to the vacuum level. After a contact between any of these materials is made, the Fermi level becomes constant throughout the system at equilibrium, and the energy bands, which should have continuous characteristics, therefore bend.

determined at these temperatures of annealing and are presented in **Figure 14**.

film.

with and without an Ni<sup>3</sup>

P film [12].

78 Advanced Material and Device Applications with Germanium

**Figure 14.** (a) Barrier heights at various temperatures of annealing and varying thickness of the Si film inserted, without the incorporation of P atoms. (b) A plot of results similar to the ones in (a) but with the incorporation of P atoms [12].

**Figure 15(i)** shows this energy band bending at the NiGe/*n*-Ge interface. **Figure 15(ii)** and **(iii)** show the energy band bending at the NiGe:P/*n*-Ge and NiGe:P/Si/*n*-Ge interfaces respectively. We see the successive reduction in the Schottky potential barrier heights from 0.54 to 0.51 eV in **Figure 15(i)** and **(ii)** respectively and then 0.42 eV in the ohmic contact of **Figure 15(iii)**. The energy band bending due to the doping by diffused P atoms is shown in **Figure 15(ii)** and **(iii)**. **Figure 15(i)** shows that the Fermi level is pinned. As explained in Section 1.1.5 of the previous chapter, this Fermi-level pinning is caused by dipole formation due to the large amount of interface states. The diameter of a silicon atom is approximately 0.1 nm and the thickness of the silicon layer in **Figure 15(iii)** is also 0.1 nm, meaning that it was essentially a monolayer deposition of silicon which released the Fermi-level pinning and achieved an ohmic contact. The large modulation of the Schottky potential barrier height due to the insertion of a 0.1-nmthick Si monolayer is explainable by considering that the Si atoms caused the formation of chemical bonds between NiGe, Si, and *n*-Ge, thereby reducing the number of dangling bonds (valence mending) that are responsible for the dipole formation which is explained in Section 1.1.5 of the previous chapter.

**2.3. PdGe contacts**

**Figure 17**.

contacts [13].

standard deviation of 0.019 eV.

bias I-V characteristics.

Chawanda et al. [13] used *n*-type Ge(111) doped with antimony (Sb) at a density of 2.5 × 1015 cm−3. Pd was deposited onto the substrates by vacuum resistive evaporation as explained in Section 2.1.1 of the previous chapter. This was done through a mechanical mask which had circular windows of diameter, 0.6 ± 0.05 mm. In this way, 24 circular contacts were prepared in a single evaporation. The thickness of each deposited layer of Pd was 30 nm. Room temperature forward and reverse bias current-voltage characteristics were obtained for five of the Pd/*n*-Ge contacts,

Interface Control Processes for Ni/Ge and Pd/Ge Schottky and Ohmic Contact Fabrication: Part Two

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Rectifying characteristics are seen for all samples in **Figure 16**. The height of the Schottky potential barrier, Φ*Bn* and the ideality *n*-factor were extracted from the forward bias I-V characteristics of the Schottky diodes at room temperature using the thermionic emission model, as explained in Section 1.1.4 of the previous chapter. This was done for several samples and a histogram was produced to show the statistical distribution of the effective potential barrier heights from the forward bias I-V characteristics, and this is presented in

The effective potential barrier heights obtained from the I-V characteristics varied from 0.492 to 0.550 eV. A Gaussian distribution function was used to obtain fits to the histogram. The statistical analysis yielded a mean Schottky potential barrier height value of 0.529 eV with a

A histogram was also produced for the values of the ideality factors determined from the I-V characteristics. **Figure 18** shows the statistical distribution of ideality factors from the forward

**Figure 16.** Room temperature forward and reverse bias current-voltage characteristics obtained for five of the Pd/*n*-Ge

which acted as Schottky barrier diodes. The results are shown in **Figure 16**.

**Figure 15.** Schematic energy band diagrams of: (i) an NiGe/*n*-Ge interface; (ii) an NiGe/*n*-Ge interface with the incorporation of P atoms; (iii) an NiGe/*n*-Ge interface with the incorporation of P atoms and the insertion of a silicon layer.
