**3. Low-***k* **plasma damage during interconnects fabrication**

As Al/SiO2 interconnects had been transferred to Cu/low-*k* interconnects, the fabrication method was also changed. "Damascene" process has been used to fabricate Cu/low-*k* interconnects because Cu cannot be easily patterned by reactive ion etching (RIE) due to the low volatility of Cu etching by-products, such as Cu chlorides and Cu fluorides [34]. Generally, "dual-damascene" process, in which both via and trench are patterned simultaneously, is widely used. The sequence of via and trench patterning can be changed. Via-first dualdamascene process, in which via is first patterned, is preferred [35]. The process flow of viafirst dual damascene is plotted step by step, as shown in **Figure 1**.

The induced plasma damage on low-*k* dielectrics during the fabrication of Cu/low-*k* interconnects by the use of via-first dual-damascene process is described below:

bombardment. The detrimental effect on the low-*k* dielectrics is caused by photoresist process

reactor is a viable alternative. To facilitate the removal rate of photoresist, the operation tem-

Then, metallization process is preceded in the dual-damascene structure. Cu barrier layer, Cu seed layer, and bulk Cu layer are subsequently deposited. Finally, Cu chemical-mechanical polishing (CMP) process is used to remove the excess metal over the field regions. Thus, a layer of Cu dual-damascene structure (via and trench) is finished. In these steps, Cu barrier layer and seed layer are performed by PVD sputtering with using plasma. The former step would cause damage on the low-*k* dielectrics due to the direct contact with the dielectric. The purpose of this step is to prevent Cu from diffusing into the dielectric, and the typically used material is a TaN/Ta barrier layer. It should be mentioned that plasma cleaning before Cu barrier layer deposition is necessary because the underlying Cu film is opening. This plasma

After completing the Cu metallization fabrication, the above steps are repeated for each metal level. After the last metal layer is fabricated, thick dielectric passivation layer (e.g., SiO2

To characterize the plasma damage on the low-*k* dielectrics, several methodologies can be used to detect the physical and chemical changes of low-*k* dielectrics after irradiation of

low-*k* dielectric. The thickness of this layer can be measured using spectral reflectivity or ellipsometry with bilayer model, scanning electron microscope (SEM), or transition emitting microscopy (TEM). **Figure 2** displays TEM image of the porous low-*k* dielectrics after O2

X-ray reflectivity (XRR) is another method to determine the density, thickness, and roughness of both pristine and damaged low-*k* layers through software data fitting [42]. **Figure 3** shows the XRR density profile of the low-*k* film after He plasma. The result demonstrates that He plasma creates a thin densification layer in the top part of the low-*k* film. The thickness of this densification layer is close to 17 nm. The density of the bulk layer in the pristine material density is constant and remained unchanged. However, the top of the densification layer has

"HF decoration" method [44] can be used to detect the modification layer induced by plasma. This method is based on the fact that a pristine low-*k* dielectric is usually not dissolved or

To minimize the plasma damage during the photoresist process, H2

cleaning can be done either by Ar physical bombardment or H2

low-*k* dielectrics are damaged under such plasma cleaning.

bilayer) is deposited, and via is opened to the bond pads.

plasma. The plasma induces a dense, hydrophilic, SiO2

plasma treatment. A distinct layer is formed at the top surface of the film.

) is widely used as plasma gas due to high reactivity of O radicals [38, 39].


Plasma Damage on Low-*k* Dielectric Materials http://dx.doi.org/10.5772/intechopen.79494

chemical reaction. However,


/SiN

297

because oxygen (O2

perature can be elevated [40, 41].

**4. Low-***k* **plasma damage**

a higher density [43].

**4.1. Plasma damage characterization**

After processing of Metal-1 (M-1), the etching stop layer (Cu barrier dielectric layer) is firstly deposited by PECVD method. The used material can be SiN, SiC, or SiCN. Before deposition, NH3 or H2 plasma clean is performed to remove copper oxide (CuOx ) for adhesion improvement [36, 37]. Both these two steps would damage the underlying low-*k* dielectric. Then, a PECVD SiCOH low-*k* dielectric film is deposited for the Via-1 (V-1)/Metal-2 (M-2) patterning. Due to the presence of the etching stop layer, the plasma damage is seldom occurred in this step. Next, Via-1 and Metal-2 trench are subsequently patterned. Via-1 patterning is stopping on the etching layer. Then, before Metal-2 trench patterning, the plug is filled into the Via-1 to avoid etching during Metal-2 trench etching. Finally, resist removal and etching stop layer opening are subsequently performed to complete the dual-damascene patterning.

In the Via-1 and Metal-2 trench patterning, the etching process induces plasma damage not only on the horizontal surfaces but also on the vertical surfaces (sidewall).

The damaged layer on the horizontal surfaces can be removed as the etching proceeds. Therefore, the resulted damage on the low-*k* dielectric is the result of a competition between the etching rate and the diffusion rate of active species causing the damage. The non-damaging process can be achieved by using higher etching rate process. However, for vertical surfaces, the damage is still remained after etch. The damage is more minor due to the absence of ion

**Figure 1.** Via-first dual-damascene process flow for Cu/low-*k* interconnects. (A) Etching stopping layer deposition (SiN, SiC, SiCN, SiCOH, SiO2 ). (B) Low-*k* dielectric (SiCOH) deposition. (C) Via-1 lithography. (D) Via-1 etching. (E) Photoresist ashing or stripping. (F) Via-1 ARC plug and M-2 trench lithography. (G) M-2 trench etching. (H) ARC plug removal, photoresist ashing, and stripping etching stop layer opening. (I) Cu metal barrier and seed layer deposition. (J) Cu ECP deposition. (K) Cu CMP. (L) Etching stopping layer deposition (repeated (A)).

bombardment. The detrimental effect on the low-*k* dielectrics is caused by photoresist process because oxygen (O2 ) is widely used as plasma gas due to high reactivity of O radicals [38, 39]. To minimize the plasma damage during the photoresist process, H2 -based plasma in the RP reactor is a viable alternative. To facilitate the removal rate of photoresist, the operation temperature can be elevated [40, 41].

Then, metallization process is preceded in the dual-damascene structure. Cu barrier layer, Cu seed layer, and bulk Cu layer are subsequently deposited. Finally, Cu chemical-mechanical polishing (CMP) process is used to remove the excess metal over the field regions. Thus, a layer of Cu dual-damascene structure (via and trench) is finished. In these steps, Cu barrier layer and seed layer are performed by PVD sputtering with using plasma. The former step would cause damage on the low-*k* dielectrics due to the direct contact with the dielectric. The purpose of this step is to prevent Cu from diffusing into the dielectric, and the typically used material is a TaN/Ta barrier layer. It should be mentioned that plasma cleaning before Cu barrier layer deposition is necessary because the underlying Cu film is opening. This plasma cleaning can be done either by Ar physical bombardment or H2 chemical reaction. However, low-*k* dielectrics are damaged under such plasma cleaning.

After completing the Cu metallization fabrication, the above steps are repeated for each metal level. After the last metal layer is fabricated, thick dielectric passivation layer (e.g., SiO2 /SiN bilayer) is deposited, and via is opened to the bond pads.
