**1. Introduction**

To improve the performance of integrated circuits (ICs), the device dimensions are continuous scaling down. However, as the technology node of ICs is advanced to 0.25 μm, the interconnect-induced delay outpaces the gate delay, becoming the main obstacles for the downscaling [1–3]. This interconnect-induced delay is so-called resistance-capacitance (*RC*) delay, which is produced by the conductors and insulators in the interconnects [4–6]. With decreasing the device dimensions, both the resistance and the interline capacitance increase due to the decrease of the conductor cross section, the increase of the wire length, and the reduction of interline spacing. Hence, the *RC* delay is significantly increased with the advance of the technology node.

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

In order to slow down the increase of *RC* delay, the introduction of new materials to the back-end-of-line (BEOL) interconnects is needed. Aluminum (Al) had been replaced by copper (Cu) as a conductor dielectric because Cu can provide a lower resistivity (ρ) [7]. In the case of the interconnecting insulator, the traditional SiO2 dielectric had been replaced by the low-*k* materials with the relative dielectric constant (*k*) lower than 4.0 (SiO2 *k* value) [8–10].

Additionally, the integration method for Cu/low-*k* interconnects must be changed because Cu etching is very challenging due to nonvolatile by-products. Traditional metal etching approach had been replaced by a damascene process [11]. In a damascene process, plasma technology is widely used because it can provide an isotropic process and a fast rate. Thus, these changes make the low-*k* materials to direct contact with the plasma, such as dielectric etching, photo strip, barrier metal deposition, and surface treatment. Under the plasma irradiation, low-*k* materials are sensitive to chemical modification, resulting in an increased *k* value. This is so-called plasma damage [12–15], becoming the main impediment to a successful integration of low-*k* materials into ICs.

In this connection, this chapter is an attempt to provide an overview of plasma damage on the low-*k* materials. This chapter is organized as follows: in Section 3, we introduce the low-*k* materials and plasma. Next, in Section 5, the processing with plasma damage on the low-*k* materials during interconnects fabrication is identified. Then, in Section 4, the results of plasma damage on the low-*k* materials based on our group's investigation are summarized. Finally, short conclusion is provided in Section 5.
