5. Hardware-in-the-loop test results

Figure 8. The peak active power ∣P2∣ (in p.u.) to a 120 A in the DC cable current i<sup>L</sup> obtained at nominal grid voltage for

VC 3:83E-02 4:44E-03 2:13E-02 2:71E-02 FLSMC 2:19E-02 1:73E-03 2:23E-02 2:18E-02 POSMC 2:33E-02 2:00E-03 2:42E-02 2:33E-02

VC 2:62E-02 2:15E-03 4:53E-03 4:13E-03 FLSMC 1:13E-02 4:13E-03 4:08E-03 3:33E-03 POSMC 5:64E-03 1:38E-03 3:88E-04 6:78E-04

Method Five-cycle LLLG fault Weak AC grid connection

Table 3. IAE indices (in p.u.) of different control schemes calculated in different cases.

Figure 9. Overall control costs IAE<sup>u</sup> (in p.u.) obtained in different cases.

IAEQ1 IAEVdc1 IAEQ2 IAEP2

IAEQ1 IAEVdc1 IAEQ1 IAEVdc1

plant-model mismatches in the range of 20% (different parameters may change at the same time).

Method Power tracking

38 Perturbation Methods with Applications in Science and Engineering

Case

Case

HIL test is an important and powerful technique used in the development and test of complex real-time embedded systems, which provides an effective platform by adding the complexity of the plant under control to the test platform. The complexity of the plant under control is included in test and development by adding a mathematical representation of all related dynamic systems.

A dSPACE simulator-based HIL test is used to validate the implementation feasibility of POSMC, which configuration and experiment platform are given by Figures 10 and 11, respectively. The rectifier controller (34) and inverter controller (41) are implemented on one dSPACE platform (DS1104 board) with a sampling frequency f <sup>c</sup> ¼ 1 kHz, and the VSC-HVDC system is simulated on another dSPACE platform (DS1006 board) with the limit sampling frequency

Figure 10. The configuration of the HIL test.

Figure 11. The experiment platform of the HIL test.

f <sup>s</sup> ¼ 50 kHz to make HIL simulator as close to the real plant as possible. The measurements of the reactive power Q1, DC voltage Vdc1, active power P2, and reactive power Q<sup>2</sup> are obtained from the real-time simulation of the VSC-HVDC system on the DS1006 board, which are sent to two controllers implemented on the DS1104 board for the control inputs calculation.

It follows from [37] that an unexpected high-frequency oscillation in control inputs may emerge as the large observer poles would result in high gains, which lead to highly sensitive observer dynamics to the measurement disturbances in the HIL test. Note that this phenomenon does not exist in the simulation. One effective way to alleviate such malignant effect is to reduce the observer poles. Through trial-and-error, an observer pole in the range of λα<sup>r</sup> ∈ ½ � 15; 25 and λα<sup>0</sup> <sup>r</sup> ¼ λα<sup>i</sup> ¼ λα<sup>0</sup> i ∈½ � 3; 10 can avoid such oscillation but with almost similar transient responses, thus the reduced poles λα<sup>r</sup> ¼ 20 and λα<sup>0</sup> <sup>r</sup> ¼ λα<sup>i</sup> ¼ λα<sup>0</sup> <sup>i</sup> ¼ 5, with br10 ¼ 50, br20 ¼ 5000, bi10 ¼ 20, and bi20 ¼ 20, are chosen in the HIL test. Furthermore, a time delay τ ¼ 3 ms has been assumed in the corresponding simulation to consider the effect of the computational delay of the real-time controller.

(1) Case 1: Active and reactive power tracking: The reference of active and reactive power changes at t ¼ 0:4 s, t ¼ 0:9 s and restores to the original value at t ¼ 1:4 s, while DC voltage is regulated at the rated value V<sup>∗</sup> dc1 ¼ 150 kV. The system responses obtained under the HIL test and simulation are compared by Figure 12, which shows that the HIL test has almost the same results as that of the simulation.

(2) Case 2: 5-cycle line-line-line-ground (LLLG) fault at AC bus 1. A 5-cycle LLLG fault occurs at AC bus 1 when t ¼ 0:1 s. Figure 13 demonstrates that the system can be rapidly restored and

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the system responses obtained by the HIL test is similar to that of simulation.

Figure 12. HIL test results of system responses obtained under the active and reactive power tracking.

Sliding-Mode Perturbation Observer-Based Sliding-Mode Control for VSC-HVDC Systems http://dx.doi.org/10.5772/intechopen.74717 41

Figure 12. HIL test results of system responses obtained under the active and reactive power tracking.

f <sup>s</sup> ¼ 50 kHz to make HIL simulator as close to the real plant as possible. The measurements of the reactive power Q1, DC voltage Vdc1, active power P2, and reactive power Q<sup>2</sup> are obtained from the real-time simulation of the VSC-HVDC system on the DS1006 board, which are sent to two controllers implemented on the DS1104 board for the control inputs calculation.

It follows from [37] that an unexpected high-frequency oscillation in control inputs may emerge as the large observer poles would result in high gains, which lead to highly sensitive observer dynamics to the measurement disturbances in the HIL test. Note that this phenomenon does not exist in the simulation. One effective way to alleviate such malignant effect is to reduce the observer poles. Through trial-and-error, an observer pole in the range of

br20 ¼ 5000, bi10 ¼ 20, and bi20 ¼ 20, are chosen in the HIL test. Furthermore, a time delay τ ¼ 3 ms has been assumed in the corresponding simulation to consider the effect of the computa-

(1) Case 1: Active and reactive power tracking: The reference of active and reactive power changes at t ¼ 0:4 s, t ¼ 0:9 s and restores to the original value at t ¼ 1:4 s, while DC voltage is

and simulation are compared by Figure 12, which shows that the HIL test has almost the same

∈½ � 3; 10 can avoid such oscillation but with almost similar

dc1 ¼ 150 kV. The system responses obtained under the HIL test

<sup>r</sup> ¼ λα<sup>i</sup> ¼ λα<sup>0</sup>

<sup>i</sup> ¼ 5, with br10 ¼ 50,

λα<sup>r</sup> ∈ ½ � 15; 25 and λα<sup>0</sup>

<sup>r</sup> ¼ λα<sup>i</sup> ¼ λα<sup>0</sup>

tional delay of the real-time controller.

Figure 11. The experiment platform of the HIL test.

40 Perturbation Methods with Applications in Science and Engineering

regulated at the rated value V<sup>∗</sup>

results as that of the simulation.

i

transient responses, thus the reduced poles λα<sup>r</sup> ¼ 20 and λα<sup>0</sup>

(2) Case 2: 5-cycle line-line-line-ground (LLLG) fault at AC bus 1. A 5-cycle LLLG fault occurs at AC bus 1 when t ¼ 0:1 s. Figure 13 demonstrates that the system can be rapidly restored and the system responses obtained by the HIL test is similar to that of simulation.

Figure 13. HIL test results of system responses obtained under the five-cycle LLLG fault at AC bus 1.

(3) Case 3: Weak AC grid connection: The same voltage variation us1 ¼ 1 þ 0:15 sin 0ð Þ :2πt is applied between 0.87 and 2.45 s. It can be readily seen from Figure 14 that the results of the HIL test and simulation match very well.

The difference of the obtained results between the HIL test and simulation is possibly due to

Sliding-Mode Perturbation Observer-Based Sliding-Mode Control for VSC-HVDC Systems

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• There exist measurement disturbances in the HIL test, which are, however, not taken into account in the simulation, a filter could be used to remove the measurement disturbances,

the following two reasons:

thus the control performance can be improved.

Figure 14. HIL test results of system responses obtained with the weak AC grid connection.

Sliding-Mode Perturbation Observer-Based Sliding-Mode Control for VSC-HVDC Systems http://dx.doi.org/10.5772/intechopen.74717 43

Figure 14. HIL test results of system responses obtained with the weak AC grid connection.

(3) Case 3: Weak AC grid connection: The same voltage variation us1 ¼ 1 þ 0:15 sin 0ð Þ :2πt is applied between 0.87 and 2.45 s. It can be readily seen from Figure 14 that the results of the

Figure 13. HIL test results of system responses obtained under the five-cycle LLLG fault at AC bus 1.

HIL test and simulation match very well.

42 Perturbation Methods with Applications in Science and Engineering

The difference of the obtained results between the HIL test and simulation is possibly due to the following two reasons:

• There exist measurement disturbances in the HIL test, which are, however, not taken into account in the simulation, a filter could be used to remove the measurement disturbances, thus the control performance can be improved.

• The sampling frequency of VSC-HVDC model and POSMC is the same in simulation (f <sup>s</sup> ¼ f <sup>c</sup> ¼ 1 kHz) as they are implemented in Matlab of the same computer. In contrast, the sampling frequency of VSC-HVDC model (f <sup>s</sup> ¼ 50 kHz) is significantly increased in the HIL test to make VSC-HVDC model as close to the real plant as possible. Note the sampling frequency of POSMC remains the same (f <sup>c</sup> ¼ 1 kHz) due to the sampling limit of the practical controller.

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