5. Concluding remarks

shown in Figure 13, up to four (the number of memory modules) memory accesses can be performed concurrently, but if two (or more) processors request access to the same memory

Petri net model of a system outlined in Figure 13 is shown in Figure 14 where only two

In Figure 14, there is a free-choice place Pri for each processor i, i ¼ 1, …, n. This free-choice place selects the requested memory module by transitions Tij, j ¼ 1, …, 4, and forwards the memory access request to the selected memory module (place Pij). If the selected module is available, i.e., if place Busj is marked, the access to shared memory is initiated by the occurrence of Taij. When this memory access is completed, the occurrence of Teij releases the memory modules (by returning a token to Busj) and resumes instruction execution in the

If memory module is not available when it is requested, the memory access is delayed (in Pij)

It is possible that more than one processor becomes waiting for the same memory module. The selection of the processor which will get access first is random with the same probability assigned to all waiting processors. In real systems, there is usually some priority scheme that determines the order in which the waiting processors access the bus. Such a priority scheme could easily be modeled if it is needed (for example, for studying the starvation effect which

In Figure 14, the selection of memory modules is random, with the same probabilities for all modules. If this policy is not realistic, a different memory accessing policy can be implemented,

Figure 15. Processor and bus utilization as functions of the number of processors—system with four memory modules

module, the requests are served one after another.

88 Petri Nets in Science and Engineering

processors and two memory modules are detailed.

processor that requested the memory access.

until the requested module becomes available.

can be created when the system is overloaded).

and h<sup>1</sup> ¼ 0:9, h<sup>2</sup> ¼ 0:8, ps ¼ 0:2.

The chapter uses timed Petri nets to model shared-memory bus-based architectures at the level of instruction execution to study the effects of modeling parameters on the performance of the system. The models are rather simple with straightforward representation of modeling parameters.

Performance results presented in this chapter have been obtained by the simulation of developed Petri net models. However, the model shown in Figure 7 has only 10 states, so its analytical solution (for different values of modeling parameters) can be easily obtained and compared with simulation results to verify their accuracy. Table 2 shows such a comparison of processor utilization for several combinations of parameters h<sup>1</sup> and h2. In all cases, the simulation-based results are very close to the analytical ones.

The models of multiprocessor systems are usually composed of many copies of the same submodel of a processor and possibly other elements of the system. Colored Petri nets [17] can significantly simplify such models by eliminating copies of similar subsystems. Analysis of colored Petri nets is, however, much more complex than that of ordinary Petri nets.

Finally, it should be noted that the performance of real-life multiprocessor systems very rarely can be described by a set of parameters that remain stable for any significant period of time. The basic parameters like the hit rates depend upon the executed programs as well as their data, and can change very quickly in a significant way. Consequently, the characteristics presented in this chapter can only be used as some insight into the complex behavior of multiprocessor systems.


Table 2. A comparison of simulation and analytical results.
