2. Control lines in LD to discrete event systems

The LD language has as its operating principle the behavior of an electromechanical relay, with the option of including function blocks. The standards IEC-61131-3 define LD like "modeling networks of simultaneous functioning electromechanical elements, such as relay contacts and coils, timers, counters, etc." The control lines analyzed are the logic AND, OR, AND–OR, auto-loop, interlocking, timers, counters and mathematic comparisons. The first five logical have discrete inputs and output. Meanwhile in the logical of timers, counters and mathematical comparisons have analog inputs and discrete outputs.

The run of control algorithm in PLC is cyclic, and it mainly performs five actions such as reading of physical inputs, copy status of physical inputs, evaluation of the control algorithm with previous copy, copy of the status of physical outputs and sending of these statuses to physical modules.

#### 2.1. Control lines both discrete inputs and outputs

outputs. The logic blocks such as timer, counter and comparator have all analog inputs, but

The main motive or need to model the control algorithms in LD is because they are developed mainly based on the experience of programmers in industrial control [2, 3], so it is important to propose approaches that help guarantee the safe control algorithms applied in machines or industrial processes, and the theory of PN [4] allows modeling the basic control lines used in the LD algorithms. Different approaches have been presented to provide a solution to analyze, model and simulate control algorithms developed in LD with PN or vice

Physical or discrete memory signals can have two states (activated or deactivated, 0 or 1, etc.), so, we propose a distribution of these signals to PN structure that can model both states, but only one active at a time. On the other hand, the cyclic operation of PLC generates cyclic evaluation of the control algorithm in function of the states of physical input and memory signals. This behavior must be considered to avoid accumulation of tokens in places of PN structures, for which reason marking conditions are proposed in places that represent physical or memory outputs of PN structures of control lines in LD. Likewise, cyclic evaluation of control lines generates the energized and de-energized behavior of coils; therefore, it is also necessary to restore conditions of PN structures of each control line in LD, conditioning the

To convert control lines with analog inputs, places where their marking is a data (color in colored Petri nets) are included [9], which may be changing depending on the logic control algorithm. Conditioned transitions are proposed for their firing depending on the behavior of

Based on analysis of the control lines, we propose the definition of a PN for discrete event

The LD language has as its operating principle the behavior of an electromechanical relay, with the option of including function blocks. The standards IEC-61131-3 define LD like "modeling networks of simultaneous functioning electromechanical elements, such as relay contacts and coils, timers, counters, etc." The control lines analyzed are the logic AND, OR, AND–OR, auto-loop, interlocking, timers, counters and mathematic comparisons. The first five logical have discrete inputs and output. Meanwhile in the logical of timers, counters and mathematical compari-

The run of control algorithm in PLC is cyclic, and it mainly performs five actions such as reading of physical inputs, copy status of physical inputs, evaluation of the control algorithm with previous copy, copy of the status of physical outputs and sending of these statuses to

systems in LD (LDPN), with which PN structures of control lines in LD are generated.

their control output is discrete.

18 Petri Nets in Science and Engineering

marking in function of the input places [12, 13].

2. Control lines in LD to discrete event systems

sons have analog inputs and discrete outputs.

physical modules.

the control block in respective LD.

versa [5–11].

Figure 1 shows the control line of logic AND, when all contacts In\_1, In\_2, …, In\_n allow electric power flow, then Out1 coil is energized. Eq. (1) is the model corresponding.

$$\text{Out1} = \text{In\\_1} \& \& \text{In\\_2} \& \& \dots \text{In\\_n} \tag{1}$$

Figure 2 shows the control line of logic OR, when any contact In\_1, In\_2, …, In\_n allows electric power flow, then Out1 coil is energized, its model is stand for the Eq. (2).

$$\text{Out1} = \text{In\\_1} \parallel \text{In\\_2} \parallel ... \text{In\\_n} \tag{2}$$

Figure 3 shows the control line of logic AND–OR. When the contacts In\_1, In\_2, …, In\_n or the contacts In\_1, In\_3, …, In\_n allow electric power flow, then Out1 coil is energized. Eq. (3) is the model corresponding.

$$\text{Out1} = (\text{In\\_1\&\&\&\In\\_2\&\&\dots\text{In\\_n}}) \parallel (\text{In\\_1\&\&\In\\_3\&\&\dots\text{In\\_n})\tag{3}$$

Figure 4 shows the control line of logic auto-loop. When the contacts In\_1, In\_2, …, In\_n or the contacts Out1, In\_2, …, In\_n allow electric power flow, then Out1 coil is energized. Eq. (4) is the model corresponding.

Figure 1. Control line of logic AND.

Figure 2. Control line of logic OR.

Figure 3. Control line of logic AND–OR.

Figure 4. Control line of logic auto-loop.

Figure 5. Control line of logic interlocking.

$$\text{Out1} = (\text{In\\_1\&\&\&\\_2\&\&\&\\_n}) \parallel (\text{Out1} \&\&\&\text{In\\_2\&\&\&\dots}) \tag{4}$$

Figure 5 shows the control line of logic interlocking, when the contacts In\_1, ~Out2, …, In\_n allow electric power flow, then Out1 coil is energized, and it blocks the energizing of Out2 coil. If Out2 coil is energized first, then Out1 coil cannot be energized. Eq. (5) is the model corresponding.

$$\text{Out1} = \text{In\\_1} \& \& \text{Out2} \& \& \dots \text{ In\\_n}; \text{Out2} = \text{In\\_2} \& \& \text{Out1} \& \& \dots \text{ In\\_m} \tag{5}$$

#### 2.2. Control lines with analog inputs and discrete output

Figure 6 shows the standard function block of on-delay timer (TON) and its timing diagram of the functional [1]. The signals Preset\_time and Elapsed\_time are analog. If the contact In\_1 allows electric energy flow, when Elapsed\_time adds base time and if Elapsed\_time is equal or greater than Preset\_time, then Out1 coil is energized. Eq. (6) depicts the logic model of the block TON.

$$\text{If } (\text{In}\\_1 = 1 \ \& \ \& \text{ET} \ge \text{PT}), \text{ then } \text{Out1} = 1 \tag{6}$$

Figure 8 shows two counter function blocks: (1) up-counter and (2) down-counter. In both blocks, the contact In\_1 is the pulse to counter, that is and positive transition is detected; if the contact In\_2 allows electric energy flow, then Out1 coil is de-energized, and the Current\_value variable is set to zero in up-counter and to Preset\_value in down-counter. In up-counter, if Current\_value is equal or greater than Preset\_value, then Out1 coil is energized. In down counter, if Current\_value is equal to zero, then Out1 coil is energized. Eqs. (8) and (9) are logic

if In\_1 ð Þ↑ ,then CV ¼ CV þ 1; if In ð Þ \_2 ¼ 0&& CV ≥ PV , then Out1 ¼ 1 (8)

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 21

if In\_1 ð Þ↑ , then CV ¼ CV � 1; if In ð Þ \_2 ¼ 0&& CV ≤ 0 , then Out1 ¼ 1 (9)

models of the counters, respectively.

Figure 6. On-delay timer.

Figure 7. Off-delay timer.

Restart condition: If In\_2 ¼ 1, then CV ¼ 0

Restart condition: If In\_2 ¼ 1, then CV ¼ PV:

Restart condition: If In\_1 ¼ 0, then ET ¼ 0 and Out1 = 0.

Figure 7 shows the standard function block of off-delay timer (TOF) and its timing diagram of the functional [1]. If the contact In\_1 allows energy power, then the Out1 coil is energized, and the Elapsed\_time variable is set to zero. When the In\_1 signal is equal to zero, the Elapsed\_time variable adds base time and if Elapsed\_time is equal or greater than Present\_time, then Out1 coil is de-energized. Eq. (7) shows the logic model of block TOF.

$$\text{If } (\text{In}\_1 = 0 \& \& \text{ET} \le \text{PT}) \text{, then } \text{Out1} = 0 \tag{7}$$

Restart condition: If In\_1 ¼ 1, then ET ¼ 0 and Out1 = 1.

Figure 7. Off-delay timer.

Out1 ¼ ðIn\_1&&In\_2&&In\_nÞ k ð Þ Out1&&In\_2&&In\_n (4)

Out1 ¼ In\_1&&Out2 & &… In\_n; Out2 ¼ In\_2&&Out1 & &… In\_m (5)

If In ð Þ \_1 ¼ 1 & &ET ≥ PT , then Out1 ¼ 1 (6)

If In ð Þ \_1 ¼ 0 & &ET ≤ PT , then Out1 ¼ 0 (7)

Figure 5 shows the control line of logic interlocking, when the contacts In\_1, ~Out2, …, In\_n allow electric power flow, then Out1 coil is energized, and it blocks the energizing of Out2 coil. If Out2 coil is energized first, then Out1 coil cannot be energized. Eq. (5) is the model

Figure 6 shows the standard function block of on-delay timer (TON) and its timing diagram of the functional [1]. The signals Preset\_time and Elapsed\_time are analog. If the contact In\_1 allows electric energy flow, when Elapsed\_time adds base time and if Elapsed\_time is equal or greater than Preset\_time, then Out1 coil is energized. Eq. (6) depicts the logic model of the block

Figure 7 shows the standard function block of off-delay timer (TOF) and its timing diagram of the functional [1]. If the contact In\_1 allows energy power, then the Out1 coil is energized, and the Elapsed\_time variable is set to zero. When the In\_1 signal is equal to zero, the Elapsed\_time variable adds base time and if Elapsed\_time is equal or greater than Present\_time, then Out1 coil

2.2. Control lines with analog inputs and discrete output

Restart condition: If In\_1 ¼ 0, then ET ¼ 0 and Out1 = 0.

is de-energized. Eq. (7) shows the logic model of block TOF.

Restart condition: If In\_1 ¼ 1, then ET ¼ 0 and Out1 = 1.

corresponding.

Figure 4. Control line of logic auto-loop.

20 Petri Nets in Science and Engineering

Figure 5. Control line of logic interlocking.

TON.

Figure 8 shows two counter function blocks: (1) up-counter and (2) down-counter. In both blocks, the contact In\_1 is the pulse to counter, that is and positive transition is detected; if the contact In\_2 allows electric energy flow, then Out1 coil is de-energized, and the Current\_value variable is set to zero in up-counter and to Preset\_value in down-counter. In up-counter, if Current\_value is equal or greater than Preset\_value, then Out1 coil is energized. In down counter, if Current\_value is equal to zero, then Out1 coil is energized. Eqs. (8) and (9) are logic models of the counters, respectively.

$$\text{if } \text{In\\_1}(\dagger) \text{, then } \text{CV}=\text{CV}+1;\\ \text{if } (\text{In\\_2}=0 \text{ \& } \text{CV}\ge \text{PV}), \text{ then } \text{Out1}=1\tag{8}$$

Restart condition: If In\_2 ¼ 1, then CV ¼ 0

$$\text{if } \text{In } \underline{1} \text{ (}\dagger\text{), then } \text{CV} = \text{CV} - 1;\\ \text{if } (\text{In } \underline{2} = 0 \text{ } \&\text{ } \text{CV} \le 0), \text{then } \text{Out1} = 1 \tag{9}$$

Restart condition: If In\_2 ¼ 1, then CV ¼ PV:

Figure 8. Counters. a) Counter up, b) Counter down.

Figure 9. Mathematical comparisons. a) Relation, equal to, b) Relation, lower than, c) Relation, greater than.

Figure 9 shows the standard comparison function blocks: a) equal to, b) lower than and c) greater than. In all the blocks, two analog signals are compared, and depending on result is energized or de-energized Out1 coil. The logic models, respectively, are specified in Eqs. (10–12).

If Value\_1 ¼ Value\_2, then Out1 ¼ 1 (10)

Likewise, the conditions for marking places and triggering transitions are described to model

PN are a graphic and mathematic tool mean to modeling DES behavior. Graphically, a PN uses circles in order to represent places, rectangles to represent transitions and arcs with arrow or circle to link the inputs and output places with a transition. The relation between places and transition can be represented mathematically by means of an incidence matrix. For a PN with <sup>n</sup> transitions and <sup>m</sup> places, its incidence matrix <sup>A</sup> <sup>¼</sup> aij is an integer number matrix

aij ¼ a<sup>þ</sup>

To model the dynamic behavior of DES, PN has the state equation, which shows the marking in the net sequentially from initial marking Mk�<sup>1</sup> and when applying a firing vector uk to the transpose of the respective incidence matrix A<sup>T</sup>, respectively. Eq. (14) shows the relationship

In an LD control algorithm, a discrete signal can have n contacts normally open and m contacts normally closed. The work in [12] shows a representation of discrete signals used in LD to PN,

ij � a�

ij represents the weighting of output

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 23

ij (13)

ij represents input arcs to transitions. Eq. (13) represents how the

Mk <sup>¼</sup> Mk�<sup>1</sup> <sup>þ</sup> <sup>A</sup>Tuk (14)

the cyclical evaluation behavior of the control algorithm in PLC.

representing the weighting of the input and output arcs; a<sup>þ</sup>

3.1. Petri nets

between them.

arcs from transitions and a�

incidence matrix values are obtained.

Figure 10. Distribution of discrete signals in PN.

3.2. LDPN: Discrete event systems

If Value\_1 < Value\_2, then Out1 ¼ 1 (11)

$$\text{If } \text{Value\\_1} > \text{Value\\_2} \text{ then } \text{Out1} = 1 \tag{12}$$

#### 3. Model of control lines in PN

In this section, the bases of the PN theory are indicated, and the discrete-LDPN network, which is the basis for generating the PN structures of the control lines in LD, is defined.

Figure 10. Distribution of discrete signals in PN.

Likewise, the conditions for marking places and triggering transitions are described to model the cyclical evaluation behavior of the control algorithm in PLC.

#### 3.1. Petri nets

Figure 9 shows the standard comparison function blocks: a) equal to, b) lower than and c) greater than. In all the blocks, two analog signals are compared, and depending on result is energized or

In this section, the bases of the PN theory are indicated, and the discrete-LDPN network, which is the basis for generating the PN structures of the control lines in LD, is defined.

If Value\_1 ¼ Value\_2, then Out1 ¼ 1 (10)

If Value\_1 < Value\_2, then Out1 ¼ 1 (11)

If Value\_1 > Value\_2, then Out1 ¼ 1 (12)

de-energized Out1 coil. The logic models, respectively, are specified in Eqs. (10–12).

Figure 9. Mathematical comparisons. a) Relation, equal to, b) Relation, lower than, c) Relation, greater than.

3. Model of control lines in PN

Figure 8. Counters. a) Counter up, b) Counter down.

22 Petri Nets in Science and Engineering

PN are a graphic and mathematic tool mean to modeling DES behavior. Graphically, a PN uses circles in order to represent places, rectangles to represent transitions and arcs with arrow or circle to link the inputs and output places with a transition. The relation between places and transition can be represented mathematically by means of an incidence matrix. For a PN with <sup>n</sup> transitions and <sup>m</sup> places, its incidence matrix <sup>A</sup> <sup>¼</sup> aij is an integer number matrix representing the weighting of the input and output arcs; a<sup>þ</sup> ij represents the weighting of output arcs from transitions and a� ij represents input arcs to transitions. Eq. (13) represents how the incidence matrix values are obtained.

$$a\_{i\circ} = a\_{i\circ}^+ - a\_{i\circ}^- \tag{13}$$

To model the dynamic behavior of DES, PN has the state equation, which shows the marking in the net sequentially from initial marking Mk�<sup>1</sup> and when applying a firing vector uk to the transpose of the respective incidence matrix A<sup>T</sup>, respectively. Eq. (14) shows the relationship between them.

$$M\_k = M\_{k-1} + A^T \mu\_k \tag{14}$$

#### 3.2. LDPN: Discrete event systems

In an LD control algorithm, a discrete signal can have n contacts normally open and m contacts normally closed. The work in [12] shows a representation of discrete signals used in LD to PN, which is the base of conversion of control lines that have both discrete inputs and outputs. On the other hand, evaluation of control algorithm in PLC is cyclical, which generates two important conditions to consider in the PN model; the cyclical evaluation in PN would generate accumulation of marks in the places, and in function of the logic, marking and consuming of theses in places that represent coils in the LD. This last condition is also necessary to restore the information of places in PN that represent physical analog signals or memory registers. Figure 10 shows the distribution of discrete signals in PN, and Eq. (15) its interpretation. Only one transition can be enabled at a time; if the input place does not have a mark, then the transition ð Þ <sup>I</sup>; <sup>O</sup>; <sup>B</sup> <sup>c</sup> is enabled for inhibitor arc. Eq. (16) is the generalization of the marking of <sup>I</sup>, O y B places.

$$I\_i = \left\{ I\_n^o \cup I\_m^c \right\} ; O\_o = \left\{ O\_n^o \cup O\_m^c \right\} ; B\_b = \left\{ B\_n^o \cup B\_m^c \right\} \tag{15}$$

LDPN considers the following transition rules to dynamic behavior:

condition of data.

output place T of P.

• To update, marking should be applied Eqs. 16–20.

A Discrete-LDPN is a 5-tuple (P, T, W, F, M0), where: P ¼ f g I ∪ O ∪ B ∪ AI ∪ AR ∪ RC is a finite set of places, where:

of inputs and outputs of control line type.

<sup>2</sup> ; …; <sup>O</sup><sup>c</sup>∣<sup>o</sup> o

function of mathematics or logics restrictions.

W ¼ F ! f g1 , all weights of the arcs are equal to 1.

P ! f g Z 16 bit integer ð Þ , analog signal:

Table 1. Definition of LDPN: Discrete event systems.

<sup>2</sup> ; …; <sup>B</sup><sup>c</sup>∣<sup>o</sup> b

F⊆ð Þ P � T ∪ð Þ T � P is a set of arcs.

<sup>M</sup><sup>0</sup> <sup>¼</sup> <sup>P</sup> ! f g <sup>0</sup>; <sup>1</sup> , discrete signal:

T ¼ I

<sup>O</sup><sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>O</sup><sup>c</sup>∣<sup>o</sup>

<sup>B</sup><sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>B</sup><sup>c</sup>∣<sup>o</sup>

�

<sup>1</sup> ; <sup>O</sup><sup>c</sup>∣<sup>o</sup>

<sup>1</sup> ; <sup>B</sup><sup>c</sup>∣<sup>o</sup>

I <sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>I</sup> c∣o <sup>1</sup> ;I c∣o <sup>2</sup> ; …;I c∣o i

3.3. Model of control lines both discrete inputs and outputs

Figure 11 shows the PN model of logic AND, if input places I

I ¼ f g I1; I2;…; Ii is a finite set of places that represent discrete physical inputs, O ¼ f g O1; O2;…; Oo is a finite set of places that represent discrete physical outputs, B ¼ f g B1; B2; …; Bb is a finite set of places that represent discrete memory signals, AI ¼ f g AI1; AI2; …; AIai is a finite set of places that represent analog physical inputs, AR ¼ f g AR1; ARI2; …; ARar is a finite set of places that represent analog memory signals,

<sup>c</sup>∣<sup>o</sup>; ; O<sup>c</sup>∣<sup>o</sup>; ; B<sup>c</sup>∣<sup>o</sup>; L; AI; RC � � is a finite set of transitions, where:

n o is a finite set of transitions that have discrete physical inputs,

n o is a finite set of transitions that have discrete physical outputs,

n o is a finite set of transitions that have discrete memory signals,

L ¼ f g L1; L2; …; L<sup>l</sup> is a finite set of transitions that may have places of discrete signals,

• In initial conditions of LDPN, inhibitor arcs enable transitions and put token in its output places O and/or B in PN model with both inputs and outputs discrete. In AI places restart

• All transitions enabled should be fired in one some evaluation. To PN model with both inputs and outputs discrete, transition fired T consume unique token Wð Þ¼ P; T 1 of each input place P of Tand put to unique token Wð Þ¼ T; P 1 to each output place Tof P. For PN model with some analog input place and output place discrete, the transition T should be fired when it satisfies the respective condition (if - then) and put to unique token in each

transition is enabled. The L1 firing puts a token at place O1. When are updates the marking of input places, the Eq. (17) disables the L1 transition, avoiding a token more in output place O1.

RC ¼ f g RC1;RC2; …; RCrc is a finite set of places to restart condition of the nets and its marking it in function of the states

AI ¼ f g AI1; AI2; …; AIai is a finite set of transitions that can have discrete and/or analog signals, its fire condition it in

RC ¼ f g RC1; RC2; …; RCrc is a finite set of transitions that have input place RC to restart condition of PN structure.

o 1, O<sup>c</sup> <sup>3</sup> y B<sup>o</sup>

<sup>2</sup> have a token, then L1

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 25

• All output places (O and B) of the PN model are binary, only one can token.

where the subscripts n and m are not necessarily equal.

$$M(I,O,B) = \begin{bmatrix} 0 \\ 1 \end{bmatrix}, \text{then } \begin{cases} M(I,O,B)^{\circ} = 0 \text{ and } M(I,O,B)^{\circ} = 1 \\ M(I,O,B)^{\circ} = 1 \text{ and } M(I,O,B)^{\circ} = 0 \end{cases} \tag{16}$$

Considering symbols of [3], for a pre-set and post-set of places, are defined:


For tokens accumulation problem in input places, the Eqs. (17) and (18) are proposed. Both equations are is in function of the marking of inputs places and of output place. Eq. (17) is for structures with logic AND, and Eq. (18) for logic OR.

$$(O,B)(t\*) = \left\{\prod M(\*t) = 1 \text{ \& } (O,B)(t\*) = 0\right\} \tag{17}$$

$$(O,B)(t\*) = \left\{\sum M(\*t) = 1 \& \& (O,B)(t\*) = 0\right\} \tag{18}$$

In the same way, to consume token in output place and restoring conditions of PN structures, Eqs. (19) and (20) are defined, which are in function of both marking input places and output places.

$$RC(t\*) = \left\{ \prod M(\*t) = 0 \text{ \& } \& (O,B)(t\*) = 1 \right\} \tag{19}$$

$$RC(t\*) = \left\{ \sum M(\*t) = 0 \text{ \& } \& (O,B)(t\*) = 1 \right\} \tag{20}$$

From the above, the ladder diagram Petri net: discrete event systems is defined as it is shown in Table 1.

Eq. 16 to distribution of signals, Eqs. 17 and 18 to accumulate tokens and Eqs. 19 and 20 to restart conditions should be evaluated after each marking of the net Mkþ<sup>1</sup> to update the marking of LDPN and simulate cycled behavior of PLC. Marking of input places I is in function of discrete sensors states.

LDPN considers the following transition rules to dynamic behavior:

which is the base of conversion of control lines that have both discrete inputs and outputs. On the other hand, evaluation of control algorithm in PLC is cyclical, which generates two important conditions to consider in the PN model; the cyclical evaluation in PN would generate accumulation of marks in the places, and in function of the logic, marking and consuming of theses in places that represent coils in the LD. This last condition is also necessary to restore the information of places in PN that represent physical analog signals or memory registers. Figure 10 shows the distribution of discrete signals in PN, and Eq. (15) its interpretation. Only one transition can be enabled at a time; if the input place does not have a mark, then the transition ð Þ <sup>I</sup>; <sup>O</sup>; <sup>B</sup> <sup>c</sup> is enabled for inhibitor arc. Eq. (16) is the generalization of the marking of <sup>I</sup>,

> <sup>n</sup> <sup>∪</sup> <sup>O</sup><sup>c</sup> m � �; Bb <sup>¼</sup> Bo

For tokens accumulation problem in input places, the Eqs. (17) and (18) are proposed. Both equations are is in function of the marking of inputs places and of output place. Eq. (17) is for

ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>Y</sup>Mð Þ¼ <sup>∗</sup><sup>t</sup> 1&& ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>0</sup>

ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>X</sup>Mð Þ¼ <sup>∗</sup><sup>t</sup> 1&& ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>0</sup>

In the same way, to consume token in output place and restoring conditions of PN structures, Eqs. (19) and (20) are defined, which are in function of both marking input places and output

RC tð Þ¼ <sup>∗</sup> <sup>Y</sup>Mð Þ¼ <sup>∗</sup><sup>t</sup> 0&&ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>1</sup>

RC tð Þ¼ <sup>∗</sup> <sup>X</sup>Mð Þ¼ <sup>∗</sup><sup>t</sup> 0&&ð Þ <sup>O</sup>; <sup>B</sup> ð Þ¼ <sup>t</sup><sup>∗</sup> <sup>1</sup>

From the above, the ladder diagram Petri net: discrete event systems is defined as it is shown

Eq. 16 to distribution of signals, Eqs. 17 and 18 to accumulate tokens and Eqs. 19 and 20 to restart conditions should be evaluated after each marking of the net Mkþ<sup>1</sup> to update the marking of LDPN and simulate cycled behavior of PLC. Marking of input places I is in

n o

n o

n o

n o

, then M Ið Þ ; <sup>O</sup>; <sup>B</sup> <sup>o</sup> <sup>¼</sup> <sup>0</sup> and M Ið Þ ; <sup>O</sup>; <sup>B</sup> <sup>c</sup> <sup>¼</sup> <sup>1</sup>

M Ið Þ ; <sup>O</sup>; <sup>B</sup> <sup>o</sup> <sup>¼</sup> <sup>1</sup> and M Ið Þ ; <sup>O</sup>; <sup>B</sup> <sup>c</sup> <sup>¼</sup> <sup>0</sup> � �

<sup>n</sup> ∪ B<sup>c</sup> m

� � (15)

(16)

(17)

(18)

(19)

(20)

O y B places.

24 Petri Nets in Science and Engineering

places.

in Table 1.

function of discrete sensors states.

Ii ¼ I o <sup>n</sup> ∪ I c m � �; Oo <sup>¼</sup> <sup>O</sup><sup>o</sup>

where the subscripts n and m are not necessarily equal.

0 1 � �

Considering symbols of [3], for a pre-set and post-set of places, are defined:

M Ið Þ¼ ; O; B

∗t ¼ f g p : ð Þ p; t ∈F , the set of input places of t. ∗t ¼ f g p : ð Þ t; p ∈F , the set of output places of t.

structures with logic AND, and Eq. (18) for logic OR.


#### 3.3. Model of control lines both discrete inputs and outputs

Figure 11 shows the PN model of logic AND, if input places I o 1, O<sup>c</sup> <sup>3</sup> y B<sup>o</sup> <sup>2</sup> have a token, then L1 transition is enabled. The L1 firing puts a token at place O1. When are updates the marking of input places, the Eq. (17) disables the L1 transition, avoiding a token more in output place O1.

P ¼ f g I ∪ O ∪ B ∪ AI ∪ AR ∪ RC is a finite set of places, where: I ¼ f g I1; I2;…; Ii is a finite set of places that represent discrete physical inputs, O ¼ f g O1; O2;…; Oo is a finite set of places that represent discrete physical outputs, B ¼ f g B1; B2; …; Bb is a finite set of places that represent discrete memory signals, AI ¼ f g AI1; AI2; …; AIai is a finite set of places that represent analog physical inputs, AR ¼ f g AR1; ARI2; …; ARar is a finite set of places that represent analog memory signals, RC ¼ f g RC1;RC2; …; RCrc is a finite set of places to restart condition of the nets and its marking it in function of the states of inputs and outputs of control line type. T ¼ I <sup>c</sup>∣<sup>o</sup>; ; O<sup>c</sup>∣<sup>o</sup>; ; B<sup>c</sup>∣<sup>o</sup>; L; AI; RC � � is a finite set of transitions, where: I <sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>I</sup> c∣o <sup>1</sup> ;I c∣o <sup>2</sup> ; …;I c∣o i n o is a finite set of transitions that have discrete physical inputs, <sup>O</sup><sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>O</sup><sup>c</sup>∣<sup>o</sup> <sup>1</sup> ; <sup>O</sup><sup>c</sup>∣<sup>o</sup> <sup>2</sup> ; …; <sup>O</sup><sup>c</sup>∣<sup>o</sup> o n o is a finite set of transitions that have discrete physical outputs, <sup>B</sup><sup>c</sup>∣<sup>o</sup> <sup>¼</sup> <sup>B</sup><sup>c</sup>∣<sup>o</sup> <sup>1</sup> ; <sup>B</sup><sup>c</sup>∣<sup>o</sup> <sup>2</sup> ; …; <sup>B</sup><sup>c</sup>∣<sup>o</sup> b n o is a finite set of transitions that have discrete memory signals, L ¼ f g L1; L2; …; L<sup>l</sup> is a finite set of transitions that may have places of discrete signals, AI ¼ f g AI1; AI2; …; AIai is a finite set of transitions that can have discrete and/or analog signals, its fire condition it in function of mathematics or logics restrictions. RC ¼ f g RC1; RC2; …; RCrc is a finite set of transitions that have input place RC to restart condition of PN structure. F⊆ð Þ P � T ∪ð Þ T � P is a set of arcs. W ¼ F ! f g1 , all weights of the arcs are equal to 1.

<sup>M</sup><sup>0</sup> <sup>¼</sup> <sup>P</sup> ! f g <sup>0</sup>; <sup>1</sup> , discrete signal: P ! f g Z 16 bit integer ð Þ , analog signal: �

Table 1. Definition of LDPN: Discrete event systems.

A Discrete-LDPN is a 5-tuple (P, T, W, F, M0), where:

Figure 11. PN model of logic AND.

By Eq. (19), the marking of place RC is in function of both marking input places and output place.

Figure 12 shows the PN model of logic OR, if any input places I c 1, O<sup>o</sup> <sup>5</sup> y Bo <sup>2</sup> have a token, then L1, L2 or L3 transition is enabled, respectively. If the transition enabled is fired, then a token is put at place O1. When are updates the marking of input places, the Eq. (18) disables the L1, L2 and L3 transitions, avoiding a toke more in output place O1. By Eq. (20), the marking of place RC is in function of both marking input places and output place.

Figure 13 shows the PN model of logic AND-OR, output place can get token from L1 or L2 transitions, in function of marking of input places I o 1, O<sup>c</sup> <sup>3</sup> y B<sup>o</sup> <sup>2</sup> or I o 1, O<sup>c</sup> <sup>3</sup> y O<sup>c</sup> <sup>7</sup> have a token, respectively. The L1 or L2 firing puts a token at place O1. When are updates the marking of input places, the Eqs. (17) and (18) disables the L1 and L2 transitions, avoiding a token more in output place O1. The marking of place RC is in function of both marking input places of L1 and L2 transitions and output place O<sup>1</sup> based on Eqs. (19) and (20) to restart condition.

Figure 14 shows the PN model of logic auto-loop. In this model, it is necessary that L1 transition to be enabled and fired set a token in the output place O1, enabling the Oo <sup>1</sup> transition, which consumes the token of O<sup>1</sup> and sets a token in the place O<sup>o</sup> <sup>1</sup>, enabling the L2 and holding a token in O1. The restart condition of the model auto-loop is in function of the Eqs. (19) and (20).

Figure 15 shows the PN model of logic interlocking. Both places O1 and O2 enable the Oc

transitions, respectively. If L1 or L2 transition is firing first disables the other transition by the

Figure 16 shows the PN model of on-delay timer. The BT and PT are variables to determine base time and preset time, respectively. The marking of the place AI<sup>2</sup> is a data analog to store the sum ET ¼ ET þ BT. The marking of the place O<sup>1</sup> is in function of firing of the AI<sup>2</sup> transition, which depends on the condition if I ð Þ <sup>1</sup> ¼ 1&& ET ≥ PT . To restart condition of the places O<sup>1</sup>

<sup>2</sup> transitions by the inhibitor arcs, placing a token in input places <sup>O</sup><sup>c</sup>

3.4. Model of control lines with analog inputs and output discrete

c 1.

inhibitor arc. The restart condition places RC<sup>1</sup> and RC<sup>2</sup> are in function of Eq. (19).

Oc

and AI<sup>2</sup> are in function of I

Figure 14. PN model of logic auto-loop.

Figure 13. PN model of logic AND–OR.

<sup>1</sup> and

<sup>2</sup> of L1 and L2

<sup>1</sup> and <sup>O</sup><sup>c</sup>

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 27

Figure 12. PN model of logic OR.

Figure 13. PN model of logic AND–OR.

By Eq. (19), the marking of place RC is in function of both marking input places and output

L2 or L3 transition is enabled, respectively. If the transition enabled is fired, then a token is put at place O1. When are updates the marking of input places, the Eq. (18) disables the L1, L2 and L3 transitions, avoiding a toke more in output place O1. By Eq. (20), the marking of place RC is

Figure 13 shows the PN model of logic AND-OR, output place can get token from L1 or L2

respectively. The L1 or L2 firing puts a token at place O1. When are updates the marking of input places, the Eqs. (17) and (18) disables the L1 and L2 transitions, avoiding a token more in output place O1. The marking of place RC is in function of both marking input places of L1 and

Figure 14 shows the PN model of logic auto-loop. In this model, it is necessary that L1

token in O1. The restart condition of the model auto-loop is in function of the Eqs. (19) and (20).

L2 transitions and output place O<sup>1</sup> based on Eqs. (19) and (20) to restart condition.

transition to be enabled and fired set a token in the output place O1, enabling the Oo

o 1, O<sup>c</sup> <sup>3</sup> y B<sup>o</sup>

c 1, O<sup>o</sup> <sup>5</sup> y Bo

<sup>2</sup> or I o 1, O<sup>c</sup> <sup>3</sup> y O<sup>c</sup>

<sup>2</sup> have a token, then L1,

<sup>7</sup> have a token,

<sup>1</sup> transition,

<sup>1</sup>, enabling the L2 and holding a

Figure 12 shows the PN model of logic OR, if any input places I

in function of both marking input places and output place.

which consumes the token of O<sup>1</sup> and sets a token in the place O<sup>o</sup>

Figure 12. PN model of logic OR.

transitions, in function of marking of input places I

place.

Figure 11. PN model of logic AND.

26 Petri Nets in Science and Engineering

Figure 14. PN model of logic auto-loop.

Figure 15 shows the PN model of logic interlocking. Both places O1 and O2 enable the Oc <sup>1</sup> and Oc <sup>2</sup> transitions by the inhibitor arcs, placing a token in input places <sup>O</sup><sup>c</sup> <sup>1</sup> and <sup>O</sup><sup>c</sup> <sup>2</sup> of L1 and L2 transitions, respectively. If L1 or L2 transition is firing first disables the other transition by the inhibitor arc. The restart condition places RC<sup>1</sup> and RC<sup>2</sup> are in function of Eq. (19).

#### 3.4. Model of control lines with analog inputs and output discrete

Figure 16 shows the PN model of on-delay timer. The BT and PT are variables to determine base time and preset time, respectively. The marking of the place AI<sup>2</sup> is a data analog to store the sum ET ¼ ET þ BT. The marking of the place O<sup>1</sup> is in function of firing of the AI<sup>2</sup> transition, which depends on the condition if I ð Þ <sup>1</sup> ¼ 1&& ET ≥ PT . To restart condition of the places O<sup>1</sup> and AI<sup>2</sup> are in function of I c 1.

it is fired, then put a token in place AI4, which enables AI3 transition and consumes the token

Figure 18 shows the PN model of logic up-counter and Figure 19 to PN model of logic down-

0&& M Ið Þ¼ <sup>1</sup>ð Þ t∗ 0g, which is to detect a positive transition in the marking, respectively. In place AI<sup>1</sup> are added the tokens (positive transition), if CV ð Þ ≥ PV then AI1 transition is enabled, and its

Figure 19 shows the PN model of logic down-counter, which has similar behavior to up-

2

o

o

<sup>1</sup> is in function of M I<sup>o</sup>

has a token, then it is consumed the token of the

<sup>1</sup> consume one token of place AI1, if CV ð Þ ≤ 0 , then the

1

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 29

<sup>¼</sup> <sup>f</sup>M Ið Þ¼ <sup>1</sup>ð Þ <sup>∗</sup><sup>t</sup>

counter. In both models, the marking of the place I

fire put a token in place O1. If the place RC I<sup>o</sup>

fire of AI1 transition puts a token in place O1.

counter, just that if one token in place I

Figure 18. PN model of logic up-counter.

Figure 17. PN model of logic off-delay timer.

of place O1.

place O1 and CV ¼ 0.

Figure 15. PN model of logic interlocking.

Figure 16. PN model of on-delay timer.

Figure 17 shows the PN model of logic off-delay timer. The place to restart condition RC and fire of RC1 is putting a token in output place O<sup>1</sup> that is the initial condition of the structure PN. When the I c <sup>1</sup> transition is fired put a token in place I c <sup>1</sup>, which enables AI1 transition to allow the sum of time ET ¼ ET þ BT. The fire of AI2 transition is in function of if Ið Þ <sup>1</sup> ¼ 0&& ET ≤ PT , if

Figure 17. PN model of logic off-delay timer.

it is fired, then put a token in place AI4, which enables AI3 transition and consumes the token of place O1.

Figure 18 shows the PN model of logic up-counter and Figure 19 to PN model of logic downcounter. In both models, the marking of the place I o <sup>1</sup> is in function of M I<sup>o</sup> 1 <sup>¼</sup> <sup>f</sup>M Ið Þ¼ <sup>1</sup>ð Þ <sup>∗</sup><sup>t</sup> 0&& M Ið Þ¼ <sup>1</sup>ð Þ t∗ 0g, which is to detect a positive transition in the marking, respectively. In place AI<sup>1</sup> are added the tokens (positive transition), if CV ð Þ ≥ PV then AI1 transition is enabled, and its fire put a token in place O1. If the place RC I<sup>o</sup> 2 has a token, then it is consumed the token of the place O1 and CV ¼ 0.

Figure 19 shows the PN model of logic down-counter, which has similar behavior to upcounter, just that if one token in place I o <sup>1</sup> consume one token of place AI1, if CV ð Þ ≤ 0 , then the fire of AI1 transition puts a token in place O1.

Figure 18. PN model of logic up-counter.

Figure 17 shows the PN model of logic off-delay timer. The place to restart condition RC and fire of RC1 is putting a token in output place O<sup>1</sup> that is the initial condition of the structure PN.

sum of time ET ¼ ET þ BT. The fire of AI2 transition is in function of if Ið Þ <sup>1</sup> ¼ 0&& ET ≤ PT , if

c

<sup>1</sup>, which enables AI1 transition to allow the

<sup>1</sup> transition is fired put a token in place I

When the I

c

Figure 16. PN model of on-delay timer.

Figure 15. PN model of logic interlocking.

28 Petri Nets in Science and Engineering

Figure 19. PN model of logic down-counter.

Figure 20. PN model of logic of comparisons.

Figure 20 shows the PN model of logic of comparisons of two analog places. Enabling and firing of AI1 is in function of if Vð Þ <sup>1</sup> ¼ V<sup>2</sup> ; if Vð Þ <sup>1</sup> < V<sup>2</sup> ; if Vð Þ <sup>1</sup> > V<sup>2</sup> ; according to the comparison. Similarly, the marking of place RC is in function of RC Vð Þ <sup>1</sup> 6¼ V<sup>2</sup> ; RC Vð Þ <sup>1</sup> ≥ V<sup>2</sup> ; RC Vð Þ <sup>1</sup> ≤ V<sup>2</sup> , respectively.

#### 4. Example

Figure 21 shows the control algorithm in LD of run of three motors sequentially [14]. The Start and Stop signals are physical inputs of type pushbutton. The Motor\_1, Motor\_2 and Motor\_3 coils are physical outputs. The IR1, IR2 and IR3 variables are bits of memory. The first control line is logic of auto-loop, if Start variable is equal to one, then, the IR1 coil is energized and so it is hold by the contact IR1. It is also energized the Motor\_1 coil, and the timer T1 and T2 begin counting time. In T1, if ET ≥ PT, then, the IR2 and Motor\_2 coils are energized. In T2, if ET ≥ PT, then, the IR3 and Motor\_3 coils are energized. If Stop = 1, then, the IR1 coil is de-energized, and are restart conditions of the control algorithm. Table 2 shows the equivalence of signals in

Figure 22 shows the LDPN to control algorithm of run of three motors sequentially. Restart

B1 is in function of input places I1 and I2 by Eqs. 19 and 20. Restart condition places RC2 to RC6

<sup>1</sup> by Eq. 19. The restarting condition of place

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 31

function of the definition LDPN.

Figure 21. Run of three motors sequentially.

conditions of the output places are in function of B<sup>c</sup>

Figure 21. Run of three motors sequentially.

Figure 20 shows the PN model of logic of comparisons of two analog places. Enabling and firing of AI1 is in function of if Vð Þ <sup>1</sup> ¼ V<sup>2</sup> ; if Vð Þ <sup>1</sup> < V<sup>2</sup> ; if Vð Þ <sup>1</sup> > V<sup>2</sup> ; according to the comparison. Similarly, the marking of place RC is in function of RC Vð Þ <sup>1</sup> 6¼ V<sup>2</sup> ; RC Vð Þ <sup>1</sup> ≥ V<sup>2</sup> ;

Figure 21 shows the control algorithm in LD of run of three motors sequentially [14]. The Start and Stop signals are physical inputs of type pushbutton. The Motor\_1, Motor\_2 and Motor\_3 coils are physical outputs. The IR1, IR2 and IR3 variables are bits of memory. The first control line is logic of auto-loop, if Start variable is equal to one, then, the IR1 coil is energized and so it is hold by the contact IR1. It is also energized the Motor\_1 coil, and the timer T1 and T2 begin counting time. In T1, if ET ≥ PT, then, the IR2 and Motor\_2 coils are energized. In T2, if ET ≥ PT,

RC Vð Þ <sup>1</sup> ≤ V<sup>2</sup> , respectively.

Figure 20. PN model of logic of comparisons.

Figure 19. PN model of logic down-counter.

30 Petri Nets in Science and Engineering

4. Example

then, the IR3 and Motor\_3 coils are energized. If Stop = 1, then, the IR1 coil is de-energized, and are restart conditions of the control algorithm. Table 2 shows the equivalence of signals in function of the definition LDPN.

Figure 22 shows the LDPN to control algorithm of run of three motors sequentially. Restart conditions of the output places are in function of B<sup>c</sup> <sup>1</sup> by Eq. 19. The restarting condition of place B1 is in function of input places I1 and I2 by Eqs. 19 and 20. Restart condition places RC2 to RC6

#### Petri Nets in Science and Engineering


Table 2. Equivalence of signals of control algorithm in LDPN.

are in function of the marking B<sup>o</sup> , which are connected from B<sup>c</sup> . For complex control algorithms implies a larger graphic LDPN, it is advisable to indicate the marking function of the places RC. Eq. 21 shows the incidence matrix of the PN model respectively, where the conditioning if-then of transitions for reasons of space, which are indicated on corresponding figures, is omitted.

The dynamic behavior of the PN model by run of three motors sequentially is described by the following marking. Fired the transitions with inhibitor arcs, initial marking M0 is:

<sup>M</sup><sup>0</sup> <sup>¼</sup> <sup>I</sup><sup>1</sup> <sup>I</sup> o I<sup>2</sup> I c I c B<sup>1</sup> Bo Bo Bo Bo AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup> 00011 0 0 0 0 01ms 0 10<sup>4</sup> <sup>1</sup>ms 0 2∗10<sup>4</sup> 000 0 1 1 1 1 1 � � (21)

<sup>M</sup><sup>1</sup> <sup>¼</sup> <sup>I</sup><sup>1</sup> <sup>I</sup> o I<sup>2</sup> I c I c B<sup>1</sup> Bo Bo Bo Bo

In these conditions, the B<sup>o</sup>

transitions by Eqs. (17) and (18). Another place B<sup>o</sup>

Figure 22. PN model of run of three motors sequentially.

AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup>

enables L3 transition; its fire puts a token in

Ladder Diagram Petri Nets: Discrete Event Systems http://dx.doi.org/10.5772/intechopen.75753 transition is enabled, its fire puts a token in four places Bo

(22)

, this

00001 1 0 0 0 01ms 0 104 <sup>1</sup>ms 0 2∗10<sup>4</sup> 000 0 0 0 0 0 0

enables L2 transition, its fire puts a new token in the place B1, it disables the fire of L1 and L2

If place I<sup>1</sup> has token, which enable the I o transition, its fire puts a token in the place I o , which enabled the L1 transition, its fire puts a token in the place B1. In these conditions, by Eq. (16), the tokens in places of restarting conditions are consumed; the marking corresponding of LDPN is shown in Eq. (23).

Figure 22. PN model of run of three motors sequentially.

are in function of the marking B<sup>o</sup>

Petri Nets in Science and Engineering

Table 2. Equivalence of signals of control algorithm in LDPN.

�11 1 1 1

AI1 �1 BT ¼ 1ms ET þ BT

If place I<sup>1</sup> has token, which enable the I

LDPN is shown in Eq. (23).

is omitted.

I<sup>1</sup> I o I<sup>2</sup> I c I c B<sup>1</sup> B<sup>o</sup> B<sup>o</sup> B<sup>o</sup> B<sup>o</sup>

�11 1

L1 �1 �1 1 L2 �1 1 �1

Aij ¼

I o �1 1 I c

Bo

Bc

<sup>M</sup><sup>0</sup> <sup>¼</sup> <sup>I</sup><sup>1</sup> <sup>I</sup> o I<sup>2</sup> I c I c B<sup>1</sup> Bo Bo Bo Bo , which are connected from B<sup>c</sup>

AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup>

AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup>

transition, its fire puts a token in the place I

rithms implies a larger graphic LDPN, it is advisable to indicate the marking function of the places RC. Eq. 21 shows the incidence matrix of the PN model respectively, where the conditioning if-then of transitions for reasons of space, which are indicated on corresponding figures,

�1 11111

The dynamic behavior of the PN model by run of three motors sequentially is described by the

00011 0 0 0 0 01ms 0 10<sup>4</sup> 1ms 0 2∗10<sup>4</sup> 000 0 1 1 1 1 1 � �

enabled the L1 transition, its fire puts a token in the place B1. In these conditions, by Eq. (16), the tokens in places of restarting conditions are consumed; the marking corresponding of

following marking. Fired the transitions with inhibitor arcs, initial marking M0 is:

o

L3 �1 1

AI3 �1 BT ¼ 1ms ET þ BT

AI2 ET <sup>þ</sup> BT PT <sup>¼</sup> <sup>10</sup><sup>4</sup> <sup>1</sup>

AI4 ET <sup>þ</sup> BT PT <sup>¼</sup> <sup>2</sup>∗104 <sup>1</sup> RC1 �1 �1 RC2 �1 �1 RC3 �1 �1 RC4 ET �1 RC5 �1 �1 RC6 ET �1

LD LDPN Start I1 Stop I2 Motor\_1 O1 Motor\_2 O2 Motor\_3 O3 IR1 B1 IR2 B2 IR3 B3

. For complex control algo-

(21)

o , which

<sup>M</sup><sup>1</sup> <sup>¼</sup> <sup>I</sup><sup>1</sup> <sup>I</sup> o I<sup>2</sup> I c I c B<sup>1</sup> Bo Bo Bo Bo AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup> 00001 1 0 0 0 01ms 0 104 <sup>1</sup>ms 0 2∗10<sup>4</sup> 000 0 0 0 0 0 0 (22)

In these conditions, the B<sup>o</sup> transition is enabled, its fire puts a token in four places Bo , this enables L2 transition, its fire puts a new token in the place B1, it disables the fire of L1 and L2 transitions by Eqs. (17) and (18). Another place B<sup>o</sup> enables L3 transition; its fire puts a token in the place O1. The others two places Bo <sup>1</sup> enable AI1 and AI3 transition to add the base time, respectively. Eq. (24) shows these conditions of LDPN, besides the update marking.

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<sup>M</sup><sup>1</sup> <sup>¼</sup> <sup>I</sup><sup>1</sup> <sup>I</sup> o <sup>1</sup> I<sup>2</sup> I c <sup>2</sup> I c <sup>2</sup> B<sup>1</sup> Bo <sup>1</sup> Bo <sup>1</sup> Bo <sup>1</sup> Bo <sup>1</sup> AI<sup>1</sup> AI<sup>2</sup> AI<sup>3</sup> AI<sup>4</sup> AI<sup>5</sup> AI<sup>6</sup> O<sup>1</sup> O<sup>2</sup> O<sup>3</sup> RC<sup>1</sup> RC<sup>2</sup> RC<sup>3</sup> RC<sup>4</sup> RC<sup>5</sup> RC<sup>6</sup> 00011 1 1 1 1 11ms Add <sup>10</sup><sup>4</sup> <sup>1</sup>ms Add <sup>2</sup>∗10<sup>4</sup> 100 0 0 0 0 0 0 (23)

In these conditions, if ET ≥ PT, in both AI2 and AI4 transitions put a token in places O<sup>2</sup> and O3, respectively. When place I o <sup>2</sup> has a token enabling the RC1 transition, its fire consumes a token in the place B1, restarting condition in LDPN.
