**4. Conclusion**

Sulfur passivation and low temperature process modules are developed and used in the fabrication of Ge0.83Sn0.17 p-MOSFET. Reduction in *S* and improvement in peak *Gm,int* and *μeff* are observed for the sulfur-passivated Ge0.83Sn0.17 p-MOSFETs as compared with the non-passivated control. This is attributed to the effective suppression of Ge and Sn oxides formation, and suppression of Sn surface segregation by sulfur passivation. In addition, the effect of sulfur passivation on *Dit* reduction is also investigated. It is observed that sulfur passivation reduces the *Dit* from the valence band edge to midgap of GeSn. As a result, the lowest *S* of 100 mV/ decade is achieved by the sulfur-passivated Ge0.83Sn0.17 p-MOSFETs. *Dit* level of 10<sup>13</sup> cm−2 eV−1 in the sulfur-passivated sample is still very high. Further improvement to significantly reduce *Dit* is needed to increase the hole mobility.

[5] Xie R, Phung TH, He W, Sun Z, Yu M, Cheng Z, Zhu C. High mobility high-*k*/Ge PMOSFETs with 1 nm EOT-new concept on interface engineering and interface charac-

Ge0.83Sn0.17 P-Channel Metal-Oxide-Semiconductor Field-Effect Transistors: Impact of Sulfur…

http://dx.doi.org/10.5772/intechopen.74532

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[6] Chern W, Hashemi P, Teherani JT, Yu T, Dong Y, Xia G, Antoniadis DA, Hoyt JL. High mobility high-*k*-all-around asymmetrically-strained germanium nanowire trigate p-MOS-

[7] Hashemi P, Chern W, Lee HS, Teherani JT, Zhu Y, Gonsalvez J, Shahidi GG, Hoyt JL. Ultrathin strained-Ge channel p-MOSFETs with high-*k*/metal gate and sub-1-nm equiva-

[8] Wu H, Si M, Dong L, Zhang J, Ye PD. Ge CMOS: Breakthroughs of nFETs (*Imax* = 714 mA/mm, *Gmax* = 590 mS/mm) by recessed channel and S/D. IEEE Symposium on VLSI

[9] Gong X, Zhou Q, Owen MHS, Xu X, Lei D, Chen S-H, Tsai G, Cheng C-C, Lin Y-R, Wu C-H, Ko C-H, Yeo Y-C. InAlP-capped (100) Ge nFETs with 1.06 nm EOT: Achieving record high peak mobility and first integration on 300 mm Si substrate. IEEE IEDM

[10] Lee CH, Lu C, Nishimura T, Nagashio K, Toriumi A. Thermally robust CMOS-aware Ge MOSFETs with high mobility at high-carrier densities on a single orientation Ge sub-

[11] Low KL, Yang Y, Han G, Fan W, Yeo Y-C. Electronic band structure and effective mass

[12] Han G, Su S, Zhan C, Zhou Q, Yang Y, Wang L, Guo P, Wang W, Wong CP, Shen ZX, Cheng B, Yeo Y-C. High-mobility germanium-tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules. IEEE IEDM Technical Digest.

[13] Gupta S, Chen R, Magyari-Kope B, Lin H, Yang B, Nainani A, Nishi Y, Harris JS, Saraswat KC. GeSn technology: Extending the Ge electronics roadmap. IEEE IEDM Technical Digest.

[14] Liu M, Han G, Liu Y, Zhang C, Wang H, Li X, Zhang J, Cheng B, Hao Y. Undoped Ge0.92Sn0.08 quantum well pMOSFETs on (001), (011) and (111) substrates with in situ

[15] Wang L, Su S, Wang W, Gong X, Yang Y, Guo P, Zhang G, Xue C, Cheng B, Han G, Yeo Y-C. Strained germanium–tin (GeSn) p-channel metal-oxide-semiconductor field-effecttransistors (p-MOSFETs) with ammonium sulfide passivation. Solid-State Electronics.

[16] Gong X, Han G, Bai F, Su S, Guo P, Yang Y, Cheng R, Zhang D, Zhang G, Xue C, Cheng B, Pan J, Zhang Z, Tok ES, Antoniadis D, Yeo Y-C. Germanium-tin (GeSn) p-channel MOSFETs

passivation: High hole mobility and dependence of performance on orientation.

alloys. Journal of Applied Physics. 2012;**112**(10):103715

lent oxide thickness. IEEE Electron Device Letters. 2012;**33**(7):943-945

strate. IEEE Symposium on VLSI Technology Digest. 2014:144-145

IEEE Symposium on VLSI Technology Digest. 2014:100-101

terization. IEEE IEDM Technical Digest. 2008:393-396

FETs. IEEE IEDM Technical Digest. 2012:387-390

Technology Digest. 2014:96-97

Technical Digest. 2014:231-234

Sn*<sup>x</sup>*

parameters of Ge1-*<sup>x</sup>*

2011:402-404

2011:398-401

2013;**83**:66-70

Si2 H6
