**1. Introduction**

Materials with high carrier mobilities such as germanium (Ge) could replace Silicon (Si) as the high performance logic applications [1–10]. Recently, germanium-tin (GeSn) was reported to have a higher hole mobility than Ge and is a promising channel material for p-channel MOSFETs (p-MOSFETs) [11–18].

Theoretical calculation [11 increasing Sn composition. It is also demonstrated experimentally [19] that increasing Sn

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composition in GeSn p-MOSFETs increases the effective hole mobility. However, due to the low surface energy and large covalent radius of Sn, Sn atoms may segregate to the surface during growth of GeSn [20–22]. Hence, the thermal stability may be worse at a higher Sn composition. Li et al. reported that a Sn-rich surface layer would form when Ge0.922Sn0.078 is annealed at 620°C [23]. A similar phenomenon occurs on Ge0.915Sn0.085 surface after annealing at 500°C [24]. For Sn composition as high as 17%, self-assembled Sn wires can form at an annealing temperature as low as 280°C [25]. Severe Sn segregation may reduce carrier mobility and degrade the drive current in MOSFETs. Therefore, in order to achieve high performance GeSn p-MOSFETs with high Sn composition, a fabrication process with low thermal budget may be required to maintain a good quality of the GeSn channel material and the GeSn/high-*k* dielectric interface.

**2. Experiment**

(DHF) (HF:H<sup>2</sup>

**2.1. Material growth and characterization of Ge0.83Sn0.17 substrate**

The high quality Ge0.83Sn0.17 sample was grown using molecular beam epitaxy (MBE). 4-inch (001)-oriented Ge wafers with n-type doping concentration of 5 × 1016 cm−3 were used as the starting substrates. After the cyclic cleaning of Ge substrates using dilute hydrofluoric acid

film was grown on the Ge substrate using the solid source low temperature MBE system [32, 33]. The growth temperature was set at 100°C. 99.9999% pure Ge and 99.9999% pure Sn were used as Ge and Sn sources, respectively. The growth chamber has a base pressure of 3 × 10−10 Torr. Ge0.83Sn0.17 film with the thickness of 10 nm was grown on the Ge substrates. **Figure 1** shows the 5 × 5 μm AFM scan of the as-grown Ge0.83Sn0.17 surface. The surface is very smooth with a root-mean-square (RMS) roughness as small as 0.198 nm. High-resolution transmission electron microscopy (HRTEM) was employed to analyze the crystalline quality of the as-grown Ge0.83Sn0.17 sample. **Figure 2(a)** shows a low magnification cross-sectional TEM (XTEM) image of an as-grown Ge0.83Sn0.17 sample, indicating that the GeSn surface is smooth. The GeSn layer thickness is ~10 nm. The high resolution TEM (HRTEM) image in **Figure 2(b)** shows the smooth Ge0.83Sn0.17 surface. In addition, very clear lattice fringes and defect-free GeSn/Ge interface can be observed, as shown in the HRTEM image of **Figure 2(c)**. High resolution X-ray diffraction (HRXRD) was also used to analyze the Sn composition and strain property of the as-grown Ge0.83Sn0.17 substrate. **Figure 3(a)** shows the (004) ω-2θ rocking scan of the as-grown sample. Both Ge and GeSn peaks are well-defined. The peak at smaller 2θ value is the GeSn peak. The relative broad full-width-half-maximum (FWHM) is due to the thin GeSn layer thickness (~10 nm). (115) reciprocal space mapping (RSM) of an as-grown Ge0.83Sn0.17/ Ge (001) sample is shown in **Figure 3(b)**. The GeSn film is fully strained to the Ge substrate and

the substitutional Sn composition is calculated to be 17% from XRD measurement.

pre-gate cleaning using DHF (HF:H<sup>2</sup>

roughness as small as 0.198 nm.

**Figure 4(a)** summarizes the key process steps for fabricating Ge0.83Sn0.17 p-MOSFETs. After the MBE growth of ~10 nm Ge0.83Sn0.17 film on the lightly n-type doped Ge (100) substrate,

**Figure 1.** 5 × 5 μm AFM scan of the as-grown Ge0.83Sn0.17 substrate. The GeSn surface is very smooth with a RMS

O = 1:50) and DI water was performed. Two splits were

O = 1:50) and deionized (DI) water, the unintentionally p-type doped Ge0.83Sn0.17

Ge0.83Sn0.17 P-Channel Metal-Oxide-Semiconductor Field-Effect Transistors: Impact of Sulfur…

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Various passivation techniques have been demonstrated to be effective in improving the gate stack quality of both Ge and GeSn channel p-MOSFETs, such as Si<sup>2</sup> H6 passivation [12, 17], Ge capping [26], GeSnO*<sup>x</sup>* passivation [27, 28], and sulfur passivation [15, 29, 30]. Among these passivation techniques adopted for GeSn p-MOSFETs fabrication, Si<sup>2</sup> H6 passivation and GeSnO*<sup>x</sup>* passivation require a process temperature higher than 370°C and 400°C, respectively. It has already been reported that Sn can segregate out to the GeSn surface during Si passivation process at a temperature of 370°C and degrades the device performance [17]. Therefore, low temperature passivation technique was investigated in this work for the fabrication of GeSn p-MOSFETs with Sn composition of 17%.

The adsorption of sulfur atoms is a promising route to chemically and electrically passivate the highly reactive Ge and GeSn surface [15, 29–31]. Compared with other passivation techniques, room temperature sulfur passivation using (NH<sup>4</sup> ) 2 S solution has several advantages: (1) GeSn surface could be effectively passivated through the formation of covalent S-Ge and S-Sn bond. This will reduce oxide formation which degrades device performance; (2) The formed sulfur passivation layer is very thin with very little increase on the effective oxide thickness (EOT); (3) Sn segregation can be suppressed during the passivation process owning to a lower thermal budget. Sulfur passivation has already been implemented into Ge0.947Sn0.053 p-MOSFETs fabrication and demonstrated enhanced peak hole mobility as compared with Si<sup>2</sup> H6 passivation [15]. However, the mechanism of the effect of sulfur passivation on the GeSn/HfO<sup>2</sup> interface quality has not been investigated. In addition, the impact of sulfur passivation on the reduction of *Dit* was not quantified.

In this chapter, sulfur passivation of GeSn surface at room temperature was investigated and implemented in the fabrication of Ge0.83Sn0.17 p-channel MOSFETs. To study the impact of sulfur passivation on the quality of high-*k* dielectric/GeSn interface, extensive X-ray photoelectron spectroscopy (XPS) analysis was carried out. Sulfur passivation is found to be effective in suppressing the formation of Sn oxides and Ge oxides, and Sn surface segregation. In addition, sulfur passivation helps to reduce the high-*k* dielectric/GeSn interface trap density *Dit* as extracted using the conductance method. Material study of nickel stanogermanide [Ni(GeSn)] contact formation at low temperatures was also performed for low resistivity [Ni(GeSn)] S/D contact. The sulfur-passivated Ge0.83Sn0.17 p-MOSFETs exhibit smaller subthreshold swing *S*, higher intrinsic transconductance *Gm,int*, and higher effective hole mobility *μeff* as compared to the non-passivated control. At a high inversion carrier density of 1 × 10<sup>13</sup> cm−2, sulfur passivation enhances *μeff* by 25% as compared with the non-passivated control.
