5. Dependence of threshold voltage on temperature

4.2. Validation of the analytical model

46 Design, Simulation and Construction of Field Effect Transistors

gate-channel overlap terminates.

The developed analytical models are validated with simulation data from TCAD. Figure 7 shows the plot of lateral electric field at the surface of the UL-HTFET in the channel region for different Ge-mole fractions of the silicon-germanium layer, at VGS ¼ 1:2 V and VDS ¼ 0:7 V. It has been seen that the modeled values match with the simulated values of lateral electric field except that a small mismatch in the field is observed at the position in the channel where the

Figure 7. Variation of lateral electric field at the surface in the channel for different Ge-mole fractions.

Figure 8. Variation of vertical electric field at the surface in the channel for different Ge-mole fractions.

An algorithm for the extraction of threshold voltage in heterojunction TFET is presented in Figure 10 [17]. The algorithm uses the analytical model of Section 4 to plot multiple curves of surface potential versus position for different gate voltages and fixed drain voltage. The advantage of this algorithm is that the procedure is completely computational, and the threshold voltage can be determined without deriving the transfer characteristics. Moreover, the method can be extended to fit different threshold voltage extraction methods by changing the fitting parameter [17].

The model takes into account the dependence of temperature. The method involves geometrical constructions on a plot of surface potential versus position and using mathematical parameters to define a variable range\_point.

transfer characteristics where the transconductance is maximum. The value at which the

Band Gap Modulated Tunnel FET

49

http://dx.doi.org/10.5772/intechopen.76098

This chapter has presented a comprehensive evaluation of a bandgap-modulated UL-HTFET. The simulation analyses have examined the different electrical parameters and their dependence on the pocket length, mole fraction of the SiGe layer, and gate voltage. An impressive on-off current ratio of >1012 and a subthreshold swing less than 60 mV/dec are observed. An analytical model based on 2-D Poisson equation has been developed for the gate-drain underlap heterojunction TFET. The modeled values of surface potential, electric field, and drain current satisfy the results of the simulation. Furthermore, a temperature-dependent algorithm has been discussed to extract threshold voltage in heterojunction TFETs, and a validation has been presented for the plot of threshold voltage at different temperatures.

The authors would like to acknowledge Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, India, for supporting

tangent intersects the gate voltage axis is taken to be the threshold voltage.

Figure 11. A plot of threshold voltage versus temperature for dielectric constants, 3.9 and 22.

6. Conclusion

Acknowledgements

the work.

Figure 10. Algorithm for the extraction of threshold voltage in heterojunction and homojunction TFETs [17].

A plot of threshold voltage versus temperature is shown in Figure 11. The plot shows that for high-k gate dielectric TFET, the threshold voltage rises with an increase in temperature, whereas for low-k dielectric, the threshold voltage remains almost constant. The simulated values of threshold voltage have been derived using linear extrapolation method of determining threshold voltage. The method involves the construction of a tangent at the point on the

Figure 11. A plot of threshold voltage versus temperature for dielectric constants, 3.9 and 22.

transfer characteristics where the transconductance is maximum. The value at which the tangent intersects the gate voltage axis is taken to be the threshold voltage.
