1. Introduction

Tunnel field effect transistor (TFET) is an asymmetrical gated p-i-n device. Unlike thermionic conduction in metal-oxide-semiconductor FETs (MOSFETs), its working principle is based on a band-to-band tunneling (BTBT) mechanism [1, 2]. This amendment results in a reduced subthreshold swing (SS), low off-state leakage currents, and less short-channel effects. Recently, numerous structural and material designs of TFETs have been proposed with an objective to achieve improvement in subthreshold swing (SS) and off current. A few of them are bandgapengineered TFETs [3], graphene nanoribbon TFETs [4], gate-engineered TFET [5], and strained silicon-germanium TFETs [6]. Double-gate TFET [7], dual-material gate TFET [8], hetero-gate dielectric TFET [9], and heterojunction TFETs [10] have also been investigated for improved electrical parameters of TFET. Generally, TFETs have a very low current as compared to ITRS requirement. In order to get a high ON current, a high-k gate dielectrics are preferred. High-k gate dielectrics causes improved capacitive coupling between the gate and the source-channel tunnel junction, resulting in an increased current in TFET. Moreover, to decline the effective oxide

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

thickness at the tunnel junction, high-k gate oxide is used so that the gate-tunneling current can be reduced. Actually, due to these reasons, the recent trend is to use high-k materials as a better replacement of the conventional SiO2 (silicon dioxide). On the other hand, it causes a significant ambipolar current. The gate-drain underlap structure in association with heterojunction can be adopted to diminish ambipolar current [2]. A silicon-germanium (SiGe) layer is used at the tunnel junction so that bandgap and tunnel width can be modulated. Electrical parameters have been investigated for various Ge-mole fractions.

The effect of germanium mole fraction on the UL-HTFET is investigated. Aluminum with work function (4.1 eV) is considered as the gate material. The proposed device spans across a total length of 100 nm with a length of the channel equal to 20 nm. The δp + Si1-xGex layer extends from the source-channel junction up to 1 nm into the channel under the gate. The various doping

voltages is applied with respect to the source. Here, voltage at the source is considered as the

The tunnel FET works on the principle of band-to-band tunneling. Here, SiGe layer is added at

Figure 2 shows the Ids-Vgs characteristics of the Si/Ge heterojunction UL-HTFET at different lengths of Lp. When the HTFET is turned on, it shows very high on-current due to the effective bandgap narrowing at the interface of source-channel junction. The Ids-Vgs curves are mainly dependent on n + doped pocket length (Lp) as shown in Figure 2; as Lp gets longer, the effective area for tunneling width is extended for HTFET. However, the low off-state current in UL-HTFET (9.205 <sup>10</sup><sup>20</sup> A/μm) when Lp is less than 2 nm, and this indicates that the ambipolar-tunneling effect at drain channel is suppressed. When Lp is 2 nm, as observed, the tunneling width becomes extremely thin to concede tunneling current at Vgs = 0.5 V. This tunneling current interrupts UL-HTFET device performance at off-state. The low Ioff can be achieved at Lp = 1 and 2 nm, and Ion is greatly higher at Lp = 4 nm in TFET. Therefore, an optimum Lp can be located at 1 nm where high ion is achieved and the leakage is suppressed

the channel near the source-channel junction to enhance the on-current.

; drain, 5 1019 cm<sup>3</sup>

. In n-channel, the operation of TFET positive gate and drain

; δp + layer, 1018 cm<sup>3</sup>

Band Gap Modulated Tunnel FET

http://dx.doi.org/10.5772/intechopen.76098

;

39

concentrations are used such as source, 1021 cm<sup>3</sup>

3. Simulated results of UL-HTFET

as shown in Ids-Vgs characteristics.

Figure 2. Transfer characteristics for varying Lp lengths at Vds = 0.7 V.

and intrinsic region, 1016 cm<sup>3</sup>

reference voltage.

Technology Computer Aided Design (TCAD) simulation is a complex iterative mathematical process, and hence various analytical models have been proposed in order to develop a better understanding of the physics-based principles of TFETs and obtain results not constrained by computational time [11]. A number of analytical models based on Poisson equation have been proposed in the study for different geometries [12–14]. In this chapter, a mole fractiondependent model has been proposed and validated.

This chapter is organized as follows: first, the heterojunction gate-drain underlap tunnel is discussed, and in the second section, the electrical parameters of the heterojunction gate-drain underlap tunnel FET (UL-HTFET) is investigated with the help of TCAD simulation. The third section discusses the physics-based compact model and the validation of the model with simulated results. In the last section, the effect of temperature on the electrical parameters is investigated.
