**2.2. Solution-processed metal oxide thin films**

However, with the recent increase on field-effect mobility of TFTs produced with the active layer deposited from solution processes [3, 5, 6, 17, 19, 20], more attention has been attracted to the possibility of using very simple and low-cost deposition methods to obtain high-performance TFTs. Solution-based deposition processes allow the use of techniques like dip coating, spin coating, spray coating, ink-jet printing, silk screen and numerous others which are compatible to large-area, flexible, affordable and scalable applications. **Figure 2** shows a schematic representation of the basic features of common low-cost deposition methods for fabrication of metal oxide TFTs. RF magnetron sputtering (**Figure 2a**) and PLD (**Figure 2b**) produce highly crystalline films with relatively good thickness and uniformity control; however, target materials, vacuum and partial gas pressure systems as well as RF source or laser beam are needed, making these techniques more sophisticated when compared to solution-based processes like spin coating (**Figure 2c**), airbrush spray pyrolysis (**Figure 2d**) or ultrasonic spray pyrolysis (**Figure 2e**). Spin coating is a widespread used deposition technique which yields very thin (ranging from few nanometers up to micrometers) and uniform films by spreading a solution of the desired material onto cleaned substrates and making them spin at high rotation speeds (about 1000–8000 rpm) promoting solvent evaporation. The technique is very successful in the formation of organic or polymeric films but can be used to deposit inorganic materials solutions or suspensions as well. Spray pyrolysis is based on spraying a solution of an organic precursor onto a preheated substrate (usually at a temperature above the degradation temperature of the

138 Design, Simulation and Construction of Field Effect Transistors

**Figure 2.** Summary of the frequently used low-cost deposition techniques used to produce electronic devices based on semiconducting metal oxides. (a) RF magnetron sputtering; (b) pulsed laser deposition (PLD); (c) spin-coating; (d)

airbrush spray-pyrolysis (ASP); and (e) ultrasonic spray-pyrolysis (USP).

Solution-processed metal oxide thin films used as the active layer of transistors can be deposited from any of the techniques mentioned previously. An important key to obtain high performance and reproducible devices is the film uniformity, which can be macroscopically inspected by visual observation (translucent and shiny films usually represent superior quality films) or microscopically from techniques like profilometry (which can measure the surface roughness), atomic force microscopy (AFM) or scanning electron microscopy (SEM). The solution preparation method plays a significant role in the film formation and must be meticulously planned to obtain improved performance devices. The most commonly used solution processing techniques used to produce SMO TFTs are based on: (i) the calcination or pyrolysis of an organic precursor of the desired metal oxide which is soluble in an organic solvent or (ii) on the physical agglomeration or chemical reaction of previously synthesized nanoparticles which can form a uniform suspension in water or in other polar protic solvents.

## *2.2.1. Organic precursor pyrolysis*

The solutions used to prepare SMO films deposited by spin-coating and spray technique are frequently obtained by the dissolution of organic salts containing the metallic atom which forms the metal oxide. **Figure 3** shows the scheme that most common organic salts used metal oxide precursors. Special attention is devoted to zinc acetate dihydrate (**Figure 3a**), which is the basic compound used to obtain ZnO and is soluble in water and other polar protic solvents like ethanol, isopropanol and methanol. Very often, 2-methoxyethanol is used as the solvent with ethanolamine as stabilizer [11, 15, 26] due to the credited better precursor dissolution and film formation.

Spin-coating deposition is commonly carried out using solution concentrations in the (0.03–0.3 M) range to originate organic precursor films which undergo a pyrolysis process by heating up the substrates in a hotplate or in an oven at temperatures above the degradation temperature of the organic compound (usually above 300°C). After the thermal decomposition of the precursor organic phase, oxide agglomerates intermediated by voids, but which can be interconnected along macroscopic distances (superior to few millimeters), are formed. To form a continuous and uniform oxide film, the multiple deposition of precursor layers by spin coating is performed, intercalated by the thermal treatment process to promote the oxide formation and to avoid the dissolution of the previous layers [14].

**Figure 3.** Scheme of the chemical structure of most commonly used organic precursors of metal oxides. (a) Zinc acetate dihydrate; (b) aluminum acetate dibasic; (c) indium acetate hydrate; (d) galium acetyl acetonate; (e) tin acetate.

of the precursor. Above 305°C, no significant mass loss is no longer observed up to 500°C, indicating that, probably, most of the remaining mass is due to the inorganic phase (ZnO). The X-ray diffraction results shown in **Figure 4c** (obtained from a spray-coated sample deposited at 350°C) corroborate the expected results observed from FTIR and TGA/DTG analysis due to the typical pattern of the ordered hexagonal wurtzite phase (according to JCPDS Card No. 36-1451). Atomic force microscopy (AFM) of a spray-coated film at 350°C is shown in **Figure 4d** demonstrating the previously discussed uniform film morphology. Average surface roughness

**Figure 4.** (a) Thermogravimetric analysis of zinc acetate; (b) FTIR spectra of zinc acetate at different temperatures; (c)

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DRX data from a spray-coated film at 350°C; and (d) AFM image of a spray-coated film.

Another interesting approach to obtain thin-film devices from solution is by the use of metal oxide nanoparticles which can be dispersed in water or organic solvents [5–7, 13]. The used nanoparticles are usually obtained by known inorganic synthesis methods and some options are commercially available. These nanoparticles can be used in the form of colloidal suspensions (which often need stabilizers to remain stable) to permit solution processing. The great advantage to use oxide nanoparticles is that the semiconducting phase is already present in the colloidal suspensions and deposition can be carried out at room temperature, without the need of further thermal treatment. This feature is important for the use of flexible substrates, which do not stand temperatures higher than 200°C. However, oxide nanoparticles suspensions usually give rise to lower quality films, with high roughness and large grain boundaries that are deleterious to the film electrical properties. Future improvements in the quality of films produced from oxide nanoparticles suspensions might improve device performance and make this alternative

is less than 5 nm and observed rod-like structures have diameters inferior to 100 nm.

more interesting than processes involving the pyrolysis of organic precursor materials.

*2.2.2. Metal oxide nanoparticles*

Spray-pyrolysis deposition, on the other hand, is a much simpler method which does not require intermediate processing like the multilayer spin-coating method described earlier, being more suitable to industrial scalable processes. During spray deposition, precursor solution droplets reach a substrate heated up to a temperature much higher than the solvent boiling point, forming a solvent vapor layer that avoids the droplet to touch the hot substrate surface (Leidenfrost effect [40]), causing a randomly distributed deposition of micrometric/ nanometric precursor particles on the surface. Since the substrate is also at a temperature above the organic precursor decomposition temperature, oxide formation initiates immediately during spray deposition, producing, if optimum deposition parameters are chosen [8], much more uniform and better quality films than the produced by spin coating.

From the considerations abovementioned concerning the organic precursor degradation temperature, it is of extreme importance to know in advance the physical chemical properties of the precursor salt. **Figure 4a** shows the Fourier-transform infrared spectra (FTIR) in attenuated reflectance mode (ATR) of zinc acetate dihydrate films treated at different temperatures, from 150 to 400°C. Peak (1) at 3377 cm−1 is from the asymmetric stretching mode of hydroxyl groups, whereas peaks (2) and (3) are from the stretching modes of the precursor ester groups (C=O and C—O, respectively). Peaks (4) and (5) are bending modes associated with the CH<sup>3</sup> groups and peaks (6) and (7) are due to bending modes of C=C bonds and COO− groups, respectively. Peaks (8) and (9) correspond to Zn—OH and Zn—O stretching modes. One observes that the peaks associated to the organic phase of zinc acetate [10] gradually disappear by increasing the temperature, remaining only species associated with the inorganic phase (Zn—O) for temperatures above 400°C. Thermogravimetric analysis (**Figure 4b**) shows two main mass loss peaks, one around 100°C, due to loss of adsorbed water and water of crystallization and another around 290°C, due to the thermal degradation of the organic phase

Electrical Characterization of Thin-Film Transistors Based on Solution-Processed Metal Oxides http://dx.doi.org/10.5772/intechopen.78221 141

**Figure 4.** (a) Thermogravimetric analysis of zinc acetate; (b) FTIR spectra of zinc acetate at different temperatures; (c) DRX data from a spray-coated film at 350°C; and (d) AFM image of a spray-coated film.

of the precursor. Above 305°C, no significant mass loss is no longer observed up to 500°C, indicating that, probably, most of the remaining mass is due to the inorganic phase (ZnO).

The X-ray diffraction results shown in **Figure 4c** (obtained from a spray-coated sample deposited at 350°C) corroborate the expected results observed from FTIR and TGA/DTG analysis due to the typical pattern of the ordered hexagonal wurtzite phase (according to JCPDS Card No. 36-1451). Atomic force microscopy (AFM) of a spray-coated film at 350°C is shown in **Figure 4d** demonstrating the previously discussed uniform film morphology. Average surface roughness is less than 5 nm and observed rod-like structures have diameters inferior to 100 nm.

#### *2.2.2. Metal oxide nanoparticles*

Spray-pyrolysis deposition, on the other hand, is a much simpler method which does not require intermediate processing like the multilayer spin-coating method described earlier, being more suitable to industrial scalable processes. During spray deposition, precursor solution droplets reach a substrate heated up to a temperature much higher than the solvent boiling point, forming a solvent vapor layer that avoids the droplet to touch the hot substrate surface (Leidenfrost effect [40]), causing a randomly distributed deposition of micrometric/ nanometric precursor particles on the surface. Since the substrate is also at a temperature above the organic precursor decomposition temperature, oxide formation initiates immediately during spray deposition, producing, if optimum deposition parameters are chosen [8],

**Figure 3.** Scheme of the chemical structure of most commonly used organic precursors of metal oxides. (a) Zinc acetate dihydrate; (b) aluminum acetate dibasic; (c) indium acetate hydrate; (d) galium acetyl acetonate; (e) tin acetate.

140 Design, Simulation and Construction of Field Effect Transistors

From the considerations abovementioned concerning the organic precursor degradation temperature, it is of extreme importance to know in advance the physical chemical properties of the precursor salt. **Figure 4a** shows the Fourier-transform infrared spectra (FTIR) in attenuated reflectance mode (ATR) of zinc acetate dihydrate films treated at different temperatures, from 150 to 400°C. Peak (1) at 3377 cm−1 is from the asymmetric stretching mode of hydroxyl groups, whereas peaks (2) and (3) are from the stretching modes of the precursor ester groups (C=O and C—O, respectively). Peaks (4) and (5) are bending modes associated with the CH<sup>3</sup>

much more uniform and better quality films than the produced by spin coating.

groups and peaks (6) and (7) are due to bending modes of C=C bonds and COO−

respectively. Peaks (8) and (9) correspond to Zn—OH and Zn—O stretching modes. One observes that the peaks associated to the organic phase of zinc acetate [10] gradually disappear by increasing the temperature, remaining only species associated with the inorganic phase (Zn—O) for temperatures above 400°C. Thermogravimetric analysis (**Figure 4b**) shows two main mass loss peaks, one around 100°C, due to loss of adsorbed water and water of crystallization and another around 290°C, due to the thermal degradation of the organic phase

groups,

Another interesting approach to obtain thin-film devices from solution is by the use of metal oxide nanoparticles which can be dispersed in water or organic solvents [5–7, 13]. The used nanoparticles are usually obtained by known inorganic synthesis methods and some options are commercially available. These nanoparticles can be used in the form of colloidal suspensions (which often need stabilizers to remain stable) to permit solution processing. The great advantage to use oxide nanoparticles is that the semiconducting phase is already present in the colloidal suspensions and deposition can be carried out at room temperature, without the need of further thermal treatment. This feature is important for the use of flexible substrates, which do not stand temperatures higher than 200°C. However, oxide nanoparticles suspensions usually give rise to lower quality films, with high roughness and large grain boundaries that are deleterious to the film electrical properties. Future improvements in the quality of films produced from oxide nanoparticles suspensions might improve device performance and make this alternative more interesting than processes involving the pyrolysis of organic precursor materials.

#### **2.3. Thin-film transistors**

Thin-film transistors are electronic devices in which all the active layers (semiconductor, electrodes and dielectric layer) are deposited as thin-films onto a supporting (non-active) substrate. The main role of the substrate in a TFT is to give mechanical support to the device structure and it does not interfere on the electrical characteristics of the transistor. The main use of this type of structure is as an electronic switch, having the current between two electrodes (drain and source) controlled (or modulated) by the voltage applied to a gate electrode which is separated from the drain and source electrodes by a highly insulating dielectric layer. Ideally, the current through the gate electrode (*I g* ) should be extremely small and could be neglected when compared to the current between the drain and source electrodes (*I DS*), which can vary several orders of magnitude by varying the gate voltage (*Vg* ). The drain-source current flows in the plane of the film direction, perpendicularly to the applied gate voltage, and is also dependent on the applied drain-source voltage (*VDS*). Drain and source electrodes are usually formed by two long parallel metal stripes separated by a distance *L* known as *channel length*. The overlapping distance of the drain and source electrodes in the plane of the film is defined as the *channel width*, *w*.

From the point of view of the structure, TFTs can be constructed in diverse ways, with four basic distinct structures as depicted in **Figure 5**. The difference among these structures is the position of the electrodes relative to the active semiconducting layer. In a top-gate, bottom-contact (TGBC) configuration (**Figure 5a**) the gate electrode is the uppermost layer, on top of the dielectric layer, and the drain and source electrodes are the lowermost layers, being underneath the semiconducting layer. In this structure, drain and source electrodes can be deposited by lift-off photolithography or shadow mask thermal evaporation directly onto the substrate. Another characteristic of this structure is that the insulating layer must be deposited onto the semiconducting layer, a condition which cannot be achieved, depending on the deposition method of the dielectric material. Top-gate, top-contact (TGTC) configuration (**Figure 5b**) is similar to TGBC configuration with the difference that the drain and source electrodes are deposited onto the semiconducting layer. This configuration has also the same limitations concerning the dielectric layer deposition as the TGBC. Bottom-gate configurations (**Figure 5c** and **d**) are interesting from the point of view that they have three common stages (substrate, gate electrode and dielectric layer) and are very convenient when only the semiconducting active layer is changed (particularly for bottom-gate, bottom-contact, BGBC). However, bottom gate structures are not appropriate for use when the dielectric layer does not support temperatures higher than the deposition temperature of the semiconducting layer or does not resist to the solvent used to deposit the active layer.

source electrode), increasing the channel conductance (accumulation regime). The higher the positive gate bias, the more conductive becomes the transistor channel. However, for a negative gate bias, free electrons are repelled from the semiconductor/dielectric interface, decreasing the density of free charge carriers in the transistor channel (depletion regime) and, consequently, reducing the

**Figure 5.** Most common electrode configuration for thin-film transistors: (a) top-gate, bottom-contact; (b) top-gate, top-

charge carriers are holes and the transistor is in the accumulation regime (conductive channel) when a negative bias is applied to the gate electrode and in depletion regime (resistive channel)

ductor/dielectric interface, the channel majority free charge carrier distribution is nearly uniform. As the value of *VDS* increases, the *IDS* starts to deviate from the linear behavior (toward a sublinear behavior) since the charge near the drain electrode is reduced by the semiconductor potential. At a certain drain-source voltage, the accumulated charge next to the drain electrode is reduced near to zero, forming what is called the *pinch-off* point, which moves toward the source electrode as *VDS* continues to increase. However, the voltage at the pinch-off point remains nearly constant. Therefore, the amount of charge that arrives at the pinch-off point remains the same (as well as the channel current) when a voltage beyond the formation of the pinch-off point (*Vsat*) is applied, despite the reduction on the effective channel length.

*DS* on *VDS*, for low values of *VDS*, is approximately linear, since, for a fixed

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143

much higher than *VDS* and in the absence of fixed charged defects at the semicon-

is almost negligible

. For a p-type semiconductor, the majority free

channel conductance. As a consequence, the channel current for a negative *Vg*

when compared to the current for a positive *Vg*

contact; (c) bottom-gate, top-contact and (d) bottom-gate, bottom-contact.

when a positive bias is applied to the gate electrode.

The dependence of *I*

value of *Vg*

Thin-film transistors have the electrical performance evaluated mainly by two characteristic current–voltage curves, namely, the *output* and the *transfer* curves. The output curve is defined by the drain-source current (*I DS*) versus the drain-source voltage (*VDS*) at different constant values of the gate voltage (*Vg* ), whereas the transfer curve is obtained by measuring *I DS versus V<sup>g</sup>* at different constant values of *VDS*. In a TFT configuration, the channel conductance (between drain and source electrodes) depends on the amount of free charge carriers present in the transistor channel, which can be controlled by the application of a bias voltage at the gate electrode.

If the semiconducting material is n-type, free electrons are accumulated next to the semiconductor/dielectric interface when a positive voltage is applied at the gate electrode (respective to the Electrical Characterization of Thin-Film Transistors Based on Solution-Processed Metal Oxides http://dx.doi.org/10.5772/intechopen.78221 143

**2.3. Thin-film transistors**

through the gate electrode (*I*

by the drain-source current (*I*

ues of the gate voltage (*Vg*

*g*

of magnitude by varying the gate voltage (*Vg*

142 Design, Simulation and Construction of Field Effect Transistors

pared to the current between the drain and source electrodes (*I*

Thin-film transistors are electronic devices in which all the active layers (semiconductor, electrodes and dielectric layer) are deposited as thin-films onto a supporting (non-active) substrate. The main role of the substrate in a TFT is to give mechanical support to the device structure and it does not interfere on the electrical characteristics of the transistor. The main use of this type of structure is as an electronic switch, having the current between two electrodes (drain and source) controlled (or modulated) by the voltage applied to a gate electrode which is separated from the drain and source electrodes by a highly insulating dielectric layer. Ideally, the current

film direction, perpendicularly to the applied gate voltage, and is also dependent on the applied drain-source voltage (*VDS*). Drain and source electrodes are usually formed by two long parallel metal stripes separated by a distance *L* known as *channel length*. The overlapping distance of the

From the point of view of the structure, TFTs can be constructed in diverse ways, with four basic distinct structures as depicted in **Figure 5**. The difference among these structures is the position of the electrodes relative to the active semiconducting layer. In a top-gate, bottom-contact (TGBC) configuration (**Figure 5a**) the gate electrode is the uppermost layer, on top of the dielectric layer, and the drain and source electrodes are the lowermost layers, being underneath the semiconducting layer. In this structure, drain and source electrodes can be deposited by lift-off photolithography or shadow mask thermal evaporation directly onto the substrate. Another characteristic of this structure is that the insulating layer must be deposited onto the semiconducting layer, a condition which cannot be achieved, depending on the deposition method of the dielectric material. Top-gate, top-contact (TGTC) configuration (**Figure 5b**) is similar to TGBC configuration with the difference that the drain and source electrodes are deposited onto the semiconducting layer. This configuration has also the same limitations concerning the dielectric layer deposition as the TGBC. Bottom-gate configurations (**Figure 5c** and **d**) are interesting from the point of view that they have three common stages (substrate, gate electrode and dielectric layer) and are very convenient when only the semiconducting active layer is changed (particularly for bottom-gate, bottom-contact, BGBC). However, bottom gate structures are not appropriate for use when the dielectric layer does not support temperatures higher than the deposition temperature of the

drain and source electrodes in the plane of the film is defined as the *channel width*, *w*.

semiconducting layer or does not resist to the solvent used to deposit the active layer.

Thin-film transistors have the electrical performance evaluated mainly by two characteristic current–voltage curves, namely, the *output* and the *transfer* curves. The output curve is defined

at different constant values of *VDS*. In a TFT configuration, the channel conductance (between drain and source electrodes) depends on the amount of free charge carriers present in the transistor channel, which can be controlled by the application of a bias voltage at the gate electrode. If the semiconducting material is n-type, free electrons are accumulated next to the semiconductor/dielectric interface when a positive voltage is applied at the gate electrode (respective to the

*DS*) versus the drain-source voltage (*VDS*) at different constant val-

*DS versus V<sup>g</sup>*

), whereas the transfer curve is obtained by measuring *I*

) should be extremely small and could be neglected when com-

). The drain-source current flows in the plane of the

*DS*), which can vary several orders

**Figure 5.** Most common electrode configuration for thin-film transistors: (a) top-gate, bottom-contact; (b) top-gate, topcontact; (c) bottom-gate, top-contact and (d) bottom-gate, bottom-contact.

source electrode), increasing the channel conductance (accumulation regime). The higher the positive gate bias, the more conductive becomes the transistor channel. However, for a negative gate bias, free electrons are repelled from the semiconductor/dielectric interface, decreasing the density of free charge carriers in the transistor channel (depletion regime) and, consequently, reducing the channel conductance. As a consequence, the channel current for a negative *Vg* is almost negligible when compared to the current for a positive *Vg* . For a p-type semiconductor, the majority free charge carriers are holes and the transistor is in the accumulation regime (conductive channel) when a negative bias is applied to the gate electrode and in depletion regime (resistive channel) when a positive bias is applied to the gate electrode.

The dependence of *I DS* on *VDS*, for low values of *VDS*, is approximately linear, since, for a fixed value of *Vg* much higher than *VDS* and in the absence of fixed charged defects at the semiconductor/dielectric interface, the channel majority free charge carrier distribution is nearly uniform. As the value of *VDS* increases, the *IDS* starts to deviate from the linear behavior (toward a sublinear behavior) since the charge near the drain electrode is reduced by the semiconductor potential. At a certain drain-source voltage, the accumulated charge next to the drain electrode is reduced near to zero, forming what is called the *pinch-off* point, which moves toward the source electrode as *VDS* continues to increase. However, the voltage at the pinch-off point remains nearly constant. Therefore, the amount of charge that arrives at the pinch-off point remains the same (as well as the channel current) when a voltage beyond the formation of the pinch-off point (*Vsat*) is applied, despite the reduction on the effective channel length.

**Figure 6.** Characteristic curves of TFTs (a) output curves with characteristic linear and saturation regions; (b) transfer curve and I1/2 versus vg (linear scale) extrapolation of Vth and slope for saturation mobility determination;.

This means that, for *VDS* higher than *Vsat*, the channel current achieves a saturation regime, as observed in the output curves of **Figure 6a**.

The drain-source current in the linear regime can be approximated by [41, 42]:

$$I\_{\rm DS,\\_thu} = \frac{w\mu \, \mathcal{C}\_m}{L} \left( V\_g - V\_{th} - \frac{V\_{\rm DS}}{2} \right) V\_{\rm DS} \quad \text{for } V\_{\rm DS} \ll \, \left( V\_g - V\_{th} \right) \tag{1}$$

Considering that TFTs can be used as electronic switches, other electrical parameters concerning the switching capacity are also used to evaluate the transistor performance: (1) the *on/off ratio*

*on/Ioff*); (2) the onset voltage (*Von*) and (3) the subthreshold swing (SS). The on/off ratio, which extraction method is shown in the transfer curve of **Figure 6b**, represents the ratio between the channel currents when the transistor is in the conduction mode (*Ion*) and when it is switched

*on/Ioff* should be the highest as possible. Typical good values for on/off ratio are above 10<sup>5</sup>

**Figure 6b**. The subthreshold voltage (which is measured in volts/decade) is defined by:

The onset voltage is defined as the gate voltage necessary for the transistor switch from the "off state" to the "on state" and can be directly determined from the transfer curve as shown in

> <sup>∂</sup> *<sup>V</sup>* \_\_\_\_\_\_\_ *<sup>g</sup>* ∂log(*I DS*)] *min*

and can also be determined from the transfer curve data. It gives the information on how much gate voltage in needed to make the drain-source current increase by a factor of 10. Thus,

In the present section, we compare the results from the electrical characterization of ZnO TFTs with the active deposited by spray-pyrolysis and by spin-coating, annealed at different temperatures (300 and 500°C) after deposition. **Figure 7a–d** shows the output curves of the produced devices. Substrates are p-type (Boron) doped Si wafers with a thermally grown

 insulating layer (100 nm thick) used in a bottom-gate structure. Aluminum top drain and source electrodes were deposited on top of the ZnO layer, with a channel width of 5 mm and

bottom layer than spin-coating).

) and also saturation mobility values almost

The output curves show that spray-coated devices present better transistor characteristics compared to spin-coated transistors. Operating currents of spray-coated devices are considerably higher (more than 7 times for devices annealed at 300 oC and more than 13 times for devices annealed at 500 oC) than the operating currents observed for devices produced by spin-coating. Moreover, spin-coated devices have much higher off currents (for *Vg* = 0 V), probably due to higher lateral leakage current (spin-coated films cover the whole substrate area whereas spray-coated films can be deposited selectively in a smaller active area) and/or higher leakage current through the gate dielectric (due to Leidenfrost effect, spray-pyrolysis

The transfer curves (**Figure 7e** and **f**) also show strong dependence on deposition method and annealing temperature. Spray-coated devices, as expected from the output curves, present

10 times higher than spin-coated TFTs. Subthreshold swing (SS) values of spray-coated TFTs are smaller and do not present significant variation on annealing temperature as observed for spin-coating. Improved device characteristics of spray-coated devices can be explained by better film quality and crystallinity, which promotes less charge trapping and scattering. The temperature influence on the transfer curves for devices produced by the same deposition method indicates that at higher temperatures the semiconductor intrinsic conductivity increases due to more efficient elimination of organic residues and better film crystallinity.

against 10<sup>3</sup>

*off* value is minimal (to avoid power consumption when not operating),

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–106 . 145

(5)

(*I*

off (*I*

SiO<sup>2</sup>

*I*

*off*). Since the ideal *I*

*SS* <sup>=</sup> [

a channel length of 100 μm (*w/L* ratio of 50).

deposition promote less cracks in the insulating SiO<sup>2</sup>

much higher on/off ratios (about 10<sup>6</sup>

*2.3.1. Solution-processed ZnO TFTs*

the lowest this value, the better is the transistor performance.

where *μ* is the charge carrier mobility, *Cox* is the capacitance per unit area of gate dielectric layer (*Cox = C/A = kε<sup>0</sup> /d*, with *ε<sup>0</sup>* the vacuum electric permittivity, *k*, the dielectric constant of the insulating layer and *d*, its thickness) and *Vth* is the *threshold voltage*, a voltage associated to the presence of charged traps at the semiconductor/dielectric interface and the difference of the work function between the semiconductor and the dielectric material, which is necessary to achieve the flat-band condition in the transistor channel. The channel current in the saturation regime, on the other hand, can be given by [41, 42]:

$$I\_{DS,\\_sat} = \frac{w\mu C\_m}{L} \left(V\_g - V\_{th}\right)^2 \quad for \; V\_{DS} \gg \quad (V\_g - V\_{th})\tag{2}$$

Eq. (2) means that the square root of the channel current depends linearly on the gate voltage. Consequently, a plot of *(IDS)1/2* versus *Vg* (curve in blue in **Figure 6b**) may give a straight line which intercepts the abscissa at *Vth* and which slope gives the transistor *transconductance, gm*:

$$\mathcal{g}\_m = \begin{bmatrix} \frac{\partial \sqrt{I\_0}}{\partial \ V\_\varepsilon} \end{bmatrix}\_{V\_{\text{re}} \approx t\varepsilon} \tag{3}$$

Combining with Eq. (2), the carrier mobility in the saturation regime can be calculated:

$$\mu\_{sat} = \frac{2L\left(\frac{\theta \cdot \left|\overline{U\_o}\right|}{\delta \cdot V\_\varepsilon}\right)^2}{w \cdot \overline{C\_m}}\tag{4}$$

Even though the carrier mobility in a TFT can be obtained in different conditions, the saturation regime is very important on the transistor operation, the reason why most of the papers use the saturation mobility as one of the relevant parameters (along with *Vth*) used to evaluate the transistor performance.

Considering that TFTs can be used as electronic switches, other electrical parameters concerning the switching capacity are also used to evaluate the transistor performance: (1) the *on/off ratio* (*I on/Ioff*); (2) the onset voltage (*Von*) and (3) the subthreshold swing (SS). The on/off ratio, which extraction method is shown in the transfer curve of **Figure 6b**, represents the ratio between the channel currents when the transistor is in the conduction mode (*Ion*) and when it is switched off (*I off*). Since the ideal *I off* value is minimal (to avoid power consumption when not operating), *I on/Ioff* should be the highest as possible. Typical good values for on/off ratio are above 10<sup>5</sup> –106 . The onset voltage is defined as the gate voltage necessary for the transistor switch from the "off state" to the "on state" and can be directly determined from the transfer curve as shown in **Figure 6b**. The subthreshold voltage (which is measured in volts/decade) is defined by:

$$SS = \left[\frac{\partial V\_{\varepsilon}}{\partial \log(I\_{\varepsilon \diamond})}\right]\_{\min} \tag{5}$$

and can also be determined from the transfer curve data. It gives the information on how much gate voltage in needed to make the drain-source current increase by a factor of 10. Thus, the lowest this value, the better is the transistor performance.
