**2.1. Material growth and characterization of Ge0.83Sn0.17 substrate**

The high quality Ge0.83Sn0.17 sample was grown using molecular beam epitaxy (MBE). 4-inch (001)-oriented Ge wafers with n-type doping concentration of 5 × 1016 cm−3 were used as the starting substrates. After the cyclic cleaning of Ge substrates using dilute hydrofluoric acid (DHF) (HF:H<sup>2</sup> O = 1:50) and deionized (DI) water, the unintentionally p-type doped Ge0.83Sn0.17 film was grown on the Ge substrate using the solid source low temperature MBE system [32, 33]. The growth temperature was set at 100°C. 99.9999% pure Ge and 99.9999% pure Sn were used as Ge and Sn sources, respectively. The growth chamber has a base pressure of 3 × 10−10 Torr. Ge0.83Sn0.17 film with the thickness of 10 nm was grown on the Ge substrates. **Figure 1** shows the 5 × 5 μm AFM scan of the as-grown Ge0.83Sn0.17 surface. The surface is very smooth with a root-mean-square (RMS) roughness as small as 0.198 nm. High-resolution transmission electron microscopy (HRTEM) was employed to analyze the crystalline quality of the as-grown Ge0.83Sn0.17 sample. **Figure 2(a)** shows a low magnification cross-sectional TEM (XTEM) image of an as-grown Ge0.83Sn0.17 sample, indicating that the GeSn surface is smooth. The GeSn layer thickness is ~10 nm. The high resolution TEM (HRTEM) image in **Figure 2(b)** shows the smooth Ge0.83Sn0.17 surface. In addition, very clear lattice fringes and defect-free GeSn/Ge interface can be observed, as shown in the HRTEM image of **Figure 2(c)**.

High resolution X-ray diffraction (HRXRD) was also used to analyze the Sn composition and strain property of the as-grown Ge0.83Sn0.17 substrate. **Figure 3(a)** shows the (004) ω-2θ rocking scan of the as-grown sample. Both Ge and GeSn peaks are well-defined. The peak at smaller 2θ value is the GeSn peak. The relative broad full-width-half-maximum (FWHM) is due to the thin GeSn layer thickness (~10 nm). (115) reciprocal space mapping (RSM) of an as-grown Ge0.83Sn0.17/ Ge (001) sample is shown in **Figure 3(b)**. The GeSn film is fully strained to the Ge substrate and the substitutional Sn composition is calculated to be 17% from XRD measurement.

**Figure 4(a)** summarizes the key process steps for fabricating Ge0.83Sn0.17 p-MOSFETs. After the MBE growth of ~10 nm Ge0.83Sn0.17 film on the lightly n-type doped Ge (100) substrate, pre-gate cleaning using DHF (HF:H<sup>2</sup> O = 1:50) and DI water was performed. Two splits were

**Figure 1.** 5 × 5 μm AFM scan of the as-grown Ge0.83Sn0.17 substrate. The GeSn surface is very smooth with a RMS roughness as small as 0.198 nm.

**Figure 2.** (a) Low magnification XTEM image of an as-grown Ge0.83Sn0.17 sample showing the smooth GeSn surface. High magnification XTEM images of the Ge0.83Sn0.17 sample shows (c) the zoom-in view of smooth GeSn surface and (d) defectfree Ge0.83Sn0.17/Ge interface.

introduced: one with 10 minutes sulfur passivation using (NH<sup>4</sup> )2 S solution (24% by weight) at room temperature (25°C) and the other one without sulfur passivation. After that, the samples were loaded into the atomic layer deposition (ALD) chamber immediately to avoid surface oxidation due to air exposure. Surface treatment was done using Trimethylaluminum (TMA) as precursor with pulse duration of 30 ms. This was followed by deposition of 3 nm-thick hafnium dioxide (HfO<sup>2</sup> ) at 250°C using Tetrakis (dimethylamido) hafnium and H<sup>2</sup> O as precursors. The total ALD process duration including the pumping and venting steps is ~ 15 min. After that, 110 nm-thick tantalum nitride (TaN) was deposited using a reactive sputtering system. The metal gate was then patterned by photolithography and etched using chlorine (Cl<sup>2</sup> )-based plasma. A 10 nm-thick nickel (Ni) was then deposited using e-beam evaporator and the self-aligned Ni(GeSn) metallic contact was formed by rapid thermal annealing (RTA) at 250°C for 30 s in the N<sup>2</sup> ambient. Finally, excess Ni was removed by selective wet etch using concentrated sulfuric acid (H<sup>2</sup> SO<sup>4</sup> ) (96% by weight). The maximum processing temperature of

the whole fabrication process was 250°C to limit out-diffusion of Sn to the channel surface or into the gate dielectric. A top-view scanning electron microscopy (SEM) image of a completed Ge0.83Sn0.17 p-MOSFET with a gate length *LG* of 4 μm is shown in **Figure 4(b)**. **Figure 4(c)** shows

**Figure 4.** (a) Process flow for fabricating Ge0.83Sn0.17 channel p-MOSFETs where a sulfur passivation step was introduced

Ge0.83Sn0.17 P-Channel Metal-Oxide-Semiconductor Field-Effect Transistors: Impact of Sulfur…

SEM image showing a completed Ge0.83Sn0.17 p-MOSFET with self-aligned NiGeSn S/D contacts. (c) HRTEM image of a

). The maximum processing temperature is 250°C. (b) Top-view

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The (001) surface of a diamond-structure semiconductor has two dangling bonds per surface atom. GeSn grown on Ge (001) surface has a (001) surface as shown in the atomic structure in **Figure 5(a)** viewed into the [110] direction. One monolayer (ML) of a Group VI element can passivate all the dangling bonds by occupying the bridge site in a (1 × 1) geometry [34, 35]. Sulfur atoms could obtain an ideal (1 × 1) termination of the bivalent (001) surfaces of silicon and Ge. Although sulfur could desorb from the Si surface at room temperature or diffuse into the Si bulk during heating [36], Weser et al. found that an ordered (1 × 1) structure with one sulfur atom bonded on a bulk-like bridge site could be achieved by introducing elemental sulfur atoms on the Ge (001) surface under ultrahigh vacuum (UHV) condition [34, 35]. The for-

based on various characterization techniques, such as photoelectron spectroscopy [37], ion scattering spectroscopy [38], as well as X-ray standing wave measurements [39]. Similarly, sulfur passivation should also be able to passivate the GeSn (001) surface through the formation of S-Ge and S-Sn covalent bonds which suppress the formation of Ge and Sn oxides at the surface, as illustrated in the atomic schematic shown in **Figure 5(b)**. In this Section, the

)2

S solution has also been reported

a HRTEM image of the transistor along the dash line *A-A'* indicated in **Figure 4(b)**.

Ge0.83Sn0.17 channel p-MOSFET as seen in a cross-section along the dash line *AA*' in (b).

**3. Results and discussion**

**3.1. Sulfur-passivated gate stack study**

prior to the deposition of high-k gate dielectric (HfO<sup>2</sup>

mation of Ge-S-Ge bridge bonds after a treatment in (NH<sup>4</sup>

**Figure 3.** (a) (004) rocking scan of the as-grown sample shows both the Ge0.83Sn0.17 and Ge peaks. The well-defined GeSn peak indicates the good crystalline quality of the GeSn layer. The peak is relatively broader than the Ge peak because of the thin layer thickness of the GeSn layer. (b) (115) RSM showing that the Ge0.83Sn0.17 film is fully strained to the Ge (001) substrate. The substitutional Sn composition is calculated to be 17%. Device fabrication of Ge0.83Sn0.17 p-MOSFETs.

**Figure 4.** (a) Process flow for fabricating Ge0.83Sn0.17 channel p-MOSFETs where a sulfur passivation step was introduced prior to the deposition of high-k gate dielectric (HfO<sup>2</sup> ). The maximum processing temperature is 250°C. (b) Top-view SEM image showing a completed Ge0.83Sn0.17 p-MOSFET with self-aligned NiGeSn S/D contacts. (c) HRTEM image of a Ge0.83Sn0.17 channel p-MOSFET as seen in a cross-section along the dash line *AA*' in (b).

the whole fabrication process was 250°C to limit out-diffusion of Sn to the channel surface or into the gate dielectric. A top-view scanning electron microscopy (SEM) image of a completed Ge0.83Sn0.17 p-MOSFET with a gate length *LG* of 4 μm is shown in **Figure 4(b)**. **Figure 4(c)** shows a HRTEM image of the transistor along the dash line *A-A'* indicated in **Figure 4(b)**.
