**4. Results and discussion**

## **4.1. DC characterization**

carrier temperature, an extended model needs to be used to study the electric properties of deep-submicron FET transistors used in plasma wave THz detection. This extended model is

The HDM [32, 33] includes a carrier energy balance by coupling to the set of DDM equations

*un* <sup>−</sup> *<sup>u</sup>* \_\_\_\_\_<sup>0</sup> *τn* + <sup>∂</sup>(*un <sup>n</sup>*) \_\_\_\_\_

*up* <sup>−</sup> *<sup>u</sup>* \_\_\_\_\_<sup>0</sup> *τp* + <sup>∂</sup>(*up <sup>p</sup>*) \_\_\_\_\_\_

) is the electron (hole) energy relaxation time, un (up) is the electron (hole) thermal

as a function of the Ge molar fraction (x = 0.30) were extracted from [37].

voltage, and the electric field that is self-consistently obtained from the Poisson equation.

Strained-Si MODFET is essentially a majority carrier device; then the hole energy balance equation (Eq. (7)) was disregarded in the model. In this work, a two-dimensional HDM (Eqs. (1)–(6)) was used. It was implemented with Synopsys TCAD [34]. Carrier relaxation times were obtained from uniform-field Monte Carlo simulations [35, 36]. In TCAD simulations, impurity de-ionization, Fermi-Dirac statistics, and mobility degradation due to both longitudinal and transverse electric field were considered. All TCAD simulations were carried out at room temperature.

The geometry and dimensions used in the simulations are the ones shown in **Figure 1(a)**. The doping level of the supply layers was 1019 cm−3 for the upper supply layer and 1.8 × 1018 cm−3 for the lower one. The thicknesses of the virtual substrate and the p-Si wafer were chosen to be 600 and 500 nm, respectively, to economize computer memory. A uniform residual n-type-doping density of 1015 cm−3 was assumed in the non-intentionally doped regions of the transistor. Under both source and drain contacts, highly doped regions were considered to ensure ensure low values of contact resistance for the ohmic contacts of the device. The values of the conduction and valence bands offsets between the strained-Si and the

Low electric field mobility in the channel was modeled using Roldan's model for biaxially strained Si on relaxed SiGe [38], and the maximum value electron mobility in the channel

Static (DC) and THz measurements were carried out at room temperature. On-wafer, DC measurements of drain-to-source current versus drain-to-source and gate-to-source bias voltages were done using a Cascade 11000B probe station and an Agilent B1500A semiconductor parameter analyzer. **Figure 3** shows a photograph with a schematic of the experimental setup used for the terahertz characterization of the strained-Si MODFETs. A solid-state harmonic generator THz source based on a dielectric resonator oscillator (DRO) at 12 GHz and electronic

<sup>∂</sup>*<sup>t</sup>* ) (6)

<sup>∂</sup>*<sup>t</sup>* ) (7)

and the electron and hole energy flow densities that are given as follows:

<sup>→</sup>*Sn* <sup>=</sup> <sup>1</sup>\_\_ *q* →*J <sup>n</sup>* ⋅ *E* <sup>→</sup> − \_\_<sup>3</sup> <sup>2</sup>(*n*

<sup>→</sup>*Sp* <sup>=</sup> \_\_<sup>1</sup> *q* →*J <sup>p</sup>* ⋅ *E* <sup>→</sup> − \_\_<sup>3</sup> <sup>2</sup>(*p*

→ ⋅

→ ⋅

known as the hydrodynamic model (HDM).

58 Design, Simulation and Construction of Field Effect Transistors

∇

∇

where <sup>→</sup> *Sn* ( → *Sp*

relaxed Si1-xGex

was 1600 cm2

**3. THz setup**

/(Vs).

Transfer characteristics of Device 3 are shown in **Figure 4(a)** for two values, 20 and 200 mV, of the drain-to-source voltage (VDS). The three transistors are depletion-mode devices, so a negative bias voltage must be applied to the gate (i.e., a negative gate-to-source voltage) to cut off the c hannel [25, 39]. Transfer characteristics in a log scale show that a total switch-off of the device was not possible, and a constant level of drain current (IDS) persists for a gate bias of −1 V (8 μA for Vds = 20 mV and 80 μA for Vds = 200 mV). As the drain voltage is moderately raised from 20 to 200 mV, the above-described behavior is enhanced, and the sub-threshold current at VGS = -1 V increases when VDS increases. As pointed out earlier, this behavior reveals a moderate control of the channel by the gate electrode due to the double supply layer; in return, this double deck ensures a suitable concentration of the electron plasma in the channel that is of paramount importance to achieve a good performance of the transistor in THz detection.

and obtained from TCAD simulations (<10 V−1) is significantly lower than the theoretical limit (38 V−1), along with the above-discussed behavior of the transconductance, suggesting that further improvements of the transistor performance may be achieved by an optimization of

Room-Temperature Terahertz Detection and Imaging by Using Strained-Silicon MODFETs

http://dx.doi.org/10.5772/intechopen.76290

61

In the second place, the drain conductance that gives the first derivative of the drain current with respect to the drain current was also determined. **Figure 5(b)** shows drain conductance as a function of drain voltage for three different gate voltages (−0.5, −0.6, and −0.7 V). Experimental and TCAD drain conductance curves show an excellent agreement between

A TCAD study of the THz photovoltaic response of the transistor was implemented, as in measurements, grounding the source, biasing the gate, and floating the drain contact while a THz small sinusoidal signal (0.15 or 0.3 THz) was superimposed to the gate voltage as described in [17–19]. As the DC drain voltage setup in the photovoltaic mode must be supported by a net charge in the drain region, in TCAD simulations, a charge boundary condition was implemented at the floating drain contact with a distributed boundary condition over all

nodes of the mesh of the drain electrode. The boundary condition is as follows:

→ ⋅ →

is the electric displacement field, Q is the total net charge, and the integral is evalu-

ated over the entire surface of the drain electrode. Eq. (8) forces the potential on the drain (i.e., the photoresponse of the detector) to be adjusted to produce the correct total charge on the electrode. HDM equations (Eqs. (1)–(6)) were solved in the time domain to obtain the transistor photoresponse. The amplitude of the sinusoidal signal superimposed in the gate contact was fixed to an arbitrary value of 5 mV. Since this value is arbitrary, the magnitude of the THz response obtained in simulations will be presented henceforward as arbitrary magnitude in

In TCAD simulations, it was found that the drain voltage (ΔU) induced by the THz sinusoidal signal exhibits both the same shape (sinusoidal) and the frequency than the AC signal superimposed to the gate bias; this ensures that no frequency conversion takes place in the simulated devices. In addition, it was found that its amplitude is considerably smaller than one of the gate's signal in agreement with the fact that in the THz range the transistor is unable to amplify signals and it is merely working as a THz detector. The mean value of the induced drain voltage by the radiation was negative as predicted by theoretical models [17–19]. The photoresponse obtained in TCAD simulations was extracted by subtracting the value of drain-to-source voltage when the THz signal was applied (Δ*UTHz-on*) from the drain-

*ΔU* = *Δ UTHz*−*off* − *Δ UTHz*−*on* (9)

*dS* = *Q* (8)

the layout of the structure.

measurements and TCAD simulations.

**4.2. THz detection: TCAD versus experimental**

∮*D*

to-source voltage when no signal was applied (Δ*UTHz-off*):

where *D* →

figures.

**Figure 4.** (a) Experimental and simulated transfer characteristics for device 3 for two values of the drain voltage plotted in a log scale and (b) output characteristics for three different values of VGS.

The TCAD simulation model of the transistor was validated through comparison with DC and AC measurements. The agreement between TCAD and experimental results across the whole ranges of gate-to-source and drain-to-source biases studied is excellent as shown in **Figure 4**.

Agreement between measurement and simulation magnitudes involving first derivatives of the drain current was also analyzed. In the first place, the efficiency of the transconductance was analyzed. This magnitude defined as the ratio of transconductance (gm) to drain-tosource DC current (IDS), is a key parameter used to compare the performance of different technologies of transistors. The efficiency of the transconductance is used here, on the one hand, because it clearly shows the operation region of the device and, on the other hand, because the efficiency of the transconductance is linearly dependent on a current derivative and discrepancies between simulation and experimental results are readily revealed. **Figure 5(a)** gives the experimental and calculated efficiency of the transconductance versus the gate voltage (VGS) of the device D3. The maximum value of the efficiency of the transconductance measured

**Figure 5.** (a) Efficiency of the transconductance versus the gate voltage obtained from measurements and numerical TCAD simulations and (b) drain conductance versus drain voltage for three different values of gate bias obtained from measurements and numerical TCAD simulations.

and obtained from TCAD simulations (<10 V−1) is significantly lower than the theoretical limit (38 V−1), along with the above-discussed behavior of the transconductance, suggesting that further improvements of the transistor performance may be achieved by an optimization of the layout of the structure.

In the second place, the drain conductance that gives the first derivative of the drain current with respect to the drain current was also determined. **Figure 5(b)** shows drain conductance as a function of drain voltage for three different gate voltages (−0.5, −0.6, and −0.7 V). Experimental and TCAD drain conductance curves show an excellent agreement between measurements and TCAD simulations.
