Preface

Chapter 8 **Electrical Characterization of Thin-Film Transistors Based on**

João P. Braga, Guilherme R. De Lima, Giovani Gozzi and Lucas

**Solution-Processed Metal Oxides 135**

Fugikawa Santos

**VI** Contents

Field effect transistors (FETs) are the fundamental building blocks of microelectronics. In recent years, research on microelectronics has been specifically focused on the proposition of efficient alternative methodologies and materials to fabricate feasible integrated circuits. This book provides a general background of thin film transistors and their simulations. Re‐ cent developments in the realm of microelectronics are elaborated with evidence. The FET models and various related issues are also carefully described. The contents of the book are broadly classified into two topics: design and simulation of FETs and construction of FETs. The design and simulation of transistors section is elaborated in Chapters 1 to 5. Chapter 1 describes the 14-nm technology node to model nanosized transistors. Chapter 2 gives a brief account of the existing works on FET-based biosensors, the principle of dielectric modula‐ tion in tunnel field effect transistors (TFETs), and TFET simulations using technology com‐ puter-aided design (TCAD). Also, a circular gate TFET is presented as a dielectricmodulated biosensor and its practical implications are explained. Chapter 3 presents TFET bandgap modulation, which is supported by simulation results. The different TFET electri‐ cal parameters are also propounded in Chapter 3 using TCAD simulations. Chapter 4 re‐ ports an experimental and theoretical study of Schottky-gated strained-Si modulationdoped field-effect transistors (MODFETs) with different sub-micron gate lengths of 100, 250, and 500 nm. This chapter also elaborates the performance of strained-Si MODFETs at room temperature detection of 0.15 and 0.3 THz via TCAD simulations . Chapter 5 demystifies the role of clamping force on insulated gated bipolar transistors.

The construction of transistors is explained in Chapters 6 to 8. Chapter 6 demonstrates the effect of sulfur passivation on the surface of Ge0.83Sn0.17 for p-channel metal-oxide-semicon‐ ductor field-effect transistors (p-MOSFETs). In addition, it also explains the growth condi‐ tions, characterization, and construction parameters of p-MOSFETs. Chapter 7 provides a short review of THz modulators and graphene FETs. The device structure, its construction, and the experimental observation of modulation characteristics of graphene FET-based THz modulators are also probed in detail for both rigid and flexible devices. Chapter 8 gives a brief introduction to TFTs based on transparent semiconducting metal oxides (SMOs) with special focus on solution-processed devices. It also explains the electrical properties of TFTs with the different active layer compositions such as intrinsic zinc oxide (ZnO), aluminumdoped ZnO, and indium-doped ZnO.

All the authors anticipate that the provided chapters will act as a single source of reference for the design, simulation, and construction of FETs. We are deeply grateful to all the authors for their great efforts and outstanding input in writing these chapters. We honestly hope that this book will be a guide to young researchers who are interested in researching FETs in the near future. We believe that the book will be a great addition to semiconductor physics.

> **Dhanasekaran Vikraman and Hyun-Seok Kim** Division of Electronics and Electrical Engineering Dongguk University-Seoul, South Korea

**Section 1**

**Design and Simulation of FETs**

**Section 1**

**Design and Simulation of FETs**

**Chapter 1**

Provisional chapter

**Modeling of Nano-Transistor Using 14-Nm Technology**

DOI: 10.5772/intechopen.76965

Latest process technologies in transistor development demonstrate massive changes in the size of transistor chip. In this chapter, a 14-nm technology node is used to model nanosize transistor. The 14-nm technology node consists of multiple numbers of carbon nanotube. Carbon nanotube is a very good energy efficient and low-cost material. Carbon nanotube demonstrates excellent characteristics in metallic and semiconducting characteristics by analyzing electrical properties. At first, the nanotube device physics and material properties are briefly explained in this chapter. Further, a nanotube device is designed for semiconducting properties. The gate length of nanotube is 14 nm which is placed on the gate channel. Finally, the model of 14-nm nano-transistor will be demonstrated for low-

energy consumption which can be considered as a better replacement of CMOS.

Keywords: nano-transistor, 14 nm, electrical properties, I-V characteristics, low energy

Nanoelectronics research is upgrading due to the increases of consumer demand of electronics device in small scale. Nanotechnology research area encourages the researchers to work on nanomaterials as an immerging technology for future. Carbon nanotube (CNT) is a potential material in the field on nanotechnology that has the ability to overcome almost all the limitations of other nanomaterials for its excellent electrical and mechanical properties. Therefore, one of the potential uses of CNT is to place as gate channel of a FET is called carbon nanotube field effect transistor (CNTFET). Silicon-based circuit is moving towards its physical limitation point according to the proven experiment [1]. Due to similar ballistic transport and high career portability of silicon material, CNTFET can be a good replacement of silicon [2] while CNT can

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

Modeling of Nano-Transistor Using 14-Nm Technology

**Node**

Node

Soheli Farhana

Abstract

1. Introduction

Soheli Farhana

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76965

#### **Modeling of Nano-Transistor Using 14-Nm Technology Node** Modeling of Nano-Transistor Using 14-Nm Technology Node

DOI: 10.5772/intechopen.76965

#### Soheli Farhana Soheli Farhana

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76965

### Abstract

Latest process technologies in transistor development demonstrate massive changes in the size of transistor chip. In this chapter, a 14-nm technology node is used to model nanosize transistor. The 14-nm technology node consists of multiple numbers of carbon nanotube. Carbon nanotube is a very good energy efficient and low-cost material. Carbon nanotube demonstrates excellent characteristics in metallic and semiconducting characteristics by analyzing electrical properties. At first, the nanotube device physics and material properties are briefly explained in this chapter. Further, a nanotube device is designed for semiconducting properties. The gate length of nanotube is 14 nm which is placed on the gate channel. Finally, the model of 14-nm nano-transistor will be demonstrated for lowenergy consumption which can be considered as a better replacement of CMOS.

Keywords: nano-transistor, 14 nm, electrical properties, I-V characteristics, low energy
