**Meet the editor**

Dr. Yogesh Sharma was born in Amritsar, India, in 1983. He received his MSc degree in Physics from the Punjab University, Chandigarh, India, in 2004. Following this, he worked as a lecturer for 3 years in a college and taught graduate-level mathematics and physics courses. Later, he moved to the USA to pursue his PhD degree. He started his integrated PhD program at the Auburn University,

AL, USA, in wide bandgap semiconductors, SiC and GaN. He completed his PhD degree in 2012 and ever since has been working in wide bandgap semiconductor technology. He has authored/coauthored over 50 journal/ conference papers. He is the holder of one patent and is a reviewer of various international journals. He is a member of IEEE and IET.

Contents

**Preface VII**

Yogesh K. Sharma

Marina Antoniou

Anup Bhalla

Yaqi Wang

Chapter 6 **GaN-Based Schottky Diode 103**

**Power Semiconductors 17**

Fan Li and Mike Jennings

**Semiconductor Modules 65**

Chapter 5 **Status of SiC Products and Technology 85**

**Nitride Power Transistors 123** Cai Qingwei Aaron and Siek Liter

Chapter 1 **Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era in Power Industry 1**

Neophytos Lophitis, Anastasios Arvanitopoulos, Samuel Perkins and

Chapter 2 **TCAD Device Modelling and Simulation of Wide Bandgap**

Chapter 3 **Main Differences in Processing Si and SiC Devices 45**

Chapter 4 **High-Performance Packaging Technology for Wide Bandgap**

Chapter 7 **Inductive Power Transfer for Electric Vehicles Using Gallium**

Paul Mumby-Croft, Daohui Li, Xiaoping Dai and Guoyou Liu

## Contents

#### **Preface XI**



Preface

ized in the following manner.

Devices fabricated from wide bandgap semiconductors such as SiC and GaN are considered to be a third generation of semiconductor devices. These devices will change the power in‐ dustry significantly in the near future. High-electric field of breakdown, low-intrinsic carrier concentration, and high-bandgap mean that the devices fabricated from these materials can outperform their Si counterparts in high-power regimes and hence enable engineers and re‐ searchers to build more efficient electrical systems. At present time, more efficient electrical systems are necessary to limit the amount of CO2 emissions and make the planet greener. In this book, we try to cover the main aspect of SiC and GaN technologies. The book is organ‐

The introductory chapter deals with the basics of power devices and explains why it is advan‐ tageous to use SiC devices in power electronics. The use of SiC devices in hybrid SiC technolo‐ gy is demonstrated, and the issues related to it are addressed. Challenges such as the quality of the oxide-SiC interface and ohmic contacts on SiC are also discussed briefly in this chapter. The second chapter covers an in-depth analysis of the main differences of, while developing the simulation platforms for, these technologies using technology computer-aided design (TCAD) tools. Most of the tools that have been established are more suitable for Si technology, so special attention is needed while using them to develop wide bandgap semiconductor de‐ vices. The third chapter highlights the processing aspects of SiC devices. This chapter ad‐ dresses the questions such as why SiC devices need a special set of expertise and tools for fabrication and why they are more expensive, and so on, as compared to their Si counterparts. The fourth chapter focuses on the development of packaging technology for power semicon‐ ductor devices. Packaging technology such as Ag sintering, copper wire bonding, and wire bond-free and planar modules with low inductance is discussed in this chapter. In Chapter 5, the current stage of SiC devices is summarized. The evolution of SiC devices, including differ‐ ent types, and market response to these devices is discussed. Also, this chapter addresses

some practical challenges, which engineers have to face while using these devices.

gate injection transistor (git) in inductive power transfer (ipt) for electric vehicles.

The last two chapters deal with GaN technology. Chapter 6 reviews the state-of-the-art GaN Schottky diode technology. This chapter covers the background of GaN-based Schottky di‐ odes, current transportation theory, Schottky material selection, contact quality, and thermal stability of Schottky contact to GaN. This chapter also discusses the evolution of epitaxial and device structures of the GaN-based lateral, quasi-vertical, and vertical Schottky diodes as well as AlGaN/GaN field effect Schottky diodes. Also, this chapter gives a viewpoint on the forth‐ coming development of GaN-based Schottky diodes. The last chapter, Chapter 7, deals with the application of GaN devices in electric vehicles (EVs). It presents the application of the GaN

## Preface

Devices fabricated from wide bandgap semiconductors such as SiC and GaN are considered to be a third generation of semiconductor devices. These devices will change the power in‐ dustry significantly in the near future. High-electric field of breakdown, low-intrinsic carrier concentration, and high-bandgap mean that the devices fabricated from these materials can outperform their Si counterparts in high-power regimes and hence enable engineers and re‐ searchers to build more efficient electrical systems. At present time, more efficient electrical systems are necessary to limit the amount of CO2 emissions and make the planet greener. In this book, we try to cover the main aspect of SiC and GaN technologies. The book is organ‐ ized in the following manner.

The introductory chapter deals with the basics of power devices and explains why it is advan‐ tageous to use SiC devices in power electronics. The use of SiC devices in hybrid SiC technolo‐ gy is demonstrated, and the issues related to it are addressed. Challenges such as the quality of the oxide-SiC interface and ohmic contacts on SiC are also discussed briefly in this chapter. The second chapter covers an in-depth analysis of the main differences of, while developing the simulation platforms for, these technologies using technology computer-aided design (TCAD) tools. Most of the tools that have been established are more suitable for Si technology, so special attention is needed while using them to develop wide bandgap semiconductor de‐ vices. The third chapter highlights the processing aspects of SiC devices. This chapter ad‐ dresses the questions such as why SiC devices need a special set of expertise and tools for fabrication and why they are more expensive, and so on, as compared to their Si counterparts. The fourth chapter focuses on the development of packaging technology for power semicon‐ ductor devices. Packaging technology such as Ag sintering, copper wire bonding, and wire bond-free and planar modules with low inductance is discussed in this chapter. In Chapter 5, the current stage of SiC devices is summarized. The evolution of SiC devices, including differ‐ ent types, and market response to these devices is discussed. Also, this chapter addresses some practical challenges, which engineers have to face while using these devices.

The last two chapters deal with GaN technology. Chapter 6 reviews the state-of-the-art GaN Schottky diode technology. This chapter covers the background of GaN-based Schottky di‐ odes, current transportation theory, Schottky material selection, contact quality, and thermal stability of Schottky contact to GaN. This chapter also discusses the evolution of epitaxial and device structures of the GaN-based lateral, quasi-vertical, and vertical Schottky diodes as well as AlGaN/GaN field effect Schottky diodes. Also, this chapter gives a viewpoint on the forth‐ coming development of GaN-based Schottky diodes. The last chapter, Chapter 7, deals with the application of GaN devices in electric vehicles (EVs). It presents the application of the GaN gate injection transistor (git) in inductive power transfer (ipt) for electric vehicles.

The chapters in this book have been contributed by the respected researchers and technolo‐ gy experts and cover up-to-date developments in wide bandgap semiconductor technology. I hope that graduate students, researchers, engineers, and technology experts who have been working in the exciting field of SiC and GaN power devices will find this book useful.

I would like to thank all the contributors for their hard work and support during this project. Special thanks go to Ms. Dajana Pemac of IntechOpen for her assistance and guid‐ ance during the writing of this book.

My greatest acknowledgement goes to my father (Jagdish Ram Sharma) and mother (Kusum Sharma) who have taught me to be a good person and respect all. I would like to thank my brother (Munish Sharma) and sister (Monika Sharma) from whom I have learned a lot throughout the life. Special thanks go to my beloved wife (Vasudha Dewan) and daughter (Ayana Sharma) for their love and patience during this work. Without my wife's encourage‐ ment, I would not have had started working on this project.

> **Yogesh Kumar Sharma** R&D Centre: Semiconductors Dynex Semiconductor Ltd. Lincoln, United Kingdom

**Chapter 1**

**Provisional chapter**

**Introductory Chapter: Need of SiC Devices in Power**

**Introductory Chapter: Need of SiC Devices in Power** 

Yogesh K. Sharma

Yogesh K. Sharma

**1. Introduction**

oxide, SiO<sup>2</sup>

900°

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.79487

**1.1. Development in device technology**

**Electronics - A Beginning of New Era in Power Industry**

Germanium (Ge) was used as a material to manufacture the first semiconductor device. Ge was touted as the semiconductor material of the future. But after the arrival of silicon (Si), it turned out to be more suitable for several reasons [1–4]. The main reason is to get the highpurity Si from silica, which is widely available. Also, it is easy to modify Si into n-type, p-type, and semi-insulating materials [5]. In addition to this, Si can easily be converted into its native

, with the help of thermal oxidation at the relatively low temperature of around

C [6–8]. These features make Si, as a material, semiconductor industry favorite. Global semiconductor industry, and currently, is worth more than \$430 billion [9]. Around 9–10% of this worth is in smart-integrated circuits and electronic power devices [10, 11]. These power devices processed more than 50% of our electricity [12, 13]. It has been reported that by 2025, Power Electronics market size will be worth \$39.22 billion [9]. As we can envision, power devices have a larger impact on the economy of any country. Power semiconductor devices

In power systems, diodes (uncontrolled switch) and transistors (controlled switch) play a major role. A small increase in their efficiency and power-handling capability make the systems more powerful and energy efficient. In the early 1950s, the advent of solid-state devices like bipolar transistors led to the phasing-out of vacuum tubes [13, 14]. These Si devices created the second wave of electronic revolution possible, with Si as the material of choice. Power devices had played a vital role in electronics industry. There is a rich history about the evolution of power devices. Initially, there were only bipolar devices with a blocking capability of 500 V (or so) and high-current capabilities. But after sometime, in the 1970s, International

are crucial to determine the cost and efficiency of electronic systems.

**Electronics - A Beginning of New Era in Power Industry**

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

DOI: 10.5772/intechopen.79487

#### **Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era in Power Industry Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era in Power Industry**

DOI: 10.5772/intechopen.79487

Yogesh K. Sharma Yogesh K. Sharma

The chapters in this book have been contributed by the respected researchers and technolo‐ gy experts and cover up-to-date developments in wide bandgap semiconductor technology. I hope that graduate students, researchers, engineers, and technology experts who have been working in the exciting field of SiC and GaN power devices will find this book useful. I would like to thank all the contributors for their hard work and support during this project. Special thanks go to Ms. Dajana Pemac of IntechOpen for her assistance and guid‐

My greatest acknowledgement goes to my father (Jagdish Ram Sharma) and mother (Kusum Sharma) who have taught me to be a good person and respect all. I would like to thank my brother (Munish Sharma) and sister (Monika Sharma) from whom I have learned a lot throughout the life. Special thanks go to my beloved wife (Vasudha Dewan) and daughter (Ayana Sharma) for their love and patience during this work. Without my wife's encourage‐

> **Yogesh Kumar Sharma** R&D Centre: Semiconductors Dynex Semiconductor Ltd. Lincoln, United Kingdom

ance during the writing of this book.

VIII Preface

ment, I would not have had started working on this project.

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.79487

#### **1. Introduction**

#### **1.1. Development in device technology**

Germanium (Ge) was used as a material to manufacture the first semiconductor device. Ge was touted as the semiconductor material of the future. But after the arrival of silicon (Si), it turned out to be more suitable for several reasons [1–4]. The main reason is to get the highpurity Si from silica, which is widely available. Also, it is easy to modify Si into n-type, p-type, and semi-insulating materials [5]. In addition to this, Si can easily be converted into its native oxide, SiO<sup>2</sup> , with the help of thermal oxidation at the relatively low temperature of around 900° C [6–8]. These features make Si, as a material, semiconductor industry favorite. Global semiconductor industry, and currently, is worth more than \$430 billion [9]. Around 9–10% of this worth is in smart-integrated circuits and electronic power devices [10, 11]. These power devices processed more than 50% of our electricity [12, 13]. It has been reported that by 2025, Power Electronics market size will be worth \$39.22 billion [9]. As we can envision, power devices have a larger impact on the economy of any country. Power semiconductor devices are crucial to determine the cost and efficiency of electronic systems.

In power systems, diodes (uncontrolled switch) and transistors (controlled switch) play a major role. A small increase in their efficiency and power-handling capability make the systems more powerful and energy efficient. In the early 1950s, the advent of solid-state devices like bipolar transistors led to the phasing-out of vacuum tubes [13, 14]. These Si devices created the second wave of electronic revolution possible, with Si as the material of choice. Power devices had played a vital role in electronics industry. There is a rich history about the evolution of power devices. Initially, there were only bipolar devices with a blocking capability of 500 V (or so) and high-current capabilities. But after sometime, in the 1970s, International

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Rectifier Inc. launched the first metal-oxide-field effect transistor (MOSFET) [15]. The idea was to switch to MOSFETs from BJTs in high-power applications. The MOSFET is a unipolar device, meaning there is only one type of carriers (electrons) which participate during conduction and thus has a high switching speed. Another advantage the MOSFET has is a voltage control device and hence it is easy to switch (on-state to off-sate). On the other hand, the BJT is a current control device and as a result not so easy to control. Voltage control instead of current control means that less internal energy loss occurs in a device. Also, with an increasing switching speed, other components of the system like filters (consist of capacitors/inductors) can be reduced in size. Si-MOSFETs could be designed to handle voltages up to 1000 V and in special case (super-junction) to 1200 V [13, 16, 17]. At voltages higher than 1000 V, the on-state losses of silicon MOSFET start increasing drastically and hence no longer able to perform efficiently. The performance predicament between bipolar and MOSFET devices was solved with the invention of an insulated gate bipolar transistor (IGBT). This is a new device structure where the best electrical features of bipolar (BJT) and unipolar (MOSFET) devices were combined together. With this new device structure, it is possible to cover the blocking voltage range from 750 to 6500 V. Like BJTSs, IGBTs are also able to carry high-forward current.

#### **1.2. Diode and transistor**

In power electronics to build electrical systems, we need both a rectifier and a transistor. The features of an ideal rectifier and a transistor are shown in **Figure 1**. For an ideal rectifier, there is no voltage drop in on-state and no current flows in off-state. Hence, there is no power loss during the operation of a rectifier, **Figure 1(a)**. Similarly, in the case of an ideal transistor, there is no power dissipation during commutation from on- to off–states, **Figure 1(b)**. The waveforms of an ideal power switching system are shown in **Figure 2**. But in reality, this is not the case, either with devices or power systems. The characteristics of a real (non-ideal) rectifier/transistor are shown in **Figure 3**, and the corresponding waveforms of a power system are shown in **Figure 4**. The total power loss occurred in a switch (PTotal) and is given by:

$$\mathbf{P}\_{\text{Total}} = \boldsymbol{\Sigma} \mathbf{P} = \mathbf{P}\_{\text{conduction}} + \mathbf{P}\_{\text{on}} + \mathbf{P}\_{\text{off}} = \mathbf{P}\_{\text{tun-on}} + \mathbf{P}\_{\text{un-off}} + \mathbf{P}\_{\text{on}} + \mathbf{P}\_{\text{off}} \tag{1}$$

At high frequencies, the switching power loss dominates, so fast switching power devices are desirable. At low frequencies, on-state power loss dictates, so power devices with a low

**Figure 4.** Switching waveforms in a real (nonideal) power system, (a) Current versus Time and (b) Volatge versus Time.

**Figure 2.** Switching waveforms of an ideal power system, (a) Current versus Time and (b) Volatge versus Time.

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

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3

**Figure 3.** Real (nonideal) current-voltage characteristics of a diode (a) and a transistor (b).

As mentioned previously with the help of an IGBT, it is possible to increase the operating voltage range of a power transistor without compromising its on-state losses. In unipolar devices like Schottky diode (SBD), MOSFET, the blocking capability of the device increases with an increasing drift region thickness. With an increasing thickness, the conduction losses of a device also increase. In a bipolar device, because of conduction modulation (injection of minority carriers (holes mainly) into the n-type drift region), this is not true, and the conduction losses are low despite a thick drift layer. For example, the specific on-resistance (Rpin) of a drift layer (blocking layer) for a unipolar device, n-type Schottky diode', is given by [18].

on-state resistance are vital.

**1.3. Conduction mechanism of a power device**

**Figure 1.** Ideal current-voltage characteristics of a diode (a) and a transistor (b).

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era… http://dx.doi.org/10.5772/intechopen.79487 3

**Figure 2.** Switching waveforms of an ideal power system, (a) Current versus Time and (b) Volatge versus Time.

**Figure 3.** Real (nonideal) current-voltage characteristics of a diode (a) and a transistor (b).

**Figure 4.** Switching waveforms in a real (nonideal) power system, (a) Current versus Time and (b) Volatge versus Time.

At high frequencies, the switching power loss dominates, so fast switching power devices are desirable. At low frequencies, on-state power loss dictates, so power devices with a low on-state resistance are vital.

#### **1.3. Conduction mechanism of a power device**

Rectifier Inc. launched the first metal-oxide-field effect transistor (MOSFET) [15]. The idea was to switch to MOSFETs from BJTs in high-power applications. The MOSFET is a unipolar device, meaning there is only one type of carriers (electrons) which participate during conduction and thus has a high switching speed. Another advantage the MOSFET has is a voltage control device and hence it is easy to switch (on-state to off-sate). On the other hand, the BJT is a current control device and as a result not so easy to control. Voltage control instead of current control means that less internal energy loss occurs in a device. Also, with an increasing switching speed, other components of the system like filters (consist of capacitors/inductors) can be reduced in size. Si-MOSFETs could be designed to handle voltages up to 1000 V and in special case (super-junction) to 1200 V [13, 16, 17]. At voltages higher than 1000 V, the on-state losses of silicon MOSFET start increasing drastically and hence no longer able to perform efficiently. The performance predicament between bipolar and MOSFET devices was solved with the invention of an insulated gate bipolar transistor (IGBT). This is a new device structure where the best electrical features of bipolar (BJT) and unipolar (MOSFET) devices were combined together. With this new device structure, it is possible to cover the blocking voltage range from 750 to 6500 V. Like BJTSs, IGBTs are also able to carry high-forward current.

2 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

In power electronics to build electrical systems, we need both a rectifier and a transistor. The features of an ideal rectifier and a transistor are shown in **Figure 1**. For an ideal rectifier, there is no voltage drop in on-state and no current flows in off-state. Hence, there is no power loss during the operation of a rectifier, **Figure 1(a)**. Similarly, in the case of an ideal transistor, there is no power dissipation during commutation from on- to off–states, **Figure 1(b)**. The waveforms of an ideal power switching system are shown in **Figure 2**. But in reality, this is not the case, either with devices or power systems. The characteristics of a real (non-ideal) rectifier/transistor are shown in **Figure 3**, and the corresponding waveforms of a power system are

shown in **Figure 4**. The total power loss occurred in a switch (PTotal) and is given by:

**Figure 1.** Ideal current-voltage characteristics of a diode (a) and a transistor (b).

PTotal = ΣP = Pconduction + Pon + Poff = Pturn−on + Pturn−off + Pon + Poff (1)

**1.2. Diode and transistor**

As mentioned previously with the help of an IGBT, it is possible to increase the operating voltage range of a power transistor without compromising its on-state losses. In unipolar devices like Schottky diode (SBD), MOSFET, the blocking capability of the device increases with an increasing drift region thickness. With an increasing thickness, the conduction losses of a device also increase. In a bipolar device, because of conduction modulation (injection of minority carriers (holes mainly) into the n-type drift region), this is not true, and the conduction losses are low despite a thick drift layer. For example, the specific on-resistance (Rpin) of a drift layer (blocking layer) for a unipolar device, n-type Schottky diode', is given by [18].

$$\mathbf{R}\_{\rm pin} = \mathbf{T}\_{\rm datt} / \mathbf{qN}\_{\rm datt} \left(\boldsymbol{\mu}\_{\rm n+} \boldsymbol{\mu}\_{\rm p}\right) \tag{2}$$

where Tdrift = thickness of the drift layer; Ndrit = doping concentration of the n drift layer; μn/μp = bulk mobility of electrons/holes in semiconductor.

For an n-type pin diode, the specific on-resistance (Rpin) under high-current density condition is given by

$$\mathbf{R}\_{\rm plan} = \mathbf{T}\_{\rm drift} \langle \mathbf{q}\mu\_n \mathbf{N}\_{\rm drift} + \mathbf{q} \left(\mu\_{n\star} \mu\_p\right) \Delta \mathbf{p} \tag{3}$$

hybrid systems. Also at present, hybrid approach strikes a good balance between cost and efficiency achieved by these modules [24–27]. Also, it is worthwhile to point out that although SiC diodes and MOSFETs are available at 1.7 kV and lower voltages, there is no MOSFET supplier at 3.3 kV. Also, SiC diode technology is more matured and has been around for some time as compared to SiC MOSFETs. SiC diodes were made available commercially in early

**Figure 5.** Output waveforms obtained for hybrid 1.7 kV SiC (a) and Si substrates (b) obtained during the first turn-on of

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

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5

The results of a double-pulse test done on a hybrid substrate, built using 1 GBT and 1 diode (Si or SiC), are shown in **Figure 5**. These substrates are manufactured to conduct only 50A. By executing this test, we can evaluate the transient behavior of both IGBT and diode. In our case, we are interested in SiC Schottky diode's transient behavior and power losses suffered by it. The external gate resistors, Rgon = Rgoff = 6 Ω, and the value of inductance (L) used is 260 μH. The waveforms during the second turn-on of the IGBT are recorded and are shown in **Figure 5**. The input voltage used for the test is around 1050 V. **Figure 5** shows that the peak reverses recovery current overshoot (Irr) increases significantly to 87A, if Si diode is used instead of an SiC diode. The values of Irr for Si and hybrid SiC substrates are listed in **Table 1**. Although the value of Irr is lower for hybrid substrate, some oscillations in the current waveform are observed. The reverse recovery charge, Qrr, is minute (3μC) in the case of SiC diode. This low Qrr can be transformed into a low-energy loss during a switching event. Also, for hybrid SiC substrate, the reverse recovery energy (Erec,) is 1 mJ. The corresponding value for Si substrate is 11 mJ. All these tests are done at 150°C. The test setup used to perform a double-pulse test is shown in **Figure 6**.

In order to build 3.3 kV hybrid SiC substrates, two 1.7 kV, 50 A diodes are packaged in series. Again, the idea of using these diodes is to reduce the overall losses as compared with Si modules. These 3.3 kV modules can be used in wind power, solar energy, and rail-car applications. Like 1.7 kV hybrid modules, new system topologies can be realized with the help of these modules. Because of the limited availability of 3.3 kV SiC diodes, 1.7 kV SiC diodes are used to realize this high-voltage hybrid technology. All the diodes used to build these substrates are

sharing in SiC diodes. This is very crucial for the reliability of these substrates. The waveforms

) so that there is no problem during current

2000s, while the first SiC MSOFET came to the market in 2011 (by CREE).

**2.1. 1700 V Si/SiC hybrid technology**

the IGBT. These devices were tested at 150°C.

**2.2. 3300 V Si/SiC technology**

chosen carefully (e.g., the devices with similar VF

Because of the extra term, q (μn + μp) ∆p, in the pin diode, the specific resistance will be lower as compared to Si Schottky diode. In the case of high injection ∆p > > Ndrift, the resistance will decrease considerably during conduction. Now, in order to get the diode into the blocking mode, minority carriers (corresponding to ∆p) have to be removed from the drift region. These minority carriers in the drift region cause stored charge in the device and hence increase the switching losses. As a result, the operating switching frequency limit for bipolar devices (PIN or BJT) is lower, as compared to unipolar device (SBD or MOSFET). With the help of a wideband semiconductor material like SiC, there is no need to switch to Si IGBT, as we can realize a high-blocking capability (>1200 V) SiC MOSFET without increasing the on-state losses. The specific on-résistance (Ron) of a MOSFET is given by [19, 20].

$$\mathbf{R}\_{\rm on} = \mathbf{4} \,\mathrm{V}\_{\rm blocking}^2 / \mu\_n \,\mathrm{e}\_{\rm S} \,\mathrm{E}\_{\rm critical}^3 \tag{4}$$

where μn = bulk mobility of SiC; εS = permittivity of SiC; E<sup>C</sup> = critical electric field of breakdown for SiC; Vblocking = the desired blocking voltage.

Bulk electron motilities are similar for low-doped Si and SiC (900–1200 cm<sup>2</sup> /Vs) [24]. However, Ecritical SiC <sup>=</sup> <sup>7</sup> Ecritical Si , so that for a given blocking voltage, the specific on-resistance can be a factor of 343 times lower for SiC devices. This is the reason why we need a wide-band gap semiconductor material for power device.

#### **2. Application of SiC devices in hybrid module technology**

There are a plethora of applications where these devices had been used and have shown their positive impact, and many more potential applications are on the horizon [21–23]. Although there are different kinds of SiC devices available, the most interesting ones are Schottky diodes and MOSFETs. These devices can be used to build either full SiC modules or hybrid SiC modules. In a hybrid SiC module, conventional Si diodes are replaced by Schottky diodes while the transistors are still Si IGBTs. With hybrid approach, we can maintain the cost of an electronic system down but the power saving would not be as much as it can be by using full SiC modules. The fabrication of SiC devices is more complicated and costly as compared with Si counterparts. The situation is more compounded for SiC MOSFETs. SiC MOSFETs are not only more expensive than SiC Schottky diodes but also there are only few suppliers who can provide these devices with limited current ratings. As a result, it makes more sense to build Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era… http://dx.doi.org/10.5772/intechopen.79487 5

**Figure 5.** Output waveforms obtained for hybrid 1.7 kV SiC (a) and Si substrates (b) obtained during the first turn-on of the IGBT. These devices were tested at 150°C.

hybrid systems. Also at present, hybrid approach strikes a good balance between cost and efficiency achieved by these modules [24–27]. Also, it is worthwhile to point out that although SiC diodes and MOSFETs are available at 1.7 kV and lower voltages, there is no MOSFET supplier at 3.3 kV. Also, SiC diode technology is more matured and has been around for some time as compared to SiC MOSFETs. SiC diodes were made available commercially in early 2000s, while the first SiC MSOFET came to the market in 2011 (by CREE).

#### **2.1. 1700 V Si/SiC hybrid technology**

Rpin = Tdrift/qNdrift (μn+ μp) (2)

where Tdrift = thickness of the drift layer; Ndrit = doping concentration of the n drift layer; μn/μp =

For an n-type pin diode, the specific on-resistance (Rpin) under high-current density condition

Rpin = Tdrift/qμ<sup>n</sup> Ndrift + q (μn+ μp) ∆p (3)

Because of the extra term, q (μn + μp) ∆p, in the pin diode, the specific resistance will be lower as compared to Si Schottky diode. In the case of high injection ∆p > > Ndrift, the resistance will decrease considerably during conduction. Now, in order to get the diode into the blocking mode, minority carriers (corresponding to ∆p) have to be removed from the drift region. These minority carriers in the drift region cause stored charge in the device and hence increase the switching losses. As a result, the operating switching frequency limit for bipolar devices (PIN or BJT) is lower, as compared to unipolar device (SBD or MOSFET). With the help of a wideband semiconductor material like SiC, there is no need to switch to Si IGBT, as we can realize a high-blocking capability (>1200 V) SiC MOSFET without increasing the on-state losses. The

<sup>2</sup> /μn εS Ecritical

Si , so that for a given blocking voltage, the specific on-resistance can be a factor of

where μn = bulk mobility of SiC; εS = permittivity of SiC; E<sup>C</sup> = critical electric field of break-

343 times lower for SiC devices. This is the reason why we need a wide-band gap semiconduc-

There are a plethora of applications where these devices had been used and have shown their positive impact, and many more potential applications are on the horizon [21–23]. Although there are different kinds of SiC devices available, the most interesting ones are Schottky diodes and MOSFETs. These devices can be used to build either full SiC modules or hybrid SiC modules. In a hybrid SiC module, conventional Si diodes are replaced by Schottky diodes while the transistors are still Si IGBTs. With hybrid approach, we can maintain the cost of an electronic system down but the power saving would not be as much as it can be by using full SiC modules. The fabrication of SiC devices is more complicated and costly as compared with Si counterparts. The situation is more compounded for SiC MOSFETs. SiC MOSFETs are not only more expensive than SiC Schottky diodes but also there are only few suppliers who can provide these devices with limited current ratings. As a result, it makes more sense to build

Bulk electron motilities are similar for low-doped Si and SiC (900–1200 cm<sup>2</sup>

**2. Application of SiC devices in hybrid module technology**

<sup>3</sup> (4)

/Vs) [24]. However,

bulk mobility of electrons/holes in semiconductor.

4 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

specific on-résistance (Ron) of a MOSFET is given by [19, 20].

Ron = 4 Vblocking

down for SiC; Vblocking = the desired blocking voltage.

is given by

Ecritical

SiC <sup>=</sup> <sup>7</sup> Ecritical

tor material for power device.

The results of a double-pulse test done on a hybrid substrate, built using 1 GBT and 1 diode (Si or SiC), are shown in **Figure 5**. These substrates are manufactured to conduct only 50A. By executing this test, we can evaluate the transient behavior of both IGBT and diode. In our case, we are interested in SiC Schottky diode's transient behavior and power losses suffered by it. The external gate resistors, Rgon = Rgoff = 6 Ω, and the value of inductance (L) used is 260 μH. The waveforms during the second turn-on of the IGBT are recorded and are shown in **Figure 5**. The input voltage used for the test is around 1050 V. **Figure 5** shows that the peak reverses recovery current overshoot (Irr) increases significantly to 87A, if Si diode is used instead of an SiC diode. The values of Irr for Si and hybrid SiC substrates are listed in **Table 1**. Although the value of Irr is lower for hybrid substrate, some oscillations in the current waveform are observed. The reverse recovery charge, Qrr, is minute (3μC) in the case of SiC diode. This low Qrr can be transformed into a low-energy loss during a switching event. Also, for hybrid SiC substrate, the reverse recovery energy (Erec,) is 1 mJ. The corresponding value for Si substrate is 11 mJ. All these tests are done at 150°C. The test setup used to perform a double-pulse test is shown in **Figure 6**.

#### **2.2. 3300 V Si/SiC technology**

In order to build 3.3 kV hybrid SiC substrates, two 1.7 kV, 50 A diodes are packaged in series. Again, the idea of using these diodes is to reduce the overall losses as compared with Si modules. These 3.3 kV modules can be used in wind power, solar energy, and rail-car applications. Like 1.7 kV hybrid modules, new system topologies can be realized with the help of these modules. Because of the limited availability of 3.3 kV SiC diodes, 1.7 kV SiC diodes are used to realize this high-voltage hybrid technology. All the diodes used to build these substrates are chosen carefully (e.g., the devices with similar VF ) so that there is no problem during current sharing in SiC diodes. This is very crucial for the reliability of these substrates. The waveforms


**Table 1.** Comparison of various parameters extracted for Si and hybrid 1.7 kVSiC substrates at 150°C from a doublepulse test.

**Figure 6.** The schematic of a double-pulse test bench used to test devices.

during the second turn-on of the IGBT at 150°C are recorded and are shown in **Figure 7**. For a di/dt = 1100 or 1388 A/μs, a reverse recovery current overshoot (Irr) of 128 A is observed for an Si substrate, which is higher than that of a hybrid SiC substrate (65A). The reverse recovery energy loss occurred in a substrate during the transient is Erec, and the values for Erec (Si) and Erec (SiC) are 0.199 and 0.01 J, respectively. This represents a reduction of about 95% for hybrid substrate. Other transient parameters for the substrates, namely Qrr, Eon, and Eoff (J), are also listed in **Table 2**. **Figure 8** shows the picture of a 3.3 kV, 200A hybrid SiC substrate. Again, like 1.7 kV hybrid substrates, 3.3 kV hybrid substrates are prone to electromagnetic interference (EMI), caused by the oscillations observed in the output waveforms.

(>200°C). But at the same time, due to its intrinsic properties, it is difficult to perform any electrical and physical change to the material at temperatures lower than 1000°C. That means in order to fabricate an SiC device, different set of tools are required as compared to Si device world [28–31]. The electrical and physical properties of Si and SiC are listed in **Table 3**.

**Table 2.** Comparison of various parameters extracted for Si and hybrid 3.3 kVSiC substrates at 150°C from a double-

**Figure 7.** Output waveforms obtained for hybrid 3.3 kV SiC (a) and Si substrates (b) obtained during the first turn-on of

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

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7

In an oxide/semiconductor system, there are different types of charges which are present in the system. These charges are not desirable and greatly influence the electrical properties of a device. For example, the threshold voltage of a MOSFET and the breakdown voltage of a power, device, could change significantly because of these charges. These charges are divided into four types—mobile oxide charge, fixed oxide charge, oxide trapped charge, and interface

At present, interface trapped charge is a key hurdle for the silicon carbide MOS R&D community. The origin of these charges is not well understood but may be related to mainly siliconand carbon-dangling bonds, carbon clusters, carbon dimers in the SiC, and oxygen vacancies in the oxide very near to the interface [33–36]. Interfacial traps create localized energy levels in the energy band gap of SiC. These interface traps form potential wells that capture electrons

**3.1. Oxidation of SiC**

pulse test.

the IGBT. These devices were tested at 150°C.

trapped charge—and are shown in **Figure 9** [32].

#### **3. Processing challenges of SiC devices**

The fabrication of SiC devices is more demanding and complicated as compared with Si devices. Intrinsic properties of SiC make the devices suitable for high operating temperatures Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era… http://dx.doi.org/10.5772/intechopen.79487 7

**Figure 7.** Output waveforms obtained for hybrid 3.3 kV SiC (a) and Si substrates (b) obtained during the first turn-on of the IGBT. These devices were tested at 150°C.


**Table 2.** Comparison of various parameters extracted for Si and hybrid 3.3 kVSiC substrates at 150°C from a doublepulse test.

(>200°C). But at the same time, due to its intrinsic properties, it is difficult to perform any electrical and physical change to the material at temperatures lower than 1000°C. That means in order to fabricate an SiC device, different set of tools are required as compared to Si device world [28–31]. The electrical and physical properties of Si and SiC are listed in **Table 3**.

#### **3.1. Oxidation of SiC**

**Figure 6.** The schematic of a double-pulse test bench used to test devices.

pulse test.

(EMI), caused by the oscillations observed in the output waveforms.

**3. Processing challenges of SiC devices**

during the second turn-on of the IGBT at 150°C are recorded and are shown in **Figure 7**. For a di/dt = 1100 or 1388 A/μs, a reverse recovery current overshoot (Irr) of 128 A is observed for an Si substrate, which is higher than that of a hybrid SiC substrate (65A). The reverse recovery energy loss occurred in a substrate during the transient is Erec, and the values for Erec (Si) and Erec (SiC) are 0.199 and 0.01 J, respectively. This represents a reduction of about 95% for hybrid substrate. Other transient parameters for the substrates, namely Qrr, Eon, and Eoff (J), are also listed in **Table 2**. **Figure 8** shows the picture of a 3.3 kV, 200A hybrid SiC substrate. Again, like 1.7 kV hybrid substrates, 3.3 kV hybrid substrates are prone to electromagnetic interference

**Table 1.** Comparison of various parameters extracted for Si and hybrid 1.7 kVSiC substrates at 150°C from a double-

6 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The fabrication of SiC devices is more demanding and complicated as compared with Si devices. Intrinsic properties of SiC make the devices suitable for high operating temperatures In an oxide/semiconductor system, there are different types of charges which are present in the system. These charges are not desirable and greatly influence the electrical properties of a device. For example, the threshold voltage of a MOSFET and the breakdown voltage of a power, device, could change significantly because of these charges. These charges are divided into four types—mobile oxide charge, fixed oxide charge, oxide trapped charge, and interface trapped charge—and are shown in **Figure 9** [32].

At present, interface trapped charge is a key hurdle for the silicon carbide MOS R&D community. The origin of these charges is not well understood but may be related to mainly siliconand carbon-dangling bonds, carbon clusters, carbon dimers in the SiC, and oxygen vacancies in the oxide very near to the interface [33–36]. Interfacial traps create localized energy levels in the energy band gap of SiC. These interface traps form potential wells that capture electrons

**Figure 8.** A picture of a 200 a, 3.3 kV hybrid SiC substrate.


**Table 3.** Electrical and physical properties of Si, 3C-SiC, 6H-SiC and 4H-SiC.

and holes. In addition, charge traps also act as Columbic scattering centers [37]. These two effects decrease the effective channel mobility in a MOSFET. In Si world, a typical oxidation temperature employed to grow an oxide layer is 1050 (dry oxidation) or 850°C (wet oxidation). The oxidation step is followed by an annealing step in H<sup>2</sup> gas ambient at 800°C for 30 min. In 4H-SiC, typical oxidation temperature to grow a layer of native oxide is 1150°C. In some cases, it could be as high as 1300 or 1500°C which requires special oxidation furnaces, not the conventional quartz furnaces used for Si oxidation [38–41]. To use SiC devices to their full potential, we must continue to work to improve the electrical characteristics of the oxide/SiC interface by developing more effective processes to passivate defects at the interface formed during the oxidation process. These defects give rise to interface trap density, DIT (cm−2 eV−1) and is shown in **Figure 10**. Depending upon the surface potential, these traps can be charged

**Figure 10.** Energy band diagram of an SiC MOS system in inversion and location (qualitative) of different types of

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

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9

As mentioned previously, these traps decrease the effective channel mobility of electrons significantly. At present, there is a standard passivation process based on post-oxidation anneal-

(passivations) increases the inversion electron channel mobility of an SiC-MOSFET from

commercialization of SiC MOSFETs possible, there is still room for significant improvement. This inversion channel mobility value is only around 4% of bulk mobility value of SiC. In case

V−1·s−1, to around 30 cm<sup>2</sup>

**Figure 9.** Different types of charges in oxide/semiconductor system [10].

O) for 2 h at 1175°C. [42, 43]. This post-oxidation annealing

/V·s. Although these processes have made the

positively or negatively charged.

ing in nitric/nitrous oxide (NO/N<sup>2</sup>

single digits, ~ 8 cm<sup>2</sup>

charges.

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era… http://dx.doi.org/10.5772/intechopen.79487 9

**Figure 9.** Different types of charges in oxide/semiconductor system [10].

and holes. In addition, charge traps also act as Columbic scattering centers [37]. These two effects decrease the effective channel mobility in a MOSFET. In Si world, a typical oxidation temperature employed to grow an oxide layer is 1050 (dry oxidation) or 850°C (wet oxidation).

In 4H-SiC, typical oxidation temperature to grow a layer of native oxide is 1150°C. In some cases, it could be as high as 1300 or 1500°C which requires special oxidation furnaces, not the conventional quartz furnaces used for Si oxidation [38–41]. To use SiC devices to their full potential, we must continue to work to improve the electrical characteristics of the oxide/SiC

gas ambient at 800°C for 30 min.

The oxidation step is followed by an annealing step in H<sup>2</sup>

**Table 3.** Electrical and physical properties of Si, 3C-SiC, 6H-SiC and 4H-SiC.

**Figure 8.** A picture of a 200 a, 3.3 kV hybrid SiC substrate.

8 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**Figure 10.** Energy band diagram of an SiC MOS system in inversion and location (qualitative) of different types of charges.

interface by developing more effective processes to passivate defects at the interface formed during the oxidation process. These defects give rise to interface trap density, DIT (cm−2 eV−1) and is shown in **Figure 10**. Depending upon the surface potential, these traps can be charged positively or negatively charged.

As mentioned previously, these traps decrease the effective channel mobility of electrons significantly. At present, there is a standard passivation process based on post-oxidation annealing in nitric/nitrous oxide (NO/N<sup>2</sup> O) for 2 h at 1175°C. [42, 43]. This post-oxidation annealing (passivations) increases the inversion electron channel mobility of an SiC-MOSFET from single digits, ~ 8 cm<sup>2</sup> V−1·s−1, to around 30 cm<sup>2</sup> /V·s. Although these processes have made the commercialization of SiC MOSFETs possible, there is still room for significant improvement. This inversion channel mobility value is only around 4% of bulk mobility value of SiC. In case of Si, the inversion channel mobility can be as much as 50% of bulk mobility [29]. In addition to standard N<sup>2</sup> O annealing, there are different types of annealing which can increase the channel mobility significantly, but these annealings degrade some important parameters of a MOSFET and hence cannot be used [44–50]. More work is still needed in this field to improve the performance of SiC MOSFETs.

#### **3.2. Ohmic contacts**

In SiC, there is no or very little diffusion as a result, it is not possible to use temperature annealing process to drive in the dopants into the material. To get a desired doping profile in SiC, dopants are implanted using a high-energy implanter (typically 50–500 keV), and sometimes, wafers are needed to be at high temperature (~500°C) during this step. Implantation of dopants is followed by a dopant activation step, which requires a very high temperature. Typically, n-dopants get electrically activated at 1550°C, while p-dopants require a temperature of as high as 1700°C, which is very challenging to achieve. With n-dopants, the electrical activation rate of more than 90% can be attained, but in p-dopants, it is tough to realize an activation rate of more than 50%. The reason why lower activation temperature is required for n-dopants as compared to p-dopants is because of the difference in the location of respective dopant energy levels in SiC. For n dopants (N), the donor energy level is located at 0.3 eV (shallow) below the conduction band edge and hence not much energy is required to electrically activate these donors. In the case of p dopants (Al), the position of the acceptor level is 0.7 eV (deep) above the valance band edge. Hence, more energy is needed to electrically activate them. Even at present, various research groups are working on p-type ohmic contacts [51–56]. Also, high temperature and special metallization processes are necessary to form ohmic and Schottky contacts on SiC.

**5. Conclusions**

diode during the second turn-on event.

**Acknowledgements**

**Author details**

Yogesh K. Sharma

SiC device technology has a promising future. Different types of more efficient power systems have already been built using SiC devices and demonstrated in real applications around the world. This technology materializes the possibility of new topologies for inverter and converter, which were not possible in the past. Various fields including automotive, traction-train, renewable energy, geothermal energy, and so on have already been benefitted from SiC technology. Despite all these advantages, this technology is relatively new and hence poses some challenges. New control strategies, and more suitable module designs and packaging options are needed to be developed for the optimal use of these devices. The cost of SiC device is still a bit high, although, in the past couple of years, it has come down significantly. Even with all these challenges, new technology like SiC is indispensable to achieve the goal of a greener planet.

**Figure 11.** The ringing/oscillations observed in the output waveforms of a 3.3 kV, 1200A SiC hybrid module due to an underdamped response to an RLC circuit formed among the diode depletion capacitance, parasitic inductance, and SiC

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

http://dx.doi.org/10.5772/intechopen.79487

11

The author would like to thank his collogues at Dynex Semiconductors for their help and support provided, during this project. Also, I would like to specially thank my old colleagues

and partners at the University of Warwick (UK) and Auburn University (USA).

Address all correspondence to: aceyogesh83@gmail.com

R&D Centre: Semiconductors, Dynex Semiconductor Ltd., Lincoln, UK

#### **4. EMI problems**

Due to fast switching speed of SiC devices (Schottky diodes, MOSFETs), some undesirable effects are observed during the switching (from on-state to off-state and vice versa) of these devices. The oscillations observed in the output current waveform, **Figure 11**, are the result of the fast switching behavior of 1.7 kV, 50 A SiC diodes, which are used to build 3.3 kV, 1200 A hybrid SiC modules. From the application point of view, this is problematic and can lead to EMI with neighboring electrical systems. Sometimes, it can also lead to a premature breakdown of the module during operation. In full SiC module, it is common measure to slow the switching speed of the devices (by increasing the gate resistance) to reduce/eliminate the oscillations. From **Figure 11**, we can clearly see that the oscillations are present, both in current and in voltage waveforms. Also, these oscillations are present in the gate signal, which is used to control Si IGBT (clear from the inset in **Figure 11**) in the module. Because of these oscillations, the gate signal voltage in some cases may shoot up/down to +40 to −40 V, much higher than the recommended voltage range (−15 to +15 V) of the gate signal. We can imagine how detrimental this would be for Si IGBTs. If new design ideas are used for the substrate layout of these modules, then the parasitic elements (stray inductance and capacitance) could be minimized, and, hence, there will be no necessity of compromising on the switching speed of SiC devices.

**Figure 11.** The ringing/oscillations observed in the output waveforms of a 3.3 kV, 1200A SiC hybrid module due to an underdamped response to an RLC circuit formed among the diode depletion capacitance, parasitic inductance, and SiC diode during the second turn-on event.

#### **5. Conclusions**

of Si, the inversion channel mobility can be as much as 50% of bulk mobility [29]. In addi-

10 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

channel mobility significantly, but these annealings degrade some important parameters of a MOSFET and hence cannot be used [44–50]. More work is still needed in this field to improve

In SiC, there is no or very little diffusion as a result, it is not possible to use temperature annealing process to drive in the dopants into the material. To get a desired doping profile in SiC, dopants are implanted using a high-energy implanter (typically 50–500 keV), and sometimes, wafers are needed to be at high temperature (~500°C) during this step. Implantation of dopants is followed by a dopant activation step, which requires a very high temperature. Typically, n-dopants get electrically activated at 1550°C, while p-dopants require a temperature of as high as 1700°C, which is very challenging to achieve. With n-dopants, the electrical activation rate of more than 90% can be attained, but in p-dopants, it is tough to realize an activation rate of more than 50%. The reason why lower activation temperature is required for n-dopants as compared to p-dopants is because of the difference in the location of respective dopant energy levels in SiC. For n dopants (N), the donor energy level is located at 0.3 eV (shallow) below the conduction band edge and hence not much energy is required to electrically activate these donors. In the case of p dopants (Al), the position of the acceptor level is 0.7 eV (deep) above the valance band edge. Hence, more energy is needed to electrically activate them. Even at present, various research groups are working on p-type ohmic contacts [51–56]. Also, high temperature and special metallization processes are necessary to form

Due to fast switching speed of SiC devices (Schottky diodes, MOSFETs), some undesirable effects are observed during the switching (from on-state to off-state and vice versa) of these devices. The oscillations observed in the output current waveform, **Figure 11**, are the result of the fast switching behavior of 1.7 kV, 50 A SiC diodes, which are used to build 3.3 kV, 1200 A hybrid SiC modules. From the application point of view, this is problematic and can lead to EMI with neighboring electrical systems. Sometimes, it can also lead to a premature breakdown of the module during operation. In full SiC module, it is common measure to slow the switching speed of the devices (by increasing the gate resistance) to reduce/eliminate the oscillations. From **Figure 11**, we can clearly see that the oscillations are present, both in current and in voltage waveforms. Also, these oscillations are present in the gate signal, which is used to control Si IGBT (clear from the inset in **Figure 11**) in the module. Because of these oscillations, the gate signal voltage in some cases may shoot up/down to +40 to −40 V, much higher than the recommended voltage range (−15 to +15 V) of the gate signal. We can imagine how detrimental this would be for Si IGBTs. If new design ideas are used for the substrate layout of these modules, then the parasitic elements (stray inductance and capacitance) could be minimized, and, hence, there will be no necessity of compromising on the switching speed of SiC devices.

O annealing, there are different types of annealing which can increase the

tion to standard N<sup>2</sup>

**3.2. Ohmic contacts**

the performance of SiC MOSFETs.

ohmic and Schottky contacts on SiC.

**4. EMI problems**

SiC device technology has a promising future. Different types of more efficient power systems have already been built using SiC devices and demonstrated in real applications around the world. This technology materializes the possibility of new topologies for inverter and converter, which were not possible in the past. Various fields including automotive, traction-train, renewable energy, geothermal energy, and so on have already been benefitted from SiC technology. Despite all these advantages, this technology is relatively new and hence poses some challenges. New control strategies, and more suitable module designs and packaging options are needed to be developed for the optimal use of these devices. The cost of SiC device is still a bit high, although, in the past couple of years, it has come down significantly. Even with all these challenges, new technology like SiC is indispensable to achieve the goal of a greener planet.

#### **Acknowledgements**

The author would like to thank his collogues at Dynex Semiconductors for their help and support provided, during this project. Also, I would like to specially thank my old colleagues and partners at the University of Warwick (UK) and Auburn University (USA).

#### **Author details**

Yogesh K. Sharma

Address all correspondence to: aceyogesh83@gmail.com

R&D Centre: Semiconductors, Dynex Semiconductor Ltd., Lincoln, UK

#### **References**

[1] Pfann WG, Scaff JH. The p-germanium transistor. Proceedings of the IRE. 1950;**38**(10): 1151-1154

[19] Baliga BJ. Trends in power semiconductor devices. IEEE Transactions on Electron

[21] She X, Huang AQ, Lucía Ó, Ozpineci B. Review of silicon carbide power devices and their applications. IEEE Transactions on Industrial Electronics. 2017;**64**(10):8193-8205 [22] Piasecki S, Kazmierkowski MP. Applications of SiC MOSFETs in AC–DC converters dedicated for distributed generation systems. In: Analysis and Simulation of Electrical

[23] Morya A, Moosavi M, Gardner MC, Toliyat HA. Applications of wide bandgap (WBG) devices in AC electric drives: A technology status review. In: 2017 IEEE International

[24] Ishikawa K, Ogawa K, Yukutake S, Kameshiro N, Kono Y. Traction inverter that applies compact 3.3 kV/1200 A SiC hybrid module. In: 2014 International Power Electronics

[25] Yuan L, Li J, Gu Q, Zhao Z, Shen Y. Power losses of Si/SiC semiconductors in medium voltage energy router sub-modules with hybrid topology. In: 2017 20th International

[26] Kranz L, Minamisawa RA, Knoll L, Matthias S, Mihaila A, Papadopoulos C, et al. Robust SiC JBS diodes for the application in hybrid modules. In: Proceedings of PCIM Europe 2017; International Exhibition and Conference for Power Electronics, Intelligent Motion,

[27] Sharma YK, Jiang H, Zheng C, Dai X, Wang Y, Deviny I. Impact of design and process variation on the fabrication of SiC diodes. Journal of Semiconductors. Manuscript ID

[28] Grossner U, Alfieri G, Nipoti R. SiC device manufacturing: How processing impacts the material and device properties. In: Materials Science Forum. Vol. 821. Switzerland: Trans

[29] Kimoto T. Material science and device physics in SiC technology for high-voltage power

[30] Bonyadi Y, Gammon PM, Sharma YK, Baker G, Mawby PA.An investigation into the impact of surface passivation techniques using metal-semiconductor interfaces. In: Materials Science Forum. Vol. 897. Switzerland: Trans Tech Publications Ltd.; 2017. pp. 443-446 [31] Liu G, Tuttle BR, Dhar S. Silicon carbide: A unique platform for metal-oxide-semiconductor

[32] Sze SM, Ng KK. Physics of Semiconductor Devices. Hoboken, New Jersey, USA: John

[33] Afanas'ev VV, Ciobanu F, Dimitrijev S, Pensl G, Stesmans A. Band alignment and defect states at SiC/oxide interfaces. Journal of Physics: Condensed Matter. 2004;**16**(17):S1839

Electric Machines and Drives Conference (IEMDC); IEEE. 2017. pp. 1-8

Conference (IPEC-Hiroshima 2014-ECCE-ASIA); IEEE. 2014. pp. 2140-2144

Conference on Electrical Machines and Systems (ICEMS); IEEE. 2017. pp. 1-6

Renewable Energy and Energy Management; VDE. 2017. pp. 1-6

devices. Japanese Journal of Applied Physics. 2015;**54**(4):040103

physics. Applied Physics Reviews. 2015;**2**(2):021307

and Computer Systems. Cham: Springer; 2018. pp. 1-14

/SiC interface passivation [doctoral dissertation]; 2012

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

http://dx.doi.org/10.5772/intechopen.79487

13

Devices. 1996;**43**(10):1717-1731

[20] Sharma Y. Advanced SiO<sup>2</sup>

18020011.R1 (in press)

Wiley & Sons Inc.; 2006

Tech Publications Ltd.; 2015. p. 381


**References**

1151-1154

ment. 1973;**22**(2):193-196

Part B. 1989;**60**(2):189-212

2017-2024-300541299.html

[10] http://www.icinsights.com

Business Media; 2010

2002;**49**(9):1657-1664

1988;**35**(1):25-37

[1] Pfann WG, Scaff JH. The p-germanium transistor. Proceedings of the IRE. 1950;**38**(10):

[2] Valdes LB. Effect of electrode spacing on the equivalent base resistance of point-contact

[3] Ball JA. The Harvard minicorrelator. IEEE Transactions on Instrumentation and Measure-

[4] Lécuyer C. Making Silicon Valley: Innovation and the Growth of High Tech. Cambridge,

[5] O'Mara W, Herring RB, Hunt LP. Handbook of Semiconductor Silicon Technology. Park

[6] Deal BE, Grove AS. General relationship for the thermal oxidation of silicon. Journal of

[7] Mott NF, Rigo S, Rochet F, Stoneham AM. Oxidation of silicon. Philosophical Magazine

[8] Kao DB, Mcvittie JP, Nix WD, Saraswat KC. Two-dimensional thermal oxidation of silicon. II. Modeling stress effects in wet oxides. IEEE Transactions on Electron Devices.

[9] https://www.prnewswire.com/news-releases/global-semiconductor-market-forecast-

[13] Baliga BJ. Fundamentals of Power Semiconductor Devices. USA: Springer Science &

[14] Warner RM. Microelectronics: Its unusual origin and personality. IEEE Transactions on

[16] Lin Z, Hu S, Yuan Q, Zhou X, Tang F.Low-reverse recovery charge superjunction MOSFET with a p-type Schottky body diode. IEEE Electron Device Letters. 2017;**38**(8):1059-1062 [17] Udrea F, Deboy G, Fujihira T. Superjunction power devices, history, development, and

[18] Morisette DT, Cooper JA. Theoretical comparison of SiC PiN and Schottky diodes based on power dissipation considerations. IEEE Transactions on Electron Devices.

future prospects. IEEE Transactions on Electron Devices. 2017;**64**(3):720-734

[11] http://www.electroiq.com/articles/sst/print/volume-54/issue-7.html

[12] http://www.power-mag.com/news.detail.php?NID=38

[15] http://www.irf.com/60anniversary/index.html#1970s

Electron Devices. 2001;**48**(11):2457-2467

transistors. Proceedings of the IRE. 1952;**40**(11):1429-1434

12 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Massachusetts, USA; MIT Press; 2006. pp. 1930-1970

Ridge, NJ, USA: Noyes Publications; 1990

Applied Physics. 1965;**36**(12):3770-3778


[34] Tuttle BR. Dangling bond defects in SiC: An ab initio study. Physical Review B. 2018;**97**(4):045203

[47] Sharma YK, Ahyi AC, Issacs-Smith T, Shen X, Pantelides ST, Zhu X, et al. Phosphorous

[48] Sharma YK, Ahyi AC, Isaacs-Smith T, Modic A, Park M, Xu Y, et al. High-mobility stable 4H-SiC MOSFETs using a thin PSG interfacial passivation layer. IEEE Electron Device

[49] Zheng Y, Isaacs-Smith T, Ahyi AC, Dhar S. 4H-SiC MOSFETs with borosilicate glass gate dielectric and antimony counter-doping. IEEE Electron Device Letters. 2017;**38**(10):

[50] Cabello M, Soler V, Rius G, Montserrat J, Rebollo J, Godignon P. Advanced processing for mobility improvement in 4H-SiC MOSFETs: A review. Materials Science in

[51] Vivona M, Greco G, Bongiorno C, Nigro RL, Scalese S, Roccaforte F. Electrical and structural properties of surfaces and interfaces in Ti/Al/Ni Ohmic contacts to p-type

[52] Fedeli P, Puzzanghera M, Moscatelli F, Minamisawa RA, Alfieri G, Grossner U, Nipoti R. Ni-Al-Ti Ohmic contacts on Al implanted 4H-SiC. In: Materials Science Forum. Vol. 897.

[53] Zhang Y, Guo T, Tang X, Yang J, He Y, Zhang Y. Thermal stability study of n-type and p-type ohmic contacts simultaneously formed on 4H-SiC. Journal of Alloys and

[54] Gammon PM, Pérez-Tomás A, Shah VA, Vavasour O, Donchev E, Pang JS, et al. Modelling the inhomogeneous SiC Schottky interface. Journal of Applied Physics.

[55] Jennings MR, Fisher CA, Walker D, Sanchez A, Pérez-Tomás A, Hamilton DP, et al. On the

Science Forum. Vol. 778. Switzerland: Trans Tech Publications Ltd.; 2014. pp. 693-696

[56] Baliga BJ, Sung WJ, Han KJ, Harmon J, Tucker A, Syed S. PRESiCETM: Process engineered for manufacturing SiC electronic devices. In: Materials Science Forum. Vol. 924.

metallic phase formation for robust p-type 4H-SiC ohmic contacts. In: Materials

implanted 4H-SiC. Applied Surface Science. 2017;**420**:331-335

Switzerland: Trans Tech Publications Ltd.; 2017. pp. 391-394

Switzerland: Trans Tech Publications Ltd.; 2018. pp. 523-526

/4H–SiC interface. Solid-State Electronics. 2012;**68**:103-107

Introductory Chapter: Need of SiC Devices in Power Electronics - A Beginning of New Era…

http://dx.doi.org/10.5772/intechopen.79487

15

passivation of the SiO<sup>2</sup>

Letters. 2013;**34**(2):175-177

Semiconductor Processing. 2018;**78**:22-31

Compounds. 2018;**731**:1267-1274

2013;**114**(22):223704

Ti3 SiC<sup>2</sup>

1433-1436


[47] Sharma YK, Ahyi AC, Issacs-Smith T, Shen X, Pantelides ST, Zhu X, et al. Phosphorous passivation of the SiO<sup>2</sup> /4H–SiC interface. Solid-State Electronics. 2012;**68**:103-107

[34] Tuttle BR. Dangling bond defects in SiC: An ab initio study. Physical Review B.

[35] Jayawardhena IU, Jayawardena A, Isaacs-Smith T, Dhar S. Effect of wafer orientation on near-interface oxide traps in 4H-SiC metal-oxide-semiconductor capacitors. In: Meeting

[36] Jiao C, Ahyi AC, Dhar S, Morisette D, Myers-Ward R. Interface trap profiles in 4H-and 6H-SiC MOS capacitors with nitrogen-and phosphorus-doped gate oxides. Journal of

[37] Pérez-Tomás A, Brosselard P, Godignon P, Millán J, Mestres N, Jennings MR, et al. Fieldeffect mobility temperature modeling of 4H-Si C metal-oxide-semiconductor transistors.

[38] Ramamurthy RP, Morisette DT, Amarasinghe V, Feldman LC. Thermal-oxidation-free dielectrics for SiC power devices. In: 2017 IEEE 5th Workshop on Wide Bandgap Power

[39] Thomas SM, Jennings MR, Sharma YK, Fisher CA, Mawby PA. Impact of the oxidation temperature on the interface trap density in 4H-SiC MOS capacitors. In: Materials Science Forum. Vol. 778. Switzerland: Trans Tech Publications Ltd.; 2014. pp. 599-602

[40] Thomas SM, Sharma YK, Crouch MA, Fisher CA, Perez-Tomas A, Jennings MR, Mawby PA. Enhanced field effect mobility on 4H-SiC by oxidation at 1500 C. IEEE Journal of the

[41] Jia Y, Lv H, Song Q, Tang X, Xiao L, Wang L, et al. Influence of oxidation temperature on the interfacial properties of n-type 4H-SiC MOS capacitors. Applied Surface Science.

[42] Chung GY, Tin CC, Williams JR, McDonald K, Chanana RK, Weller RA, et al. Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in

[44] Modic A, Sharma YK, Xu Y, Liu G, Ahyi AC, Williams JR, et al. Nitrogen plasma process-

[45] Okamoto D, Sometani M, Harada S, Kosugi R, Yonezawa Y, Yano H. Effect of boron

[46] Liu G, Ahyi AC, Xu Y, Isaacs-Smith T, Sharma YK, Williams JR, et al. Enhanced inversion

/4H-SiC interfaces. Journal of Electronic Materials. 2014;**43**(4):857-862

grown on SiC by rapid thermal processing. Applied Physics Letters.

20) using phosphorus and nitrogen interface passivation. IEEE

/4H-SiC structures. Applied Physics A.

O and

[43] Li HF, Dimitrijev S, Harrison HB, Sweatman D. Interfacial characteristics of N<sup>2</sup>

Abstracts, No. 23; The Electrochemical Society. 2018. pp. 1441-1441

14 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Electronic Materials. 2017;**46**(4):2296-2300

Journal of Applied Physics. 2006;**100**(11):114508

Electron Devices Society. 2014;**2**(5):114-117

incorporation on slow interface traps in SiO<sup>2</sup>

Electron Device Letters. 2013;**34**(2):181-183

2017;**397**:175-182

NO nitrided SiO<sup>2</sup>

ing of SiO<sup>2</sup>

2017;**123**(2):133

mobility on 4H-SiC (11¯

1997;**70**(15):2028-2030

Devices and Applications (WiPDA); IEEE. 2017. pp. 242-245

nitric oxide. IEEE Electron Device Letters. 2001;**22**(4):176-178

2018;**97**(4):045203


**Chapter 2**

Provisional chapter

**TCAD Device Modelling and Simulation of Wide**

DOI: 10.5772/intechopen.76062

Technology computer-aided Design (TCAD) is essential for devices technology development, including wide bandgap power semiconductors. However, most TCAD tools were originally developed for silicon and their performance and accuracy for wide bandgap semiconductors is contentious. This chapter will deal with TCAD device modelling of wide bandgap power semiconductors. In particular, modelling and simulating 3C- and 4H-Silicon Carbide (SiC), Gallium Nitride (GaN) and Diamond devices are examined. The challenges associated with modelling the material and device physics are analyzed in detail. It also includes convergence issues and accuracy of predicted performance. Modelling and simulating defects, traps and the effect of these traps on the characteristics are

Keywords: TCAD, modelling and simulation, silicon carbide, gallium nitride, diamond,

Power devices made from wide bandgap materials have superior performance compared to those made from silicon. They can sustain higher voltages or endure smaller losses, they can operate at much higher junction temperatures and can switch faster. This is because, as seen in Figure 1, of their superior electrical properties. This in turn can revolutionize how applications work and possibly make new applications possible. The most mature materials in terms of process and device technology are the 4H-SiC and GaN-based devices. There is however, an

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

TCAD Device Modelling and Simulation of Wide

**Bandgap Power Semiconductors**

Bandgap Power Semiconductors

Neophytos Lophitis, Anastasios Arvanitopoulos,

Neophytos Lophitis, Anastasios Arvanitopoulos,

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Samuel Perkins and Marina Antoniou

Samuel Perkins and Marina Antoniou

http://dx.doi.org/10.5772/intechopen.76062

Abstract

also discussed.

1. Introduction

1.1. Materials and devices

physics modelling, material parameters

#### **TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors** TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

DOI: 10.5772/intechopen.76062

Neophytos Lophitis, Anastasios Arvanitopoulos, Samuel Perkins and Marina Antoniou Neophytos Lophitis, Anastasios Arvanitopoulos, Samuel Perkins and Marina Antoniou

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76062

#### Abstract

Technology computer-aided Design (TCAD) is essential for devices technology development, including wide bandgap power semiconductors. However, most TCAD tools were originally developed for silicon and their performance and accuracy for wide bandgap semiconductors is contentious. This chapter will deal with TCAD device modelling of wide bandgap power semiconductors. In particular, modelling and simulating 3C- and 4H-Silicon Carbide (SiC), Gallium Nitride (GaN) and Diamond devices are examined. The challenges associated with modelling the material and device physics are analyzed in detail. It also includes convergence issues and accuracy of predicted performance. Modelling and simulating defects, traps and the effect of these traps on the characteristics are also discussed.

Keywords: TCAD, modelling and simulation, silicon carbide, gallium nitride, diamond, physics modelling, material parameters

#### 1. Introduction

#### 1.1. Materials and devices

Power devices made from wide bandgap materials have superior performance compared to those made from silicon. They can sustain higher voltages or endure smaller losses, they can operate at much higher junction temperatures and can switch faster. This is because, as seen in Figure 1, of their superior electrical properties. This in turn can revolutionize how applications work and possibly make new applications possible. The most mature materials in terms of process and device technology are the 4H-SiC and GaN-based devices. There is however, an

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Figure 1. Material properties of significant power semiconductors normalized against Si, data taken form [1, 2].

increased interest and effort in advancing 3C-SiC and overcoming the technical challenges associated with the development of good-quality 3C-SiC wafers because of lower processing costs and the possibility for high channel mobility MOSFETs. Ultra-wide bandgap materials such as diamond are also being explored.

stage, the device geometry, the material and doping profile, and concentration of regions is defined. Commercial tools include Synopsys Sentaurus Structure Editor [6] and SilvacoDev-Edit™ [7]. These tools allow device designers to parameterize device aspects and features to optimize their design or to assess the performance dependence on the parameters of question.

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

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19

Figure 2. Exemplary combination of tools making up a typical TCAD suite framework.

The process simulation tools allow for the virtual fabrication of devices and the emulation of fabrication steps and conditions. They typically make use of a scripting language and require knowledge of a process recipe. These tools allow process engineers to fine tune their recipe and to analyze the effect of each process step and condition on the resulting device structure. Commercial tools include Synopsys Sentaurus Sentaurus Process [8] and Silvaco Athena [9].

Device simulation tools have the capability to simulate the electrical, thermal, and optical properties and performance of devices. They can also account for the circuitry that surrounds a device when used in real applications. Therefore, they typically have SPICE capabilities too. They predict the device performance by executing finite element analysis and the solution of fundamental semiconductor physics equations. They make use of numerical devices created either through a device design tool or a process simulation tool. They take into consideration the materials incorporated in the device and they have a database with physics equations and the equivalent material parameters. Commercial tools include Synopsys Sentaurus Device [10]

This chapter aims to highlight issues and present solutions and methods for achieving accurate models of WBG power devices. This includes proper modelling the material physics equations

• Process simulation tool

and Silvaco Atlas [11].

1.3. Summary

• Device (and circuit) simulation tool

Silicon carbide is similar to silicon in terms of device design and optimization strategies. Most devices made in silicon can also be made in SiC. This includes Schottky Barrier Diodes, MOSFETs, IGBTs, and Thyristors. However, devices made in GaN are hetero devices and base their operation on the two-dimensional electron gas (2DEG) that is formed in the quantum well between the heterojunction interfaces. This quantum well provides electrons with a highly conductive channel, allowing high electron mobility. It is reported in literature that the electron mobility in GaN HEMT devices can be upwards of 1500 cm<sup>2</sup> /Vs [3].

#### 1.2. Technology computer-aided design

TCAD is an engineering computer-aided tool which enables the physics-based modelling of semiconductor devices and their fabrication process. Due to the excellent predicting capability, semiconductor process and device engineers use TCAD for virtual prototyping and optimization of devices, to reduce the number of experimental cycles and, therefore, to reduce the production cost. TCAD can also be used to study the performance of devices when used in new applications or environments, to find performance limits and to analyze failures [4, 5]. Modern TCAD suites are compiled by several tools. A typical example of a TCAD suite is diagrammatically described in Figure 2 and it consists of the following elements:

#### • Device design tool

The device design tool allows the rapid creation of device structures via the use of scripting language or a graphical user interface without the need to know the process recipe. At this

Figure 2. Exemplary combination of tools making up a typical TCAD suite framework.

stage, the device geometry, the material and doping profile, and concentration of regions is defined. Commercial tools include Synopsys Sentaurus Structure Editor [6] and SilvacoDev-Edit™ [7]. These tools allow device designers to parameterize device aspects and features to optimize their design or to assess the performance dependence on the parameters of question.

#### • Process simulation tool

increased interest and effort in advancing 3C-SiC and overcoming the technical challenges associated with the development of good-quality 3C-SiC wafers because of lower processing costs and the possibility for high channel mobility MOSFETs. Ultra-wide bandgap materials

Figure 1. Material properties of significant power semiconductors normalized against Si, data taken form [1, 2].

18 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Silicon carbide is similar to silicon in terms of device design and optimization strategies. Most devices made in silicon can also be made in SiC. This includes Schottky Barrier Diodes, MOSFETs, IGBTs, and Thyristors. However, devices made in GaN are hetero devices and base their operation on the two-dimensional electron gas (2DEG) that is formed in the quantum well between the heterojunction interfaces. This quantum well provides electrons with a highly conductive channel, allowing high electron mobility. It is reported in literature that the electron

TCAD is an engineering computer-aided tool which enables the physics-based modelling of semiconductor devices and their fabrication process. Due to the excellent predicting capability, semiconductor process and device engineers use TCAD for virtual prototyping and optimization of devices, to reduce the number of experimental cycles and, therefore, to reduce the production cost. TCAD can also be used to study the performance of devices when used in new applications or environments, to find performance limits and to analyze failures [4, 5]. Modern TCAD suites are compiled by several tools. A typical example of a TCAD suite is

The device design tool allows the rapid creation of device structures via the use of scripting language or a graphical user interface without the need to know the process recipe. At this

diagrammatically described in Figure 2 and it consists of the following elements:

/Vs [3].

such as diamond are also being explored.

1.2. Technology computer-aided design

• Device design tool

mobility in GaN HEMT devices can be upwards of 1500 cm<sup>2</sup>

The process simulation tools allow for the virtual fabrication of devices and the emulation of fabrication steps and conditions. They typically make use of a scripting language and require knowledge of a process recipe. These tools allow process engineers to fine tune their recipe and to analyze the effect of each process step and condition on the resulting device structure. Commercial tools include Synopsys Sentaurus Sentaurus Process [8] and Silvaco Athena [9].

#### • Device (and circuit) simulation tool

Device simulation tools have the capability to simulate the electrical, thermal, and optical properties and performance of devices. They can also account for the circuitry that surrounds a device when used in real applications. Therefore, they typically have SPICE capabilities too. They predict the device performance by executing finite element analysis and the solution of fundamental semiconductor physics equations. They make use of numerical devices created either through a device design tool or a process simulation tool. They take into consideration the materials incorporated in the device and they have a database with physics equations and the equivalent material parameters. Commercial tools include Synopsys Sentaurus Device [10] and Silvaco Atlas [11].

#### 1.3. Summary

This chapter aims to highlight issues and present solutions and methods for achieving accurate models of WBG power devices. This includes proper modelling the material physics equations and their parameters, creating the finite elements and geometry and simulation of device characteristics including numerical issues and the effect of traps.

#### 2. Material physics modelling

TCAD tools solve fundamental semiconductor physics equations to predict the performance of semiconductor devices. Accurately modelling the material properties through appropriate physics equations and parameters is essential for reliable simulations. These can depend on how advanced and mature the process, growth and technology is. For silicon, the material properties have been studied extensively and the technology is mature. Therefore, the material models and their parameters are typically considered accurate and able to predict the siliconbased devices performance with high level of accuracy. However, for WBG semiconductorbased devices, a lower confidence level exists. In the following subsections, we discuss the physics equations and the parameter sets required for accurate physical modelling of 3C-SiC, 4H-SiC, GaN and diamond power semiconductors. The equations used and parameters are compatible with most TCAD products.

#### 2.1. Silicon carbide

There are hundreds of Silicon Carbide polytypes. From those, 4H-SiC is the most mature and studied polytype. The cubic polytype, 3C-SiC is also of particular interest because of its special properties, such as the ability to grow this compound semiconductor on large area silicon wafers, the lower temperatures required when processing the material and the ability to make MOSFETs with much higher channel mobility. The former two results in a much cheaper starting wafer whereas the latter one can enable the development of devices with higher efficiency. The corresponding values required in a physics parameter file for 4H-SiC were developed and improved alongside the improvement of the technology. Recently there have been efforts to compile an equivalent set of parameters for 3C and to validate them [12, 13]. This section presents the required models and the parameters of both materials. Wherever necessary, a range of values is used. Further, each physical mechanism presented is accompanied with the corresponding identified limitations. SiC polytypes can experience anisotropic properties, therefore when aiming multidimensional device simulation, these must be accounted for in the material parameter file and physics equations [14]. 4H-SiC experiences such behaviour, whilst 3C-SiC experiences isotropic behaviour. The parameters are then included within the 'Device (and Circuit) Simulation' tool of TCAD tools.

addition, the phenomenon of bandgap narrowing causes band displacements in the energy scale directly related to doping according to Eq. (2), (3). These displacements represent potential barriers that may influence carrier transportation phenomena in the device. The bandgap dependence on doping in SiC can be described as in Eq. (4). The perception of the modeled effective bandgap value for the SiC can be expressed as Eg,effð Þ¼ T Egð Þ� T Ebgn utilizing the

Figure 3. The 3C-SiC (top) and 4H-SiC (bottom) bandgap dependence on temperature as described with the models

given in this chapter are in excellent agreement to literature data [15] for both β-SiC and α-SiC, respectively.

<sup>=</sup> <sup>T</sup> <sup>þ</sup> <sup>β</sup> � � (1)

(2)

Egð Þ¼ <sup>T</sup> Egð Þ� <sup>0</sup> <sup>α</sup>T<sup>2</sup>

Bp∙N<sup>1</sup>=<sup>4</sup>

tot <sup>þ</sup> Cn∙N<sup>1</sup>=<sup>2</sup>

tot <sup>þ</sup> Dp∙N<sup>1</sup>=<sup>2</sup>

tot , ND,<sup>0</sup> > NA,<sup>0</sup>

tot , otherwise

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

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21

parameters shown in Tables 1–3.

Econd

bgn <sup>¼</sup> An∙N<sup>1</sup>=<sup>3</sup>

8 < :

#### 2.1.1. Band parameters

The desired properties of the WBG SiC originate from its bandgap characteristics. The value of Eg shall not be considered constant, but variable with dependencies on both the concentration of impurities and temperature as shown in Figures 3 and 4 correspondingly. Increasing the temperature of the material essentially leads to lower gap values as described by Eq. (1). In

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors http://dx.doi.org/10.5772/intechopen.76062 21

and their parameters, creating the finite elements and geometry and simulation of device

TCAD tools solve fundamental semiconductor physics equations to predict the performance of semiconductor devices. Accurately modelling the material properties through appropriate physics equations and parameters is essential for reliable simulations. These can depend on how advanced and mature the process, growth and technology is. For silicon, the material properties have been studied extensively and the technology is mature. Therefore, the material models and their parameters are typically considered accurate and able to predict the siliconbased devices performance with high level of accuracy. However, for WBG semiconductorbased devices, a lower confidence level exists. In the following subsections, we discuss the physics equations and the parameter sets required for accurate physical modelling of 3C-SiC, 4H-SiC, GaN and diamond power semiconductors. The equations used and parameters are

There are hundreds of Silicon Carbide polytypes. From those, 4H-SiC is the most mature and studied polytype. The cubic polytype, 3C-SiC is also of particular interest because of its special properties, such as the ability to grow this compound semiconductor on large area silicon wafers, the lower temperatures required when processing the material and the ability to make MOSFETs with much higher channel mobility. The former two results in a much cheaper starting wafer whereas the latter one can enable the development of devices with higher efficiency. The corresponding values required in a physics parameter file for 4H-SiC were developed and improved alongside the improvement of the technology. Recently there have been efforts to compile an equivalent set of parameters for 3C and to validate them [12, 13]. This section presents the required models and the parameters of both materials. Wherever necessary, a range of values is used. Further, each physical mechanism presented is accompanied with the corresponding identified limitations. SiC polytypes can experience anisotropic properties, therefore when aiming multidimensional device simulation, these must be accounted for in the material parameter file and physics equations [14]. 4H-SiC experiences such behaviour, whilst 3C-SiC experiences isotropic behaviour. The parameters are then

The desired properties of the WBG SiC originate from its bandgap characteristics. The value of Eg shall not be considered constant, but variable with dependencies on both the concentration of impurities and temperature as shown in Figures 3 and 4 correspondingly. Increasing the temperature of the material essentially leads to lower gap values as described by Eq. (1). In

included within the 'Device (and Circuit) Simulation' tool of TCAD tools.

characteristics including numerical issues and the effect of traps.

20 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

2. Material physics modelling

compatible with most TCAD products.

2.1. Silicon carbide

2.1.1. Band parameters

Figure 3. The 3C-SiC (top) and 4H-SiC (bottom) bandgap dependence on temperature as described with the models given in this chapter are in excellent agreement to literature data [15] for both β-SiC and α-SiC, respectively.

addition, the phenomenon of bandgap narrowing causes band displacements in the energy scale directly related to doping according to Eq. (2), (3). These displacements represent potential barriers that may influence carrier transportation phenomena in the device. The bandgap dependence on doping in SiC can be described as in Eq. (4). The perception of the modeled effective bandgap value for the SiC can be expressed as Eg,effð Þ¼ T Egð Þ� T Ebgn utilizing the parameters shown in Tables 1–3.

$$E\_{\mathcal{S}}(T) = E\_{\mathcal{S}}(0) - \alpha T^2 / \left(T + \beta\right) \tag{1}$$

$$E\_{byn}^{cond} = \begin{cases} A\_n \cdot N\_{\text{bot}}^{1/3} + \mathbb{C}\_n \cdot N\_{\text{bot}}^{1/2} & N\_{D,0} > N\_{A,0} \\ & B\_p \cdot N\_{\text{bot}}^{1/4} + D\_p \cdot N\_{\text{bot}}^{1/2} \text{ } \text{ } otherwise \end{cases} \tag{2}$$

Figure 4. The bandgap narrowing phenomenon as modeled for TCAD simulations assuming n-type SiC material. The measured energy displacements of the bands are sourced from [16].

Eval

Table 3. 4H-SiC bandgap narrowing doping dependence.

Table 2. 3C-SiC band gap narrowing doping dependence.

Table 1. SiC parameter set related to bandgap.

Table 4. SiC temperature dependent density of states.

NC (300 K) [cm�<sup>3</sup>

NV (300 K) [cm�<sup>3</sup>

bgn <sup>¼</sup> Bn∙N<sup>1</sup>=<sup>4</sup>

8 < :

Lindefelt model coefficients 4H-SiC semiconductor material

Lindefelt model coefficients 3C-SiC semiconductor material

tot <sup>þ</sup> Dn∙N<sup>1</sup>=<sup>2</sup>

Parameters description 3C-SiC 4H-SiC

An, <sup>p</sup> [eV�cm] �1.791 � <sup>10</sup>�<sup>8</sup> 3.507 � <sup>10</sup>�<sup>8</sup> Bn, <sup>p</sup> [eV�cm3/4] 8.927 � <sup>10</sup>�<sup>7</sup> �2.312 � <sup>10</sup>�<sup>6</sup> Cn,p [eV�cm3/2] �2.2 � <sup>10</sup>�<sup>12</sup> 6.74 � <sup>10</sup>�<sup>12</sup> Dn, <sup>p</sup> [eV�cm3/2] 6.24 � <sup>10</sup>�<sup>12</sup> �1.07 � <sup>10</sup>�<sup>12</sup>

Parameters description 3C-SiC 4H-SiC Eg(0) [eV] 2.39 3.265 <sup>α</sup> [eV/K] 0.66 � <sup>10</sup>�<sup>3</sup> 3.3 � <sup>10</sup>�<sup>2</sup> <sup>β</sup> [Κ] <sup>1335</sup> 1.0 � <sup>10</sup><sup>5</sup>

An, <sup>p</sup> [eV�cm] �1.48 � <sup>10</sup>�<sup>8</sup> 1.3 � <sup>10</sup>�<sup>8</sup> Bn, <sup>p</sup> [eV�cm3/4] 9.0 � <sup>10</sup>�<sup>7</sup> �4.8 � <sup>10</sup>�<sup>7</sup> Cn,p [eV�cm3/2] �3.06 � <sup>10</sup>�<sup>12</sup> 1.43 � <sup>10</sup>�<sup>12</sup> Dn, <sup>p</sup> [eV�cm3/2] 6.85 � <sup>10</sup>�<sup>12</sup> �6.41 � <sup>10</sup>�<sup>13</sup>

tot <sup>þ</sup> Cp∙N<sup>1</sup>=<sup>2</sup>

] 1.5536 � 1019 1.719 � <sup>10</sup><sup>19</sup>

] 1.1639 � 1019 2.509 � <sup>10</sup><sup>19</sup>

bgn <sup>þ</sup> <sup>E</sup>val

Ap∙N<sup>1</sup>=<sup>3</sup>

<sup>g</sup> ¼ �Econd

To model the intrinsic characteristics of the semiconductor, the temperature dependence of the density of states (DoS) for SiC in Eq. (5) is used. The parameters of Table 4 determine the

ΔE<sup>0</sup>

tot , ND,<sup>0</sup> > NA, <sup>0</sup>

tot , otherwise

n-type p-type

n-type p-type

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

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23

bgn (4)

(3)


Table 1. SiC parameter set related to bandgap.


Table 2. 3C-SiC band gap narrowing doping dependence.


Table 3. 4H-SiC bandgap narrowing doping dependence.


Table 4. SiC temperature dependent density of states.

Figure 4. The bandgap narrowing phenomenon as modeled for TCAD simulations assuming n-type SiC material. The

measured energy displacements of the bands are sourced from [16].

22 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

$$E\_{bgn}^{val} = \begin{cases} B\_n \cdot \mathbf{N}\_{tot}^{1/4} + D\_n \cdot \mathbf{N}\_{tot}^{1/2} & \text{N}\_{D,0} > \mathbf{N}\_{A,0} \\\\ A\_p \cdot \mathbf{N}\_{tot}^{1/3} + \mathbf{C}\_p \cdot \mathbf{N}\_{tot}^{1/2} & \text{otherwise} \end{cases} \tag{3}$$

$$
\Delta E\_{\rm g}^{0} = -E\_{\rm byn}^{cond} + E\_{\rm byn}^{val} \tag{4}
$$

To model the intrinsic characteristics of the semiconductor, the temperature dependence of the density of states (DoS) for SiC in Eq. (5) is used. The parameters of Table 4 determine the

Figure 5. The intrinsic carrier concentration as resulting from the model of DoS for both SiC cases in question. Comparison with literature data for 3C-SiC [18] and 4H-SiC [16] is performed. Assuming low doping levels (5 � <sup>10</sup><sup>15</sup> cm�<sup>3</sup> ) the bandgap narrowing is considered negligible.

intrinsic carrier concentration of the semiconductor as well as quantities like the effective carrier masses. In Figure 5, plotting the intrinsic carrier concentration against the temperature a discrepancy with measurements can be noticed for the case of 3C-SiC. This suggests that the TCAD simulations of 3C-SiC power devices utilizing this model should yield reasonably good results for limited temperature range of 200–500 K.

Under low field conditions, the mobility of both types of carriers in SiC also depends on the doping concentration and on temperature. The first dependence is described by the Caughey-Thomas (C-T) model <sup>μ</sup><sup>0</sup> <sup>¼</sup> <sup>μ</sup>min <sup>þ</sup> <sup>μ</sup>max � <sup>μ</sup>min <sup>=</sup> <sup>1</sup> <sup>þ</sup> <sup>N</sup>=Nref <sup>α</sup> as illustrated in Figure 6. Each coefficient in the C-T equation changes with temperature as in Eq. (6) and the values in Table 6. Currently, there is an uncertainty for the holes' mobility actual value in 3C-SiC. However, the values adopted in Table 5 are suggested from recent measurements [16, 17]. The mobility of carriers for the temperature range of 250–700 K was described in [12]. In high field conditions, with magnitude of values as shown in Figure 7, the mobility and velocity of carriers become inseparable directly affecting each other. The Canali model, Eq. (7) is utilized for these purposes and its parameters for SiC are presented in Table 7. In Eq. (8), the holes' saturation velocity determines the range of electric field values at 200 kV/cm < E < 2000 kV/cm [12].

$$N\_{\mathbb{C},V}(T) = N\_{\mathbb{C},V} \mathbf{300} \times \left(T/\mathbf{300}\right)^{\circ\_{\mathbb{C}}} \tag{5}$$

$$\text{Par} = \text{Par}\_0 \times (T/300\text{K})^\circ \tag{6}$$

Figure 6. Based on experimental data [19], the SiC models utilized result in a very good accuracy. Increased the doping concentration, more scattering occurs and the mobility drops. The maximum carrier mobility values in SiC range and

Parameter 3C-SiC 4H-SiC [perpendicular to c-axis] 4H-SiC [parallel to c-axis]

/Vs] 650 70 910 114 1100 114

] 1.5 <sup>10</sup><sup>17</sup> <sup>5</sup> <sup>10</sup><sup>19</sup> 2.0 <sup>10</sup><sup>17</sup> 2.4 <sup>10</sup><sup>18</sup> 2.0 <sup>10</sup><sup>17</sup> 2.4 <sup>10</sup><sup>18</sup>

/Vs] 40 15 40 0 40 0

α 0.8 0.3 0.76 0.69 0.76 0.69

[same for both directions]

Table 6. SiC parameters for low field mobility and coefficients used to express temperature dependence.

Table 5. SiC parameters for low field mobility and coefficients used to express doping dependence.

Electrons Holes Electrons Holes <sup>γ</sup>max 0.3 2.5 2.4 2.6 <sup>μ</sup>max [cm<sup>2</sup>

<sup>γ</sup>min 0.5 0.5 1.536 0.57 <sup>μ</sup>min [cm<sup>2</sup>

γNref 2 0 0.75 2.9 Nref [cm<sup>3</sup>

γα 0 0 0.722 0.2 α

Electrons Holes Electrons Holes Electrons Holes

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

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25

Corresponding parameter from Table 5

/Vs]

/Vs]

]

depend on crystal thickness [20] and impurities level.

Parameter 3C-SiC 4H-SiC

μmax [cm<sup>2</sup>

μmin [cm<sup>2</sup>

Nref [cm<sup>3</sup>

$$\mu\_0(E) = \frac{(\alpha + 1)\mu\_{low}}{\alpha + \left[1 + \left(\frac{(a+1)\mu\_{low}E}{v\_{\rm sat}}\right)^{\beta}\right]^{1/\rho}}\tag{7}$$

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors http://dx.doi.org/10.5772/intechopen.76062 25

Figure 6. Based on experimental data [19], the SiC models utilized result in a very good accuracy. Increased the doping concentration, more scattering occurs and the mobility drops. The maximum carrier mobility values in SiC range and depend on crystal thickness [20] and impurities level.


Table 5. SiC parameters for low field mobility and coefficients used to express doping dependence.

intrinsic carrier concentration of the semiconductor as well as quantities like the effective carrier masses. In Figure 5, plotting the intrinsic carrier concentration against the temperature a discrepancy with measurements can be noticed for the case of 3C-SiC. This suggests that the TCAD simulations of 3C-SiC power devices utilizing this model should yield reasonably good

Figure 5. The intrinsic carrier concentration as resulting from the model of DoS for both SiC cases in question. Comparison with literature data for 3C-SiC [18] and 4H-SiC [16] is performed. Assuming low doping levels (5 � <sup>10</sup><sup>15</sup> cm�<sup>3</sup>

Under low field conditions, the mobility of both types of carriers in SiC also depends on the doping concentration and on temperature. The first dependence is described by the Caughey-

<sup>=</sup> <sup>1</sup> <sup>þ</sup> <sup>N</sup>=Nref

coefficient in the C-T equation changes with temperature as in Eq. (6) and the values in Table 6. Currently, there is an uncertainty for the holes' mobility actual value in 3C-SiC. However, the values adopted in Table 5 are suggested from recent measurements [16, 17]. The mobility of carriers for the temperature range of 250–700 K was described in [12]. In high field conditions, with magnitude of values as shown in Figure 7, the mobility and velocity of carriers become inseparable directly affecting each other. The Canali model, Eq. (7) is utilized for these purposes and its parameters for SiC are presented in Table 7. In Eq. (8), the holes' saturation velocity

determines the range of electric field values at 200 kV/cm < E < 2000 kV/cm [12].

<sup>μ</sup>0ð Þ¼ <sup>E</sup> ð Þ <sup>α</sup> <sup>þ</sup> <sup>1</sup> <sup>μ</sup>low

<sup>α</sup> <sup>þ</sup> <sup>1</sup> <sup>þ</sup> ð Þ <sup>α</sup>þ<sup>1</sup> <sup>μ</sup>low<sup>E</sup>

vsat <sup>β</sup> 1=<sup>β</sup>

<sup>α</sup> as illustrated in Figure 6. Each

NC,Vð Þ¼ <sup>T</sup> NC,V<sup>300</sup> � ð Þ <sup>T</sup>=<sup>300</sup> <sup>3</sup>=<sup>2</sup> (5)

Par <sup>¼</sup> Par<sup>0</sup> � ð Þ <sup>T</sup>=300<sup>K</sup> <sup>γ</sup> (6)

(7)

) the

results for limited temperature range of 200–500 K.

24 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Thomas (C-T) model μ<sup>0</sup> ¼ μmin þ μmax � μmin

bandgap narrowing is considered negligible.


Table 6. SiC parameters for low field mobility and coefficients used to express temperature dependence.

Figure 7. The models for SiC electrons' velocity allow accurate TCAD simulations for temperatures up to 600 K. Comparison with literature data for 3C-SiC [21] and 4H-SiC [19] is performed. A doping level of 5 � <sup>10</sup><sup>15</sup> cm�<sup>3</sup> is assumed.


Table 7. SiC parameters for high field mobility and saturation velocity along with coefficients used to express temperature dependence.

$$
\upsilon\_{sat} = \upsilon\_{sat,0} \left(\frac{\text{300K}}{T}\right)^{\upsilon\_{sat,\text{exp}}} \tag{8}
$$

metallic-type conduction mechanism starts [22]. The degeneracy factor temperature dependence can be expressed by Eq. (11), whilst the typical values for gA is 4 and for gD is 2 for the impurity

The impact ionization coefficients of electrons and holes need to be determined to specify the breakdown voltage [24]. For 3C-SiC, the Chynoweth law αð Þ¼ Eava γ∙α∙exp ð Þ �γb=Eava can be adopted. The parameter values are determined in Table 9, following the work of van Overstraeten-de Man [25]. The temperature dependence of these parameters is expressed by

> ] 1.28 � 10<sup>6</sup>

> > 106

Optical phonon energy ħωop [eV] 0.120 0.120 0.190 0.190 0.190 0.190

bn,p [V/cm] 5.54 �

GA,Dð Þ¼ T gA,D � exp

determining the optical phonon energy as indicated by γ ¼ tanh ħωop=2kT<sup>0</sup>

name

Low field range up to this value E0 [V/cm] 4.0 � <sup>10</sup><sup>5</sup> 4.0 �

Table 9. SiC impact ionization coefficients for T<sup>0</sup> ¼ 300 K

an,p [cm�<sup>1</sup>

=kT NA,D < Ncrit (9)

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

kT (11)

3C-SiC 4H-SiC

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27

=tanh ħωop=2kT .

2.1 � <sup>10</sup><sup>7</sup> 2.96 � 107

1.7 � <sup>10</sup><sup>7</sup> 1.6 � 107

3C-SiC 4H-SiC [┴ to c-axis] 4H-SiC [// to c-axis] Electrons Holes Electrons Holes Electrons Holes

> 3.3 � <sup>10</sup><sup>7</sup> 2.5 � 107

3.41 � 108

— —— —

1.76 � 108

NA,D<sup>0</sup> ¼ NA,D NA,D ≥ Ncrit (10)

1.07 � 107

1.12 � 107

105

ΔEA,D

levels of acceptors and donors in SiC, respectively [23]:

The formed energy level is considered from the conduction band (EC). <sup>b</sup> The formed energy level is considered from the valence band (EV).

Table 8. SiC impurities/shallow traps due to doping.

2.1.3. Impact ionization

Parameters description Parameter

Ionization coefficients for electrons

and holes

a

NA,D<sup>0</sup> ¼ NA,D= 1 þ GA∗ EA,D � E<sup>f</sup>

Impurity Species type Energy levels [eV]

Nitrogen (N) Donor<sup>a</sup> 0.057 0.071 Vanadium (V) Donor<sup>a</sup> 0.660 0.800 Aluminium (Al) Acceptor<sup>b</sup> 0.260 0.265 Gallium (Ga) Acceptor<sup>b</sup> 0.343 0.300 Boron (B) Acceptor<sup>b</sup> 0.735 0.293

#### 2.1.2. Doping and incomplete ionization

Compared to silicon, dopants in wide bandgap semiconductors have larger ionization energies, making activation of the doping species an issue. The dopant impurities are better modeled as traps to account for the phenomenon of incomplete ionization. As shown in Table 8, the formed energy levels depend on the polytype and the impurity. To model this behaviour, Eqs. (9) and (10) are utilized, where NA,D is the doping concentration, NA,D<sup>0</sup> is the effective doping concentration, EA,D and Ef are the activation energy, and the Fermi level, respectively, GA is the degeneracy factor, and Ncrit is the value that determines where the


The formed energy level is considered from the valence band (EV).

Table 8. SiC impurities/shallow traps due to doping.

metallic-type conduction mechanism starts [22]. The degeneracy factor temperature dependence can be expressed by Eq. (11), whilst the typical values for gA is 4 and for gD is 2 for the impurity levels of acceptors and donors in SiC, respectively [23]:

$$\mathbf{N}\_{A,D'} = \mathbf{N}\_{A,D} / \left( \mathbf{1} + \mathbf{G}\_A \ast \left( \mathbf{E}\_{A,D} - \mathbf{E}\_f \right) / \mathbf{k} \mathbf{T} \right) \tag{9}$$

$$\mathbf{N}\_{\mathbf{A}, D'} = \mathbf{N}\_{\mathbf{A}, D} \tag{10}$$

$$\mathbf{G}\_{A,D}(T) = \mathbf{g}\_{A,D} \cdot \exp\left(\frac{\Delta E\_{A,D}}{kT}\right) \tag{11}$$

#### 2.1.3. Impact ionization

vsat ¼ vsat,<sup>0</sup>

beta (β0) 0.75 2.5 1.2 1.2 1.2 γbeta �0.9 0 1.0 1.0 1.0 alpha (α) 00 0 0 0 vsat,0 [cm/sec] 2.5 � 107 1.63 � <sup>10</sup><sup>7</sup> 2.2 � <sup>10</sup><sup>7</sup> 1.9 � <sup>10</sup><sup>7</sup> 2.2 � <sup>10</sup><sup>7</sup> vsat,exp �0.65 1.55 0.44 0.44 0.44

Figure 7. The models for SiC electrons' velocity allow accurate TCAD simulations for temperatures up to 600 K. Comparison with literature data for 3C-SiC [21] and 4H-SiC [19] is performed. A doping level of 5 � <sup>10</sup><sup>15</sup> cm�<sup>3</sup> is assumed.

Table 7. SiC parameters for high field mobility and saturation velocity along with coefficients used to express

2.1.2. Doping and incomplete ionization

temperature dependence.

Parameter 3C-SiC 4H-SiC

26 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

300K T vsat, exp

Electrons Holes Electrons [┴ to c-axis] Electrons [// to c-axis] Holes

Compared to silicon, dopants in wide bandgap semiconductors have larger ionization energies, making activation of the doping species an issue. The dopant impurities are better modeled as traps to account for the phenomenon of incomplete ionization. As shown in Table 8, the formed energy levels depend on the polytype and the impurity. To model this behaviour, Eqs. (9) and (10) are utilized, where NA,D is the doping concentration, NA,D<sup>0</sup> is the effective doping concentration, EA,D and Ef are the activation energy, and the Fermi level, respectively, GA is the degeneracy factor, and Ncrit is the value that determines where the

(8)

The impact ionization coefficients of electrons and holes need to be determined to specify the breakdown voltage [24]. For 3C-SiC, the Chynoweth law αð Þ¼ Eava γ∙α∙exp ð Þ �γb=Eava can be adopted. The parameter values are determined in Table 9, following the work of van Overstraeten-de Man [25]. The temperature dependence of these parameters is expressed by determining the optical phonon energy as indicated by γ ¼ tanh ħωop=2kT<sup>0</sup> =tanh ħωop=2kT .


Table 9. SiC impact ionization coefficients for T<sup>0</sup> ¼ 300 K

Notably, it has been found in [26] that these values are relatively insensitive to temperature variations in the range of 300 K < T < 500 K. For 4H-SiC, a slightly different model is utilized after Hatakeyama's work [27] to effectively describe the anisotropic behaviour of the avalanche coefficients. The avalanche force is considered to have two components to account for the anisotropic structure of 4H-SiC [28], satisfying <sup>F</sup><sup>2</sup> <sup>¼</sup> <sup>F</sup><sup>2</sup> == <sup>þ</sup> <sup>F</sup><sup>2</sup> ┴. Utilizing the projections of these electric field components, the avalanche coefficients can be computed as indicated in Eqs. (12)–(15), with the default value of θ ¼ 1:

$$a = a\_{\bullet}^{\left(\frac{B \cdot F\_{\bullet}}{b\_{\bullet} \cdot J}\right)^2} \cdot a\_{\prime/\prime}^{\left(\frac{B \cdot F\_{\prime/\prime}}{b\_{\bullet} \cdot J}\right)^2} \tag{12}$$

$$b = B\sqrt{1 - \theta A^2 \left(\frac{BF\_\bullet F\_{//}}{Fb\_\bullet b\_{//}}\right)^2} \tag{13}$$

$$A = \log \frac{a\_{\parallel}}{a\_{\oplus}} \tag{14}$$

τdop ¼ τmin þ

] 1.0 � <sup>10</sup><sup>19</sup> 1.0 � <sup>10</sup><sup>18</sup>

Parameter 3C-SiC 4H-SiC

T T0 � �

T T0 � �

compound of interest, which in turn would give more accurate simulations.

þ Cn

þ Cp

GaN-based devices utilize GaN, AlGaN and AlN materials. AlGaN is a molar fraction of AlN and GaN. GaN and AlGaN naturally form Wurtzite crystal structures with the ability of forming different Ga and N faces. For this chapter, only the Ga-face is considered. In TCAD, it is necessary to define the material properties of AlN and GaN separately. AlGaN material properties are thereafter approximated through a linear interpolation, depending on the molar fraction of AlN and GaN. A more accurate result can be yielded wherever the molar compounds are known and experimental evaluation of their properties has been performed. In those cases, new material parameters can be made which would reflect the exact molar

Similar to modelling SiC, the important parameters include modelling the bandgap, doping

Like all III-Nitride semiconductors, GaN and AlN are direct bandgap semiconductors, that is, the maximum valley in their valance band is directly below the minimum conduction valley. Similar to SiC examined earlier, Eg cannot be assumed constant in value and will vary heavily with temperature and doping concentration. Again, like SiC, thermally exciting GaN leads to lower band gap energies. According to Eq. (1) the variation of bandgap value can be described

and incomplete ionization, impact ionization, mobility and generation-recombination.

T T0 � �<sup>2</sup> ! <sup>1</sup> <sup>þ</sup> Hnexp � <sup>n</sup>

T T0 � �<sup>2</sup> ! <sup>1</sup> <sup>þ</sup> Hpexp � <sup>p</sup>

Cnð Þ¼ T; n An þ Bn

Table 11. SiC Auger recombination rates.

Cpð Þ¼ T; p Ap þ Bp

2.2. Gallium nitride

A [cm<sup>6</sup>

B [cm6

C [cm6

N0 [cm�<sup>3</sup>

2.2.1. Band parameters

utilizing the parameters in Table 12 [29].

τmax � τmin <sup>1</sup> <sup>þ</sup> NA, <sup>0</sup>þND, <sup>0</sup>

Electrons Holes Electrons Holes

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

/sec] 0.3 � <sup>10</sup>�<sup>31</sup> 0.2 � <sup>10</sup>�<sup>31</sup> 6.7 � <sup>10</sup>�<sup>32</sup> 7.2 � <sup>10</sup>�<sup>32</sup>

/sec] <sup>0</sup> <sup>0</sup> 2.45 � <sup>10</sup>�<sup>31</sup> 4.5 � <sup>10</sup>�<sup>33</sup>

/sec] <sup>0</sup> <sup>0</sup> �2.2 � <sup>10</sup>�<sup>32</sup> 2.63 � <sup>10</sup>�<sup>32</sup>

H 1.9 1.9 3.47 8.26

T0 [K] 300 300 300 300

Nref � �<sup>γ</sup> (16)

<sup>N</sup>0, n � � � � (17)

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29

<sup>N</sup>0, p � � � � (18)

$$B = \frac{F}{\sqrt{\left(\frac{F\_\bullet}{b\_\bullet}\right)^2 + \left(\frac{F\_{\prime\prime}}{b\_{\prime\prime}}\right)^2}}\tag{15}$$

#### 2.1.4. Generation-recombination

The doping dependence of the SRH lifetime is modeled with Scharfetter in Eq. (16). The bandto-band non-radiative recombination is expressed with the Auger recombination rates, RA net <sup>¼</sup> Cnn <sup>þ</sup> Cpp � � np � <sup>n</sup><sup>2</sup> i,eff � �. As shown in Eqs. (17) and (18), the effect of temperature and doping is accounted for. Typical values for the Scharfetter and Auger models are shown in Tables 10 and 11. However, since these are heavily process dependent, they need to be adjusted every time the process conditions change:


Table 10. SiC SRH lifetime parameter set.


Table 11. SiC Auger recombination rates.

Notably, it has been found in [26] that these values are relatively insensitive to temperature variations in the range of 300 K < T < 500 K. For 4H-SiC, a slightly different model is utilized after Hatakeyama's work [27] to effectively describe the anisotropic behaviour of the avalanche coefficients. The avalanche force is considered to have two components to account for

these electric field components, the avalanche coefficients can be computed as indicated in

<sup>B</sup>�F== b==�F � �<sup>2</sup>

Fb┴b==

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi <sup>1</sup> � θΑ<sup>2</sup> <sup>Β</sup>F┴F==

> a== a┴

<sup>þ</sup> <sup>F</sup>== b==

� �<sup>2</sup> <sup>s</sup>

A ¼ log

<sup>B</sup> <sup>¼</sup> <sup>F</sup> ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi F┴ b┴ � �<sup>2</sup>

The doping dependence of the SRH lifetime is modeled with Scharfetter in Eq. (16). The bandto-band non-radiative recombination is expressed with the Auger recombination rates,

doping is accounted for. Typical values for the Scharfetter and Auger models are shown in Tables 10 and 11. However, since these are heavily process dependent, they need to be

τmin [sec] 0 0

γ 0.3 0.3 T<sup>α</sup> 1.72 1.72 Τcoef 2.55 2.55 Etrap [eV] 0 0

<sup>τ</sup>max [sec] 2.5 � <sup>10</sup>�<sup>6</sup> 0.5 � <sup>10</sup>�<sup>6</sup>

] 1 � <sup>10</sup><sup>17</sup> <sup>1</sup> � <sup>10</sup><sup>17</sup>

a ¼ a <sup>B</sup>�F┴ ð Þ <sup>b</sup>┴�<sup>F</sup> 2 ┴ � a

b ¼ B

== <sup>þ</sup> <sup>F</sup><sup>2</sup>

┴. Utilizing the projections of

(13)

(14)

== (12)

� �<sup>2</sup> <sup>r</sup> (15)

. As shown in Eqs. (17) and (18), the effect of temperature and

Electrons Holes

the anisotropic structure of 4H-SiC [28], satisfying <sup>F</sup><sup>2</sup> <sup>¼</sup> <sup>F</sup><sup>2</sup>

28 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Eqs. (12)–(15), with the default value of θ ¼ 1:

2.1.4. Generation-recombination

net <sup>¼</sup> Cnn <sup>þ</sup> Cpp � � np � <sup>n</sup><sup>2</sup>

i,eff � �

adjusted every time the process conditions change:

Parameter SiC

Table 10. SiC SRH lifetime parameter set.

RA

Nref [cm�<sup>3</sup>

$$\tau\_{dop} = \tau\_{min} + \frac{\tau\_{\text{max}} - \tau\_{\text{min}}}{1 + \left(\frac{N\_{A\_c0} + N\_{D,0}}{N\_{nf}}\right)^{\gamma}} \tag{16}$$

$$\mathbb{C}\_{n}(T, n) = \left( A\_{n} + B\_{n} \left( \frac{T}{T\_{0}} \right) + \mathbb{C}\_{n} \left( \frac{T}{T\_{0}} \right)^{2} \right) \left[ 1 + H\_{n} \exp \left( - \frac{n}{N0, n} \right) \right] \tag{17}$$

$$\mathbb{C}\_{p}(T, p) = \left( A\_{p} + B\_{p} \left( \frac{T}{T\_{0}} \right) + \mathbb{C}\_{p} \left( \frac{T}{T\_{0}} \right)^{2} \right) \left[ 1 + H\_{p} \exp \left( - \frac{p}{N \mathbf{0}, p} \right) \right] \tag{18}$$

#### 2.2. Gallium nitride

GaN-based devices utilize GaN, AlGaN and AlN materials. AlGaN is a molar fraction of AlN and GaN. GaN and AlGaN naturally form Wurtzite crystal structures with the ability of forming different Ga and N faces. For this chapter, only the Ga-face is considered. In TCAD, it is necessary to define the material properties of AlN and GaN separately. AlGaN material properties are thereafter approximated through a linear interpolation, depending on the molar fraction of AlN and GaN. A more accurate result can be yielded wherever the molar compounds are known and experimental evaluation of their properties has been performed. In those cases, new material parameters can be made which would reflect the exact molar compound of interest, which in turn would give more accurate simulations.

Similar to modelling SiC, the important parameters include modelling the bandgap, doping and incomplete ionization, impact ionization, mobility and generation-recombination.

#### 2.2.1. Band parameters

Like all III-Nitride semiconductors, GaN and AlN are direct bandgap semiconductors, that is, the maximum valley in their valance band is directly below the minimum conduction valley. Similar to SiC examined earlier, Eg cannot be assumed constant in value and will vary heavily with temperature and doping concentration. Again, like SiC, thermally exciting GaN leads to lower band gap energies. According to Eq. (1) the variation of bandgap value can be described utilizing the parameters in Table 12 [29].


Table 12. GaN/AlN parameter set related to bandgap.

Further, utilizing Eq. (19), the intrinsic carrier concentration of the GaN material can be calculated. This premises that the DoS and/or the effective carrier masses in this WBG material are known. Equations (20) and (21) adequately describe this temperature dependent procedure. The intrinsic characteristics of GaN can then be given by [30]:

$$\mathbf{n}\_{\mathrm{i}} = (\mathbf{N}\_{\mathrm{c}} \cdot \mathbf{N}\_{\mathrm{v}})^{1/2} \exp\left(-\mathrm{E}\_{\mathrm{g}}/(2\mathrm{k}\_{\mathrm{B}}\mathrm{T})\right) \tag{19}$$

model, in Eq. (22), is preferred to describe the doping dependence, with the fitting parameters

Table 14. GaN/AlN parameters for high field mobility and saturation velocity along with coefficients used to express

of the maximum mobility parameter, as described by Eq. (6). This is the only temperature

The calculated mobility in low field conditions is utilized in the Canali model, as discussed in SiC section with Eq. (7). The parameter values presented in Table 14 enable modelling the mobility in high field conditions while taking into consideration the temperature dependence

Dopants in this WBG semiconductor would not fully ionize even at high temperatures [32] because the impurities form deep levels, as further observed in Table 15 [33–38]. The models as presented in Eqs. (9)–(11) can be utilized here following the same degeneracy factor values for the conduction and valence bands [39]. That is, gA equals 4 for shallow acceptors and gD equals

The Van Overstraetan-de Man expression, described in SiC section, with the parameters in Table 16 can be used to model the impact ionization phenomenon [29]. It is worth noticing that for the case of high electric fields (i.e. larger than the E0 value) the impact ionization coefficients

The non-radiative recombination [41], SRH, is described by the Scharfetter model in Eq. (15) is considered a dominant process in the bulk. Table 17 includes the relevant parameter values. Auger recombination process is realized utilizing Eqs. (17)–(18) along with the coefficient

<sup>þ</sup> <sup>μ</sup>const � <sup>μ</sup>min2 <sup>1</sup> <sup>þ</sup> NA,0<sup>þ</sup> ND,<sup>0</sup> Cr

Electrons Holes Electrons Holes

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

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31

indicates the coefficient for the temperature dependency

<sup>1</sup> <sup>þ</sup> Cs NA,0þND,<sup>0</sup>

<sup>β</sup> (22)

<sup>α</sup> � <sup>μ</sup><sup>1</sup>

shown in Table 13. In this table, γμmax

temperature dependence.

μdop ¼ μmin1exp

2.2.3. Doping and incomplete ionization

are predicted to be similar in GaN [40].

2.2.5. Generation-recombination

with Eq. (6).

2 for shallow donors.

2.2.4. Impact ionization

dependent parameter that the Masetti model accounts for:

Parameter GaN AlN

beta (β0) 7.2044 4 17.3681 4 γbeta 6.1973 0 8.7253 0 alpha (α) 0.7857 0 0.8554 0 vsat,0 [cm/sec] 1.3�107 1.7�107 1.5�10<sup>7</sup> 1.25�10<sup>7</sup> vsat,exp 0.7 0.725 2 2

> Pc NA, <sup>0</sup> þ ND,<sup>0</sup>

$$\text{N}\_{\text{c}}\text{''} = 4.82 \times 10^{15} \cdot \left(\text{m}\_{\text{l}}\text{/m}\_{\text{0}}\right)^{3/2} \text{T}^{3/2} \left(\text{cm}^{-3}\right) \text{''} = 4.3 \times 10^{14} \times \text{T}^{3/2} \left(\text{cm}^{-3}\right) \tag{20}$$

$$\text{N}\_{\text{v}} = 8.9 \times 10^{15} \times \text{T}^{3/2} \text{ (cm}^{-3}\text{)}\tag{21}$$

#### 2.2.2. Mobility

The low field carriers' mobility for the bulk WBG compound depends on the carriers' density following the C-T formula, as illustrated in SiC physical model. However, variations of this model exist to fit better some compound semiconductors behaviour. In SiC above, the so-called Arora model is utilized originating from the C-T model. It provides additional control on the temperature dependence of SiC low field mobility parameters. For GaN and AlN, the Masetti


Table 13. Coefficients used for temperature and doping (Masetti model) dependency of low field mobility in GaN and AlN.


Table 14. GaN/AlN parameters for high field mobility and saturation velocity along with coefficients used to express temperature dependence.

model, in Eq. (22), is preferred to describe the doping dependence, with the fitting parameters shown in Table 13. In this table, γμmax indicates the coefficient for the temperature dependency of the maximum mobility parameter, as described by Eq. (6). This is the only temperature dependent parameter that the Masetti model accounts for:

$$\mu\_{dup} = \mu\_{\min1} \exp\left(\frac{P\_c}{N\_{A,0} + N\_{D,0}}\right) + \frac{\mu\_{\text{const}} - \mu\_{\min2}}{1 + \left(\frac{N\_{A,0} + N\_{D,0}}{C\_r}\right)^{\alpha}} - \frac{\mu\_1}{1 + \left(\frac{C\_r}{N\_{A,0} + N\_{D,0}}\right)^{\beta}}\tag{22}$$

The calculated mobility in low field conditions is utilized in the Canali model, as discussed in SiC section with Eq. (7). The parameter values presented in Table 14 enable modelling the mobility in high field conditions while taking into consideration the temperature dependence with Eq. (6).

#### 2.2.3. Doping and incomplete ionization

Dopants in this WBG semiconductor would not fully ionize even at high temperatures [32] because the impurities form deep levels, as further observed in Table 15 [33–38]. The models as presented in Eqs. (9)–(11) can be utilized here following the same degeneracy factor values for the conduction and valence bands [39]. That is, gA equals 4 for shallow acceptors and gD equals 2 for shallow donors.

#### 2.2.4. Impact ionization

Further, utilizing Eq. (19), the intrinsic carrier concentration of the GaN material can be calculated. This premises that the DoS and/or the effective carrier masses in this WBG material are known. Equations (20) and (21) adequately describe this temperature dependent proce-

Parameters description GaN AlN Eg(0) [eV] 3.507 6.23 <sup>α</sup> [eV/K] 9.1�10�<sup>4</sup> 1.79�10�<sup>3</sup> <sup>β</sup> [Κ] <sup>836</sup> 1.462�103

The low field carriers' mobility for the bulk WBG compound depends on the carriers' density following the C-T formula, as illustrated in SiC physical model. However, variations of this model exist to fit better some compound semiconductors behaviour. In SiC above, the so-called Arora model is utilized originating from the C-T model. It provides additional control on the temperature dependence of SiC low field mobility parameters. For GaN and AlN, the Masetti

/Vs] 1500 [31] – 1800 [29] 20 300 14

/Vs] 85 33 20 11

/Vs] 75 0 65 0

/Vs] 50 20 20 10

α 0.55 0.55 0.88 1.05 β 0.75 0.7 0.75 0.75

] 6.5�1015 <sup>5</sup>�10<sup>15</sup> <sup>8</sup>�10<sup>17</sup> <sup>5</sup>�10<sup>18</sup>

] 9.5�10<sup>16</sup> <sup>8</sup>�10<sup>16</sup> <sup>7</sup>�10<sup>16</sup> <sup>8</sup>�10<sup>17</sup>

] 7.2�10<sup>19</sup> <sup>8</sup>�10<sup>20</sup> 5.2�10<sup>17</sup> <sup>8</sup>�10<sup>18</sup>

Table 13. Coefficients used for temperature and doping (Masetti model) dependency of low field mobility in GaN and

Electrons Holes Electrons Holes

1 2.1 1 2.1

exp �Eg=ð Þ 2kBT (19)

<sup>T</sup><sup>3</sup>=<sup>2</sup> cm�<sup>3</sup> ˜ <sup>¼</sup> <sup>4</sup>:<sup>3</sup> � 1014 � <sup>T</sup><sup>3</sup>=<sup>2</sup> cm�<sup>3</sup> (20)

Nv <sup>¼</sup> <sup>8</sup>:<sup>9</sup> � 1015 � T3=<sup>2</sup> cm�<sup>3</sup> (21)

dure. The intrinsic characteristics of GaN can then be given by [30]:

30 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Parameter GaN AlN

Nc˜ <sup>¼</sup> <sup>4</sup>:82 1015 � ð Þ <sup>m</sup>Γ=m0

Table 12. GaN/AlN parameter set related to bandgap.

2.2.2. Mobility

μconst [cm<sup>2</sup>

<sup>μ</sup>min1 [cm<sup>2</sup>

<sup>μ</sup>min2 [cm<sup>2</sup>

<sup>μ</sup><sup>1</sup> [cm<sup>2</sup>

Pc [cm�<sup>3</sup>

Cr [cm�<sup>3</sup>

Cs [cm�<sup>3</sup>

AlN.

γμmax

ni <sup>¼</sup> ð Þ Nc � Nv <sup>1</sup>=<sup>2</sup>

3=2

The Van Overstraetan-de Man expression, described in SiC section, with the parameters in Table 16 can be used to model the impact ionization phenomenon [29]. It is worth noticing that for the case of high electric fields (i.e. larger than the E0 value) the impact ionization coefficients are predicted to be similar in GaN [40].

#### 2.2.5. Generation-recombination

The non-radiative recombination [41], SRH, is described by the Scharfetter model in Eq. (15) is considered a dominant process in the bulk. Table 17 includes the relevant parameter values. Auger recombination process is realized utilizing Eqs. (17)–(18) along with the coefficient


a The formed energy level is considered from the Conduction band (EC) <sup>b</sup>

The formed energy level is considered from the Valence band (EV)

Table 15. Impurities and shallow traps due to doping in GaN/AlN


2.3. Diamond

Nref [cm<sup>3</sup>

A [cm<sup>6</sup>

B [cm6

C [cm6

N0 [cm<sup>3</sup>

] 1<sup>10</sup><sup>16</sup>

Table 17. GaN/AlN SRH lifetime parameter set.

Table 18. GaN Auger recombination rates.

Parameter GaN

be added manually.

2.3.1. Band parameters

Diamond (C) is considered to be a strong contester for high power due to its outstanding electrical and thermal material properties [44]. However, the realization of power semiconductor devices based on this material is extremely difficult and such devices are currently at the research level. The main reason is that there are not enough activated carriers at room temperature, leading to poor device performance. Furthermore, diamond is also extremely expensive to

/sec] 3.0<sup>10</sup><sup>31</sup> 3.0<sup>10</sup><sup>31</sup>

] 1.0<sup>10</sup><sup>18</sup> 1.0<sup>10</sup><sup>18</sup>

/sec] 0 0

/sec] 0 0 H 0 0

T0 [K] 300 300

Parameter GaN AlN

<sup>τ</sup>max [sec] 0.7<sup>10</sup><sup>11</sup> 2.0<sup>10</sup><sup>11</sup> 1.0<sup>10</sup><sup>9</sup>

τmin [sec] 0 0 0 0

γ 1 1 11 T<sup>α</sup> 1.5 1.5 1.5 1.5 Τcoef 2.5 2.5 2.5 2.5

Electrons Holes Electrons Holes

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Electrons Holes

It is worth mentioning that since diamond is at very early stages of development, it is also at very early stage at the material characterization and modelling. Currently, diamond does not exist in the material libraries of the commercial TCAD simulation packages. As a result, all material properties and fitting parameters of various materials interface with diamond need to

The experimentally extracted value of diamond bandgap (Eg) is about 5.47 eV at room temperature [45]. This value directly translated into high material critical electric strength. High

fabricate due to large scale material growth constrains.

Table 16. GaN/AlN impact ionization coefficients for T<sup>0</sup> ¼ 300 K

values shown in Table 18 [42]. Auger recombination in nitrides is responsible for the loss of quantum efficiency in InGaN-based light emitters [43]. This non-radiative loss mechanism is due to the large values of the Auger coefficients (2 � <sup>10</sup>�<sup>30</sup> cm<sup>6</sup> /s) for specific parts of the emission spectrum, like blue to green region.


Table 17. GaN/AlN SRH lifetime parameter set.


Table 18. GaN Auger recombination rates.

#### 2.3. Diamond

Diamond (C) is considered to be a strong contester for high power due to its outstanding electrical and thermal material properties [44]. However, the realization of power semiconductor devices based on this material is extremely difficult and such devices are currently at the research level. The main reason is that there are not enough activated carriers at room temperature, leading to poor device performance. Furthermore, diamond is also extremely expensive to fabricate due to large scale material growth constrains.

It is worth mentioning that since diamond is at very early stages of development, it is also at very early stage at the material characterization and modelling. Currently, diamond does not exist in the material libraries of the commercial TCAD simulation packages. As a result, all material properties and fitting parameters of various materials interface with diamond need to be added manually.

#### 2.3.1. Band parameters

values shown in Table 18 [42]. Auger recombination in nitrides is responsible for the loss of quantum efficiency in InGaN-based light emitters [43]. This non-radiative loss mechanism is

Low field range up to this value E0 [V/cm] 4.0�105 4.0�10<sup>5</sup> 4.0�10<sup>5</sup> 4.0�10<sup>5</sup> Optical phonon energy ħωop [eV] 0.035 0.035 0.035 0.035

Parameters description Parameter name GaN AlN

/s) for specific parts of the

Electrons Holes Electrons Holes

] 1.5�10<sup>5</sup> 6.4�10<sup>5</sup> 2.9�10<sup>8</sup> 1.34�10<sup>7</sup>

bn,p [V/cm] 1.41�10<sup>7</sup> 1.46�10<sup>7</sup> 3.4�10<sup>8</sup> 2.03�10<sup>8</sup>

due to the large values of the Auger coefficients (2 � <sup>10</sup>�<sup>30</sup> cm<sup>6</sup>

Impurity Species type Energy levels [eV]

32 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The formed energy level is considered from the Conduction band (EC) <sup>b</sup> The formed energy level is considered from the Valence band (EV)

Table 15. Impurities and shallow traps due to doping in GaN/AlN

Ionization coefficients for electrons and holes an,p [cm�<sup>1</sup>

Table 16. GaN/AlN impact ionization coefficients for T<sup>0</sup> ¼ 300 K

GaN AlN

Silicon (Si) Donor<sup>a</sup> 0.017 — —— Nitrogen (N) Donor<sup>a</sup> — — 1.4–1.85 — Vacancy (VN) Donor<sup>a</sup> — 0.03–0.1 — 0.17 Carbon (C) Donor<sup>a</sup> 0.11–0.14 — 0.2 — Magnesium (Mg) Donor<sup>a</sup> — 0.26, 0.6 — — Vacancy (VGA) Acceptor<sup>b</sup> 0.14 — —— Silicon (Si) Acceptor<sup>b</sup> 0.19 — —— Magnesium (Mg) Acceptor<sup>b</sup> — 0.14–0.21 0.1 — Zinc (Zn) Acceptor<sup>b</sup> 0.21–0.34 — 0.2 — Mercury (Hg) Acceptor<sup>b</sup> 0.41 — —— Cadmium (Cd) Acceptor<sup>b</sup> 0.55 — —— Beryllium (Be) Acceptor<sup>b</sup> 0.7 — —— Lithium (Li) Acceptor<sup>b</sup> 0.75 — —— Carbon (C) Acceptor<sup>b</sup> — 0.89 — 0.4 Gallium (Ga) Acceptor<sup>b</sup> — 0.59–1.09 — — Aluminium (Al) Donor<sup>a</sup> ——— 3.4–4.5 Vacancy (VAl) Acceptor<sup>b</sup> — — 0.5 —

Ga N Al N

emission spectrum, like blue to green region.

a

The experimentally extracted value of diamond bandgap (Eg) is about 5.47 eV at room temperature [45]. This value directly translated into high material critical electric strength. High breakdown field strength means that the material can withstand high potential drops across very thin layers thus minimizing the on-state resistance of the device allowing for the fabrication of highly energy efficient high voltage high current devices.

The values for the density of states for the valence and the conduction band (Nv,Nc) are given by expressions Eq. (5) where in this case Nv300 = 1.8e19 and Nc300 = 5e18 [cm�<sup>3</sup> ], as reported in [22, 44–47]. Therefore, the appropriate levels of density of state could be calculated using Eq. (19). For CVD diamond this value is around 1.2 � <sup>10</sup>�<sup>27</sup> cm�<sup>3</sup> [22] at 300 K, Eg is the bandgap, T is the absolute temperature in Kelvin and k the Boltzmann constant (1.38 � <sup>10</sup>�<sup>23</sup> J/K). This value is extremely small for any meaningful numerical analysis using TCAD simulations. Therefore, possible strategies to facilitate and match experimental results include adding a fitting coefficient/value for intrinsic concentration, activating the constant carrier generation models or including trap levels and recombination centres in the materials bandwidth [22].

#### 2.3.2. Doping and incomplete ionization

Diamond doping either of n-type or p-type to a less extent is challenging; in order to develop accurate and reliable simulation models one has to include the incomplete ionization models with the appropriate coefficients. It is therefore necessary to use the 'incomplete ionization model' [48] (Figure 8). The equations implemented follow the model described in Eqs. (9) and (10). Note that the degeneracy factor in this particular case is a function of temperature, given by the model in Eq. (23):

$$\mathbf{g}\_{A,D} = 4 + 2 \exp\left(-\Delta \mathbf{g}\_{A,D} / (kT)\right) \tag{23}$$

2.3.3. Mobility

2.3.4. Impact ionization

in Table 19:

3. Device modelling and simulation

For an intrinsic diamond, the hole mobility is up to 3800 cm2

Ionization coefficients for electrons and holes an (cm�<sup>1</sup>

Table 19. Avalanche coefficients for diamond.

mobility on the doping and on the temperature using with a single model.

diamond the mobility is dominated by the concentration dependent scattering. At elevated temperatures, above 325 K it has been shown that the mobility is decreased due to acoustic phonon scattering [48, 49]. The combination of p+ doped diamond leads to lattice scattering. It therefore is advisable that these complex relationships between mobility, doping and temperature are taken into consideration when diamond simulations are implemented. A fairly accurate model, the unified mobility model (UniBo) [50] accounts for the dependence of the

Diamond [22] 1.89�105 5.48�10<sup>6</sup> 1.7�10<sup>7</sup> 1.42�10<sup>7</sup>

) ap (cm�<sup>1</sup>

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

Impact ionization integral coefficients for electron and holes are very important in the design of diamond devices with the appropriate values been included in the impact ionization models parameters. Under reverse bias conditions, the increase of the ionization integral towards unity indicates the increase in the generation of avalanche carriers due to impact ionization, leading eventually to the device breakdown. The avalanche coefficients are given by Eq. (24) where in which an,p, bn,p and cn,p are fitting parameters and E is the lateral electric field through the semiconductor layer. The numerical values for both diamond and silicon are given

Due to the very low intrinsic carrier concentration of WBG semiconductors, the expected leakage current is very low (� <sup>10</sup>�<sup>20</sup>Acm�2), which causes converge issues. To alleviate from this, the numerical precision should be significantly high. This is achieved with the inclusion of certain keywords in the 'Device (and Circuit) Simulation' tool command file (e.g. 'Extended-Precision' for SDevice tool of the Synopsys Sentaurus TCAD). Simulations that use extended arithmetic precision are computational more intensive, therefore, the arithmetic precision should be increased in a trade-off manner up to a level that is able to provide a solution.

A further method utilized to improve convergence issues, especially when simulating the blocking characteristics, is to add extra carriers' generation through an equivalent keyword in the command file. The latter can increase the leakage current to levels that are high enough (e.g. > 10�<sup>10</sup>Acm�2) for the simulations to converge at lower precision level. This

<sup>Α</sup> <sup>¼</sup> an,pexp �bn,p=<sup>E</sup> cn,<sup>p</sup> (24)

/(Vs) whereas for boron-doped

) bp (Vcm�<sup>1</sup>

)

35

) bn (Vcm�<sup>1</sup>

http://dx.doi.org/10.5772/intechopen.76062

Figure 8. (a) Incomplete ionization model implemented for boron in single crystal diamond and (b) variation of activation energy with doping concentration of boron [22].


Table 19. Avalanche coefficients for diamond.

#### 2.3.3. Mobility

breakdown field strength means that the material can withstand high potential drops across very thin layers thus minimizing the on-state resistance of the device allowing for the fabrica-

The values for the density of states for the valence and the conduction band (Nv,Nc) are given

in [22, 44–47]. Therefore, the appropriate levels of density of state could be calculated using Eq. (19). For CVD diamond this value is around 1.2 � <sup>10</sup>�<sup>27</sup> cm�<sup>3</sup> [22] at 300 K, Eg is the bandgap, T is the absolute temperature in Kelvin and k the Boltzmann constant (1.38 � <sup>10</sup>�<sup>23</sup> J/K). This value is extremely small for any meaningful numerical analysis using TCAD simulations. Therefore, possible strategies to facilitate and match experimental results include adding a fitting coefficient/value for intrinsic concentration, activating the constant carrier generation models or including trap levels and recombination centres in the materials

Diamond doping either of n-type or p-type to a less extent is challenging; in order to develop accurate and reliable simulation models one has to include the incomplete ionization models with the appropriate coefficients. It is therefore necessary to use the 'incomplete ionization model' [48] (Figure 8). The equations implemented follow the model described in Eqs. (9) and (10). Note that the degeneracy factor in this particular case is a function of temperature, given

gA,D ¼ 4 þ 2exp �ΔgA,D=ð Þ kT

Figure 8. (a) Incomplete ionization model implemented for boron in single crystal diamond and (b) variation of activation

], as reported

(23)

by expressions Eq. (5) where in this case Nv300 = 1.8e19 and Nc300 = 5e18 [cm�<sup>3</sup>

tion of highly energy efficient high voltage high current devices.

34 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

bandwidth [22].

by the model in Eq. (23):

2.3.2. Doping and incomplete ionization

energy with doping concentration of boron [22].

For an intrinsic diamond, the hole mobility is up to 3800 cm2 /(Vs) whereas for boron-doped diamond the mobility is dominated by the concentration dependent scattering. At elevated temperatures, above 325 K it has been shown that the mobility is decreased due to acoustic phonon scattering [48, 49]. The combination of p+ doped diamond leads to lattice scattering. It therefore is advisable that these complex relationships between mobility, doping and temperature are taken into consideration when diamond simulations are implemented. A fairly accurate model, the unified mobility model (UniBo) [50] accounts for the dependence of the mobility on the doping and on the temperature using with a single model.

#### 2.3.4. Impact ionization

Impact ionization integral coefficients for electron and holes are very important in the design of diamond devices with the appropriate values been included in the impact ionization models parameters. Under reverse bias conditions, the increase of the ionization integral towards unity indicates the increase in the generation of avalanche carriers due to impact ionization, leading eventually to the device breakdown. The avalanche coefficients are given by Eq. (24) where in which an,p, bn,p and cn,p are fitting parameters and E is the lateral electric field through the semiconductor layer. The numerical values for both diamond and silicon are given in Table 19:

$$\mathbf{A} = \mathbf{a}\_{\mathrm{n,p}} \exp\left(-\mathbf{b}\_{\mathrm{n,p}}/\mathrm{E}\right) \mathbf{c}\_{\mathrm{n,p}} \tag{24}$$

#### 3. Device modelling and simulation

Due to the very low intrinsic carrier concentration of WBG semiconductors, the expected leakage current is very low (� <sup>10</sup>�<sup>20</sup>Acm�2), which causes converge issues. To alleviate from this, the numerical precision should be significantly high. This is achieved with the inclusion of certain keywords in the 'Device (and Circuit) Simulation' tool command file (e.g. 'Extended-Precision' for SDevice tool of the Synopsys Sentaurus TCAD). Simulations that use extended arithmetic precision are computational more intensive, therefore, the arithmetic precision should be increased in a trade-off manner up to a level that is able to provide a solution.

A further method utilized to improve convergence issues, especially when simulating the blocking characteristics, is to add extra carriers' generation through an equivalent keyword in the command file. The latter can increase the leakage current to levels that are high enough (e.g. > 10�<sup>10</sup>Acm�2) for the simulations to converge at lower precision level. This method not only helps the simulations convergence but it also helps with accounting the realistic leakage currents in WBG devices, which are orders of magnitudes higher than the predicted ideal ones. The reason for the much higher real leakage currents is attributed to the immaturity of the technology, the high defects and traps density and due to background irradiation. Their effect on the leakage current is therefore, considered with this constant carrier generation statement.

The choice of solvers is also important when simulating WBG devices. Some linear solvers will be more suited for small to medium 2D simulations and others for medium to large 3D simulations due to their superior parallel performance and significantly smaller memory usage. In addition, relaxing the numerical setting for the linear solver constitutes another trade-off which may improve the operation of the solver, however, convergence complications may come as a cost.

#### 3.1. Silicon carbide

For accurate simulation results, modelling the defects and traps is imperative. They directly influence the performance and strongly affect its reliability [51]. To highlight the effect of traps on the device performance and electrical characteristics, the P-i-N rectifier structure of Figure 9 was prepared for modelling and simulation. A Gaussian energetic distribution of deep levels is considered distributed spatially uniformly.

For most applications, the linear region of the forward I-V characteristics is important [14], the sub-threshold characteristics, however, are indicators of the material quality [53]. Both regions of the device characteristics are affected by the presence of traps. Figure 10 depicts the effect of the traps capture cross section, whereas Figure 11 depicts the effect of the concentration of deep level traps on the sub-threshold current-voltage (IV) forward characteristics. Because

Figure 9. Simplified device schematic used for simulations of a SiC P-i-N power rectifier following the fabricated diode in [52]. The Gaussian energetic distribution of the deep levels considered is also illustrated.

generation-recombination is the main carrier transport mechanism in the sub-threshold region, an increased concentration of deep levels or a larger capture-cross-section results in a higher

Figure 12. The impact of carriers' scattering lowers with increased temperature. This behaviour is independent of the

type and the concentration of the deep level as can be seen for the 4H-SiC (left) and the 3C-SiC (right) case.

Figure 10. Sub-threshold region of a SiC P-i-N structure with 10 um drift region at 1.4e16 cm<sup>3</sup>

Figure 11. Sub-threshold region of a SiC P-i-N structure with 10 um drift region at 1.4e16 cm<sup>3</sup>

is fixed with a variable cross section value. The simulated 4H-SiC material contains donor traps (left), whereas the 3C-SiC

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37

is fixed with a variable concentration value. The simulated 4H-SiC material contains donor traps (left), whereas the 3C-

. The defects concentration

. The defects' cross section

magnitude for leakage current [14].

contains acceptor traps (right).

SiC contains acceptor traps (right).

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors http://dx.doi.org/10.5772/intechopen.76062 37

method not only helps the simulations convergence but it also helps with accounting the realistic leakage currents in WBG devices, which are orders of magnitudes higher than the predicted ideal ones. The reason for the much higher real leakage currents is attributed to the immaturity of the technology, the high defects and traps density and due to background irradiation. Their effect on the leakage current is therefore, considered with this constant

36 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The choice of solvers is also important when simulating WBG devices. Some linear solvers will be more suited for small to medium 2D simulations and others for medium to large 3D simulations due to their superior parallel performance and significantly smaller memory usage. In addition, relaxing the numerical setting for the linear solver constitutes another trade-off which may improve the operation of the solver, however, convergence complications

For accurate simulation results, modelling the defects and traps is imperative. They directly influence the performance and strongly affect its reliability [51]. To highlight the effect of traps on the device performance and electrical characteristics, the P-i-N rectifier structure of Figure 9 was prepared for modelling and simulation. A Gaussian energetic distribution of deep levels is

For most applications, the linear region of the forward I-V characteristics is important [14], the sub-threshold characteristics, however, are indicators of the material quality [53]. Both regions of the device characteristics are affected by the presence of traps. Figure 10 depicts the effect of the traps capture cross section, whereas Figure 11 depicts the effect of the concentration of deep level traps on the sub-threshold current-voltage (IV) forward characteristics. Because

Figure 9. Simplified device schematic used for simulations of a SiC P-i-N power rectifier following the fabricated diode in

[52]. The Gaussian energetic distribution of the deep levels considered is also illustrated.

carrier generation statement.

may come as a cost.

3.1. Silicon carbide

considered distributed spatially uniformly.

Figure 10. Sub-threshold region of a SiC P-i-N structure with 10 um drift region at 1.4e16 cm<sup>3</sup> . The defects concentration is fixed with a variable cross section value. The simulated 4H-SiC material contains donor traps (left), whereas the 3C-SiC contains acceptor traps (right).

Figure 11. Sub-threshold region of a SiC P-i-N structure with 10 um drift region at 1.4e16 cm<sup>3</sup> . The defects' cross section is fixed with a variable concentration value. The simulated 4H-SiC material contains donor traps (left), whereas the 3C-SiC contains acceptor traps (right).

Figure 12. The impact of carriers' scattering lowers with increased temperature. This behaviour is independent of the type and the concentration of the deep level as can be seen for the 4H-SiC (left) and the 3C-SiC (right) case.

generation-recombination is the main carrier transport mechanism in the sub-threshold region, an increased concentration of deep levels or a larger capture-cross-section results in a higher magnitude for leakage current [14].

The forward the linear region is governed by the recombination-generation and the driftdiffusion. In this case, the defects have an opposite effect on the IV characteristics. An increased concentration of the traps intensifies carriers scattering, thus effectively reducing the mobility of carriers, which in turn leads to a decreased conductivity. This behaviour is less significant at elevated temperatures as the carriers gain enough kinetic energy to remain unaffected from the presence of nearby defects in the bulk. Consequently, the on-resistance of the material can decrease, as illustrated in Figure 12.

Traps also need to be included when modelling the interfaces between SiC and other materials. The traps' energetic profile at or near the interface in those cases need to be identified and modeled appropriately. For SiC Schottky interfaces, the combined effect of tunnelling and traps is modeled with the quantum tunnelling and trap-assisted tunnelling models [54]. The effect of traps also needs to be modeled at the SiC/SiO2 interface, in particular when modelling SiC MOSFETs [55].

fraction of the AlGaN layer and the corresponding strain based on the GaN layer. Another technique is applying a full strain model which calculates the polarization charges and are expressed through the local strain tensor. Finally, a stress model can be applied which calcu-

Figure 13. Simplified schematic representation of the simulated HEMT device (left) and its simulated transfer character-

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39

TCAD simulations with the simplified strain model utilized, describe how the threshold voltage changes with the thickness of AlGaN. This behaviour is in accordance to Eq. (25) [58] where; Vth is threshold voltage, Φ<sup>B</sup> is the height of the Schottky barrier, EC is the conduction band offset, d is the thickness of the AlGaN barrier, ND is the 2DEG concentration and ε is the relative dielectric constant of AlGaN. To increase the threshold voltage of the GaN HEMT, three parameters can be changed, the work function of the Schottky contact, the aluminium mole concentration in the AlGaN and the thickness of the AlGaN region. In this model, we have chosen to decrease the thickness of the AlGaN barrier whilst maintaining the same parameters for the rest of the device. Figure 13 depicts the simplified equivalent schematic representation of the simulated device and the transfer characteristics for three different AlGaN thicknesses of 0.20, 0.23 and 25 μm. As shown, the threshold of the device varies even with a very small change in the AlGaN thickness. This also demonstrates how sensitive the 2DEG is to the process. For that reason, a fixed interface charge across the AlGaN/GaN interface, is many times the preferred modelling approach, the concentration of which can be

lates the polarization charges and are expressed in the local stress tensor.

istics for 0.20, 0.23 and 0.25 μm AlGaN barrier layers (right).

Vth <sup>¼</sup> <sup>Φ</sup><sup>B</sup> � <sup>Δ</sup>EC

q �

Adequate modelling and simulation of WBG power devices and their performance with TCAD presents challenges and complexities. It includes modelling the material physical properties, improving the numerical accuracy of simulations, taking special care for the device structure design and incorporating the effect of defects, often in the form of traps. It also includes understanding the complexities and trade-offs between convergence and simulation

ðð d

qNDð Þx ε

dx<sup>2</sup> (25)

used as a fitting parameter:

4. Conclusions

#### 3.2. Gallium nitride

The GaN High Electron Mobility Transistor (HEMT) is regarded as the most successful attempt at harnessing the superior material properties of Gallium Nitride. The AlGaN HEMT is a heterostructure formed through the union of AlXGa1-XN and GaN. The inherent spontaneous and mechanically induced piezoelectric polarization charges a dictate the formation of a 2D Electron Gas across the heterojunction interface [56]. It is worth noting that the 2DEG channel is inherently present across the device and therefore, means that the device is naturally on. This has caused engineers to develop normally off GaN HEMT one being the p-type Gate GaN HEMT device. This device contains a p-typed GaN region beneath the gate which depletes the 2DEG of carriers and therefore, effectively stops the channel underneath the gate. In this section, device modelling will focus upon this device. The complexities associated with modelling GaN HEMT devices in TCAD are summarized below [57]:


The forward operation of the GaN HEMT device is dependent on the characteristics of the 2DEG channel. There are multiple methods that can be employed to model the 2DEG channel. The first is the placement of an interface charge across the AlGaN/GaN interface. The second is a simplified strain model in which the TCAD calculates the polarization charges based on the material which calculates the spontaneous and piezoelectric charges through the molar

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors http://dx.doi.org/10.5772/intechopen.76062 39

Figure 13. Simplified schematic representation of the simulated HEMT device (left) and its simulated transfer characteristics for 0.20, 0.23 and 0.25 μm AlGaN barrier layers (right).

fraction of the AlGaN layer and the corresponding strain based on the GaN layer. Another technique is applying a full strain model which calculates the polarization charges and are expressed through the local strain tensor. Finally, a stress model can be applied which calculates the polarization charges and are expressed in the local stress tensor.

TCAD simulations with the simplified strain model utilized, describe how the threshold voltage changes with the thickness of AlGaN. This behaviour is in accordance to Eq. (25) [58] where; Vth is threshold voltage, Φ<sup>B</sup> is the height of the Schottky barrier, EC is the conduction band offset, d is the thickness of the AlGaN barrier, ND is the 2DEG concentration and ε is the relative dielectric constant of AlGaN. To increase the threshold voltage of the GaN HEMT, three parameters can be changed, the work function of the Schottky contact, the aluminium mole concentration in the AlGaN and the thickness of the AlGaN region. In this model, we have chosen to decrease the thickness of the AlGaN barrier whilst maintaining the same parameters for the rest of the device. Figure 13 depicts the simplified equivalent schematic representation of the simulated device and the transfer characteristics for three different AlGaN thicknesses of 0.20, 0.23 and 25 μm. As shown, the threshold of the device varies even with a very small change in the AlGaN thickness. This also demonstrates how sensitive the 2DEG is to the process. For that reason, a fixed interface charge across the AlGaN/GaN interface, is many times the preferred modelling approach, the concentration of which can be used as a fitting parameter:

$$V\_{th} = \Phi\_{\mathcal{B}} - \frac{\Delta E\_{\mathcal{C}}}{q} - \iint\_{d} \frac{qN\_D(\mathbf{x})}{\varepsilon} d\mathbf{x}^2 \tag{25}$$

#### 4. Conclusions

The forward the linear region is governed by the recombination-generation and the driftdiffusion. In this case, the defects have an opposite effect on the IV characteristics. An increased concentration of the traps intensifies carriers scattering, thus effectively reducing the mobility of carriers, which in turn leads to a decreased conductivity. This behaviour is less significant at elevated temperatures as the carriers gain enough kinetic energy to remain unaffected from the presence of nearby defects in the bulk. Consequently, the on-resistance of

Traps also need to be included when modelling the interfaces between SiC and other materials. The traps' energetic profile at or near the interface in those cases need to be identified and modeled appropriately. For SiC Schottky interfaces, the combined effect of tunnelling and traps is modeled with the quantum tunnelling and trap-assisted tunnelling models [54]. The effect of traps also needs to be modeled at the SiC/SiO2 interface, in particular when modelling

The GaN High Electron Mobility Transistor (HEMT) is regarded as the most successful attempt at harnessing the superior material properties of Gallium Nitride. The AlGaN HEMT is a heterostructure formed through the union of AlXGa1-XN and GaN. The inherent spontaneous and mechanically induced piezoelectric polarization charges a dictate the formation of a 2D Electron Gas across the heterojunction interface [56]. It is worth noting that the 2DEG channel is inherently present across the device and therefore, means that the device is naturally on. This has caused engineers to develop normally off GaN HEMT one being the p-type Gate GaN HEMT device. This device contains a p-typed GaN region beneath the gate which depletes the 2DEG of carriers and therefore, effectively stops the channel underneath the gate. In this section, device modelling will focus upon this device. The complexities associated with model-

• Reduced crystal symmetry compared to silicon due to the Wurtzite crystal structure.

• The lower intrinsic carrier concentration associated with wide bandgaps semiconductors. • The exchange of the inter-valley at high field that modulates the current through the Gunn

• The abrupt nature of the heterojunction between the semiconductors and partially floating

The forward operation of the GaN HEMT device is dependent on the characteristics of the 2DEG channel. There are multiple methods that can be employed to model the 2DEG channel. The first is the placement of an interface charge across the AlGaN/GaN interface. The second is a simplified strain model in which the TCAD calculates the polarization charges based on the material which calculates the spontaneous and piezoelectric charges through the molar

• The significant and extensive quantity of traps and their subsequent characteristics.

• The polarization charges and subsequent effects on the device performance.

the material can decrease, as illustrated in Figure 12.

38 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

ling GaN HEMT devices in TCAD are summarized below [57]:

SiC MOSFETs [55].

3.2. Gallium nitride

effect.

regions.

Adequate modelling and simulation of WBG power devices and their performance with TCAD presents challenges and complexities. It includes modelling the material physical properties, improving the numerical accuracy of simulations, taking special care for the device structure design and incorporating the effect of defects, often in the form of traps. It also includes understanding the complexities and trade-offs between convergence and simulation speed, and how these are affected by the choice of solvers and numerical accuracy. This chapter gave an overview of those for 3C-SiC, 4H-SiC, GaN and diamond-based devices.

[11] Silvaco Inc. Atlas User's Manual. 2016

tronics and Drives; 2017. pp. 565-571

Technical University of Munchen; 2000

ence on Silicon Carbide; 1969. pp. 141-152

actions on Electron Devices. 2001;48(7):1442-1447

ity in β-SiC. Solid State Electronics. 1995;38(11):1911-1916

p-n junctions. Solid State Electronics. 1970;13(5):583-608

cam.ac.uk/handle/1810/252098

January 01, 2018]

5075

3389-3394

[12] Arvanitopoulos A, Lophitis N, Gyftakis KN, Perkins S, Antoniou M. Validated physical models and parameters of bulk 3C-SiC aiming for credible technology computer aided design (TCAD) simulation. Semiconductor Science and Technology. 2017;32(10):104009

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

http://dx.doi.org/10.5772/intechopen.76062

41

[13] Arvanitopoulos A et al. Physical parameterisation of 3C-silicon carbide (SiC) with scope to evaluate the suitability of the material for power diodes as an alternative to 4H-SiC. In: 2017 IEEE 11th International Symposium on Diagnostics Electric Machines, Power Elec-

[14] Lades M. Modeling and Simulation of Wide Bandgap Semiconductor Devices: 4H/6H-SiC.

[15] Choyke WJ, Patrick L. Optical properties of polytypes of SiC: interband absorption, and luminescence of nitrogen-exciton complexes. In: Proceedings of the International Confer-

[16] Silicon Carbide. [Online]. Available: http://ioffe.ru/SVA/NSM/Semicond/SiC [Accessed:

[17] Bellotti E, Nilsson HE, Brennan KF, Ruben P. Ensemble Monte Carlo calculation of hole

[18] Goldberg Y, Levinshtein M, Rumyantsev S. Silicon Carbide (SiC) Properties of Advanced Semiconductor Materials: GaN, AlN, InN, BN, SiC, SiGe. New York: Wiley; 2001

[19] Roschke M, Schwierz F. Electron mobility models for 4H, 6H, and 3C SiC. IEEE Trans-

[20] Matsuura H, Masuda Y, Chen Y, Nishino S. Determination of donor densities and donor levels in 3C-SiC grown from Si2(CH3)6 using hall-effect measurements. Japanese Journal Applied Physics, Part 1 Regular Papers Short Notes Review Papers. 2000;39(9 A):5069-

[21] Joshi RP, Ferry DK. Calculations of the temperature and field dependent electronic mobil-

[22] Rashid SJ. High Voltage Packaging Technology for Wide Bandgap Power Semiconductor Devices. PhD thesis. Cambridge: University of Cambridge; 2008. https://www.repository.

[23] Ayalew T. SiC Semiconductor Devices Technology, Modeling, and Simulation. PhD thesis. Austria: Vienna University of Technology; 2004. http://www.iue.tuwien.ac.at/phd/ayalew/

[24] Nilsson HE, Englund U, Hjelm M, Bellotti E, Brennan K. Full band Monte Carlo study of high field transport in cubic phase silicon carbide. Journal of Applied Physics. 2003;93(6):

[25] Van Overstraeten R, De Man H. Measurement of the ionization rates in diffused silicon

transport in bulk 3C–SiC. Journal of Applied Physics. 1999;85(6):3211-3217

#### Acknowledgements

The authors would like to thank the Research Institute for Future Cities and Transport, Coventry University and the Royal Society for funding this research.

#### Author details

Neophytos Lophitis<sup>1</sup> \*, Anastasios Arvanitopoulos<sup>1</sup> , Samuel Perkins<sup>1</sup> and Marina Antoniou<sup>2</sup>

\*Address all correspondence to: n.lophitis@coventry.ac.uk

1 Faculty of Engineering, Environment and Computing, Coventry University, Coventry, UK

2 Electrical Engineering Division, Engineering Department, University of Cambridge, Cambridge, UK

#### References


[11] Silvaco Inc. Atlas User's Manual. 2016

speed, and how these are affected by the choice of solvers and numerical accuracy. This chapter gave an overview of those for 3C-SiC, 4H-SiC, GaN and diamond-based devices.

The authors would like to thank the Research Institute for Future Cities and Transport,

1 Faculty of Engineering, Environment and Computing, Coventry University, Coventry, UK

[1] Meneghini M, Meneghesso G, Zanoni E, editors. Power GaN Devices: Materials, applications and reliability. Proquest Ebook Central. Cham: Springer; 2016. [5 January 2018]. https://ebookcentral.proquest.com/lib/coventry/reader.action?docID=4676658&query= [2] Elasser A, Chow TP. Silicon carbide benefits and advantages for power electronics circuits

[3] Inoue K et al. Development of gallium nitride high electron mobility transistors for

[4] Lophitis N et al. The destruction mechanism in GCTs. IEEE Transactions on Electron

[5] Lophitis N et al. Gate commutated thyristor with voltage independent maximum control-

2 Electrical Engineering Division, Engineering Department, University of Cambridge,

, Samuel Perkins<sup>1</sup> and Marina Antoniou<sup>2</sup>

Coventry University and the Royal Society for funding this research.

40 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

\*, Anastasios Arvanitopoulos<sup>1</sup>

and systems. Proceedings of the IEEE. 2002;90(6):969-986

cellular base stations. SEI Technical Review. 2010;71:88-93

lable current. IEEE Electron Device Letters. 2013;34(8):954-956

[6] Synopsys. Sentaurus ™ Structure Editor User Guide. 2017

Devices. 2013;60(2):819-826

[7] Silvaco Inc. DevEdit User's Manual. 2014

[9] Silvaco Inc. Athena User's Manual. 2016

[8] Synopsys. Sentaurus ™ Process User Guide. 2017

[10] Synopsys. Sentaurus ™ Device User Guide. 2017

\*Address all correspondence to: n.lophitis@coventry.ac.uk

Acknowledgements

Author details

Neophytos Lophitis<sup>1</sup>

Cambridge, UK

References


[26] Tirino L, Weber M, Brennan KF, Bellotti E, Goano M. Temperature dependence of the impact ionization coefficients in GaAs, cubic SiC, and zinc-blende GaN. Journal of Applied Physics. 2003;94(1):423-430

[42] Pearton SJ, Abernathy CR, Ren F. Gallium Nitride Processing for Electronics, Sensors, and

TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors

http://dx.doi.org/10.5772/intechopen.76062

43

[43] Delaney K, Rinke P, Van de Walle C. Auger recombination rates in nitrides from first

[44] Nebel CE. Electronic properties of CVD diamond. Semiconductor Science and Technol-

[45] Takahashi K, Yoshikawa A, Sandhu A. Wide Bandgap Semiconductors: Fundamental Properties and Modern Photonic and Electronic Devices. New York: Springer; 2007

[46] Sussmann RS. CVD Diamond for Electronic Devices and Sensors. New York: Wiley; 2008

[47] Kone S et al. High performances CVD diamond Schottky barrier diode—Simulation and carrying out. In: Epe 2009 13th European Conference on Power Electronics and Applica-

[48] Isberg J, Lindblom A, Tajani A, Twitchen D. Temperature dependence of hole drift mobility in high-purity single-crystal CVD diamond. Physica Status Solidi. 2005;202(11):2194-

[49] Nebel CE, Stutzmann M. Transport properties of diamond: Carrier mobility and resistivity. In: Nazare M, Neves A, editors. Properties, Growth and Applications of Diamond.

[50] Reggiani S, Valdinoci M. A unified analytical model for bulk and surface mobility in Si nand p-channel MOSFET's. In: Procedings of the 29th European Solid-State Device Researh

[51] Amini Moghadam H, Dimitrijev S, Han J, Haasmann D. Active defects in MOS devices on

[52] Alexandrov P, Zhao JH, Wright W, Pan M, Weiner M. Demonstration of 140 A, 800 V 4H-SiC pin/Schottky barrier diodes with multi-step junction termination extension structures.

[53] Mandurrino M et al. Trap-assisted tunneling in InGaN/GaN LEDs: Experiments and physics-based simulation. In: Proceedings of the Interational Conference on Numerical

[54] Arvanitopoulos A et al. Carrier transport mechanisms contributing to the sub-threshold current in 3C-SiC Schottky barrier diodes. In: IEEE Workshop on Wide Bandgap Power

[55] Pensl G et al. Traps at the SiC/SiO2 interface. Materials Research Society. 2001;640:1-11

[56] He XG, Zhao DG, Jiang DS. Formation of two-dimensional electron gas at AlGaN/GaN heterostructure and the derivation of its sheet density expression. Chinese Physics B. 2015;

4H-SiC: A critical review. Microelectronics and Reliability. 2016;60:1-9

Simulation of Optoelectronic Devices, NUSOD; 2014, pp. 13-14

Devices and Applications (WiPDA); 2018. p. (to be published)

Spintronics. New York: Springer; 2006

tions; 2009. Vols. 1-9. pp. 5137-5144

London: INSPEC; 2001. pp. 40-52

Electronics Letters. 2001;37(18):1139-1140

Conference; 1999. p. 240

ogy. 2003;18(3):S1-S11

2198

24(6):1-5

principles. Applied Physics Letters. 2009;94(19):191109


[42] Pearton SJ, Abernathy CR, Ren F. Gallium Nitride Processing for Electronics, Sensors, and Spintronics. New York: Springer; 2006

[26] Tirino L, Weber M, Brennan KF, Bellotti E, Goano M. Temperature dependence of the impact ionization coefficients in GaAs, cubic SiC, and zinc-blende GaN. Journal of

[27] Hatakeyama T, Nishio J, Ota C, Shinohe T, Jsap. Physical modeling and scaling properties of 4H-SiC power devices. In: SISPAD 2005 International Conference on Simulation of

[28] Starke U. Non-basal plane SiC surfaces: Anisotropic structures and low-dimensional

[29] Sabui G, Parbrook PJ, Arredondo-Arechavala M, Shen ZJ. Modeling and simulation of bulk gallium nitride power semiconductor devices. AIP Advances. 2016;6(5):55006

[30] Gallium Nitride. [Online]. Available: http://www.ioffe.ru/SVA/NSM/Semicond/GaN/

[31] Hilt O, Knauer A, Brunner F, Bahat-Treidel E, Wurfl J. Normally-off AlGaN/GaN HFET with p-type GaN gate and AlGaN buffer. In: 2010 6th International Conference on Inte-

[32] Baik KH et al. Temperature dependence of forward current characteristics of GaN junction

[33] Gorczyca I, Pressure H, Svane A, Christensen NE. Theoretical study of point defects in GaN and AlN; lattice relaxations and pressure effects. Internet Journal Nitride Semicon-

[34] Tansley TL, Egan RJ. Point-defect energies in the nitrides of aluminum, gallium, and

[35] Boguslawski P, Briggs EL, Bernholc J. Amphoteric properties of substitutional carbon

[36] Mohammad SN, Salvador AA, Morkoc H. Emerging gallium nitride based devices. Pro-

[37] Francis RW, Worrell WL. High temperature electrical conductivity of aluminum nitride.

[38] Levinshtein ME, Rumyantsev SL, Shur M. Properties of Advanced Semiconductor Mate-

[40] Ismail H et al. Theory of hole initiated impact ionization in bulk zincblende and wurtzite

[41] Brandt O et al. Recombination dynamics in GaN. Journal of Crystal Growth. 1998;189-190:

[39] Razeghi M, Henini M. Optoelectronic Devices: III Nitrides. New York: Elsevier; 2005

and Schottky rectifiers. Solid State Electronics. 2003;47(9):1533-1538

impurity in GaN and AlN. Applied Physics Letters. 1996;69(2):233-235

Semiconductor Processes and Devices. Vol. 1; 2005. pp. 171-174

42 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

electron systems. Physica Status Solidi. 2009;246(7):1569-1579

Applied Physics. 2003;94(1):423-430

[Accessed: January 01, 2018]

ductor Research. 1997;2(18):2-6

790-793

grated Power Electronic Systems; 2010. pp. 1-4

indium. Physical Review B. 1992;45(19):10942-10950

Journal of the Electrochemical Society. 1976;123:430-433

GaN. Journal of Applied Physics. 1997;81(12):7827-7834

rials: GaN, AlN, InN, BN, SiC, SiGe. New York: Wiley; 2001

ceedings of the IEEE. 1995;83(10):1306-1355


[57] Strauss S et al. TCAD methodology for simulation of GaN-HEMT power devices. In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs; 2014. pp. 257-260

**Chapter 3**

**Provisional chapter**

**Main Differences in Processing Si and SiC Devices**

**Main Differences in Processing Si and SiC Devices**

DOI: 10.5772/intechopen.76293

Due to the different physical properties of Si and SiC, many conventional Si device processing techniques cannot be directly transferred to SiC device fabrication. To deliver high-performance SiC commercial power devices, new techniques quite different from Si industry were developed in past decades for processing device, such as dopant implantation, metal contact, MOS interface, etc. On the other hand, the physics model behind many of these SiC processing technologies is not updated in the same pace that the suc-

**Keywords:** SiC processing, dopant implantation, metal contact, MOS interface, physics

Silicon has dominated the electronics industry ever since it was born. In power electronics area, nearly all commercial power devices are made of Si nowadays. However, due to the target of a more environmental friendly society, there has been a continuously increasing demand of power devices working in more harsh conditions such as higher power, higher temperature, higher frequency or even higher radiation, some of which are well beyond the physical limits of Si. For the first time, the position of Si is challenged by some other materials, most of which have a larger band gap than Si, thus called wide band gap (WBG) semiconductors, including silicon carbide (SiC), gallium nitride (GaN) and diamond. SiC may be the most promising candidate at the moment, whose technology is most mature among WBG semiconductors with commercial devices readily on the market [1, 2], and most importantly, SiC is the

devices as insulators, dielectrics and diffusion barriers [3]. Just as the SiC substrate and epilayer

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

as the nature oxide, which is used extensively in power

Fan Li and Mike Jennings

Fan Li and Mike Jennings

**Abstract**

model

**1. Introduction**

only WBG semiconductor with SiO<sup>2</sup>

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

cess of them can still not be fully understood.

http://dx.doi.org/10.5772/intechopen.76293

[58] Ikeda N, Li J, Kato S, Masuda M, Yoshida S. A novel GaN device with thin AIGaN/GaN heterostructure for high-power applications. Furukawa Review. 2006;(29):1-6

#### **Main Differences in Processing Si and SiC Devices Main Differences in Processing Si and SiC Devices**

DOI: 10.5772/intechopen.76293

Fan Li and Mike Jennings Fan Li and Mike Jennings

[57] Strauss S et al. TCAD methodology for simulation of GaN-HEMT power devices. In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs;

44 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

[58] Ikeda N, Li J, Kato S, Masuda M, Yoshida S. A novel GaN device with thin AIGaN/GaN heterostructure for high-power applications. Furukawa Review. 2006;(29):1-6

2014. pp. 257-260

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76293

**Abstract**

Due to the different physical properties of Si and SiC, many conventional Si device processing techniques cannot be directly transferred to SiC device fabrication. To deliver high-performance SiC commercial power devices, new techniques quite different from Si industry were developed in past decades for processing device, such as dopant implantation, metal contact, MOS interface, etc. On the other hand, the physics model behind many of these SiC processing technologies is not updated in the same pace that the success of them can still not be fully understood.

**Keywords:** SiC processing, dopant implantation, metal contact, MOS interface, physics model

#### **1. Introduction**

Silicon has dominated the electronics industry ever since it was born. In power electronics area, nearly all commercial power devices are made of Si nowadays. However, due to the target of a more environmental friendly society, there has been a continuously increasing demand of power devices working in more harsh conditions such as higher power, higher temperature, higher frequency or even higher radiation, some of which are well beyond the physical limits of Si. For the first time, the position of Si is challenged by some other materials, most of which have a larger band gap than Si, thus called wide band gap (WBG) semiconductors, including silicon carbide (SiC), gallium nitride (GaN) and diamond. SiC may be the most promising candidate at the moment, whose technology is most mature among WBG semiconductors with commercial devices readily on the market [1, 2], and most importantly, SiC is the only WBG semiconductor with SiO<sup>2</sup> as the nature oxide, which is used extensively in power devices as insulators, dielectrics and diffusion barriers [3]. Just as the SiC substrate and epilayer

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

growth technologies which had gone through decades of developments before power device quality level wafers can be delivered, SiC device processing techniques were improved as well at the same time. It has been studied intensively in last 20 years, and although there is still plenty of room to be improved, commercial power MOSFETs and Schottky diodes with some more conventional structures are not an issue anymore. This chapter will talk about the state-of-the-art processing techniques for SiC devices, including intentional doping, electrical activation, metal/semiconductor interfaces and MOS interface. Particularity, the difference between Si and SiC processing in these areas will be discussed.

## **2. Intentional doping in SiC**

In 1930, Bernhard Gudden [4] was the first one to report that the electrical carriers of semiconductors are actually the impurities within their crystal lattices. If the impurity concentration is too high, the semiconductor becomes metallic, and if too low, more like an insulator.

> shown in **Figure 2**. Being ionised, the dopant atoms can be accelerated by electromagnetic field to gain energy so high that, when hitting the target surface, they are able to break the semiconductor chemical bonds and penetrate into the crystal lattices. The implantation depth can be controlled by changing the electromagnetic field strength, and the resultant impurity concentration (cm−3) is determined by the amount of dopants supplied by the source, which is

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 47

**Figure 1.** Schematic graph showing a typical dopant thermal diffusion process using a gas source.

In Si device processing, both thermal diffusion and ion implantation can be used depending on specific requirements. In fact, implantation followed by a short time thermal diffusion is becoming popular nowadays. For WBG semiconductors such as SiC, however, diffusion coefficients of common dopants are so low that are negligible below 1800°C [8], which leaves ion

Even being a more complex and expensive system, ion implantation proved to be more controllable than thermal diffusion. Also, the movement of dopants in a thermal diffusion process may involve unexpected spreading in other directions, leading to poor doping profiles. This is not an issue for ion implantation since dopant movement in the semiconductor is minimal, which means the elimination of dopant out-diffusion. There are, of course, also limitations for ion implantations. First of all, it is essentially a dopant bombarding process, which means damages are inevitably induced to the target, mainly in the surface region. Secondly, as-implanted dopants are almost always interstitial (not chemically bonded), namely, not active carriers. An extra post-implantation annealing (PIA) process is typically required to recover the lattice damage and put the implanted dopants into substitutional positions so they can contribute to current conduction, called dopant

The activation of dopants in 4H-SiC has been intensively studied, and the efforts are mainly put into two directions, namely, protecting the semiconductor surface morphology while at

the same time maximising the active concentration of implanted dopants.

called 'dose', and the unit is number per specific area (cm−2).

implantation the only option, and the PIA process is essential.

activation.

**2.2. Activating implanted dopants in SiC**

#### **2.1. Thermal diffusion and ion implantation**

Impurities are usually introduced to the bulk semiconductor in early stages of a device fabrication process. Most commonly used dopants are from group V (N, P and As) for n-type and group III (B, Al and Ga) for p-type doping purposes. Doping a bulk semiconductor can be relative easily achieved by adding dopant elements into the epilayer growing process, and the impurity level can be modulated by controlling the precursor gas concentrations [5]. Take a typical vertical MOSFET structure as an example; on the epilayer surface, specific n-type and p-type regions are required to form ohmic contact, MOS channel and body diode. The selective doping area is usually defined by doping masks made of dielectrics or metals using standard photolithography processes. Nowadays the selective doping of semiconductor is achieved mostly in two ways, namely, thermal diffusion and ion implantation.

It is well known that molecules tend to move from higher to lower concentration regions, and this process can be enhanced by increasing the ambient temperature, pressure or concentration gradient in-between. This idea is adopted in semiconductor industry to introduce impurities using dopant sources with various phases: gas, liquid or solid. Thermal diffusionbased doping process often occurs in a quarts tube (see **Figure 1**) in an inert gas atmosphere to minimise contaminations. The dopants firstly arrived at the semiconductor surface form a relative high impurity concentration region; consequently, a concentration gradient exists between the surface and bulk, after which the diffusion is initiated by the thermal energy provided. With time going on, dopants diffuse deeper into the semiconductor bulk, and when the desired doping profile is obtained, it can be stopped quite conveniently by simply cutting the heat supply.

Attributed to the developments of experimental physics, ion implanting dopants directly into semiconductors are also an option now. Ion implanters were not widely available to device engineers until the 1970s [6], while now it is commonly used in both lab and industry processing. In an ion implantation system, dopants are ionised atoms generated from an ion source

**Figure 1.** Schematic graph showing a typical dopant thermal diffusion process using a gas source.

shown in **Figure 2**. Being ionised, the dopant atoms can be accelerated by electromagnetic field to gain energy so high that, when hitting the target surface, they are able to break the semiconductor chemical bonds and penetrate into the crystal lattices. The implantation depth can be controlled by changing the electromagnetic field strength, and the resultant impurity concentration (cm−3) is determined by the amount of dopants supplied by the source, which is called 'dose', and the unit is number per specific area (cm−2).

In Si device processing, both thermal diffusion and ion implantation can be used depending on specific requirements. In fact, implantation followed by a short time thermal diffusion is becoming popular nowadays. For WBG semiconductors such as SiC, however, diffusion coefficients of common dopants are so low that are negligible below 1800°C [8], which leaves ion implantation the only option, and the PIA process is essential.

Even being a more complex and expensive system, ion implantation proved to be more controllable than thermal diffusion. Also, the movement of dopants in a thermal diffusion process may involve unexpected spreading in other directions, leading to poor doping profiles. This is not an issue for ion implantation since dopant movement in the semiconductor is minimal, which means the elimination of dopant out-diffusion. There are, of course, also limitations for ion implantations. First of all, it is essentially a dopant bombarding process, which means damages are inevitably induced to the target, mainly in the surface region. Secondly, as-implanted dopants are almost always interstitial (not chemically bonded), namely, not active carriers. An extra post-implantation annealing (PIA) process is typically required to recover the lattice damage and put the implanted dopants into substitutional positions so they can contribute to current conduction, called dopant activation.

#### **2.2. Activating implanted dopants in SiC**

growth technologies which had gone through decades of developments before power device quality level wafers can be delivered, SiC device processing techniques were improved as well at the same time. It has been studied intensively in last 20 years, and although there is still plenty of room to be improved, commercial power MOSFETs and Schottky diodes with some more conventional structures are not an issue anymore. This chapter will talk about the state-of-the-art processing techniques for SiC devices, including intentional doping, electrical activation, metal/semiconductor interfaces and MOS interface. Particularity, the difference

In 1930, Bernhard Gudden [4] was the first one to report that the electrical carriers of semiconductors are actually the impurities within their crystal lattices. If the impurity concentration is

Impurities are usually introduced to the bulk semiconductor in early stages of a device fabrication process. Most commonly used dopants are from group V (N, P and As) for n-type and group III (B, Al and Ga) for p-type doping purposes. Doping a bulk semiconductor can be relative easily achieved by adding dopant elements into the epilayer growing process, and the impurity level can be modulated by controlling the precursor gas concentrations [5]. Take a typical vertical MOSFET structure as an example; on the epilayer surface, specific n-type and p-type regions are required to form ohmic contact, MOS channel and body diode. The selective doping area is usually defined by doping masks made of dielectrics or metals using standard photolithography processes. Nowadays the selective doping of semiconductor is achieved mostly in two ways, namely, thermal diffusion and

It is well known that molecules tend to move from higher to lower concentration regions, and this process can be enhanced by increasing the ambient temperature, pressure or concentration gradient in-between. This idea is adopted in semiconductor industry to introduce impurities using dopant sources with various phases: gas, liquid or solid. Thermal diffusionbased doping process often occurs in a quarts tube (see **Figure 1**) in an inert gas atmosphere to minimise contaminations. The dopants firstly arrived at the semiconductor surface form a relative high impurity concentration region; consequently, a concentration gradient exists between the surface and bulk, after which the diffusion is initiated by the thermal energy provided. With time going on, dopants diffuse deeper into the semiconductor bulk, and when the desired doping profile is obtained, it can be stopped quite conveniently by simply cutting

Attributed to the developments of experimental physics, ion implanting dopants directly into semiconductors are also an option now. Ion implanters were not widely available to device engineers until the 1970s [6], while now it is commonly used in both lab and industry processing. In an ion implantation system, dopants are ionised atoms generated from an ion source

too high, the semiconductor becomes metallic, and if too low, more like an insulator.

between Si and SiC processing in these areas will be discussed.

46 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**2. Intentional doping in SiC**

ion implantation.

the heat supply.

**2.1. Thermal diffusion and ion implantation**

The activation of dopants in 4H-SiC has been intensively studied, and the efforts are mainly put into two directions, namely, protecting the semiconductor surface morphology while at the same time maximising the active concentration of implanted dopants.

**3. Ohmic contact on SiC**

ries are challenged.

[28, 29].

**3.1. Metal contact interface: classic theory**

Most metals are known as highly electrical and thermal conductive attributed to their delocalised electrons, not to mention the convenient alloying process which helps to form reliable interactions for packaging. Consequently, they are the most widely used material for contact materials in semiconductor industry. Dating back to Braun's discovery in 1874 [27], the study of metal/semiconductor (M-S) interface is almost as old as the semiconductor device itself. A lot of huge efforts were put into exploring the M-S interface, and there had been classic physics models that were well developed. Yet still, this area remains active with new discoveries reported, and novel theories developed continuously. The emergence and adoption of WBG semiconductors raise discussions on new experimental results, and the well-established theo-

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 49

It can be seen in **Figure 3** that the work functions of most metals used in electronic industry are quite big compared with Si affinity, that is, an inherent energy barrier exists between metal/Si interfaces, preventing free carrier exchange. And due to a much lower affinity value (except for 3C-SiC), this barrier is only getting higher at a metal/SiC interface, which also explains why Schottky behaviour is typically observed for as-deposited metal contacts on

**Figure 3.** Band diagrams of Si, 3C-, 4H- and 6H-SiC and work functions of commonly used metals in electronic industry

**Figure 2.** The schematic diagram of an ion implantation system [7].

The temperature required for SiC post-implantation activation (PIA) is very high that above 1400°C [9, 10] is common for n-type and even higher (>1600°C) for p-type [11–13] since acceptors generally sit deeper in the band gap than donors, namely, more difficult to activate. This high temperature means conventional quartz tubes are not up to the task and high melting point tubes made of Al<sup>2</sup> O3 and SiC or similar have to be used. Also, high-temperature annealing leads to a roughened semiconductor surface (known as 'step bunching'), enhanced at implanted regions. This can deteriorate the performance of interface features such as Schottky contacts and FET channels [14–16]. A protection capping layer is often used to preserve the SiC surface; such cap materials studied for 4H-SiC include AlN [17, 18], BN/AlN [19] and graphite [12, 15]. AlN and BN/AlN processes are found complex and expensive, thus not widely accepted. The graphite cap proved to be effective in preserving surface morphology up to 1800°C [11] but may reduce the MOSFET channel mobility due to the excessive silicon vacancies, which are most likely induced by the reaction between diffused Si atoms and the graphite [11, 20]. A SiO<sup>2</sup> layer should not react with Si or C at the common annealing temperatures and can be easily deposited by CVD method and removed via HF etching. It was also studied and resulted a similar surface roughness level as a graphite cap with the same annealing conditions [21]. In the few literatures on 3C-SiC, n-type implanted 3C-SiC was studied for different annealing conditions (1150–1400°C) with [22] and without [23, 24] a graphite cap, and it turned out that there was little advantage of using a graphite cap in terms of protecting the 3C-SiC surface, probably because the temperature limited by Si substrates is not high enough to make the difference.

For a given implanted doping level, the active dopant concentration in SiC generally increases with the PIA temperature. And for a fixed PIA temperature, the active dopant concentration increases with the implanted doping level [25], although the percentage of activated dopants (activation rate) seems to decrease [9]. Complete activation of N-type implanted 4H-SiC has been demonstrated by annealing at 1700°C and using phosphorous as dopant [26], while P-type material still remains a challenge [12].

#### **3. Ohmic contact on SiC**

Most metals are known as highly electrical and thermal conductive attributed to their delocalised electrons, not to mention the convenient alloying process which helps to form reliable interactions for packaging. Consequently, they are the most widely used material for contact materials in semiconductor industry. Dating back to Braun's discovery in 1874 [27], the study of metal/semiconductor (M-S) interface is almost as old as the semiconductor device itself. A lot of huge efforts were put into exploring the M-S interface, and there had been classic physics models that were well developed. Yet still, this area remains active with new discoveries reported, and novel theories developed continuously. The emergence and adoption of WBG semiconductors raise discussions on new experimental results, and the well-established theories are challenged.

#### **3.1. Metal contact interface: classic theory**

The temperature required for SiC post-implantation activation (PIA) is very high that above 1400°C [9, 10] is common for n-type and even higher (>1600°C) for p-type [11–13] since acceptors generally sit deeper in the band gap than donors, namely, more difficult to activate. This high temperature means conventional quartz tubes are not up to the task and high melting

leads to a roughened semiconductor surface (known as 'step bunching'), enhanced at implanted regions. This can deteriorate the performance of interface features such as Schottky contacts and FET channels [14–16]. A protection capping layer is often used to preserve the SiC surface; such cap materials studied for 4H-SiC include AlN [17, 18], BN/AlN [19] and graphite [12, 15]. AlN and BN/AlN processes are found complex and expensive, thus not widely accepted. The graphite cap proved to be effective in preserving surface morphology up to 1800°C [11] but may reduce the MOSFET channel mobility due to the excessive silicon vacancies, which are most likely induced by the reaction between diffused Si atoms and the graphite [11, 20]. A SiO<sup>2</sup> layer should not react with Si or C at the common annealing temperatures and can be easily deposited by CVD method and removed via HF etching. It was also studied and resulted a similar surface roughness level as a graphite cap with the same annealing conditions [21]. In the few literatures on 3C-SiC, n-type implanted 3C-SiC was studied for different annealing conditions (1150–1400°C) with [22] and without [23, 24] a graphite cap, and it turned out that there was little advantage of using a graphite cap in terms of protecting the 3C-SiC surface, probably because the temperature limited by Si substrates is not high enough to make the difference.

For a given implanted doping level, the active dopant concentration in SiC generally increases with the PIA temperature. And for a fixed PIA temperature, the active dopant concentration increases with the implanted doping level [25], although the percentage of activated dopants (activation rate) seems to decrease [9]. Complete activation of N-type implanted 4H-SiC has been demonstrated by annealing at 1700°C and using phosphorous as dopant [26], while

and SiC or similar have to be used. Also, high-temperature annealing

point tubes made of Al<sup>2</sup>

O3

**Figure 2.** The schematic diagram of an ion implantation system [7].

48 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

P-type material still remains a challenge [12].

It can be seen in **Figure 3** that the work functions of most metals used in electronic industry are quite big compared with Si affinity, that is, an inherent energy barrier exists between metal/Si interfaces, preventing free carrier exchange. And due to a much lower affinity value (except for 3C-SiC), this barrier is only getting higher at a metal/SiC interface, which also explains why Schottky behaviour is typically observed for as-deposited metal contacts on

**Figure 3.** Band diagrams of Si, 3C-, 4H- and 6H-SiC and work functions of commonly used metals in electronic industry [28, 29].

4H-SiC. To fabricate an ohmic contact, increasing the contact region local doping level (via thermal diffusion or ion implantation) is the most common way for both Si and SiC. When the contact region is lowly doped, the depletion region is quite wide that the electron exchange at the M-S interface is only possible when electrons overcome the barrier by gaining enough energy as shown in **Figure 4**, usually thermally activated and thus called thermionic emission (TE). If doping level is very high, the depletion region becomes quite narrow, and electrons can tunnel through the barrier freely with the help of an external electric field, which is called field emission (FE). And if the doping value is in the middle, the depletion region is narrowed but not enough to enable electron tunnelling. In this case, electrons still need extra thermal energy to 'climb up' the barrier, but not as much as TE. The energy required just needs to be adequate for the electrons to 'climb' to a position shallow enough for tunnelling that begins to take effect. Since both TE and FE mechanisms are involved, this is therefore called as thermionic/field emission (TFE).

Among all, FE is the most desired conduction mechanism for deletion-type ohmic contact fabrication, since it is not a thermally activated process, namely, the electrical performance is relative temperature insensitive, which is attractive in more reliable device operation point of view. In real cases, both TFE and FE conduction are quite common. To predict the potential conduction mechanism at the SiC ohmic contact interface, the characteristic energy E00 of 3C-, 4H- and 6H-SiC as well as Si is calculated [30] for doping values from 1 × 10<sup>16</sup> to 1 × 1020 cm−3 and plotted in **Figure 5**. Dielectric constants and electron conductivity effective mass are shown in **Table 1**. The specific boundaries between three mechanisms may vary a bit between groups; the one used in **Figure 5** is proposed by Schroder [31]. As can be seen, to enable FE tunnelling, a doping level above 1 × 1020 cm−3 is required for all semiconductors studied here.

Until now, the contact local doping level has been considered as a constant, which cannot be true for WBG materials. This is because with a wider band gap, dopants naturally sit in deeper energy levels and may not be thermally ionised at room temperature; it is called 'freeze-out' [33]. The partial ionisation of carriers leads to quite different ohmic contact performances from conventional theories. Field emission, for example, in which case the contact resistance used

to be temperature independent, now will drop with elevating temperature. This is because with more dopants ionised, the contact local doping increases; thus, the depletion width is reduced [34], in favour of the field emission conduction. On the other hand, partial ionisation also means it is more difficult to achieve lower contact resistance at room temperature. To compensate this, after metal deposition on even very highly doped SiC films, extra annealing step (1000–1200°C) is usually required to form a homogeneous silicide or carbide layer at the contact interface, which further lowers the Schottky barrier height, leading to a lower contact resistance. For N-type ohmic contact, nickel-based alloys are typically used, and resultant

**Figure 5.** Characteristic energy E00 as a function of doping density for n-type Si, 3C-, 4H- and 6H-SiC.

**Table 1.** Dielectric constants and electron conductivity effective mass of Si, 3C-, 4H- and 6H-SiC [32].

**Semiconductor Dielectric constant Electron conductivity effective mass**

Si 11.7 0.26 3C-SiC 9.72 0.32 4H-SiC 9.66 0.36 6H-SiC 9.66 0.57

rapid thermal anneal for SiC ohmic contact is still not clear; apart from the silicide reaction, which had been consistently observed and confirmed, local carbon clusters [37, 38] enriched at close to the contact interface, potentially providing more free carriers, were also often discussed and may have played a part, too. Specific contact resistance as low as 1 × 10−6 Ω cm<sup>2</sup> [9, 39] can be obtained on N-type SiC ohmic contact, and for the more difficult P-type due to

Si [35], while for P-type, Ti/Al alloys are common, leading to the formation

[36] at the interface after the contact anneal. The complete story behind the

is typical [12, 36, 40].

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 51

silicides are Ni<sup>2</sup>

SiC<sup>2</sup>

deeper acceptor level, a higher value around 1 × 10−4 Ω cm<sup>2</sup>

of TiC or Ti<sup>3</sup>

**Figure 4.** Metal-semiconductor (n-type) interface carrier conduction mechanisms for different doping levels.

**Figure 5.** Characteristic energy E00 as a function of doping density for n-type Si, 3C-, 4H- and 6H-SiC.

4H-SiC. To fabricate an ohmic contact, increasing the contact region local doping level (via thermal diffusion or ion implantation) is the most common way for both Si and SiC. When the contact region is lowly doped, the depletion region is quite wide that the electron exchange at the M-S interface is only possible when electrons overcome the barrier by gaining enough energy as shown in **Figure 4**, usually thermally activated and thus called thermionic emission (TE). If doping level is very high, the depletion region becomes quite narrow, and electrons can tunnel through the barrier freely with the help of an external electric field, which is called field emission (FE). And if the doping value is in the middle, the depletion region is narrowed but not enough to enable electron tunnelling. In this case, electrons still need extra thermal energy to 'climb up' the barrier, but not as much as TE. The energy required just needs to be adequate for the electrons to 'climb' to a position shallow enough for tunnelling that begins to take effect. Since both TE and FE mechanisms are involved, this is therefore called as therm-

50 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Among all, FE is the most desired conduction mechanism for deletion-type ohmic contact fabrication, since it is not a thermally activated process, namely, the electrical performance is relative temperature insensitive, which is attractive in more reliable device operation point of view. In real cases, both TFE and FE conduction are quite common. To predict the potential conduction mechanism at the SiC ohmic contact interface, the characteristic energy E00 of 3C-, 4H- and 6H-SiC as well as Si is calculated [30] for doping values from 1 × 10<sup>16</sup> to 1 × 1020 cm−3 and plotted in **Figure 5**. Dielectric constants and electron conductivity effective mass are shown in **Table 1**. The specific boundaries between three mechanisms may vary a bit between groups; the one used in **Figure 5** is proposed by Schroder [31]. As can be seen, to enable FE tunnelling, a doping level above 1 × 1020 cm−3 is required for all semiconductors studied here. Until now, the contact local doping level has been considered as a constant, which cannot be true for WBG materials. This is because with a wider band gap, dopants naturally sit in deeper energy levels and may not be thermally ionised at room temperature; it is called 'freeze-out' [33]. The partial ionisation of carriers leads to quite different ohmic contact performances from conventional theories. Field emission, for example, in which case the contact resistance used

**Figure 4.** Metal-semiconductor (n-type) interface carrier conduction mechanisms for different doping levels.

ionic/field emission (TFE).


**Table 1.** Dielectric constants and electron conductivity effective mass of Si, 3C-, 4H- and 6H-SiC [32].

to be temperature independent, now will drop with elevating temperature. This is because with more dopants ionised, the contact local doping increases; thus, the depletion width is reduced [34], in favour of the field emission conduction. On the other hand, partial ionisation also means it is more difficult to achieve lower contact resistance at room temperature. To compensate this, after metal deposition on even very highly doped SiC films, extra annealing step (1000–1200°C) is usually required to form a homogeneous silicide or carbide layer at the contact interface, which further lowers the Schottky barrier height, leading to a lower contact resistance. For N-type ohmic contact, nickel-based alloys are typically used, and resultant silicides are Ni<sup>2</sup> Si [35], while for P-type, Ti/Al alloys are common, leading to the formation of TiC or Ti<sup>3</sup> SiC<sup>2</sup> [36] at the interface after the contact anneal. The complete story behind the rapid thermal anneal for SiC ohmic contact is still not clear; apart from the silicide reaction, which had been consistently observed and confirmed, local carbon clusters [37, 38] enriched at close to the contact interface, potentially providing more free carriers, were also often discussed and may have played a part, too. Specific contact resistance as low as 1 × 10−6 Ω cm<sup>2</sup> [9, 39] can be obtained on N-type SiC ohmic contact, and for the more difficult P-type due to deeper acceptor level, a higher value around 1 × 10−4 Ω cm<sup>2</sup> is typical [12, 36, 40].

#### **4. SiC/SiO2 MOS interface**

Early MOSFETs have a long channel, leading to excessive on-state resistance which is not appropriate for power electronics, thus only applied in low power levels such as microprocessors, microcontrollers and logic circuits. On the other hand, the voltage-control and fast-switching features of MOSFETs are very attractive for power switch applications; consequently many efforts had been put into making power MOSFETs. The first high-voltage structure was developed in the 1970s and called V-MOSFET [41], named after the V-shape grove channel as seen in **Figure 6a**. This design never got popular due to the difficulty in fabricating a smooth V-shape trench on Si substrates, which was at that time formed by potassium hydroxide-based etching, whereas etching rate varies in different crystal orientations [42]. Also, the pointy trench bottom causes severe electric field crowding and easily leads to device early breakdown. Not long after, a planar structure shown in **Figure 6b** was invented. Instead of a V-shape grove, the channel was defined by controlling the thermal diffusion of dopants in the P-base and N<sup>+</sup> source regions, thus called vertical-diffused (VD) MOSFET. With main features relatively easy to fabricate and quite reliable, VD-MOSFET is the most successful design up to date. To achieve higher forward current density, the cell pitch of VD-MOSFET is usually made as small as possible. However, the narrow JFET region between two P-bases restricts the current flowing between channels and drift region, inducing extra on-resistance [43]. In the late 1980s, U-MOSFET design (**Figure 6c**) was proposed as a potential solution of getting rid of the JFET region. U-MOSFET is similar to the V-groove design in the sense that both of them use a trench to eliminate the JFET region, reducing the device on-resistance. By the time U-MOSFET was proposed, Si etching technology had been greatly improved that rounded trench corners are possible with reactive ion etching or other techniques [44]. However, the trench MOS interface and oxide reliability issues are not fully solved; consequently, U-MOSFETs still cannot compete with their planar counterparts.

All three power MOSFET designs introduced above have a vertical structure to maximise current handling ability of discrete devices. For vertical devices, the current rating can be increased by simply enlarging the device active area, such as bigger contacts for diodes or more parallel cells for MOSFETs. In some applications where power devices and control and logic circuits are integrated (e.g. smart power devices, power ICs), the processing and packaging may require all electrodes on the same side of the device, which makes a lateral design necessary, and this is where lateral diffused (LD) MOSFET fits in. As a modification from the long channel design, LDMOSFET usually has a much shorter channel length to minimise the on-resistance. Meanwhile, a long drift region is included for high-voltage purpose as seen in **Figure 6d**. Unlike vertical designs whose breakdown voltage is constrained by the drift region (epilayer) thickness, LDMOSFET utilises the semiconductor surface to greatly increase the device blocking voltage. Inevitably, the current conducting ability of LDMOSFET has to be greatly compromised. As a result, LDMOSFETs are mostly used for RF power amplifiers, microwave and medium power switching applications.

studied and the technology being very mature, the SiC/SiO<sup>2</sup>

Apart from phonon and coulombic which also troubles the bulk region, for channel region there is an extra surface roughness scattering mechanism. Among all, the Coulombic scattering caused by extra charges at the MOS interface is more process dependent and has been the target of studies. In real life, gate oxides are often with defects acting as carriers' leakage paths and cause early breakdown. By trapping and discharging carriers during the MOS device operation, these defects (also called states) are the main reason behind the severe Coulombic scattering. Extra charges found in most MOS systems are categorised into four groups, namely,

revealing all kinds of possibilities and challenges.

**Figure 6.** Schematic structure views of various MOSFET designs.

**4.1. Degradation of MOS channel mobility**

interface is still an active topic,

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 53

The adoption of WBG semiconductors enables MOSFETs to be used in power electronics applications with much higher power levels. While the Si/SiO<sup>2</sup> interface has been intensively

**Figure 6.** Schematic structure views of various MOSFET designs.

studied and the technology being very mature, the SiC/SiO<sup>2</sup> interface is still an active topic, revealing all kinds of possibilities and challenges.

#### **4.1. Degradation of MOS channel mobility**

**4. SiC/SiO2**

in the P-base and N<sup>+</sup>

 **MOS interface**

52 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Early MOSFETs have a long channel, leading to excessive on-state resistance which is not appropriate for power electronics, thus only applied in low power levels such as microprocessors, microcontrollers and logic circuits. On the other hand, the voltage-control and fast-switching features of MOSFETs are very attractive for power switch applications; consequently many efforts had been put into making power MOSFETs. The first high-voltage structure was developed in the 1970s and called V-MOSFET [41], named after the V-shape grove channel as seen in **Figure 6a**. This design never got popular due to the difficulty in fabricating a smooth V-shape trench on Si substrates, which was at that time formed by potassium hydroxide-based etching, whereas etching rate varies in different crystal orientations [42]. Also, the pointy trench bottom causes severe electric field crowding and easily leads to device early breakdown. Not long after, a planar structure shown in **Figure 6b** was invented. Instead of a V-shape grove, the channel was defined by controlling the thermal diffusion of dopants

features relatively easy to fabricate and quite reliable, VD-MOSFET is the most successful design up to date. To achieve higher forward current density, the cell pitch of VD-MOSFET is usually made as small as possible. However, the narrow JFET region between two P-bases restricts the current flowing between channels and drift region, inducing extra on-resistance [43]. In the late 1980s, U-MOSFET design (**Figure 6c**) was proposed as a potential solution of getting rid of the JFET region. U-MOSFET is similar to the V-groove design in the sense that both of them use a trench to eliminate the JFET region, reducing the device on-resistance. By the time U-MOSFET was proposed, Si etching technology had been greatly improved that rounded trench corners are possible with reactive ion etching or other techniques [44]. However, the trench MOS interface and oxide reliability issues are not fully solved; conse-

All three power MOSFET designs introduced above have a vertical structure to maximise current handling ability of discrete devices. For vertical devices, the current rating can be increased by simply enlarging the device active area, such as bigger contacts for diodes or more parallel cells for MOSFETs. In some applications where power devices and control and logic circuits are integrated (e.g. smart power devices, power ICs), the processing and packaging may require all electrodes on the same side of the device, which makes a lateral design necessary, and this is where lateral diffused (LD) MOSFET fits in. As a modification from the long channel design, LDMOSFET usually has a much shorter channel length to minimise the on-resistance. Meanwhile, a long drift region is included for high-voltage purpose as seen in **Figure 6d**. Unlike vertical designs whose breakdown voltage is constrained by the drift region (epilayer) thickness, LDMOSFET utilises the semiconductor surface to greatly increase the device blocking voltage. Inevitably, the current conducting ability of LDMOSFET has to be greatly compromised. As a result, LDMOSFETs are mostly used for RF power amplifiers,

The adoption of WBG semiconductors enables MOSFETs to be used in power electronics

interface has been intensively

quently, U-MOSFETs still cannot compete with their planar counterparts.

microwave and medium power switching applications.

applications with much higher power levels. While the Si/SiO<sup>2</sup>

source regions, thus called vertical-diffused (VD) MOSFET. With main

Apart from phonon and coulombic which also troubles the bulk region, for channel region there is an extra surface roughness scattering mechanism. Among all, the Coulombic scattering caused by extra charges at the MOS interface is more process dependent and has been the target of studies. In real life, gate oxides are often with defects acting as carriers' leakage paths and cause early breakdown. By trapping and discharging carriers during the MOS device operation, these defects (also called states) are the main reason behind the severe Coulombic scattering. Extra charges found in most MOS systems are categorised into four groups, namely, mobile charges, fixed charges, oxide-trapped charges and interface charges. A schematic graph indicating the general location and polarity of various charges are shown in **Figure 7**.

the interface traps come from unterminated Si dangling bonds. H<sup>2</sup>

SiC polytypes are similar [47]; thus, the study on the 4H-SiC/SiO<sup>2</sup>

great insight for other polytypes. Unfortunately, the 4H-SiC/SiO<sup>2</sup>

**4.2. SiC/SiO2**

 **interface traps**

density (Dit) at an as-grown 4H-SiC/SiO<sup>2</sup>

is hundreds of times higher than the Si/SiO<sup>2</sup>

Si(s) + O2(g) → SiO<sup>2</sup>

SiC(s) + x O2(g) → SiO<sup>2</sup>

SiC(s) + O2(g) → SiO<sup>2</sup>

[50] demonstrated an almost ideal SiC/SiO<sup>2</sup>

dation is typically applied to passivate the unterminated Si dangling bonds. Unlike the previous three, oxide-trapped charges are induced by the device operation rather than the fabrication process. The oxide layer, thermally grown or deposited, contains intrinsic defects such as oxygen vacancies [46]. Although these defects are electrically neutral, during the device operation, carriers may be injected into them and make them negatively or positively charged. Depending on the energy level, they may or may not be able to communicate with the semiconductor carriers. For those very close to the MOS interface that are able to be charged and discharged during device operation, they effectively behave as interface traps, otherwise similar to fixed charges.

With all the superior electrical performance and the ability to be thermally oxidised, it is no surprise that there are a lot of interests in making SiC MOS devices. The most commercialised 4H-SiC is naturally mostly studied. The hexagonal lattice of 4H-SiC means there will be several faces available for oxidation. Most of the work has been devoted into the (0001) Si-face, the only one available in commercial wafer form. Following discussions are therefore mainly based on (0001) Si-face. There have been studies suggesting that MOS interface traps for all

quite poor, and the electrical performance is not even close to the Si case. The interface trap

decreases with increasing Dit; thus, the latter is commonly used as an indicator for the MOS

still not fully understood. In [46], a discussion was made on the potential origins of interface traps, and two sources were identified, first of which is the carbon accumulated at the MOS interface during the SiC oxidation process. The reactions occurring during Si and SiC oxida-

Depending on the oxygen pressure, there may be some intermediate reactions [49], but it can be seen that SiC oxidation is accompanied by the release of gaseous carbon, either CO or CO<sup>2</sup>

However, the increase of oxide thickness after the oxidation process goes for a while makes it

The theory of carbon failing to escape through thicker oxide naturally leads to the idea that there should be less carbon at the MOS interface with thinner oxide. Indeed, a recent study

more difficult for carbon to escape, and the reaction (Eq. (3)) may occur instead:

interface quality. With decades of study, reasons behind the poor 4H-SiC/SiO<sup>2</sup>

tion processes can be generally expressed by reactions described in Eqs. (1) and (2):

annealing after the gate oxi-

55

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293

interface also provides a

interface turns out to be

interface are

.

interface is typically close to 10<sup>13</sup> cm−2 eV−1, which

interface [48]. The channel mobility generally

(s) (1)

(s) + CO/CO2(g) (2)

(s) + C(s) (3)

interface with a very thin oxide layer (≈14 nm);

Mobile charges are metal ionic impurities (such as Na+) introduced during the device fabrication process and can move freely in the oxide with a gate bias. Since positively charged, they will attract semiconductor electrons to the surface and induce extra band bending, leading to a shift of flat band voltage. Mobile charges are highly uncontrollable and thus must be minimised through clean and careful fabrication process. In contrast to mobile charges, fixed charges refer to those who do not move with gate biases. The origin of fixed charges is believed to be the excessive ions left near the interface after the oxidation process termination [45]. They are usually located in the oxide and close to the MOS interface as shown in **Figure 7**. Fixed charges can be both positive and negative, and the total amount depends heavily on the oxidation condition. Since fixed charges stay close to the interface, they also affect the semiconductor band bending. As a result, a shift of flat band voltage from the theoretical value is again observed.

Interface charges, as the name suggests, sit at the MOS interface. Energy levels of these traps are in the semiconductor band gap; consequently, they can act as carrier traps communicating (charge/discharge) with the bulk semiconductor during device operation. And since these traps are right at the MOS interface, they scatter the channel carriers much more than other charges. The origins of interface traps vary among different MOS systems. For Si/SiO<sup>2</sup> interface, most of

**Figure 7.** Common oxide charges at MOS interface with locations and charge polarity indicated.

the interface traps come from unterminated Si dangling bonds. H<sup>2</sup> annealing after the gate oxidation is typically applied to passivate the unterminated Si dangling bonds. Unlike the previous three, oxide-trapped charges are induced by the device operation rather than the fabrication process. The oxide layer, thermally grown or deposited, contains intrinsic defects such as oxygen vacancies [46]. Although these defects are electrically neutral, during the device operation, carriers may be injected into them and make them negatively or positively charged. Depending on the energy level, they may or may not be able to communicate with the semiconductor carriers. For those very close to the MOS interface that are able to be charged and discharged during device operation, they effectively behave as interface traps, otherwise similar to fixed charges.

#### **4.2. SiC/SiO2 interface traps**

mobile charges, fixed charges, oxide-trapped charges and interface charges. A schematic graph

Mobile charges are metal ionic impurities (such as Na+) introduced during the device fabrication process and can move freely in the oxide with a gate bias. Since positively charged, they will attract semiconductor electrons to the surface and induce extra band bending, leading to a shift of flat band voltage. Mobile charges are highly uncontrollable and thus must be minimised through clean and careful fabrication process. In contrast to mobile charges, fixed charges refer to those who do not move with gate biases. The origin of fixed charges is believed to be the excessive ions left near the interface after the oxidation process termination [45]. They are usually located in the oxide and close to the MOS interface as shown in **Figure 7**. Fixed charges can be both positive and negative, and the total amount depends heavily on the oxidation condition. Since fixed charges stay close to the interface, they also affect the semiconductor band bending. As a result, a shift of flat band voltage from the theoretical value is

Interface charges, as the name suggests, sit at the MOS interface. Energy levels of these traps are in the semiconductor band gap; consequently, they can act as carrier traps communicating (charge/discharge) with the bulk semiconductor during device operation. And since these traps are right at the MOS interface, they scatter the channel carriers much more than other charges.

interface, most of

The origins of interface traps vary among different MOS systems. For Si/SiO<sup>2</sup>

**Figure 7.** Common oxide charges at MOS interface with locations and charge polarity indicated.

indicating the general location and polarity of various charges are shown in **Figure 7**.

54 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

again observed.

With all the superior electrical performance and the ability to be thermally oxidised, it is no surprise that there are a lot of interests in making SiC MOS devices. The most commercialised 4H-SiC is naturally mostly studied. The hexagonal lattice of 4H-SiC means there will be several faces available for oxidation. Most of the work has been devoted into the (0001) Si-face, the only one available in commercial wafer form. Following discussions are therefore mainly based on (0001) Si-face. There have been studies suggesting that MOS interface traps for all SiC polytypes are similar [47]; thus, the study on the 4H-SiC/SiO<sup>2</sup> interface also provides a great insight for other polytypes. Unfortunately, the 4H-SiC/SiO<sup>2</sup> interface turns out to be quite poor, and the electrical performance is not even close to the Si case. The interface trap density (Dit) at an as-grown 4H-SiC/SiO<sup>2</sup> interface is typically close to 10<sup>13</sup> cm−2 eV−1, which is hundreds of times higher than the Si/SiO<sup>2</sup> interface [48]. The channel mobility generally decreases with increasing Dit; thus, the latter is commonly used as an indicator for the MOS interface quality. With decades of study, reasons behind the poor 4H-SiC/SiO<sup>2</sup> interface are still not fully understood. In [46], a discussion was made on the potential origins of interface traps, and two sources were identified, first of which is the carbon accumulated at the MOS interface during the SiC oxidation process. The reactions occurring during Si and SiC oxidation processes can be generally expressed by reactions described in Eqs. (1) and (2):

$$\text{Si(s)} + \text{O}\_2(\text{g}) \rightarrow \text{SiO}\_2(\text{s}) \tag{1}$$

$$\text{SiC(s)} + \text{xO}\_{2(g)} \rightarrow \text{SiO}\_{2}(s) + \text{CO/CO}\_{2(g)}\tag{2}$$

Depending on the oxygen pressure, there may be some intermediate reactions [49], but it can be seen that SiC oxidation is accompanied by the release of gaseous carbon, either CO or CO<sup>2</sup> . However, the increase of oxide thickness after the oxidation process goes for a while makes it more difficult for carbon to escape, and the reaction (Eq. (3)) may occur instead:

$$\text{SiC(s)} + \text{O}\_{2(g)} \rightarrow \text{SiO}\_{2}(s) + \text{C(s)}\tag{3}$$

The theory of carbon failing to escape through thicker oxide naturally leads to the idea that there should be less carbon at the MOS interface with thinner oxide. Indeed, a recent study [50] demonstrated an almost ideal SiC/SiO<sup>2</sup> interface with a very thin oxide layer (≈14 nm); the Dit value was below 10<sup>11</sup> cm−2 eV−1. However, as mentioned before a certain oxide thickness (≈50 nm for SiC MOS devices) is necessary for a reasonable threshold voltage, which means very thin oxide is not practical in real device fabrications. Thin thermally grown oxide with deposited oxide on top of it may be an option but still not easy, since deposited oxide is known to contain many more defects than thermally grown ones [51].

clusters near the 3C-SiC conduction band edge are donor-like, thus positively charged if unoccupied, which means the resultant threshold voltage may be more negative. Dangling bonds still contribute to some of the interface traps here but are only secondary concerns.

namely, post-oxidation annealing (POA), channel counter-doping and high-temperature

is usually achieved by annealing thermally grown gate oxides in nitrogenous trace gas envi-

bond breaks at high temperature and supplies free oxygen which oxidises 4H-SiC [54]; consequently, nitridation by POA is accompanied by a further growth of the oxide, although not significantly. Gate oxide can also be directly grown in such atmosphere to obtain similar benefits. Previous X-ray photoelectron spectroscopy (XPS) results showed that after NO/

O POA, there were fixed nitrogen atoms near the interface with a density ≈1 × 10<sup>14</sup> cm−2 [55], even after removing all the oxide by a hard HF etching, indicating that nitrogen atoms were strongly bonded to 4H-SiC substrate. There had been evidence showing the nitridation reduced both carbon-related and near-interface traps [56], even though there is still no complete explanation of the theory established. The near-interface traps are probably reduced by the formation of an oxynitride layer between 4H-SiC and gate oxide, which redefines the oxide/semiconductor boundary [57], and the oxide-trapped charges are no longer near the interface. In terms of the carbon clusters, they are probably decomposed by inserted nitrogen atoms, which shift the energy levels of remaining clusters deeper into band gap, namely, further away from the conduction band edge and less effective in terms of scattering channel

Nitridation may be the most widely used method to improve the 4H-SiC/SiO<sup>2</sup>

[59] or P<sup>2</sup>

increase further, and the peak value typically stays around 40 cm<sup>2</sup>

O5

into phosphor silicate glasses. Reducing the number of interface traps by introducing extra atoms into the interface is called passivation, and regardless of the source (N or P), it is always required that enough foreign atoms diffuse through the gate oxide and reach the interface. Certainly higher annealing temperature and time duration will help with that; however, due to the very low diffusion coefficient of nitrogen in SiC, nitrogen atoms saturate only within a monolayer deeper into the interface [61], and consequently the mobility value does not

a higher saturation density than nitrogen in 4H-SiC, but still, the peak mobility value stays

/V s [63] regardless of further increased annealing time durations. The limitation of thermal diffusion naturally leads to the idea of incorporating more passivating atoms into the interface by ion implantation, also known as channel counter-doping. 4H-SiC MOSFETs were fabricated on nitrogen-implanted substrates and higher peak channel mobility

although it introduced severe threshold voltage instability as a result of SiO<sup>2</sup>

interface optimisation.

annealing is not as effective as it is for Si. Other techniques had to

O), called post-oxidation annealing (POA). It is believed that the N-O

O/NO, it was reported that annealing the gate oxide in a phospho-

[60]) also led to a channel mobility improvement,

interface can be grouped into three directions,

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293

interfaces. It

57

being converted

/V s [62]. Phosphorous has

Consequently, for SiC, H<sup>2</sup>

 **interface treatments**

The efforts put into improving the SiC/SiO<sup>2</sup>

be explored for SiC/SiO<sup>2</sup>

**4.3. SiC/SiO2**

oxidation.

N2

ronment (NO or N<sup>2</sup>

carriers [58]. Apart from N<sup>2</sup>

around 80 cm<sup>2</sup>

rous trace atmosphere (POCl<sup>3</sup>

This leads to the second source of SiC/SiO<sup>2</sup> interface traps, namely, oxide defects. Oxide defectinduced traps are essentially the oxide-trapped charges mentioned before. In SiC/SiO<sup>2</sup> study they are also known as 'near-interface traps' since they do not actually sit at the interface but instead are located in the SiO<sup>2</sup> very close to the interface. For Si, energy levels of oxide-trapped states are in the conduction band, thus not electrically active. For SiC, however, whose band gaps are 2–3 times wider, many of the oxide-trapped charges located in the band gap are being electrically active, as has been confirmed by photon-stimulated electron tunnelling [52]. The near-interface traps have time constants much smaller than the carbon clusters, which are also called fast traps while the latter known as slow traps. A schematic representation of the carbon cluster mode is illustrated in **Figure 8** with energy levels of the traps specified. Due to the much lower mobility of holes than electrons, SiC MOS devices are almost exclusively based on n-channel design; naturally, the traps scattering the channel carriers most are the ones located close to the conduction band edge. **Figure 8** shows that the 4H-SiC conduction band edge is mostly troubled by near-interface traps and π-bonded carbon clusters, with the former more dominant. Both of these traps are accepter-like, namely, negatively charged when being occupied, which can explain the quite positive threshold values often observed for 4H-SiC MOS devices. On the other hand, 3C-SiC is free from near-interface traps attributed to a smaller band gap but is still troubled by π-bonded carbon clusters. These carbon

**Figure 8.** Schematic representation of the 'carbon cluster model' [53].

clusters near the 3C-SiC conduction band edge are donor-like, thus positively charged if unoccupied, which means the resultant threshold voltage may be more negative. Dangling bonds still contribute to some of the interface traps here but are only secondary concerns. Consequently, for SiC, H<sup>2</sup> annealing is not as effective as it is for Si. Other techniques had to be explored for SiC/SiO<sup>2</sup> interface optimisation.

#### **4.3. SiC/SiO2 interface treatments**

**Figure 8.** Schematic representation of the 'carbon cluster model' [53].

the Dit value was below 10<sup>11</sup> cm−2 eV−1. However, as mentioned before a certain oxide thickness (≈50 nm for SiC MOS devices) is necessary for a reasonable threshold voltage, which means very thin oxide is not practical in real device fabrications. Thin thermally grown oxide with deposited oxide on top of it may be an option but still not easy, since deposited oxide is

induced traps are essentially the oxide-trapped charges mentioned before. In SiC/SiO<sup>2</sup>

they are also known as 'near-interface traps' since they do not actually sit at the interface but

states are in the conduction band, thus not electrically active. For SiC, however, whose band gaps are 2–3 times wider, many of the oxide-trapped charges located in the band gap are being electrically active, as has been confirmed by photon-stimulated electron tunnelling [52]. The near-interface traps have time constants much smaller than the carbon clusters, which are also called fast traps while the latter known as slow traps. A schematic representation of the carbon cluster mode is illustrated in **Figure 8** with energy levels of the traps specified. Due to the much lower mobility of holes than electrons, SiC MOS devices are almost exclusively based on n-channel design; naturally, the traps scattering the channel carriers most are the ones located close to the conduction band edge. **Figure 8** shows that the 4H-SiC conduction band edge is mostly troubled by near-interface traps and π-bonded carbon clusters, with the former more dominant. Both of these traps are accepter-like, namely, negatively charged when being occupied, which can explain the quite positive threshold values often observed for 4H-SiC MOS devices. On the other hand, 3C-SiC is free from near-interface traps attributed to a smaller band gap but is still troubled by π-bonded carbon clusters. These carbon

interface traps, namely, oxide defects. Oxide defect-

very close to the interface. For Si, energy levels of oxide-trapped

study

known to contain many more defects than thermally grown ones [51].

56 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

This leads to the second source of SiC/SiO<sup>2</sup>

instead are located in the SiO<sup>2</sup>

The efforts put into improving the SiC/SiO<sup>2</sup> interface can be grouped into three directions, namely, post-oxidation annealing (POA), channel counter-doping and high-temperature oxidation.

Nitridation may be the most widely used method to improve the 4H-SiC/SiO<sup>2</sup> interfaces. It is usually achieved by annealing thermally grown gate oxides in nitrogenous trace gas environment (NO or N<sup>2</sup> O), called post-oxidation annealing (POA). It is believed that the N-O bond breaks at high temperature and supplies free oxygen which oxidises 4H-SiC [54]; consequently, nitridation by POA is accompanied by a further growth of the oxide, although not significantly. Gate oxide can also be directly grown in such atmosphere to obtain similar benefits. Previous X-ray photoelectron spectroscopy (XPS) results showed that after NO/ N2 O POA, there were fixed nitrogen atoms near the interface with a density ≈1 × 10<sup>14</sup> cm−2 [55], even after removing all the oxide by a hard HF etching, indicating that nitrogen atoms were strongly bonded to 4H-SiC substrate. There had been evidence showing the nitridation reduced both carbon-related and near-interface traps [56], even though there is still no complete explanation of the theory established. The near-interface traps are probably reduced by the formation of an oxynitride layer between 4H-SiC and gate oxide, which redefines the oxide/semiconductor boundary [57], and the oxide-trapped charges are no longer near the interface. In terms of the carbon clusters, they are probably decomposed by inserted nitrogen atoms, which shift the energy levels of remaining clusters deeper into band gap, namely, further away from the conduction band edge and less effective in terms of scattering channel carriers [58]. Apart from N<sup>2</sup> O/NO, it was reported that annealing the gate oxide in a phosphorous trace atmosphere (POCl<sup>3</sup> [59] or P<sup>2</sup> O5 [60]) also led to a channel mobility improvement, although it introduced severe threshold voltage instability as a result of SiO<sup>2</sup> being converted into phosphor silicate glasses. Reducing the number of interface traps by introducing extra atoms into the interface is called passivation, and regardless of the source (N or P), it is always required that enough foreign atoms diffuse through the gate oxide and reach the interface. Certainly higher annealing temperature and time duration will help with that; however, due to the very low diffusion coefficient of nitrogen in SiC, nitrogen atoms saturate only within a monolayer deeper into the interface [61], and consequently the mobility value does not increase further, and the peak value typically stays around 40 cm<sup>2</sup> /V s [62]. Phosphorous has a higher saturation density than nitrogen in 4H-SiC, but still, the peak mobility value stays around 80 cm<sup>2</sup> /V s [63] regardless of further increased annealing time durations.

The limitation of thermal diffusion naturally leads to the idea of incorporating more passivating atoms into the interface by ion implantation, also known as channel counter-doping. 4H-SiC MOSFETs were fabricated on nitrogen-implanted substrates and higher peak channel mobility (≈60 cm<sup>2</sup> /V s) than unimplanted or even NO/N<sup>2</sup> O annealed samples was observed [64–66], before the mobility curve becomes significantly distorted for a dose level of 2.2 × 10<sup>14</sup> cm−2. The success of counter-doping technique brings in another possible explanation [66] other than the defect passivation for the improved 4H-SiC/SiO<sup>2</sup> interface. With the channel surface being partially compensated by the nitrogen implantation, a depletion region is formed between the thin counter-doped n-type surface and the underlying p-type channel region. The n-type counter-doped surface may be positively charged even without any gate bias due to the p-n junction depletion. In inversion mode, higher carrier mobility can be achieved since these positive charges will cancel part of the negative electric field built in the channel region, reducing the surface roughness scattering. Apart from nitrogen, other elements were also studied for the counterdoping. In [67], a variety of ions including B, N, F, Al, P and Cl were individually implanted into a 4H-SiC substrate, which was then oxidised to make MOS capacitors. It turned out only group V elements (N and P) led to a reduced Dit while the other increased it. A negative shift of flat band voltage is always observed for N or P counter-doped MOSFETs, a natural result of the channel being partially compensated. For devices fabricated with N- or P-based POAs, similar negative shifts were also observed, which suggests that counter-doping may have occurred in POAs through minor thermal diffusion, making it difficult to distinguish the effects from passivation and counter-doping. More recently [68], counter-doping 4H-SiC MOSFET channel using Sb was studied, and a peak field-effect mobility as high as 80 cm<sup>2</sup> /V s was obtained. The fact that the mobility value dropped to almost zero at 70 K (Sb freezes out) confirmed that the improvement is not achieved by defect passivation, since otherwise the mobility should only be influenced by SiC electrons and the Sb freeze-out will have minimal effect. Further processing the Sb counter-doped sample with NO POA led to an increased channel mobility in all temperatures including 70 K, which suggests that the counter-doping and defect passivation may be two independent mechanisms, yet both increase the channel mobility.

**References**

MOSFET. Cree Press Release; 2015

10.1063/1.1651325

9-7121-0

10.1109/5.658764

10.1088/0143-0807/10/4/002

tion.html. [Accessed: 2018-01-02]

10.1007/s11664-010-1128-1

10.1088/0268-1242/29/7/075018

DOI: 10.1088/0022-3727/44/25/255302

s11664-008-0405-8

Books, Gordon and Breach Science Pub.; 2004

[1] CoolSiC™ MOSFET, revolution to rely on. Infineon Technologies AG; 2016

[2] Cree redefines the discrete power MOSFET landscape with the industry's first 900-V SiC

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 59

[3] Dhar S, Song YW, Feldman LC, Isaacs-Smith T, Tin CC, Williams JR, et al. Effect of nitric oxide annealing on the interface trap density near the conduction band edge of 4H--SiC at the oxide/(112-0) 4H--SiC interface. Applied Physics Letters. 2004;**84**:1498-1500. DOI:

[4] Busch G. Early history of the physics and chemistry of semiconductors-from doubts to fact in a hundred years. European Journal of Physics. 1989;**10**(4):254-260. DOI:

[5] Wijesundara M, Azevedo R. Silicon Carbide Microsystems for Harsh Environments. New York: Springer-Verlag, Springer Science & Business Media; 2011. DOI: 10.1007/978-1-441

[6] Fair RB. History of some early developments in ion-implantation technology leading to silicon transistor manufacturing. Proceedings of the IEEE. 1998;**86**(1):111-137. DOI:

[7] Group TP. Components and spare parts for ion implantation [Internet]. 2018. Available from: https://www.plansee.com/en/products/components/spare-parts-for-ion implanta-

[8] Zhe CF. Silicon Carbide: Materials, Processing & Devices. Amsterdam: Taylor & Francis

[9] Li M, Ahyi AC, Zhu X, Chen Z, Isaacs-Smith T, Williams JR, et al. Nickel ohmic contacts to N-implanted (0001) 4H-SiC. Journal of Electronic Materials. 2010;**39**(5):540-544. DOI:

[10] Vivona M, Greco G, Giannazzo F, Nigro RL, Rascuna S, Saggio M, Roccaforte F. Thermal stability of the current transport mechanisms in Ni-based ohmic contacts on n- and p-implanted 4H-SiC. Semiconductor Science and Technology. 2014;**29**(7):075018. DOI:

[11] Jones KA, Wood MC, Zheleva TS, Kirchner KW, Derenge MA, Bolonikov A, et al. Structural and chemical comparison of graphite and BN/AlN caps used for annealing ion implanted SiC. Journal of Electronic Materials. 2008;**37**(6):917-924. DOI: 10.1007/

[12] Frazzetto A, Giannazzo F, Nigro RL, Raineri V, Roccaforte F. Structural and transport properties in alloyed Ti/Al Ohmic contacts formed on p-type Al-implanted 4H-SiC annealed at high temperature. Journal of Physics D: Applied Physics. 2011;**44**(25):255302.

Both previous methods introduce extra foreign element atoms to the SiC/SiO<sup>2</sup> system. It will be ideal to have an as-oxidised MOS interface free from excessive interface traps. Hightemperature oxidation is considered as a possible solution. It was firstly reported in [69] that Dit decreases with increasing oxidation temperature, which was related to a reduction of SiCx Oy near the interface at higher oxidation temperature. More recently [70], a channel mobility of 40 cm<sup>2</sup> /V s was reported for 4H-SiC MOSFET with gate oxide thermally grown at 1500°C without any further treatment, and the XPS measurement suggests a reduction of carbon near the interface. The mechanism behind high-temperature oxidation is still unclear and needs to be explored more.

#### **Author details**

Fan Li<sup>1</sup> \* and Mike Jennings<sup>2</sup>

Address all correspondence to: f.li.3@warwick.ac.uk

1 University of Warwick, Coventry, United Kingdom

2 School of Engineering, University of Warwick, Coventry, United Kingdom

#### **References**

(≈60 cm<sup>2</sup>

of SiCx Oy

Fan Li<sup>1</sup>

mobility of 40 cm<sup>2</sup>

**Author details**

and needs to be explored more.

\* and Mike Jennings<sup>2</sup>

Address all correspondence to: f.li.3@warwick.ac.uk 1 University of Warwick, Coventry, United Kingdom

/V s) than unimplanted or even NO/N<sup>2</sup>

58 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

using Sb was studied, and a peak field-effect mobility as high as 80 cm<sup>2</sup>

be two independent mechanisms, yet both increase the channel mobility.

Both previous methods introduce extra foreign element atoms to the SiC/SiO<sup>2</sup>

2 School of Engineering, University of Warwick, Coventry, United Kingdom

passivation for the improved 4H-SiC/SiO<sup>2</sup>

the mobility curve becomes significantly distorted for a dose level of 2.2 × 10<sup>14</sup> cm−2. The success of counter-doping technique brings in another possible explanation [66] other than the defect

compensated by the nitrogen implantation, a depletion region is formed between the thin counter-doped n-type surface and the underlying p-type channel region. The n-type counter-doped surface may be positively charged even without any gate bias due to the p-n junction depletion. In inversion mode, higher carrier mobility can be achieved since these positive charges will cancel part of the negative electric field built in the channel region, reducing the surface roughness scattering. Apart from nitrogen, other elements were also studied for the counterdoping. In [67], a variety of ions including B, N, F, Al, P and Cl were individually implanted into a 4H-SiC substrate, which was then oxidised to make MOS capacitors. It turned out only group V elements (N and P) led to a reduced Dit while the other increased it. A negative shift of flat band voltage is always observed for N or P counter-doped MOSFETs, a natural result of the channel being partially compensated. For devices fabricated with N- or P-based POAs, similar negative shifts were also observed, which suggests that counter-doping may have occurred in POAs through minor thermal diffusion, making it difficult to distinguish the effects from passivation and counter-doping. More recently [68], counter-doping 4H-SiC MOSFET channel

fact that the mobility value dropped to almost zero at 70 K (Sb freezes out) confirmed that the improvement is not achieved by defect passivation, since otherwise the mobility should only be influenced by SiC electrons and the Sb freeze-out will have minimal effect. Further processing the Sb counter-doped sample with NO POA led to an increased channel mobility in all temperatures including 70 K, which suggests that the counter-doping and defect passivation may

will be ideal to have an as-oxidised MOS interface free from excessive interface traps. Hightemperature oxidation is considered as a possible solution. It was firstly reported in [69] that Dit decreases with increasing oxidation temperature, which was related to a reduction

at 1500°C without any further treatment, and the XPS measurement suggests a reduction of carbon near the interface. The mechanism behind high-temperature oxidation is still unclear

near the interface at higher oxidation temperature. More recently [70], a channel

/V s was reported for 4H-SiC MOSFET with gate oxide thermally grown

O annealed samples was observed [64–66], before

interface. With the channel surface being partially

/V s was obtained. The

system. It


[13] Jacob C, Pirouz P, Kuo HI, Mehregany M. High temperature ohmic contacts to 3C–silicon carbide films. Solid-State Electronics. 1998;**42**(12):2329-2334. DOI: 10.1016/S0038-1101(98) 00234-2

[25] Parisini A, Gorni M, Nath A, Belsito L, Rao MV, Nipoti R. Remarks on the room temperature impurity band conduction in heavily Al+ implanted 4H-SiC. Journal of Applied

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293 61

[26] Laube M, Schmid F, Pensl G, Wagner G, Linnarsson M, Maier M. Electrical activation of high concentrations of N+ and P+ ions implanted into 4H–SiC. Journal of Applied

[27] Braun F. On the current transport in metal sulfides. Annual Review of Physical Chemistry.

[28] Lide D, Bruno TJ, Haynes W. CRC Handbook of Chemistry and Physics: A Ready-Reference Book of Chemical and Physical Data. Boca Raton: CRC Press; 2009

[29] Roccaforte F, Giannazzo F, Raineri V. Nanoscale transport properties at silicon carbide interfaces. Journal of Physics D: Applied Physics. 2010;**43**(22):223001. DOI: 10.1088/0022-

[30] Padovani FA, Stratton R. Field and thermionic-field emission in Schottky barriers. Solid-

[31] Schroder DK. Semiconductor Material and Device Characterization. 3rd ed. Hoboken,

[32] Levinshtein ME, Rumyantsev SL, Shur MS. Properties of Advanced Semiconductor Materials: GaN, AIN, InN, BN, SiC, SiGe. New York, Chichester, Weinheim, Brisbane,

[33] Shou-Guo W, Yi-Men Z, Yu-Ming Z. Theoretical investigation of incomplete ionization of dopants in uniform and ion-implanted 4H-SiC MESFETs. Chinese Physics.

[34] Perez-Tomas A, Fontsere A, Placidi M, Jennings MR, Gammon PM. Modelling the metal–semiconductor band structure in implanted ohmic contacts to GaN and SiC. Modelling and Simulation in Materials Science and Engineering. 2013;**21**(3):035004.

[35] Kuchuk A, Kladko V, Guziewicz M, Piotrowska A, Minikayev R, Stonert A, Ratajczak R. Fabrication and characterization of nickel silicide ohmic contacts to n-type 4H silicon carbide. Journal of Physics: Conference Series. 2008;**100**(4):042003. DOI: 10.1088/

[36] Jennings MR, Fisher CA, Walker D, Sanchez A, Pérez-Tomás A, Hamilton DP, et al. On

[37] Levit M, Grimberg I, Weiss BZ. Interaction of Ni90Ti10 alloy thin film with 6H-SiC single crystal. Journal of Applied Physics. 1996;**80**(1):167-173. DOI: 10.1063/1.362801

[38] Roccaforte F, La Via F, Baeri A, Raineri V, Calcagno L, Mangano F. Structural and electrical properties of Ni∕Ti Schottky contacts on silicon carbide upon thermal annealing.

Journal of Applied Physics. 2004;**96**(8):4313-4318. DOI: 10.1063/1.1787138

Science Forum. 2014;**778-780**:693-696. DOI: 10.4028/www.scientific.net/MSF.778-780.693

metallic phase formation for robust p-Type 4H-SiC ohmic contacts. Materials

State Electronics. 1966;**9**(7):695-707. DOI: 10.1016/0038-1101(66)90097-9

New Jersey: John Wiley & Sons; 2006. DOI: 10.1002/0471749095

Singapore, Toronto: John Wiley & Sons; 2001

DOI: 10.1088/0965-0393/21/3/035004/meta

1742-6596/100/4/042003/meta

the Ti<sup>3</sup>

SiC<sup>2</sup>

2003;**12**(1):89-93. DOI: 10.1088/1009-1963/12/1/316

Physics. 2015;**118**(3):035101. DOI: 10.1063/1.4926751

Physics. 2002;**92**(1):549-554. DOI: 10.1063/1.1479462

1874;**153**:556-563

3727/43/22/223001/meta


[25] Parisini A, Gorni M, Nath A, Belsito L, Rao MV, Nipoti R. Remarks on the room temperature impurity band conduction in heavily Al+ implanted 4H-SiC. Journal of Applied Physics. 2015;**118**(3):035101. DOI: 10.1063/1.4926751

[13] Jacob C, Pirouz P, Kuo HI, Mehregany M. High temperature ohmic contacts to 3C–silicon carbide films. Solid-State Electronics. 1998;**42**(12):2329-2334. DOI: 10.1016/S0038-1101(98)

[14] Capano MA, Ryu S, Cooper JA Jr, Melloch MR, Rottner K, Karlsson S, et al. Surface roughening in ion implanted 4H-silicon carbide. Journal of Electronic Materials. 1999;

[15] Negoro Y, Katsumoto K, Kimoto T, Matsunami H. Electronic behaviors of high-dose phosphorus-ion implanted 4H–SiC (0001). Journal of Applied Physics. 2004;**96**(1):224-

[16] Vassilevski KV, Wright NG, Nikitina IP, Horsfall AB, O'Neill AG, Uren MJ, Hilton KP, Masterton AG, Hydes AJ, Johnson CM. Protection of selectively implanted and patterned silicon carbide surfaces with graphite capping layer during post-implantation annealing. Semiconductor Science and Technology. 2005;**20**(3):271-278. DOI:

[17] Derenge MA, Jones KA, Kirchner K, Ervin M, editors. A Comparison of the AlN Annealing Cap for 4H SiC Annealed in a Nitrogen Versus an Argon Atmosphere. 2003 International Semiconductor Device Research Symposium; 2003. DOI: 10.1109/ISDRS.2003.1272026

[18] Jones KA, Shah PB, Kirchner KW, Lareau RT, Wood MC, Ervin MH, et al. Annealing ion implanted SiC with an AlN cap. Materials Science and Engineering: B. 1999;**61-62**:281-

[19] Ruppalt L, Stafford S, Yuan D, Vispute R, Venkatesan T, Sharma R, et al. Using a PLD BN/AlN composite as an annealing cap for ion implanted SiC. In: 2001 International Semiconductor Device Research symposium; 2001. DOI: 10.1109/ISDRS.2001.984565

[20] Naik H, Tang K, Chow TP. Effect of graphite cap for implant activation on inversion channel mobility in 4H-SiC MOSFETs. Materials Science Forum. 2009;**615-617**:773-776.

phorus implant activation in 4H-SiC. Materials Letters. 2010;**64**(23):2593-2596. DOI:

[22] Song X, Biscarrat J, Michaud J-F, Cayrel F, Zielinski M, Chassagne T, et al. Structural and electrical characterizations of n-type implanted layers and ohmic contacts on 3C-SiC. Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with

[23] Bazin A, Michaud J, Autret-Lambert C, Cayrel F, Chassagne T, Portail M, et al. Ti–Ni ohmic contacts on 3C–SiC doped by nitrogen or phosphorus implantation. Materials

Science and Engineering: B. 2010;**171**(1):120-126. DOI: 10.1016/j.mseb.2010.03.084 [24] Song X, Bazin AE, Michaud JF, Cayrel F, Zielinski M, Portail M, et al. Electrical characterization of nitrogen implanted 3C-SiC by SSRM and CTLM measurements. Materials Science Forum. 2011;679**-680**:193-196. DOI: 10.4028/www.scientific.net/MSF.679-680.193

Materials and Atoms. 2011;**269**(18):2020-2025. DOI: 10.1016/j.nimb.2011.06.004

encapsulation for aluminium and phos-

**28**(3):214-218. DOI: 10.1007/s11664-999-0016-z

60 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

228. DOI: 10.1063/1.1756213

10.1088/0268-1242/20/3/003/meta

286. DOI: 10.1016/S0921-5107(98)00518-2

DOI: 10.4028/www.scientific.net/MSF.615-617.773

[21] Zhao F, Islam MM, Huang C-F. Study of SiO<sup>2</sup>

10.1016/j.matlet.2010.08.048

00234-2


[39] Biscarrat J, Song X, Michaud JF, Cayrel F, Portail M, Zielinski M, et al. Ti thickness influence for Ti/Ni ohmic contacts on n-type 3C-SiC. Materials Science Forum. 2012;**711**:179- 183. DOI: 10.4028/www.scientific.net/MSF.711.179

[53] Esteve R. Fabrication and Characterization of 3C-and 4H-SiC MOSFETs [thesis]. School

[54] Morales-Acevedo A, Santana G, Carrillo-López J. Thermal oxidation of silicon in nitrous oxide at high pressures. Journal of The Electrochemical Society. 2001;**148**(10):F200-F202.

their direct relationship to interface trap density. Applied Physics Letters. 2011;**99**(18):

[56] Afanas'ev VV, Stesmans A, Ciobanu F, Pensl G, Cheong KY, Dimitrijev S. Mechanisms

[57] Rozen J, Dhar S, Zvanut ME, Williams JR, Feldman LC. Density of interface states, elec-

[58] McDonald K, Weller RA, Pantelides ST, Feldman LC, Chung GY, Tin CC, et al. Characterization and modelling of the nitrogen passivation of interface traps in SiO<sup>2</sup>

[59] Okamoto D, Yano H, Kenji H, Hatayama T, Fuyuki T. Improved inversion channel mobility in 4H-SiC MOSFETs on Si face utilizing phosphorus-doped gate oxide. Electron

[60] Sharma YK, Ahyi AC, Isaacs-Smith T, Modic A, Park M, Xu Y, et al. High-mobility stable 4H-SiC MOSFETs using a thin PSG interfacial passivation layer. Electron Device Letters,

[61] Chen Z, Xu Y, Garfunkel E, Feldman LC, Buyuklimanli T, Ou W, et al. Kinetics of nitro-

[62] Rozen J, Ahyi AC, Xingguang Z, Williams JR, Feldman LC. Scaling between channel mobility and interface state density in SiC MOSFETs. IEEE Transactions on Electron

[63] Sharma YK, Ahyi AC, Issacs-Smith T, Shen X, Pantelides ST, Zhu X, et al. Phosphorous

[64] Moscatelli F, Poggi A, Solmi S, Nipoti R. Nitrogen implantation to improve electron channel mobility in 4H-SiC MOSFET. IEEE Transactions on Electron Devices. 2008;**55**(4):961-

[65] Poggi A, Moscatelli F, Hijikata Y, Solmi S, Nipoti R. MOS capacitors obtained by wet oxidation of n-type 4H–SiC pre-implanted with nitrogen. Microelectronic Engineering.

SiC. Journal of Applied Physics. 2003;**93**(5):2719-2722. DOI: 10.1063/1.1542935

Device Letters, IEEE. 2010;**31**(7):710-712. DOI: 10.1109/LED.2010.2047239

Surface Science. 2014;**317**:593-597. DOI: 10.1016/j.apsusc.2014.08.181

Devices. 2011;**58**(11):3808-3811. DOI: 10.1109/TED.2011.2164800

/SiC interface region and

on SiC. Journal of

/4H–

63

interface properties by nitridation. Applied

Main Differences in Processing Si and SiC Devices http://dx.doi.org/10.5772/intechopen.76293

/4H-SiC interface during an NO passivation. Applied

/4H–SiC interface. Solid-State Electronics. 2012;**68**:103-107. DOI:

of Information and Communication Technology (ICT), KTH; 2011.

[55] Kosugi R, Umeda T, Sakuma Y. Fixed nitrogen atoms in the SiO<sup>2</sup>

Physics Letters. 2003;**82**(4):568-570. DOI: 10.1063/1.1532103

Applied Physics. 2009;**105**(12):124506. DOI: 10.1063/1.3131845

IEEE. 2013;**34**(2):175-177. DOI: 10.1109/LED.2012.2232900

tron traps, and hole traps as a function of the nitrogen density in SiO<sup>2</sup>

DOI: 10.1149/1.1398278

182111. DOI: 10.1063/1.3659689

gen incorporation at the SiO<sup>2</sup>

passivation of the SiO<sup>2</sup>

10.1016/j.sse.2011.10.030

967. DOI: 10.1109/TED.2008.917107

2007;**84**(12):2804-2809. DOI: 10.1016/j.mee.2007.01.241

responsible for improvement of 4H–SiC/SiO<sup>2</sup>


[53] Esteve R. Fabrication and Characterization of 3C-and 4H-SiC MOSFETs [thesis]. School of Information and Communication Technology (ICT), KTH; 2011.

[39] Biscarrat J, Song X, Michaud JF, Cayrel F, Portail M, Zielinski M, et al. Ti thickness influence for Ti/Ni ohmic contacts on n-type 3C-SiC. Materials Science Forum. 2012;**711**:179-

[40] Fisher C, Jennings M, Sharma Y, Sanchez-Fuentes A, Walker D, Gammon P, et al.

[41] Holmes FE, Salama CAT. VMOS—A new MOS integrated circuit technology. Solid-State

[42] Baliga BJ. Fundamentals of Power Semiconductor Devices. Springer Science & Business

[43] Ng JCW, Sin JKO. A low-voltage planar power MOSFET with a segmented JFET region. IEEE Transactions on Electron Devices. 2009;**56**(8):1761-1766. DOI: 10.1109/TED.

[44] Saxena RS, Kumar MJ. Trench gate power MOSFET: Recent advances and innovations. In: Jit S, editor. Advances in Microelectronics and Photonics, Chapter 1. NY: Nova

[45] Brennan KF. Introduction to Semiconductor Devices: For Computing and Telecommuni-

Status Solidi (a). 1997;**162**(1):321-337. DOI: 10.1002/1521-396X(199707)162:1<321::AID-

[47] Afanasev VV, Ciobanu F, Pensl G, Stesmans A. Contributions to the density of interface states in SiC MOS structures. In: Choyke WJ, Matsunami H, Pensl G, editors. Silicon Carbide: Recent Major Advances. Verlag, Berlin, Heidelberg and New York: Springer;

[48] Liu G, Tuttle BR, Dhar S. Silicon carbide: A unique platform for metal-oxide-semiconductor physics. Applied Physics Reviews. 2015;**2**(2):021307. DOI: 10.1063/1.4922748 [49] Roy J, Chandra S, Das S, Maitra S. Oxidation behaviour of silicon carbide-a review.

itance-voltage characteristics by thermal oxidation. Applied Physics Letters. 2014;**105**

ited by PECVD using an oxygen-TEOS-argon mixture. Brazilian Journal of Physics.

for a defect-assisted process. Journal of Physics: Condensed Matter. 1997;**9**(6):L55. DOI:

4H-SiC. International Journal of Fundamental Physical Sciences. 2014;**4**(3). DOI: 10.14331/

SiC<sup>2</sup>

in ohmic contacts to P-Type

interface states. Physica

thin films depos-

: Evidence

/4H-SiC (0001) interface with nearly ideal capac-

183. DOI: 10.4028/www.scientific.net/MSF.711.179

Media; 2010. DOI: 10.1007/978-0-387-47314-7\_6

Science Publishers Inc; 2012. pp. 1-23

ijfps.2014.330071

2009.2024105

PSSA321>3.0.CO;2-F

On the Schottky barrier height lowering effect of Ti<sup>3</sup>

62 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Electronics. 1974;**17**(8):791-797. DOI: 10.1016/0038-1101(74)90026-4

cations Applications. New York: Cambridge University Press; 2005

[46] Afanasev VV, Bassler M, Pensl G, Schulz M. Intrinsic SiC/SiO<sup>2</sup>

2004. pp. 343-371. DOI : 10.1007/978-3-642-18870-1

Review on Advanced Materials Science. 2014;**38**:29-39

[51] Viana CE, Silva ANRd, Morimoto NI, Bonnaud O. Analysis of SiO<sup>2</sup>

[52] Afanas'ev VV, Stesmans A. Photon-stimulated tunnelling of electrons in SiO<sup>2</sup>

2001;**31**:299-303. DOI: 10.1590/S0103-97332001000200023

[50] Kikuchi RH, Kita K. Fabrication of SiO<sup>2</sup>

(3):032106. DOI: 10.1063/1.4891166

10.1088/0953-8984/9/6/002


[66] Dhar S, Sei-Hyung R, Agarwal AK. A study on pre-oxidation nitrogen implantation for the improvement of channel mobility in 4H-SiC MOSFETs. IEEE Transactions on Electron Devices. 2010;**57**(6):1195-1200. DOI: 10.1109/TED.2010.2045670

**Chapter 4**

**Provisional chapter**

**High-Performance Packaging Technology for Wide**

**High-Performance Packaging Technology for Wide** 

The properties of wide band gap (WBG) semiconductors are beneficial to power electronics applications ranging from consumer electronics and renewable energy to electric vehicles and high-power traction applications like high-speed trains. WBG devices, properly integrated, will allow power electronics systems to be smaller, lighter, operate at higher temperatures, and at higher frequencies than previous generations of Si-based systems. These will contribute to higher efficiency, and therefore, lower lifecycle costs

low-defect-density wafers, epitaxy, and device fabrication and processing technology. In power electronics applications, devices are normally packaged into large integrated modules with electrical, mechanical and thermal connection to the system and control circuit. The first generations of WBG device have used conventional or existing module designs to allow drop-in replacement of Si devices; this approach limits the potential benefit. To realize the full potential of WBG devices, especially the higher operating temperatures and faster switching frequency, a new generation of packaging design and

**Keywords:** reliability, solder, wirebonding, inductance, thermal impedance, sintering,

Semiconductor packaging provides the interface between semiconductor devices and the outside world. All semiconductor devices need packaging of some sort, whether they are the integrated circuits of a computer's central processing unit, an amplifier, diode, transistor or

emissions. Over 20 years have been spent developing WBG materials,

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

DOI: 10.5772/intechopen.78765

**Bandgap Semiconductor Modules**

**Bandgap Semiconductor Modules**

Paul Mumby-Croft, Daohui Li, Xiaoping Dai and

Paul Mumby-Croft, Daohui Li, Xiaoping Dai and

technology concepts must be widely implemented.

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.78765

Guoyou Liu

Guoyou Liu

**Abstract**

and lower CO<sup>2</sup>

high-frequency

**1. Introduction**


#### **High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules**

DOI: 10.5772/intechopen.78765

Paul Mumby-Croft, Daohui Li, Xiaoping Dai and Guoyou Liu Paul Mumby-Croft, Daohui Li, Xiaoping Dai and Guoyou Liu

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.78765

#### **Abstract**

[66] Dhar S, Sei-Hyung R, Agarwal AK. A study on pre-oxidation nitrogen implantation for the improvement of channel mobility in 4H-SiC MOSFETs. IEEE Transactions on

[67] Okamoto D, Yano H, Hatayama T, Fuyuki T. Systematic investigation of interface properties in 4H-SiC MOS structures prepared by over-oxidation of ion-implanted substrates. Materials Science Forum. 2010;**645-648**:495-498. DOI: 10.4028/www.scientific.

[68] Modic A, Gang L, Ahyi AC, Yuming Z, Pingye X, Hamilton MC, et al. High channel mobility 4H-SiC MOSFETs by antimony counter-doping. Electron Device Letters. 2014;**35**(9):

[69] Kurimoto H, Shibata K, Kimura C, Aoki H, Sugino T. Thermal oxidation temperature dependence of 4H-SiC MOS interface. Applied Surface Science. 2006;**253**(5):2416-2420.

[70] Thomas SM, Sharma YK, Crouch MA, Fisher CA, Perez-Tomas A, Jennings MR, et al. Enhanced field effect mobility on 4H-SiC by oxidation at 1500°C. IEEE Journal of the

Electron Devices Society. 2014;**2**(5):114-117. DOI: 10.1109/JEDS.2014.2330737

Electron Devices. 2010;**57**(6):1195-1200. DOI: 10.1109/TED.2010.2045670

64 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

net/MSF.645-648.495

894-896. DOI: 10.1109/LED.2014.2336592

DOI: 10.1016/j.apsusc.2006.04.054

The properties of wide band gap (WBG) semiconductors are beneficial to power electronics applications ranging from consumer electronics and renewable energy to electric vehicles and high-power traction applications like high-speed trains. WBG devices, properly integrated, will allow power electronics systems to be smaller, lighter, operate at higher temperatures, and at higher frequencies than previous generations of Si-based systems. These will contribute to higher efficiency, and therefore, lower lifecycle costs and lower CO<sup>2</sup> emissions. Over 20 years have been spent developing WBG materials, low-defect-density wafers, epitaxy, and device fabrication and processing technology. In power electronics applications, devices are normally packaged into large integrated modules with electrical, mechanical and thermal connection to the system and control circuit. The first generations of WBG device have used conventional or existing module designs to allow drop-in replacement of Si devices; this approach limits the potential benefit. To realize the full potential of WBG devices, especially the higher operating temperatures and faster switching frequency, a new generation of packaging design and technology concepts must be widely implemented.

**Keywords:** reliability, solder, wirebonding, inductance, thermal impedance, sintering, high-frequency

#### **1. Introduction**

Semiconductor packaging provides the interface between semiconductor devices and the outside world. All semiconductor devices need packaging of some sort, whether they are the integrated circuits of a computer's central processing unit, an amplifier, diode, transistor or

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

any other kind of device. This chapter focuses on power modules: a subsection of the field of semiconductor packaging. A power module normally contains several power electronics devices such as MOSFETs or IGBTs, diodes, and often the associated passive components like gate resistors and DC link capacitors. The package provides a mechanical interface with the rest of the system, since most semiconductor components produce heat that must be managed in order to keep the device below its maximum allowable junction temperate (Tjmax), the package is almost always mechanically connected to a heatsink. The packaging is also the primary thermal interface between the heat-generating devices and the heat sink. The operating temperature of the devices defines their performance and long-term reliability, if devices operate at higher temperatures their reliability will decrease exponentially as temperature increases [1]. As a result, the thermal interface provided by the packaging is crucially important, and many of the properties of the processes and materials are optimized to provide the best possible heat sink with the lowest achievable thermo-mechanical stress. Electrical interfaces between the devices and the system are also features of the package, with signal pins and power terminals being internally connected to the devices, and emerging through the packaging to allow external connections. Depending on the design, it is also common for electrical insulation to be a feature of the package, normally to ensure that the high-voltage part of the circuit inside is suitably isolated from the heatsink to which the package is attached. The outer surface of the package must also meet the requirements of creepage and clearance to ensure that the terminals are properly insulated from each other. The packaging also provides environmental protection for the modules to some degree. The simplest arrangements have a plastic housing filled with a potting compound, normally a silicone gel. The plastic case makes the module a robust component which can easily be handled during testing, installation, and operation while protecting the devices inside. The case and potting provide protection from dirt, contamination and foreign objects which could damage them or their interconnections. The package can provide reasonable protection from liquid water, but most packages do not provide thorough protection from water vapor. For special applications such as some aerospace systems, hermetically sealed packages are required to provide complete isolation from the environment.

A simplified diagram of a typical power electronics module is shown in **Figure 1** which has the main design elements outlined above. There is a broad range of shapes and sizes of power modules, but the structure of many of the most commercially successful ones can be described as having similar construction to this. The semiconductor devices are attached, normally using solder, to a ceramic tile metallized with copper on each side. The tile, or substrate, provides a thermal path to extract heat from the device and has a circuit outline etched into the top to provide.

conditions [2]. The entire substrate is then soldered to the base plate, providing a thermal path from the device to the outside world. In many packages, multiple substrate tiles are soldered into one module. Terminals also need to be connected to the contact pads on the substrate tile to allow current flow into and out of the package, and auxiliary signal pins are connected for the device gates and other connections needed to control the devices. The entire arrangement is then surrounded by a plastic case and potted with dielectric gel to provide some protection

**Figure 1.** A simplified diagram of conventional power module packaging structure. Key to structure is the insulating ceramic tile which is soldered to a base plate. The semiconductors are soldered to the topside of the tile along with the power and signal terminals. The topside interconnection to the devices is achieved with wire bonding. The structure is

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules

http://dx.doi.org/10.5772/intechopen.78765

67

Power module packages based on the principles shown in **Figure 1** have been successful for decades but are not capable of exploiting the benefits of WBG devices such as higher junction temperatures and faster switching speeds. Every part of the package needs to be reconsidered if it is to become a high-performance part suitable for housing WBG semiconductors: the backside die attach material must be able to operate reliably for years at junction temperatures over 200°C; the topside attachment must be suitable for high power density and high reliability. The ceramic substrate and the base plate must have excellent thermal conductivity to keep the devices as cool as possible. The current density of SiC devices is higher than Si which is an advantage for reducing the volume of components, but it also makes it more difficult to cool them. The encapsulating gel must be able to sustain high temperatures without degrading especially since they are normally in intimate contact with the devices themselves, and therefore will be subject to some of the highest temperatures in the package. Further from the

and electrical insulation (**Figure 2**).

then encapsulated in silicone gel and a plastic housing.

Isolation between contact pads for the various terminals of the device: anode and cathode in the case of a diode; emitter, gate and collector in the case of an IGBT; or gate, drain and source in the case of a MOSFET for example. Connections between these pads and the device are made using wirebonds, aluminum being a widely used metal in power electronics which is compatible with the aluminum surface of the device. With this combination of soldering and wirebonding, the device is connected to the package, and these connections are some of the most crucial for ensuring the long-term reliability of the entire package under real-world High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules http://dx.doi.org/10.5772/intechopen.78765 67

any other kind of device. This chapter focuses on power modules: a subsection of the field of semiconductor packaging. A power module normally contains several power electronics devices such as MOSFETs or IGBTs, diodes, and often the associated passive components like gate resistors and DC link capacitors. The package provides a mechanical interface with the rest of the system, since most semiconductor components produce heat that must be managed in order to keep the device below its maximum allowable junction temperate (Tjmax), the package is almost always mechanically connected to a heatsink. The packaging is also the primary thermal interface between the heat-generating devices and the heat sink. The operating temperature of the devices defines their performance and long-term reliability, if devices operate at higher temperatures their reliability will decrease exponentially as temperature increases [1]. As a result, the thermal interface provided by the packaging is crucially important, and many of the properties of the processes and materials are optimized to provide the best possible heat sink with the lowest achievable thermo-mechanical stress. Electrical interfaces between the devices and the system are also features of the package, with signal pins and power terminals being internally connected to the devices, and emerging through the packaging to allow external connections. Depending on the design, it is also common for electrical insulation to be a feature of the package, normally to ensure that the high-voltage part of the circuit inside is suitably isolated from the heatsink to which the package is attached. The outer surface of the package must also meet the requirements of creepage and clearance to ensure that the terminals are properly insulated from each other. The packaging also provides environmental protection for the modules to some degree. The simplest arrangements have a plastic housing filled with a potting compound, normally a silicone gel. The plastic case makes the module a robust component which can easily be handled during testing, installation, and operation while protecting the devices inside. The case and potting provide protection from dirt, contamination and foreign objects which could damage them or their interconnections. The package can provide reasonable protection from liquid water, but most packages do not provide thorough protection from water vapor. For special applications such as some aerospace systems, hermetically sealed packages are required to provide

66 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

A simplified diagram of a typical power electronics module is shown in **Figure 1** which has the main design elements outlined above. There is a broad range of shapes and sizes of power modules, but the structure of many of the most commercially successful ones can be described as having similar construction to this. The semiconductor devices are attached, normally using solder, to a ceramic tile metallized with copper on each side. The tile, or substrate, provides a thermal path to extract heat from the device and has a circuit outline etched into

Isolation between contact pads for the various terminals of the device: anode and cathode in the case of a diode; emitter, gate and collector in the case of an IGBT; or gate, drain and source in the case of a MOSFET for example. Connections between these pads and the device are made using wirebonds, aluminum being a widely used metal in power electronics which is compatible with the aluminum surface of the device. With this combination of soldering and wirebonding, the device is connected to the package, and these connections are some of the most crucial for ensuring the long-term reliability of the entire package under real-world

complete isolation from the environment.

the top to provide.

**Figure 1.** A simplified diagram of conventional power module packaging structure. Key to structure is the insulating ceramic tile which is soldered to a base plate. The semiconductors are soldered to the topside of the tile along with the power and signal terminals. The topside interconnection to the devices is achieved with wire bonding. The structure is then encapsulated in silicone gel and a plastic housing.

conditions [2]. The entire substrate is then soldered to the base plate, providing a thermal path from the device to the outside world. In many packages, multiple substrate tiles are soldered into one module. Terminals also need to be connected to the contact pads on the substrate tile to allow current flow into and out of the package, and auxiliary signal pins are connected for the device gates and other connections needed to control the devices. The entire arrangement is then surrounded by a plastic case and potted with dielectric gel to provide some protection and electrical insulation (**Figure 2**).

Power module packages based on the principles shown in **Figure 1** have been successful for decades but are not capable of exploiting the benefits of WBG devices such as higher junction temperatures and faster switching speeds. Every part of the package needs to be reconsidered if it is to become a high-performance part suitable for housing WBG semiconductors: the backside die attach material must be able to operate reliably for years at junction temperatures over 200°C; the topside attachment must be suitable for high power density and high reliability. The ceramic substrate and the base plate must have excellent thermal conductivity to keep the devices as cool as possible. The current density of SiC devices is higher than Si which is an advantage for reducing the volume of components, but it also makes it more difficult to cool them. The encapsulating gel must be able to sustain high temperatures without degrading especially since they are normally in intimate contact with the devices themselves, and therefore will be subject to some of the highest temperatures in the package. Further from the

manufacturers. Active metal brazing for bonding the metallization to the ceramic has shown to be more reliable to peeling off then direct copper bonding (DBC), and also aluminum

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules

to be an ideal substrate candidate material for WBG devices. Conventionally substrates have been formed of a single layer of ceramic with metallization on either side, but double layer ceramics are becoming more common for WBG applications: Two ceramic layers are bonded together with a metallization layer between them, with metallization on the top and bottom sides also, giving an overall sandwich structure of three layers of metal and two ceramic [5]. Typically, the top and middle metal layers are used for conducting current, and the bottom layer is used to connect to a heatsink. Electrical connections are made using through the ceramics, thus allowing a very low profile package with a large degree of overlap between conducting surfaces. This allows designers to create very low inductance and low thermal

The module baseplate in silicon power module has normally been made from Cu in lessexpensive modules and AlSiC in high-reliability modules. AlSiC is required for achieving the maximum benefit from AlN ceramic tiles, as the large CTE mismatch between AlN and Cu causes excessive stress, despite the high thermal conductivity of the system. High reliability baseplates are normally the largest single component of a module and the most expensive after the semiconductors. The trend in baseplate material is toward higher thermal conductivity, lower CTE, and higher mechanical strength. Base plates must also be finished to a high quality to give excellent bonding and interconnection with the other components. Enhanced cooling can be provided to the module by incorporating metal pin fins on the underside which can be used to directly liquid-cool the material, and these solutions have been widely used in automotive and traction applications to give low Zth from junction to case in the module [6]. Recently, MgSiC has emerged as a promising new baseplate material, which offers marginally higher thermal conductivity (up to around 210 W/mK compared with 170–180 for AlSiC) but

For high-power modules, thick copper bus bars are needed to handle high current loads without overheating. Solder interconnects have been very common as they are easily manufacturable and can be made in the same process as die attach soldering or substrate attach. As these other processes are becoming solder free, a new attach process for bus bars is beneficial, otherwise one soldering process will remain. Ultrasonic bonding is a mature process for bus-

The most widespread interconnection process for the backside of vertical power semiconductor devices is soldering, either using a solder paste which is mixture of flux and solder alloy; or using a solder preform which is a pre-fabricated foil of solder alloy, usually with the same surface area as the device to be soldered. The choice of alloy to be used for the die attach depends on several factors, such as whether or not the application has a requirement to be Pb free; the maximum processing temperature of other components in the module (such as passive SMT components); and cost. If there is no requirement to be Pb-free, this

which could be simpler to manufacture, and hence help to reduce cost [7].

bar attach, which is already widely used in power electronics modules [8].

N4

http://dx.doi.org/10.5772/intechopen.78765

is likely

69

direct bonding (DBA) has been shown to excellent reliability. For these reasons, Si<sup>3</sup>

impedance packages.

**2.1. Die attach**

**Figure 2.** An example of a three-phase power module with one SiC MOSFET per switch, negative temperature coefficient resistor for temperature sensing, and a DC link capacitor on each substrate. The package concept is similar to that shown in **Figure 1**. Image courtesy of Dynex Semiconductor Ltd.

junction, temperatures will be lower but the capabilities of materials still need to improve, including the plastic housings, and glue used to connect the housing to the baseplate.

These shortcomings in packaging technology have been recognized and described thoroughly for example in [3], and Section 2 presents a summary of some of the solutions that have been investigated.

#### **2. Materials and processes**

SiC has a higher thermal conductivity than Si which is one of the properties that makes it an excellent material for power electronics devices. To take advantage of this, all the other materials in the module must have compatible high performance. Alumina or Al<sup>2</sup> O3 is the most widely used ceramic used for insulating substrates in power modules primarily due to its low cost and large numbers of suppliers across the world. The properties of Al<sup>2</sup> O3 are not ideal, having a relatively large thermal impedance and high coefficient of thermal expansion. AlN is commonly used in modules where higher reliability and lower thermal impedance are more important requirements, in applications such as rail traction and renewable energy, where system failures can be costly in terms of maintenance and operational losses. AlN has a thermal conductivity around six times greater than Al<sup>2</sup> O3, and CTE around half as much, making it a much more efficient heat sink which is a better thermal match to the semiconductor devices and therefore reduces thermomechanical stress, which is the main cause of fatigue and wear-out failure in power electronics modules. Silicon nitride, Si<sup>3</sup> N4 , is being increasingly used because it has an even lower CTE than AlN and high mechanical strength [4]. The bond between the ceramic material and the metal layer of the substrate is a common wear-out failure mode caused by long time-constant (minutes and hours rather than seconds) temperature cycling of the module. Therefore, the reliability of the overall system is dependent on the reliability of the substrate material, and improving substrates is an intense area of R&D for the manufacturers. Active metal brazing for bonding the metallization to the ceramic has shown to be more reliable to peeling off then direct copper bonding (DBC), and also aluminum direct bonding (DBA) has been shown to excellent reliability. For these reasons, Si<sup>3</sup> N4 is likely to be an ideal substrate candidate material for WBG devices. Conventionally substrates have been formed of a single layer of ceramic with metallization on either side, but double layer ceramics are becoming more common for WBG applications: Two ceramic layers are bonded together with a metallization layer between them, with metallization on the top and bottom sides also, giving an overall sandwich structure of three layers of metal and two ceramic [5]. Typically, the top and middle metal layers are used for conducting current, and the bottom layer is used to connect to a heatsink. Electrical connections are made using through the ceramics, thus allowing a very low profile package with a large degree of overlap between conducting surfaces. This allows designers to create very low inductance and low thermal impedance packages.

The module baseplate in silicon power module has normally been made from Cu in lessexpensive modules and AlSiC in high-reliability modules. AlSiC is required for achieving the maximum benefit from AlN ceramic tiles, as the large CTE mismatch between AlN and Cu causes excessive stress, despite the high thermal conductivity of the system. High reliability baseplates are normally the largest single component of a module and the most expensive after the semiconductors. The trend in baseplate material is toward higher thermal conductivity, lower CTE, and higher mechanical strength. Base plates must also be finished to a high quality to give excellent bonding and interconnection with the other components. Enhanced cooling can be provided to the module by incorporating metal pin fins on the underside which can be used to directly liquid-cool the material, and these solutions have been widely used in automotive and traction applications to give low Zth from junction to case in the module [6]. Recently, MgSiC has emerged as a promising new baseplate material, which offers marginally higher thermal conductivity (up to around 210 W/mK compared with 170–180 for AlSiC) but which could be simpler to manufacture, and hence help to reduce cost [7].

For high-power modules, thick copper bus bars are needed to handle high current loads without overheating. Solder interconnects have been very common as they are easily manufacturable and can be made in the same process as die attach soldering or substrate attach. As these other processes are becoming solder free, a new attach process for bus bars is beneficial, otherwise one soldering process will remain. Ultrasonic bonding is a mature process for busbar attach, which is already widely used in power electronics modules [8].

#### **2.1. Die attach**

junction, temperatures will be lower but the capabilities of materials still need to improve,

**Figure 2.** An example of a three-phase power module with one SiC MOSFET per switch, negative temperature coefficient resistor for temperature sensing, and a DC link capacitor on each substrate. The package concept is similar to that shown

These shortcomings in packaging technology have been recognized and described thoroughly for example in [3], and Section 2 presents a summary of some of the solutions that have been

SiC has a higher thermal conductivity than Si which is one of the properties that makes it an excellent material for power electronics devices. To take advantage of this, all the other

most widely used ceramic used for insulating substrates in power modules primarily due to

ideal, having a relatively large thermal impedance and high coefficient of thermal expansion. AlN is commonly used in modules where higher reliability and lower thermal impedance are more important requirements, in applications such as rail traction and renewable energy, where system failures can be costly in terms of maintenance and operational losses. AlN has

making it a much more efficient heat sink which is a better thermal match to the semiconductor devices and therefore reduces thermomechanical stress, which is the main cause of fatigue

used because it has an even lower CTE than AlN and high mechanical strength [4]. The bond between the ceramic material and the metal layer of the substrate is a common wear-out failure mode caused by long time-constant (minutes and hours rather than seconds) temperature cycling of the module. Therefore, the reliability of the overall system is dependent on the reliability of the substrate material, and improving substrates is an intense area of R&D for the

O3 is the

are not

O3

, is being increasingly

O3, and CTE around half as much,

N4

materials in the module must have compatible high performance. Alumina or Al<sup>2</sup>

its low cost and large numbers of suppliers across the world. The properties of Al<sup>2</sup>

a thermal conductivity around six times greater than Al<sup>2</sup>

and wear-out failure in power electronics modules. Silicon nitride, Si<sup>3</sup>

including the plastic housings, and glue used to connect the housing to the baseplate.

investigated.

**2. Materials and processes**

in **Figure 1**. Image courtesy of Dynex Semiconductor Ltd.

68 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The most widespread interconnection process for the backside of vertical power semiconductor devices is soldering, either using a solder paste which is mixture of flux and solder alloy; or using a solder preform which is a pre-fabricated foil of solder alloy, usually with the same surface area as the device to be soldered. The choice of alloy to be used for the die attach depends on several factors, such as whether or not the application has a requirement to be Pb free; the maximum processing temperature of other components in the module (such as passive SMT components); and cost. If there is no requirement to be Pb-free, this allows a wide choice of relatively inexpensive Pb-based alloys with melting points up to 300°C, albeit alloys which are far from being eutectic and could have a pasty phase 10°C wide or more between solidus and liquidus. High-melting point lead-bearing alloys are common in high-power, high-reliability power modules in which maximum Tj of the current generation of Si devices is 150°C and while it is theoretically possible to operate Si devices of around 200 V blocking voltage up to 200°C [9], is unlikely to increase above 175°C in high-power modules with blocking voltages greater than 3.3 kV due to device-physics limitations. This gives a temperature range of more than 100°C between the absolute maximum junction temperature of the devices and the melting point of the solder. When considering the suitability of an interconnection material, a useful parameter to define is the homologous temperature, TH, where

consortium is known as the Die Attach 5 (DA5) [12]. The DA5 are focusing on four potential replacements to high-Pb solder: Ag sintering; high electrical and thermal conductivity adhesives; alternative solders; and transient liquid phase soldering (TLPS) [13]. Alternative solders with appropriate properties are available, such as Au80Sn20, AuGe, and AuSi, but the high gold content makes them too expensive to be viable for most applications. Even the best conductive adhesives have poor electrical and thermal properties compared with solder. Ag

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Sintering is the process of forming a solid mass of material from smaller particles or flakes using temperature, pressure, or both, while remaining below the melting point of the sinter material. It is widely used in manufacturing of metallic and ceramic parts. In the context of power-electronics packaging, we refer to sintering as the process of forming interconnection layers by processing a layer of micro or nanoparticles (normally of Ag) by applying a temperature and pressure profile for a controlled period of time. The resulting porous Ag layer has excellent electrical and thermal conductivity and a melting point equal to bulk silver at 961°C, normally with some remaining porosity. The silver particles (also known as the filler) in the paste are combined with a capping agent, binders and solvents. The purpose of these additional materials is to ensure that the silver particles do not begin to sinter themselves together before the actual processing begins, and to make the consistency of the past suitable for screen printing or dispensing. A range of chemicals have been used by the different suppliers of sinter pastes, a useful summary of these was published in 2014 [14]. Sinter pastes are broadly classified as being either 'pressured,' that is they require pressure to be applied during processing, or 'pressureless.' Sintering is an attractive technology for Pb-free and high temperature operations because the processing temperature are similar to those already used for device soldering, and pressureless paste in particular is seen as a potential drop-in solution which would require the minimum of additional manufacturing equipment; however, it is common for even pressureless pastes to benefit from some application of pressure during the manufacturing stage to increase the deformation of the Ag filler particles and increase the diffusion rate of silver atoms. An early patent (1973) for using sintering to join metal parts illustrated the use of the technique in lap, butt, and T-joints [15]. Sintered connections are not a new technology in semiconductor device packaging, with sintered glass beads being used for insulating materials, and sintering ceramic sheets being used as substrates ( [16] for example). Only more recently, sintering has been used as a means to connect electronic components themselves [17] and particular powersemiconductor devices [18]. In 2006, a sintered interconnection for semiconductor device interconnection was described [19] which had an electrical conductivity of around 2.6 × 10−5 (Ωcm)−1, thermal conductivity of around 2.4 W/Kcm and apparent elastic modulus of 9 GPa. The high thermal conductivity of a sintered joint can lead to a small reduction in the thermal impedance Zth from junction to case compared with a soldered die, particularly in small modules where there are not many devices which may overlap thermally with one another. One team of researchers [20] observed 12% lower thermal impedance compared to a SAC305

sintering or transient liquid phase bonding provides a more promising alternative.

**2.2. Silver sintering**

solder connection (**Figures 3** and **4**).

$$T\_H = \frac{T}{T\_M}$$

T (K) is the temperature of interest, which could be the mean operational temperature or the maximum junction temperature in this case, and TM (K) is the melting point of the material. In general, smaller homologous temperatures will give longer lifetimes in electronics packages either by operating as far as possible from the melting point of the solder, or by using a higher melting point solder; however, creep deformation can still occur at relatively low temperatures [10]. If TH is <0.4 this is considered mechanically stable, 0.4 < T<sup>M</sup> < 0.6 is considered to be the creep range, sensitive to strain, and T<sup>M</sup> > 0.6 is unable to bear engineering loads [9]. If we take 473 K (200°C) to be a useful operating temperature for SiC devices, the melting point of 1234 K (961°C) for pure silver gives a TH value of 0.38. In comparison, a Pb-rich solder with a melting point of 573 K (300°C) has a TH value of 0.82.

The wide band gap of SiC or GaN allows devices to have a maximum junction temperature of around 300°C, this rules out any solder with a melting point close that figure. Solders with even higher melting points could be too costly, so there has been a great deal of effort in packaging R&D to find an alternative interconnection technology for Si and WBG devices. At the same time that WBG power devices are becoming mature, along with the associated demands on power electronics packaging, there is also the external pressure of environmental policy to eliminate hazardous substances from manufacturing. As mentioned earlier, Pb and its use in solder have been specifically targeted in legislation worldwide as a material which could be eliminated from consumer and industrial products. The European End of Life Vehicle (ELV) Directive sets targets for the reuse, recycling, and recovery of ELVs and their components [11] and the European Reduction of Hazardous Substances (RoHS) Directive Restriction of the Use of Certain Hazardous Substances in Electronic and Electrical Equipment specifically restricts the use of Pb. As of 2018, alloys with a Pb content of more than 85% are exempt from the RoHS restrictions but are subject to periodic exemption review.

In 2010, a consortium of Bosch, Infineon Technologies, NXP, Freescale Semiconductor and STMicroelectronics formed with the aim of developing alternative processes for die attach in semiconductor packages to replace Pb solders, specifically high-melting point solders. The consortium is known as the Die Attach 5 (DA5) [12]. The DA5 are focusing on four potential replacements to high-Pb solder: Ag sintering; high electrical and thermal conductivity adhesives; alternative solders; and transient liquid phase soldering (TLPS) [13]. Alternative solders with appropriate properties are available, such as Au80Sn20, AuGe, and AuSi, but the high gold content makes them too expensive to be viable for most applications. Even the best conductive adhesives have poor electrical and thermal properties compared with solder. Ag sintering or transient liquid phase bonding provides a more promising alternative.

#### **2.2. Silver sintering**

allows a wide choice of relatively inexpensive Pb-based alloys with melting points up to 300°C, albeit alloys which are far from being eutectic and could have a pasty phase 10°C wide or more between solidus and liquidus. High-melting point lead-bearing alloys are

generation of Si devices is 150°C and while it is theoretically possible to operate Si devices of around 200 V blocking voltage up to 200°C [9], is unlikely to increase above 175°C in high-power modules with blocking voltages greater than 3.3 kV due to device-physics limitations. This gives a temperature range of more than 100°C between the absolute maximum junction temperature of the devices and the melting point of the solder. When considering the suitability of an interconnection material, a useful parameter to define is the homologous

*TM*

T (K) is the temperature of interest, which could be the mean operational temperature or the maximum junction temperature in this case, and TM (K) is the melting point of the material. In general, smaller homologous temperatures will give longer lifetimes in electronics packages either by operating as far as possible from the melting point of the solder, or by using a higher melting point solder; however, creep deformation can still occur at relatively low temperatures [10]. If TH is <0.4 this is considered mechanically stable, 0.4 < T<sup>M</sup> < 0.6 is considered to be the creep range, sensitive to strain, and T<sup>M</sup> > 0.6 is unable to bear engineering loads [9]. If we take 473 K (200°C) to be a useful operating temperature for SiC devices, the melting point of 1234 K (961°C) for pure silver gives a TH value of 0.38. In comparison, a Pb-rich solder with a

The wide band gap of SiC or GaN allows devices to have a maximum junction temperature of around 300°C, this rules out any solder with a melting point close that figure. Solders with even higher melting points could be too costly, so there has been a great deal of effort in packaging R&D to find an alternative interconnection technology for Si and WBG devices. At the same time that WBG power devices are becoming mature, along with the associated demands on power electronics packaging, there is also the external pressure of environmental policy to eliminate hazardous substances from manufacturing. As mentioned earlier, Pb and its use in solder have been specifically targeted in legislation worldwide as a material which could be eliminated from consumer and industrial products. The European End of Life Vehicle (ELV) Directive sets targets for the reuse, recycling, and recovery of ELVs and their components [11] and the European Reduction of Hazardous Substances (RoHS) Directive Restriction of the Use of Certain Hazardous Substances in Electronic and Electrical Equipment specifically restricts the use of Pb. As of 2018, alloys with a Pb content of more than 85% are exempt from the RoHS restrictions but are subject to periodic exemption

In 2010, a consortium of Bosch, Infineon Technologies, NXP, Freescale Semiconductor and STMicroelectronics formed with the aim of developing alternative processes for die attach in semiconductor packages to replace Pb solders, specifically high-melting point solders. The

of the current

common in high-power, high-reliability power modules in which maximum Tj

70 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

temperature, TH, where

review.

*TH* <sup>=</sup> \_\_\_*<sup>T</sup>*

melting point of 573 K (300°C) has a TH value of 0.82.

Sintering is the process of forming a solid mass of material from smaller particles or flakes using temperature, pressure, or both, while remaining below the melting point of the sinter material. It is widely used in manufacturing of metallic and ceramic parts. In the context of power-electronics packaging, we refer to sintering as the process of forming interconnection layers by processing a layer of micro or nanoparticles (normally of Ag) by applying a temperature and pressure profile for a controlled period of time. The resulting porous Ag layer has excellent electrical and thermal conductivity and a melting point equal to bulk silver at 961°C, normally with some remaining porosity. The silver particles (also known as the filler) in the paste are combined with a capping agent, binders and solvents. The purpose of these additional materials is to ensure that the silver particles do not begin to sinter themselves together before the actual processing begins, and to make the consistency of the past suitable for screen printing or dispensing. A range of chemicals have been used by the different suppliers of sinter pastes, a useful summary of these was published in 2014 [14]. Sinter pastes are broadly classified as being either 'pressured,' that is they require pressure to be applied during processing, or 'pressureless.' Sintering is an attractive technology for Pb-free and high temperature operations because the processing temperature are similar to those already used for device soldering, and pressureless paste in particular is seen as a potential drop-in solution which would require the minimum of additional manufacturing equipment; however, it is common for even pressureless pastes to benefit from some application of pressure during the manufacturing stage to increase the deformation of the Ag filler particles and increase the diffusion rate of silver atoms. An early patent (1973) for using sintering to join metal parts illustrated the use of the technique in lap, butt, and T-joints [15]. Sintered connections are not a new technology in semiconductor device packaging, with sintered glass beads being used for insulating materials, and sintering ceramic sheets being used as substrates ( [16] for example). Only more recently, sintering has been used as a means to connect electronic components themselves [17] and particular powersemiconductor devices [18]. In 2006, a sintered interconnection for semiconductor device interconnection was described [19] which had an electrical conductivity of around 2.6 × 10−5 (Ωcm)−1, thermal conductivity of around 2.4 W/Kcm and apparent elastic modulus of 9 GPa. The high thermal conductivity of a sintered joint can lead to a small reduction in the thermal impedance Zth from junction to case compared with a soldered die, particularly in small modules where there are not many devices which may overlap thermally with one another. One team of researchers [20] observed 12% lower thermal impedance compared to a SAC305 solder connection (**Figures 3** and **4**).

Sintering for die attach in power electronics modules has been an area of extensive research and development and a recent consideration of the maturity of the state of the art has been published in [14, 21]. Ag sintering processes are mature enough for some manufacturers to ship power modules with sintered interconnections, for example it has been used by Semikron to produce entirely solder-free modules [9] and has been used successfully in bipolar devices for joining large thyristors to molybdenum plates. The SKiN module went even further and replaced the wirebonds with a PCB which is sintered to the topside of the device [22]. Uncertainty around the potential for widespread use of Ag sintering for die attach centers on a relative lack of data on the long term reliability compared with soldered interfaces, although many laboratory studies of reliability have been carried out that invariably show a large increase in the number of cycles-to-failure, sometimes by a factor of 10 compared to solder.

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One reason silver sintering is more challenging to apply to mass production because of the difficulty in carrying out in-line high-volume automated quality control of sintered joints. In IGBT module production lines, there is 100% screening of the solder layers using X-ray imaging to find and measure the presence of voids in the solder caused by contamination, poor wetting or process irregularities. Modern industrial X-ray imaging systems are capable of automatically detecting and measuring the area of voids for statistical process control and comparison against defined pass/fail criteria. Imperfections in sintered bond lines do not appear as voids in the die attach layer, a good sintered joint and a failed sintered joint look identical to most X-ray systems with the exception of an advanced 3D tomography system, but such analysis would take too long per scan and therefore be too expensive to use as a screening technique in large-scale production. Poor bonding during the sintering process which leaves thin planar areas of no contact between the device and sinter layer, or the sinter layer and the substrate, might potentially be identifiable using scanning acoustic microscopy (SAM). The other alternative would be to forgo complete screening and instead carry out destructive tests on samples from each production batch using the mechanical strength measured in a die-shear test for example as a figure of merit. An alternative destructive method used during process development is a bend test in which the die and substrate and bent over a mandrel, of the substrate cracks and deforms before the device adhesion fails, the sintered joint is considered to be good. **Figure 5** shows the result of a bend test of 0.635 mm thick AlN active metal-brazed (AMB) tiles from the FIR3ST project power module. The tiles have been bent over a mandrel almost 90° which has caused the AlN ceramic and the SiC devices to

The long-term reliability of Ag-sintered interfaces under thermomechanical cycling conditions is not as well understood as for soldered interconnections, but is an area of ongoing research. Sintered interconnections are vulnerable to the same driving forces of failure as soldered ones because they form a sandwich of materials with different coefficients of thermal expansion and experience temperature cycling with both fast time constants (caused by losses when the devices are switched and conducting current) and slow time constants (caused by heat soak of the overall system and the specific mission profile of the application). This causes thermomechanical stress which leads to cracking and delamination of the layers. Even if the CTE of the materials is closely matched thermomechanical failure modes will take place because power semiconductor modules are, in general, rarely in thermal equilibrium, but always have some temperature gradient across the vertical structure of the module. Studies

fracture. The devices remain adhered to the surface.

**Figure 3.** Cross section of a sintered die attach layer captured using scanning electron microscopy. The bright central area shows where the porosity of the layer has been revealed using focused ion beam (FIB) milling. The edges of the image show the apparent porosity after polishing with diamond suspension fluid. Image courtesy of Dynex Semiconductor Ltd.

**Figure 4.** Scanning electron microscope (SEM) images of the sinter layer under a semiconductor die showing the variation in porosity from the edges to the middle. The measured porosity on the left, middle, and right-hand side is 22.6, 19.5 and 26.1%, respectively. Image courtesy of Dynex Semiconductor Ltd.

Sintering for die attach in power electronics modules has been an area of extensive research and development and a recent consideration of the maturity of the state of the art has been published in [14, 21]. Ag sintering processes are mature enough for some manufacturers to ship power modules with sintered interconnections, for example it has been used by Semikron to produce entirely solder-free modules [9] and has been used successfully in bipolar devices for joining large thyristors to molybdenum plates. The SKiN module went even further and replaced the wirebonds with a PCB which is sintered to the topside of the device [22]. Uncertainty around the potential for widespread use of Ag sintering for die attach centers on a relative lack of data on the long term reliability compared with soldered interfaces, although many laboratory studies of reliability have been carried out that invariably show a large increase in the number of cycles-to-failure, sometimes by a factor of 10 compared to solder.

One reason silver sintering is more challenging to apply to mass production because of the difficulty in carrying out in-line high-volume automated quality control of sintered joints. In IGBT module production lines, there is 100% screening of the solder layers using X-ray imaging to find and measure the presence of voids in the solder caused by contamination, poor wetting or process irregularities. Modern industrial X-ray imaging systems are capable of automatically detecting and measuring the area of voids for statistical process control and comparison against defined pass/fail criteria. Imperfections in sintered bond lines do not appear as voids in the die attach layer, a good sintered joint and a failed sintered joint look identical to most X-ray systems with the exception of an advanced 3D tomography system, but such analysis would take too long per scan and therefore be too expensive to use as a screening technique in large-scale production. Poor bonding during the sintering process which leaves thin planar areas of no contact between the device and sinter layer, or the sinter layer and the substrate, might potentially be identifiable using scanning acoustic microscopy (SAM). The other alternative would be to forgo complete screening and instead carry out destructive tests on samples from each production batch using the mechanical strength measured in a die-shear test for example as a figure of merit. An alternative destructive method used during process development is a bend test in which the die and substrate and bent over a mandrel, of the substrate cracks and deforms before the device adhesion fails, the sintered joint is considered to be good. **Figure 5** shows the result of a bend test of 0.635 mm thick AlN active metal-brazed (AMB) tiles from the FIR3ST project power module. The tiles have been bent over a mandrel almost 90° which has caused the AlN ceramic and the SiC devices to fracture. The devices remain adhered to the surface.

**Figure 3.** Cross section of a sintered die attach layer captured using scanning electron microscopy. The bright central area shows where the porosity of the layer has been revealed using focused ion beam (FIB) milling. The edges of the image show the apparent porosity after polishing with diamond suspension fluid. Image courtesy of Dynex Semiconductor

72 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**Figure 4.** Scanning electron microscope (SEM) images of the sinter layer under a semiconductor die showing the variation in porosity from the edges to the middle. The measured porosity on the left, middle, and right-hand side is

22.6, 19.5 and 26.1%, respectively. Image courtesy of Dynex Semiconductor Ltd.

Ltd.

The long-term reliability of Ag-sintered interfaces under thermomechanical cycling conditions is not as well understood as for soldered interconnections, but is an area of ongoing research. Sintered interconnections are vulnerable to the same driving forces of failure as soldered ones because they form a sandwich of materials with different coefficients of thermal expansion and experience temperature cycling with both fast time constants (caused by losses when the devices are switched and conducting current) and slow time constants (caused by heat soak of the overall system and the specific mission profile of the application). This causes thermomechanical stress which leads to cracking and delamination of the layers. Even if the CTE of the materials is closely matched thermomechanical failure modes will take place because power semiconductor modules are, in general, rarely in thermal equilibrium, but always have some temperature gradient across the vertical structure of the module. Studies

temperature cycling and active cycling conditions, between a factor of 4 and 10 increases in the number of cycles to failure. This large increase in reliability of one specific interface usually means that another interface in the system becomes the first failure mode instead of the die attach layer, or other solder layer. In many cases, the weak point is the ceramic tile, which starts to delaminate and will quickly cause a large rise in the thermal resistance between junc-

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One negative aspect of sinter layers for both die and substrate attach is that the thin, stiff layers offer less stress relaxation to the structure, and the mechanical stress is transferred to other layers in the module. **Figure 6** shows how from changing from soldering to sintering of substrates on a base plate the convex bow shape is completely reversed to become concave. The convex bow is necessary to ensure good thermal contact during operation as the module tends to flatten out due an effect similar to a bimetallic strip as it heats up, thus ensuring as large as possible contact area between base plate and heat sink. If the base plate has become concave, there will be a large area which is not contacted with the heat sink, so

In any fully formed solder joint, there is a layer of intermetallic compounds formed as the metallization of the workpieces is dissolved into the molten solder. Typically, these intermetallic

**solder**

**Table 1.** Showing a comparison of some important properties of solders and sinter materials used for die attach.

**Figure 6.** Three profiles of nominally identical baseplates before processing (left), after substrates have been soldered (middle) and after substrates have been attached by sintering (right). The sintering process causes the baseplate to switch

**Pb-free solder**

**Ag nanopowder**

tion and case once the delamination begins to impinge on the area under the devices.

thermal impedance will increase, and as a result, the junction temperature.

CTE (ppm/K) 28 20 19–21 Thermal Conductivity (W/mK) 70 70 (SnAg3.5) 240–290 Melting Point (°C) 183 220 ~961 Electrical Conductivity 14.5 8–12 41

**2.3. Diffusion soldering**

Data have been gathered from [9, 28, 29].

from a convex to a concave profile.

**Parameter Pb-Sb**

**Figure 5.** Sintered SiC MOSFETs on direct bonded copper (DBC) ceramic tiles after bend test. The substrate is bent through almost 90° and is cracked beneath the devices, which have remained adhered to the damaged surface. Image courtesy of Dynex Semiconductor Ltd.

have focused on how resilient sintered connections are compared with soldered interconnections under temperature cycling conditions, and on the nature of failure modes unique to sintered interfaces. Mechanical shear strength of nano-silver sintered die has been used as a measure of bond quality in 1.706 × 1.380 mm SiC SBDs [23]. It was found that the die shear strength was strongly related to the process time and temperature, with a 40 minute dwell at 300°C providing shear strength of around 40 MPa. These reduced by around 50% (the failure criteria defined in this study) after 5000 temperature cycles between 50 and 250°C. The reduction in shear strength was attributed to thermal-stress-induced dislocation creep leading to the formation of microcavities and grain boundaries.

The properties of sintered interfaces have been found to be a function of the porosity and porosity is a function of the starting material and the pressure used in the process [24]. Even small changes in the porosity can have a large impact, for example increasing the porosity from 5 to 7% (in other words from 95% dense to 93% dense) decreased the thermal conductivity from 380 to 320 W/mK at 100°C, accompanied by a similar relative change in electrical conductivity. On the other hand, the coefficient of thermal expansion was found to be relatively constant at temperatures less than 250°C and between porosity of 5 and 38% [25]. One study found that an established production process capable of sintering DBC master cards up to 5″ × 7″ in area has a porosity of 5%, but that reducing pressure by a factor of 4, the porosity increases to around 20%. **Figures 3** and **4** show SEM images of a 20 μm thick sinter layer showing the variation in porosity between the central area of the bond and the edges. Focused ion beam (FIB) milling is needed to reveal the true porosity under the polished surface.

A comparison of some properties between solder and silver sinter materials is shown in **Table 1**. Large area sintering has been investigated as a possible alternative to the use of solder for substrate to baseplate attachment [26]. A large ceramic tile (40 cm<sup>2</sup> ) was sintered to a baseplate and subjected to temperature cycling between −40 and +150°C. The integrity of the sample was measured using scanning acoustic microscopy and the test was stopped after 3000 cycles when it was found that the sinter layer showed no signs of degradation, but the substrate was beginning to delaminate. This is a common trend found in many papers on sintering: practically, all of the research papers report considerable increases in reliability under temperature cycling and active cycling conditions, between a factor of 4 and 10 increases in the number of cycles to failure. This large increase in reliability of one specific interface usually means that another interface in the system becomes the first failure mode instead of the die attach layer, or other solder layer. In many cases, the weak point is the ceramic tile, which starts to delaminate and will quickly cause a large rise in the thermal resistance between junction and case once the delamination begins to impinge on the area under the devices.

One negative aspect of sinter layers for both die and substrate attach is that the thin, stiff layers offer less stress relaxation to the structure, and the mechanical stress is transferred to other layers in the module. **Figure 6** shows how from changing from soldering to sintering of substrates on a base plate the convex bow shape is completely reversed to become concave. The convex bow is necessary to ensure good thermal contact during operation as the module tends to flatten out due an effect similar to a bimetallic strip as it heats up, thus ensuring as large as possible contact area between base plate and heat sink. If the base plate has become concave, there will be a large area which is not contacted with the heat sink, so thermal impedance will increase, and as a result, the junction temperature.

#### **2.3. Diffusion soldering**

have focused on how resilient sintered connections are compared with soldered interconnections under temperature cycling conditions, and on the nature of failure modes unique to sintered interfaces. Mechanical shear strength of nano-silver sintered die has been used as a measure of bond quality in 1.706 × 1.380 mm SiC SBDs [23]. It was found that the die shear strength was strongly related to the process time and temperature, with a 40 minute dwell at 300°C providing shear strength of around 40 MPa. These reduced by around 50% (the failure criteria defined in this study) after 5000 temperature cycles between 50 and 250°C. The reduction in shear strength was attributed to thermal-stress-induced dislocation creep leading to

**Figure 5.** Sintered SiC MOSFETs on direct bonded copper (DBC) ceramic tiles after bend test. The substrate is bent through almost 90° and is cracked beneath the devices, which have remained adhered to the damaged surface. Image

The properties of sintered interfaces have been found to be a function of the porosity and porosity is a function of the starting material and the pressure used in the process [24]. Even small changes in the porosity can have a large impact, for example increasing the porosity from 5 to 7% (in other words from 95% dense to 93% dense) decreased the thermal conductivity from 380 to 320 W/mK at 100°C, accompanied by a similar relative change in electrical conductivity. On the other hand, the coefficient of thermal expansion was found to be relatively constant at temperatures less than 250°C and between porosity of 5 and 38% [25]. One study found that an established production process capable of sintering DBC master cards up to 5″ × 7″ in area has a porosity of 5%, but that reducing pressure by a factor of 4, the porosity increases to around 20%. **Figures 3** and **4** show SEM images of a 20 μm thick sinter layer showing the variation in porosity between the central area of the bond and the edges. Focused ion beam (FIB) milling is needed to reveal the true porosity under the polished surface.

A comparison of some properties between solder and silver sinter materials is shown in **Table 1**. Large area sintering has been investigated as a possible alternative to the use of

a baseplate and subjected to temperature cycling between −40 and +150°C. The integrity of the sample was measured using scanning acoustic microscopy and the test was stopped after 3000 cycles when it was found that the sinter layer showed no signs of degradation, but the substrate was beginning to delaminate. This is a common trend found in many papers on sintering: practically, all of the research papers report considerable increases in reliability under

) was sintered to

solder for substrate to baseplate attachment [26]. A large ceramic tile (40 cm<sup>2</sup>

the formation of microcavities and grain boundaries.

74 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

courtesy of Dynex Semiconductor Ltd.

In any fully formed solder joint, there is a layer of intermetallic compounds formed as the metallization of the workpieces is dissolved into the molten solder. Typically, these intermetallic


**Table 1.** Showing a comparison of some important properties of solders and sinter materials used for die attach.

**Figure 6.** Three profiles of nominally identical baseplates before processing (left), after substrates have been soldered (middle) and after substrates have been attached by sintering (right). The sintering process causes the baseplate to switch from a convex to a concave profile.

layers are of irregular thickness of around several microns. Diffusion soldering promotes the growth of the intermetallics throughout the bulk of the solder joint, so that at the end of the process, the entire solder layer is formed of intermetallics. Sn rich solders and copper metallized substrates are a common combination which give Cu<sup>6</sup> Sn<sup>5</sup> and Cu<sup>3</sup> Sn intermetallics that have melting points of 416 and 676°C, respectively. A combination of Ag metallized die backside and Sn rich solder can give Ag<sup>3</sup> Sn (T<sup>m</sup> = 480°C). Studies have shown that diffusionsoldered interconnections can have a factor of 10 higher reliability than conventional solder joints, at least as good as sintered interconnections [27].

#### **2.4. New topside interconnections**

Aluminum wedge wirebonding remains the most widely used topside interconnection and has been an area of intense R&D to improve reliability. The most dramatic change is the use of copper wire instead of aluminum [30, 31]. The higher thermal and electrical conductivity of the wire allows increased current density for a given reliability or greater reliability at a given current density. The use of copper wire for die topside interconnection requires a special metallization on the topside of the chip, and some groups have experimented with the use of thick pads on the die topside to enhance the bondability of copper wire [32]. An alternative is the use of aluminum clad copper wire [33–35].

One study introduced the concept of spot sintering braided cable connections to the topside of devices [36]. A power cycling comparison was made between soldered, wirebonded diodes; and sintered diodes with spot sintered braid topside interconnection. A load current of 90A was used with a constant on time and off time of 1 and 5 s respectively. This test method gave a ΔTj of between 86 and 100 K. The average number of cycles to failure of the soldered/ wirebonded interconnection was 50 k cycles, for the sintered die, it was around 300 k cycles.

*V* = *L* \_\_*di*

bipolar Si diode [37].

*dt*

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77

MPECT collaboration [38] achieved low stray induc-

where V is the overshoot voltage, L is the inductance, and di/dt is the rate of change of current. Clearly any inductance in the circuit combined with the high di/dt values associated with WBG devices will cause large voltage overshoots which could destroy the devices if the overall voltage exceeds the breakdown voltage of the device. Stray inductance can easily be minimized in principal by making the current carrying components planar, reducing depth, and overlapping terminals with opposite polarity as much as possible. In practice, however, this is more challenging to achieve: the presence of wire bonds for interconnection make it difficult to achieve really low parasitic inductance, say <5 nH per phase leg, and achieving low

**Figure 7.** Turn-on waveforms for a 3.3 kV Si IGBT with Si fast recovery diode (top), and the same IGBT but with SiC SBD (bottom). The first turn off of the unipolar SiC diode causes oscillation of the output current compared with the slower

tance by adopting a wirebond free design, instead sintering a flexible PCB directly to the topside of the devices and using a low profile design with ultrasonically bonded bus bars for

profile planar modules requires totally different module design concepts.

**3.1. Examples of advanced packaging concept implementation**

The power module developed by the I<sup>2</sup>

#### **3. Special design considerations for wide band gap power modules**

Advantages of using unipolar wide-band gap devices in power electronics applications also have downsides. High switching speeds when switching inductive loads will cause large voltage overshoots which may exceed the breakdown capability of the device. The ringing of the voltage and current in the circuit caused by fast switching can have implications for EMC and interference at a system level. **Figure 7** shows examples of waveforms from 3.3 kV rated devices.

Packaging design has an important role to play in mitigating these unwanted side effects. Any electronic component always has some unwanted electrical characteristics and these are normally referred to as 'stray' or 'parasitic' properties. Stray capacitance, inductance, and resistance can all have negative effects in power electronics modules, and the fast switching speeds of WBG devices make it crucial to not only minimize these stray properties, but even to engineer them to specific values in order to optimize performance. Stray inductance causes voltage overshoots during periods of changing electrical current according to the relationship

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules http://dx.doi.org/10.5772/intechopen.78765 77

layers are of irregular thickness of around several microns. Diffusion soldering promotes the growth of the intermetallics throughout the bulk of the solder joint, so that at the end of the process, the entire solder layer is formed of intermetallics. Sn rich solders and copper

that have melting points of 416 and 676°C, respectively. A combination of Ag metallized die

soldered interconnections can have a factor of 10 higher reliability than conventional solder

Aluminum wedge wirebonding remains the most widely used topside interconnection and has been an area of intense R&D to improve reliability. The most dramatic change is the use of copper wire instead of aluminum [30, 31]. The higher thermal and electrical conductivity of the wire allows increased current density for a given reliability or greater reliability at a given current density. The use of copper wire for die topside interconnection requires a special metallization on the topside of the chip, and some groups have experimented with the use of thick pads on the die topside to enhance the bondability of copper wire [32]. An alternative is

One study introduced the concept of spot sintering braided cable connections to the topside of devices [36]. A power cycling comparison was made between soldered, wirebonded diodes; and sintered diodes with spot sintered braid topside interconnection. A load current of 90A was used with a constant on time and off time of 1 and 5 s respectively. This test method

wirebonded interconnection was 50 k cycles, for the sintered die, it was around 300 k cycles.

Advantages of using unipolar wide-band gap devices in power electronics applications also have downsides. High switching speeds when switching inductive loads will cause large voltage overshoots which may exceed the breakdown capability of the device. The ringing of the voltage and current in the circuit caused by fast switching can have implications for EMC and interference at a system level. **Figure 7** shows examples of waveforms from 3.3 kV rated

Packaging design has an important role to play in mitigating these unwanted side effects. Any electronic component always has some unwanted electrical characteristics and these are normally referred to as 'stray' or 'parasitic' properties. Stray capacitance, inductance, and resistance can all have negative effects in power electronics modules, and the fast switching speeds of WBG devices make it crucial to not only minimize these stray properties, but even to engineer them to specific values in order to optimize performance. Stray inductance causes voltage overshoots during periods of changing electrical current according to the relationship

**3. Special design considerations for wide band gap power modules**

of between 86 and 100 K. The average number of cycles to failure of the soldered/

Sn<sup>5</sup>

Sn (T<sup>m</sup> = 480°C). Studies have shown that diffusion-

and Cu<sup>3</sup>

Sn intermetallics

metallized substrates are a common combination which give Cu<sup>6</sup>

76 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

joints, at least as good as sintered interconnections [27].

backside and Sn rich solder can give Ag<sup>3</sup>

the use of aluminum clad copper wire [33–35].

**2.4. New topside interconnections**

gave a ΔTj

devices.

**Figure 7.** Turn-on waveforms for a 3.3 kV Si IGBT with Si fast recovery diode (top), and the same IGBT but with SiC SBD (bottom). The first turn off of the unipolar SiC diode causes oscillation of the output current compared with the slower bipolar Si diode [37].

$$V = L\frac{di}{dt}$$

where V is the overshoot voltage, L is the inductance, and di/dt is the rate of change of current. Clearly any inductance in the circuit combined with the high di/dt values associated with WBG devices will cause large voltage overshoots which could destroy the devices if the overall voltage exceeds the breakdown voltage of the device. Stray inductance can easily be minimized in principal by making the current carrying components planar, reducing depth, and overlapping terminals with opposite polarity as much as possible. In practice, however, this is more challenging to achieve: the presence of wire bonds for interconnection make it difficult to achieve really low parasitic inductance, say <5 nH per phase leg, and achieving low profile planar modules requires totally different module design concepts.

#### **3.1. Examples of advanced packaging concept implementation**

The power module developed by the I<sup>2</sup> MPECT collaboration [38] achieved low stray inductance by adopting a wirebond free design, instead sintering a flexible PCB directly to the topside of the devices and using a low profile design with ultrasonically bonded bus bars for a solder free final package. Ag plated Si3N4 substrates are used and a pressure-assisted sintering processing connects SiC MOSFETs to the substrates, and the substrates are also sintered to the baseplate. The module is shown in **Figure 8**.

A 3.3 kV full SiC power module for rail traction applications has been reported [39] and further use of a full SiC 3.3 kV module rated at 450 A has been described in [40] and a similar package type has been used with 3rd generation SiC MOSFETs to give a module with 3.3 kV voltage rating and RDS (on) of 5 mΩ at 25°C and 13.8 mΩ at 175°C [41]. This package is becoming widely available from all the principal power module manufacturers, and while it uses relatively conventional packaging technology, for example, it still relies on extensive wire bonding for the topside connections to the devices, it focuses on using a new design approach to reduce the parasitic inductance. In rail traction applications, power modules normally consist of a single switch circuit topology combined together in the inverter to form phase legs. This newer style of package adopts a phase leg topology in a single package, which allows the bus bars to be designed in a way which allows a high degree of overlap between the DC+ and DC− bus bars, thus reducing the inductance while maintaining a module that can be manufactured on existing production lines.

In [42], a packaging concept is presented featuring a modular full SiC design. In each switching element, 1200 V 80 mΩ SiC MOSFETs with solderable top and bottom sides are joined source-to-source with solder and copper bumps in a flipchip type arrangement. This allows a planar, low inductance, double-side cooled switch to be manufactured with a reported inductance [43] of around 12 nH at 10 kHz. VON of the MOSFETs was monitored during temperature cycling from −55°C to +150°C with 30 min soak at each temperature extreme and 15 min transition time. No sign of degradation was apparent after 500 cycles. Thermal simulation and FLIR camera measurement showed that with 100 W dissipated in each MOSFET, junction temperature could be kept below 80°C [44]. The main elements of this design are shown in **Figure 9**.

die attachment in a wirebond free arrangement which gave an overall thermal resistance in the range 0.11 to 0.14 K/W. This design allowed the low power-loop inductance of 4.4 nH to be achieved, while a direct impingement liquid cooled heat sink allows power densities up

**Figure 9.** Overview of the module design concept described in [42]. A CAD drawing of the substrate element is shown in (a) revealing the source-to-source soldered MOSFET chips and Cu bumps used for interconnection. (b) Shows the overall sandwich structure allowing double side cooling, (c) and (d) show the real implementation of the building blocks and interconnecting elements. (image credit to Dr. Alberto Castellazzi, Univeristy of Nottingham, and Mr. Philippe Lasserre,

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79

Market forces and technology trends push semiconductor power modules requirements to higher power density, higher operating temperature, higher efficiency, lower cost and higher reliability. Wide band gap power semiconductor devices and Si devices are placing new demands on packaging technology in order to realize the potential of the latest generation of devices to meet these requirements. Silicon devices still have a much larger market share across all applications in which the ever increasing demands outlined above are already providing challenges. As a result, it is often Si power modules that lead the way with the most advanced packaging technology because of the high demand for these devices and competitive market for high reliability products. Sintering, copper wire bonding, wirebond free, planar modules with low inductance have all been introduced with Si devices. It is almost counter intuitive that the first generations of SiC power devices have been brought to market using less advanced packaging technology, often simply being used as drop in replacements for Si devices in conventional packaging, so the full capability of the devices cannot be

to 18.1 W/mm3.

deep concept, France).

**4. Conclusions**

In [45], a novel 10 kV, 60 A all SiC power module prototype was manufactured using third Generation Wolfspeed 350 mΩ SiC MOSFETs. Pressure-assisted sintering was used for the

**Figure 8.** I2MPECT SiC power module. On the left, the complete package with lid. The right-hand side shows package internal solder-free structure, with ultrasonically bonded bus bars, double side sintering, and flexible PCB for topside die attach. Image courtesy of Dynex Semiconductor Ltd.

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules http://dx.doi.org/10.5772/intechopen.78765 79

**Figure 9.** Overview of the module design concept described in [42]. A CAD drawing of the substrate element is shown in (a) revealing the source-to-source soldered MOSFET chips and Cu bumps used for interconnection. (b) Shows the overall sandwich structure allowing double side cooling, (c) and (d) show the real implementation of the building blocks and interconnecting elements. (image credit to Dr. Alberto Castellazzi, Univeristy of Nottingham, and Mr. Philippe Lasserre, deep concept, France).

die attachment in a wirebond free arrangement which gave an overall thermal resistance in the range 0.11 to 0.14 K/W. This design allowed the low power-loop inductance of 4.4 nH to be achieved, while a direct impingement liquid cooled heat sink allows power densities up to 18.1 W/mm3.

#### **4. Conclusions**

a solder free final package. Ag plated Si3N4 substrates are used and a pressure-assisted sintering processing connects SiC MOSFETs to the substrates, and the substrates are also sintered to

A 3.3 kV full SiC power module for rail traction applications has been reported [39] and further use of a full SiC 3.3 kV module rated at 450 A has been described in [40] and a similar package type has been used with 3rd generation SiC MOSFETs to give a module with 3.3 kV voltage rating and RDS (on) of 5 mΩ at 25°C and 13.8 mΩ at 175°C [41]. This package is becoming widely available from all the principal power module manufacturers, and while it uses relatively conventional packaging technology, for example, it still relies on extensive wire bonding for the topside connections to the devices, it focuses on using a new design approach to reduce the parasitic inductance. In rail traction applications, power modules normally consist of a single switch circuit topology combined together in the inverter to form phase legs. This newer style of package adopts a phase leg topology in a single package, which allows the bus bars to be designed in a way which allows a high degree of overlap between the DC+ and DC− bus bars, thus reducing the inductance while maintaining a module that can be

In [42], a packaging concept is presented featuring a modular full SiC design. In each switching element, 1200 V 80 mΩ SiC MOSFETs with solderable top and bottom sides are joined source-to-source with solder and copper bumps in a flipchip type arrangement. This allows a planar, low inductance, double-side cooled switch to be manufactured with a reported inductance [43] of around 12 nH at 10 kHz. VON of the MOSFETs was monitored during temperature cycling from −55°C to +150°C with 30 min soak at each temperature extreme and 15 min transition time. No sign of degradation was apparent after 500 cycles. Thermal simulation and FLIR camera measurement showed that with 100 W dissipated in each MOSFET, junction temperature could be kept below 80°C [44]. The main elements of this design are shown in

In [45], a novel 10 kV, 60 A all SiC power module prototype was manufactured using third Generation Wolfspeed 350 mΩ SiC MOSFETs. Pressure-assisted sintering was used for the

**Figure 8.** I2MPECT SiC power module. On the left, the complete package with lid. The right-hand side shows package internal solder-free structure, with ultrasonically bonded bus bars, double side sintering, and flexible PCB for topside

the baseplate. The module is shown in **Figure 8**.

78 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

manufactured on existing production lines.

die attach. Image courtesy of Dynex Semiconductor Ltd.

**Figure 9**.

Market forces and technology trends push semiconductor power modules requirements to higher power density, higher operating temperature, higher efficiency, lower cost and higher reliability. Wide band gap power semiconductor devices and Si devices are placing new demands on packaging technology in order to realize the potential of the latest generation of devices to meet these requirements. Silicon devices still have a much larger market share across all applications in which the ever increasing demands outlined above are already providing challenges. As a result, it is often Si power modules that lead the way with the most advanced packaging technology because of the high demand for these devices and competitive market for high reliability products. Sintering, copper wire bonding, wirebond free, planar modules with low inductance have all been introduced with Si devices. It is almost counter intuitive that the first generations of SiC power devices have been brought to market using less advanced packaging technology, often simply being used as drop in replacements for Si devices in conventional packaging, so the full capability of the devices cannot be utilized. However, it seems certain that the time is near when the combination of advanced packaging and the latest generation of WBG devices is realized in mass production of power electronics modules.

[6] Stockmeier T, Bayerer R, Herr E, Sinerius D, Thiemann U. Reliable 1200 amp 2500 V IGBT modules for traction applications. IEE Colloquium on IGBT Propulsion Drives;

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules

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81

[7] Iwayama I, Kuwabara T, Nakai Y, Ikeda T, Koyama S, Okamoto M. New heat sink for

[8] Nishimura Y, Kido K, Momose F, Goto T. Development of ultrasonic welding for IGBT modules structure. In: Proceedings of the 22nd International Symposium on Power

[9] Göbl C, Faltenbacher J. Low temperature sinter technology die attachment for power

[10] Zhang Y, Zhu H, Fujiwara M, Xu J, Dao M. Low-temperature creep of SnPb and SnAgCu solder alloys and reliability prediction in electronic packaging modules. Scipta

[11] Directive 2000/53/EC of the European Parliament and of the Council of 18 September

[12] Electronics Sourcing Online [Internet]. 2010. Available from: http://www.electronicssourcing.com/2010/04/21/da5-consortium-to-develop-high-lead-solder-alternatives/

[13] Die Attach 5 Project, Customer Presentation. Infineon Technologies [Internet]. 2018. Available from: https://www.infineon.com/dgdl/DA5\_customer\_presentation\_1612016.

[14] Siow Kim S. Are sintered silver joints ready for use as interconnect material in microelectronic packaging. Journal of Electronic Materials. 2014;**43**:947-961. DOI: 10.1007/s11664-

[15] Bergstrom Theodore R, Takkunen Philip D. Metal Parts Joined with Sintered Powdered

[16] Takashi M. Semiconductor Device Provided with a Package for a Semiconductor Element Having a Plurality of Electrodes to Be Applied with Substantially Same Voltage (Patent);

[17] Herbert S. Method for Mounting Electronic Components on a Substrate (Patent); 22

[18] Palm G, Tadros Y, Thoben M. Power module with improved transient thermal imped-

[19] Bai JG, Zhang ZZ, Calata JN, Lu GQ. Low-temperature sintered nanoscale silver as a novel semiconductor device-metallized substrate interconnect material. IEEE Transactions on

pdf?fileId=5546d461545309420154708923da0064 [Accessed: May 01, 2018]

Metal. US3716347A United States; September 21, 1973. US Grant

railroad vehicle power modules. SEI Technical Review. April 2014;**78**:63-67

Semiconductor Devices & ICs (ISPSD); 6-10 June 2010; Hiroshima

electronic applications; CIPS; 16-18 March 2010; Nuremberg

25th April 1995; DOI: 10.1049/ic:19950530

Materialia. 2013;**68**:607-610

[Accessed: April 01, 2018]

09 July 1982. US4608592A

April 1986; Germnay. EP0242626A3

ance (Patent); 13 December 2000. US6812559B2

Components and Packaging Technologies. 2006;**29**:589-593

013-2967-3

2000 on end-of-life vehicles; 2000. 2000/53/EC

#### **Acknowledgements**

The authors wish to thank their colleagues at Dynex semiconductor and CRRC for their cooperation in proof reading the manuscript, to Dr. Yimin Zhao for her technical expertise on aspects of silver sintering, and to Anne Harris for her assistance regarding the FiRS3T and I2MPECT projects.

### **Author details**

Paul Mumby-Croft<sup>1</sup> \*, Daohui Li<sup>1</sup> , Xiaoping Dai<sup>2</sup> and Guoyou Liu<sup>2</sup>

\*Address all correspondence to: paul\_mumby-croft@dynexsemi.com

1 Dynex Semiconductor Ltd., Lincoln, United Kingdom

2 State Key Laboratory of Advanced Power Semiconductor Devices, CRRC Times Electric Co., Ltd., China

#### **References**


[6] Stockmeier T, Bayerer R, Herr E, Sinerius D, Thiemann U. Reliable 1200 amp 2500 V IGBT modules for traction applications. IEE Colloquium on IGBT Propulsion Drives; 25th April 1995; DOI: 10.1049/ic:19950530

utilized. However, it seems certain that the time is near when the combination of advanced packaging and the latest generation of WBG devices is realized in mass production of power

The authors wish to thank their colleagues at Dynex semiconductor and CRRC for their cooperation in proof reading the manuscript, to Dr. Yimin Zhao for her technical expertise on aspects of silver sintering, and to Anne Harris for her assistance regarding the FiRS3T and

[1] Pecht M. The Influence of Temperature on Microelectronic Device Failure Mechanisms,

[2] Schutze T, Berg H, Hierholzer: Further improvements in the reliability of IGBT modules. Industry Applications Conference, 1998. 33rd IAS Annual Meeting; 12-15 October 1998,

[3] Tolbert LM, King TJ, et al. Power Electronics for Distributed Energy Systems and Transmission and Distribution Applications. Southwest Washington, DC: US Department

[4] Miyazaki H, Zhou Y, Iwakiri S, Hirotsuru H, Hirao K, Fukuda S, Izu N, Hyuga H. Development of thermal fatigue-tolerant active metal brazing substrates using highlythermal conductive silicon nitrides with high toughness. PCIM; 16-18 May 2017.

[5] Copper Bonded Silicon Nitride Packages for Power Modules. Kyocera [Internet]. Available from: https://global.kyocera.com/prdct/semicon/semi/power/amb.html

RAMSEARCH Co, Crofton, MD (USA), 1993 Final rep. US Army Phase II

of Energy, Oak Ridge National Laboratory; 2005. ORNL/TM-2005/230

and Guoyou Liu<sup>2</sup>

, Xiaoping Dai<sup>2</sup>

\*Address all correspondence to: paul\_mumby-croft@dynexsemi.com

80 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

2 State Key Laboratory of Advanced Power Semiconductor Devices,

electronics modules.

I2MPECT projects.

**Author details**

Paul Mumby-Croft<sup>1</sup>

**References**

St. Louis, MO

Nuremberg

[Accessed: March 23, 2018]

\*, Daohui Li<sup>1</sup>

1 Dynex Semiconductor Ltd., Lincoln, United Kingdom

CRRC Times Electric Co., Ltd., China

**Acknowledgements**


[20] Cao X, Wang T, Ngo KDT, Lu G-Q. Characterization of lead-free solder and sintered nanosilver die-attach layers using thermal impedance. IEEE Transactions on Components, Packaging and Manufacturing Technology. April 2011;**1**(4):546-552

[33] Schmidt R, Scheuemann U, Milke E. Al-Clad Cu Wire Bonds Multiply Power Cycling

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules

http://dx.doi.org/10.5772/intechopen.78765

[34] Naumann F, März B, Schischka J, Petzold M. Microstructural study of the fatigue mechanism of aluminum cladded copper wires. In: 8th International Conference on Integrated

[35] Schmidt R, König C, Prenosil P. Novel wire bond material for advanced power module

[36] Eisele R, Migdalek D, Rabsch T, Rudzki J. Reliable chip contact joining. In: Proceedings

[37] Sharma YK, Jiang H, Zheng C, Dai X, Deviny I. Effect of design variations and N<sup>2</sup>

[38] Integrated, Intelligent module power electronic converter [Internet]. Available from: https://ec.europa.eu/inea/en/horizon-2020/projects/h2020-transport/aviation/i2mpect

[39] Negishi T et al. 3.3 kV All SiC Power Module for Traction System Use. Europe: PCIM;

[40] Ishigaki T et al. 3.3 kV/450 A Full-SiC nHPD2 (Next High Power Density Dual) With

[41] Hayes J, Curbow A, Sparkman B, Martin D, Olejniczak K, Wijenayake A, McNutt T. Dynamic Characterisation of Next Generation Medium Voltage (3.3 kV & 10 kV)

[42] Aliyu AM, Castellazzi A, Lasserrre P, Delmonte N, Cova P. Full SiC integrated power converter module with replaceable building blocks. In: 10th International Conference on

[43] Aliyu AM, Castellazzi A, Lasserre P, Delmonte N. Modular integrated SiC MOSFET matrix converter, In: 2017 IEEE 3rd International Future Energy Electronics Conference

[44] Cova P, Aliyu AM, Castellazzi A, Chiozzi D, Delmonte N, Lasserre P, Pignoloni N. Thermal design and characterization of a modular integrated liquid cooled 1200 V-35 A SiC

[45] Johnson M, DiMarino C, Mouawad B, Li J, Skuriat R, Wang M, Tan Y, Lu G.Q., Boroyevich D, Burgos R. 10 kV SiC power module packaging. In: 10th International Conference on

MOSFET bi-directional switch. Microelectronics Reliability. 2017;**76-77**:277-281

and ECCE Asia (IFEEC 2017–ECCE Asia); 3-7 June 2017, Kaohsiung, Taiwan

Related Materials (ISCRM); 17-22 September; 2017. Washington DC

annealing on 1.7kV 4H-SiC Diodes. In: International Conference on Silicon Carbide and

O

83

Lifetime of Advanced Power Module. Europe: PCIM; 2012

Power Electronics Systems. February 25-27, 2014. CIPS. 2014

packages. Microelectronics Reliability. 2012;**52**:2283-2288

PCIM Europe 2009 Conference. ISBN: 978-3-8007-3158-9

Smooth Switching. Vol. 2017. Europe: PCIM; 2017

Silicon Carbide Power Modules. Europe: PCIM; 2017

Integrated Power Electronics Systems; 2018. Stuttgart, Germany

Integrated Power Electronics Systems; 2018. Stuttgart, Germany

[Accessed:April 01, 2018]

2017


[33] Schmidt R, Scheuemann U, Milke E. Al-Clad Cu Wire Bonds Multiply Power Cycling Lifetime of Advanced Power Module. Europe: PCIM; 2012

[20] Cao X, Wang T, Ngo KDT, Lu G-Q. Characterization of lead-free solder and sintered nanosilver die-attach layers using thermal impedance. IEEE Transactions on Components,

[21] Lu G-Q. Advanced die-attach by metal-powder sintering: The science and the practice. In: 10th International Conference on Integrated Power Electronics Systems; 2018

[22] Stockmeier T, Beckedahl P, Goble C, Malzer T. SKiN: Double side sintering technology for new packages. In: 23rd International Symposium on Power Semiconductor Devices

[23] Guofeng Bai J, Lu G-Q. Thermomechancial reliability of low-temperature sintered silver die attached. IEEE Transactions on Device and Materials Reliability. 2006;**6**:436-441 [24] Knoerr M, Schletz A. Power semiconductor joining through sintering of silver nanoparticles: Evaluation of influence of parameters time, temperature and pressure on density, strength and reliability. In: 6th International Conference on Integrated Power Electronics

[25] Wereszczak, Andrew A, Vuono, Daniel J, Wang Hsin, Ferber, Mattison K, Liang, Zhenxian. Properties of Bulk Sintered Silver as a Function of Porosity. United States: N.

[26] Licht T, Speckels R, Thoben M. Sintering technology used for interconnection of large areas: Potential and limitation for power modules. In: 6th International Conference on

[27] Guth K, Heuck N, Stalhut C, Ciliox A, Oeschler N, Bower L, Tophinke S, Bolokski D, Speckels R, Kersting C, Krasel S, Strotman G. End-of-Life Investigation on the .XT

[28] Siewert T, Liu S, Smith D, Madeni JC. Properties of Lead-Free Solders. Gaithersburg: National Institute of Standards and Technology and Colorado School of Mines; February 11, 2002 [29] Scheuermann U. Increasing component reliability by eliminating solder interfaces. In: 13th European Conference on Power Electronics and Applications (EPE); 8-10 September

[30] Siepe D, Bayerer R, Roth R. The future of wirebonding is wirebonding. In: 7th International Conference on Integrated Power Electronics Systems (CIPS), 6-8 March 2012;

[31] Ling J, Xu T, Luechinger C. Large cu wire wedge bonding process for power devices. In: Electronics Packaging Technology Conference (EPTC); 2011 IEEE 13th. DOI: 10.1109/

[32] Haumann S, Rudzki J, Osterwald F, Becker M, Eisele R. Novel Bonding and Joining Technology for Power Electronics. In: Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 17-21 March 2013. Long Beach, CA, USA: IEEE;

Integrated Power Electronics Systems. CIPS 2010. March 16-18, 2010

Interconnect Technology. Europe: PCIM; 19-21 May 2015

Packaging and Manufacturing Technology. April 2011;**1**(4):546-552

82 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

& IC's; 2011. pp. 324-327

Systems. CIPS 2010. March 16-18, 2010

p.; 2012. Web. DOI: 10.2172/1041433

Nuremberg, Germany: CIPS; 2012

DOI: 10.1109/APEC.2013.6520275

2009. Barcelona

EPTC.2011.6184375


**Chapter 5**

**Provisional chapter**

**Status of SiC Products and Technology**

**Status of SiC Products and Technology**

DOI: 10.5772/intechopen.76061

The benefits of silicon carbide (SiC) devices for use in power electronics are driven by fundamental material benefits of high breakdown field and thermal conductivity, and over 25 years of sustained development in materials and devices has brought adoption to a tipping point. It takes the confluence of many separate developments to drive large-

Silicon carbide (SiC) has about a 10× higher critical field for breakdown and a 3.5× higher thermal conductivity than silicon (Si). The former characteristic allows unipolar devices to be built with 1/100 on-resistance of silicon devices for the same voltage rating, while the latter allows efficient removal of heat generated during power conversion. The system benefits of SiC for power electronic applications have been amply demonstrated, but the growth of SiC adoption especially for transistors to replace Si IGBTs and Si MOSFETs has, until 2017, been relatively slow [1–3]. Projections in the last 5–10 years showing a "hockey-stick" ramp in SiC shipments have not occurred. It has taken time for the material, technology, and products to mature, reliability concerns to be addressed, prices to drop sufficiently, and the driver and applications ecosystem to develop. Finally, with the migration to 6-inch wafers, SiC adoption is poised for rapid acceleration. We examine each of the major contributing factors,

**Keywords:** silicon carbide, SiC, SiC substrates, SiC epitaxy, SiC applications, SiC packaging, SiC Schottky diode, SiC cascode, SiC MOSFET, supercascode, SiC reliability,

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

scale adoption, which we will examine in this chapter.

http://dx.doi.org/10.5772/intechopen.76061

Anup Bhalla

Anup Bhalla

**Abstract**

SiC gate oxide

**1. Introduction**

#### **Status of SiC Products and Technology Status of SiC Products and Technology**

#### Anup Bhalla Anup Bhalla

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76061

**Abstract**

The benefits of silicon carbide (SiC) devices for use in power electronics are driven by fundamental material benefits of high breakdown field and thermal conductivity, and over 25 years of sustained development in materials and devices has brought adoption to a tipping point. It takes the confluence of many separate developments to drive largescale adoption, which we will examine in this chapter.

DOI: 10.5772/intechopen.76061

**Keywords:** silicon carbide, SiC, SiC substrates, SiC epitaxy, SiC applications, SiC packaging, SiC Schottky diode, SiC cascode, SiC MOSFET, supercascode, SiC reliability, SiC gate oxide

#### **1. Introduction**

Silicon carbide (SiC) has about a 10× higher critical field for breakdown and a 3.5× higher thermal conductivity than silicon (Si). The former characteristic allows unipolar devices to be built with 1/100 on-resistance of silicon devices for the same voltage rating, while the latter allows efficient removal of heat generated during power conversion. The system benefits of SiC for power electronic applications have been amply demonstrated, but the growth of SiC adoption especially for transistors to replace Si IGBTs and Si MOSFETs has, until 2017, been relatively slow [1–3]. Projections in the last 5–10 years showing a "hockey-stick" ramp in SiC shipments have not occurred. It has taken time for the material, technology, and products to mature, reliability concerns to be addressed, prices to drop sufficiently, and the driver and applications ecosystem to develop. Finally, with the migration to 6-inch wafers, SiC adoption is poised for rapid acceleration. We examine each of the major contributing factors,

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

highlighting the enormous progress across all fronts, as well as the work remaining to be done at this exciting time for SiC power electronics.

#### **2. SiC market projections and driving applications**

**Figure 1** shows the projected SiC growth by the application area. The traditional markets in power supplies for SiC Schottky diodes and (photovoltaic) PV inverters are rapidly being supplemented by growth in (electric vehicle) EV on-board chargers and charging stations, and 2018 is expected to see growth of SiC transistors in power supplies, previously the domain of silicon super-junction (SJ) MOSFETs. Strong growth is also happening in the UPS systems driven by higher efficiency and in high-performance motor-drive segments. Moreover, strong market pull from automotive inverter companies developing SiC solutions, ramping 2020–2024, is expected to rapidly tip SiC device revenues past the \$1 b revenue threshold. Given the favorable policies of governments in Asia and Europe toward EVs (**Figure 2**), the demand currently seen for SiC devices for chargers is expected to grow quickly as market penetration increases from the meager 1–2% to 10–15% in the next decade. Traditional applications will then open up to SiC as prices fall, driven by the growing economies of scale and increasing competition in the supply of SiC substrates, epitaxial material, and products. This will be tracked by the introduction of an ecosystem of high-performance passives, drivers, and sensors that simplify the extraction of the system benefits of this wide bandgap technology. It is expected that SiC will reach about 10% of the Si market by 2025. Over a longer time frame, 3300V–10KV class of products will get deployed in applications such as railway traction, MW motor drives for wind, ship, and industrial use, high-voltage DC power conversion, solid-state breakers, etc.

**3. SiC material and epitaxy progress**

**Figure 2.** Expected growth of EV Sales.

mity ±8%, doping ±15%, and BPDs <0.1/cm2

advancement in post-epitaxial wafer defect density.

ers compete.

**Figure 3** captures the rapid improvement in the density of micropipe defects in SiC 6-inch substrates. While 6-inch substrates dominate the cost of SiC products presently, the rapid capacity expansion by key suppliers in the USA, coupled with robust volume growth, is expected to bring cost parity with 4-inch mature SiC substrates by mid-2018. Beyond 2018, 6-in. SiC will drive cost reductions across all product types. Improvements in wafer shape, boule yields, and reduced defects are key to eventual device yields and lower costs. As with silicon technology, many quality improvements are possible only when the scale of the business allows large-scale manufacturing that brings clarity to underlying issues and drives equipment improvements and investments as manufactur-

There has also been considerable progress in 6-in. epitaxy [4], along with the introduction of improved single-wafer tools and better metrology for defects. Post-epitaxy thickness unifor-

state-of-the-art 6-in. product yield on 200A, 650 V JBS diodes, a testament to the starting epi material quality married to Si foundry manufacturing discipline. **Figure 5** shows the rapid

Also significant is the introduction of the foundry model in SiC. Until SiC volumes grow to exceed 10–30 K wafers/month, the economics of a dedicated factory for wafer cost are not favorable, since the entire cost of running the fab must be amortized over a small

are available up to 1700 V. **Figure 4** shows the

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 87

**Figure 1.** SiC device market projection. Source: Yole developpement 2016.

**Figure 2.** Expected growth of EV Sales.

highlighting the enormous progress across all fronts, as well as the work remaining to be

**Figure 1** shows the projected SiC growth by the application area. The traditional markets in power supplies for SiC Schottky diodes and (photovoltaic) PV inverters are rapidly being supplemented by growth in (electric vehicle) EV on-board chargers and charging stations, and 2018 is expected to see growth of SiC transistors in power supplies, previously the domain of silicon super-junction (SJ) MOSFETs. Strong growth is also happening in the UPS systems driven by higher efficiency and in high-performance motor-drive segments. Moreover, strong market pull from automotive inverter companies developing SiC solutions, ramping 2020–2024, is expected to rapidly tip SiC device revenues past the \$1 b revenue threshold. Given the favorable policies of governments in Asia and Europe toward EVs (**Figure 2**), the demand currently seen for SiC devices for chargers is expected to grow quickly as market penetration increases from the meager 1–2% to 10–15% in the next decade. Traditional applications will then open up to SiC as prices fall, driven by the growing economies of scale and increasing competition in the supply of SiC substrates, epitaxial material, and products. This will be tracked by the introduction of an ecosystem of high-performance passives, drivers, and sensors that simplify the extraction of the system benefits of this wide bandgap technology. It is expected that SiC will reach about 10% of the Si market by 2025. Over a longer time frame, 3300V–10KV class of products will get deployed in applications such as railway traction, MW motor drives for wind, ship, and industrial use, high-voltage DC power conversion,

done at this exciting time for SiC power electronics.

solid-state breakers, etc.

**2. SiC market projections and driving applications**

86 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**Figure 1.** SiC device market projection. Source: Yole developpement 2016.

#### **3. SiC material and epitaxy progress**

**Figure 3** captures the rapid improvement in the density of micropipe defects in SiC 6-inch substrates. While 6-inch substrates dominate the cost of SiC products presently, the rapid capacity expansion by key suppliers in the USA, coupled with robust volume growth, is expected to bring cost parity with 4-inch mature SiC substrates by mid-2018. Beyond 2018, 6-in. SiC will drive cost reductions across all product types. Improvements in wafer shape, boule yields, and reduced defects are key to eventual device yields and lower costs. As with silicon technology, many quality improvements are possible only when the scale of the business allows large-scale manufacturing that brings clarity to underlying issues and drives equipment improvements and investments as manufacturers compete.

There has also been considerable progress in 6-in. epitaxy [4], along with the introduction of improved single-wafer tools and better metrology for defects. Post-epitaxy thickness uniformity ±8%, doping ±15%, and BPDs <0.1/cm2 are available up to 1700 V. **Figure 4** shows the state-of-the-art 6-in. product yield on 200A, 650 V JBS diodes, a testament to the starting epi material quality married to Si foundry manufacturing discipline. **Figure 5** shows the rapid advancement in post-epitaxial wafer defect density.

Also significant is the introduction of the foundry model in SiC. Until SiC volumes grow to exceed 10–30 K wafers/month, the economics of a dedicated factory for wafer cost are not favorable, since the entire cost of running the fab must be amortized over a small

**Figure 3.** Improvement in SiC substrate quality over time. Courtesy: II-VI corporation.

**4. Device technology**

Progress on device technology and products has been considerable in the last few years. The improvement in RdsA, reliability, chip current ratings, and improved knowledge on how to use the devices in new designs is now bearing fruit. Up to 100A, 1200 V, and 200A, 650 V single chip JBS diodes are now available, bringing SiC diode ratings to silicon soft-recovery diode levels. The improvements in Eon losses by 2× at 150°C through the use of these diodes lead to large loss reduction for hybrid SiC modules even at modest switching frequencies.

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 89

**Figure 5.** Rapid improvements in epitaxial layer defects. Courtesy: Showa Denko Corporation.

In the SiC transistor space, the main device structures in use are shown in **Figure 6**. Trench MOSFET offerings from Rohm and Infineon [5] compete with advanced planar technologies from Wolfspeed, Panasonic [6], Mitsubishi, ST, and GE. Evolution of trench technology is expected to continue the RdsA improvement of SiC MOSFETs, since mobility is improved along the a- and m-faces. Cascode technology from USCi based on trench JFETs provides the lowest RdsA technology SiC switch, configured as a normally-off MOSFET by cascode connection to a custom Si device, designed to present an IGBT/Si MOSFET interface to all users (**Figure 7**).

The use of advanced wafer thinning to reduce substrate resistance together with the dense trench JFET cell technology for SiC [7] has resulted in the introduction of 650 V cascode devices

**Figure 4.** Yield on 6-inch 200A, 650 V JBS diodes. Courtesy: USCi 2017.

volume. Most large silicon manufacturers entering SiC try to leverage their silicon mass production lines. The transition to 6-in. makes this process easier, and an initial investment of \$2–30 m is sufficient, since the majority of process steps can share equipment with silicon. The foundry model brings a high level of manufacturing expertise, low process cost from sharing the line with silicon, and the ability to aggregate SiC volume to further drive down prices.

**Figure 5.** Rapid improvements in epitaxial layer defects. Courtesy: Showa Denko Corporation.

#### **4. Device technology**

volume. Most large silicon manufacturers entering SiC try to leverage their silicon mass production lines. The transition to 6-in. makes this process easier, and an initial investment of \$2–30 m is sufficient, since the majority of process steps can share equipment with silicon. The foundry model brings a high level of manufacturing expertise, low process cost from sharing the line with silicon, and the ability to aggregate SiC volume to further

**Figure 4.** Yield on 6-inch 200A, 650 V JBS diodes. Courtesy: USCi 2017.

**Figure 3.** Improvement in SiC substrate quality over time. Courtesy: II-VI corporation.

88 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

drive down prices.

Progress on device technology and products has been considerable in the last few years. The improvement in RdsA, reliability, chip current ratings, and improved knowledge on how to use the devices in new designs is now bearing fruit. Up to 100A, 1200 V, and 200A, 650 V single chip JBS diodes are now available, bringing SiC diode ratings to silicon soft-recovery diode levels. The improvements in Eon losses by 2× at 150°C through the use of these diodes lead to large loss reduction for hybrid SiC modules even at modest switching frequencies.

In the SiC transistor space, the main device structures in use are shown in **Figure 6**. Trench MOSFET offerings from Rohm and Infineon [5] compete with advanced planar technologies from Wolfspeed, Panasonic [6], Mitsubishi, ST, and GE. Evolution of trench technology is expected to continue the RdsA improvement of SiC MOSFETs, since mobility is improved along the a- and m-faces. Cascode technology from USCi based on trench JFETs provides the lowest RdsA technology SiC switch, configured as a normally-off MOSFET by cascode connection to a custom Si device, designed to present an IGBT/Si MOSFET interface to all users (**Figure 7**).

The use of advanced wafer thinning to reduce substrate resistance together with the dense trench JFET cell technology for SiC [7] has resulted in the introduction of 650 V cascode devices

**Figure 6.** SiC transistor types aavilable in the 650–1200 V class 2016–2017.

10 kV-rated modules is longer, and the supercascode structure [9] is a very promising alternative, with large benefits in switching speed, diode recovery, and drive simplification as

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 91

**Table 1.** Comparative performance of advanced 650 V devices in 2016–2017.

Much has been reported in the last 3–4 years on the rapid improvements in the understanding of the MOS interface in SiC [10]. This has led to much reduced Vth shift in commercial products from leading manufacturers. In addition, the trench MOSFET structure allows the use of thicker gate oxides for better reliability margins, given the better mobility observed on the a- and m-faces of SiC. Progress has been made ensuring the reliability of SiC transistors and diodes to combined moisture and field-dependent degradations by the introduction of devices that can withstand 1000htrs of H3TRB stress at 80% of the rated VDS(MAX). A working group under JEDEC JC-70 is formalizing improved standards for SiC MOSFET testing and qualification, based on the deeper understanding of failure modes and interface physics. In addition, great strides have been made in understanding and mitigating BPD-dependent degradation mechanisms [11]. Most gate oxide issues are not a matter of concern in the cascode structure, since the SiC JFET device has no gate oxide and can therefore operate at higher bulk E-fields without degradation. Furthermore, the Si MOS used in the cascode has a high Vth and a thicker gate oxide, which leads to greater margin between operating and maximum ratings. SiC MOSFETs and cascodes offer excellent avalanche ratings. SiC devices are also able to withstand repetitive avalanche events, and studies on cascodes have shown that 1E6 cycles at the rated datasheet EAS condition result in no-device degradation, since current flow is in the bulk SiC.

**Figure 8** shows a UJC1206K cascode device tested for short-circuit withstand time at starting Tj = 25 and 200°C at Vds = 850 V. The datasheet conditions for SCWT are met for all operating gate voltages and even with Tj = 200°C since the SiC JFET limits the short-circuit current

attractive cost points.

**5. Reliability**

**Figure 7.** Comparison of transistor technology in the 650 V class 2016–2017.

from USCi that can complete very favorably with incumbent Si superjunction, GaN HEMT, and SiC MOS devices. **Table 1** shows the RdsA of commercially available 650 V devices, with SiC Cascodes providing >10× RdsA improvement over silicon devices, with obvious benefits in cost and lower capacitances. A key improvement with WBG devices is the improved bodydiode with very low recovery losses that in turn allows the use of circuits such as totem-pole PFC to push efficiency to new heights. Thermal management for the smaller SiC chips is driving packaging technology enhancements, both in discrete devices and in power modules.

Development of 3300 V MOSFETs at 4 in. and 6 in. [8] indicates that commercial introduction from multiple suppliers may be expected in the next 1–2 years. The horizon for 6.5 kV- and

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 91


**Table 1.** Comparative performance of advanced 650 V devices in 2016–2017.

10 kV-rated modules is longer, and the supercascode structure [9] is a very promising alternative, with large benefits in switching speed, diode recovery, and drive simplification as attractive cost points.

#### **5. Reliability**

from USCi that can complete very favorably with incumbent Si superjunction, GaN HEMT, and SiC MOS devices. **Table 1** shows the RdsA of commercially available 650 V devices, with SiC Cascodes providing >10× RdsA improvement over silicon devices, with obvious benefits in cost and lower capacitances. A key improvement with WBG devices is the improved bodydiode with very low recovery losses that in turn allows the use of circuits such as totem-pole PFC to push efficiency to new heights. Thermal management for the smaller SiC chips is driving packaging technology enhancements, both in discrete devices and in power modules. Development of 3300 V MOSFETs at 4 in. and 6 in. [8] indicates that commercial introduction from multiple suppliers may be expected in the next 1–2 years. The horizon for 6.5 kV- and

**Figure 6.** SiC transistor types aavilable in the 650–1200 V class 2016–2017.

90 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**Figure 7.** Comparison of transistor technology in the 650 V class 2016–2017.

Much has been reported in the last 3–4 years on the rapid improvements in the understanding of the MOS interface in SiC [10]. This has led to much reduced Vth shift in commercial products from leading manufacturers. In addition, the trench MOSFET structure allows the use of thicker gate oxides for better reliability margins, given the better mobility observed on the a- and m-faces of SiC. Progress has been made ensuring the reliability of SiC transistors and diodes to combined moisture and field-dependent degradations by the introduction of devices that can withstand 1000htrs of H3TRB stress at 80% of the rated VDS(MAX). A working group under JEDEC JC-70 is formalizing improved standards for SiC MOSFET testing and qualification, based on the deeper understanding of failure modes and interface physics. In addition, great strides have been made in understanding and mitigating BPD-dependent degradation mechanisms [11]. Most gate oxide issues are not a matter of concern in the cascode structure, since the SiC JFET device has no gate oxide and can therefore operate at higher bulk E-fields without degradation. Furthermore, the Si MOS used in the cascode has a high Vth and a thicker gate oxide, which leads to greater margin between operating and maximum ratings.

SiC MOSFETs and cascodes offer excellent avalanche ratings. SiC devices are also able to withstand repetitive avalanche events, and studies on cascodes have shown that 1E6 cycles at the rated datasheet EAS condition result in no-device degradation, since current flow is in the bulk SiC.

**Figure 8** shows a UJC1206K cascode device tested for short-circuit withstand time at starting Tj = 25 and 200°C at Vds = 850 V. The datasheet conditions for SCWT are met for all operating gate voltages and even with Tj = 200°C since the SiC JFET limits the short-circuit current

short-circuit withstand times in the cascode is favorable compared to SiC MOSFETs, since the reduction in peak current by tuning JFET Vth does not drastically increase RdsA. **Figure 9** shows that a short-circuit withstand time of 10 μs can be achieved with minimal change in JFET RdsA. Recent studies of SiC devices have shown better immunity to terrestrial neutron radiation, which is a key problem for high-voltage IGBTs. Much work remains to be done, however, to improve the immunity of heavy ions that affect device operations in space. NASA has led the research into ultra-high temperature operation (500°C-long duration) of SiC JFET devices and ICs, in understanding the degradation mechanisms. At this time, these applications are niche

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 93

The last few years have also marked the rapid proliferation of gate drive solutions suitable for use for SiC power MOSFETs, with the extended voltage range and strong sink currents. Non-isolated drivers for use with signal isolators, or isolated drivers from multiple vendors, are available, with common mode transient immunity of 100–200 V/ns. However, many more options exist for the better developed ecosystem of Si MOSFET and IGBT drives, which can be used with SiC cascode devices, easing the transition to the use of WBG switches. **Figure 10** shows an important benefit of SiC cascode devices, which cannot only be dropped into Si IGBT/MOSFET circuits but also offer a larger margin between operating and maximum gate

**Figure 11** shows a schematic for the gate drive interfaced with a half-bridge connection of two SiC transistors. When the upper device is turned on, the voltage rises across the lower device once its body diode recovers. This fast dV/dt can induce a voltage spike at the gate, due to the Igd displacement current (proportional to Cgd.dV/dt), turning-on the lower device, creating a brief shoot-through condition where both transistors are on. This can be avoided by having a low Cgd/Ciss ratio, low internal Rg in the transistor, and a gate driver with a strong current sink or a Miller clamp. Similarly, if the gate driver power supply or the signal barrier allows capacitive coupling between the input and output, injected displacement currents during high dV/dt operations can cause misoperation of the signal processing electronics. Advanced solutions are now available to handle these issues from many analog IC companies (see **Table 2**).

**Figure 10.** Operating and maximum gate voltages for Si IGBT, SiC cascode, and SiC MOSFET switches.

but hold the potential to unlock entirely new businesses for SiC.

voltages, as is prevalent for incumbent silicon devices.

**6. SiC gate drive**

**Figure 8.** UJC1206K cascode device is capable of handling repetitive short circuits even with starting Tj=200°C. SiC devices will offer robustness exceeding Si IGBTs.

**Figure 9.** Short circuit time-RdsA trade-off for 1200V Stack cascode with Vbus = 850V. Courtesy USCi 2017.

within the cascode. A study of the 650/1200 V USCi cascodes undergoing 100 repetitions at the rated short-circuit conditions shows no degradation in any device characteristics, whereas SiC MOSFETs typical undergo Vth shifts after such exposure [12]. The trade-off in RdsA to get long short-circuit withstand times in the cascode is favorable compared to SiC MOSFETs, since the reduction in peak current by tuning JFET Vth does not drastically increase RdsA. **Figure 9** shows that a short-circuit withstand time of 10 μs can be achieved with minimal change in JFET RdsA.

Recent studies of SiC devices have shown better immunity to terrestrial neutron radiation, which is a key problem for high-voltage IGBTs. Much work remains to be done, however, to improve the immunity of heavy ions that affect device operations in space. NASA has led the research into ultra-high temperature operation (500°C-long duration) of SiC JFET devices and ICs, in understanding the degradation mechanisms. At this time, these applications are niche but hold the potential to unlock entirely new businesses for SiC.

#### **6. SiC gate drive**

within the cascode. A study of the 650/1200 V USCi cascodes undergoing 100 repetitions at the rated short-circuit conditions shows no degradation in any device characteristics, whereas SiC MOSFETs typical undergo Vth shifts after such exposure [12]. The trade-off in RdsA to get long

**Figure 8.** UJC1206K cascode device is capable of handling repetitive short circuits even with starting Tj=200°C. SiC

92 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

devices will offer robustness exceeding Si IGBTs.

**Figure 9.** Short circuit time-RdsA trade-off for 1200V Stack cascode with Vbus = 850V. Courtesy USCi 2017.

The last few years have also marked the rapid proliferation of gate drive solutions suitable for use for SiC power MOSFETs, with the extended voltage range and strong sink currents. Non-isolated drivers for use with signal isolators, or isolated drivers from multiple vendors, are available, with common mode transient immunity of 100–200 V/ns. However, many more options exist for the better developed ecosystem of Si MOSFET and IGBT drives, which can be used with SiC cascode devices, easing the transition to the use of WBG switches. **Figure 10** shows an important benefit of SiC cascode devices, which cannot only be dropped into Si IGBT/MOSFET circuits but also offer a larger margin between operating and maximum gate voltages, as is prevalent for incumbent silicon devices.

**Figure 11** shows a schematic for the gate drive interfaced with a half-bridge connection of two SiC transistors. When the upper device is turned on, the voltage rises across the lower device once its body diode recovers. This fast dV/dt can induce a voltage spike at the gate, due to the Igd displacement current (proportional to Cgd.dV/dt), turning-on the lower device, creating a brief shoot-through condition where both transistors are on. This can be avoided by having a low Cgd/Ciss ratio, low internal Rg in the transistor, and a gate driver with a strong current sink or a Miller clamp. Similarly, if the gate driver power supply or the signal barrier allows capacitive coupling between the input and output, injected displacement currents during high dV/dt operations can cause misoperation of the signal processing electronics. Advanced solutions are now available to handle these issues from many analog IC companies (see **Table 2**).

**Figure 10.** Operating and maximum gate voltages for Si IGBT, SiC cascode, and SiC MOSFET switches.

package offerings has been expanded to include the TO247-4L and D2PAK-7L, where the source Kelvin connection allows faster di/dt switching without excessive gate ringing. With the entry of 650 V SiC switches, in the near future, we can expect additional Si packages like the DFN8x8, TOLL, DPAK-3L, and D2PAK-3L to follow. As frequencies rise further, requiring switching at >200 V/ns, use of co-packaged half-bridge elements, as well as co-packaged

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 95

Module packaging based on IPM technology is already offered by Mitsubishi, Fuji, and others. Automotive grade IPMs with built-in gate drives minimize losses for higher frequency switching and can serve the 8–25 kW space quite well for power supplies and on-board char-

The potential for hybrid modules has been thoroughly examined, but the expanding offerings of full SiC modules will likely see more growth. While few modules offer Tjmax >175°C today, considerable improvements have been made in inductance, to allow fast switching. **Figure 12**

**Figure 12.** A wide-array of discrete surface mount and thorugh hole packages have become available for discrete SiC

**Figure 13.** A 400, 1200V half-bridge module with 1.4nH power loop inductance presented by Semikron. Packaging of this

type can allow the full use of the high frequency switching benefits of SiC at high power levels.

devices. For high-speed switching, packages that provide a separate source Kelvin connection are beneficial.

drivers is planned to replace standard discretes.

gers, albeit at a cost premium.

**Figure 11.** The key challenges of high dV/dt switching is to have gate drivers with strong current sink capability, dV/dt immunity and an isolation barrier with high common mode rejection.



**Table 2.** A selection of gate drivers for SiC devices and key characteristics.

#### **7. Packaging for SiC**

It has been clear since the early days of SiC transistor technology that the high temperature and fast switching capability of SiC switches could not be exploited without the use of low-inductance packaging. However, the initial introduction of discrete devices has used traditional silicon through-hole packages like TO247-3L. Very recently, the range of discrete package offerings has been expanded to include the TO247-4L and D2PAK-7L, where the source Kelvin connection allows faster di/dt switching without excessive gate ringing. With the entry of 650 V SiC switches, in the near future, we can expect additional Si packages like the DFN8x8, TOLL, DPAK-3L, and D2PAK-3L to follow. As frequencies rise further, requiring switching at >200 V/ns, use of co-packaged half-bridge elements, as well as co-packaged drivers is planned to replace standard discretes.

Module packaging based on IPM technology is already offered by Mitsubishi, Fuji, and others. Automotive grade IPMs with built-in gate drives minimize losses for higher frequency switching and can serve the 8–25 kW space quite well for power supplies and on-board chargers, albeit at a cost premium.

The potential for hybrid modules has been thoroughly examined, but the expanding offerings of full SiC modules will likely see more growth. While few modules offer Tjmax >175°C today, considerable improvements have been made in inductance, to allow fast switching. **Figure 12**

**Figure 12.** A wide-array of discrete surface mount and thorugh hole packages have become available for discrete SiC devices. For high-speed switching, packages that provide a separate source Kelvin connection are beneficial.

**7. Packaging for SiC**

It has been clear since the early days of SiC transistor technology that the high temperature and fast switching capability of SiC switches could not be exploited without the use of low-inductance packaging. However, the initial introduction of discrete devices has used traditional silicon through-hole packages like TO247-3L. Very recently, the range of discrete

**Figure 11.** The key challenges of high dV/dt switching is to have gate drivers with strong current sink capability, dV/dt

immunity and an isolation barrier with high common mode rejection.

94 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**Table 2.** A selection of gate drivers for SiC devices and key characteristics.

**Figure 13.** A 400, 1200V half-bridge module with 1.4nH power loop inductance presented by Semikron. Packaging of this type can allow the full use of the high frequency switching benefits of SiC at high power levels.

shows a recent Semikron development that cuts loop inductance to just 1.4 nH in a 400 A, 1200 V half-bridge [13], allowing very fast switching without excessive voltage overshoots and good current sharing. These packaging innovations are key to unlocking the system-level benefits of SiC (**Figures 13** and **14**).

**8. Application drivers**

A roadmap of applications for SiC devices was compiled by the PowerAmerica Institute and described in terms of voltage class and whether they are near, medium, or long term, as shown in **Figure 15**. It can be seen that the near-term applications fall in the 650–1700 V range.

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 97

The benefits of SiC Schottky diodes in reducing CCM mode EON losses in PFC circuits that led to the widespread use of these devices in the last decade continue today. However, the drive to

**Figure 15.** Applications roadmap for SiC devices by voltage rating. Courtesy: PowerAmerica.

**Figure 16.** >99% Efficiency on Totem pole Demonstration board with UJC06505K.

In the automotive space, considerable effort has been expended on double-sided cooling. This technology is already used for Si IGBTs by many car manufacturers and is being actively developed for SiC as well [14]. While the CTE difference between Si and SiC is small, the much higher Young's modulus of SiC leads to higher stresses, requiring careful mechanical package development, especially for double sided cooling extended to 175–200°C temperature ratings.

## **8. Application drivers**

shows a recent Semikron development that cuts loop inductance to just 1.4 nH in a 400 A, 1200 V half-bridge [13], allowing very fast switching without excessive voltage overshoots and good current sharing. These packaging innovations are key to unlocking the system-level

96 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

In the automotive space, considerable effort has been expended on double-sided cooling. This technology is already used for Si IGBTs by many car manufacturers and is being actively developed for SiC as well [14]. While the CTE difference between Si and SiC is small, the much higher Young's modulus of SiC leads to higher stresses, requiring careful mechanical package development, especially for double sided cooling extended to 175–200°C temperature ratings.

**Figure 14.** Double-sided cooling technologies developed for silicon IGBTs will be rapidly adapted to SiC MOSFETs.

benefits of SiC (**Figures 13** and **14**).

A roadmap of applications for SiC devices was compiled by the PowerAmerica Institute and described in terms of voltage class and whether they are near, medium, or long term, as shown in **Figure 15**. It can be seen that the near-term applications fall in the 650–1700 V range.

The benefits of SiC Schottky diodes in reducing CCM mode EON losses in PFC circuits that led to the widespread use of these devices in the last decade continue today. However, the drive to

**Figure 15.** Applications roadmap for SiC devices by voltage rating. Courtesy: PowerAmerica.

**Figure 16.** >99% Efficiency on Totem pole Demonstration board with UJC06505K.

**Figure 17.** Excellent Qrr for UJC06505K enables hard switching. Low Qrr body diode behavior is a key benefit of SiC MOSFETs and GaN devices over silicon superjunction devices.

eliminate bridge losses [15] has led to the development of the Totem-pole PFC topology. To use this bridgeless circuit in CCM mode, the device required must feature very low-diode recovery losses in addition to basic fast switching capability. **Figure 16** shows the efficiency achieved in a Totem-Pole PFC, and **Figure 17** shows the excellent body diode recovery behavior that makes this possible. For this reason, 650 V SiC devices are likely to compete with GaN devices at >1.5 kW level of server/telecom supplies that require >99% PFC stage efficiency at high frequencies. This lack of diode recovery charge also makes the SiC-based switches useful in avoiding recoveryinduced failures in PSFB and LLC applications when ZVS conditions are temporarily lost.

**Figure 19.** A 200KW full-SiC converter presented by Fraunhofer. The converter achieves an impressive power density

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 99

The rapid adoption of 1200 V SiC MOSFET and cascode devices in the charger market for forklifts and vehicle bidirectional on-board chargers can be easily understood based on the very high efficiency achieved with phase-shift full-bridge topology, that benefit from the low conduction and turn-off loss and from the low Coss and Qrr at light loads. **Figure 18** shows the PSFB efficiency and the waveforms resulting from the low capacitance of the SiC devices compared to incumbent superjunction devices. **Figure 19** shows an excellent demonstration of the power density improvements possible with SiC 1200 V switches for high-power conver-

The long wait for SiC to reach a tipping point appears to be nearing its end. This is due to steady progress on every front needed to realize large-scale adoption, from the maturation of 6-in. SiC material and a deep understanding of SiC defects to improved, easy-to-use devices with a growing reliability track record. An ecosystem of excellent gate drivers makes design simpler, and improved discrete, IPM, and module packages have become available to allow

sion applications, needed on space constrained environments like EVs.

switching at 200kHz, with an efficiency of 98.9%.

**9. Conclusion and outlook**

>100W/cm3

**Figure 18.** Phase shift full-bridge using SiC cascodes UJC06505K with low capacitances, driven by simple pulsetransformer gate drives at 75kHz. Efficiency benefits at standard operating frequencies are also enabled by SiC.

**Figure 19.** A 200KW full-SiC converter presented by Fraunhofer. The converter achieves an impressive power density >100W/cm3 switching at 200kHz, with an efficiency of 98.9%.

eliminate bridge losses [15] has led to the development of the Totem-pole PFC topology. To use this bridgeless circuit in CCM mode, the device required must feature very low-diode recovery losses in addition to basic fast switching capability. **Figure 16** shows the efficiency achieved in a Totem-Pole PFC, and **Figure 17** shows the excellent body diode recovery behavior that makes this possible. For this reason, 650 V SiC devices are likely to compete with GaN devices at >1.5 kW level of server/telecom supplies that require >99% PFC stage efficiency at high frequencies. This lack of diode recovery charge also makes the SiC-based switches useful in avoiding recoveryinduced failures in PSFB and LLC applications when ZVS conditions are temporarily lost.

The rapid adoption of 1200 V SiC MOSFET and cascode devices in the charger market for forklifts and vehicle bidirectional on-board chargers can be easily understood based on the very high efficiency achieved with phase-shift full-bridge topology, that benefit from the low conduction and turn-off loss and from the low Coss and Qrr at light loads. **Figure 18** shows the PSFB efficiency and the waveforms resulting from the low capacitance of the SiC devices compared to incumbent superjunction devices. **Figure 19** shows an excellent demonstration of the power density improvements possible with SiC 1200 V switches for high-power conversion applications, needed on space constrained environments like EVs.

#### **9. Conclusion and outlook**

**Figure 17.** Excellent Qrr for UJC06505K enables hard switching. Low Qrr body diode behavior is a key benefit of SiC

**Figure 18.** Phase shift full-bridge using SiC cascodes UJC06505K with low capacitances, driven by simple pulsetransformer gate drives at 75kHz. Efficiency benefits at standard operating frequencies are also enabled by SiC.

MOSFETs and GaN devices over silicon superjunction devices.

98 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The long wait for SiC to reach a tipping point appears to be nearing its end. This is due to steady progress on every front needed to realize large-scale adoption, from the maturation of 6-in. SiC material and a deep understanding of SiC defects to improved, easy-to-use devices with a growing reliability track record. An ecosystem of excellent gate drivers makes design simpler, and improved discrete, IPM, and module packages have become available to allow the exploitation of the faster switching capability of SiC. These benefits have allowed users to apply circuits previously not possible with Si devices, and this is fueling the growth in the power supply and on-board charger area. With the type of capability now demonstrated with commercial products, there is little doubt that expansion to the automotive inverter will further accelerate the ramp by the early 2020s.

[11] Stahlbush R et al. Basal plane dislocation reduction in 4H-SiC epitaxy by growth inter-

Status of SiC Products and Technology http://dx.doi.org/10.5772/intechopen.76061 101

[13] Kasko I et al. High efficient approach to utilize SiC MOSFET potential in power mod-

[14] Kimura T et al. High-power-density inverter technology for hybrid and electric vehicle

[15] Zhao Z et al. Application opportunities and expectations for wide bandgap devices in

[12] Li X et al. Short circuit capability of SiC cascode. To be published ICSCRM; 2017

ruption. Applied Physics Letter. 2009;**94**(041916):1-3

applications. Hitachi Review. 2014;**63**(2):41-46

power supply. ISPSD. 2017. pp. 13-18

ules. ISPSD; 2017. pp. 259-26

#### **Acknowledgements**

USCi would like to acknowledge contributions from II-VI Corporation, Show Denko Corporation, Yole Developpement, Franuhofer, Hitachi, Semikron, PowerAmerica, Army Research Labs, Naval Research Labs, and Air Force Research Labs to the information in this chapter.

#### **Author details**

Anup Bhalla

Address all correspondence to: abhalla@unitedsic.com

United Silicon Carbide, Inc., Monmouth Junction, NJ, USA

#### **References**


the exploitation of the faster switching capability of SiC. These benefits have allowed users to apply circuits previously not possible with Si devices, and this is fueling the growth in the power supply and on-board charger area. With the type of capability now demonstrated with commercial products, there is little doubt that expansion to the automotive inverter will

USCi would like to acknowledge contributions from II-VI Corporation, Show Denko Corporation, Yole Developpement, Franuhofer, Hitachi, Semikron, PowerAmerica, Army Research Labs,

[1] Wawer P. Tipping point for wide band gap technology signals start of mainstream SiC

[2] Filsecker F, Mashaly A. Reliable SiC power devices for automotive applications. Power

[4] Status of development and mass production for SiC power device. Show Denko KK.

[5] Peters D et al. Performance and ruggedness of 1200V SiC-Trench-MOSFET. ISPSD; 2017.

[8] Huang X et al. Design and fabrication of 3.3KV SiC MOSFETs for industrial applications.

[9] Li X et al. Medium Voltage Power Module Based on SiC JFETs. APEC; 2017. pp. 3033-3037

Naval Research Labs, and Air Force Research Labs to the information in this chapter.

further accelerate the ramp by the early 2020s.

100 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Address all correspondence to: abhalla@unitedsic.com

United Silicon Carbide, Inc., Monmouth Junction, NJ, USA

adoption. In: Bodo's Power Systems; 2017. pp. 20-24

6inch SiC Epitaxial Specifications; 2017

[6] Panasonic at PCIM 2017, DioMOS 6-inch SiC

[10] Lelis A et al. ARL SiC MOS Program Review. 2015

[3] IHS Technology. SiC & GaN Power Semiconductor Report; 2016

[7] Aexandrov P et al. ICSCRM. Material Science Forum. 2016;**897**:673-676

**Acknowledgements**

**Author details**

Anup Bhalla

**References**

EE; 1017

pp. 239-242

ISPSD; 2017. pp. 255-258


**Chapter 6**

Provisional chapter

**GaN-Based Schottky Diode**

GaN-Based Schottky Diode

http://dx.doi.org/10.5772/intechopen.77024

Additional information is available at the end of the chapter

Schottky diode, also known as Schottky barrier diode (SBD), fabricated on GaN and related III-Nitride materials has been researched intensively and extensively for the past two decades. This chapter reviews the property of GaN material, the advantage of GaN-based SBD, and the Schottky contact to GaN including current transporation theory, Schottky material selection, contact quality and thermal stability. The chapter also discusses about the GaN lateral, quasi-vertical and vertical SBDs, and AlGaN/GaN field effect SBDs: the evolution of the epitaxial structure, processing techniques and device structure. The chapter closes with challenges ahead and gives an outlook on the future development of the GaN SBDs.

DOI: 10.5772/intechopen.77024

Wide band gap (WBG) semiconductor materials are the best candidates for high frequency, high power and high temperature applications because of their superior intrinsic material

Among the WBG materials, SiC and GaN are the most successfully developed in terms of material growth, device fabrication and commercialization. GaN and related III-Nitride materials such as InN and AlN and their alloys have many advantages in optoelectronics. III-Nitride materials have a wide range of direct bandgap from the lower end 1.9 eV (InN) to the high end 6.2 eV (AlN) and can also support multi-quantum well and superlattice structures, enabled by epitaxial thin-film growth technology, primarily metal organic chemical vapor deposition (MOCVD). GaN and AlGaN are also the preferred WBG materials in high

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

Keywords: GaN, AlN, AlGaN, Schottky diode, Schottky barrier diode (SBD),

Additional information is available at the end of the chapter

Yaqi Wang

Yaqi Wang

Abstract

Schottky contact

properties compared to Si, and GaAs (Table 1).

1. Introduction

#### **Chapter 6** Provisional chapter

#### **GaN-Based Schottky Diode** GaN-Based Schottky Diode

#### Yaqi Wang Yaqi Wang

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.77024

#### Abstract

Schottky diode, also known as Schottky barrier diode (SBD), fabricated on GaN and related III-Nitride materials has been researched intensively and extensively for the past two decades. This chapter reviews the property of GaN material, the advantage of GaN-based SBD, and the Schottky contact to GaN including current transporation theory, Schottky material selection, contact quality and thermal stability. The chapter also discusses about the GaN lateral, quasi-vertical and vertical SBDs, and AlGaN/GaN field effect SBDs: the evolution of the epitaxial structure, processing techniques and device structure. The chapter closes with challenges ahead and gives an outlook on the future development of the GaN SBDs.

DOI: 10.5772/intechopen.77024

Keywords: GaN, AlN, AlGaN, Schottky diode, Schottky barrier diode (SBD), Schottky contact

#### 1. Introduction

Wide band gap (WBG) semiconductor materials are the best candidates for high frequency, high power and high temperature applications because of their superior intrinsic material properties compared to Si, and GaAs (Table 1).

Among the WBG materials, SiC and GaN are the most successfully developed in terms of material growth, device fabrication and commercialization. GaN and related III-Nitride materials such as InN and AlN and their alloys have many advantages in optoelectronics. III-Nitride materials have a wide range of direct bandgap from the lower end 1.9 eV (InN) to the high end 6.2 eV (AlN) and can also support multi-quantum well and superlattice structures, enabled by epitaxial thin-film growth technology, primarily metal organic chemical vapor deposition (MOCVD). GaN and AlGaN are also the preferred WBG materials in high

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


discussed sequentially in this section. The section also covers topics such as nonmetal Schottky contact to GaN, Schottky contact to AlGaN, and Schottky contact to nonpolar

GaN-Based Schottky Diode

105

http://dx.doi.org/10.5772/intechopen.77024

• GaN lateral, quasi-vertical and vertical SBDs: This section covers material growth and epitaxial structure optimization techniques, device fabrication and device structure optimization techniques such as: surface treatment, dielectric deposition, floating metal ring,

• AlGaN/GaN field effect SBDs: This section discusses about AlGaN/GaN heterojunction formation, material growth and epitaxial structure optimization techniques, device fabrication and device structure optimization techniques that are unique to AlGaN/GaN field effect Schottky barrier diodes such as: dual Schottky anode, Schottky-ohmic-combined anode, gated edge termination, fully recessed Schottky anode and MIS-gated hybrid anode. A brief summary and outlook on GaN SBD development are presented in the last section.

Metal–semiconductor contact plays a crucial role in semiconductor devices, such as diodes and transistors. There are two types of metal-semiconductor contact: Ohmic and Schottky. Schottky contact has a rectifying barrier, which is formed when there is an energy level mismatch between the semiconductor and the metal. The difference between the semiconductor electron affinity and metal work function is defined as Schottky barrier height. The band structure before and after Schottky contact formation to n-type semiconductor, such as intrinsic GaN, is shown in Figure 1. Fermi levels of the metal and semiconductor need to line up to reach an equilibrium when they are put in contact, and the space charge built at the semiconductor side

There are two carrier transportation mechanisms for an ideal Schottky contact: thermionic emission (TE) and field emission (FE). At a forward bias, the carrier transportation is determined by temperature and the n doping concentration of GaN. A lower temperature and a more highly doped GaN can lead to a higher FE component. As Schottky contact is usually deposited on intrinsic GaN or lightly n doped GaN, and the operation temperature of GaN SBD is usually above room temperature, the dominant transportation mechanism is TE. The

current-voltage characteristics of the SBD in the TE regime is given by Eq. (1, 2):

<sup>I</sup> <sup>¼</sup> I0 exp q Vð Þ � IRs

nkT � <sup>1</sup>

(1)

field plate, ion implanted guard ring and Schottky junction barrier diode.

GaN.

2. Schottky contacts to GaN

leads to band bending effect.

where I0 is the saturation current:

2.1. Theoretical basis of Schottky contact to GaN

Eg: bandgap; Ec: critical electric field; μn: electron mobility; ε: dielectric constant; Vsat: saturation electron velocity; λ: thermal conductivity.

Table 1. Comparison of material properties of Si, GaAs, 4H-SiC and GaN [1].

frequency applications as two-dimensional electron gas (2DEG) with high carrier concentration and mobility can be formed at the AlGaN/GaN heterointerface by spontaneous and piezoelectric polarization effect [2]. GaN based light emitting diode (LED), GaN based laser diode (LD) and AlGaN/GaN based high-electron-mobility transistor (HEMT) were commercialized in early 1990s, late 1990s and mid 2000s respectively.

In the realm of high power and high temperature applications, as Si based power device is reaching its theoretical limit and cannot meet the increasing demand of key performance metrics, such as high blocking voltage, low switching loss, high switching speed and high operating temperature at the same time, WBG materials has great potential to replace Si in those applications [3].

Specifically, in applications that require high reverse blocking voltage and high switching frequency, SiC and GaN Schottky barrier diodes (SBDs) are preferred over bipolar Si p-i-n diode, whose switching speed is compromised due to long minority carrier lifetime. SiC and GaN are comparable in many aspects: GaN has higher Baliga's figure of merit (BFoM) because of its better electrical properties, while SiC has better thermal conductivity, thus the two materials are in direct competition for the application [4]. SiC SBD was successfully introduced to the market in early 2000s, and gradually matured to displace the Si p-i-n diode. On the other hand, because of the nonoptimal material quality, which once limited the application of its SiC counterpart, GaN SBD still cannot achieve its theoretical performance. Researchers around the world have been continuously working on improving GaN material quality, while exploring novel ways to fabricate GaN SBD with better performance since mid-1990s. Although great progress has been made, significant amount of effort is still need for GaN SBD to overcome the technical challenges, close its performance gap to SiC SBD, and eventually achieve commercial success.

In the following sections of this chapter, several topics are discussed in details:

• Schottky contacts to GaN: Theoretical basis, current transportation mechanisms, characterization methods, metal selection and comparison, the impact to contact performance by material and surface quality, and thermal stability of Schottky contact to GaN were discussed sequentially in this section. The section also covers topics such as nonmetal Schottky contact to GaN, Schottky contact to AlGaN, and Schottky contact to nonpolar GaN.


A brief summary and outlook on GaN SBD development are presented in the last section.

#### 2. Schottky contacts to GaN

frequency applications as two-dimensional electron gas (2DEG) with high carrier concentration and mobility can be formed at the AlGaN/GaN heterointerface by spontaneous and piezoelectric polarization effect [2]. GaN based light emitting diode (LED), GaN based laser diode (LD) and AlGaN/GaN based high-electron-mobility transistor (HEMT) were commer-

) 1500 8500 1000 1250

) 1.5 0.5 4.9 2.3 Eg: bandgap; Ec: critical electric field; μn: electron mobility; ε: dielectric constant; Vsat: saturation electron velocity;

Parameter Si GaAs 4H-SiC GaN Eg (eV) 1.12 1.42 3.25 3.40 Ec (MV/cm) 0.3 0.4 3.0 4.0

ε 11.8 12.8 9.7 9.0 Vsat (107 cm/s) 1 2 2 2.5

In the realm of high power and high temperature applications, as Si based power device is reaching its theoretical limit and cannot meet the increasing demand of key performance metrics, such as high blocking voltage, low switching loss, high switching speed and high operating temperature at the same time, WBG materials has great potential to replace Si in

Specifically, in applications that require high reverse blocking voltage and high switching frequency, SiC and GaN Schottky barrier diodes (SBDs) are preferred over bipolar Si p-i-n diode, whose switching speed is compromised due to long minority carrier lifetime. SiC and GaN are comparable in many aspects: GaN has higher Baliga's figure of merit (BFoM) because of its better electrical properties, while SiC has better thermal conductivity, thus the two materials are in direct competition for the application [4]. SiC SBD was successfully introduced to the market in early 2000s, and gradually matured to displace the Si p-i-n diode. On the other hand, because of the nonoptimal material quality, which once limited the application of its SiC counterpart, GaN SBD still cannot achieve its theoretical performance. Researchers around the world have been continuously working on improving GaN material quality, while exploring novel ways to fabricate GaN SBD with better performance since mid-1990s. Although great progress has been made, significant amount of effort is still need for GaN SBD to overcome the technical challenges, close its performance gap to SiC SBD, and eventually achieve commercial success.

In the following sections of this chapter, several topics are discussed in details:

• Schottky contacts to GaN: Theoretical basis, current transportation mechanisms, characterization methods, metal selection and comparison, the impact to contact performance by material and surface quality, and thermal stability of Schottky contact to GaN were

cialized in early 1990s, late 1990s and mid 2000s respectively.

Table 1. Comparison of material properties of Si, GaAs, 4H-SiC and GaN [1].

104 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

those applications [3].

μ<sup>n</sup> (cm<sup>2</sup> <sup>V</sup><sup>1</sup> s 1

<sup>λ</sup> (Wcm<sup>1</sup>

<sup>K</sup><sup>1</sup>

λ: thermal conductivity.

#### 2.1. Theoretical basis of Schottky contact to GaN

Metal–semiconductor contact plays a crucial role in semiconductor devices, such as diodes and transistors. There are two types of metal-semiconductor contact: Ohmic and Schottky. Schottky contact has a rectifying barrier, which is formed when there is an energy level mismatch between the semiconductor and the metal. The difference between the semiconductor electron affinity and metal work function is defined as Schottky barrier height. The band structure before and after Schottky contact formation to n-type semiconductor, such as intrinsic GaN, is shown in Figure 1. Fermi levels of the metal and semiconductor need to line up to reach an equilibrium when they are put in contact, and the space charge built at the semiconductor side leads to band bending effect.

There are two carrier transportation mechanisms for an ideal Schottky contact: thermionic emission (TE) and field emission (FE). At a forward bias, the carrier transportation is determined by temperature and the n doping concentration of GaN. A lower temperature and a more highly doped GaN can lead to a higher FE component. As Schottky contact is usually deposited on intrinsic GaN or lightly n doped GaN, and the operation temperature of GaN SBD is usually above room temperature, the dominant transportation mechanism is TE. The current-voltage characteristics of the SBD in the TE regime is given by Eq. (1, 2):

$$\mathbf{I} = \mathbf{I}\_0 \left\{ \exp\left[\frac{q(V - IR\_s)}{nkT}\right] - \mathbf{1} \right\} \tag{1}$$

where I0 is the saturation current:

$$\mathbf{I}\_0 = \mathbf{A} \mathbf{A}^\* \mathbf{T}^2 \exp\left(\frac{-q\Phi\_\mathcal{B}}{kT}\right) \tag{2}$$

Miller et al. designed an experiment to detect localized leakage path on GaN surface by conductive atomic force microscope (AFM), and developed a surface modification method by selectively applying voltage at the recorded leakage locations to form a thin passivation layer that blocks the leakage path. Schottky contact made on surface modified GaN showed much better reverse leakage characteristics than unmodified GaN [15]. Sang et al. performed detailed analysis on leakage path by photon emission microscopy (PEM), and found the leakage current occurred at polygonal pits, where carbon impurity accumulated and acted as trap in carrier tunneling [16]. The result aligned with the Cao et al.'s finding that low carbon concentration was necessary to achieve high Schottky contact quality, by an experiment correlating contact performance with carbon doping level [17]. Reddy et al. demonstrated a homogeneous Schottky contact to GaN with unity ideality factor and low leakage current by acid treatment. XPS studies showed the treatment removed excess carbon and restored Ga/N composition at the interface [18]. It can be concluded that removal of impurities such as carbon, and/or passivation of leakage path by surface treatment, is effective in improving Schottky contact

Table 2. Summary of Schottky barrier height of Au, Ni, Pd, and Pt to GaN from I-V, I-V-T, and C-V experiment results.

Metal Φ<sup>b</sup> (eV) by I-V Φ<sup>b</sup> (eV) by I-V-T Φ<sup>b</sup> (eV) by C-V Reported Au 0.844 — 0.94 Hacke et al. [5]

Ni 1.15 — 1.11 Kalinina et al. [9]

Pd — 0.91 0.94 Guo et al. [7]

Pt — 1.03 1.04 Guo et al. [7]

0.91 — 1.01 Khan et al. [6] 1.03 — 1.03 Kalinina et al. [9] 0.87 0.88 0.98 Ping et al. [10]

0.95 0.99 1.13 Schmitz et al. [11] 0.83 0.93 1.03 Liu et al. [12]

1.11 0.96 1.24 Wang et al. [8] 0.94 0.92 1.07 Ping et al. [10]

1.13 — 1.27 Wang et al. [8] 1.01 1.08 1.16 Schmitz et al. [11]

Schmitz et al. [11]

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Schmitz et al. [11]

Schottky contact thermal stability is important to GaN SBDs, as high operating temperature is desired for power applications. At elevated temperature, Schottky metal reacts with GaN, gradually turning the contact nonrectifying. Guo et al. reported Ni Schottky contact started to react with GaN, forming nickel nitrides, at temperature above 200C [19]. For noble metal Pd, interdiffusion of the metal and GaN was discovered at 300C [20]. If stable temperature is defined as temperature at which Schottky contact is still rectifying after 1 hour of annealing,

quality.

The three most common Schottky contact characterization methods are current-voltage (IV), current-voltage-temperature (I-V-T) and capacitance-voltage (C-V). Key parameters, such as Schottky barrier height (ΦB), ideality factor (n), effective Richardson's constant (A\* ), doping concentration (ND) and series resistance (Rs) can be extracted from the characterization methods mentioned above.

#### 2.2. Metal Schottky contacts to GaN

Tremendous amount of work on Schottky contacts to GaN was done in mid 1990s, which built solid foundation for later development of vertical and lateral GaN SBDs. Au Schottky contact to n-GaN was first reported by Hacke et al. [5] and Khan et al. [6]. Schottky contact formation of Ni, Pd and Pt to GaN was then extensively studied by various research groups [7–12]. I-V, I-V-T and C-V measurements were performed to find the characteristics of the Schottky contacts, such as ideality factor, effective Richardson coefficient, and Schottky barrier height. Table 2 shows a brief summary of Schottky barrier heights of common contact metals by the three methods mentioned above.

Liu and Lau reviewed the scattered results reported and suggested the nonideal Schottky contact behavior probably stemmed from surface defect which can cause inhomogeneity in the transport current even within a single device, while material quality and metal-GaN reactions were the other two contributing factors [13]. Hsu et al. performed scanning current– voltage microscopy (SIVM) measurements and found nonuniform spatial reverse leakage distribution within a device. The correlation of SIVM, topographical and TEM images showed that leakage occurred at screw and mixed dislocation [14]. The experiment confirmed surface and material quality is crucial to good Schottky contact formation.

Figure 1. Band structure of Schottky barrier formation [1].


I0 <sup>¼</sup> AA<sup>∗</sup>

106 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

methods mentioned above.

methods mentioned above.

2.2. Metal Schottky contacts to GaN

T2

Schottky barrier height (ΦB), ideality factor (n), effective Richardson's constant (A\*

The three most common Schottky contact characterization methods are current-voltage (IV), current-voltage-temperature (I-V-T) and capacitance-voltage (C-V). Key parameters, such as

concentration (ND) and series resistance (Rs) can be extracted from the characterization

Tremendous amount of work on Schottky contacts to GaN was done in mid 1990s, which built solid foundation for later development of vertical and lateral GaN SBDs. Au Schottky contact to n-GaN was first reported by Hacke et al. [5] and Khan et al. [6]. Schottky contact formation of Ni, Pd and Pt to GaN was then extensively studied by various research groups [7–12]. I-V, I-V-T and C-V measurements were performed to find the characteristics of the Schottky contacts, such as ideality factor, effective Richardson coefficient, and Schottky barrier height. Table 2 shows a brief summary of Schottky barrier heights of common contact metals by the three

Liu and Lau reviewed the scattered results reported and suggested the nonideal Schottky contact behavior probably stemmed from surface defect which can cause inhomogeneity in the transport current even within a single device, while material quality and metal-GaN reactions were the other two contributing factors [13]. Hsu et al. performed scanning current– voltage microscopy (SIVM) measurements and found nonuniform spatial reverse leakage distribution within a device. The correlation of SIVM, topographical and TEM images showed that leakage occurred at screw and mixed dislocation [14]. The experiment confirmed surface

and material quality is crucial to good Schottky contact formation.

Figure 1. Band structure of Schottky barrier formation [1].

exp �qΦ<sup>B</sup> kT 

(2)

), doping

Table 2. Summary of Schottky barrier height of Au, Ni, Pd, and Pt to GaN from I-V, I-V-T, and C-V experiment results.

Miller et al. designed an experiment to detect localized leakage path on GaN surface by conductive atomic force microscope (AFM), and developed a surface modification method by selectively applying voltage at the recorded leakage locations to form a thin passivation layer that blocks the leakage path. Schottky contact made on surface modified GaN showed much better reverse leakage characteristics than unmodified GaN [15]. Sang et al. performed detailed analysis on leakage path by photon emission microscopy (PEM), and found the leakage current occurred at polygonal pits, where carbon impurity accumulated and acted as trap in carrier tunneling [16]. The result aligned with the Cao et al.'s finding that low carbon concentration was necessary to achieve high Schottky contact quality, by an experiment correlating contact performance with carbon doping level [17]. Reddy et al. demonstrated a homogeneous Schottky contact to GaN with unity ideality factor and low leakage current by acid treatment. XPS studies showed the treatment removed excess carbon and restored Ga/N composition at the interface [18]. It can be concluded that removal of impurities such as carbon, and/or passivation of leakage path by surface treatment, is effective in improving Schottky contact quality.

Schottky contact thermal stability is important to GaN SBDs, as high operating temperature is desired for power applications. At elevated temperature, Schottky metal reacts with GaN, gradually turning the contact nonrectifying. Guo et al. reported Ni Schottky contact started to react with GaN, forming nickel nitrides, at temperature above 200C [19]. For noble metal Pd, interdiffusion of the metal and GaN was discovered at 300C [20]. If stable temperature is defined as temperature at which Schottky contact is still rectifying after 1 hour of annealing, the highest stable temperature for Ni and Pt was reported to be 500C [12] and 400C [21], respectively. Several techniques were applied to improve stability of Schottky contact to GaN. Thermal stability of metal silicide is usually better than elemental metal. The stable temperature was reported to be 600C for NiSi [12] and PtSi [21], 100–200C higher than elemental Ni and Pt. Multilayer contact structure with inert and high melting point metal as insert or cap layers can also help to improve the thermal stability of Schottky contact. Stable temperature of Ni/Ta bilayer Schottky contact was reported to be 700C [22], 200C higher than pure Ni.

3. GaN lateral, quasi-vertical, and vertical SBDs

vertical structures are preferred for practical applications.

current GaN material growth technology.

black region is ohmic contact and the grid region is substrate.

3.1. GaN substrate growth and epitaxial structure optimization

The extensive study of Schottky contacts to GaN enabled the development of high breakdown GaN SBDs in late 1990s. GaN based SBDs have three common structures: lateral, quasi-vertical and vertical. Figure 2 shows the schematics of the three structures. Lateral and quasi-vertical SBDs are usually fabricated on GaN grown on a foreign substrate, such as sapphire, SiC and Si. For lateral SBD, Schottky contact and ohmic contact are on the same surface. For quasi-vertical SBDs, a mesa is etched first, followed by ohmic contact deposition on the etched GaN and Schottky contact deposition on top of mesa. Vertical SBDs are usually fabricated on freestanding GaN substrate by depositing ohmic contact on the nitride face and Schottky contact on the gallium face. Lateral SBDs are easy to fabricate and thus are still used as development vehicles for testing new material growth and device processing methods, while quasi-vertical and

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Hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) are the three most common methods for substrate growth. The GaN thickness, doping level are critical to SBD performance. While a design with a thinner and more highly doped GaN can lead to better on-state resistance and lower turn-on voltage, it has negative impact on breakdown voltage. The ideal substrate for GaN SBD shall have a gradient doping profile, with low dopant concentration on the Schottky side, and high dopant concentration on the ohmic side. However, such structure cannot be well supported by the

Quasi-vertical and vertical GaN SBDs are usually fabricated on substrates with layer structure, which has a lightly doped GaN drift layer on top of a highly doped low resistivity GaN layer, where Schottky contact and ohmic contact are formed, respectively. The layer structure has been developed on various substrate types. Sheu et al. reported a very thin low-temperategrown (LTG) cap layer can greatly suppress reverse leakage current [35]. The layer structure consisted of a 30 nm LTG GaN cap layer, a 0.6 μm thick intrinsic GaN layer and a 1 μm thick highly doped GaN layer, grown by MOCVD on sapphire substrate. The highly doped and intrinsic GaN layers were grown at 1060C, while the LTG GaN cap layer was grown at 550C.

Figure 2. Schematics of (a) lateral, (b) quasi-vertical, and (c) vertical SBDs on GaN: the gray region is Schottky contact,

#### 2.3. Nonmetallic Schottky contacts to GaN

ITO and graphene Schottky contacts to GaN were also studied, as they are transparent and have potential applications in optoelectronic devices such as MSM photodetector. Sheu et al. reported ITO Schottky contact to GaN with increasing barrier height from 0.68 eV as deposited to 0.95 eV after annealed at 600C [23]. Tongay et al. first reported graphene and multilayer graphene (MLG) Schottky contact, with barrier height of 0.74 eV as deposited and 0.70 eV after prolonged annealing at ~ 600C [24]. The large ideality factor (>2) indicated high contact inhomogeneity. Kim et al. reported improved graphene Schottky contact with 0.9 eV barrier height and 1.32 ideality factor [25].

#### 2.4. Schottky contacts to AlGaN

Schottky contacts need to be made to AlGaN in some AlGaN/GaN field effect SBD applications. Qiao et al. characterized Ni Schottky contact to AlGaN by I-V, C-V and photoemission methods, and found the barrier height increased linearly with Al mole fraction up to 0.23 [26]. Lv et al. applied two-diode model and determined barrier height of Ni Schottky contact to AlGaN/GaN heterostructures by forward I-V measurement [27]. Shin et al. investigated common GaN Schottky metals, such as Au, Ni, Pd and Pt, to AlGaN/GaN heterostructures and found barrier inhomogeneity was related with Schottky metal type [28]. Nonmetallic materials such as TiN was also studied. TiN can be deposited to AlGaN surface by reactive sputtering [29]. The lower barrier height of TiN compared to common Schottky metals enables a lower turn-on voltage, which is preferred in application such as microwave rectification [30].

#### 2.5. Schottky contacts to nonpolar GaN

Schottky contacts made to a-plane and m-plane nonpolar GaN were also studied. Phark et al. studied Pt Schottky contacts to a-plane n-GaN [31]. Yamada et al. fabricated Ni Schottky diode on m-plane n-GaN [32], and compared with the Schottky diode with same structure fabricated on c-plane [33]. Although the carbon concentration of the m-plane GaN was much less than c-plan GaN, the reverse leakage was three orders of magnitude larger due to lower barrier height. To date, it still remains unclear whether c-plane or nonpolar GaN is preferred in Schottky diode application mainly because nonpolar GaN Schottky devices were much less frequently investigated [34].

## 3. GaN lateral, quasi-vertical, and vertical SBDs

the highest stable temperature for Ni and Pt was reported to be 500C [12] and 400C [21], respectively. Several techniques were applied to improve stability of Schottky contact to GaN. Thermal stability of metal silicide is usually better than elemental metal. The stable temperature was reported to be 600C for NiSi [12] and PtSi [21], 100–200C higher than elemental Ni and Pt. Multilayer contact structure with inert and high melting point metal as insert or cap layers can also help to improve the thermal stability of Schottky contact. Stable temperature of Ni/Ta bilayer Schottky contact was reported to be 700C [22], 200C higher than pure Ni.

108 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

ITO and graphene Schottky contacts to GaN were also studied, as they are transparent and have potential applications in optoelectronic devices such as MSM photodetector. Sheu et al. reported ITO Schottky contact to GaN with increasing barrier height from 0.68 eV as deposited to 0.95 eV after annealed at 600C [23]. Tongay et al. first reported graphene and multilayer graphene (MLG) Schottky contact, with barrier height of 0.74 eV as deposited and 0.70 eV after prolonged annealing at ~ 600C [24]. The large ideality factor (>2) indicated high contact inhomogeneity. Kim et al. reported improved graphene Schottky contact with 0.9 eV barrier

Schottky contacts need to be made to AlGaN in some AlGaN/GaN field effect SBD applications. Qiao et al. characterized Ni Schottky contact to AlGaN by I-V, C-V and photoemission methods, and found the barrier height increased linearly with Al mole fraction up to 0.23 [26]. Lv et al. applied two-diode model and determined barrier height of Ni Schottky contact to AlGaN/GaN heterostructures by forward I-V measurement [27]. Shin et al. investigated common GaN Schottky metals, such as Au, Ni, Pd and Pt, to AlGaN/GaN heterostructures and found barrier inhomogeneity was related with Schottky metal type [28]. Nonmetallic materials such as TiN was also studied. TiN can be deposited to AlGaN surface by reactive sputtering [29]. The lower barrier height of TiN compared to common Schottky metals enables a lower

turn-on voltage, which is preferred in application such as microwave rectification [30].

Schottky contacts made to a-plane and m-plane nonpolar GaN were also studied. Phark et al. studied Pt Schottky contacts to a-plane n-GaN [31]. Yamada et al. fabricated Ni Schottky diode on m-plane n-GaN [32], and compared with the Schottky diode with same structure fabricated on c-plane [33]. Although the carbon concentration of the m-plane GaN was much less than c-plan GaN, the reverse leakage was three orders of magnitude larger due to lower barrier height. To date, it still remains unclear whether c-plane or nonpolar GaN is preferred in Schottky diode application mainly because nonpolar GaN Schottky devices were much less frequently

2.3. Nonmetallic Schottky contacts to GaN

height and 1.32 ideality factor [25].

2.4. Schottky contacts to AlGaN

2.5. Schottky contacts to nonpolar GaN

investigated [34].

The extensive study of Schottky contacts to GaN enabled the development of high breakdown GaN SBDs in late 1990s. GaN based SBDs have three common structures: lateral, quasi-vertical and vertical. Figure 2 shows the schematics of the three structures. Lateral and quasi-vertical SBDs are usually fabricated on GaN grown on a foreign substrate, such as sapphire, SiC and Si. For lateral SBD, Schottky contact and ohmic contact are on the same surface. For quasi-vertical SBDs, a mesa is etched first, followed by ohmic contact deposition on the etched GaN and Schottky contact deposition on top of mesa. Vertical SBDs are usually fabricated on freestanding GaN substrate by depositing ohmic contact on the nitride face and Schottky contact on the gallium face. Lateral SBDs are easy to fabricate and thus are still used as development vehicles for testing new material growth and device processing methods, while quasi-vertical and vertical structures are preferred for practical applications.

#### 3.1. GaN substrate growth and epitaxial structure optimization

Hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) are the three most common methods for substrate growth. The GaN thickness, doping level are critical to SBD performance. While a design with a thinner and more highly doped GaN can lead to better on-state resistance and lower turn-on voltage, it has negative impact on breakdown voltage. The ideal substrate for GaN SBD shall have a gradient doping profile, with low dopant concentration on the Schottky side, and high dopant concentration on the ohmic side. However, such structure cannot be well supported by the current GaN material growth technology.

Quasi-vertical and vertical GaN SBDs are usually fabricated on substrates with layer structure, which has a lightly doped GaN drift layer on top of a highly doped low resistivity GaN layer, where Schottky contact and ohmic contact are formed, respectively. The layer structure has been developed on various substrate types. Sheu et al. reported a very thin low-temperategrown (LTG) cap layer can greatly suppress reverse leakage current [35]. The layer structure consisted of a 30 nm LTG GaN cap layer, a 0.6 μm thick intrinsic GaN layer and a 1 μm thick highly doped GaN layer, grown by MOCVD on sapphire substrate. The highly doped and intrinsic GaN layers were grown at 1060C, while the LTG GaN cap layer was grown at 550C.

Figure 2. Schematics of (a) lateral, (b) quasi-vertical, and (c) vertical SBDs on GaN: the gray region is Schottky contact, black region is ohmic contact and the grid region is substrate.

Lu et al. reported a method to regrow GaN epitaxial layers by MOCVD on HVPE grown low resistivity freestanding GaN substrate. The layer structure has a 2 μm thick lightly doped GaN lay on a 0.5 μm thick highly doped GaN layer. It was reported that the structure greatly reduced the on-state resistance [36]. Fu et al. made further improvement to MOCVD regrown drift layers on HVPE substrate by introducing double-drift-layer (DDL) design [37]. An additional moderately doped GaN layer was inserted in between the lightly doped top layer and the highly doped bottom layer. It was demonstrated the breakdown voltage was improved with DDL design, while the forward characteristics was not compromised. The DDL design is much close to the ideal structure mentioned above. Cao et al. introduced a graded AlN cap layer on top of the GaN drift layer [38]. The cap layer has a thickness of 5 nm with Al composition from 0–23%. It was reported the cap layer reduced the leakage current by three orders of magnitude and the turn-on voltage from 0.77 to 0.67 V from tunneling effect.

pits around defects [43]. The leakage characteristics was improved for SBDs fabricated on both MBE and HVPE grown GaN substrates. It can be concluded that surface treatment, with a variety of techniques such as annealing, PEC etching in KOH solution, and molten KOH etch,

Dielectric layer deposition on drift layer top surface or mesa side wall can reduce the arcing effect, thus can improve the breakdown voltage of the GaN SBD. Most common dielectric materials used are SiO2, SiNx and Al2O3. The layer can be deposited by plasma-enhanced chemical vapor deposition (PECVD), RF sputtering and e-beam evaporation. In Zhu et al.'s work, a dielectric SiO2 layer was deposited on the mesa wall by PECVD for passivation [42]. Float metal ring (FMR) technique uses an additional metal ring around Schottky contact to reduce electric field crowding at reverse bias. Two parameters: ring width and ring space, are critical to the FMR effectiveness. Schematics of FMR structure is shown in Figure 3a. GaN SBDs fabricated with FMR was first reported by Lee et al. A high breakdown voltage of 353 V was obtained on the SBD fabricated with FMR versus only 159 V without FMR [44]. The author also demonstrated the optimized structure by a design of experiment (DOE) with parameters ring width and ring space. Field plate (FP) incorporates both dielectric layer and metal overlay on top of dielectric layer to reduce electric field crowding. Dielectric layer thickness, metal overlay extent and dielectric permittivity are the three key parameters of FP. Schematics of FP structure is shown in Figure 3b. Bandić et al. first compared GaN lateral SBD with a field plate on sputtered SiO2 dielectric layer and without field plate and found the field plate can suppress the leakage current by one to two orders of magnitude. Simulation was performed by Baik et al. to find the optimized FP structure [45]. A minimum metal overlay extent of 5 μm and a minimum dielectric layer thickness of 0.3 μm for SiNx was needed to avoid dielectric breakdown at the FP on GaN cap layer with an unintentional n doping level of 5 1016 cm<sup>3</sup>

Kang et al. fabricated GaN vertical SBD with Pt/Au Schottky contact and FP on e-beam deposited SiNx dielectric layer based on the simulation result, but to find a much lower experimental breakdown voltage than theoretical because of the GaN surface degradation from device processing [46]. Lei et al. did a comprehensive investigation of the GaN SBD FP design rule by simulation and came with the conclusions: Metal overlay extent beyond maximum depletion depth of GaN under reverse bias do not further improve breakdown voltage; The two competing reverse breakdown modes: GaN breakdown and dielectric breakdown

Figure 3. Schematics of (a) FMR and (b) FP structure: the gray region is Schottky contact, black region is ohmic contact,

and the dotted region is dielectric.

.

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is very effective to improve the GaN SBD quality.

#### 3.2. SBD device fabrication and device structure optimization

The theoretical limit of the key parameters of GaN SBDs, such as breakdown voltage etc., are determined by the substrate structure. However, the SBDs performance reported is still far from the theoretical limit. Premature breakdown and high reverse leakage are the two main major areas that can be improved by better device processing and structure. Surface treatment, dielectric deposition, floating metal ring, field plate, ion implanted guard ring and Schottky junction barrier diode are discussed below.

Mesa etch is a necessary step for quasi-vertical GaN SBD fabrication. The mesa wall quality after etching can greatly affect the breakdown voltage and reverse leakage of the SBD. Surface treatment after mesa etching or material growth is critical for device performance. Bandić et al. first fabricated high breakdown voltage (450 V) lateral and quasi-vertical SBDs using Au as Schottky contact metal. The substrates used in the study consisted of an 8–10 μm GaN drift layer on a very thin (<100 nm) n+ layer, and were grown by hydride vapor phase epitaxy (HVPE) on sapphire [39]. High leakage current was observed on quasi-vertical SBD structure due to plasma etch damage on mesa wall. Cao et al. explained the forms of plasma-induced damage to GaN as follows: generation of surface defects by ion, dopants passivation by atomic hydrogen, deposition of impurities and creation of nonstoichiometric surfaces [40]. The study also found a subsequent annealing at 750C under N2 or photoelectrochemical (PEC) etching in KOH solution to remove ~ 500–600 Å of the surface helped on the mesa wall quality improvement and leakage current reduction. Further study by Cao et al. suggested that the wet KOH etching is more effective than annealing for mesa wall treatment and diode characteristics restoration [41]. The GaN structures used in both studies were grown by RF plasmaassisted MBE on sapphire [40–41]. Zhu et al. fabricated quasi-vertical SBDs with mesa formed by both dry etching with a following KOH mesa wall treatment, and full wet PEC etching [42]. The GaN epitaxial structure with a 2 μm drift layer on top of a 1 μm n<sup>+</sup> GaN layer was grown by low-pressure MOCVD on sapphire substrate. Pt/Au was used as Schottky contact metal. The study demonstrated the device performance with wet-etched mesa is comparable or better than dry-etched. Spradlin et al. used molten KOH etching instead of PEC etching in KOH solution, and showed the molten KOH etching reduced the surface roughness and form etch pits around defects [43]. The leakage characteristics was improved for SBDs fabricated on both MBE and HVPE grown GaN substrates. It can be concluded that surface treatment, with a variety of techniques such as annealing, PEC etching in KOH solution, and molten KOH etch, is very effective to improve the GaN SBD quality.

Lu et al. reported a method to regrow GaN epitaxial layers by MOCVD on HVPE grown low resistivity freestanding GaN substrate. The layer structure has a 2 μm thick lightly doped GaN lay on a 0.5 μm thick highly doped GaN layer. It was reported that the structure greatly reduced the on-state resistance [36]. Fu et al. made further improvement to MOCVD regrown drift layers on HVPE substrate by introducing double-drift-layer (DDL) design [37]. An additional moderately doped GaN layer was inserted in between the lightly doped top layer and the highly doped bottom layer. It was demonstrated the breakdown voltage was improved with DDL design, while the forward characteristics was not compromised. The DDL design is much close to the ideal structure mentioned above. Cao et al. introduced a graded AlN cap layer on top of the GaN drift layer [38]. The cap layer has a thickness of 5 nm with Al composition from 0–23%. It was reported the cap layer reduced the leakage current by three

orders of magnitude and the turn-on voltage from 0.77 to 0.67 V from tunneling effect.

The theoretical limit of the key parameters of GaN SBDs, such as breakdown voltage etc., are determined by the substrate structure. However, the SBDs performance reported is still far from the theoretical limit. Premature breakdown and high reverse leakage are the two main major areas that can be improved by better device processing and structure. Surface treatment, dielectric deposition, floating metal ring, field plate, ion implanted guard ring and Schottky

Mesa etch is a necessary step for quasi-vertical GaN SBD fabrication. The mesa wall quality after etching can greatly affect the breakdown voltage and reverse leakage of the SBD. Surface treatment after mesa etching or material growth is critical for device performance. Bandić et al. first fabricated high breakdown voltage (450 V) lateral and quasi-vertical SBDs using Au as Schottky contact metal. The substrates used in the study consisted of an 8–10 μm GaN drift layer on a very thin (<100 nm) n+ layer, and were grown by hydride vapor phase epitaxy (HVPE) on sapphire [39]. High leakage current was observed on quasi-vertical SBD structure due to plasma etch damage on mesa wall. Cao et al. explained the forms of plasma-induced damage to GaN as follows: generation of surface defects by ion, dopants passivation by atomic hydrogen, deposition of impurities and creation of nonstoichiometric surfaces [40]. The study also found a subsequent annealing at 750C under N2 or photoelectrochemical (PEC) etching in KOH solution to remove ~ 500–600 Å of the surface helped on the mesa wall quality improvement and leakage current reduction. Further study by Cao et al. suggested that the wet KOH etching is more effective than annealing for mesa wall treatment and diode characteristics restoration [41]. The GaN structures used in both studies were grown by RF plasmaassisted MBE on sapphire [40–41]. Zhu et al. fabricated quasi-vertical SBDs with mesa formed by both dry etching with a following KOH mesa wall treatment, and full wet PEC etching [42]. The GaN epitaxial structure with a 2 μm drift layer on top of a 1 μm n<sup>+</sup> GaN layer was grown by low-pressure MOCVD on sapphire substrate. Pt/Au was used as Schottky contact metal. The study demonstrated the device performance with wet-etched mesa is comparable or better than dry-etched. Spradlin et al. used molten KOH etching instead of PEC etching in KOH solution, and showed the molten KOH etching reduced the surface roughness and form etch

3.2. SBD device fabrication and device structure optimization

110 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

junction barrier diode are discussed below.

Dielectric layer deposition on drift layer top surface or mesa side wall can reduce the arcing effect, thus can improve the breakdown voltage of the GaN SBD. Most common dielectric materials used are SiO2, SiNx and Al2O3. The layer can be deposited by plasma-enhanced chemical vapor deposition (PECVD), RF sputtering and e-beam evaporation. In Zhu et al.'s work, a dielectric SiO2 layer was deposited on the mesa wall by PECVD for passivation [42]. Float metal ring (FMR) technique uses an additional metal ring around Schottky contact to reduce electric field crowding at reverse bias. Two parameters: ring width and ring space, are critical to the FMR effectiveness. Schematics of FMR structure is shown in Figure 3a. GaN SBDs fabricated with FMR was first reported by Lee et al. A high breakdown voltage of 353 V was obtained on the SBD fabricated with FMR versus only 159 V without FMR [44]. The author also demonstrated the optimized structure by a design of experiment (DOE) with parameters ring width and ring space. Field plate (FP) incorporates both dielectric layer and metal overlay on top of dielectric layer to reduce electric field crowding. Dielectric layer thickness, metal overlay extent and dielectric permittivity are the three key parameters of FP. Schematics of FP structure is shown in Figure 3b. Bandić et al. first compared GaN lateral SBD with a field plate on sputtered SiO2 dielectric layer and without field plate and found the field plate can suppress the leakage current by one to two orders of magnitude. Simulation was performed by Baik et al. to find the optimized FP structure [45]. A minimum metal overlay extent of 5 μm and a minimum dielectric layer thickness of 0.3 μm for SiNx was needed to avoid dielectric breakdown at the FP on GaN cap layer with an unintentional n doping level of 5 1016 cm<sup>3</sup> . Kang et al. fabricated GaN vertical SBD with Pt/Au Schottky contact and FP on e-beam deposited SiNx dielectric layer based on the simulation result, but to find a much lower experimental breakdown voltage than theoretical because of the GaN surface degradation from device processing [46]. Lei et al. did a comprehensive investigation of the GaN SBD FP design rule by simulation and came with the conclusions: Metal overlay extent beyond maximum depletion depth of GaN under reverse bias do not further improve breakdown voltage; The two competing reverse breakdown modes: GaN breakdown and dielectric breakdown

Figure 3. Schematics of (a) FMR and (b) FP structure: the gray region is Schottky contact, black region is ohmic contact, and the dotted region is dielectric.

lead to an optimum dielectric layer thickness; Optimum dielectric layer thickness is related with dielectric permittivity [47]. In summary, both simulation and experiment results demonstrated that addition device structures such as dielectric passivation layer, FRM and FP, can contribute to better GaN SBD performance.

p+

FESBD.

leakage current compared to traditional SBD.

4. AlGaN/GaN field effect SBDs

/n junction. In trench JBSD, a p+ epitaxy layer is firstly deposited, followed by a selective etching down to nGaN substrate to form trench structure. The Schottky contact is then deposited on the trench. Under reverse bias, the depletion region spread laterally from the p+/n interface and pinch off the Schottky barrier. The study of Li et al. shows about 20 times reduction in the

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Spontaneous and piezoelectric polarization can result in built-in electric field in AlGaN/GaN heterostructure. Band bending and alignment of Fermi level in AlGaN and GaN forms a twodimensional electron gas (2DEG) at the interface. Figure 5 shows band diagram of the AlGaN/ GaN heterostructure. Because of the high carrier mobility of the 2DEG, low on-state resistance can be achieved for device utilizing AlGaN/GaN heterostructure. GaN based High-electron mobility transistor (HEMT) has been developed for power and RF applications and showed

The AlGaN/GaN heterostructure can also be used in SBD. The concept of GaN field effect Schottky barrier diode (FESBD) was first brought up by Yoshida et al. in 2004 [54], with device schematics shown in Figure 6. AlGaN/GaN FESBD shares the same epitaxial structure and device fabrication process with AlGaN/GaN HEMT, making it a perfect diode for monolithic microwave integrated circuit (MMIC) application. Standalone AlGaN/GaN FESBD also has

AlGaN/GaN heterostructure is usually grown on foreign substrates such as sapphire, SiC, or Si by MOCVD or MBE. In order to achieve high blocking voltage, low leakage and low on-state resistance at the same time, the epitaxial structure needs to be carefully designed. Several growth techniques have been reported to improve the device performance of AlGaN/GaN

significant improvement of performance compared to Si and GaAs.

lower cost than GaN vertical SBD on freestanding substrate.

Figure 5. Band structure of the AlGaN/GaN heterostructure.

4.1. AlGaN/GaN substrate growth and epitaxial structure optimization

Guard ring formed by ion implantation is also a very effective technique for edge termination: a high resistivity layer can be formed on the surface and help spreading electrical field under reverse bias. There are two types of implantation ion: p-type dopant or noble gas. Zhang et al. reported a p type guard ring by ion implantation of Mg at the edge of the Schottky contact followed by annealing [48]. A high breakdown voltage of ~700 V was achieved on vertical SBD structure with a 75 μm diameter circular Pt/Ti/Au Schottky contact. Laroche et al. reported simulation of multiple p type guard rings with 1 μm, and 5 μm spacing, and found a theoretical breakdown voltage of 700 V with 1 μm spacing, and the breakdown voltage did not further improve when multiple guard rings were applied [49]. Ozbek et al. reported that ion implantation of Ar can greatly improve the breakdown voltage of vertical GaN SBD [50, 51]. Simulation and experiment were carried out to analyze breakdown voltage versus length of implantation region. It was found that 50 μm is the optimum length, leading to a breakdown voltage of 1700 V, about four times higher than unterminated SBD.

Besides guard rings, ion implantation can also be used in fabrication of GaN junction barrier Schottky diode (JBSD). JBSD has been successfully demonstrated in Si and SiC. For n type JBSD, a p+ /n grid structure is used instead of an intrinsic or n- layer in the drift region. Under forward bias, the p<sup>+</sup> region is not functioning, and the current flows through Schottky contact into the n channel. Under reverse bias, the depletion region spreads around the p<sup>+</sup> well and pinch off the n channel, thus suppresses premature breakdown and excessive leakage current. The p<sup>+</sup> well spacing and depth are important for best JBSD performance. Schematic of p<sup>+</sup> well JBSD is shown in Figure 4a. Zhang et al. fabricated GaN JBSD using both p+ well on n channel and n<sup>+</sup> well on p channel, by ion implantation of Mg and Si into n-GaN and p-GaN respectively [52]. Both types of devices has breakdown voltages of 500 V- 600 V, and the leakage current was reduced 100-fold than conventional SBD fabricated without grid structure. The forward characteristics of the n type JBSD is much better than its p type counterpart. Ion implantation is not the only method to fabricate JBSD. Li et al. demonstrated trench JBSD, which eliminate the ion implantation step [53]. The schematics of the trench JBSD is shown in Figure 4b. The major difference between trench JBSD and regular JBSD is the formation of the

Figure 4. Schematics of (a) JBSD and (b) trench JBSD: the gray region is Schottky contact, black region is ohmic contact, and the dotted region is p<sup>+</sup> doped GaN.

p+ /n junction. In trench JBSD, a p+ epitaxy layer is firstly deposited, followed by a selective etching down to nGaN substrate to form trench structure. The Schottky contact is then deposited on the trench. Under reverse bias, the depletion region spread laterally from the p+/n interface and pinch off the Schottky barrier. The study of Li et al. shows about 20 times reduction in the leakage current compared to traditional SBD.

## 4. AlGaN/GaN field effect SBDs

lead to an optimum dielectric layer thickness; Optimum dielectric layer thickness is related with dielectric permittivity [47]. In summary, both simulation and experiment results demonstrated that addition device structures such as dielectric passivation layer, FRM and FP, can contribute to

Guard ring formed by ion implantation is also a very effective technique for edge termination: a high resistivity layer can be formed on the surface and help spreading electrical field under reverse bias. There are two types of implantation ion: p-type dopant or noble gas. Zhang et al. reported a p type guard ring by ion implantation of Mg at the edge of the Schottky contact followed by annealing [48]. A high breakdown voltage of ~700 V was achieved on vertical SBD structure with a 75 μm diameter circular Pt/Ti/Au Schottky contact. Laroche et al. reported simulation of multiple p type guard rings with 1 μm, and 5 μm spacing, and found a theoretical breakdown voltage of 700 V with 1 μm spacing, and the breakdown voltage did not further improve when multiple guard rings were applied [49]. Ozbek et al. reported that ion implantation of Ar can greatly improve the breakdown voltage of vertical GaN SBD [50, 51]. Simulation and experiment were carried out to analyze breakdown voltage versus length of implantation region. It was found that 50 μm is the optimum length, leading to a breakdown

Besides guard rings, ion implantation can also be used in fabrication of GaN junction barrier Schottky diode (JBSD). JBSD has been successfully demonstrated in Si and SiC. For n type

forward bias, the p<sup>+</sup> region is not functioning, and the current flows through Schottky contact into the n channel. Under reverse bias, the depletion region spreads around the p<sup>+</sup> well and pinch off the n channel, thus suppresses premature breakdown and excessive leakage current. The p<sup>+</sup> well spacing and depth are important for best JBSD performance. Schematic of p<sup>+</sup> well JBSD is shown in Figure 4a. Zhang et al. fabricated GaN JBSD using both p+ well on n channel and n<sup>+</sup> well on p channel, by ion implantation of Mg and Si into n-GaN and p-GaN respectively [52]. Both types of devices has breakdown voltages of 500 V- 600 V, and the leakage current was reduced 100-fold than conventional SBD fabricated without grid structure. The forward characteristics of the n type JBSD is much better than its p type counterpart. Ion implantation is not the only method to fabricate JBSD. Li et al. demonstrated trench JBSD, which eliminate the ion implantation step [53]. The schematics of the trench JBSD is shown in Figure 4b. The major difference between trench JBSD and regular JBSD is the formation of the

Figure 4. Schematics of (a) JBSD and (b) trench JBSD: the gray region is Schottky contact, black region is ohmic contact,

/n grid structure is used instead of an intrinsic or n- layer in the drift region. Under

voltage of 1700 V, about four times higher than unterminated SBD.

112 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

better GaN SBD performance.

JBSD, a p+

and the dotted region is p<sup>+</sup> doped GaN.

Spontaneous and piezoelectric polarization can result in built-in electric field in AlGaN/GaN heterostructure. Band bending and alignment of Fermi level in AlGaN and GaN forms a twodimensional electron gas (2DEG) at the interface. Figure 5 shows band diagram of the AlGaN/ GaN heterostructure. Because of the high carrier mobility of the 2DEG, low on-state resistance can be achieved for device utilizing AlGaN/GaN heterostructure. GaN based High-electron mobility transistor (HEMT) has been developed for power and RF applications and showed significant improvement of performance compared to Si and GaAs.

The AlGaN/GaN heterostructure can also be used in SBD. The concept of GaN field effect Schottky barrier diode (FESBD) was first brought up by Yoshida et al. in 2004 [54], with device schematics shown in Figure 6. AlGaN/GaN FESBD shares the same epitaxial structure and device fabrication process with AlGaN/GaN HEMT, making it a perfect diode for monolithic microwave integrated circuit (MMIC) application. Standalone AlGaN/GaN FESBD also has lower cost than GaN vertical SBD on freestanding substrate.

#### 4.1. AlGaN/GaN substrate growth and epitaxial structure optimization

AlGaN/GaN heterostructure is usually grown on foreign substrates such as sapphire, SiC, or Si by MOCVD or MBE. In order to achieve high blocking voltage, low leakage and low on-state resistance at the same time, the epitaxial structure needs to be carefully designed. Several growth techniques have been reported to improve the device performance of AlGaN/GaN FESBD.

Figure 5. Band structure of the AlGaN/GaN heterostructure.

Figure 6. Schematics of AlGaN/GaN FESBD.

A buffer layer structure under the GaN channel layer is crucial because it can reduce the screw dislocation density thus can help on reducing reverse leakage and prevent premature breakdown. Lee et al. systematically investigated the electrical characteristics of the FEBSD with and without a composite buffer layer [55]. The buffer layer consisted of an 800 nm of AlN followed by a 30 nm of AlGaN. The breakdown voltage of the FEBSD with buffer layer was 3489 V, while that of FEBSD without buffer layer was only 382 V.

Similar to GaN SBD, a cap layer can help on the reverse leakage and breakdown voltage in FEBSD. Kamada et al. reported LTG GaN cap layer for edge termination in FEBSD [56]. A 20 nm LTG GaN, a 25 nm AlGaN and a 1 μm GaN were grown on Si substrate by MOCVD. A selective dry etching removed part of the GaN cap layer and exposed AlGaN layer for Schottky contact deposition. The FESBD with the GaN cap layer for edge termination has three order of magnitude lower leakage current than the traditional FESBD. A cap layer on top of barrier layer can also lower the barrier height and the turn-on voltage for better forward characteristics in FEBSD. Lee et al. developed a method to in situ grow a SiCN cap layer on top of the AlGaN barrier [57]. A 2 nm SiCN cap, a 25 nm AlGaN, and a 3 μm GaN were grown on sapphire substrate by MOCVD. It was found that forward current, reverse leakage and breakdown voltage of FESBD with SiCN cap layer were much better than regular FESBD.

pinch off the device under reverse bias. A breakdown voltage of over 400 V was achieved. Park et al. adopted the concept and made improvement by introducing different Schottky and Ohmic contact patterns [58]. Schematics of the device was shown in Figure 7b. The on-state resistance was reduced by 25–75% at the cost of up to 3 orders of magnitude increment in leakage current, improved from 5 to 7 orders of magnitude increment with Yoshida's original design that has no pattern. However, the leakage current of the FESBD with dual Schottky anode design cannot be reduced to the same level of regular FESBD with only high Schottky barrier no matter how the contact pattern is optimized because of its normally-on nature.

Figure 8. Schematics of AlGaN/GaN FESBD with SOC anode by (a) CF4 plasma surface treatment (b) recessed Schottky: the gray region is Schottky contact, black region is ohmic contact, dotted region is plasma-treated AlGaN, and dotted line

Figure 7. Schematics of AlGaN/GaN FESBD with dual Schottky anode: the gray region is Schottky contact, black region is

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ohmic contact, and dotted line is 2DEG.

is 2DEG.

To further reduce the turn-on voltage and suppress the reverse leakage, Schottky-ohmic combined (SOC) anode technique was introduced. Note that the technique can only be applied to depletion mode (normally-off) FESBD as the device will be shorted by the 2DEG under reverse bias if it is normally-on. As we know, there are two common methods to fabricate depletion mode HEMT: surface treatment and recessed gate. Both methods are also applicable to FESBD, with recessed gate changed to recessed Schottky. Takatani et al. [59] and Chen et al. [60] introduced SOC FESBD with surface treatment. CF4 plasma was applied to the Schottky region of the FESBD to achieve normally-off mode, as the 2DEG under the Schottky region was depleted by negative fluorine ions. The device structure is illustrated in Figure 8a. The technique effectively improved the forward characteristics of the device and did not degrade reverse leakage and breakdown voltage [60]. SOC FESBD with recessed Schottky was also reported by multiple research groups. The device structure is illustrated in Figure 8b. Lee et al.

#### 4.2. FESBD device fabrication and device structure optimization

Because of the 2DEG feature, the device structure optimization for FESBD is not exactly the same as GaN SBD. Some structures that are widely used in GaN SBD and has been discussed in Section 3, such as dielectric passivation, FMR and FP, can also be used in FESBD, while some structures such as dual Schottky anode, Schottky-ohmic combined anode, recessed Schottky anode, gated edge termination and MIS-gated hybrid anode are unique to FESBD. The unique techniques that are discussed in the following paragraphs of this section share the same mechanism: Current flow path is optimized in the forward regime, while reverse blocking capability is not compromised by depletion of the 2DEG channel.

Yoshida et al. first introduced dual Schottky anode concept [54]. The schematics of the dual Schottky anode is shown in Figure 7a. A low Schottky barrier metal Al/Ti was used as lo Schottky barrier metal for better on-voltage, while a high Schottky barrier metal Pt was used to

Figure 7. Schematics of AlGaN/GaN FESBD with dual Schottky anode: the gray region is Schottky contact, black region is ohmic contact, and dotted line is 2DEG.

A buffer layer structure under the GaN channel layer is crucial because it can reduce the screw dislocation density thus can help on reducing reverse leakage and prevent premature breakdown. Lee et al. systematically investigated the electrical characteristics of the FEBSD with and without a composite buffer layer [55]. The buffer layer consisted of an 800 nm of AlN followed by a 30 nm of AlGaN. The breakdown voltage of the FEBSD with buffer layer was 3489 V,

Similar to GaN SBD, a cap layer can help on the reverse leakage and breakdown voltage in FEBSD. Kamada et al. reported LTG GaN cap layer for edge termination in FEBSD [56]. A 20 nm LTG GaN, a 25 nm AlGaN and a 1 μm GaN were grown on Si substrate by MOCVD. A selective dry etching removed part of the GaN cap layer and exposed AlGaN layer for Schottky contact deposition. The FESBD with the GaN cap layer for edge termination has three order of magnitude lower leakage current than the traditional FESBD. A cap layer on top of barrier layer can also lower the barrier height and the turn-on voltage for better forward characteristics in FEBSD. Lee et al. developed a method to in situ grow a SiCN cap layer on top of the AlGaN barrier [57]. A 2 nm SiCN cap, a 25 nm AlGaN, and a 3 μm GaN were grown on sapphire substrate by MOCVD. It was found that forward current, reverse leakage and breakdown voltage of FESBD with SiCN cap layer were much better than regular FESBD.

Because of the 2DEG feature, the device structure optimization for FESBD is not exactly the same as GaN SBD. Some structures that are widely used in GaN SBD and has been discussed in Section 3, such as dielectric passivation, FMR and FP, can also be used in FESBD, while some structures such as dual Schottky anode, Schottky-ohmic combined anode, recessed Schottky anode, gated edge termination and MIS-gated hybrid anode are unique to FESBD. The unique techniques that are discussed in the following paragraphs of this section share the same mechanism: Current flow path is optimized in the forward regime, while reverse blocking

Yoshida et al. first introduced dual Schottky anode concept [54]. The schematics of the dual Schottky anode is shown in Figure 7a. A low Schottky barrier metal Al/Ti was used as lo Schottky barrier metal for better on-voltage, while a high Schottky barrier metal Pt was used to

while that of FEBSD without buffer layer was only 382 V.

114 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Figure 6. Schematics of AlGaN/GaN FESBD.

4.2. FESBD device fabrication and device structure optimization

capability is not compromised by depletion of the 2DEG channel.

Figure 8. Schematics of AlGaN/GaN FESBD with SOC anode by (a) CF4 plasma surface treatment (b) recessed Schottky: the gray region is Schottky contact, black region is ohmic contact, dotted region is plasma-treated AlGaN, and dotted line is 2DEG.

pinch off the device under reverse bias. A breakdown voltage of over 400 V was achieved. Park et al. adopted the concept and made improvement by introducing different Schottky and Ohmic contact patterns [58]. Schematics of the device was shown in Figure 7b. The on-state resistance was reduced by 25–75% at the cost of up to 3 orders of magnitude increment in leakage current, improved from 5 to 7 orders of magnitude increment with Yoshida's original design that has no pattern. However, the leakage current of the FESBD with dual Schottky anode design cannot be reduced to the same level of regular FESBD with only high Schottky barrier no matter how the contact pattern is optimized because of its normally-on nature.

To further reduce the turn-on voltage and suppress the reverse leakage, Schottky-ohmic combined (SOC) anode technique was introduced. Note that the technique can only be applied to depletion mode (normally-off) FESBD as the device will be shorted by the 2DEG under reverse bias if it is normally-on. As we know, there are two common methods to fabricate depletion mode HEMT: surface treatment and recessed gate. Both methods are also applicable to FESBD, with recessed gate changed to recessed Schottky. Takatani et al. [59] and Chen et al. [60] introduced SOC FESBD with surface treatment. CF4 plasma was applied to the Schottky region of the FESBD to achieve normally-off mode, as the 2DEG under the Schottky region was depleted by negative fluorine ions. The device structure is illustrated in Figure 8a. The technique effectively improved the forward characteristics of the device and did not degrade reverse leakage and breakdown voltage [60]. SOC FESBD with recessed Schottky was also reported by multiple research groups. The device structure is illustrated in Figure 8b. Lee et al.

material limit. However, there are still challenges ahead for the GaN based Schottky diodes: (a) Improvement of the material quality is desired. (b) Novel epitaxial and device structures leveraging state-of-art growth and fabrication techniques are needed. (c) Significant cost reduction from substrate and fabrication is crucial. With continuous effort from academia and industry, GaN based Schottky diodes will mature and be successful commercialized in a

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[1] Wang Y. Fabrication and characterization of gallium nitride based diodes [Ph.D disserta-

[2] Zhang A. Gallium nitride-based electronic devices [Ph.D dissertation]. In: University of

[3] Zhou Y. Bulk gallium nitride based electronic devices: Schottky diodes, Schottky-type ultraviolet photodetectors and metal-oxide-semiconductor capacitors [Ph.D dissertation].

[4] Kaminski N, Hilt O. SiC and GaN Devices–Competition or Coexistence?, 2012 7th International Conference on Integrated Power Electronics Systems. Nuremberg: CIPS; 2012.

[5] Hacke P, Detchprohm T, Hiramatsu K, Sawaki N. Schottky barrier on n-type GaN grown by hydride vapor phase epitaxy. Applied Physics Letters. 1993;63:2676. DOI: 10.1063/

[6] Khan MRH, Detchprohm T, Hacke P, Hiramatsu K, Sawaki N. The barrier height and interface effect of Au-n-GaN Schottky diode. Journal of Physics D: Applied Physics. 1995;

[7] Guo JD, Feng MS, Guo RJ, Pan FM, Chang CY. Study of Schottky barriers on n-type GaN grown by low-pressure metalorganic chemical vapor deposition. Applied Physics Letters.

[8] Wang L, Nathan MI, Lim T-H, Khan MA, Chen Q. High barrier height GaN Schottky diodes: Pt/GaN and Pd/GaN. Applied Physics Letters. 1996;68:1267. DOI: 10.1063/

foreseeable future.

Author details

Address all correspondence to: yaqi.wang@outlook.com

28:1169-1174. DOI: 10.1088/0022-3727/28/6/021

1995;67:2657. DOI: 10.1063/1.114327

Luminus Devices Inc., Sunnyvale, USA

tion]. Auburn University; 2011

In: Auburn University. 2007

Yaqi Wang

References

Florida. 2001

pp. 1-11

1.110417

1.115948

Figure 9. Schematics of AlGaN/GaN FESBD with (a) GET (b) fully recessed Schottky (c) MIS-gated hybrid anode: the gray region is Schottky contact, black region is ohmic contact, crossed region is gate dielectric, and dotted line is 2DEG.

compared it with conventional normally-on FESBD and normally-off FESBD with recessed Schottky but no SOC structure [61]. It was clearly demonstrated that the SOC FESBD with recessed Schottky is far superior to conventional FESBDs in turn-on voltage without breakdown voltage degradation. Recess depth is a very important parameter of SOC FESBD with recessed Schottky. Lee et al. did a comprehensive study of recess depth [62]. An optimized recess depth was found in between half and full thickness of AlGaN layer.

Lenci et al. introduced gated edge termination (GET) as illustrated in Figure 9a [63]. A thin dielectric layer was inserted underneath the recessed Schottky contact and formed an MIS gate structure. Under reverse bias, the 2DEG below the gate was pinched off. The reverse leakage current can be significantly reduced by the dielectric layer. The marginal extend-out of the Schottky metal on the dielectric layer formed a FP and reduced the electric field crowding. Bahat-Treidel et al. introduced a fully recessed Schottky anode with a slanted FP, which can significantly reduce the turn-on voltage because of the direct contact of Schottky anode to the 2DEG [64]. The schematics of the device structure is shown in Figure 9b. Yao et al. further investigated the current transport mechanism of the full recessed Schottky FESBD and found it was thermal field emission (TFE) instead of TE [65]. The GET and full recessed is compatible with other device optimization techniques. Hu et al. [66] and Zhu et al. [67] combined a 2nd FP technique with GET and fully recessed Schottky, respectively. The dual FP structure improved the breakdown voltage of FESBD with fully recessed Schottky.

Zhou et al. further optimized the device structure by combining the techniques above, and named it MIS-Gated hybrid anode [68]. The schematics of the device structure is shown in Figure 9c. It has an SOC anode with GET recessed Schottky, and fully recessed ohmic in direct contact with 2DEG. It also has a fully recessed ohmic contact on the cathode side. High breakdown voltage over 1.1 kV and leakage current as low as 10 μA/mm were achieved.

#### 5. Summary

In this chapter, we gave a broad review of the GaN based Schottky diodes. The competitive position of GaN among the WBG materials in the high temperature, high frequency and high voltage rectifying applications was discussed first, followed with Schottky contact to GaN, and the development of GaN SBD and AlGaN/GaN FESBD in the last two decades. A lot of progress was made; and the best performing GaN based Schottky diode got close to SiC material limit. However, there are still challenges ahead for the GaN based Schottky diodes: (a) Improvement of the material quality is desired. (b) Novel epitaxial and device structures leveraging state-of-art growth and fabrication techniques are needed. (c) Significant cost reduction from substrate and fabrication is crucial. With continuous effort from academia and industry, GaN based Schottky diodes will mature and be successful commercialized in a foreseeable future.

### Author details

Yaqi Wang

compared it with conventional normally-on FESBD and normally-off FESBD with recessed Schottky but no SOC structure [61]. It was clearly demonstrated that the SOC FESBD with recessed Schottky is far superior to conventional FESBDs in turn-on voltage without breakdown voltage degradation. Recess depth is a very important parameter of SOC FESBD with recessed Schottky. Lee et al. did a comprehensive study of recess depth [62]. An optimized

Figure 9. Schematics of AlGaN/GaN FESBD with (a) GET (b) fully recessed Schottky (c) MIS-gated hybrid anode: the gray region is Schottky contact, black region is ohmic contact, crossed region is gate dielectric, and dotted line is 2DEG.

Lenci et al. introduced gated edge termination (GET) as illustrated in Figure 9a [63]. A thin dielectric layer was inserted underneath the recessed Schottky contact and formed an MIS gate structure. Under reverse bias, the 2DEG below the gate was pinched off. The reverse leakage current can be significantly reduced by the dielectric layer. The marginal extend-out of the Schottky metal on the dielectric layer formed a FP and reduced the electric field crowding. Bahat-Treidel et al. introduced a fully recessed Schottky anode with a slanted FP, which can significantly reduce the turn-on voltage because of the direct contact of Schottky anode to the 2DEG [64]. The schematics of the device structure is shown in Figure 9b. Yao et al. further investigated the current transport mechanism of the full recessed Schottky FESBD and found it was thermal field emission (TFE) instead of TE [65]. The GET and full recessed is compatible with other device optimization techniques. Hu et al. [66] and Zhu et al. [67] combined a 2nd FP technique with GET and fully recessed Schottky, respectively. The dual FP structure improved

Zhou et al. further optimized the device structure by combining the techniques above, and named it MIS-Gated hybrid anode [68]. The schematics of the device structure is shown in Figure 9c. It has an SOC anode with GET recessed Schottky, and fully recessed ohmic in direct contact with 2DEG. It also has a fully recessed ohmic contact on the cathode side. High breakdown voltage over 1.1 kV and leakage current as low as 10 μA/mm were achieved.

In this chapter, we gave a broad review of the GaN based Schottky diodes. The competitive position of GaN among the WBG materials in the high temperature, high frequency and high voltage rectifying applications was discussed first, followed with Schottky contact to GaN, and the development of GaN SBD and AlGaN/GaN FESBD in the last two decades. A lot of progress was made; and the best performing GaN based Schottky diode got close to SiC

recess depth was found in between half and full thickness of AlGaN layer.

116 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

the breakdown voltage of FESBD with fully recessed Schottky.

5. Summary

Address all correspondence to: yaqi.wang@outlook.com

Luminus Devices Inc., Sunnyvale, USA

#### References


[9] Kalinina EV, Kuznetsov NI, Dmitriev VA, Irvine KG, Carter CH. Schottky barriers on n-GaN grown on SiC. Journal of Electronic Materials. 1996;25:831. DOI: 10.1007/BF02666644

[22] Chen GL, Chang FC, Shen KC, Ou J, Chen WH, Lee MC, Chen WK, Jou MJ, Huang CN. Thermal stability study of Ni/Ta n-GaN Schottky contacts. Applied Physics Letters. 2002;

GaN-Based Schottky Diode

119

http://dx.doi.org/10.5772/intechopen.77024

[23] Sheu JK, Su YK, Chi GC, Jou MJ, Chang CM. Effects of thermal annealing on the indium tin oxide Schottky contacts of n-GaN. Applied Physics Letters. 1998;72:3317. DOI: 10.1063/

[24] Tongay S, Lemaitre M, Schumann T, Berke K, Appleton BR, Gila B, Hebard AF. Graphene/ GaN Schottky diodes: Stability at elevated temperatures. Applied Physics Letters. 2011;99:

[25] Kim S, Seo TH, Kim MJ, Song KM, Suh E, Kim H. Graphene–GaN Schottky diodes. Nano

[26] Qiao D, Yu LS, Lau SS, Redwing JM, Lin JY, Jiang HX. Dependence of Ni/AlGaN Schottky barrier height on Al mole fraction. Journal of Applied Physics. 2000;87:801. DOI: 10.1063/

[27] Lv Y, Lin Z, Corrigan TD, Zhao J, Cao Z, Meng L, Luan C, Wang Z, Chen H. Extraction of AlGaN/GaN heterostructure Schottky diode barrier heights from forward current-voltage characteristics. Journal of Applied Physics. 2011;109:074512. DOI: 10.1063/1.3569594

[28] Shin J, Park J, Jang S, Jang T, Kim KS. Metal induced inhomogeneous Schottky barrier height in AlGaN/GaN Schottky diode. Applied Physics Letters. 2013;102:243505. DOI:

[29] Ao J, Naoi Y, Ohno Y. Thermally stable TiN Schottky contact on AlGaN/GaN heterostructure. Vacuum. 2013;87:150-154. DOI: 10.1016/j.vacuum.2012.02.038

[30] Li L, Kishi A, Liu Q, Itai Y, Fujihara R, Ohno Y, Ao J. GaN Schottky barrier diode with TiN electrode for microwave rectification. IEEE Journal of the Electron Devices Society. 2014;2:

[31] Phark S, Kim H, Song KM, Kang PG, Shin HS, Kim D. Current transport in Pt Schottky contacts to a-plane n-type GaN. Journal of Physics D: Applied Physics. 2010;43:165102.

[32] Yamada H, Chonan H, Takahashi T, Shimizu M. Electrical properties of Ni/n-GaN Schottky diodes on freestanding m-plane GaN substrates. Applied Physics Express. 2017;

[33] Yamada H, Chonan H, Takahashi T, Shimizu M. Comparison of electrical properties of Ni/n-GaN Schottky diodes on c-plane and m-plane GaN substrates. Physica Status Solidi A: Applications and Materials Science. 2017;214:1700362. DOI: 10.1002/pssa.201700362

[34] Tanaka A, Ando Y, Nagamatsu K, Deki M, Cheong H, Ousmane B, Kushimoto M, Nitta S, Honda Y, Amano H. M-plane GaN Schottky barrier diodes fabricated with MOVPE layer

Research. 2015;8(4):1327-1338. DOI: 10.1007/s12274-014-0624-7

80:595. DOI: 10.1063/1.1425455

102102. DOI: 10.1063/1.3628315

1.121636

1.371944

10.1063/1.4811756

168. DOI: 10.1109/JEDS.2014.2346395

DOI: 10.1088/0022-3727/43/16/165102

10:041001. DOI: 10.7567/APEX.10.041001


[22] Chen GL, Chang FC, Shen KC, Ou J, Chen WH, Lee MC, Chen WK, Jou MJ, Huang CN. Thermal stability study of Ni/Ta n-GaN Schottky contacts. Applied Physics Letters. 2002; 80:595. DOI: 10.1063/1.1425455

[9] Kalinina EV, Kuznetsov NI, Dmitriev VA, Irvine KG, Carter CH. Schottky barriers on n-GaN grown on SiC. Journal of Electronic Materials. 1996;25:831. DOI: 10.1007/BF02666644

[10] Ping AT, Schmitz AC, Khan MA, Adesida I. Characterization of Pd Schottky barrier on n-

[11] Schmitz AC, Ping AT, Asif Khan M, Chen Q, Yang JW, Adesida I. Schottky barrier properties of various metals on n-type GaN. Semiconductor Science and Technology.

[12] Liu QZ, Yu LS, Deng F, Lau SS, Redwing JM. Ni and Ni silicide Schottky contacts on n-

[13] Liu QZ, Lau SS. A review of the metal–GaN contact technology. Solid-State Electronics.

[14] Hsu JWP, Manfra MJ, Lang DV, Richter S, Chu SNG, Sergent AM, Kleiman RN, Pfeiffer LN, Molnar RJ. Inhomogeneous spatial distribution of reverse bias leakage in GaN

[15] Miller EJ, Schaadt DM, Yu ET, Poblenz C, Elsass C, Speck JS. Reduction of reverse-bias leakage current in Schottky diodes on GaN grown by molecular-beam epitaxy using surface modification with an atomic force microscope. Journal of Applied Physics. 2002;

[16] Sang L, Ren B, Sumiya M, Liao M, Koide Y, Tanaka A, Cho Y, Harada Y, Nabatame T, Sekiguchi T, Usami S, Honda Y, Amano H. Initial leakage current paths in the verticaltype GaN-on-GaN Schottky barrier diodes. Applied Physics Letters. 2017;111:122102.

[17] Cao Y, Chu R, Li R, Chen M, Chang R, Hughes B. High-voltage vertical GaN Schottky diode enabled by low-carbon metal-organic chemical vapor deposition growth. Applied

[18] Reddy P, Sarkar B, Kaess F, Gerhold M, Kohn E, Collazo R, Sitar Z. Defect-free Ni/GaN Schottky barrier behavior with high temperature stability. Applied Physics Letters. 2017;

[19] Guo JD, Pan FM, Feng MS, Guo RJ, Chou PF, Chang CY. Schottky contact and the thermal stability of Ni on n-type GaN. Journal of Applied Physics. 1996;80:1623. DOI: 10.1063/

[20] Schmitz AC, Ping AT, Khan MA, Chen Q, Yang JW, Adesida I. High temperature characteristics of Pd Schottky contacts on n-type GaN. Electronics Letters. 1996;32:1832-1833.

[21] Liu QZ, Yu LS, Lau SS, Redwing JM, Perkins NR, Kuech TF. Thermally stable PtSi Schottky contact on n-GaN. Applied Physics Letters. 1997;70:1275. DOI: 10.1063/1.118551

Schottky diodes. Applied Physics Letters. 2001;78:1685. DOI: 10.1063/1.1356450

type GaN. Electronics Letters. 1996:68. DOI: 10.1049/el:19960029

GaN. Applied Physics Letters. 1998;84:881. DOI: 10.1063/1.368151

1996;11:1464-1467. DOI: 10.1088/0268-1242/11/10/002

118 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

1998;42:677. DOI: 10.1016/S0038-1101(98)00099-9

Physics Letters. 2016;108:062103. DOI: 10.1063/1.4941814

91:9821. DOI: 10.1063/1.1478793

110:011603. DOI: 10.1063/1.4973762

DOI: 10.1049/el:19961191

DOI: 10.1063/1.4994627

1.363822


on several off-angle m-plane GaN substrates. Physica Status Solidi A: Applications and Materials Science. 2017;214:1700645. DOI: 10.1002/pssa.201700645

[47] Lei Y, Shi H, Lu H, Chen D, Zhang R, Zheng Y. Field plate engineering for GaN-based Schottky barrier diodes. Journal of Semiconductors. 2013;34:054007. DOI: 10.1088/1674-

GaN-Based Schottky Diode

121

http://dx.doi.org/10.5772/intechopen.77024

[48] Zhang AP, Johnson JW, Luo B, Ren F, Pearton SJ, Park SS, Park YJ, Chyi J-I. Vertical and lateral GaN rectifiers on free-standing GaN substrates. Applied Physics Letters. 2001;79:

[49] Laroche JR, Ren F, Baik KW, Pearton SJ, Shelton BS, Peres B. Design of Edge Termination for GaN power Schottky diodes. Journal of Electronic Materials. 2005;34:370-374. DOI:

[50] Ozbek AM, Baliga BJ. Planar nearly ideal edge-termination technique for GaN devices.

[51] Ozbek AM, Baliga BJ. Finite-zone argon implant edge termination for high-voltage GaN Schottky rectifiers. IEEE Transactions on Electron Devices. 2011;32:1361. DOI: 10.1109/

[52] Zhang Y, Liu Z, Tadjer MJ, Sun M, Piedra D, Hatem C, Anderson TJ, Luna LE, Nath A, Koehler AD, Okumura H. Vertical GaN junction barrier Schottky rectifiers by selective ion implantation. IEEE Electron Device Letters. 2017;38:1097. DOI: 10.1109/LED.2017.2720689

[53] Li W, Nomoto K, Pilla M, Pan M, Gao X, Jena D, Xing HG. Design and realization of GaN trench junction-barrier-Schottky-diodes. IEEE Transactions on Electron Devices. 2017;64:

[54] Yoshida S, Ikeda N, Li J, Wada T, Takehara H. A New GaN Based Field Effect Schottky Barrier Diode with a Very Low on-Voltage Operation, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs. Japan: Kitakyushu;

[55] Lee GY, Liu HH, Chyi JI. High-performance AlGaN/GaN Schottky diodes with an AlGaN/ AlN buffer layer. IEEE Electron Device Letters. 2011;32:1519. DOI: 10.1109/LED.2011.2164610

[56] Kamada A, Matsubayashi K, Nakagawa A, Terada Y, Egawa T. High-voltage AlGaN/GaN Schottky barrier diodes on Si substrate with low-temperature gan cap layer for edge termination. 2008 20th International Symposium On Power Semiconductor Devices and

[57] Lee JH, Jeong JH, Lee JH. Enhanced electrical characteristics of AlGaN-based SBD with in situ deposited silicon carbon nitride cap layer. IEEE Electron Device Letters. 2012;33:492.

[58] Park K, Park Y, Hwang S, Jeon W, Lee J. 1kV AlGaN/GaN Power SBDs with Reduced on Resistances. In: 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs. San Diego: CA; 2011. pp. 223-226. DOI: 10.1109/ISPSD.2011.5890831 [59] Takatani K, Nozawa T, Oka T, Kawamura H, Sakuno K. AlGaN/GaN Schottky-ohmic combined anode field effect diode with fluoride-based plasma treatment. Electronics

IC's, Orlando, FL; 2008. pp. 225-228. DOI: 10.1109/ISPSD.2008.4538939

IEEE Electron Device Letters. 2011;32:300. DOI: 10.1109/LED.2010.2095825

4926/34/5/054007

1555. DOI: 10.1063/1.1400771

10.1007/s11664-005-0113-6

1635. DOI: 10.1109/TED.2017.2662702

DOI: 10.1109/LED.2012.2182671

2004. pp. 323-326. DOI: 10.1109/WCT.2004.240038

Letters. 2008;44:320-321. DOI: 10.1049/el:20083428

LED.2011.2162221


[47] Lei Y, Shi H, Lu H, Chen D, Zhang R, Zheng Y. Field plate engineering for GaN-based Schottky barrier diodes. Journal of Semiconductors. 2013;34:054007. DOI: 10.1088/1674- 4926/34/5/054007

on several off-angle m-plane GaN substrates. Physica Status Solidi A: Applications and

[35] Sheu JK, Lee ML, Lai WC. Effect of low-temperature-grown GaN cap layer on reduced leakage current of GaN Schottky diodes. Applied Physics Letters. 2005;86:052103. DOI:

[36] Lu H, Zhang R, Xiu X, Xie Z, Zheng Y, Li Z. Low leakage Schottky rectifiers fabricated on homoepitaxial GaN. Applied Physics Letters. 2007;91:172113. DOI: 10.1063/1.2795083 [37] Fu H, Huang X, Chen H, Lu Z, Baranowski I, Zhao Y. Ultra-low turn-on voltage and onresistance vertical GaN-on-GaN Schottky power diodes with high mobility double drift

[38] Cao Y, Chu R, Li R, Chen M, Williams AJ. Improved performance in vertical GaN Schottky diode assisted by AlGaN tunneling barrier. Applied Physics Letters. 2016;108:

[39] Bandić ZZ, Bridger PM, Piquette EC, McGill TC, Vaudo RP, Phanse VM, Redwing JM. High voltage (450 V) GaN Schottky rectifiers. Applied Physics Letters. 1999;74:1266. DOI:

[40] Cao XA, Cho H, Pearton SJ, Dang GT, Zhang AP, Ren F, Shul RJ, Zhang L, Hickman R, Van Hove JM. Depth and thermal stability of dry etch damage in GaN Schottky diodes.

[41] Cao XA, Pearton SJ, Dang GT, Zhang AP, Ren F, Van Hove JM. GaN n- and p-type Schottky diodes: Effect of dry etch damage. IEEE Transactions on Electron Devices. 2000;

[42] Zhu TG, Lambert DJH, Shelton BS, Wong MM, Chowdhury U, Dupuis RD. High-voltage mesa-structure GaN Schottky rectifiers processed by dry and wet etching. Applied Phys-

[43] Spradlin J, Dogan S, Mikkelson M, Huang D, He L, Johnstone D, Morkoç H, Molnar RJ. Improvement of n-GaN Schottky diode rectifying characteristics using KOH etching.

[44] Lee S, Her J, Kim S, Ha M, Seo K, Choi Y, Han M. A New Vertical GaN Schottky Barrier Diode with Floating Metal Ring for High Breakdown Voltage, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs. Japan: Kitakyu-

[45] Baik KH, Irokawa Y, Ren F, Pearton SJ, Park SS, Park YJ. Design of junction termination structures for GaN Schottky power rectifiers. Solid-State Electronics. 2003;47:975. DOI:

[46] Kang BS, Ren F, Irokawa Y, Baik KW, Pearton SJ, Pan C-C, Chen G-T, Chyi J-I, Ko H-J, Lee H-Y. Temperature dependent characteristics of bulk GaN Schottky rectifiers on freestanding GaN substrates. Journal of Vacuum Science & Technology B. 2004;22:710. DOI:

layers. Applied Physics Letters. 2017;111:152102. DOI: 10.1063/1.4993201

Applied Physics Letters. 1999;75:232. DOI: 10.1063/1.124332

Applied Physics Letters. 2003;82:3556. DOI: 10.1063/1.1572532

shu; 2004. pp. 319-322. DOI: 10.1109/WCT.2004.240037

ics Letters. 2000;77:2918. DOI: 10.1063/1.1322050

Materials Science. 2017;214:1700645. DOI: 10.1002/pssa.201700645

120 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

10.1063/1.1861113

10.1063/1.123520

112101. DOI: 10.1063/1.4943946

47:1320. DOI: 10.1109/16.848271

10.1016/S0038-1101(02)00464-1

10.1116/1.1689303


[60] Chen W, Wong K-Y, Huang W, Chen KJ. High-performance AlGaN/GaN lateral fieldeffect rectifiers compatible with high electron mobility transistors. Applied Physics Letters. 2008;92:253501. DOI: 10.1063/1.2951615

**Chapter 7**

**Provisional chapter**

**Inductive Power Transfer for Electric Vehicles Using**

**Inductive Power Transfer for Electric Vehicles Using** 

This chapter will present the application of the GaN Gate Injection Transistor (GIT) in Inductive Power Transfer (IPT) for Electric Vehicles (EV). IPT provides significant benefits over conventional plug-in chargers but suffers from lower efficiency. A high frequency inverter using GaN GIT, which has low on-resistance and gate charge, is implemented to reduce switching and conduction loss, resulting in higher efficiency. Different gate drive strategies will be compared for driving the GaN GIT at high slew rates while ensuring cross-conduction protection. The switching characteristics of the GaN GIT are studied and the inverter is designed to ensure low switching losses, while keeping overshoot and slew rates under control. Experiment results presented will demonstrate that the system efficiency peaks at 95% at 100 kHz operation and 92% at 250 kHz operation for a coil gap

**Keywords:** gallium nitride, enhancement mode, wireless power transfer, inductive power transfer, electric vehicles, wide bandgap semiconductor application, gate driver

Development of battery technology and advancement of power electronics has allowed EVs to

From an environmental conservation perspective, EVs demonstrate benefits above conventional Internal Combustion Engines (ICE) vehicles. EVs provide the energy efficient solution to conventional ICE, with energy efficiencies going as high as 62% compared to 21% for internal combustion vehicles. Pollution due to EVs is lesser as it does not produce emission unlike ICE [1].

gain popularity in the recent years, with strong boost to greener environment.

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

DOI: 10.5772/intechopen.76057

**Gallium Nitride Power Transistors**

**Gallium Nitride Power Transistors**

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Cai Qingwei Aaron and Siek Liter

Cai Qingwei Aaron and Siek Liter

http://dx.doi.org/10.5772/intechopen.76057

of 80 mm at 2 kW output power.

**Abstract**

**1. Introduction**


#### **Inductive Power Transfer for Electric Vehicles Using Gallium Nitride Power Transistors Inductive Power Transfer for Electric Vehicles Using Gallium Nitride Power Transistors**

DOI: 10.5772/intechopen.76057

Cai Qingwei Aaron and Siek Liter Cai Qingwei Aaron and Siek Liter

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76057

#### **Abstract**

[60] Chen W, Wong K-Y, Huang W, Chen KJ. High-performance AlGaN/GaN lateral fieldeffect rectifiers compatible with high electron mobility transistors. Applied Physics Let-

[61] Lee JG, Park BR, Cho CH, Seo KS, Cha HY. Low turn-on voltage AlGaN/GaN-on-Si rectifier with gated Ohmic anode. IEEE Electron Device Letters. 2013;34:214-216. DOI:

[62] Lee HS, Jung DY, Park Y, Na J, Jang H-G, Lee HS, Jun C-H, Park J, Ryu SO, Ko SC, Nam ES. 0.34 VT AlGaN/GaN-on-Si large Schottky barrier diode with recessed dual anode metal. IEEE Electron Device Letters. 2015;36:1132-1134. DOI: 10.1109/LED.2015.2475178

[63] Lenci S, Jaeger BD, Carbonell L, Hu J, Mannaert G, Wellekens D, You S, Bakeroot B, Decoutere S. Au-free AlGaN/GaN power diode on 8-in Si substrate with gated edge termination. IEEE Electron Device Letters. 2013;34:1035-1037. DOI: 10.1109/LED.2013.22

[64] Bahat-Treidel E, Hilt O, Zhytnytska R, Wentzel A, Meliani C, Würfl J, Tränkle G. Fastswitching GaN-based lateral power Schottky barrier diodes with low onset voltage and strong reverse blocking. IEEE Electron Device Letters. 2012;33:357-359. DOI: 10.1109/

[65] Yao Y, Zhong J, Zheng Y, Yang F, Ni Y, He Z, Shen Z, Zhou G, Wang S, Zhang J, Li J. Current transport mechanism of AlGaN/GaN Schottky barrier diode with fully recessed Schottky anode. Japanese Journal of Applied Physics. 2014;54:011001. DOI: 10.7567/

[66] Hu J, Stoffels S, Lenci S, Bakeroot B, Jaeger BD, Hove MV, Ronchi N, Venegas R, Liang H, Zhao M, Groeseneken G, Decoutere S. Performance optimization of au-free lateral AlGaN/ GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate. IEEE Transactions on Electron Devices. 2016;63:997-1004. DOI: 10.1109/TED.2016.2515566

[67] Zhu M, Song B, Qi M, Hu Z, Nomoto K, Yan X, Cao Y, Johnson W, Kohn E, Jena D, Xing HG. 1.9-kV AlGaN/GaN lateral Schottky barrier diodes on silicon. IEEE Electron Device

[68] Zhou Q, Jin Y, Shi Y, Mou J, Bao X, Chen B, Zhang B. High reverse blocking and low onset voltage AlGaN/GaN-on-Si lateral power diode with MIS-gated hybrid anode. IEEE Elec-

Letters. 2015;36:375-377. DOI: 10.1109/LED.2015.2404309

tron Device Letters. 2015;36:660-662. DOI: 10.1109/LED.2015.2432171

ters. 2008;92:253501. DOI: 10.1063/1.2951615

122 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

10.1109/LED.2012.2235403

67933

LED.2011.2179281

jjap.54.011001

This chapter will present the application of the GaN Gate Injection Transistor (GIT) in Inductive Power Transfer (IPT) for Electric Vehicles (EV). IPT provides significant benefits over conventional plug-in chargers but suffers from lower efficiency. A high frequency inverter using GaN GIT, which has low on-resistance and gate charge, is implemented to reduce switching and conduction loss, resulting in higher efficiency. Different gate drive strategies will be compared for driving the GaN GIT at high slew rates while ensuring cross-conduction protection. The switching characteristics of the GaN GIT are studied and the inverter is designed to ensure low switching losses, while keeping overshoot and slew rates under control. Experiment results presented will demonstrate that the system efficiency peaks at 95% at 100 kHz operation and 92% at 250 kHz operation for a coil gap of 80 mm at 2 kW output power.

**Keywords:** gallium nitride, enhancement mode, wireless power transfer, inductive power transfer, electric vehicles, wide bandgap semiconductor application, gate driver

#### **1. Introduction**

Development of battery technology and advancement of power electronics has allowed EVs to gain popularity in the recent years, with strong boost to greener environment.

From an environmental conservation perspective, EVs demonstrate benefits above conventional Internal Combustion Engines (ICE) vehicles. EVs provide the energy efficient solution to conventional ICE, with energy efficiencies going as high as 62% compared to 21% for internal combustion vehicles. Pollution due to EVs is lesser as it does not produce emission unlike ICE [1].

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Another push for in EVs is the performance benefits. Electric motors have smoother operations and quieter than ICE, while having stronger accelerations, and lesser maintenance [2].

**2. Comparing gate drive methods for driving GaN GIT**

collapse [14].

OUT1.

using an external resistor.

Among the various enhancement mode GaN, Gate Injection Transistor (GIT) is one such technology, which is able to achieve normally off operation and high current driving capability [13]. The GaN GIT adopts p-GaN with recessed gate to achieve normally-off. The Hybrid Drain embedded in the GIT (HD-GIT) allows the device to overcome the current

Inductive Power Transfer for Electric Vehicles Using Gallium Nitride Power Transistors

http://dx.doi.org/10.5772/intechopen.76057

125

Since the GaN GIT is a normally-off device, it can be driven by conventional gate drive methods like the R-type gate drive is shown in **Figure 2a**. Resistor RA1 facilitates the charging dur-

To capitalize on the switching performance of the GaN device, the RC-type gate drive method [15] is recommended. This gate drive strategy allows the driving of the GaN GIT's gate at a higher voltage allowing faster slew rate. It produces negative gate voltage during turn off to

A single channel GaN GIT gate driver Integrated Circuit (IC) (AN34092B) utilizes a novel gate drive strategy to compare against existing gate drive methods is shown in [16]. The simplified gate drive circuit for the GaN GIT gate driver IC, AN34092B [17], is shown in **Figure 3a**. The gate driver IC has 3 output pins, namely OUT1, OUT2 and OUT3. OUT1's purpose is to charge the GaN power transistor during turn ON phase and discharging the speed-up capacitor C1 during turn off. When the device is fully turned on, C1 will block current through

OUT2 will continue to supply an adjustable DC current of 2.5–25 mA during conduction phase. Integrated within the IC is an adjustable current source, which is able to provide a constant current during turn ON, that is important for the conductivity modulation of the GaN GIT. It also provides a low impedance path using the active miller clamp function.

OUT3 is responsible for the discharge path by pulling the gate to the negative voltage VEE. The turn off slew rate can be controlled using resistor R2. Another integrated function is a charge pump to provide the negative voltage, VEE, during turn OFF, which is adjustable

ing turn on, while the path along RA2 forms the discharge path during turn off.

prevent false turn-on, while using a unipolar supply voltage.

**Figure 2.** Various gate drive methods: (a) the R-type and (b) the RC-type.

However, there are some battery related challenges facing EVs. Due to limited charge holding capacity of Li-ion batteries, the driving range of EVs are limited compared to ICE vehicles, being able to only travel one-third or half the distance of an ICE vehicle [2]. In addition, the battery charging time is time consuming, with a full charge taking about 4–8 h and fast charge about 30 min compared to 5 min for an ICE vehicle [3]. Despite having higher charge carrying capacity compared to other battery materials, Li-ion batteries for EVs are still very big and bulky. They are expensive and need replacement during the car's lifetime [3, 4].

Inductive Power Transfer (IPT) is the method of wirelessly transferring power. The system for static wireless charging is as shown in **Figure 1**. AC power is drawn from the grid into the system. This power is rectified using a diode bridge to supply a DC voltage. This is followed by a Power Factor Correction (PFC) stage to improve the power factor and step up the voltage to 380 V. The DC input voltage is supplied into an inverter, which converts it in high frequency AC so that power can be transmitted by primary coil to the secondary coil using IPT. The secondary coil will take in the HF AC power and rectify it using the SiC diode bridge into a DC voltage for vehicle charging. IPT for EVs provide a convenience and safety for the user [5, 6]. This system is weatherproof and difficult to vandalism like a plug-in station [4].

However, there are challenges facing wireless charging, such as low efficiency compared to plug-in chargers [4]. This is overcome by using wide bandgap semiconductor materials such as GaN, which is attracting attention for enabling high efficiency, high power density converters [7], rectifiers [8] and inverters [9, 10]. The material properties of GaN such as high critical field, electron mobility and saturation velocity [11] push the boundaries of power electronics performance such as efficiency, power density, reliability and cost [12].

The remainder of the chapter is organized as follows. Section 2 will compare various gate driving methods for driving the GaN GIT. This is followed by Section 3 which will explain the design considerations for apply the GaN GIT in WPT applications. Finally, Section 4 contains experiment results that demonstrate the advantages of using GaN in IPT.

**Figure 1.** Static wireless charging.

## **2. Comparing gate drive methods for driving GaN GIT**

Another push for in EVs is the performance benefits. Electric motors have smoother operations

However, there are some battery related challenges facing EVs. Due to limited charge holding capacity of Li-ion batteries, the driving range of EVs are limited compared to ICE vehicles, being able to only travel one-third or half the distance of an ICE vehicle [2]. In addition, the battery charging time is time consuming, with a full charge taking about 4–8 h and fast charge about 30 min compared to 5 min for an ICE vehicle [3]. Despite having higher charge carrying capacity compared to other battery materials, Li-ion batteries for EVs are still very big and

Inductive Power Transfer (IPT) is the method of wirelessly transferring power. The system for static wireless charging is as shown in **Figure 1**. AC power is drawn from the grid into the system. This power is rectified using a diode bridge to supply a DC voltage. This is followed by a Power Factor Correction (PFC) stage to improve the power factor and step up the voltage to 380 V. The DC input voltage is supplied into an inverter, which converts it in high frequency AC so that power can be transmitted by primary coil to the secondary coil using IPT. The secondary coil will take in the HF AC power and rectify it using the SiC diode bridge into a DC voltage for vehicle charging. IPT for EVs provide a convenience and safety for the user [5, 6]. This system is weatherproof and difficult to vandalism like a plug-in station [4].

However, there are challenges facing wireless charging, such as low efficiency compared to plug-in chargers [4]. This is overcome by using wide bandgap semiconductor materials such as GaN, which is attracting attention for enabling high efficiency, high power density converters [7], rectifiers [8] and inverters [9, 10]. The material properties of GaN such as high critical field, electron mobility and saturation velocity [11] push the boundaries of power electronics

The remainder of the chapter is organized as follows. Section 2 will compare various gate driving methods for driving the GaN GIT. This is followed by Section 3 which will explain the design considerations for apply the GaN GIT in WPT applications. Finally, Section 4 contains

performance such as efficiency, power density, reliability and cost [12].

experiment results that demonstrate the advantages of using GaN in IPT.

**Figure 1.** Static wireless charging.

and quieter than ICE, while having stronger accelerations, and lesser maintenance [2].

124 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

bulky. They are expensive and need replacement during the car's lifetime [3, 4].

Among the various enhancement mode GaN, Gate Injection Transistor (GIT) is one such technology, which is able to achieve normally off operation and high current driving capability [13]. The GaN GIT adopts p-GaN with recessed gate to achieve normally-off. The Hybrid Drain embedded in the GIT (HD-GIT) allows the device to overcome the current collapse [14].

Since the GaN GIT is a normally-off device, it can be driven by conventional gate drive methods like the R-type gate drive is shown in **Figure 2a**. Resistor RA1 facilitates the charging during turn on, while the path along RA2 forms the discharge path during turn off.

To capitalize on the switching performance of the GaN device, the RC-type gate drive method [15] is recommended. This gate drive strategy allows the driving of the GaN GIT's gate at a higher voltage allowing faster slew rate. It produces negative gate voltage during turn off to prevent false turn-on, while using a unipolar supply voltage.

A single channel GaN GIT gate driver Integrated Circuit (IC) (AN34092B) utilizes a novel gate drive strategy to compare against existing gate drive methods is shown in [16]. The simplified gate drive circuit for the GaN GIT gate driver IC, AN34092B [17], is shown in **Figure 3a**. The gate driver IC has 3 output pins, namely OUT1, OUT2 and OUT3. OUT1's purpose is to charge the GaN power transistor during turn ON phase and discharging the speed-up capacitor C1 during turn off. When the device is fully turned on, C1 will block current through OUT1.

OUT2 will continue to supply an adjustable DC current of 2.5–25 mA during conduction phase. Integrated within the IC is an adjustable current source, which is able to provide a constant current during turn ON, that is important for the conductivity modulation of the GaN GIT. It also provides a low impedance path using the active miller clamp function.

OUT3 is responsible for the discharge path by pulling the gate to the negative voltage VEE. The turn off slew rate can be controlled using resistor R2. Another integrated function is a charge pump to provide the negative voltage, VEE, during turn OFF, which is adjustable using an external resistor.

**Figure 2.** Various gate drive methods: (a) the R-type and (b) the RC-type.

which is responsible for high slew rate performance. On the other hand, the GaN GIT driver IC and RC-type gate drive provide two current paths, a high current path during turn-on transients for high slew rate performance and a low current path to keep the GaN GIT in

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127

The high current source path of the GaN GIT driver IC and RC-type gate driver comprises a resistor in series with a capacitor. When the power device is fully turned on, the capacitor will block current flow, protecting the gate of the GaN GIT. This allows the GaN GIT driver IC and RC-type gate driver to drive the GaN GIT at a higher supply voltage, resulting in a higher gate current and larger turn-on slew rate. This is supported by Eq. (1), which shows that a higher

For RC circuit, turn-on slew rate is affected by negative voltage of the speed-up capacitor, CB1 on **Figure 2b**. The residue voltage in the capacitor CB1 will reduce the VDDB voltage used to charge the power device. The GaN GIT driver IC resolves this problem with a high speed discharge circuit to discharge C1. So when the gate driver charges the power device during, it

The GaN GIT driver IC and RC type gate drive generates a negative voltage turn-off. The RC-type gate driver relies on the connection of the speed-up capacitor, CB1, to create a negative voltage during turn off. With reference to **Figure 1b**, during turn-on transition, the capacitor CB1 is charged up such that the left hand side is positive relative to the right hand side of CB1. During turn-off, the positive side of CB1 is connected to ground, GNDB, which presents a negative voltage at the gate. This negative voltage slowly decays as it is discharged through

On the other hand, the GaN GIT driver IC has a built in charge pump to generate an adjustable negative rail, VEE, from −3 to −5 V. According to Eq. (2), negative voltage turn-off allows larger gate discharging current leading to larger turn-off slew rates compared to R-type gate

Cross conduction is a false turn-on mechanism that occurs when the high side device is turned on during dead time. When the high side device is turned on, the drain of the low side power transistor is pulled up, inducing a current across the gate-drain capacitor of the low side power device. This current causes a voltage across the gate-source pin of the power device as it flows through the gate resistor. Research showed slew rates and gate resistance [18] affects the induced gate voltage. For high slew rate power devices, these are practical challenges which need to be addressed. This work aims to reduce VGS spike voltage without sacrificing slew rate performance. There are various countermeasures to reduce the effects of

conduction. This is to prevent damaging the gate.

*2.1.2. Turn-on: discharging speed-up capacitor to improve turn-on slew rate*

is able to charge the GaN GIT gate from the full VDDB rail.

VDD increases slew rate.

*2.1.3. Turn-off: negative voltage*

drive circuits, which discharge at 0 V.

**2.2. Cross conduction protection**

RB1 and RB2.

cross conduction.

**Figure 3.** (a) GaN GIT gate driver IC circuit and (b) gate driver timing diagram.

#### **2.1. High slew rate gate drive**

Power density and efficiency are important metrics in power electronics. High slew rates allow high operating frequencies, which lead to higher power density due to smaller passive components. In addition, higher slew rates result in an improvement in the switching losses which result in higher efficiency.

The general equation of VDS turn-on and turn-off slew rate is shown in Eqs. (1) and (2) respectively. The fall and rise in the drain-source voltage, VDS, occurs during the charging and discharging of the gate-drain charge, *QGD*, at the plateau voltage, *Vpl*. The ability to charge and discharge faster means higher slew rates for the power device.

discharge faster means higher slow sales for the power device.

$$
\frac{d\,V\_{DS}}{dT\_{t\_{known}}} = \frac{I\_{Cs} \times V\_{p\_{Run supply}}}{Q\_{GD}} = \frac{(VDD - V\_p) \times V\_{p\_{Run supply}}}{R\_{gav} \times Q\_{GD}}\tag{1}
$$

$$
\frac{d\,V\_{DS}}{dT\_{\text{new}\,\text{gf}}} = \frac{I\_{GS} \times V\_{Run\,\text{supply}}}{Q\_{GD}} = \frac{(VEE - V\_p) \times V\_{Run\,\text{supply}}}{R\_{par\,\text{supply}}}\tag{2}
$$

Based on Eqs. (1) and (2), slew rates can be improved by controlling gate current or using a device with a small QGD. The high breakdown electric field of GaN material allows the GaN GIT to have smaller die size compared to Si power MOSFETs of similar breakdown voltage, which results in smaller parasitic capacitance and correspondingly smaller QGD. To control the charging and discharging of gate current, one can choose to control the value of the gate resistor or adjust the gate driver source and sink voltage.

#### *2.1.1. Turn-on: dual current source paths for gate protection*

To protect the GaN GIT's gate from damage, it is important to keep the gate pulse current and gate pulse charge below the absolute limit. However, controlling the turn-on gate current source through a single path like the R-type gate drive method limits the peak gate current, which is responsible for high slew rate performance. On the other hand, the GaN GIT driver IC and RC-type gate drive provide two current paths, a high current path during turn-on transients for high slew rate performance and a low current path to keep the GaN GIT in conduction. This is to prevent damaging the gate.

The high current source path of the GaN GIT driver IC and RC-type gate driver comprises a resistor in series with a capacitor. When the power device is fully turned on, the capacitor will block current flow, protecting the gate of the GaN GIT. This allows the GaN GIT driver IC and RC-type gate driver to drive the GaN GIT at a higher supply voltage, resulting in a higher gate current and larger turn-on slew rate. This is supported by Eq. (1), which shows that a higher VDD increases slew rate.

#### *2.1.2. Turn-on: discharging speed-up capacitor to improve turn-on slew rate*

For RC circuit, turn-on slew rate is affected by negative voltage of the speed-up capacitor, CB1 on **Figure 2b**. The residue voltage in the capacitor CB1 will reduce the VDDB voltage used to charge the power device. The GaN GIT driver IC resolves this problem with a high speed discharge circuit to discharge C1. So when the gate driver charges the power device during, it is able to charge the GaN GIT gate from the full VDDB rail.

#### *2.1.3. Turn-off: negative voltage*

**2.1. High slew rate gate drive**

which result in higher efficiency.

*<sup>d</sup> <sup>V</sup>* \_\_\_\_\_\_\_\_\_ *DS*

*<sup>d</sup> <sup>V</sup>* \_\_\_\_\_\_\_\_\_ *DS*

Power density and efficiency are important metrics in power electronics. High slew rates allow high operating frequencies, which lead to higher power density due to smaller passive components. In addition, higher slew rates result in an improvement in the switching losses

The general equation of VDS turn-on and turn-off slew rate is shown in Eqs. (1) and (2) respectively. The fall and rise in the drain-source voltage, VDS, occurs during the charging and discharging of the gate-drain charge, *QGD*, at the plateau voltage, *Vpl*. The ability to charge and

Based on Eqs. (1) and (2), slew rates can be improved by controlling gate current or using a device with a small QGD. The high breakdown electric field of GaN material allows the GaN GIT to have smaller die size compared to Si power MOSFETs of similar breakdown voltage, which results in smaller parasitic capacitance and correspondingly smaller QGD. To control the charging and discharging of gate current, one can choose to control the value of the gate

To protect the GaN GIT's gate from damage, it is important to keep the gate pulse current and gate pulse charge below the absolute limit. However, controlling the turn-on gate current source through a single path like the R-type gate drive method limits the peak gate current,

<sup>=</sup> (*VDD* <sup>−</sup> *Vpl*) <sup>×</sup> *VPower supply* \_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_ *Rgate* <sup>×</sup> *QGD*

<sup>=</sup> (*VEE* <sup>−</sup> *Vpl*) <sup>×</sup> *VPower supply* \_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_ *Rgate* <sup>×</sup> *QGD* (1)

(2)

discharge faster means higher slew rates for the power device.

**Figure 3.** (a) GaN GIT gate driver IC circuit and (b) gate driver timing diagram.

126 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

= *I*

= *I*

*GS* <sup>×</sup> *<sup>V</sup>* \_\_\_\_\_\_\_\_\_\_\_\_ *Power supply QGD*

*GS* <sup>×</sup> *<sup>V</sup>* \_\_\_\_\_\_\_\_\_\_\_\_ *Power supply QGD*

*d Tturn on*

*d Tturn off*

resistor or adjust the gate driver source and sink voltage.

*2.1.1. Turn-on: dual current source paths for gate protection*

The GaN GIT driver IC and RC type gate drive generates a negative voltage turn-off. The RC-type gate driver relies on the connection of the speed-up capacitor, CB1, to create a negative voltage during turn off. With reference to **Figure 1b**, during turn-on transition, the capacitor CB1 is charged up such that the left hand side is positive relative to the right hand side of CB1. During turn-off, the positive side of CB1 is connected to ground, GNDB, which presents a negative voltage at the gate. This negative voltage slowly decays as it is discharged through RB1 and RB2.

On the other hand, the GaN GIT driver IC has a built in charge pump to generate an adjustable negative rail, VEE, from −3 to −5 V. According to Eq. (2), negative voltage turn-off allows larger gate discharging current leading to larger turn-off slew rates compared to R-type gate drive circuits, which discharge at 0 V.

#### **2.2. Cross conduction protection**

Cross conduction is a false turn-on mechanism that occurs when the high side device is turned on during dead time. When the high side device is turned on, the drain of the low side power transistor is pulled up, inducing a current across the gate-drain capacitor of the low side power device. This current causes a voltage across the gate-source pin of the power device as it flows through the gate resistor. Research showed slew rates and gate resistance [18] affects the induced gate voltage. For high slew rate power devices, these are practical challenges which need to be addressed. This work aims to reduce VGS spike voltage without sacrificing slew rate performance. There are various countermeasures to reduce the effects of cross conduction.

#### *2.2.1. Low gate impedance*

A common countermeasure using the R-type gate drive for cross conduction protection is to implement a low impedance discharge path through the Schottky barrier diode (DA1) in series with a small resistor (RA2) as shown in **Figure 1a**. During the turn off, this forms a very low impedance path, which sinks the induced current to GND. In this method, the slew rate is dependent on the cross conduction protection.

Unlike the R-type gate drive, which has only one output to sink the gate current, the GaN GIT driver IC has 2 gate sink paths. One path (OUT3) to control the GaN GIT gate discharge current to control the slew rate and another path (OUT2) for active miller clamp function, which implements low gate impedance during the cross conduction period and reduces gate ringing. This unique function allows slew rate control independent of the active miller clamp protection function.

> Double pulse test was conducted with an inductive load and bus voltage of 400 V. It is tested for load currents at 2.5, 5, 7.5 and 10A. Since it is a half bridge circuit, the slew rates for the low side and high side GaN GIT are measured. The gate-source voltage of the low side is probed

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**Figure 4.** Experiment setup for (a) R-type and RC-type gate drive method and (b) GaN GIT gate driver IC.

The waveforms are taken at IDS = 10A and VDS = 400 V. The results for the VDS turn-on and turn-off slew rate were measured from 10 to 90% and waveforms are shown in **Figure 5**. From **Figure 5**, it is observed that the VGS is charged up slower for the R-type gate drive (**Figure 5a**) compared to the RC-type (**Figure 5b**) and GaN GIT gate driver (**Figure 5c**). This is because the RC-type and GaN GIT gate driver charge the gate up with VDD = 12 V, allowing more charge to be supplied compared to the R-type gate drive which have VDD = 5 V supply. Thus, results

With reference to **Figure 5**, it shows that VGS for the R-type gate drive (**Figure 5d**) is turned off at 0 V, while the RC-type (**Figure 5e**) and GaN GIT gate driver (**Figure 5f**) are turned off with a negative voltage. The negative voltage of the RC-type circuit is decaying to 0 V as the capacitor discharges while the GaN GIT gate driver is held at −5 V until the next turn on cycle.

The results for the low side slew rates are shown in **Figure 6**, which illustrate the turn-on (**Figure 6a**) and turn-off (**Figure 6b**) slew rates. From **Figure 6a**, the GaN GIT has the highest turn-on slew rate (97 V/ns) followed by the RC-type (48 V/ns) and finally the R-type (26 V/ns). The gate drive resistor value, which is critical for turn-on slew rate, is fixed at 51 Ω for all three

The RC-type and GaN GIT driver are clearly faster than R-type because they are driven at 12 V. GaN GIT driver is faster than the RC-type gate drive because of the discharging speed-up capacitor function and the choice of a smaller speed-up capacitor (C1 = 120 pF vs. CB1 = 1.2 nF). The reason for the larger capacitor for the RC-type gate drive is to increase the

setups to make a fair comparison with the other gate drive methods.

RC time constant to slow down the decay of the negative turn-off voltage.

during high side test to study the cross conduction protection.

*2.3.2. Slew rates results*

in a faster VDS slew rate.

#### *2.2.2. Negative voltage*

Implementing a negative gate-source voltage during turn off creates a voltage buffer between VGS and Vth to prevent the GaN GIT from turning on when cross conduction occurs. The RC-type gate drive creates a negative voltage across the VGS during turn-off due to the change in polarity of the speed up capacitor CB1. On the other hand, the GaN GIT driver IC has built-in negative voltage rail to create this voltage buffer. These two methods are able to create a negative voltage rail with a unipolar voltage supply, which reduce cost.

#### **2.3. Experiment results of gate drive methods**

#### *2.3.1. Experiment setup*

The driving methods are tested using a half bridge configuration based on **Figures 2** and **3a** as shown below in **Table 1**. The evaluation was conducted using 600 V, 10A SMD GaN GIT. R-type and RC-type gate drive were tested using SWEVB005-PGA26E19BA half bridge evaluation board (**Figure 4a**), while the GaN GIT gate driver IC (AN34092B) was tested using SWEVB008-PGA26E19BA half bridge evaluation board (**Figure 4b**). The purpose is to keep the parasitic inductance of the gate drive loop and power loop similar across the three evaluation setups.


**Table 1.** Design parameters and values for experiment.

**Figure 4.** Experiment setup for (a) R-type and RC-type gate drive method and (b) GaN GIT gate driver IC.

Double pulse test was conducted with an inductive load and bus voltage of 400 V. It is tested for load currents at 2.5, 5, 7.5 and 10A. Since it is a half bridge circuit, the slew rates for the low side and high side GaN GIT are measured. The gate-source voltage of the low side is probed during high side test to study the cross conduction protection.

#### *2.3.2. Slew rates results*

*2.2.1. Low gate impedance*

protection function.

*2.2.2. Negative voltage*

reduce cost.

ation setups.

*2.3.1. Experiment setup*

is dependent on the cross conduction protection.

128 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**2.3. Experiment results of gate drive methods**

**Table 1.** Design parameters and values for experiment.

A common countermeasure using the R-type gate drive for cross conduction protection is to implement a low impedance discharge path through the Schottky barrier diode (DA1) in series with a small resistor (RA2) as shown in **Figure 1a**. During the turn off, this forms a very low impedance path, which sinks the induced current to GND. In this method, the slew rate

Unlike the R-type gate drive, which has only one output to sink the gate current, the GaN GIT driver IC has 2 gate sink paths. One path (OUT3) to control the GaN GIT gate discharge current to control the slew rate and another path (OUT2) for active miller clamp function, which implements low gate impedance during the cross conduction period and reduces gate ringing. This unique function allows slew rate control independent of the active miller clamp

Implementing a negative gate-source voltage during turn off creates a voltage buffer between VGS and Vth to prevent the GaN GIT from turning on when cross conduction occurs. The RC-type gate drive creates a negative voltage across the VGS during turn-off due to the change in polarity of the speed up capacitor CB1. On the other hand, the GaN GIT driver IC has built-in negative voltage rail to create this voltage buffer. These two methods are able to create a negative voltage rail with a unipolar voltage supply, which

The driving methods are tested using a half bridge configuration based on **Figures 2** and **3a** as shown below in **Table 1**. The evaluation was conducted using 600 V, 10A SMD GaN GIT. R-type and RC-type gate drive were tested using SWEVB005-PGA26E19BA half bridge evaluation board (**Figure 4a**), while the GaN GIT gate driver IC (AN34092B) was tested using SWEVB008-PGA26E19BA half bridge evaluation board (**Figure 4b**). The purpose is to keep the parasitic inductance of the gate drive loop and power loop similar across the three evalu-

R-type gate drive 5 Nil RA1 = 51 Ω RA2 = 1 Ω DA1 = SBD RC-type gate drive 12 −5 V RB1 = 51 Ω RB2 = 2700 Ω CB1 = 1.2 nF GaN GIT gate driver IC 12 −5 V R1 = 51 Ω R2 = 1 Ω C1 = 120 pF

**VDD (V) VNegative Component 1 Component 2 Component 3**

The waveforms are taken at IDS = 10A and VDS = 400 V. The results for the VDS turn-on and turn-off slew rate were measured from 10 to 90% and waveforms are shown in **Figure 5**. From **Figure 5**, it is observed that the VGS is charged up slower for the R-type gate drive (**Figure 5a**) compared to the RC-type (**Figure 5b**) and GaN GIT gate driver (**Figure 5c**). This is because the RC-type and GaN GIT gate driver charge the gate up with VDD = 12 V, allowing more charge to be supplied compared to the R-type gate drive which have VDD = 5 V supply. Thus, results in a faster VDS slew rate.

With reference to **Figure 5**, it shows that VGS for the R-type gate drive (**Figure 5d**) is turned off at 0 V, while the RC-type (**Figure 5e**) and GaN GIT gate driver (**Figure 5f**) are turned off with a negative voltage. The negative voltage of the RC-type circuit is decaying to 0 V as the capacitor discharges while the GaN GIT gate driver is held at −5 V until the next turn on cycle.

The results for the low side slew rates are shown in **Figure 6**, which illustrate the turn-on (**Figure 6a**) and turn-off (**Figure 6b**) slew rates. From **Figure 6a**, the GaN GIT has the highest turn-on slew rate (97 V/ns) followed by the RC-type (48 V/ns) and finally the R-type (26 V/ns). The gate drive resistor value, which is critical for turn-on slew rate, is fixed at 51 Ω for all three setups to make a fair comparison with the other gate drive methods.

The RC-type and GaN GIT driver are clearly faster than R-type because they are driven at 12 V. GaN GIT driver is faster than the RC-type gate drive because of the discharging speed-up capacitor function and the choice of a smaller speed-up capacitor (C1 = 120 pF vs. CB1 = 1.2 nF). The reason for the larger capacitor for the RC-type gate drive is to increase the RC time constant to slow down the decay of the negative turn-off voltage.

**Figure 5.** Double pulse waveform for (a) R-type, (b) RC-type and (c) GaN GIT gate driver during turn-off and for (d) R-type, (e) RC-type and (f) GaN GIT gate driver during turn-on.

The turn-off slew rate results is depicted in **Figure 6b**. From the graph, it is shown that slew rate for RC-type and R-type are close, while GaN GIT driver IC outperforms them to achieve

a maximum slew rate of 110 V/ns. While both RC-type and GaN GIT driver IC discharges the gate with negative voltage, the RC-gate drive method has a larger discharge resistance resulting in a slower turn-off slew rate. The R-type gate drive has a low resistance to GND, but discharges to GND instead to a negative voltage. The GaN GIT driver IC capitalizes on low

The high side slew rate is shown in **Figure 7**. Results are very similar to the low side results in **Figure 6**, except that the high side results are slightly faster. This is because of the probe capacitance loading on the VGS and VDS pin during low side test that slow down the slew

impedance from gate to VEE and a negative voltage to achieve twice the slew rate.

**Figure 7.** Slew rate measurement results for (a) high side turn-on and (b) high side turn-off.

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rate measurement results.

**Figure 8.** Cross conduction test.

**Figure 6.** Slew rate measurement results for (a) low side turn-on and (b) low side turn-off.

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**Figure 7.** Slew rate measurement results for (a) high side turn-on and (b) high side turn-off.

**Figure 8.** Cross conduction test.

**Figure 6.** Slew rate measurement results for (a) low side turn-on and (b) low side turn-off.

R-type, (e) RC-type and (f) GaN GIT gate driver during turn-on.

130 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The turn-off slew rate results is depicted in **Figure 6b**. From the graph, it is shown that slew rate for RC-type and R-type are close, while GaN GIT driver IC outperforms them to achieve

**Figure 5.** Double pulse waveform for (a) R-type, (b) RC-type and (c) GaN GIT gate driver during turn-off and for (d)

a maximum slew rate of 110 V/ns. While both RC-type and GaN GIT driver IC discharges the gate with negative voltage, the RC-gate drive method has a larger discharge resistance resulting in a slower turn-off slew rate. The R-type gate drive has a low resistance to GND, but discharges to GND instead to a negative voltage. The GaN GIT driver IC capitalizes on low impedance from gate to VEE and a negative voltage to achieve twice the slew rate.

The high side slew rate is shown in **Figure 7**. Results are very similar to the low side results in **Figure 6**, except that the high side results are slightly faster. This is because of the probe capacitance loading on the VGS and VDS pin during low side test that slow down the slew rate measurement results.

#### *2.3.3. Cross conduction protection*

The low side VGS spike voltage occurs when high side is turned on is measured and plotted against the slew rates (according to **Figure 7a**) and shown in **Figure 8**. From the results, it shows that the GaN GIT gate driver has the lowest VGS spike voltage, despite higher slew rate operation than the other two methods. All three methods managed to keep this spike voltage below the threshold voltage of the GaN GIT.

The total conduction loss is shown in Eq. (4) and is influenced by the on-resistance, Ron, of the device and application requirements such as drain-source current, IDS, and duty, D. Switching loss, on the other hand, is frequency dependent as shown in Eq. (5). It is affected by the drainsource voltage, VDS, and current during the turn on (ton) and turn off (toff) switching transition. This shows the need for soft switching or fast slew rates for hard switching applications to

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The ringing loss is obtained from [20] and modified for GaN GIT as shown in Eq. (6). GaN GIT does not have Qrr but still has to discharge drain-source capacitor, CDS, which is represented by the drain source charge, Qoss. Ringing losses are proportionate to frequency and DC-link voltages, Vbulk. The turn on ringing loss are affected by the Qoss, while the turn off losses are affected by charges, QVpeak, due to the peak ringing voltage Vpeak. High slew rates and parasitic

The absence of reverse recovery diode implies that dead time, tSD, can be reduced. However, the GaN device will still experience a dead time loss according to Eq. (7). When a reverse current ISD flows through the device, it will have a voltage drop, VSD, during dead time that

*PHB loss* = *Pcond loss* + *Psw loss* + *Pringing* + *Pdead time* (3)

<sup>2</sup> *Ron*,*top D* + *I*

2 *f*

Double pulse switching characteristic test, using an inductive load circuit shown in **Figure 9**, is conducted to evaluate the performance of the GaN GIT under EV wireless charging conditions. The GaN GIT is evaluated based on the specifications of the design. The drain-source parameters of the device is tested based on a DC-link voltage of 400 V, with load current varying from 2.5 to 15A. The gate drive voltage is set at 12 V. The value of drain-source voltage/current overshoot, drain-source voltage slew rate and switching losses energy will be measured. The gate drive resistor R1 will be varied from 5.1 to 36 Ω. **Figure 10** shows the

Parasitic inductance in the gate drive loop should be small to improve the slew rate of the GaN device. One should consider reduction of the source and drain inductances along the

*SD* × *t*

*DS*

<sup>2</sup> *Ron*,*bot*(1 − *D*) (4)

(*QVpeak*(*Vpeak* − 2 *Vbulk*) + *QVin Vbulk*) (6)

*SD* × *f* (7)

*off*,*bot*) (5)

*DS*

<sup>2</sup> *Qoss*,*bot*) <sup>+</sup> \_\_<sup>1</sup>

*DS*(*t on*,*top* + *t off*,*top* + *t on*,*bot* + *t*

<sup>2</sup> *f VDS I*

+ \_\_1

(*Qoss*,*top*

**3.3. Experimental results and GaN GIT gate driver optimization**

*Pdead time* = *VSD* × *I*

waveforms at 400 V and 10A using R1 = 10 Ω.

reduce switching losses.

results in dead time loss.

source drain inductances increase the peak voltage.

*Ptop*&*bot*,*cond loss* = *I*

*Psw*,*on*&*off* <sup>=</sup> \_\_<sup>1</sup>

*Pringing* = *Vbulk f*

### **3. Switching loss evaluation and gate drive optimization for IPT in EV system**

#### **3.1. Power device selection**

A common Figure of Merit (FOM) adopted by power semiconductor devices is RonQg. This FOM accounts for the switching and conduction loss such that the lower the FOM, the better the performance. This is a representative of the technology [19]. A comparison of FOM among three state-of-the-art transistors using GaN, SiC and Si are compared and shown in **Table 2**.

GaN GIT has the lowest FOM due to the high critical field of GaN and the High Electron Mobility Transistor (HEMT) structure. The Si vertical MOSFET performs the worst with the highest FOM. This is followed by SiC MOSFETs which perform an order of magnitude better. It is shown that Si Super Junction MOSFETs being able to outperform SiC MOSFETs for RonQg. This is because the Super Junction technology is able to push beyond the theoretical limits of Si.

#### **3.2. Half bridge circuit loss modeling**

The total losses in a half bridge circuit contains conduction loss, switching loss, ringing loss and dead time loss of the top and bottom power device and is shown in Eq. (3). The subscript top and bot respectively denote the top and bottom power device.


**Table 2.** FOM comparison between semiconductor devices.

The total conduction loss is shown in Eq. (4) and is influenced by the on-resistance, Ron, of the device and application requirements such as drain-source current, IDS, and duty, D. Switching loss, on the other hand, is frequency dependent as shown in Eq. (5). It is affected by the drainsource voltage, VDS, and current during the turn on (ton) and turn off (toff) switching transition. This shows the need for soft switching or fast slew rates for hard switching applications to reduce switching losses.

The ringing loss is obtained from [20] and modified for GaN GIT as shown in Eq. (6). GaN GIT does not have Qrr but still has to discharge drain-source capacitor, CDS, which is represented by the drain source charge, Qoss. Ringing losses are proportionate to frequency and DC-link voltages, Vbulk. The turn on ringing loss are affected by the Qoss, while the turn off losses are affected by charges, QVpeak, due to the peak ringing voltage Vpeak. High slew rates and parasitic source drain inductances increase the peak voltage.

The absence of reverse recovery diode implies that dead time, tSD, can be reduced. However, the GaN device will still experience a dead time loss according to Eq. (7). When a reverse current ISD flows through the device, it will have a voltage drop, VSD, during dead time that results in dead time loss.

$$P\_{\text{HB loss}} = P\_{\text{cond loss}} + P\_{\text{su loss}} + P\_{\text{ringing}} + P\_{\text{dead time}} \tag{3}$$

$$P\_{\text{topdobt}, \text{cond loss}} = I\_{DS}^2 R\_{\text{on,top}} D + I\_{DS}^2 R\_{\text{on,bot}} \text{(1} - D\text{)}\tag{4}$$

$$P\_{sun,outage} = \frac{1}{2} f V\_{DS} I\_{DS} (t\_{on,top} + t\_{off,top} + t\_{on,bot} + t\_{off,bot}) \tag{5}$$

$$P\_{ring\_{\rm{ig}}} = V\_{ball} f\left(Q\_{os,up} + \frac{1}{2} Q\_{os,hot}\right) + \frac{1}{2} f\left(Q\_{\rm{lyack}} (V\_{\rm{peak}} - 2 \, V\_{\rm{bulk}}) + Q\_{\rm{Un}} \, V\_{\rm{bulk}}\right) \tag{6}$$

$$P\_{\text{dand time}} = \left. \mathcal{V}\_{\text{SD}} \times I\_{\text{SD}} \times t\_{\text{SD}} \times f \right. \tag{7}$$

#### **3.3. Experimental results and GaN GIT gate driver optimization**

Material GaN Si Si SiC SiC

top and bot respectively denote the top and bottom power device.

Rated current (A) 15 6 18 29 40 Ron (mΩ) 65 1000 125 120 80

(nC) 11 33 35 61 106

(nΩC) 0.715 33 4.38 7.32 8.48

MOSFET Super Junction MOSFET

The low side VGS spike voltage occurs when high side is turned on is measured and plotted against the slew rates (according to **Figure 7a**) and shown in **Figure 8**. From the results, it shows that the GaN GIT gate driver has the lowest VGS spike voltage, despite higher slew rate operation than the other two methods. All three methods managed to keep this spike

A common Figure of Merit (FOM) adopted by power semiconductor devices is RonQg. This FOM accounts for the switching and conduction loss such that the lower the FOM, the better the performance. This is a representative of the technology [19]. A comparison of FOM among three state-of-the-art transistors using GaN, SiC and Si are compared and

GaN GIT has the lowest FOM due to the high critical field of GaN and the High Electron Mobility Transistor (HEMT) structure. The Si vertical MOSFET performs the worst with the highest FOM. This is followed by SiC MOSFETs which perform an order of magnitude better. It is shown that Si Super Junction MOSFETs being able to outperform SiC MOSFETs for RonQg. This is because the Super Junction technology is able to push beyond the theoretical

The total losses in a half bridge circuit contains conduction loss, switching loss, ringing loss and dead time loss of the top and bottom power device and is shown in Eq. (3). The subscript

**3. Switching loss evaluation and gate drive optimization for IPT in** 

600 600 700 650 1200

MOSFET MOSFET

Technology Gate Injection

**3.2. Half bridge circuit loss modeling**

*2.3.3. Cross conduction protection*

**EV system**

shown in **Table 2**.

limits of Si.

**3.1. Power device selection**

voltage below the threshold voltage of the GaN GIT.

132 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Breakdown voltage

(V)

Qg

RonQ<sup>g</sup>

Transistor

**Table 2.** FOM comparison between semiconductor devices.

Double pulse switching characteristic test, using an inductive load circuit shown in **Figure 9**, is conducted to evaluate the performance of the GaN GIT under EV wireless charging conditions. The GaN GIT is evaluated based on the specifications of the design. The drain-source parameters of the device is tested based on a DC-link voltage of 400 V, with load current varying from 2.5 to 15A. The gate drive voltage is set at 12 V. The value of drain-source voltage/current overshoot, drain-source voltage slew rate and switching losses energy will be measured. The gate drive resistor R1 will be varied from 5.1 to 36 Ω. **Figure 10** shows the waveforms at 400 V and 10A using R1 = 10 Ω.

Parasitic inductance in the gate drive loop should be small to improve the slew rate of the GaN device. One should consider reduction of the source and drain inductances along the

**Figure 9.** Experimental setup for inductive load circuit for double pulse test.

power loop to reduce the VDS ringing. For realistic results, adopt a freewheeling diode that have a similar reverse recovery charge to the GaN GIT's reverse conduction QDS.

The turn-off and turn-on switching loss energy per cycle is shown in **Figure 11**. Reducing the gate drive resistor, R1, results in higher gate current, reducing rise and fall time and thus reducing switching losses. As load current increases, the switching loss also increase. These two observations agree with Eq. (5).

The second factor for consideration is the drain-source voltage overshoot. **Figure 12a** and **b** shows the turn-off voltage peak and turn-on current peak respectively, with variation in the load current and the gate drive resistor. Voltage and current overshoot is directly proportional to load current. Reduction in the gate drive resistance increases the overshoot. From the evaluation results, it shows that the observed overshoot is below the absolute voltage and

**Figure 11.** Evaluation results for switching energy per cycle: (a) turn-off switching energy and (b) turn-on switching energy.

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Finally, we will evaluate the slew rate results in **Figure 13**. **Figure 13a** illustrates the slew rate during the turn off transition. The slew rate increases as the gate drive resistance is reduced and achieves a maximum slew rate of 67 V/ns at 5 Ω. This work utilizes the GaN GIT with TO-220 package which has higher parasitic inductance compared to surface mount packages,

**Figure 12.** Evaluation results for overshoot: (a) drain source voltage peak vs. absolute rating and (b) drain source current

current rating and hence the device is safe.

resulting in slower slew rates.

peak vs. absolute rating.

**Figure 10.** Switching experimental results of 2-pulse test results: (a) turn-off transition for TO-220 GaN GIT and (b) turn-on transition for TO-220 GaN GIT.

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**Figure 11.** Evaluation results for switching energy per cycle: (a) turn-off switching energy and (b) turn-on switching energy.

The second factor for consideration is the drain-source voltage overshoot. **Figure 12a** and **b** shows the turn-off voltage peak and turn-on current peak respectively, with variation in the load current and the gate drive resistor. Voltage and current overshoot is directly proportional to load current. Reduction in the gate drive resistance increases the overshoot. From the evaluation results, it shows that the observed overshoot is below the absolute voltage and current rating and hence the device is safe.

Finally, we will evaluate the slew rate results in **Figure 13**. **Figure 13a** illustrates the slew rate during the turn off transition. The slew rate increases as the gate drive resistance is reduced and achieves a maximum slew rate of 67 V/ns at 5 Ω. This work utilizes the GaN GIT with TO-220 package which has higher parasitic inductance compared to surface mount packages, resulting in slower slew rates.

**Figure 12.** Evaluation results for overshoot: (a) drain source voltage peak vs. absolute rating and (b) drain source current peak vs. absolute rating.

**Figure 10.** Switching experimental results of 2-pulse test results: (a) turn-off transition for TO-220 GaN GIT and (b)

power loop to reduce the VDS ringing. For realistic results, adopt a freewheeling diode that

The turn-off and turn-on switching loss energy per cycle is shown in **Figure 11**. Reducing the gate drive resistor, R1, results in higher gate current, reducing rise and fall time and thus reducing switching losses. As load current increases, the switching loss also increase. These

have a similar reverse recovery charge to the GaN GIT's reverse conduction QDS.

**Figure 9.** Experimental setup for inductive load circuit for double pulse test.

134 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

turn-on transition for TO-220 GaN GIT.

two observations agree with Eq. (5).

**Figure 13.** Evaluation results for slew rate: (a) VDS slew rate during turn-off transition and (b) VDS slew rate during turn-on transition.

**Figure 13b** shows the turn on slew rate. Lower gate drive resistance causes higher slew rates while slew rates drop as load current increases. Due to parasitic inductance within the TO-220 package, a voltage drop is observed across the drain to source nodes when drain source current flows through it, affecting the slew rate measurement of VDS at low load (2.5 and 5A condition). Therefore, only higher load conditions (10 and 15A) are shown.

The efficiency breakdowns of each individual stages at 150 and 80 mm are shown in **Figures 16** and **17** respectively. They are tested at an operating frequency 100 kHz. The high frequency inverter maintains its efficiency within the 97–98% region across the varying distances at 2 kW. The coil efficiency falls drastically as the coil gap increases. This is because the increase in distance results in a weaker coupling factor causing a higher secondary current and hence increases the copper loss in the coil. At 80 mm, the efficiency of the rectifier performs well. This is because the SiC diode forward voltage is small relative to output voltage. However, as coil gap increase, the secondary voltage drops, which makes

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the diode forward voltage loss more significant.

**Figure 15.** Experimental results: efficiency vs. distance.

**Figure 14.** Wireless power transfer experiment setup.

Based on the evaluation data, the choice of R1 should ensure low total switching energy and peak drain-source voltage. Although the 5 Ω results performed better, it has a slew rate above 50 V/ns. During the design, there were not many isolated half bridge gate drivers, which can handle high slew rate operations, characterized by the parameter called common mode transient immunity (CMTI). The highest CMTI was from ADuM3223 at 50 V/ns. Therefore, while 5 Ω had better evaluation results, we chose 10 Ω so that it can function within the limits of our isolated gate driver.

#### **4. Experiment results of inductive power transfer system**

The hardware for the solution is shown in **Figure 14**, comprising of a high frequency inverter, a pair of magnetically coupled coils, a high frequency rectifier on the secondary side and a resistor bank acting as a load. The system is tested from 80 to 150 mm. The input voltage to the inverter is 370VDC, which is the typical output voltage from the PFC stage. In order to ensure the inverter output current is below the current rating of the GaN GIT, the resistor load is set to 47 Ω at 80 mm and 11.5 Ω at 150 mm. This is because variation in coil gap affects the mutual inductance and hence affects the reflected load from the secondary side to the primary side.

The system efficiency from 80 to 150 mm is shown in **Figure 15**. The highest efficiency is obtained at 80 mm at 2.1 kW. As the coil gap increases, the efficiency falls as shown with the peak efficiency occurring at 90.4% at 150 mm. The reason for testing at 150 mm up to 1.5 kW is to operate the inverter below the absolute current limit of the 15A GaN GIT device.

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**Figure 14.** Wireless power transfer experiment setup.

**Figure 13.** Evaluation results for slew rate: (a) VDS slew rate during turn-off transition and (b) VDS slew rate during

**Figure 13b** shows the turn on slew rate. Lower gate drive resistance causes higher slew rates while slew rates drop as load current increases. Due to parasitic inductance within the TO-220 package, a voltage drop is observed across the drain to source nodes when drain source current flows through it, affecting the slew rate measurement of VDS at low load (2.5 and 5A condition).

Based on the evaluation data, the choice of R1 should ensure low total switching energy and peak drain-source voltage. Although the 5 Ω results performed better, it has a slew rate above 50 V/ns. During the design, there were not many isolated half bridge gate drivers, which can handle high slew rate operations, characterized by the parameter called common mode transient immunity (CMTI). The highest CMTI was from ADuM3223 at 50 V/ns. Therefore, while 5 Ω had better evaluation results, we chose 10 Ω so that it can function within the limits of our

The hardware for the solution is shown in **Figure 14**, comprising of a high frequency inverter, a pair of magnetically coupled coils, a high frequency rectifier on the secondary side and a resistor bank acting as a load. The system is tested from 80 to 150 mm. The input voltage to the inverter is 370VDC, which is the typical output voltage from the PFC stage. In order to ensure the inverter output current is below the current rating of the GaN GIT, the resistor load is set to 47 Ω at 80 mm and 11.5 Ω at 150 mm. This is because variation in coil gap affects the mutual inductance and hence affects the reflected load from the secondary side to the primary side.

The system efficiency from 80 to 150 mm is shown in **Figure 15**. The highest efficiency is obtained at 80 mm at 2.1 kW. As the coil gap increases, the efficiency falls as shown with the peak efficiency occurring at 90.4% at 150 mm. The reason for testing at 150 mm up to 1.5 kW is

to operate the inverter below the absolute current limit of the 15A GaN GIT device.

Therefore, only higher load conditions (10 and 15A) are shown.

136 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

**4. Experiment results of inductive power transfer system**

turn-on transition.

isolated gate driver.

The efficiency breakdowns of each individual stages at 150 and 80 mm are shown in **Figures 16** and **17** respectively. They are tested at an operating frequency 100 kHz. The high frequency inverter maintains its efficiency within the 97–98% region across the varying distances at 2 kW. The coil efficiency falls drastically as the coil gap increases. This is because the increase in distance results in a weaker coupling factor causing a higher secondary current and hence increases the copper loss in the coil. At 80 mm, the efficiency of the rectifier performs well. This is because the SiC diode forward voltage is small relative to output voltage. However, as coil gap increase, the secondary voltage drops, which makes the diode forward voltage loss more significant.

**Figure 15.** Experimental results: efficiency vs. distance.

**Figure 16.** Experimental results: efficiency breakdown at 150 mm.

The waveform of the inverter output current (CH1), inverter output voltage (CH2), IPT output voltage (CH3) and IPT output current (CH4) at 80 mm distance, operating at 100 kHz is shown in **Figure 18**. The figure shows the zoom out version at 20 μs/div on the top and the zoom in image at 2 μs/div on the bottom.

The next experiment compared efficiencies by varying the operating frequency from 100 kHz to 250 kHz at a 80 mm coil gap, evaluating the system up to 2 kW. **Figure 19** illustrates the results and it shows a drop in system efficiency from 95.13 to 91.7% at 2 kW. This efficiency in the inverter fell due to switching losses at higher frequency operation. The IPT coils will experience higher AC resistance due to skin effect as the operating frequency increase by 2.5 times. The rectifier suffers from higher reverse recovery loss at higher frequencies.

A similar setup was made using a SiC based high frequency inverter. The efficiency comparison between the GaN based and SiC based system is illustrated in **Figure 20**. The GaN based system outperformed the SiC based system by 1% at 2 kW, which translates to 20 W less heat dissipated on the inverter. This was because of the lower on-resistance and gate charge of the

**Figure 18.** Experimental results of inverter and coil channel 1: inverter output current, channel 2: inverter output voltage,

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GaN GIT, resulting in lower conduction and switching loss.

**Figure 19.** Experimental results: efficiency vs. input power for varying frequencies.

channel 3: IPT output voltage, channel 4: IPT output current.

**Figure 17.** Experimental results: efficiency breakdown at 80 mm.

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**Figure 18.** Experimental results of inverter and coil channel 1: inverter output current, channel 2: inverter output voltage, channel 3: IPT output voltage, channel 4: IPT output current.

**Figure 16.** Experimental results: efficiency breakdown at 150 mm.

138 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

zoom in image at 2 μs/div on the bottom.

The waveform of the inverter output current (CH1), inverter output voltage (CH2), IPT output voltage (CH3) and IPT output current (CH4) at 80 mm distance, operating at 100 kHz is shown in **Figure 18**. The figure shows the zoom out version at 20 μs/div on the top and the

The next experiment compared efficiencies by varying the operating frequency from 100 kHz to 250 kHz at a 80 mm coil gap, evaluating the system up to 2 kW. **Figure 19** illustrates the results and it shows a drop in system efficiency from 95.13 to 91.7% at 2 kW. This efficiency in the inverter fell due to switching losses at higher frequency operation. The IPT coils will experience higher AC resistance due to skin effect as the operating frequency increase by 2.5

times. The rectifier suffers from higher reverse recovery loss at higher frequencies.

**Figure 17.** Experimental results: efficiency breakdown at 80 mm.

A similar setup was made using a SiC based high frequency inverter. The efficiency comparison between the GaN based and SiC based system is illustrated in **Figure 20**. The GaN based system outperformed the SiC based system by 1% at 2 kW, which translates to 20 W less heat dissipated on the inverter. This was because of the lower on-resistance and gate charge of the GaN GIT, resulting in lower conduction and switching loss.

**Figure 19.** Experimental results: efficiency vs. input power for varying frequencies.

**References**

September 2012

pp. 275-282

Boca Raton. 2012

20-22 May 2014. Nuremberg. pp. 1-8

(APEC); 6-11 March 2011; Fort Worth. pp. 481-484

20-23 October 2008; Beijing. 2008. pp. 1078-1081

notes. [Accessed: April 9, 2014]

[1] Omori H, Iga Y, Morizane T, Kimura N, Nakagawa K, Nakaoka M. A novel wireless EV charger using SiC single-ended quasi-resonant inverter for home use. In: 2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC); 4-6

Inductive Power Transfer for Electric Vehicles Using Gallium Nitride Power Transistors

http://dx.doi.org/10.5772/intechopen.76057

141

[2] US Department of Energy. All-Electric Vehicles (EVs). US Department of Energy; 08 April 2014. [Online]. Available: https://www.fueleconomy.gov/feg/evtech.shtml#end-

[3] Li S, Mi C. Wireless power transfer for electric vehicle applications. IEEE Journal of

[4] Wu H, Gilchrist A, Sealy K, Bronson D. A 90 percent efficient 5kW inductive charger for EVs. IEEE Energy Conversion Congress and Exposition (ECCE); 15-20 September 2012.

[5] Onar OC, Miller JM, Campbell SL, Coomer C, White C, Seiber LE. A novel wireless power transfer for in-motion EV/PHEV charging. In: Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC); 17-21 March 2013 [6] Chawla N, Tosunoglu S. State of the art in inductive charging for electronic appliances and its future in transportation. In: Florida Conference on Recent Advances in Robotics;

[7] Umeda H, Kinoshita Y, Ujita S, Morita T, Tamura S, Ishida M, Ueda T. Highly efficient low-voltage DC-DC converter at 2-5 MHz with high operating current using GaN gate injection transistors. In: International Exhibition Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management PCIM Europe 2014;

[8] Liu Z, Lee FC, Li Q, Yang Y. Design of GaN-based MHz totem-pole PFC rectifier. IEEE Journal of Emerging and Selected Topics in Power Electronics. 2016;**4**(3):799-807

[9] Morita T, Tamura S, Anda Y, Ishida M, Uemoto Y, Ueda T, Tanaka T, Ueda D. 99.3% efficiency of three-phase inverter for motor drive using GaN-based Gate Injection Transistors. In: 2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition

[10] Cai A, Pereira A, Tanzania R, Tan YK, Siek L. A high frequency, high efficiency GaN HFET based inductive power transfer system. In: 2015 IEEE Applied Power Electronics

[11] Ueda D, Hikita M, Nakazawa S, Nakazawa K, Ishida H, Yanagihara M, Inoue K, Ueda T, Uemoto Y, Tanaka T, Egawa T. Present and future prospects of gan-based power electronics. In: 9th International Conference on Solid-State and Integrated-Circuit Technology;

[12] Kolar JW, Biela J, Waffler S, Friedli T and Badstuebner U. Performance trends and limitations of power electronic systems. In: 6th International Conference on Integrated Power

Conference and Exposition (APEC); Charlotte. 2015. pp. 3094-3100

Electronics Systems; 16-18 March 2010; Nuremberg. 2010. pp. 1-20

Emerging and Selected Topics in Power Electronics. 2015;**3**(1):4-17

**Figure 20.** Experimental results: efficiency comparison between GaN and SiC.

## **5. Conclusion**

In this work, a practical high efficiency wireless power transfer system for EV charging application is developed. The GaN GIT introduced is able to provide superior performance and system benefits. Gate drive strategies are introduced with performance evaluation showing that GaN GIT gate driver achieves high slew rate, while still providing protection from cross conduction. Application of GaN GIT is adopted to improve the efficiency of the inverter by optimizing the gate drive circuit. Experimental results prove the efficiency advantage of adopting GaN GIT in high frequency applications such as inductive power transfer for electric vehicle charging.

#### **Acknowledgements**

The authors would like to acknowledge the funding support from NTU-A\*STAR Silicon Technologies Centre of Excellence (Si-COE) under the program grant No. 11235100003. The authors would like to acknowledge the provision of GaN GIT samples and the financial support from Panasonic Industrial Devices Semiconductor Development Asia (PIDSCDA). The authors are grateful for the financial support provided by the Economic Development Board (EDB) of Singapore. We would like to express our appreciation to Energy Research Institute @ NTU (ERI@N) for providing the facilities and technical support for this project. Finally, the authors would like to express gratitude towards VIRTUS IC design center.

#### **Author details**

Cai Qingwei Aaron\* and Siek Liter

\*Address all correspondence to: aaroncaiqw@gmail.com

Nanyang Technological University, Singapore

#### **References**

**5. Conclusion**

**Acknowledgements**

**Author details**

Cai Qingwei Aaron\* and Siek Liter

\*Address all correspondence to: aaroncaiqw@gmail.com

Nanyang Technological University, Singapore

In this work, a practical high efficiency wireless power transfer system for EV charging application is developed. The GaN GIT introduced is able to provide superior performance and system benefits. Gate drive strategies are introduced with performance evaluation showing that GaN GIT gate driver achieves high slew rate, while still providing protection from cross conduction. Application of GaN GIT is adopted to improve the efficiency of the inverter by optimizing the gate drive circuit. Experimental results prove the efficiency advantage of adopting GaN GIT in high frequency applications such as inductive power transfer for electric vehicle charging.

**Figure 20.** Experimental results: efficiency comparison between GaN and SiC.

140 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

The authors would like to acknowledge the funding support from NTU-A\*STAR Silicon Technologies Centre of Excellence (Si-COE) under the program grant No. 11235100003. The authors would like to acknowledge the provision of GaN GIT samples and the financial support from Panasonic Industrial Devices Semiconductor Development Asia (PIDSCDA). The authors are grateful for the financial support provided by the Economic Development Board (EDB) of Singapore. We would like to express our appreciation to Energy Research Institute @ NTU (ERI@N) for providing the facilities and technical support for this project. Finally, the

authors would like to express gratitude towards VIRTUS IC design center.


[13] Uemoto Y, Hikita M, Ueno H, Matsuo H, Ishida H, Yanagihara M, Ueda T, Tanaka T, Ueda D. Gate injection transistor (GIT)—A normally-off AlGaN/GaN power transistor using conductivity modulation. IEEE Transactions on Electron Devices. 2007;**54**(12):3393-3399 [14] Kaneko S, Kuroda M., Yanagihara M, Ikoshi A, Okita H, Morita T, Tanaka K, Hikita M, Uemoto Y, Takahashi S, Ueda T. Current-collapse-free operations up to 850 V by GaN-GIT utilizing hole injection from drain. In: IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD); 10-14 May 2015; Hong Kong. 2015. pp. 41-44 [15] Morita T, Handa H, Ujita S, Ishida M, Ueda T. 99.3% efficiency of boost-up converter for totem-pole bridge-less PFC using GaN gate injection transistor. In: Proceedings of the International Exhibition and Conference for Power Electronics, Intelligent Motion,

Renewable Energy and Energy Management, PCIM Europe; Nuremberg. 2014 [16] Cai A, Herreria AC, How SB, Siek L. Gate driver IC for GaN GIT for high slew rate and cross conduction protection. In: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management,

[17] Panasonic Semiconductor. GaN Power Devices. [Online]. Available: http://www.semicon.panasonic.co.jp/en/products/powerics/ganpower/#products-document. [Accessed:

[18] Elbanhawy A. Limiting cross-conduction current in synchronous buck converter designs.

[19] Christian M, Guillemant O. Simple Design Techniques for Optimizing Efficiency and Over voltage Spike of Synchronous Rectification in DC to DC Converters. Austria: Infineon;

[20] Ren Y, Xu M, Zhou J, Lee FC.Analytical loss model of power MOSFET. IEEE Transactions

Nuremberg; PCIM Europe 2017. pp. 1537-1544

142 Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

January 24, 2017]

2012

Fairchild Semiconductor; 2005

on Power Electronics. 2006;**21**(2):310-319

## *Edited by Yogesh Kumar Sharma*

SiC and GaN devices have been around for some time. The first dedicated international conference on SiC and related devices, "ICSCRM," was held in Washington, DC, in 1987. But only recently, the commercialization of SiC and GaN devices has happened. Due to its material properties, Si as a semiconductor has limitations in hightemperature, high-voltage, and high-frequency regimes. With the help of SiC and GaN devices, it is possible to realize more efficient power systems. Devices manufactured from SiC and GaN have already been impacting different areas with their ability to outperform Si devices. Some of the examples are the telecommunications, automotive/ locomotive, power, and renewable energy industries. To achieve the carbon emission targets set by different countries, it is inevitable to use these new technologies. This book attempts to cover all the important facets related to wide bandgap semiconductor technology, including new challenges posed by it. This book is intended for graduate students, researchers, engineers, and technology experts who have been working in the exciting fields of SiC and GaN power devices.

Published in London, UK © 2018 IntechOpen © pinglabel / iStock

Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications

Disruptive Wide Bandgap

Semiconductors, Related

Technologies, and Their

Applications

*Edited by Yogesh Kumar Sharma*