**1. Introduction**

The revolutionizing Internet of Things (IoT) devices connect us to a new horizon of smart wearable gadgets, home appliances, health monitors, home automation controllers, etc. According to a growth projection of IoT devices by CISCO in 2013, the number of these

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connected IoT devices could reach 50 billion by the year 2020 [1]. Among these IoT devices, a significant amount of products would be of wearable or portable categories. Thus, the portability and form factor of such smaller devices restrict the use of power source to smaller batteries. Besides, these mobile IoT devices could harvest energy from ambient light, body heat, etc. energy sources. Based on the power consumption of these IoT devices, the battery life would vary for different applications [2]. However, power storage capacity of smaller batteries, both non-rechargeable and rechargeable, is limited. Therefore, all of these so-called battery-operated portable devices are limited by the battery life, and battery replacement of millions of IoT devices per year could result in millions of dollars in replacement cost.

On the other hand, energy harvesters could transform light, radio wave, and vibration energy to electrical energy that could be a potential solution for battery life and replacement issues. However, the limited harvested power [2] from various energy sources may be insufficient to power IoT devices for applications requiring milliwatt or even hundreds of microwatts of power with the constraints of a smaller form factor. Also, guaranteed availability of energy sources may not be available for long-term application usage. Therefore, batteries remain the primary power source and choice for most of the IoT applications. However, due to self-leakage and energy consumption in IoT applications, the battery life and replacement time of IoT devices are major concerns, which last much less than the shelf-life of batteries of about 10 years. As battery energy density doubles every 10 years [3], which is much slower than Moore's law of the number of transistors doubling every 2 years [3], the low-power circuit solutions show great promises to empower IoT devices for longer battery life.

Every modern-day electronic gadget that has a digital processor in its circuit board, starting from the household micro-oven to Apple's iPhone and the commercial Amazon's cloud servers, uses a fast and power-efficient on-chip memory called the static random access memory (SRAM). The SRAM has three operations: one can write some desired data into a particular memory address location or read some data from a specific memory address or hold the written data to access in the future. Hence, the usual metrics to evaluate an SRAM are (1) the ability to write (write-ability), (2) ability to read (readability), and (3) ability to retain data (data retention) without any operation. Also, there is another metric called read stability that evaluates the stability of unselected bitcell columns while writing a data in selected columns. A simple architecture of the SRAM is given in **Figure 1(a)**, which shows it has an address bus to select an address for a write or read operation. The other pins are a data input bus DIN, a data output bus DOUT, a chip enable signal EN, a synchronous clock signal Clk, and a write and read select signal WRRD. More advanced SRAMs can have additional pins, such as test pins, write and read margin control pins, power management pins, etc. SRAMs are nonvolatile: disconnecting the power supply from the SRAM would result in loss of memory data stored previously. The SRAM typically shares the power rail with the microprocessor's digital circuits (logic core). The SRAM and microprocessor logic core can also have a separate supply rail at the cost of power rail routing, silicon area of the DC-DC converter, chip design time, and overheads. **Figure 1(b)** and **(c)** shows the two usual topologies used in system on chip (SoC) integrated circuits. The advantage of SRAM power rail topology shown in **Figure 1(b)** over **Figure 1(c)** is that it saves silicon area required by the additional onchip DC-DC converter blocks; those are usually very large compared to the other blocks in the SoC. Due to the square-law dependency of power with supply voltage, one of the best ways for

low-power operation of an SoC is to lower the supply voltage (VDD) and operate the entire digital microprocessor block at the scaled VDD. Digital logic has been demonstrated to work at subthreshold [4] supply voltages [4–6] (100 mV and lower) that is lower than the threshold voltage (VT) of bulk MOSFETs, as shown in **Figure 2**, in a MOSFET ID-VGS curve. However, the conventional 6T SRAM bitcell (**Figure 3(a)**) being a ratioed logic, which shares the same M5 and M6 transistors

**Figure 2.** Drain current (ID) vs. gate-to-source voltage (VGS) plot for an NMOS transistor showing on and off states in 130 nm bulk predictive technology model from Arizona State University. Below the threshold voltage (VT) of the

**Figure 1.** (a) SRAM architecture, (b) digital core and SRAM sharing the same rail, and (c) digital core and SRAM having

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dual-rail architecture.

MOSFET, the transistor is still operable.

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connected IoT devices could reach 50 billion by the year 2020 [1]. Among these IoT devices, a significant amount of products would be of wearable or portable categories. Thus, the portability and form factor of such smaller devices restrict the use of power source to smaller batteries. Besides, these mobile IoT devices could harvest energy from ambient light, body heat, etc. energy sources. Based on the power consumption of these IoT devices, the battery life would vary for different applications [2]. However, power storage capacity of smaller batteries, both non-rechargeable and rechargeable, is limited. Therefore, all of these so-called battery-operated portable devices are limited by the battery life, and battery replacement of millions of IoT devices per year could result in millions of dollars in replacement cost.

On the other hand, energy harvesters could transform light, radio wave, and vibration energy to electrical energy that could be a potential solution for battery life and replacement issues. However, the limited harvested power [2] from various energy sources may be insufficient to power IoT devices for applications requiring milliwatt or even hundreds of microwatts of power with the constraints of a smaller form factor. Also, guaranteed availability of energy sources may not be available for long-term application usage. Therefore, batteries remain the primary power source and choice for most of the IoT applications. However, due to self-leakage and energy consumption in IoT applications, the battery life and replacement time of IoT devices are major concerns, which last much less than the shelf-life of batteries of about 10 years. As battery energy density doubles every 10 years [3], which is much slower than Moore's law of the number of transistors doubling every 2 years [3], the low-power circuit solutions show great promises to empower IoT devices for

Every modern-day electronic gadget that has a digital processor in its circuit board, starting from the household micro-oven to Apple's iPhone and the commercial Amazon's cloud servers, uses a fast and power-efficient on-chip memory called the static random access memory (SRAM). The SRAM has three operations: one can write some desired data into a particular memory address location or read some data from a specific memory address or hold the written data to access in the future. Hence, the usual metrics to evaluate an SRAM are (1) the ability to write (write-ability), (2) ability to read (readability), and (3) ability to retain data (data retention) without any operation. Also, there is another metric called read stability that evaluates the stability of unselected bitcell columns while writing a data in selected columns. A simple architecture of the SRAM is given in **Figure 1(a)**, which shows it has an address bus to select an address for a write or read operation. The other pins are a data input bus DIN, a data output bus DOUT, a chip enable signal EN, a synchronous clock signal Clk, and a write and read select signal WRRD. More advanced SRAMs can have additional pins, such as test pins, write and read margin control pins, power management pins, etc. SRAMs are nonvolatile: disconnecting the power supply from the SRAM would result in loss of memory data stored previously. The SRAM typically shares the power rail with the microprocessor's digital circuits (logic core). The SRAM and microprocessor logic core can also have a separate supply rail at the cost of power rail routing, silicon area of the DC-DC converter, chip design time, and overheads. **Figure 1(b)** and **(c)** shows the two usual topologies used in system on chip (SoC) integrated circuits. The advantage of SRAM power rail topology shown in **Figure 1(b)** over **Figure 1(c)** is that it saves silicon area required by the additional onchip DC-DC converter blocks; those are usually very large compared to the other blocks in the SoC. Due to the square-law dependency of power with supply voltage, one of the best ways for

longer battery life.

128 Green Electronics

**Figure 1.** (a) SRAM architecture, (b) digital core and SRAM sharing the same rail, and (c) digital core and SRAM having dual-rail architecture.

low-power operation of an SoC is to lower the supply voltage (VDD) and operate the entire digital microprocessor block at the scaled VDD. Digital logic has been demonstrated to work at subthreshold [4] supply voltages [4–6] (100 mV and lower) that is lower than the threshold voltage (VT) of bulk MOSFETs, as shown in **Figure 2**, in a MOSFET ID-VGS curve. However, the conventional 6T SRAM bitcell (**Figure 3(a)**) being a ratioed logic, which shares the same M5 and M6 transistors

**Figure 2.** Drain current (ID) vs. gate-to-source voltage (VGS) plot for an NMOS transistor showing on and off states in 130 nm bulk predictive technology model from Arizona State University. Below the threshold voltage (VT) of the MOSFET, the transistor is still operable.

for write as well as read operation, faces write-ability and read stability challenges across process variation, and the minimum operating voltage (VMIN) of SRAM increases. Thus, sharing the same power rail of the logic core with SRAMs limits the voltage scaling of the SRAM with logic core for low-power operations. Additionally, with technology scaling in nanometer domain, the 14-nm FinFETs experience huge process variation [7], and the conventional high-density (HD) 6T FinFET bitcell (**Figure 3(a)**) with 1:1:1 M1:M2:M5 beta ratios has insufficient write-ability and read stability across process variation. With further technology scaling in 7 nm and smaller processes, it will be very challenging to make the conventional 6T SRAM memory to work, which

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There are mainly two available solutions to address these challenges of 6T SRAM by trading off SRAM area such as alternative bitcells and a write-read peripheral assist (PA) to improve VMIN of 6T SRAM bitcell. The alternative bitcells are a class of bitcells that has lower VMIN or lower energy consumption than the conventional 6T SRAM bitcell. A very popular alternative bitcell is 8 T bitcell, as shown in **Figure 4(a)**. Here, the write and read path are decoupled to improve the write-ability, readability, and read stability of the 8 T SRAM compared to the 6Ts. However, after a certain VDD, even alternative bitcells are inoperable, and one of the popular SRAM schemes comes into the play for further VMIN lowering: peripheral write and read assist techniques. Although the PAs reduce the worst-case SRAM VMIN, it does not remove the SRAM VMIN guardbanding across process variation, which costs additional area and energy penalty in the typical and best case dies. A couple of recently published works address this VMIN guardbanding issue by tracking it using canary sensor SRAM. The canary SRAM extends the SRAM operating range by reducing VMIN guardbanding across process variation, which promises to enable a multitude of IoT applications. This chapter will discuss aforementioned three major techniques that could enable ULP low-VMIN SRAMs for IoT applications as follows. Before delving details into these topics, we need to understand the SRAM design metrics as follows.

As discussed earlier SRAM has four different categories of design metrics such as write-ability, readability, read stability, and data retention. The first three categories of design metrics can have static and dynamic measures. Here the static measures are obtained using DC SPICE simulations, and dynamic measures are obtained using transient simulations. Static measures for write and read metrics are easy to evaluate and are widely being used to quantify the SRAM static VMIN across process and temperature corners. On the other hand, dynamic measures for write and read metrics are more accurate to represent an actual SRAM write or read operation; however, they are harder to evaluate and time-consuming. The static measures for write-ability are called write margin (WM) and write static noise margin (WSNM). Both WM and WSNM assume an infinitely long wordline pulse. The WM during a write is defined in two ways: the margin between VDD and WL while BL and BLB are fixed at VSS and VDD and the margin between VDD and BL while WL is fixed at VDD. On the other hand, WSNM has a single definition for measuring the SRAM static noise margin (SNM) when the wordline is turned on. The static measure of readability is the DC read current (Iread) drawn from the bitline while reading a bitcell. The static measure of read stability is read static noise margin (RSNM), which assumes an infinitely long wordline pulse too. The measurement technique of RSNM and WSNM using

has been there for decades.

**2. SRAM write and read design metrics**

**Figure 3.** (a) Conventional 6T SRAM and (b) its write and read waveforms.

**Figure 4.** (a) Conventional 8 T SRAM bitcell, (b) Kulkarni's 10 T bitcell, (c) Chiu's 8 T bitcell, (d) Chang's 10 T bitcell, (e) Feki's bitcell, and (f) Arijit's 9 T bitcell.

for write as well as read operation, faces write-ability and read stability challenges across process variation, and the minimum operating voltage (VMIN) of SRAM increases. Thus, sharing the same power rail of the logic core with SRAMs limits the voltage scaling of the SRAM with logic core for low-power operations. Additionally, with technology scaling in nanometer domain, the 14-nm FinFETs experience huge process variation [7], and the conventional high-density (HD) 6T FinFET bitcell (**Figure 3(a)**) with 1:1:1 M1:M2:M5 beta ratios has insufficient write-ability and read stability across process variation. With further technology scaling in 7 nm and smaller processes, it will be very challenging to make the conventional 6T SRAM memory to work, which has been there for decades.

There are mainly two available solutions to address these challenges of 6T SRAM by trading off SRAM area such as alternative bitcells and a write-read peripheral assist (PA) to improve VMIN of 6T SRAM bitcell. The alternative bitcells are a class of bitcells that has lower VMIN or lower energy consumption than the conventional 6T SRAM bitcell. A very popular alternative bitcell is 8 T bitcell, as shown in **Figure 4(a)**. Here, the write and read path are decoupled to improve the write-ability, readability, and read stability of the 8 T SRAM compared to the 6Ts. However, after a certain VDD, even alternative bitcells are inoperable, and one of the popular SRAM schemes comes into the play for further VMIN lowering: peripheral write and read assist techniques. Although the PAs reduce the worst-case SRAM VMIN, it does not remove the SRAM VMIN guardbanding across process variation, which costs additional area and energy penalty in the typical and best case dies. A couple of recently published works address this VMIN guardbanding issue by tracking it using canary sensor SRAM. The canary SRAM extends the SRAM operating range by reducing VMIN guardbanding across process variation, which promises to enable a multitude of IoT applications. This chapter will discuss aforementioned three major techniques that could enable ULP low-VMIN SRAMs for IoT applications as follows. Before delving details into these topics, we need to understand the SRAM design metrics as follows.
