*3.2.1. Chemical pathways*

Finally, using the LZ37 film UV/O<sup>3</sup>

without solvothermal treatment.

82 Green Electronics

TFTs with the thermally grown SiO<sup>2</sup>

**films and transistors**

**3.1. Introduction**

processed In-Zn-O/LaZrO [35] and In-Zn-O/SiO<sup>2</sup>

the similar channel/gate insulator interface properties.


insulator [36], indicating excellent insulating property of

(channel/gate insulator) TFTs, suggesting

, a field-effect mobility (*μ*) of

V−1 s−1) and stabil-

gate top-contact structure. The TFT exhibited a low-gate leakage current of less than 10 pA

**Figure 4.** (a) UV-vis absorption spectra of LZO precursor solutions and (b) eakage currents of LZO films with and

0.37 cm<sup>2</sup> V−1 s−1, and a subthreshold swing factor (*SS*) of 0.61 V decade−1. The off current of the drain (3–30 pA) and the gate leakage (~10 pA) were extremely low and comparable to those of

the low-temperature-processed LaZrO. The *SS* value is similar to those of high-temperature-

Inorganic semiconductors including silicon and chalcogenides have been solution-processed

ity in comparison with organic semiconductors [37, 38]. These solution-processed inorganic semiconductors, however, generally require high annealing temperature, necessary for generating crystalline phases, impurity-free, and dense structures for device-quality films.

On the contrary, in oxide semiconductors, the amorphous phases are capable of exhibiting electron mobilities comparable to those of their crystalline phase counterparts [39–41], which allow the exclusion of a high-temperature annealing process for obtaining crystalline phases. The conduction band minimum (CBM), which constitutes the electron conduction pathway, is composed of vacant metal cation s-states, and the spatial expanse of these s-states is greater than the inter-cation distances. The s-state spatial overlap is primarily determined by the principal

**3. Low-temperature solution-processed oxide semiconductor thin** 

into high-performance semiconductors that have better mobility (>10 cm<sup>2</sup>

at an operating voltage of 15 V, a large "on/off" ratio of near 10<sup>6</sup>

## *3.2.1.1. Nanomaterials-based process*

The nanoparticles (NPs)-based chemical approach is, in principle, the promising pathway for low-temperature annealed, high-performance semiconducting layers. Nevertheless, whereas the metal NPs, smaller than a few tens of nanometers, can be melted even below 200°C due to the dramatic lowering of the melting point [44, 45], the oxide NPs are not capable of undergoing the structural transformation into a granular film morphology at low temperatures, since the melting point of oxide NPs is not decreased depending on the particle size. This unique physical property of oxide NPs leads to the large surface area, porous, and poorly interconnected particulate film at low annealing temperatures, which limits device performance (low mobility and poor stability). For example, In<sup>2</sup> O3 NPs, less than 10 nm in size and spherical in shape, have been generated through chemical synthesis and implemented into device structures by ink-jet printing even at room temperature. However, the *μ* was confined to 0.8 cm<sup>2</sup> V−1 s−1 [46–48], which is associated with the inefficient carrier transport at junctions between neighboring NPs.
