**4. Nanodevices based on SOI configuration of low consumption**

The SOI structures stand for an alternative manufacturing technique for many nanodevices. An uniatomic semiconductor layer is able to be deposited onto an insulator support, since to be mechanical handled and to avoid the electrical leakage current thru substrate, [32].

When the film thickness is decreased sub-20 nm, a distinct nanostructure with a cavity was proposed. The upper source or drain zones that contain two higher undulations of the Si-n+ layer are placed onto the oxide substrate. The middle Si-p region is thinned down to 1 nm and then to 0.3 nm. The carriers transport is constrained to one by one carrier for 0.3 nm structure. Essentially, the device could be conceived as a Single Electron Transistor type, at the theoretical Introductory Chapter: Green Electronics Starting from Nanotechnologies and Organic… http://dx.doi.org/10.5772/intechopen.73312 7

**Figure 2.** The conceptual architecture of the a-NOI nanotransistor sub-10 nm with a cavity.

Sometimes the SOI device studies go to other aims: devices suitable for high temperature work regime, micro-nanosensors, [27], low power consumption, atypical SOI-MOSFET transistors, [28]. Other materials than Silicon on insulator were also intensively approached in the last period, (e.g. Germanium on oxides thin layers). The germanium growth is starting from the silicon seed and continues by wetting the SiO2 film, producing mono-crystalline layers [29].

The Nothing On Insulator (NOI) transistor is another candidate to green electronic devices. Its technology can be rather based on room temperature processes. A sub-10 nm undulated polysilicon structure on insulator, [30] can be manufactured by the Secco etching that etches especially the boundaries of the polysilicon nanoclusters, providing nanoundulated films

This undulation technology can be adapted for the NOI manufacturing, increasing the etching time, up to the Si valleys reaches the oxide. The NOI nanotransistor is a link device among vacuum transistors, SOI-MOSFETs, and Few Electron Transistors (FET), borrowing some

In a mirror relation there is placed another representative of the SOI limit devices: the Silicon

The SOI structures stand for an alternative manufacturing technique for many nanodevices. An uniatomic semiconductor layer is able to be deposited onto an insulator support, since to

When the film thickness is decreased sub-20 nm, a distinct nanostructure with a cavity was proposed. The upper source or drain zones that contain two higher undulations of the Si-n+ layer are placed onto the oxide substrate. The middle Si-p region is thinned down to 1 nm and then to 0.3 nm. The carriers transport is constrained to one by one carrier for 0.3 nm structure. Essentially, the device could be conceived as a Single Electron Transistor type, at the theoretical

be mechanical handled and to avoid the electrical leakage current thru substrate, [32].

On Nothing transistor made by special etching techniques of the Si-membrane, [31].

**4. Nanodevices based on SOI configuration of low consumption**

with top of 7 nm and valley of 3 nm thickness, **Figure 1**.

**Figure 1.** A manufactured SOI nanotransistor with maximum 7 nm.

6 Green Electronics

characteristics from all of these, but being distinct.

limit. This cavity nanodevice is presented in **Figure 2** and can associate a green implementation technology, by undulated polysilicon film. In this case, just two high rectangular undulations of Silicon are preserved on the oxide layer. Therefore it was also called almost-NOI device, [33]. The substrate electrode acts as a back-gate terminal. Due to a vacuum distance under 4 nm (xc < 4 nm), the tunneling probability between the islands - n+ – source / n+ – drain significantly increases, [34, 35].

Other recent research studies, in the field of the electron device with low power consumption, indicated an elevated interest for the pin devices as tunneling transistor or Tunnel-pin-FETs with extremely low sub-threshold slope, less than 60 mV/dec—the MOSFET physical limit, [36]. They are also based on the tunneling conduction mechanism, as a direct band to band tunneling, [37]. Other authors claimed in 2014 "Introducing the vacuum transistor: a device made of Nothing", "Transistorizing the Vacuum Tube", "A vacuum-channel transistor closely resembles an ordinary MOSFET", [38]. This NASA research group fabricated and measured a vacuum nanotransistor, [39]. However, this experimental device gets weaker performances (SS = 4 V/dec, VDS = 20 V) versus the simulated NOI characteristics, [40, 41] (SS = 650 mV/dec, VDS = 10 V). Obviously, the NOI nanotransistor has a similar work principle as these nanotransistors with vacuum that incited the international interest, [38].
