**2. The integration technologies evolution**

The nanotechnologies applied in integrated circuits give new challenge in nanometric scale structures, launching new applications or new components [13]. The traditional CMOS is more than nanoelectronics, passing rapidly from the 22 nm technology in 2012 to 10 nm technology in 2017 and toward 5 nm in 2020. Therefore, some authors claim that the future solutions require a diversification among nanocomponents, so that other devices than CMOS can restore or can be co-integrated together with CMOS circuitry to allow new functions, [14]. An extremely large palette of diversified devices is accomplished by the Silicon On Insulator (SOI) technologies [15]: from SOI-MOSFETs to radiation hardened circuits [16], up to micromachined NMEMS and sensors [17].

The classical High Temperature Annealing Separation by IMplanted OXygen (HTA SIMOX) technology still offers clean SOI wafers with 200 nm Si-film on 400 nm buried oxide (BOX), and fixed interface charges of Qox = 1010÷1012 e/cm2 , [15]. These charges are dispersed inside a thin oxide slice. Any SOI device possesses two interfaces: Si-film with BOX, and BOX with Substrate and thirdly the superior interface near gate oxide with Si-film, [18]. The classical model considers the electric charge included in first two interfaces, [15]. These fixed charges are spatially expanded inside a volume in oxide. In ultrathin SOI structures, consequently this charges can be modeled by a surface charge density, [18].

There are some distinct methods of the electrical characterization of the SOI products. If the studied SOI transistor has an uniform film, thicker than 200 nm, the classical method can be applied. In this case, the effect of the interface charges is modeled by the classical physics by VFB−C, [19]:

$$V\_{FB-C} = -\frac{Q\_{i1}}{\varepsilon\_{\alpha}} \cdot \chi\_{\alpha} - \frac{Q\_{w}}{2\,\varepsilon\_{\text{Si}}qN\_A} \tag{1}$$

where NA is the same doping concentration in film and substrate, Qi1 is the electric charge densities at upper interface, Qox is the fixed charges density, xox is the thickness of the buried oxide, εSi, εox are the dielectric permittivity respectively for silicon and for oxide, VFB-C is the classical model of the flat-band voltage. For a thick SOI film, the total charge density in BOX is Qox = Qi1 + Qi2, where Qi1 and Qi2 are the upper, respectively bottom interface charge density.

If the SOI structure has Si-film thickness less than 10 nm, the sheet interface charge belongs to a space and can be treated by the distribution theory, [20]. Assuming the Dirac δ-distribution as a limit of the regulates distribution string, Ix , [21], where xk is the spatial coordinate for Qik, k = 1 or 2 and Δx<sup>k</sup> → 0 stands for the spatial dispersion coefficients for Qi1, Qi2, the final flatband model with distributions, VFB−D, can be computed by:

$$V\_{FB-D} = -\frac{Q\_{\rm el}}{\varepsilon\_{\rm w}} \cdot \left(\chi\_{\rm av} - \frac{\Delta \mathbf{x}\_{\rm i}}{2}\right) - \frac{Q\_{\rm 2}}{2} \cdot \Delta \mathbf{x}\_{\rm z} - \frac{Q\_{\rm w}^2}{2} \frac{Q\_{\rm w}^2}{\varepsilon\_{\rm s\rm z} \cdot qN\_A} \tag{2}$$

For this model, if the spreading coefficients reset to zero (Δx1,2 = 0), the distribution (Eq. (2)) becomes the conventional (Eq. (1)).

The accurate model with distribution (Eq. (2)) shows that the effect of a fixed charges about 1012 e/cm2 , at the back interface can be neglected in a classical SOI-MOSFET with more than 200 nm Si/400 nm BOX sizes, but the same value is vital to characterize the SOI ultrathin technology of 10 nm Si/10 nm BOX.
