**5. Final test and spring pins**

The decision on how to partition test between wafer and package tests and where to focus efforts to increase parallel testing is always on the agenda of test practitioners in the industry. A wafer test probing is a short-cut in addressing both wafer test and package test, if it can be a bundled solution for productivity of the test floors. This potentially reduces total cost of test substantially. The trend nowadays is to focus on wafer sort in high parallelism mode.

diameter of the spring wire section was 0.51 mm. The contactor has a 5 mm in uncompressed total length including the plunger and the spring. The length of the spring wire section was

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The measurement results in **Figure 18** show the contact resistance behavior of the spring assembly for SS304V/Cu plated with Ni/Au contacts in a 36-Pin test socket. SS304 stands for stainless steel spring wire and Cu, Ni and Au are overplating applied to the spring to improve the electrical performance characteristics. S parameter characterization has shown better results than those of traditional spring pins. **Figure 19** shows electrical simulation results for pitches of 0.8, 1.6 and 2.5 mm are shown. Insertion loss was estimated to be at −1 dB bandwidth as 5.025 GHz (A). Return loss of −16 dB at 4 GHz is illustrated

The plunger pin and stainless steel spring wire can be manufactured with MEMS processes to

**Figure 17.** Prototype of new contactor design showing the plunger and the spring sections held in a retaining plate.

**Figure 18.** The contact resistance behavior if the plated spring contact.

make them scalable to much finer pitches than these versions can support.

0.27 mm.

at (B).

The wafer level chip scale package (WLCSP) format has been rising and in the final test, there is strong push for cost-effective RF testing solutions [9, 10]. The spring-pin technology for the final test still inexpensive workhorse of the package test industry. The system board level functionality is moving into package-level (SiP) or chip-level (SoC) implementations. The spring pins, are not scalable at fine pitches and will not support test speeds necessary.

A socket-contactor design is proposed for reliable electrical contact and allows testing for best wafer yields. This type of approach must replace known vertical probe technology or membrane probe technology for testing wafer level packages. A novel contactor and socket were designed for high performance and low-cost for use in wafer probe or final test [11].

**Figure 16** shows a socket test system overview showing a load-board and device under test (DUT) with a ball-grid-array (BGA) in contact with traditional spring pins, that is, pogo pins™. The DUT can be packaged as BGA with bumps or land grid array (LGA) and the contactor pin geometry will change depending on the pad/bump materials and contact surfaces [11].

The proposed design of new contactor is illustrated in **Figure 17** including a plunger, spring wire and the socket with a retaining plate. The contactor consists of a plunger pin made of beryllium copper and a braided stainless steel spring wire. The spring wire is typically copper over-plated. The socket materials with retaining plates were made of FR4. The overall

**Figure 16.** A pogo pin socket system overview.

diameter of the spring wire section was 0.51 mm. The contactor has a 5 mm in uncompressed total length including the plunger and the spring. The length of the spring wire section was 0.27 mm.

**5. Final test and spring pins**

202 MEMS Sensors - Design and Application

necessary.

test [11].

faces [11].

**Figure 16.** A pogo pin socket system overview.

The decision on how to partition test between wafer and package tests and where to focus efforts to increase parallel testing is always on the agenda of test practitioners in the industry. A wafer test probing is a short-cut in addressing both wafer test and package test, if it can be a bundled solution for productivity of the test floors. This potentially reduces total cost of test substantially. The trend nowadays is to focus on wafer sort in high parallelism mode. The wafer level chip scale package (WLCSP) format has been rising and in the final test, there is strong push for cost-effective RF testing solutions [9, 10]. The spring-pin technology for the final test still inexpensive workhorse of the package test industry. The system board level functionality is moving into package-level (SiP) or chip-level (SoC) implementations. The spring pins, are not scalable at fine pitches and will not support test speeds

A socket-contactor design is proposed for reliable electrical contact and allows testing for best wafer yields. This type of approach must replace known vertical probe technology or membrane probe technology for testing wafer level packages. A novel contactor and socket were designed for high performance and low-cost for use in wafer probe or final

**Figure 16** shows a socket test system overview showing a load-board and device under test (DUT) with a ball-grid-array (BGA) in contact with traditional spring pins, that is, pogo pins™. The DUT can be packaged as BGA with bumps or land grid array (LGA) and the contactor pin geometry will change depending on the pad/bump materials and contact sur-

The proposed design of new contactor is illustrated in **Figure 17** including a plunger, spring wire and the socket with a retaining plate. The contactor consists of a plunger pin made of beryllium copper and a braided stainless steel spring wire. The spring wire is typically copper over-plated. The socket materials with retaining plates were made of FR4. The overall The measurement results in **Figure 18** show the contact resistance behavior of the spring assembly for SS304V/Cu plated with Ni/Au contacts in a 36-Pin test socket. SS304 stands for stainless steel spring wire and Cu, Ni and Au are overplating applied to the spring to improve the electrical performance characteristics. S parameter characterization has shown better results than those of traditional spring pins. **Figure 19** shows electrical simulation results for pitches of 0.8, 1.6 and 2.5 mm are shown. Insertion loss was estimated to be at −1 dB bandwidth as 5.025 GHz (A). Return loss of −16 dB at 4 GHz is illustrated at (B).

The plunger pin and stainless steel spring wire can be manufactured with MEMS processes to make them scalable to much finer pitches than these versions can support.

**Figure 17.** Prototype of new contactor design showing the plunger and the spring sections held in a retaining plate.

**Figure 18.** The contact resistance behavior if the plated spring contact.

**Acknowledgements**

**Author details**

Bahadir Tunaboylu1

**References**

San Diego. S01-00. pp. 1-49

TCPMT.2011.2173493

thank SV Probe Inc. R&D members for discussions.

\* and Ali M. Soydan2

2017;**64**:1284-1290. DOI: 10.1109/TIE.2016.2615273

test, assembly and packaging times. 2010;**1**(6):1-7

\*Address all correspondence to: btunaboylu@sehir.edu.tr

We gratefully acknowledge the support by a Marie Curie International Reintegration Grant within the European Union Seventh Framework Program under Grant No. 271545. We also

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1 Istanbul Sehir University, Department of Industrial Engineering, Istanbul, Turkey

2 Gebze Technical University, Institute of Energy Technologies, Gebze-Kocaeli, Turkey

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[6] Tunaboylu B. Testing of copper pillar bumps for wafer sort. IEEE Transactions on Components, Packaging and Manufacturing Technology. 2012;**2**:985-993. DOI: 10.1109/

[7] Sperling E. Variation spreads at 10/7 nm. Semiconductor Engineering, Nov 17, 2017. Available form: https://semiengineering.com/author/esperling [Accessed: Nov 28, 2017]

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**Figure 19.** Simulation results for pitches of 0.8, 1.6 and 2.5 mm are shown. (A) Insertion loss, −1 dB bandwidth is 5.025 GHz (top). (B) Return loss of −16 dB at 4 GHz.

#### **6. Conclusions**

Wafer test systems and enabling requirements for effective testing of mixed signal, logic and memory ICs were reviewed. TSVs and 3D packaging are evolving and making silicon interposers available and high performance stacked die packages without wire-bonding. Silicon interposers using TSV technology based on MEMS processes can be utilized in probe card assemblies to enable next generation fine-pitch vertical probing. MEMS technologies are being developed for manufacturing of novel high density substrates and fine-pitch probes for cantilever as well as vertical probing. MEMS technologies already dominate the memory test market. It is clear though the overall market is trending toward MEMS technologies and purely vertical, cantilever, blade technology or others will shrink in probe card market and advanced MEMS technologies will win.
