**3. Probe technology and designs for fine-pitch probing**

Cantilever probing technologies, both traditional and MEMS-style cantilever, have limitations for multi-DUT probing at 50 μm or below. Wafer test becomes challenging because of design complexity of devices. For instance, one limit is the number of rows of bond pads that can be tested at one time, dependent heavily on pad density. Another parameter of a design test limitation with cantilever-style technologies is the corner keep-out in device layouts. Yet another requirement of this mode of technology is the need for skip DUT configurations, compromising test stepping efficiency.

is illustrated on the right. There are significant limitations to standard cantilever probes technologies as the number of rows or DUTs rises. For three rows of pads, a vertical style technology is needed for efficient probing, as shown in **Figure 4**. Traditional vertical buckling beam style probes of three different diameters (4-mil, 3-mil and 2-mil) which address different device pitch requirements in wafer test are also shown. MEMS-vertical technologies enable probing of full arrays, as shown in **Figure 5**, that are typically not feasible with conventional

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Probe action, scrub mark size and depth must be precisely controlled to prevent damage to bond pads, typically Al or Cu, and low-k dielectrics during wafer probe. Fine-pitch probing

**Figure 4.** Vertical probes, 3-row peripheral layouts on a device and illustrations of three different vertical probe designs

requires precise control of alignment at pad sizes smaller than 40 μm.

vertical probe technologies.

**Figure 3.** Cantilever design and contact pad layouts.

on a wafer.

Vertical style technology approaches allow more rows of peripheral pads and array patterns for contacts. Images of probe cards of a traditional cantilever, vertical and MEMS-memory types are illustrated in **Figure 2**. The market for devices with multiple peripheral pads is moving to finer pitches and the demand for higher levels of parallel testing is increasing for such logic configurations. These requirements are driven by higher I/O requirements, smaller device dies, longer test times and more challenging cost of test economics. It is required to probe devices at higher levels of parallelism and finer pad pitches. Pads can be arranged inline, dual or multi inline rows or staggered pads. This design space is typically not addressable by standard vertical, advanced memory cards or standard cantilever cards but a new segment for advanced fine-pitch MEMS type probe technologies. Major product families in this space at increasingly higher parallelism requirements are high-end ASICS, SoCs/high level digital signal processor (DSPs) and low-end DSPs/low-end microcontrollers.

Cantilever probe cards are used in addressing 1-row peripheral multi-DUT or 1–2 row peripheral layouts of pads on devices, as shown in **Figure 3**. Probe card with 2-row cantilever probes

**Figure 2.** Cantilever, standard vertical and MEMS type probe cards.

is illustrated on the right. There are significant limitations to standard cantilever probes technologies as the number of rows or DUTs rises. For three rows of pads, a vertical style technology is needed for efficient probing, as shown in **Figure 4**. Traditional vertical buckling beam style probes of three different diameters (4-mil, 3-mil and 2-mil) which address different device pitch requirements in wafer test are also shown. MEMS-vertical technologies enable probing of full arrays, as shown in **Figure 5**, that are typically not feasible with conventional vertical probe technologies.

Probe action, scrub mark size and depth must be precisely controlled to prevent damage to bond pads, typically Al or Cu, and low-k dielectrics during wafer probe. Fine-pitch probing requires precise control of alignment at pad sizes smaller than 40 μm.

**Figure 3.** Cantilever design and contact pad layouts.

**3. Probe technology and designs for fine-pitch probing**

ing test stepping efficiency.

192 MEMS Sensors - Design and Application

Cantilever probing technologies, both traditional and MEMS-style cantilever, have limitations for multi-DUT probing at 50 μm or below. Wafer test becomes challenging because of design complexity of devices. For instance, one limit is the number of rows of bond pads that can be tested at one time, dependent heavily on pad density. Another parameter of a design test limitation with cantilever-style technologies is the corner keep-out in device layouts. Yet another requirement of this mode of technology is the need for skip DUT configurations, compromis-

Vertical style technology approaches allow more rows of peripheral pads and array patterns for contacts. Images of probe cards of a traditional cantilever, vertical and MEMS-memory types are illustrated in **Figure 2**. The market for devices with multiple peripheral pads is moving to finer pitches and the demand for higher levels of parallel testing is increasing for such logic configurations. These requirements are driven by higher I/O requirements, smaller device dies, longer test times and more challenging cost of test economics. It is required to probe devices at higher levels of parallelism and finer pad pitches. Pads can be arranged inline, dual or multi inline rows or staggered pads. This design space is typically not addressable by standard vertical, advanced memory cards or standard cantilever cards but a new segment for advanced fine-pitch MEMS type probe technologies. Major product families in this space at increasingly higher parallelism requirements are high-end ASICS, SoCs/high level

Cantilever probe cards are used in addressing 1-row peripheral multi-DUT or 1–2 row peripheral layouts of pads on devices, as shown in **Figure 3**. Probe card with 2-row cantilever probes

digital signal processor (DSPs) and low-end DSPs/low-end microcontrollers.

**Figure 2.** Cantilever, standard vertical and MEMS type probe cards.

**Figure 4.** Vertical probes, 3-row peripheral layouts on a device and illustrations of three different vertical probe designs on a wafer.

**Figure 5.** MEMS-vertical probes for contacting an array of bumps.

The contact model for vertical probe contacts is different than cantilever-style beams. Scrub marks generated by cantilever beams by design are typically longer than marks by vertical probes. Accurate guiding of probes permits finer controls and precise scrub marks for vertical. The tolerances on guiding holes as well as probes are critical for positions.

**Figure 6** illustrates results of deflection and stress simulations for the models of cantilever probe designs and MEMS-cantilever probe designs exhibiting deflection upon pad contact and generating scrub motion on probe tips. MEMS-cantilever type designs are well suited for memory device testing up to 1–4 touchdowns for 300 mm wafers with probe counts up to 60,000 probes.

Vertical buckling beam model and MEMS-fine pitch vertical probe design contacts and simulations of deflection under load are shown in **Figure 7**. Vertical probes are typically manufactured

from Paliney 7™ or BeCu materials by stamping a wire version followed by a final finishing process. MEMS-vertical or cantilever probes are lithographically produced and involves many process steps typical in MEMS technologies. Different types of nickel alloys (Ni-Co and Ni-Mn) are commonly used for MEMS spring or probe manufacturing. Probe tips may be coated with harder alloys for better lifecycle, which may involve Pd and Pt alloys such as PdCo, PtIr, PtNi, Rh or hard gold and other alloys. It should be noted that MEMS-based vertical technology has an edge over buckling beam technologies for design flexibility for highly parallel peripheral devices as well as the accuracy of scrub signatures required for smaller pad sizes.Flip chip type area-array applications such as microprocessors, graphics chips and microcontrollers, are addressed by traditional vertical or MEMS-style vertical probe technologies. **Figure 8** shows MEMS probe products, advanced vertical probe technologies for testing full area-array (A) or testing multi-row peripheral or partial arrays (B) and advanced cantilever types for testing

**Figure 7.** Vertical buckling beam probe design and MEMS-vertical probe designs showing deflection and contacting a

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The electrical contact resistance measurements for MEMS-vertical probe technology as illustrated in **Figure 5** were performed on various emerging bump types. **Figure 9** provides the eutectic bump resistance measurements done by MEMS-vertical probes on a test

The contact resistance (Cres) was indicated to be stable at 25 μm overdrive (3 gf) for all tip sizes (9, 12, 16, 36 μm) studied. The Cres is the path resistance including connections from tester to the probe tip. The effective contact resistance of just the bump and the probe tip is

The contact resistance on copper pillar bumps is illustrated for MEMS-vertical technology in **Figure 10**. It that shows the Cres with 12 μm probe tips is much higher than those from 9 μm tips. For probes with 9 μm-tips, Cres was stable at 50 μm overdrive (5–6 gf). The copper pillars are much harder than eutectic or Sn-Ag type bumps, therefore it requires higher forces to establish good contact. However, the probe tips remain much cleaner in life testing on copper

memory devices (DRAM or flash).

estimated to be less than 0.2 Ohms.

pillars compared to solder-based bumps.

system.

pad/bump.

**Figure 6.** Cantilever probe design (conventional) and MEMS-cantilever probe designs showing deflection and scrub on pad during contact.

**Figure 7.** Vertical buckling beam probe design and MEMS-vertical probe designs showing deflection and contacting a pad/bump.

The contact model for vertical probe contacts is different than cantilever-style beams. Scrub marks generated by cantilever beams by design are typically longer than marks by vertical probes. Accurate guiding of probes permits finer controls and precise scrub marks for verti-

**Figure 6** illustrates results of deflection and stress simulations for the models of cantilever probe designs and MEMS-cantilever probe designs exhibiting deflection upon pad contact and generating scrub motion on probe tips. MEMS-cantilever type designs are well suited for memory device testing up to 1–4 touchdowns for 300 mm wafers with probe counts up to

Vertical buckling beam model and MEMS-fine pitch vertical probe design contacts and simulations of deflection under load are shown in **Figure 7**. Vertical probes are typically manufactured

**Figure 6.** Cantilever probe design (conventional) and MEMS-cantilever probe designs showing deflection and scrub on

cal. The tolerances on guiding holes as well as probes are critical for positions.

**Figure 5.** MEMS-vertical probes for contacting an array of bumps.

60,000 probes.

194 MEMS Sensors - Design and Application

pad during contact.

from Paliney 7™ or BeCu materials by stamping a wire version followed by a final finishing process. MEMS-vertical or cantilever probes are lithographically produced and involves many process steps typical in MEMS technologies. Different types of nickel alloys (Ni-Co and Ni-Mn) are commonly used for MEMS spring or probe manufacturing. Probe tips may be coated with harder alloys for better lifecycle, which may involve Pd and Pt alloys such as PdCo, PtIr, PtNi, Rh or hard gold and other alloys. It should be noted that MEMS-based vertical technology has an edge over buckling beam technologies for design flexibility for highly parallel peripheral devices as well as the accuracy of scrub signatures required for smaller pad sizes.Flip chip type area-array applications such as microprocessors, graphics chips and microcontrollers, are addressed by traditional vertical or MEMS-style vertical probe technologies. **Figure 8** shows MEMS probe products, advanced vertical probe technologies for testing full area-array (A) or testing multi-row peripheral or partial arrays (B) and advanced cantilever types for testing memory devices (DRAM or flash).

The electrical contact resistance measurements for MEMS-vertical probe technology as illustrated in **Figure 5** were performed on various emerging bump types. **Figure 9** provides the eutectic bump resistance measurements done by MEMS-vertical probes on a test system.

The contact resistance (Cres) was indicated to be stable at 25 μm overdrive (3 gf) for all tip sizes (9, 12, 16, 36 μm) studied. The Cres is the path resistance including connections from tester to the probe tip. The effective contact resistance of just the bump and the probe tip is estimated to be less than 0.2 Ohms.

The contact resistance on copper pillar bumps is illustrated for MEMS-vertical technology in **Figure 10**. It that shows the Cres with 12 μm probe tips is much higher than those from 9 μm tips. For probes with 9 μm-tips, Cres was stable at 50 μm overdrive (5–6 gf). The copper pillars are much harder than eutectic or Sn-Ag type bumps, therefore it requires higher forces to establish good contact. However, the probe tips remain much cleaner in life testing on copper pillars compared to solder-based bumps.

**Figure 8.** MEMS type advanced vertical probe technologies are used for (a) full area-array, (B) peripheral-rows or partial-array and (C) advanced cantilever probes for inline memory testing.

**4. Next generation interconnects and substrates for probing systems**

**Figure 10.** The eutectic bump resistance measurements done by MEMS-vertical probes on a test system are shown.

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**4.1. Space transformers**

Higher levels of system integration and new IC technologies allow placement of significant test resources on the probe card, such as caps or resistors to very close proximity to the DUT, device supplies, digital channels and analog test circuitry, to improve signal integrity and performance. This capability helps overcome some test limitations, and make it possible to add RF test structures, and circuits enabling high-speed loop-back solutions. These solutions help in the cost-effectiveness of the test strategy. Advanced probe cards have to be designed to support high-speed testing and cold and hot temperature testing (from −55 to 150°C). Providing robust precision contact capability enables reliable contacts on smaller die sizes with better signal fidelity. Probe structures can be manufactured in a cost-effective way by MEMS methods to enable scaling to a finer bump pitch well below 50 μm area-arrays. Probe repair concepts are available on a restricted basis and this capability usually strongly requested by wafer test houses when high number of touchdowns on wafers is required.

Substrates are typically perform the function of space transformers in advanced probe cards, routing fine pitch of a device to a larger pitch of a PCB and tester boards in wafer test systems. Although the probe count is very large, memory type probe cards can handle 200mm or 300mm wafers due to device geometries with 1 or 2 row peripheral layouts. Space trans-

Space transformers need to be able feature following requirements to support next generation advanced probe cards: (1) very low pitch fanout (30 μm), (2) high frequency operation with a high bandwidth of 3 GHz, signal length matching, low crosstalk for analog and digital

former in this case is typically a single-layer thin film on MLC.

**Figure 9.** The results from the eutectic bump resistance measurements.

**Figure 10.** The eutectic bump resistance measurements done by MEMS-vertical probes on a test system are shown.

## **4. Next generation interconnects and substrates for probing systems**

Higher levels of system integration and new IC technologies allow placement of significant test resources on the probe card, such as caps or resistors to very close proximity to the DUT, device supplies, digital channels and analog test circuitry, to improve signal integrity and performance. This capability helps overcome some test limitations, and make it possible to add RF test structures, and circuits enabling high-speed loop-back solutions. These solutions help in the cost-effectiveness of the test strategy. Advanced probe cards have to be designed to support high-speed testing and cold and hot temperature testing (from −55 to 150°C). Providing robust precision contact capability enables reliable contacts on smaller die sizes with better signal fidelity. Probe structures can be manufactured in a cost-effective way by MEMS methods to enable scaling to a finer bump pitch well below 50 μm area-arrays. Probe repair concepts are available on a restricted basis and this capability usually strongly requested by wafer test houses when high number of touchdowns on wafers is required.

#### **4.1. Space transformers**

**Figure 8.** MEMS type advanced vertical probe technologies are used for (a) full area-array, (B) peripheral-rows or

partial-array and (C) advanced cantilever probes for inline memory testing.

196 MEMS Sensors - Design and Application

**Figure 9.** The results from the eutectic bump resistance measurements.

Substrates are typically perform the function of space transformers in advanced probe cards, routing fine pitch of a device to a larger pitch of a PCB and tester boards in wafer test systems. Although the probe count is very large, memory type probe cards can handle 200mm or 300mm wafers due to device geometries with 1 or 2 row peripheral layouts. Space transformer in this case is typically a single-layer thin film on MLC.

Space transformers need to be able feature following requirements to support next generation advanced probe cards: (1) very low pitch fanout (30 μm), (2) high frequency operation with a high bandwidth of 3 GHz, signal length matching, low crosstalk for analog and digital signal, shielding, (3) high pin counts for dense device designs (> 5000), (4) large arrays, (5) path resistance <2 Ohms, (6) no skip DUT and (7) peripheral device test with ore than 3 rows of pad per side and array configuration. Some of these requirements may not possible with MLC ceramic manufacturing with extra polyimide (PI) layers. Multilayer organic substrate (MLOs) is lower cost versions, but also have similar geometric and process limitations along with some thermal test restrictions.

MLS (multilayer substrate) is proposed as a type of silicon interposer manufacturable using MEMS technology to reach these target requirements. Space transformer technology comparison is provided for fine-pitch probing applications in **Figure 11**. WST stands for wired space transformer used in standard vertical probe cards. These are quickly changing with various capability enhancing feature every year. WST, MLC and MLO are well established while MLS and other high density ST scenarios are emerging. BGA and LGA stands for ball-grid array or land grid array versions of MLC. CTE is the coefficient of thermal expansion of a material.

Substrate interconnect process flow is shown in **Figure 12**(**A**, **B**) for creation of a silicon interposer with fine pitch and its bonding onto a MLC carrier. This type of a silicon interposer allows for fine pitch top surface routing capability for fanout on a MLC. Silicon interposer will have TSVs for connecting the top to bottom side. It features a probing contact pad on the surface and a bump connection to 200 μm-pitch MLC on the other side.


MLC process may involve ceramic manufacturing process and additional polyimide (PI) process layers. Fine pitch on the surface is reached by stacking up three layers of PI. Vias on ceramic layer are routed to pad locations. As the pin count is raised, thin film layer count increases to match the required probing pads. In some cases as row count increases, then a test scheme requires skipping a DUT due to such substrate density restrictions. 3-row pad structure is shown in **Figure 13** and the pin count versus the pad density is also shown.

**Figure 12.** Substrate interconnect process flow is shown in (A) process steps for MLS and (B) substrate interconnect

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The increasing requirement for more functionality in smaller packages forces trends toward 3D packaging approaches for portability [8]. Higher routing density enabled by finer pitch flip chip technology using copper pillars is highly desirable for lower costs and

**4.2. Copper pillar bumps**

features.

**Figure 11.** The space transformer technology capabilities for advanced probe cards.

**Figure 12.** Substrate interconnect process flow is shown in (A) process steps for MLS and (B) substrate interconnect features.

MLC process may involve ceramic manufacturing process and additional polyimide (PI) process layers. Fine pitch on the surface is reached by stacking up three layers of PI. Vias on ceramic layer are routed to pad locations. As the pin count is raised, thin film layer count increases to match the required probing pads. In some cases as row count increases, then a test scheme requires skipping a DUT due to such substrate density restrictions. 3-row pad structure is shown in **Figure 13** and the pin count versus the pad density is also shown.

#### **4.2. Copper pillar bumps**

signal, shielding, (3) high pin counts for dense device designs (> 5000), (4) large arrays, (5) path resistance <2 Ohms, (6) no skip DUT and (7) peripheral device test with ore than 3 rows of pad per side and array configuration. Some of these requirements may not possible with MLC ceramic manufacturing with extra polyimide (PI) layers. Multilayer organic substrate (MLOs) is lower cost versions, but also have similar geometric and process limitations along

MLS (multilayer substrate) is proposed as a type of silicon interposer manufacturable using MEMS technology to reach these target requirements. Space transformer technology comparison is provided for fine-pitch probing applications in **Figure 11**. WST stands for wired space transformer used in standard vertical probe cards. These are quickly changing with various capability enhancing feature every year. WST, MLC and MLO are well established while MLS and other high density ST scenarios are emerging. BGA and LGA stands for ball-grid array or land grid array versions of MLC. CTE is the coefficient of thermal expansion of a material. Substrate interconnect process flow is shown in **Figure 12**(**A**, **B**) for creation of a silicon interposer with fine pitch and its bonding onto a MLC carrier. This type of a silicon interposer allows for fine pitch top surface routing capability for fanout on a MLC. Silicon interposer will have TSVs for connecting the top to bottom side. It features a probing contact pad on the

surface and a bump connection to 200 μm-pitch MLC on the other side.

**Figure 11.** The space transformer technology capabilities for advanced probe cards.

with some thermal test restrictions.

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The increasing requirement for more functionality in smaller packages forces trends toward 3D packaging approaches for portability [8]. Higher routing density enabled by finer pitch flip chip technology using copper pillars is highly desirable for lower costs and

and the mechanical properties of bump materials as well as the probe tip geometry and probe force [6]. Fine-pitch technologies for ICs below 40-nm node are accelerating the move toward copper pillar lead-free bumps and interconnections. Probing lead-free solder micro-bumps or copper pillars at 40 μm-array pitch requires MEMS-style probe technologies. There are many known benefits of using copper pillars reported in the literature. **Figure 14** shows images of copper pillars and lead-free micro-bumps at 50 μm pitch. The bump profile on the right illustrates a minor scrub mark, 9 μm wide, on top of the Cu-pillar. In this case, the probe makes good and reliable electrical contact, however, the scrub signature is not easily seen on optical images because of the hardness of copper. **Figure 15** illustrates Sn-Ag based solder microbumps on top a copper pillar before and after probing at 50 μm pitch. The solder deformation is observed on the probed bump on the image on the left side. The solder bumps on the left

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**Figure 14.** Images of copper pillars and lead-free micro-bumps at 50 μm pitch. The profile shows the pillar bump after

**Figure 15.** Solder micro-bumps illustrated on the left have no copper pillar-base. Solder micro-bumps on top a copper

are of eutectic type.

probing with vertical MEMS probe technology.

pillar before and after probing (on the right) at 50 μm pitch.

**Figure 13.** Density on substrates is illustrated for various configurations.

scalability. Copper pillar bumps typically consist of a copper base and a solder capped top [6]. These copper pillars, sometimes called high pillars or micro-bumps, act as an interconnect structure which lowers stress on low-k layers in finer silicon nodes and increase reliability. Use of such micro-bumps simplifies substrates for packages, thereby decreasing cost, and allows natural migration toward TSV technologies of the future. On the other hand, as the metallurgy of the bump structure changes from eutectic to lead-free solders and more importantly to solder-cap on copper pillars with varying contact geometries, probing very fine-pitch bumps presents new test, process and precision challenges [8]. There is also an increasing trend toward performing the final test in wafer level to reduce both cycle time and cost of test while moving to environment friendly manufacturing processes. It is important for IC design and packaging development and test engineers to understand the material impacts of new wafer bumping system and technology. They need to address both reliability and manufacturability of the entire process, which includes test process development early in the cycle so that the overall system level cost is optimized [8].

Probing of traditional solder bumps at 120 μm pitch or above, whether eutectic, high-lead or lead-free solder balls are performed typically by buckling beam/vertical technologies. The contact area formed on the top of a round bump after a probe contact is related to the metallurgy and the mechanical properties of bump materials as well as the probe tip geometry and probe force [6]. Fine-pitch technologies for ICs below 40-nm node are accelerating the move toward copper pillar lead-free bumps and interconnections. Probing lead-free solder micro-bumps or copper pillars at 40 μm-array pitch requires MEMS-style probe technologies. There are many known benefits of using copper pillars reported in the literature. **Figure 14** shows images of copper pillars and lead-free micro-bumps at 50 μm pitch. The bump profile on the right illustrates a minor scrub mark, 9 μm wide, on top of the Cu-pillar. In this case, the probe makes good and reliable electrical contact, however, the scrub signature is not easily seen on optical images because of the hardness of copper. **Figure 15** illustrates Sn-Ag based solder microbumps on top a copper pillar before and after probing at 50 μm pitch. The solder deformation is observed on the probed bump on the image on the left side. The solder bumps on the left are of eutectic type.

**Figure 14.** Images of copper pillars and lead-free micro-bumps at 50 μm pitch. The profile shows the pillar bump after probing with vertical MEMS probe technology.

scalability. Copper pillar bumps typically consist of a copper base and a solder capped top [6]. These copper pillars, sometimes called high pillars or micro-bumps, act as an interconnect structure which lowers stress on low-k layers in finer silicon nodes and increase reliability. Use of such micro-bumps simplifies substrates for packages, thereby decreasing cost, and allows natural migration toward TSV technologies of the future. On the other hand, as the metallurgy of the bump structure changes from eutectic to lead-free solders and more importantly to solder-cap on copper pillars with varying contact geometries, probing very fine-pitch bumps presents new test, process and precision challenges [8]. There is also an increasing trend toward performing the final test in wafer level to reduce both cycle time and cost of test while moving to environment friendly manufacturing processes. It is important for IC design and packaging development and test engineers to understand the material impacts of new wafer bumping system and technology. They need to address both reliability and manufacturability of the entire process, which includes test process development early in the cycle so that the overall system level cost

**Figure 13.** Density on substrates is illustrated for various configurations.

Probing of traditional solder bumps at 120 μm pitch or above, whether eutectic, high-lead or lead-free solder balls are performed typically by buckling beam/vertical technologies. The contact area formed on the top of a round bump after a probe contact is related to the metallurgy

is optimized [8].

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**Figure 15.** Solder micro-bumps illustrated on the left have no copper pillar-base. Solder micro-bumps on top a copper pillar before and after probing (on the right) at 50 μm pitch.
