**2. Trends in silicon and systems for test**

The cost of scaling is rapidly increasing and the expected development cost for systemon-chip (SoC) for 10 nm is 400M USD and for 7 nm it is projected to be approaching 600M USD [2]. This means that it requires multibillion dollar lifetime revenue to be economically feasible per design. System solutions need to balance performance, power and cost. The industry of moving to 3D architectures adds challenges in variability in manufacturing next generation devices, requires more stringent variability control by data analytics and Industry 4.0 applications [7]. Advanced packaging also adds multiple levels and variability can happen across multiple die, as memory chip stack with through-silicon vias (TSVs) placed on a logic device which is integrated to a substrate with copper pillar bumps, SnAg bumps or micro-bumps. At 10 nm process node, 3D TSVs are projected to be at 6 μm diameter with depth of 55 μm [2]. Logic-memory integration improves the bandwidth and provides higher performance per watt while SoC partitioning increases yield and helps cost optimization. In a total package stack-up, thin silicon layers become an issue due to low-k modulus reliability while the substrate can become subjected to a thermal mismatch stress and induced warpage problems, as well as routability issues.

The cost is increasing with decreasing pitch, increasing probe count and increasing parallelism. The area-array type of logic test is challenging below 100 μm bump pitch and push for MEMS type of probe solutions are required to scale with the technology. Design for tests (DFTs) with wrappers are targeted to reduce number of I/O's that need to be contacted during test. Also, the ability to reuse testers is also studied to lower the total cost of test. A test system architecture with vertical style probe card is shown is **Figure 1**. In the system, ST stands for space transformer, multilayer ceramic substrate (MLC) and device under test (DUT).

When the roadmaps for probe card requirements are reviewed, there are many critical test system parameters that must be considered especially for large-sized highly parallel cards. They are mainly:

• Controlled overdrive

the probing and test side of the equation forces development of newer probes, interposers, interconnects and robust assembly systems [2, 3]. As 3D IC packaging is becoming mature, there is a strong push toward 3D IC Si integration. In a 3D IC integration, some of the chips, a microdisplay, microelectromechanical systems (MEMSs), memory, microprocessor, application-specific IC (ASIC), micro-controller unit, digital signal processor, microbattery and analog-to digital mixed signal are combined and stacked in three dimensions [4, 5]. These system and component level challenges are being addressed by silicon carriers or 3D-stacking, interposers, substrates and newer probe materials by MEMS processes. Developing a common intermediate board for a substrate or space transformer and probe card assembly will help solve technical challenges and reduce cost of test in both wafer and package level testing. An optimal design, which includes the IC design, the automated test equipment (ATE) test cell and the probe card solution, of the test flow between wafer sort and final test can yield benefits. Standard vertical probing technologies use microfabrication technologies for probes, templates and substrate-ceramic packages [6]. Pitches below 50 μm pose enormous challenges on fabrication of probe card components and nanotechnology and MEMS processes are required for producing probes, carrier or substrate structures for precision requirements. Probe structures must be designed with precision and their power delivery properties must be optimized. Advanced probe cards must be able to support high-speed testing and cold and hot temperature cycle testing with precision contact capability. They also need to address contact challenges for multi-row pads/bumps, full array Cu-pillar micro-bumps with various solder-bump metallurgies at temperature. Application of various technology approaches in test systems against the test

requirements of silicon logic or memory or mixed signal devices is discussed.

stress and induced warpage problems, as well as routability issues.

The cost of scaling is rapidly increasing and the expected development cost for systemon-chip (SoC) for 10 nm is 400M USD and for 7 nm it is projected to be approaching 600M USD [2]. This means that it requires multibillion dollar lifetime revenue to be economically feasible per design. System solutions need to balance performance, power and cost. The industry of moving to 3D architectures adds challenges in variability in manufacturing next generation devices, requires more stringent variability control by data analytics and Industry 4.0 applications [7]. Advanced packaging also adds multiple levels and variability can happen across multiple die, as memory chip stack with through-silicon vias (TSVs) placed on a logic device which is integrated to a substrate with copper pillar bumps, SnAg bumps or micro-bumps. At 10 nm process node, 3D TSVs are projected to be at 6 μm diameter with depth of 55 μm [2]. Logic-memory integration improves the bandwidth and provides higher performance per watt while SoC partitioning increases yield and helps cost optimization. In a total package stack-up, thin silicon layers become an issue due to low-k modulus reliability while the substrate can become subjected to a thermal mismatch

**2. Trends in silicon and systems for test**

190 MEMS Sensors - Design and Application


**Figure 1.** Probe card system architecture is shown.
