1. Introduction

Stating optimization as a usual phenomenon is a bit of exaggeration, which includes economic development to engineering strategy as well as job scheduling to resource allocation. The intention of optimization is certainly to produce comparable outcomes under specified conditions bearing some parametric minimization or maximization. In VLSI physical design context

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

numerous parameters are needed to be optimized like transistor count, power delay product, interconnect delay.

et al. [8]. Again a PSO algorithm was proposed by Liu et al. [9] to reduce binding during routing where this version of PSO algorithm was successful in reducing the binding problem but in turn it increased the cost of the wire lengths. Among many other proposed algorithm, the one proposed by Shen et al. [10] has some important significance which dealt with the selfadaptive technique of inertia weight update. Many other technique based on SI has been used for escalation of VLSI routing, among them the one proposed by Arora and Moses is important. Both Manhattan as well as a non- Manhattan routing scheme based on Ant Colony Optimization (ACO) [11] were proposed by the duo. A proposal was introduced by Ayob

Performance Comparison of PSO and Its New Variants in the Context of VLSI Global Routing

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Two algorithms centered on inertia weighted PSO (PSO-W) [13] are presented in here. In the prior one, named as Self-Adaptive acceleration coefficient PSO (PSO-SAAC), the acceleration coefficients are adjusted by the means of an adaptive procedure of local search and global search to heighten the property of the searching technique composed with efficient converging rate. Additional new tactic is implemented where the perception of the genetic algorithm is hybridized with PSO-W by comprising a component related with a breading factor in the position update characteristic equation of PSO-W. In supplement to the above two alternatives of PSO, PSO with constriction factor (PSO-C) [14] are evaluated with these algorithms, most lately familiarized, on a mutual platform of optimization of VLSI global routing. Further all the algorithms are verified

The remaining chapter is arranged accordingly. Section 2 portrays the elementary theory of VLSI Global routing, RMST and PSO. In Section 3 algorithms variants on PSO-W are illustrated in specifics shadowed by the implementation of modified PSO algorithms in Section 4. Section 5 confers the experimental results acquired in context to VSLI global routing and lastly the chapter

VLSI routing in Physical Design context initiates with the procedure of interconnections amongst the circuit blocks and pins, specified according to the net list, generate results in the

Conventionally, the routing fashion can be broadly cleft into two main stages: the initial stage, also called as the "Global Routing" allocates a list of routing areas for individual net, putting aside the absolute geometrical blueprint of wires; whereas, the secondary stage, called as "Detailed Routing", finds the absolute geometrical blueprint of any net within the allocated routing areas. The purpose of the routing problem is to curtail the wire length, at the same time accommodating the timing budget for the critical nets. Global routing is the initial phase of routing

et al to evade VLSI routing scheme by using Firefly optimization [12].

in several distribution topologies of VLSI terminal nodes in a definite search area.

phase of placement. The inputs to the general routing problem are as follows:

gets concluded with Section 6.

2.1. Global routing in VLSI physical design

• Timing budget for the critical nets.

• RC delay of per unit length of metal layers and vias.

2. Preliminaries

• Net list.

Conferring to Moore's Law, the transistor count doubles up in every 18 months [1]. Since the dimensions of the transistors are radically diminishing by the contemporary ages as a result of massive development in technologies, additional transistors are getting assimilated in that single chip region than before by means of cutting-edge assembling techniques. Therefore the length of interconnect has also been considerably amplified. Previously it was sufficient to overhaul the gate delay but interconnect delay has been more noticeable after the 130 nm technological node was pioneered.

The objective of VLSI physical design is to optimize the devices arrangements and interconnection schemes among these devices for desired performance.

Wire-length approximation of interconnects is considered in the routing phase of VLSI physical design process, which is largely categorized into Global Routing and Detailed Routing. In Global routing phase the circuit interconnections in shortest possible wavelength and minimum interconnect delay is required to be achieved. The complexities of global routing problem is solved to some extent with sequential approach where VLSI nets are sequenced according to their criticality and practical routers employs improvement phase. Technique of rerouting after ripping interfering wires [2] and 'shove-aside' technique [3] and also introducing concurrent approach where parallel integer programming concept are tried for enhancement of global routing but with limitations.

The Routing problem of VLSI physical design can also be mapped in classical Graph Theory where wire-length minimization of interconnected nodes rests in solving the Rectilinear Minimal Steiner Tree Problem (RMST) [4], a renowned NP Complete problem of Graph Theory. Such NP complete problems can be aimed to solve by a division of Artificial Intelligence known as Swarm Intelligence. Swarms interact among themselves to persist in any situation. It has been observed that these social agents have restricted competences of their own as an individual, however as an assemblage they are capable of accomplishing an assignment, somewhat perceptively for their existence. Scientists and engineers were ardent to mimic these activities of these natural swarm systems. Swarm intelligence was maidenly commenced in 1989 by G Beni and J Wang [5] to crack some practical problems associated to global optimization. These algorithms are heuristics and meta-heuristics in character. Heuristic infers "to ascertain by trial and error". These approaches are fairly beneficial in obtaining optimal solution or near optimal solution aimed at a complex optimization problem (like NP-complete problems) within a judicious time frame. Meta-heuristics ("meta" means "beyond" or "higher level") conversely execute even better than heuristic algorithms herein because they comprise of precise compromises related to randomization & local search. One such prevalent metaheuristics algorithm is PSO (Particle Swarm Optimization) [6].

In VLSI system for solving the Routing problem the researcher Dong et al. [7] used PSO in 2009. The proposal by the authors was mainly novel encoding and updating schemes for a discrete or binary version of PSO where Interconnect delay is one of the most important disadvantage. A routing scheme based on PSO combined with buffer insertion at suitable intervals, was taken into consideration for overcoming the disadvantage, as proposed by Ayob et al. [8]. Again a PSO algorithm was proposed by Liu et al. [9] to reduce binding during routing where this version of PSO algorithm was successful in reducing the binding problem but in turn it increased the cost of the wire lengths. Among many other proposed algorithm, the one proposed by Shen et al. [10] has some important significance which dealt with the selfadaptive technique of inertia weight update. Many other technique based on SI has been used for escalation of VLSI routing, among them the one proposed by Arora and Moses is important. Both Manhattan as well as a non- Manhattan routing scheme based on Ant Colony Optimization (ACO) [11] were proposed by the duo. A proposal was introduced by Ayob et al to evade VLSI routing scheme by using Firefly optimization [12].

Two algorithms centered on inertia weighted PSO (PSO-W) [13] are presented in here. In the prior one, named as Self-Adaptive acceleration coefficient PSO (PSO-SAAC), the acceleration coefficients are adjusted by the means of an adaptive procedure of local search and global search to heighten the property of the searching technique composed with efficient converging rate. Additional new tactic is implemented where the perception of the genetic algorithm is hybridized with PSO-W by comprising a component related with a breading factor in the position update characteristic equation of PSO-W. In supplement to the above two alternatives of PSO, PSO with constriction factor (PSO-C) [14] are evaluated with these algorithms, most lately familiarized, on a mutual platform of optimization of VLSI global routing. Further all the algorithms are verified in several distribution topologies of VLSI terminal nodes in a definite search area.

The remaining chapter is arranged accordingly. Section 2 portrays the elementary theory of VLSI Global routing, RMST and PSO. In Section 3 algorithms variants on PSO-W are illustrated in specifics shadowed by the implementation of modified PSO algorithms in Section 4. Section 5 confers the experimental results acquired in context to VSLI global routing and lastly the chapter gets concluded with Section 6.
