**3. Dynamic random access memory (DRAM)**

Economical and faster dynamic random access memories (DRAMs) have been widely used in all kinds of electronic devices. DRAMs have found extensive application; their mass production embarks the maturity of a semiconductor technology, which is continuously driven to give smaller dimension devices. A new semiconductor technology era having a relatively higher yield has led to the mass production of novel DRAM-generation structures. DRAM refers to a volatile memory, that is, data stored have to be dynamically refreshed to generate a correct memory data value. DRAM bits are randomly accessible compared to a conventional tape recorder. Read and write operations are necessary for DRAM cells. For reading a DRAM cell, row addresses are sent to row decoders in order to select the cell to be read by activating the necessary word line driver. When one of the word line drivers is high, the turned-on DRAM cell capacitance will charge the bit line capacitance, forming a voltage in the range of 100–200 mV [10].

In order to amplify the bit line voltage value and recover the stored data, sense amplifier is used. One sense amplifier is connected to multiple cells; hence a large amount of data is available at the same time, and large data are divided into pages, which can be accessed simultaneously. To indicate the completion of reading process, word line is turned on to isolate the DRAM cell from the bit lines. A write operation follows the similar process, with a global bit line giving the row address to the decoder and local bit lines of the cell are activated. With the help of sense amplifiers, VDD or "0" are written into the cell. A refresh operation is required to compensate for the leakage current and to refurbish the storage cell value of the cell as it elapses gradually with time. For refresh process, column access is not required as compared to the read process. First-stage sense amplifiers easily refresh the memory cells [12].

The number of data bits per unit area is the area efficiency of a memory array. It is one of the essential parameters of a memory cell along with access times. These parameters determine the overall storage capacity and memory cost per bit. Access time is essential in determining the time required to store and/or retrieve data from the memory array. Access time helps in the determination of the speed of the memory array cell structure. Power consumption both static and dynamic is also a significant factor of the design. In this section, we would instigate various types of DRAM cells with speed and power consumption comparison being carried out between the designs. A new DRAM cell design has been described which considerably improves the speed of DRAM. The improvement in data rate consists of improvement in read access time, write access time, and retention time. These improvements will help in gaining a DRAM cell design that will be capable of giving a high performance in terms of delay and power consumptions [11, 12].

## **3.1. Different DRAM cells**

Different DRAM cell designs based on their power and retention time are analyzed. Different DRAM cell designs are as follows:


In **Figure 6**, the SNM variation of different SRAM cells with cell ratio is shown. It can be concluded from the graph that the noise tolerance of 8T SRAM cell is more than the other two cells [9].

Economical and faster dynamic random access memories (DRAMs) have been widely used in all kinds of electronic devices. DRAMs have found extensive application; their mass production embarks the maturity of a semiconductor technology, which is continuously driven to give smaller dimension devices. A new semiconductor technology era having a relatively higher yield has led to the mass production of novel DRAM-generation structures. DRAM refers to a volatile memory, that is, data stored have to be dynamically refreshed to generate a correct memory data value. DRAM bits are randomly accessible compared to a conventional tape recorder. Read and write operations are necessary for DRAM cells. For reading a DRAM cell, row addresses are sent to row decoders in order to select the cell to be read by activating the necessary word line driver. When one of the word line drivers is high, the turned-on DRAM cell capacitance will charge the

In order to amplify the bit line voltage value and recover the stored data, sense amplifier is used. One sense amplifier is connected to multiple cells; hence a large amount of data is available at the same time, and large data are divided into pages, which can be accessed simultaneously. To indicate the completion of reading process, word line is turned on to isolate the DRAM cell from the bit lines. A write operation follows the similar process, with a global bit line giving the row address to the decoder and local bit lines of the cell are activated. With the help of sense amplifiers, VDD or "0" are written into the cell. A refresh operation is required to compensate for the leakage current and to refurbish the storage cell value of the cell as it elapses gradually with time. For refresh process, column access is not required as compared

to the read process. First-stage sense amplifiers easily refresh the memory cells [12].

The number of data bits per unit area is the area efficiency of a memory array. It is one of the essential parameters of a memory cell along with access times. These parameters determine the overall storage capacity and memory cost per bit. Access time is essential in determining

**3. Dynamic random access memory (DRAM)**

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**Figure 6.** Cell ratio versus static noise margin.

bit line capacitance, forming a voltage in the range of 100–200 mV [10].


These DRAM structures differ in the form of a number of transistors, area occupied. All these different designs have different structures and properties. The first three DRAM architectures use parasitic capacitance to store data values while the last one utilizes gated diodes to store the values. These gated diodes are generally formed from N-type metal oxide semiconductor field-effect transistor (MOSFET), but in order to reduce the power dissipation, P-type MOSFET can be utilized in their place. The advantage of this modification has been shown in comparing the various DRAM structures based on power consumption (during full cycle operation of write "0," read "0," write "1" and read "1"), write access time, read access time, and retention time (refresh time) (**Figure 7**).

#### **3.2. Performance comparison**

A new cell structure with a P-type MOSFET as a gated diode working as a capacitor has been compared on the basis of data rate and power consumption with the already existing DRAM cell structures. This gated diode cell structure is much faster than the already existing cell structures. All the cell structures are compared in an identical environment with their simulation profile as described in **Table 2**. Write and read operations are carried out on these cell structures, and their performances have been compared in **Table 3**. **Figure 8** shows the operation read-write waveform [14, 15].

#### *3.2.1. Analysis of DRAM designs*

Power consumption and access times decrease the P-3T1D DRAM cell, hence making it a faster and a low power cell as compared to the other variations. While the retention time also tends to decrease slightly, this means the memory has to be refreshed after a slightly smaller duration [11].

**Figure 7.** (a) 1T1C DRAM cell, (b) 3T DRAM cell, (c) 4T DRAM cell, and (d) 3T1D DRAM cell [13].


or the time after which the cell needs to be refreshed while the traditional cell has a very small retention time; it is quite comparable with the already existing gated diode-based

**Parameter 4T DRAM 3T DRAM N-3T1D DRAM P-3T1D DRAM** Average power consumption (μW) 2.384711 2.262632 2.170092 2.149554 Write access time (ps) 37.45 20.89 385.45 312.69 Read access time (ps) 71.19 70.7 68.65 44.89 Retention time (μs) 2.45621 3.49827 40.07223 33.716

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The layout of P-3T1D cell is drawn on a 250-nm technology occupying an area of 1139.29 μm2

The layout is drawn on LEDIT and it perfectly resembles the circuit implementation as being

A full memory is being implemented using the P-3T1D DRAM cell. The memory consists of a writing decoder, a reading decoder, 16 instances of P-3T1D DRAM cell, and four instances of output cell-reading circuitry. This output cell-reading circuitry consists of a precharge cir-

.

DRAM cell.

**Figure 8.** Read-write waveform.

**3.3. Layout for P-3T1D DRAM cell**

verified by layout versus schematic verification (**Figure 9**).

**Table 3.** Parameter comparison for DRAM cell simulation results.

cuitry and a gated diode sense amplifier (**Figure 10**).

**3.4. Full 16-bit memory subsystem using P-3T1D DRAM cell**

**Table 2.** Working operation of cells.

Power consumption for the proposed cell is less than the existing cells. However, the write access time is quite comparable to gated diode type DRAM cell. Read access time is almost 50% less than traditional 3T and 4T DRAM cells and approximately 34% less than N-3T1D DRAM cell. One of the most important parameters for DRAM cell is the retention time


**Table 3.** Parameter comparison for DRAM cell simulation results.

**Figure 8.** Read-write waveform.

Power consumption for the proposed cell is less than the existing cells. However, the write access time is quite comparable to gated diode type DRAM cell. Read access time is almost 50% less than traditional 3T and 4T DRAM cells and approximately 34% less than N-3T1D DRAM cell. One of the most important parameters for DRAM cell is the retention time

**Operation Time period (ns)**

**Figure 7.** (a) 1T1C DRAM cell, (b) 3T DRAM cell, (c) 4T DRAM cell, and (d) 3T1D DRAM cell [13].

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WRITE "1" 2–3 READ "1" 4–5 WRITE "0" 6–7 READ "0" 8–9

**Table 2.** Working operation of cells.

or the time after which the cell needs to be refreshed while the traditional cell has a very small retention time; it is quite comparable with the already existing gated diode-based DRAM cell.

#### **3.3. Layout for P-3T1D DRAM cell**

The layout of P-3T1D cell is drawn on a 250-nm technology occupying an area of 1139.29 μm2 . The layout is drawn on LEDIT and it perfectly resembles the circuit implementation as being verified by layout versus schematic verification (**Figure 9**).

#### **3.4. Full 16-bit memory subsystem using P-3T1D DRAM cell**

A full memory is being implemented using the P-3T1D DRAM cell. The memory consists of a writing decoder, a reading decoder, 16 instances of P-3T1D DRAM cell, and four instances of output cell-reading circuitry. This output cell-reading circuitry consists of a precharge circuitry and a gated diode sense amplifier (**Figure 10**).

**Figure 9.** P-3T1D layout on 250 nm.

**Figure 10.** 16-bit memory using P-3T1D.

There are eight address lines AD0–AD7. AD0 and AD1 are used to select a bit cell from Column 1. AD2 and AD3 are used to select a bit cell from Column 2. AD4 and AD5 are used to select a bit cell from Column 3. AD6 and AD7 are used to select a bit cell from Column 4. WBL0, WBL1, WBL2, and WBL3 are 4-bit write data lines that are used in this memory cell subsystem design (**Figure 11**). RBL0, RBL1, RBL2, and RBL3 are 4-bit read data lines that are used in this memory cell subsystem design (**Figure 12**). RWL is used to control read operation turned 1 to read. WWL is used to control write operation turned 1 to write. The time for execution of the circuit is 0–50 ns. In these data 1, 0, 1, and 0 is written into CELL0, CELL 5, CELL 10, and CELL 15, respectively.

For the time period 20–30 ns, PRECHARGE is high, reading and writing both turned off, and

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For the time period 30–40 ns, PRECHARGE is low, writing is turned off. Reading is on as READ WORD LINE is turned on. Address line selects the cells. Using the reading decoder and address lines, data are read from the CELLS 0, 5, 10, and 15 and transferred to the output

For the time period 40–50 ns, PRECHARGE is high after performing sensing and amplification of the required data. Data are read from READ BIT LINES 0, 1, 2, and 3 together (**Figure 13**).

data are stored in the cell.

**Figure 12.** Reading waveform.

**Figure 11.** Writing waveform.

circuitry of the required column.

For the time period 0–10 ns, reading and writing are both turned off and PRECHARGE is at one.

For the time period 10–20 ns, PRECHARGE is low, writing is turned on, reading is off, and address line selected the cells. Using the writing decoder and address lines, data from write bit line are written onto the CELLS 0, 5, 10, and 15.

**Figure 12.** Reading waveform.

There are eight address lines AD0–AD7. AD0 and AD1 are used to select a bit cell from Column 1. AD2 and AD3 are used to select a bit cell from Column 2. AD4 and AD5 are used to select a bit cell from Column 3. AD6 and AD7 are used to select a bit cell from Column 4. WBL0, WBL1, WBL2, and WBL3 are 4-bit write data lines that are used in this memory cell subsystem design (**Figure 11**). RBL0, RBL1, RBL2, and RBL3 are 4-bit read data lines that are used in this memory cell subsystem design (**Figure 12**). RWL is used to control read operation turned 1 to read. WWL is used to control write operation turned 1 to write. The time for execution of the circuit is 0–50 ns. In these data 1, 0, 1, and 0 is written into CELL0, CELL 5,

For the time period 0–10 ns, reading and writing are both turned off and PRECHARGE is at one. For the time period 10–20 ns, PRECHARGE is low, writing is turned on, reading is off, and address line selected the cells. Using the writing decoder and address lines, data from write

CELL 10, and CELL 15, respectively.

**Figure 10.** 16-bit memory using P-3T1D.

**Figure 9.** P-3T1D layout on 250 nm.

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bit line are written onto the CELLS 0, 5, 10, and 15.

For the time period 20–30 ns, PRECHARGE is high, reading and writing both turned off, and data are stored in the cell.

For the time period 30–40 ns, PRECHARGE is low, writing is turned off. Reading is on as READ WORD LINE is turned on. Address line selects the cells. Using the reading decoder and address lines, data are read from the CELLS 0, 5, 10, and 15 and transferred to the output circuitry of the required column.

For the time period 40–50 ns, PRECHARGE is high after performing sensing and amplification of the required data. Data are read from READ BIT LINES 0, 1, 2, and 3 together (**Figure 13**).

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**Figure 13.** Final read output.
