Author details

Soheil Salari1 , Francois Chan<sup>2</sup> \* and Yiu-Tong Chan<sup>2</sup>

\*Address all correspondence to: chan-f@rmc.ca

1 Calian Group, Kingston, ON, Canada

2 Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada

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Kingston, ON, Canada

, Francois Chan<sup>2</sup>

1 Calian Group, Kingston, ON, Canada

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\*Address all correspondence to: chan-f@rmc.ca

\* and Yiu-Tong Chan<sup>2</sup>

124 Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

2 Department of Electrical and Computer Engineering, Royal Military College of Canada,

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**Chapter 6**

**Provisional chapter**

**High-Speed Electronic Memories and Memory**

**High-Speed Electronic Memories and Memory** 

DOI: 10.5772/intechopen.76257

Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of highspeed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its

In today's modern evolving electronics, manufacturing semiconductor memory technology is an essential element. Normally, based on semiconductor technology, memories, which are being used in any equipment, use processor in one form or the other. Processors have recently become much popular with an increasing number of multiprocessor system being fabricated on a single chip to increase the performance of a system. In order to support this system, memory technology needs to be escalated to compete with processor technology. An additional driver has been endowed with the fact that the software associated with the processors and computers has become more sophisticated and much larger, and this too has greatly

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

**Subsystems**

**Abstract**

**1. Introduction**

**Subsystems**

Prateek Asthana and Loveneet Mishra

Prateek Asthana and Loveneet Mishra

http://dx.doi.org/10.5772/intechopen.76257

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

implementation in a practical 16-bit memory subsystem.

**Keywords:** SRAM, DRAM, memory subsystem, P-3TD, static noise margin


#### **High-Speed Electronic Memories and Memory Subsystems High-Speed Electronic Memories and Memory Subsystems**

DOI: 10.5772/intechopen.76257

Prateek Asthana and Loveneet Mishra Prateek Asthana and Loveneet Mishra

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.76257

#### **Abstract**

[27] Gezici S, Tian Z, Giannakis GB, Kobayashi H, Molisch AF, Poor H, Sahinoglu Z. Localization via ultra-wideband radios: A look at positioning aspects for future sensor net-

[28] Schmitz J, Mathar R, Dorsch D. Compressed time difference of arrival based emitter localization. In: Proceedings of the International Workshop on Compressed Sensing Theory and its Applications to Radar Sonar and Remote Sensing (CoSeRa); 2015. pp. 263-267

[29] Velasco J, Pizarro D, Macias-Guarasa J, Asaei A. TDOA matrices: Algebraic properties and their application to robust denoising with missing data. IEEE Transactions on Signal

works. IEEE Signal Processing Magazine. 2005:22(4);70-84

126 Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

Processing. 2016:64(20);5242-5244

Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of highspeed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its implementation in a practical 16-bit memory subsystem.

**Keywords:** SRAM, DRAM, memory subsystem, P-3TD, static noise margin
