**2. Static random access memory (SRAM)**

In high-performance integrated circuits, static random access memories (SRAMs) have been used as on-chip memories, due to its intense access speed and compatibility with process and supply voltage. Due to aggressive complementary metal oxide semiconductor (CMOS) technology scaling, the demand for a high-performance technology has increased the amount of on-chip memory integrated into modern semiconductor devices. Recently, there has been a rapid increase in the total area occupied by these memories. The continued scaling of CMOS technology has also resulted in problems which were less severe in earlier generations. These include process-induced variations, soft errors, transistor degradation mechanism, and so on. SRAM dominates the memory hierarchy in performance, but due to area limitations and high cost per bit, they are often integrated in lesser capacity. Furthermore, as the technology scales deepen into nanometer levels, there is a reduction of the stability of SRAM to noise and radiation is reduced. It is becoming increasingly challenging to maintain an acceptable static noise margin (SNM) of SRAMs while scaling the minimum feature sizes and supply voltages. Static noise margin (SNM) degradation, which characterizes the data integrity of SRAM during a read operation, has driven the development of SRAM cell design into a new direction as the supply voltage reaches near the threshold voltage. However, the shrinking of the transistor dimensions has also increased the probability of radiation-induced errors. This chapter has the following outline. We discuss the background information on different SRAM cells and describe the SRAM stability concept along with equations. In this section, we present our simulations and discuss the results [5].

#### **2.1. Different types of SRAM cells**

#### *2.1.1. SRAM 6T cell*

The conventional SRAM cell consists of two cross-coupled CMOS inverters with two access transistors connected to supportive bit lines. **Figure 1** shows the circuit diagram of a SRAM 6T cell. During read operation, pre-charge the bit lines (BL), BLB (bit line bar) to VDD. Turn on WL (word line). BL or BLB will pull down to low depending on storage node QD and QB. For write operation, drive bit line (BL) and bit line bar (BLB) with necessary values (0.1 or 1.0) [6]. Turn on word line, bit lines (BL or BLB overpower cell with a new value).

## *2.1.2. SRAM 11T cell*

increased the necessity for semiconductor memory. In view of the pressure on memory, new and upgraded semiconductor memory technologies were being researched, and development could have been very expeditious. The mature semiconductor memory technologies are still

The requirement for semiconductor memories with rapid advancement in technologies has been an overabundance of technologies and types of memories that have emanated viz. ROM, RAM, EPROM, EEPROM, Flash memory, static random access memory (SRAM) [1, 2], dynamic random access memory (DRAM) [3, 4], synchronous dynamic random access memory (SDRAM), and the very new magnetoresistive random access memory (MRAM) that could now be seen in the electronics literature. Each one has its own merits and areas in which it may be used. In addition to these new applications such as digital cameras, PDAs and many more applications have given rise to the exigency of memories. This chapter discusses the advancement made in the field of SRAM and DRAM memory cells while proposing a new architecture of a faster DRAM cell.

In high-performance integrated circuits, static random access memories (SRAMs) have been used as on-chip memories, due to its intense access speed and compatibility with process and supply voltage. Due to aggressive complementary metal oxide semiconductor (CMOS) technology scaling, the demand for a high-performance technology has increased the amount of on-chip memory integrated into modern semiconductor devices. Recently, there has been a rapid increase in the total area occupied by these memories. The continued scaling of CMOS technology has also resulted in problems which were less severe in earlier generations. These include process-induced variations, soft errors, transistor degradation mechanism, and so on. SRAM dominates the memory hierarchy in performance, but due to area limitations and high cost per bit, they are often integrated in lesser capacity. Furthermore, as the technology scales deepen into nanometer levels, there is a reduction of the stability of SRAM to noise and radiation is reduced. It is becoming increasingly challenging to maintain an acceptable static noise margin (SNM) of SRAMs while scaling the minimum feature sizes and supply voltages. Static noise margin (SNM) degradation, which characterizes the data integrity of SRAM during a read operation, has driven the development of SRAM cell design into a new direction as the supply voltage reaches near the threshold voltage. However, the shrinking of the transistor dimensions has also increased the probability of radiation-induced errors. This chapter has the following outline. We discuss the background information on different SRAM cells and describe the SRAM stability concept along with equations. In this section, we present our

The conventional SRAM cell consists of two cross-coupled CMOS inverters with two access transistors connected to supportive bit lines. **Figure 1** shows the circuit diagram of a SRAM 6T cell. During read operation, pre-charge the bit lines (BL), BLB (bit line bar) to VDD. Turn on

extensively used and would form the paradigms of manufacturing for years to come.

128 Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

**2. Static random access memory (SRAM)**

simulations and discuss the results [5].

**2.1. Different types of SRAM cells**

*2.1.1. SRAM 6T cell*

An SRAM 11T cell is shown in **Figure 2**. The circuit enumerates a circuit which exists as two cross-coupled inverters along with an access transistor which is controlled by the read word line (RWL) for read operation and two more access transistors which are controlled by the write word line (WWL) for write operation [3]. **Figure 2** depicts the circuit diagram of an SRAM 11T cell.
