*2.1.3. SRAM 8T cell*

In SRAM 8T cell, two voltage sources S1 and S2 are used, one connected to the output of the bit line and the other with the bit bar line. Two NMOS transistors are connected with inputs of bit line and bit bar line, respectively, straight to switch ON and OFF the power source supply during write 0 write 1 operations. The SRAM 8T cell is shown in **Figure 3**. These power supply sources diminish the voltage swing at the output node when write operation is being performed [7]. **Figure 3** shows the circuit diagram of SRAM 8T cell.

#### **2.2. Static noise margin**

The stability of an SRAM cell is critically functional in nanometer technologies as it determines the ability to retain stored information. The static noise margin (SNM) is a measure

**Figure 1.** SRAM 6T cell.

**Figure 2.** SRAM 11T cell.

**Figure 3.** SRAM 8T cell.

of the SRAM stability; it is defined as the maximum static noise voltage that could be tolerated by the SRAM stability and without the loss of stored information. In other words, SNM quantifies the amount of noise voltage Vn required to flip the cell data during a read access or a standby mode. **Figure 4** shows an SRAM cell presented as two equivalent inverters with the noise voltage inserted between the corresponding inputs and outputs. Both series voltage noise sources have the same value and act in a synchronized way to upset the state of the cell.

transistor attributes could result in cell imbalance. If the inverters of cell are not identical, one lobe is smaller than the other. Then, the SNM of the cell is the length of the side of the largest

**Cell ratio (CR) SNM 6T SRAM (mV) SNM 11T SRAM (mV) SNM 8T SRAM (mV)**

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1 136.84 328.7 336.4 1.4 141.4 343.2 391.2 1.8 150.53 348.5 411.5 2.0 159.65 354.6 429.6

**Table 1** presents the SNM variation of different SRAM cells with the cell ratio (CR) during the read operation. It can be seen that as the CR of the SRAM cell increases, the SNM also increases. Cell ratio: the ratio of driver transistor to access transistor is an important cell

square that fits inside the smaller of the two lobes [8].

**2.3. Measurement results**

**Table 1.** SRAM variation with CR.

**Figure 5.** Static noise margin.

**Figure 4.** SRAM cell with a noise source.

parameter called the cell ratio.

The SNM of an SRAM cell can be represented graphically using the superimposed voltage transfer characteristics (VTC) of the inverters as shown in **Figure 5**. The resulting two-lobed curves are generally referred to as the "butterfly curve." The SNM is now defined as the length of the side of the largest embedded square inside the butterfly plot. In an ideal SRAM cell, the VTC of both inverts would be symmetrical. However, due to process variations, change in

**Figure 4.** SRAM cell with a noise source.

**Figure 5.** Static noise margin.


**Table 1.** SRAM variation with CR.

of the SRAM stability; it is defined as the maximum static noise voltage that could be tolerated by the SRAM stability and without the loss of stored information. In other words, SNM quantifies the amount of noise voltage Vn required to flip the cell data during a read access or a standby mode. **Figure 4** shows an SRAM cell presented as two equivalent inverters with the noise voltage inserted between the corresponding inputs and outputs. Both series voltage noise sources have the same value and act in a synchronized way to upset the state of the cell. The SNM of an SRAM cell can be represented graphically using the superimposed voltage transfer characteristics (VTC) of the inverters as shown in **Figure 5**. The resulting two-lobed curves are generally referred to as the "butterfly curve." The SNM is now defined as the length of the side of the largest embedded square inside the butterfly plot. In an ideal SRAM cell, the VTC of both inverts would be symmetrical. However, due to process variations, change in

130 Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

**Figure 2.** SRAM 11T cell.

**Figure 3.** SRAM 8T cell.

transistor attributes could result in cell imbalance. If the inverters of cell are not identical, one lobe is smaller than the other. Then, the SNM of the cell is the length of the side of the largest square that fits inside the smaller of the two lobes [8].

#### **2.3. Measurement results**

**Table 1** presents the SNM variation of different SRAM cells with the cell ratio (CR) during the read operation. It can be seen that as the CR of the SRAM cell increases, the SNM also increases. Cell ratio: the ratio of driver transistor to access transistor is an important cell parameter called the cell ratio.

the time required to store and/or retrieve data from the memory array. Access time helps in the determination of the speed of the memory array cell structure. Power consumption both static and dynamic is also a significant factor of the design. In this section, we would instigate various types of DRAM cells with speed and power consumption comparison being carried out between the designs. A new DRAM cell design has been described which considerably improves the speed of DRAM. The improvement in data rate consists of improvement in read access time, write access time, and retention time. These improvements will help in gaining a DRAM cell design that will be capable of giving a high performance in terms of delay and power consumptions [11, 12].

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Different DRAM cell designs based on their power and retention time are analyzed. Different

These DRAM structures differ in the form of a number of transistors, area occupied. All these different designs have different structures and properties. The first three DRAM architectures use parasitic capacitance to store data values while the last one utilizes gated diodes to store the values. These gated diodes are generally formed from N-type metal oxide semiconductor field-effect transistor (MOSFET), but in order to reduce the power dissipation, P-type MOSFET can be utilized in their place. The advantage of this modification has been shown in comparing the various DRAM structures based on power consumption (during full cycle operation of write "0," read "0," write "1" and read "1"), write access time, read access time,

A new cell structure with a P-type MOSFET as a gated diode working as a capacitor has been compared on the basis of data rate and power consumption with the already existing DRAM cell structures. This gated diode cell structure is much faster than the already existing cell structures. All the cell structures are compared in an identical environment with their simulation profile as described in **Table 2**. Write and read operations are carried out on these cell structures, and their performances have been compared in **Table 3**. **Figure 8** shows the opera-

Power consumption and access times decrease the P-3T1D DRAM cell, hence making it a faster and a low power cell as compared to the other variations. While the retention time also tends to decrease slightly, this means the memory has to be refreshed after a slightly smaller duration [11].

**3.1. Different DRAM cells**

**1.** 1T1C DRAM CELL

**2.** 3T DRAM CELL

**3.** 4T DRAM CELL

**4.** 3T1D DRAM CELL

DRAM cell designs are as follows:

and retention time (refresh time) (**Figure 7**).

**3.2. Performance comparison**

tion read-write waveform [14, 15].

*3.2.1. Analysis of DRAM designs*

**Figure 6.** Cell ratio versus static noise margin.

In **Figure 6**, the SNM variation of different SRAM cells with cell ratio is shown. It can be concluded from the graph that the noise tolerance of 8T SRAM cell is more than the other two cells [9].
