4. Two-type data cache model

Table 4. Simulation parameters of sequential circuit for exclusive caches.

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Table 5. Power consumed in sequential circuit of exclusive cache.

Figure 9. AMAT comparison of sequential circuit model for exclusive caches.

The caches discussed so far in this chapter are inclusive and exclusive. A two-level data cache model [9] which selectively makes the cache ways in various levels as inclusive or exclusive is presented in the following section. This model makes the cache ways inclusive based on access. A two-level data cache is chosen for discussion. Initially, both cache levels are exclusive. The first occurrence of address places the data in one of cache levels making the occupied way exclusive. Preference is given to place the data in level one in this case. On consecutive access to data in level one cache, cache way is made inclusive with level two cache. During this process, data in level two cache may be replaced. The least recently used algorithm (LRU) is used for data replacement in level two cache. If the data have temporal access in level two cache, the way is made exclusive. On a cold miss with both the levels occupied, the block is placed in level one cache making it exclusive. As the number of ways to place the data increases, the performance increases in terms of the average memory access time (AMAT). Figure 10 shows this architecture.

The algorithm for two-type data cache model is given in the following section.

Algorithm for two-type data cache: Given two-level data cache, this algorithm places the line in the cache system. Input is the address. An index array is maintained per cache for each way. It is zero to indicate inclusive and one to indicate exclusive.


Figure 10. Two-type data cache model [5].


Let R, H1, H2, x1, x2, y be the number of references, number of hits in level one, number of hits in level two, number of hits in level one after first hit, number of new level one hits, misses that are filled in vacant level two ways, respectively. Let t1, t2, t12, t2m, t1<sup>m</sup> be level one access time, level two access time, transfer time between level one and level two, transfer time between level two and main memory, transfer time between level one and main memory, respectively. Let the proposed system be denoted as Ctwotype. Let k be the time taken to update index array. The AMAT is given by Eq. (9).

$$AMAT\left(\mathbf{C}\_{\text{tuty}}\right) = \frac{1}{R} \begin{pmatrix} \mathbf{x}\_1(t\_1 + 2k) + \mathbf{x}\_2(t\_1 + t\_{12} + 2k) + \\\\ H\_2(t\_1 + t\_2 + 2k) + \\\\ y(t\_1 + t\_2 + t\_{2m} + 2k) + \\\\ (R - \mathbf{x}\_1 - \mathbf{x}\_2 - H\_2 - y) \\\\ (t\_1 + t\_2 + t\_{1m} + 2k) \end{pmatrix} \tag{9}$$

where H<sup>1</sup> ¼ x<sup>1</sup> þ x2.


Table 6. Two-type data cache algorithm.

In Eq. (9) the first term gives inclusive cache type hits, the second term indicates first time level one hits. The third term indicates the level two hits. The fourth term indicates placing a block in vacant level two way/set. The fifth term indicates either placing a block in free level one cache set/way or replacing a level one cache set/way on cache full scenario. It is assumed that exchange of a block from level one to memory can be done in parallel. The term 2 k is to update the index arrays of both the cache levels. The first term gives the hit time in level one cache. The second term gives the hit time in level two cache. This involves accessing level one and level two caches. The third term gives the time to service the misses. This involves accessing level one and level two caches, determining if it is missed in both levels, accessing main memory and fetching the block into level one. The level one block is written to the memory before the new block is fetched. Simultaneously, the requested block is sent to the processor.

Denote the inclusive cache as Ci and exclusive cache as Ce. Let Hi1, Hi2, He1, He<sup>2</sup> be the number of level one hits and level two hits in inclusive cache, number of level one hits and number of level two hits in exclusive cache, respectively.

The AMAT for inclusive cache is given by Eq. (10).

1. A level one hit occurs if the address is found in level one. The block is made inclusive by placing a copy of it in level two cache. The index array entry is set to 00 to indicate this in

2. A level one miss and level two hit occurs if the address is not found in level one but is found in level two cache. The block is made exclusive in this case. This is indicated by setting index array entry of block to 11. The block is accessed and the process stops. 3. A cache miss occurs if the block is not present in level one and level two cache. If level one cache is vacant, it is placed in level one cache. Else, if level two cache way is vacant, it is placed in level two cache. The block is made exclusive. The block is accessed and process stops. If the level one set is full, the block replaces an existing block based on least recently used algorithm. The corresponding index array entry is made exclusive by setting it to 11.

Let R, H1, H2, x1, x2, y be the number of references, number of hits in level one, number of hits in level two, number of hits in level one after first hit, number of new level one hits, misses that are filled in vacant level two ways, respectively. Let t1, t2, t12, t2m, t1<sup>m</sup> be level one access time, level two access time, transfer time between level one and level two, transfer time between level two and main memory, transfer time between level one and main memory, respectively. Let the proposed system be denoted as Ctwotype. Let k be the time taken to update index array. The AMAT is given by Eq. (9).

x1ð Þþ t<sup>1</sup> þ 2k x2ðt<sup>1</sup> þ t<sup>12</sup> þ 2kÞþ

1

CCCCCCCCA

(9)

H2ð Þþ t<sup>1</sup> þ t<sup>2</sup> þ 2k y tð <sup>1</sup> þ t<sup>2</sup> þ t2<sup>m</sup> þ 2kÞþ ð Þ R � x<sup>1</sup> � x<sup>2</sup> � H<sup>2</sup> � y ð Þ t<sup>1</sup> þ t<sup>2</sup> þ t1<sup>m</sup> þ 2k

both the levels. The block is accessed and the process stops.

The mapping process stops. Table 6 gives the algorithm.

AMAT Ctwotype

where H<sup>1</sup> ¼ x<sup>1</sup> þ x2.

280 Management of Information Systems

Table 6. Two-type data cache algorithm.

� � <sup>¼</sup> <sup>1</sup>

R

0

BBBBBBBB@

$$AMAT(\mathbf{C}\_i) = \frac{1}{R} \begin{pmatrix} H\_{i1}t\_1 + H\_{i2}(2t\_1 + t\_2 + t\_{12}) + \\ (R - H\_{i1} - H\_{i2}) \\ (2t\_1 + 2t\_2 + t\_{1m} + t\_{12}) \end{pmatrix} \tag{10}$$

The first term is the level one hit time. The level two hit time is given by second term. This involves accessing level one, level two and transferring data from level one to memory and data from level two to level one cache. The miss time is given by third term. This involves accessing level one, level two to determine it is a miss in both levels, write from level one to memory and level two to memory the existing blocks. The new block from main memory is fetched into level two cache and from there to level one cache. Simultaneously, it is given for processing. An improvement in performance is observed as given by Eq. (11).

$$\frac{1}{R} \begin{pmatrix} \mathbf{x}\_1(t\_1 + 2k) + \mathbf{x}\_2(t\_1 + t\_{12} + 2k) + H\_2(t\_1 + t\_2 + 2k) \\\\ + y(t\_1 + t\_2 + t\_{2m} + 2k) + \\\ (R - \mathbf{x}\_1 - \mathbf{x}\_2 - H\_2 - y) \\\\ (t\_1 + t\_2 + t\_{1m} + 2k) \end{pmatrix} \prec \frac{1}{R} \begin{pmatrix} H\_{\mathrm{il}}t\_1 + H\_{\mathrm{il}}(2t\_1 + t\_2 + t\_{12}) + \\\\ (R - H\_{\mathrm{il}} - H\_{\mathrm{il}}) \\\\ (2t\_1 + 2t\_2 + t\_{1m} + t\_{12}) \end{pmatrix} \tag{11}$$

The AMAT for the exclusive system is given by Eq. (12).

$$AMAT(\mathbf{C}\_{\epsilon}) = \frac{1}{R} \begin{pmatrix} H\_{\epsilon1}t\_1 + H\_{\epsilon2}(t\_1 + t\_2 + t\_{12}) + \\ (R - H\_{\epsilon1} - H\_{\epsilon2}) \\ (t\_1 + t\_2 + t\_{1m} + t\_{12} + t\_{2m}) \end{pmatrix} \tag{12}$$

The first term in Eq. (12) is the level one hit time. The second term is for level two cache hits. This needs access of level one cache, level two cache and exchange the contents. On a miss in both the levels, the contents of level two are updated in the main memory, level one cache block is sent to level two and new block is fetched from main memory to level one cache. Simultaneously, the requested block is sent to the processor. The terms in Eq. (9) and Eq. (12) differ due to the architectural differences. A performance improvement in the proposed model over exclusive cache is seen as given by Eq. (13).

$$\frac{1}{R} \begin{pmatrix} \mathbf{x}\_1(t\_1 + 2k) + \mathbf{x}\_2(t\_1 + t\_{12} + 2k) +\\ H\_2(t\_1 + t\_2 + 2k) +\\ \mathbf{y}(t\_1 + t\_2 + t\_{2m} + 2k) +\\ (\mathbf{R} - \mathbf{x}\_1 - \mathbf{x}\_2 - H\_2 - y) \\\\ (t\_1 + t\_2 + t\_{1m} + 2k) \end{pmatrix} \prec \frac{1}{R} \begin{pmatrix} H\_{\ell 1}t\_1 + H\_{\ell 2}(t\_1 + t\_2 + t\_{12}) +\\ (\mathbf{R} - H\_{\ell 1} - H\_{\ell 2}) \\\\ (t\_1 + t\_2 + t\_{1m} + t\_{12} + t\_{2m}) \end{pmatrix} \tag{13}$$

In all the models, it is assumed that the cache block when fetched into the cache is simultaneously sent to the processor.

The proposed two-type data cache model is simulated using SPEC2000 benchmarks. The proposed model is compared with inclusive, exclusive caches described in this chapter. The simulation parameters are given as follows (Tables 7 and 8):

The AMAT values are given in the graph in Figure 11. It is compared with inclusive and exclusive caches.


Table 7. Simulation parameters of proposed two-type data cache and inclusive cache.


Table 8. Simulation parameters for exclusive cache in two-type data cache.

Figure 11. AMAT comparison with inclusive cache.

both the levels, the contents of level two are updated in the main memory, level one cache block is sent to level two and new block is fetched from main memory to level one cache. Simultaneously, the requested block is sent to the processor. The terms in Eq. (9) and Eq. (12) differ due to the architectural differences. A performance improvement in the proposed model

1

0

BB@

CCCCCCCCA ( 1 R

In all the models, it is assumed that the cache block when fetched into the cache is simulta-

The proposed two-type data cache model is simulated using SPEC2000 benchmarks. The proposed model is compared with inclusive, exclusive caches described in this chapter. The

The AMAT values are given in the graph in Figure 11. It is compared with inclusive and

He1t<sup>1</sup> þ He2ð Þþ t<sup>1</sup> þ t<sup>2</sup> þ t<sup>12</sup>

1

CCA

(13)

ð Þ t<sup>1</sup> þ t<sup>2</sup> þ t1<sup>m</sup> þ t<sup>12</sup> þ t2<sup>m</sup>

ð Þ R � He<sup>1</sup> � He<sup>2</sup>

over exclusive cache is seen as given by Eq. (13).

H2ð Þþ t<sup>1</sup> þ t<sup>2</sup> þ 2k y tð <sup>1</sup> þ t<sup>2</sup> þ t2<sup>m</sup> þ 2kÞþ ð Þ R � x<sup>1</sup> � x<sup>2</sup> � H<sup>2</sup> � y ð Þ t<sup>1</sup> þ t<sup>2</sup> þ t1<sup>m</sup> þ 2k

x1ð Þþ t<sup>1</sup> þ 2k x2ðt<sup>1</sup> þ t<sup>12</sup> þ 2kÞþ

simulation parameters are given as follows (Tables 7 and 8):

Table 7. Simulation parameters of proposed two-type data cache and inclusive cache.

Table 8. Simulation parameters for exclusive cache in two-type data cache.

1 R 0

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BBBBBBBB@

neously sent to the processor.

exclusive caches.


Table 9. AMAT values for two-type data cache simulations.

As observed from Figure 11, improvement in AMAT in proposed system compared with inclusive cache is seen. There is a decrease in AMAT by 3% compared with exclusive caches. The proposed model has better performance for systems where elements of set are accessed more than two times after a sequence of other cold misses mapped to the same set such that the number of total misses is a multiple of number of elements of level one cache.

The AMAT values are shown in Table 9.
