3. Exclusive caches

Exclusive caches have a line in one cache level only. There is no containment property of the inclusive caches. Let the cache levels be L1, L2, ::, Ln.The exclusive cache has the property that Li ∩ Lj ¼ ϕ, for i not equal to j. The exclusive cache is depicted in Figure 3.

Consider cache with two cache levels. The placement, replacement algorithm as proposed by Jouppi and Wilton [5] is given as follows:


The number of sets in both levels has to be equal in the abovementioned design. Let h1, h<sup>2</sup> be level one hits and level two hits in trace of R references. Let t1, t2, t12, t1<sup>m</sup> be access time to level one, level two, transfer time between level one and level two caches, transfer time between level one and main memory. Let M be miss penalty. Denote this exclusive cache system as Cexcl. The average memory access time is given by Eq. (2).

Figure 3. Exclusive cache of n levels.

$$AMAT(\mathbb{C}\_{\text{ext}}) = \frac{1}{R}(h\_1t\_1 + h\_2(2t\_1 + t\_2 + 2t\_{12}) + (R - h\_1 - h\_2)(2t\_1 + t\_2 + t\_{1m} + t\_{12})M) \tag{2}$$

The first term in Eq. (2) is level one hit time. The second term is level two hit time. The factor of 2 in this expression is because of swapping of the lines. The third term is the miss penalty.

Another logic to realize exclusive caches is proposed by Subha [6]. Consider two-level cache system. The placement, replacement logic is given as follows:

1. Initialize all lines to be in level zero.

3. Exclusive caches

270 Management of Information Systems

stop.

Jouppi and Wilton [5] is given as follows:

cache to second level cache.

The average memory access time is given by Eq. (2).

Exclusive caches have a line in one cache level only. There is no containment property of the inclusive caches. Let the cache levels be L1, L2, ::, Ln.The exclusive cache has the property that

Consider cache with two cache levels. The placement, replacement algorithm as proposed by

2. Check if line is present in level two. If present, swap with level one cache line, access and

3. If line is not present in cache, put the line in level one cache evicting the victim in first level

The number of sets in both levels has to be equal in the abovementioned design. Let h1, h<sup>2</sup> be level one hits and level two hits in trace of R references. Let t1, t2, t12, t1<sup>m</sup> be access time to level one, level two, transfer time between level one and level two caches, transfer time between level one and main memory. Let M be miss penalty. Denote this exclusive cache system as Cexcl.

Li ∩ Lj ¼ ϕ, for i not equal to j. The exclusive cache is depicted in Figure 3.

Figure 2. Sequential circuit in cache way to save power consumption. For details, refer [3].

1. Check if line is present in level one. If present, access the line and stop.


The abovementioned model does not require the two cache levels to have equal sets. There is a path between main memory and level two. Let β, γ, t2<sup>m</sup> be the decrease in level one hits from model proposed in [5], increase in level two hits from model proposed in [5], transfer time between level two and main memory. Let this exclusive cache system be denoted as Cexcl2. The average memory access time of this system is given by Eq. (3).

$$AMAT(\mathbb{C}\_{\text{ext}\mathcal{Q}}) = \frac{1}{R} \left( H\_1 - \beta \right) + (H\_2 + \gamma)(t\_1 + t\_2) + 2\mathbf{x}t\_{1m} + 2\mathbf{y}t\_{2m} \tag{3}$$

where H1, H<sup>2</sup> are level one and level two hits and x þ y ¼ R � H<sup>1</sup> � H<sup>2</sup> � β � γ. An improvement in AMAT is observed given by Eq. (4).

$$\begin{aligned} \frac{1}{R}(h\_1t\_1 + h\_2(2t\_1 + t\_2 + 2t\_{12}) + (R - h\_1 - h\_2)(2t\_1 + t\_2 + t\_{1m} + t\_{12})M) &> \frac{1}{R}(H\_1 - \beta) + (H\_2 + \gamma)(t\_1 + t\_2) + 2xt\_{1m} + 2yt\_{2m} \end{aligned} \tag{4}$$

The simulations of exclusive cache proposed in [6] using SPEC2K benchmarks are presented in the following section. Table 1 gives the configurations and Table 2 gives the AMAT.

The AMAT is depicted in Figure 4.

The power consumed by exclusive depends on the number of active cache lines. One method to reduce the number of active lines is to have separate cache called tag cache [7]. The tag cache contains the tag values of all cache levels. The address mapping proceeds as follows in the tag cache.

1. Compute the following

```
Set1 = a mod S1.
Tag1 = a div S1.
Set2 = a mod S2.
Tag2 = a div S2.
```


Table 1. Simulation configurations for two-level exclusive cache.


Table 2. AMAT values of two-level exclusive caches.

Figure 4. AMAT comparisons of two-level exclusive caches.

#### 4. Stop

where H1, H<sup>2</sup> are level one and level two hits and x þ y ¼ R � H<sup>1</sup> � H<sup>2</sup> � β � γ. An improve-

<sup>R</sup>ð Þ <sup>h</sup>1t<sup>1</sup> <sup>þ</sup> <sup>h</sup>2ð2t<sup>1</sup> <sup>þ</sup> <sup>t</sup><sup>2</sup> <sup>þ</sup> <sup>2</sup>t12Þ þ ð Þ <sup>R</sup> � <sup>h</sup><sup>1</sup> � <sup>h</sup><sup>2</sup> ð Þ <sup>2</sup>t<sup>1</sup> <sup>þ</sup> <sup>t</sup><sup>2</sup> <sup>þ</sup> <sup>t</sup>1<sup>m</sup> <sup>þ</sup> <sup>t</sup><sup>12</sup> <sup>M</sup> <sup>&</sup>gt;

The simulations of exclusive cache proposed in [6] using SPEC2K benchmarks are presented in

The power consumed by exclusive depends on the number of active cache lines. One method to reduce the number of active lines is to have separate cache called tag cache [7]. The tag cache contains the tag values of all cache levels. The address mapping proceeds as follows in the tag

2. Check in tag cache for the matching of Tag1. If match is found, the line is present in level one cache as it is level one hit condition. Access the line in level one cache and stop. If there is level one cache miss, check for level two cache hit by inspecting match of Tag2. If there is

3. This step is for cache miss condition. Place the least recently used line in Set2 of level two in main memory. Transfer the least recently used line of Set1 in level one cache in the evicted level two line. Place the line with address a in level one cache. Update the entries in

level two cache hit, access the line in level two cache and stop.

Table 1. Simulation configurations for two-level exclusive cache.

the following section. Table 1 gives the configurations and Table 2 gives the AMAT.

(4)

<sup>R</sup> <sup>H</sup><sup>1</sup> � <sup>β</sup> <sup>þ</sup> ð Þ <sup>H</sup><sup>2</sup> <sup>þ</sup> <sup>γ</sup> ð Þþ <sup>t</sup><sup>1</sup> <sup>þ</sup> <sup>t</sup><sup>2</sup> <sup>2</sup>xt1<sup>m</sup> <sup>þ</sup> <sup>2</sup>yt2<sup>m</sup>

ment in AMAT is observed given by Eq. (4).

1

272 Management of Information Systems

1

1. Compute the following

Set1 = a mod S1. Tag1 = a div S1. Set2 = a mod S2. Tag2 = a div S2.

the tag cache.

cache.

The AMAT is depicted in Figure 4.

In the abovementioned algorithm, a level one cache line or higher level cache line is enabled only on cache hit or cache miss in all levels. This saves the energy consumed by the cache system. The cache is exclusive in nature and the exclusive algorithm proposed by Jouppi and Wilton [5] is used. The proposed model has scalability. The architecture is shown in Figure 5.

Let trace be R references. Let h1, h2, cmiss1, cmiss2, miss be he hits in level one cache, hits in level two cache, misses filled in vacant level one cache, misses filled in vacant level two cache, conflict misses in level one and level two caches, respectively. Let t0, t1, t2, t1m, t2m, t<sup>12</sup> be tag cache access time, level one cache access time, level two cache access time, transfer time between level one and main memory, transfer time between level two and main memory,

Figure 5. Exclusive tag cache architecture [6].

transfer time between level one and level caches, respectively. Let the tag cache system be denoted as Cexcltag. The average memory access time is given by Eq. (5).

$$AMAT\left(\mathbb{C}\_{\text{ex:lagu}}\right) = \frac{1}{R} \begin{pmatrix} Rt\_0 + h\_1t\_1 + h\_2t\_2 + \\\\ c \text{miss1}(t\_1 + 2t\_0) + \\\\ c \text{miss2}(t\_2 + 3t\_0) + \\\\ \text{miss}\left(\begin{array}{c} \mathbf{4}t\_0 + t\_1 +\\\\ t\_2 + t\_{12} + t\_{2\text{n}} + t\_{1\text{n}} \end{array}\right) \end{pmatrix} \tag{5}$$

The tag cache access time is the first term in Eq. (5). The hit time accesses to level one and level two caches are given by second and third terms, respectively. The time taken to fill vacant way in level one cache is given by the fourth term. This involves accessing tag cache in level one, fetching the line to level one cache and updating the tag cache entry. The time taken to fill vacant second level cache line is given by the fifth term. This includes accessing the tag cache to check for match in level one cache and level two cache and placing the line in level two cache, updating the tag cache entry. The time taken to replace existing line is given by the sixth term. This involves checking for tag match in level one cache, level two cache, replacing the level one cache line and updating the tag cache entries. As the tag cache contains the tags in consecutive locations, it may be the case that the tag entries in level one and level two are in two different cache blocks.

The energy consumed in exclusive tag cache is calculated in the following section. Let us assume that the cache operates in two modes: high-power mode and low-power mode. On accessing cache way, its corresponding set is placed in high-power mode from low-power mode. Let Ehigh, Elow be the energy consumed by the cache way in the proposed tag cache model in high-power mode and low-power mode, respectively. Let Whigh, Wlow be the energy consumed by one cache line in tag cache in high-power mode and low-power mode, respectively. Let Edelta,Wdelta be the difference in energy level for cache way and tag cache way between the two modes of operation, respectively. When no cache operation is performed, the energy consumed in the cache system is ð Þ w1S<sup>1</sup> þ w2S<sup>2</sup> þ T Elow for w1-way set associative cache at level one and w2-set associative cache in level two. For level one cache hit, the energy consumed is Wdelta þ w1Edelts. This is because the tag cache entry and the set in level one cache are enabled in high energy mode. For level two cache hit, the energy consumed is 2Wdelta þ w2Edelta. This is because the tag cache is searched for match in level one cache and level two cache and the level two cache set containing the line is enabled. For the unfilled level one cache situation, the energy consumed is Wdelta þ w1Edelta as the tag cache is searched to confirm that it is a free level one cache and the way in the level one cache is filled with the block. For the free level two cache way, the energy consumed is 2Wdelta þ w2Edelta. This is because the tag cache entry in level one and level two caches are searched to confirm that there is free level two cache way, and the corresponding level two cache set is enabled to fill the way. For a miss, the total energy consumed is given by 2Wdelta þ w1Edelta þ w2Edelta. This is because the tag entries for level one and level two caches are enabled, and the line replaces a filled level one cache set and level two cache set. Consider a program with R references. The total energy consumed for this address trace is given by Eq. (6).

$$\begin{aligned} &R(S\_1 + S\_2 + T)E\_{low} + h\_1(\mathcal{W}\_{delta} + \varpi\_1 E\_{delta}) + \\ &h\_2(2\mathcal{W}\_{delta} + \varpi\_2 E\_{delta}) + \\ &c \text{miss1}(\mathcal{W}\_{delta} + \varpi\_1 E\_{delta}) + \\ &c \text{miss2}(2\mathcal{W}\_{delta} + \varpi\_2 E\_{delta}) + \\ &\min(2\mathcal{W}\_{delta} + \varpi\_1 E\_{delta} + \varpi\_2 E\_{delta}) \end{aligned} \tag{6}$$

The first term in Eq. (6) is the energy consumed when the cache is not accessed. The second term is the energy consumed in level one hits. This is equal to enabling the line in tag cache and accessing the ways in the level one cache for the set. The third term gives the energy consumed for level two cache hits. The fourth term is the energy consumed for filling a vacant level one cache line. The fifth term is the energy consumed to fill a vacant level two cache line. The sixth term is the energy consumed to replace an existing line in level one cache on a conflict miss. Consider a traditional exclusive cache with the same algorithm given in Section 3. The energy consumed for R references is calculated as follows. Let Ehigh be the energy consumed per way in the cache system. All the sets in both the cache levels are enabled in high energy power mode for all references. The energy consumed is given by Eq. (7).

$$(\mathcal{S}\_1 + \mathcal{S}\_2)E\_{high} \tag{7}$$

A saving in energy consumption is observed as given by Eq. (8).

transfer time between level one and level caches, respectively. Let the tag cache system be

miss

The tag cache access time is the first term in Eq. (5). The hit time accesses to level one and level two caches are given by second and third terms, respectively. The time taken to fill vacant way in level one cache is given by the fourth term. This involves accessing tag cache in level one, fetching the line to level one cache and updating the tag cache entry. The time taken to fill vacant second level cache line is given by the fifth term. This includes accessing the tag cache to check for match in level one cache and level two cache and placing the line in level two cache, updating the tag cache entry. The time taken to replace existing line is given by the sixth term. This involves checking for tag match in level one cache, level two cache, replacing the level one cache line and updating the tag cache entries. As the tag cache contains the tags in consecutive locations, it may be the case that the tag entries in level one and level two are in two different cache blocks.

The energy consumed in exclusive tag cache is calculated in the following section. Let us assume that the cache operates in two modes: high-power mode and low-power mode. On accessing cache way, its corresponding set is placed in high-power mode from low-power mode. Let Ehigh, Elow be the energy consumed by the cache way in the proposed tag cache model in high-power mode and low-power mode, respectively. Let Whigh, Wlow be the energy consumed by one cache line in tag cache in high-power mode and low-power mode, respectively. Let Edelta,Wdelta be the difference in energy level for cache way and tag cache way between the two modes of operation, respectively. When no cache operation is performed, the

Rt<sup>0</sup> þ h1t<sup>1</sup> þ h2t2þ cmiss1ð Þþ t<sup>1</sup> þ 2t<sup>0</sup> cmiss2ð Þþ t<sup>2</sup> þ 3t<sup>0</sup>

1

CCCCCCCCA

(5)

4t<sup>0</sup> þ t1þ t<sup>2</sup> þ t<sup>12</sup> þ t2<sup>m</sup> þ t1<sup>m</sup>

!

denoted as Cexcltag. The average memory access time is given by Eq. (5).

� � <sup>¼</sup> <sup>1</sup>

R

0

BBBBBBBB@

AMAT Cexcltag

Figure 5. Exclusive tag cache architecture [6].

274 Management of Information Systems

$$\begin{aligned} &R(S\_1 + S\_2 + T)E\_{low} + h\_1(W\_{\\\text{left}} + \varpi\_2 E\_{\\\\text{right}}) + \\ &c \text{miss1}(W\_{\\\\text{2}}(2W\_{\\\\text{to}} + \varpi\_2 E\_{\\\\text{to}}) + \\ &\min(2W\_{\\\\delta} + \varpi\_2 E\_{\\\\delta}) + \\ &\xi =\\\xi \end{aligned} \tag{8}$$
 
$$\begin{aligned} &\xi = \mathcal{W}\_{\\\\delta} + \varpi\_1 E\_{\\\\delta} + \varpi\_2 E\_{\\\\delta} \\ &\xi = \mathcal{Y}\_{\\\\delta} \end{aligned} \tag{9}$$


Table 3. Simulation parameters for Exclusive Tag cache model.

The simulations for the above proposed tag cache model of exclusive cache is presented in the following section [7]. The simulation parameters are given in Table 3. The energy consumed in low-power mode is 5 J and high-power mode is 15 J. The AMAT was calculated using C routines. Figure 6 gives the AMAT and Figure 7 gives the energy consumed. As seen from Figure 6, the AMAT performance is comparable with traditional exclusive cache. The energy is saved by 23% as seen from Figure 7 when compared with traditional exclusive cache.

A hardware method [8] to improve the power consumption is to enable level one and level two cache lines based on the contents of the tag cache. This is depicted in Figure 8.

Figure 6. AMAT comparison for tag cache model of exclusive caches.

Figure 7. Energy comparison of tag cache model of exclusive caches.

The simulations for the above proposed tag cache model of exclusive cache is presented in the following section [7]. The simulation parameters are given in Table 3. The energy consumed in low-power mode is 5 J and high-power mode is 15 J. The AMAT was calculated using C routines. Figure 6 gives the AMAT and Figure 7 gives the energy consumed. As seen from Figure 6, the AMAT performance is comparable with traditional exclusive cache. The energy is

A hardware method [8] to improve the power consumption is to enable level one and level two

saved by 23% as seen from Figure 7 when compared with traditional exclusive cache.

cache lines based on the contents of the tag cache. This is depicted in Figure 8.

Table 3. Simulation parameters for Exclusive Tag cache model.

276 Management of Information Systems

Figure 6. AMAT comparison for tag cache model of exclusive caches.

The simulations for the model presented in [8] are presented in the following section. The simulation parameters are shown in Table 4. The power consumed is shown in Table 5. The AMAT is shown in Figure 9. The t is traditional model and p is the proposed model. There is 49% improvement in power consumption with no change in AMAT for this model compared

Figure 8. Proposed hardware for power saving in exclusive tag cache architecture of two levels [9].


Table 4. Simulation parameters of sequential circuit for exclusive caches.


Table 5. Power consumed in sequential circuit of exclusive cache.

Figure 9. AMAT comparison of sequential circuit model for exclusive caches.

with the exclusive model proposed in tag cache model of exclusive cache (t in this discussion) as proposed in [7].
