**2. Standard cell characterization in very large scale integration (VLSI) design**

In semiconductor design, standard cell methodology is a method that is widely used for very large scale integration (VLSI) design, especially for digital logic circuits. It is a design abstraction, where the low-level circuit layout can be encapsulated into many abstract logic representations (e.g., NOR2, NAND2 cells). As a cell-based methodology, it can enable one designer to focus on the high-level aspect (logical function) of a design, while another designer can work on the implementation aspect (physical layout). As semiconductor fabrication technology progressed to sub-10 nm regime, standard cell methodology was the enabler to allow designers to scale application-specific integrated circuits (ASICs) from simple chips of several thousand cells, to complex chips with hundreds of millions of cells.

A standard cell provides a Boolean logic function (e.g., AND, OR) or a storage function (latch or flip-flop). A standard cell can be as simple as an inverter which consists of only two transistors. It can also be as complex as adders or multiplexers which have tens of transistors. As a standard cell is a logic gate, "cell" and "gate" are often interchangeable. Standard cell library is a collection of predefined cells which are usually fully customized to a specific technology and optimized for best delay, power, area, and so on. The standard cell library provides a way for designers to place cells in rows, and it enables the automated layout generations for digital ASICs.

The objective of standard cell characterization is to create a set of high-quality models of a standard cell library that could accurately and efficiently model cell behavior. Cell behavior may come from a variety of parameters in different aspects like capacitance, power, timing, current, waveform, and so on. Among them, one of the most important models in standard cell characterization is timing delay models. In this chapter, for simplicity, we focus on the characterization of the pin-to-pin propagation delay of standard cells. Propagation delay is the time required for the input to be propagated to the output. In other words, it is defined as the time it takes for the effect change in input to be visible at the output. Propagation delay is important because it has a direct effect on the speed at which a digital device, such as a computer, can operate. This is true of memory chips as well as microprocessors. As mentioned earlier that a gate and a cell are often interchangeable in this chapter, cell delay and gate delay are interchangeable as well.

Cell propagation delays change with many factors, including the following:


linear model), nonlinear regression (e.g., generalized linear/nonlinear models), and regression trees (e.g., classification and regression trees), and so on. It is also worth noting that a neural network, which is very popular nowadays in an era of artificial intelligence and machine learn-

MARSP is a nonparametric regression procedure that makes no assumptions about the underlying functional relationships between dependent and independent variables. The form of MARSP and its coefficients are entirely derived from the regression data. The modeling strategy is called "divide and conquer," by which the input space is partitioned into a number of regions, with each region having its own regression equation. This makes MARSP particularly efficient for high-dimension problems, where other techniques most likely have

As the name suggests, MARSP uses splines as its main component. Splines are piecewise curves from polynomial functions. When different splines are smoothly connected, it can result in a flexible model which can handle both linear and nonlinear situations. The connection points between different pieces are called knots, which connect the end of one region of

The MARSP technique has been particularly popular in data mining because it does not require or assume any particular type or any class of relationship (e.g., logistic, linear, etc.) between the outcome variable of interest and the predictor variables. Instead, MARSP derives useful models (i.e., models that yield accurate predictions) even in situations where the relationship between the predictor variable and the predictor variables is difficult to approximate with parametric models. If you are interested in more information about MARSP and how it compares to other

In semiconductor design, standard cell methodology is a method that is widely used for very large scale integration (VLSI) design, especially for digital logic circuits. It is a design abstraction, where the low-level circuit layout can be encapsulated into many abstract logic representations (e.g., NOR2, NAND2 cells). As a cell-based methodology, it can enable one designer to focus on the high-level aspect (logical function) of a design, while another designer can work on the implementation aspect (physical layout). As semiconductor fabrication technology progressed to sub-10 nm regime, standard cell methodology was the enabler to allow designers to scale application-specific integrated circuits (ASICs) from simple chips of several

A standard cell provides a Boolean logic function (e.g., AND, OR) or a storage function (latch or flip-flop). A standard cell can be as simple as an inverter which consists of only two transistors. It can also be as complex as adders or multiplexers which have tens of transistors. As a standard cell is a logic gate, "cell" and "gate" are often interchangeable. Standard cell library is a collection of predefined cells which are usually fully customized to a specific technology and optimized

methods for nonlinear regression (or regression trees), please refer to Chapter 9 of [2].

**2. Standard cell characterization in very large scale integration** 

thousand cells, to complex chips with hundreds of millions of cells.

ing, is also a modeling technique.

48 Topics in Splines and Applications

data and the beginning of another.

accuracy issues.

**(VLSI) design**

**5.** The temperature (Although temperature is not a factor with significant impact, it is still an impacting factor).

Among the different factors above, the process parameters are included because of the emergingly pronounced effect called process variations, which is introduced in details in Section 2.1.1. In the later sections, we use process-voltage-temperature (PVT) parameters to denote process parameters, VDD, and temperature.

#### **2.1. Introduction (problem formation)**

As mentioned above, one of the most important tasks in standard cell characterization is to find a model which can accurately capture the relationship between the cell propagation delay and the parameters that have impact on cell delay (as shown in the paragraph above). Here, the cell propagation delay is the response variable, and the impacting parameters (input transition time, output loads, VDD, and the process parameters) are the explanatory parameters.

We have not talked about the number of explanatory parameters yet. But as mentioned in Section 1, MARSP is suitable for the high-dimension problem while capturing essential nonlinearities and interactions. In the following subsections, we introduce the high-dimension parameter space when characterizing the delay models of standard cells, especially when the process variations and aging effect are included [3–7].

#### **2.2. Parameter space**

#### *2.2.1. Process variations*

When integrated circuits are fabricated, the parameters of individual transistors vary. The observed random distribution of identically drawn devices is caused by the fabrication process like impurity concentration densities, oxide thicknesses, and diffusion depths, and so on. These physical variations cause changes in the electrical characteristics of the transistors which eventually lead to the variability in the circuit performance. This is called process variation. Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness) during the chip fabrication. The scaling down of the VLSI process technologies has increased the process variations, especially in sub-45 nm era.

Process variations can be generally categorized into two classes: inter-die and intra-die variations. Inter-die variations occur from one die (chip) to another, meaning that the same transistor in the design can get different features (channel lengths, threshold voltages, etc.) among different dies (chips). Intra-die variations are variations in transistor features within a chip, meaning that transistors at different locations on the same die can get different features. Spatial correlations are often seen for intra-die variations, meaning adjacent transistors have a higher probability of having similar features than transistors that are far apart. In this work, we consider not only inter-die and intra-die variations, but also the intra-gate variations. Intra-gate variations are part of intra-die variations, in some sense. It is the variations within a gate (cell), meaning that the transistors within the same gate can have different features. While most of the literature works ignored the intra-gate variations, our work has included it. As VLSI technology continues to scale down to sub-10 nm process, intra-die variations (including intra-gate variations) are becoming more and more dominant.

Reduced-order models are routinely used to replace the original large-order models. The Pi-model is the most popular reduced-order model to estimate the input admittance of RC interconnects. **Figure 2** gives the structure of the Pi-model, where *Y(s)* denotes the input admittance of the original network and *Y′(s)* denotes the input admittance of the Pi-model.

**Figure 1.** Input capacitances of the loading standard cells and the interconnect network formed the load of the previous driving gate. (a) A driving buffer and two loading cells (NOR2 and Inverter); (b) The driving buffer, with the input

In Pi-model, we use three parameters to represent the loading effect of the whole RC intercon-

time, construct the parameter space for standard cell characterization which is introduced

The shift in channel length (from the nominal value) is denoted as ∆*L*, and threshold voltage shift (from the nominal value) is denoted as ∆*Vth*. The supply voltage and temperature of a gate are denoted as ∆*VDD* and ∆*T*, respectively, assuming that all the transistors within the same gate share the same voltage and temperature. The Pi-model which represents the load of

, *Cpi*<sup>2</sup>

for each timing arc. Note that in this work the effect of Multiple Input Switching (MIS) was

**Figure 2.** Y′(s) in Pi-model as an approximation of original input admittance function Y(s). (a) original interconnect

are obtained by equating the first, second, and third moments of the

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51

, as well as the PVT parameters and input transition

. The input slew time (*Slope*) is also included

The values of *C*<sup>1</sup>

later in Section 3.

not considered.

(b) Pi-model.

, *R*, and *C*<sup>2</sup>

capacitances of the two loading cells incorporated into its load.

a gate includes three parameters, namely *Rpi*, *<sup>C</sup>pi*<sup>1</sup>

nect. These three parameters *C1*

Pi-model to corresponding moments of the original network.

*, R,* and *C2*

The overall objective of standard cell characterization is to characterize a cell-delay model which is general and able to include inter-die, intra-die, and intra-gate variations with any kind of distribution and any correlation profile between different parameters. In this work, only process variations of standard cells are considered, meaning the variations in interconnect geometries are not considered.

#### *2.2.2. Loading effect modeling (pi-model)*

As technology scales down, the impact of interconnect on circuit timing cannot be neglected. In this work, we model interconnect as a resistive-capacitive (RC) network where all the capacitances are grounded.

A small patch of a gate-level circuit is illustrated in **Figure 1(a)**, where a driving Buffer gate has two loading gates, a NOR2 gate and an inverter gate. **Figure 1(b)** replaces the two loading gates with corresponding input capacitances. The input capacitances of loading cells, together with the interconnect network, form the load of the previous driving cell. With loading gates modeled as corresponding input capacitances, circuit timing can be analyzed in the way that each stage contains a standard cell and its connecting load as **Figure 1(b)** shows. If the readers are interested in the input-capacitance modeling of the standard cells, they can refer to [8, 9] for more details.

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**2.2. Parameter space**

50 Topics in Splines and Applications

*2.2.1. Process variations*

When integrated circuits are fabricated, the parameters of individual transistors vary. The observed random distribution of identically drawn devices is caused by the fabrication process like impurity concentration densities, oxide thicknesses, and diffusion depths, and so on. These physical variations cause changes in the electrical characteristics of the transistors which eventually lead to the variability in the circuit performance. This is called process variation. Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness) during the chip fabrication. The scaling down of the VLSI

process technologies has increased the process variations, especially in sub-45 nm era.

(including intra-gate variations) are becoming more and more dominant.

nect geometries are not considered.

*2.2.2. Loading effect modeling (pi-model)*

capacitances are grounded.

for more details.

Process variations can be generally categorized into two classes: inter-die and intra-die variations. Inter-die variations occur from one die (chip) to another, meaning that the same transistor in the design can get different features (channel lengths, threshold voltages, etc.) among different dies (chips). Intra-die variations are variations in transistor features within a chip, meaning that transistors at different locations on the same die can get different features. Spatial correlations are often seen for intra-die variations, meaning adjacent transistors have a higher probability of having similar features than transistors that are far apart. In this work, we consider not only inter-die and intra-die variations, but also the intra-gate variations. Intra-gate variations are part of intra-die variations, in some sense. It is the variations within a gate (cell), meaning that the transistors within the same gate can have different features. While most of the literature works ignored the intra-gate variations, our work has included it. As VLSI technology continues to scale down to sub-10 nm process, intra-die variations

The overall objective of standard cell characterization is to characterize a cell-delay model which is general and able to include inter-die, intra-die, and intra-gate variations with any kind of distribution and any correlation profile between different parameters. In this work, only process variations of standard cells are considered, meaning the variations in intercon-

As technology scales down, the impact of interconnect on circuit timing cannot be neglected. In this work, we model interconnect as a resistive-capacitive (RC) network where all the

A small patch of a gate-level circuit is illustrated in **Figure 1(a)**, where a driving Buffer gate has two loading gates, a NOR2 gate and an inverter gate. **Figure 1(b)** replaces the two loading gates with corresponding input capacitances. The input capacitances of loading cells, together with the interconnect network, form the load of the previous driving cell. With loading gates modeled as corresponding input capacitances, circuit timing can be analyzed in the way that each stage contains a standard cell and its connecting load as **Figure 1(b)** shows. If the readers are interested in the input-capacitance modeling of the standard cells, they can refer to [8, 9]

**Figure 1.** Input capacitances of the loading standard cells and the interconnect network formed the load of the previous driving gate. (a) A driving buffer and two loading cells (NOR2 and Inverter); (b) The driving buffer, with the input capacitances of the two loading cells incorporated into its load.

Reduced-order models are routinely used to replace the original large-order models. The Pi-model is the most popular reduced-order model to estimate the input admittance of RC interconnects. **Figure 2** gives the structure of the Pi-model, where *Y(s)* denotes the input admittance of the original network and *Y′(s)* denotes the input admittance of the Pi-model. The values of *C*<sup>1</sup> , *R*, and *C*<sup>2</sup> are obtained by equating the first, second, and third moments of the Pi-model to corresponding moments of the original network.

In Pi-model, we use three parameters to represent the loading effect of the whole RC interconnect. These three parameters *C1 , R,* and *C2* , as well as the PVT parameters and input transition time, construct the parameter space for standard cell characterization which is introduced later in Section 3.

The shift in channel length (from the nominal value) is denoted as ∆*L*, and threshold voltage shift (from the nominal value) is denoted as ∆*Vth*. The supply voltage and temperature of a gate are denoted as ∆*VDD* and ∆*T*, respectively, assuming that all the transistors within the same gate share the same voltage and temperature. The Pi-model which represents the load of a gate includes three parameters, namely *Rpi*, *<sup>C</sup>pi*<sup>1</sup> , *Cpi*<sup>2</sup> . The input slew time (*Slope*) is also included for each timing arc. Note that in this work the effect of Multiple Input Switching (MIS) was not considered.

**Figure 2.** Y′(s) in Pi-model as an approximation of original input admittance function Y(s). (a) original interconnect (b) Pi-model.

For a cell which has *N* transistors, there are 2\**N* device parameters (i.e., ∆*L*, ∆*Vth* for each transistor within the cell), and six global parameters (∆*VDD,* <sup>∆</sup>*T, <sup>R</sup>pi*, *<sup>C</sup>pi*<sup>1</sup> , *Cpi*<sup>2</sup> , *Slope*). This results in a total of (2\**N + 6*) parameters for a cell with *N* transistors. In our experiments with a commercial standard cell library, the highest value of *N* is 32, making the highest *(2\*N + 6)* as 70, which results in a quite high-dimension parameter space for cell characterization.

At this point, we have not introduced the aging effect into the parameter space. If the characterized delay models need to be aging-aware, the aging parameters should be included in the parameter space. With aging parameters included, the dimension of the parameter space would be even higher. We discuss it in the following subsection.

## *2.2.3. High-dimensional parameter space in aging-aware standard cell characterization*

For timing analysis, transistor aging is another source of variability besides PVT variations [10, 11]. Our work has considered the following wear-out mechanisms: bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). The impact of BTI and HCI is similar as they both cause the threshold voltage of aged transistors to increase, which further decreases the driving strength and ultimately increases gate delay over time. TDDB degrades the drain current of the stressed devices which also results in increased gate delay. Overall, BTI, HCI, and TDDB ultimately cause the cell delay to increase over time. When the increased circuit delay exceeds the clock period, the degraded circuit will fail to work. Therefore, the aging effect needs to be taken into account in circuit timing simulations, especially for those high-reliability applications like aviation, space, automotive [12], medical [13–17], data center [18], and so on.

The variation of channel length and the variation of threshold voltage are denoted as ∆*L* and ∆*Vth*, respectively. For channel length, the variation (∆*L*) comes from only process variation, while for transistor threshold voltage, the variation (∆*Vth*) comes from both process variation and aging effect (BTI and HCI).

$$
\Delta Vth = \Delta Vth\_{pmeas} + \Delta Vth\_{BT1} + \Delta Vth\_{HCl} \tag{1}
$$

*2.2.4. Training data*

We have obtained our training data from simulation program with integrated circuit emphasis (SPICE) simulations. A mixture of central composite design and random samples are used for the design of experiments. **Table 1** shows the corners which are used for central composite design.

(pF) [1100]

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(pF) [0.1,10]

Why is MARSP better than other methods in our application of standard cell characterization? Traditional methods like response surface methodology (RSM) use the same model to cover the entire parameter space. In our application where intra-gate variability is considered, the dimension of the parameter space is particularly high. When the number of input parameters is high, the parameter space is very high dimension. Using one single regression model to estimate gate delay (or slew time) over the whole parameter space is not sufficiently accurate, especially for a complex cell containing over 40 transistors. References [23, 24] proposed a clustering method which categorized transistors into switching/non-switching devices and on-transition/off-transition/non-transition devices. This method requires manual intervention to 'filter out' the negligible devices for each of the switching scenarios, which is quite cumbersome. Using MARSP, it can reduce the manual work and automatically capture the

This chapter employs MARSP to characterize a fitted function between response variables (gate delay or slew time) and the explanatory parameters (process-voltage-temperature parameters, aging parameters, and RC loads). MARSP uses piecewise polynomial segments to capture essential nonlinearities and interactions, and it is particularly suitable for highdimension problems. This piecewise nature allows MARSP models to split the whole parameter space into multiple subspaces, and each subspace can have a unique regression model. By using hinge functions, MARSP then inherently integrates the regression models of all the

**2.3. Why is multivariate adaptive regression splines (MARSP) better**

**Var. Corners Var. Corners** ΔL<sup>p</sup> [−30%, 30%] ΔL<sup>n</sup> [−30%, 30%] ΔVth<sup>p</sup> [−30%, 30%] ΔVth<sup>n</sup> [−30%, 30%] ΔVdd [−10%, 10%] ΔT (°C) [−50,50]

Slope [10 ps, 3 ns] *Cpi*<sup>2</sup>

*Rpi* (Ohm) [1, 1000] *Cpi*<sup>1</sup>

**Table 1.** Variations and corners of considered parameters.

essential parameters in its intelligent process.

subspaces into a single general form.

**3. MARSP for standard cell characterization**

For the effect of TDDB, we need to include two additional parameters for each transistor within a gate, namely, *RG*2*<sup>S</sup>* (gate-to-source resistance), and *RG*2*<sup>D</sup>* (gate-to-drain resistance), because the gate-oxide breakdown paths can happen from gate-to-drain or from gate-to-source [19–22]. In summary, each transistor contributes four parameters (∆*Vth*, <sup>∆</sup>*L*, *RG*2*<sup>D</sup>*, *RG*2*<sup>S</sup>* ) as input parameters. Thus, for a cell with *N* transistors, there are 4\**N* parameters for ∆*L*, <sup>∆</sup>*Vth*, *RG*2*<sup>S</sup>* and *RG*2*<sup>D</sup>*, plus six global parameters (∆*VDD,* <sup>∆</sup>*T, <sup>R</sup>pi*, *<sup>C</sup>pi*<sup>1</sup> , *Cpi*<sup>2</sup> , *Slope*), resulting in a total of (4*\*N + 6*) parameters for each cell.

As the value of *N* is as high as 32 in our experiments with a commercial library, the value of *(4\*N + 6)* can be as high as 134. Compared to 70, which is the value of *(2\*N + 6)* for cell characterization without aging effect, the dimension of parameter space in the aging-aware cell characterization has nearly doubled.

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**Table 1.** Variations and corners of considered parameters.

#### *2.2.4. Training data*

For a cell which has *N* transistors, there are 2\**N* device parameters (i.e., ∆*L*, ∆*Vth* for each tran-

total of (2\**N + 6*) parameters for a cell with *N* transistors. In our experiments with a commercial standard cell library, the highest value of *N* is 32, making the highest *(2\*N + 6)* as 70, which

At this point, we have not introduced the aging effect into the parameter space. If the characterized delay models need to be aging-aware, the aging parameters should be included in the parameter space. With aging parameters included, the dimension of the parameter space

For timing analysis, transistor aging is another source of variability besides PVT variations [10, 11]. Our work has considered the following wear-out mechanisms: bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). The impact of BTI and HCI is similar as they both cause the threshold voltage of aged transistors to increase, which further decreases the driving strength and ultimately increases gate delay over time. TDDB degrades the drain current of the stressed devices which also results in increased gate delay. Overall, BTI, HCI, and TDDB ultimately cause the cell delay to increase over time. When the increased circuit delay exceeds the clock period, the degraded circuit will fail to work. Therefore, the aging effect needs to be taken into account in circuit timing simulations, especially for those high-reliability applications like aviation, space, automotive

The variation of channel length and the variation of threshold voltage are denoted as ∆*L* and ∆*Vth*, respectively. For channel length, the variation (∆*L*) comes from only process variation, while for transistor threshold voltage, the variation (∆*Vth*) comes from both process variation

∆*Vth* = ∆*Vthprocess* + ∆*VthBTI* + ∆*VthHCI* (1)

For the effect of TDDB, we need to include two additional parameters for each transistor within

gate-oxide breakdown paths can happen from gate-to-drain or from gate-to-source [19–22]. In

Thus, for a cell with *N* transistors, there are 4\**N* parameters for ∆*L*, <sup>∆</sup>*Vth*, *RG*2*<sup>S</sup>* and *RG*2*<sup>D</sup>*, plus six

As the value of *N* is as high as 32 in our experiments with a commercial library, the value of *(4\*N + 6)* can be as high as 134. Compared to 70, which is the value of *(2\*N + 6)* for cell characterization without aging effect, the dimension of parameter space in the aging-aware cell

summary, each transistor contributes four parameters (∆*Vth*, <sup>∆</sup>*L*, *RG*2*<sup>D</sup>*, *RG*2*<sup>S</sup>*

, *Cpi*<sup>2</sup>

(gate-to-source resistance), and *RG*2*<sup>D</sup>* (gate-to-drain resistance), because the

, *Slope*), resulting in a total of (4*\*N + 6*) parameters for

, *Cpi*<sup>2</sup>

, *Slope*). This results in a

) as input parameters.

sistor within the cell), and six global parameters (∆*VDD,* <sup>∆</sup>*T, <sup>R</sup>pi*, *<sup>C</sup>pi*<sup>1</sup>

would be even higher. We discuss it in the following subsection.

[12], medical [13–17], data center [18], and so on.

and aging effect (BTI and HCI).

52 Topics in Splines and Applications

global parameters (∆*VDD,* <sup>∆</sup>*T, <sup>R</sup>pi*, *<sup>C</sup>pi*<sup>1</sup>

characterization has nearly doubled.

a gate, namely, *RG*2*<sup>S</sup>*

each cell.

results in a quite high-dimension parameter space for cell characterization.

*2.2.3. High-dimensional parameter space in aging-aware standard cell characterization*

We have obtained our training data from simulation program with integrated circuit emphasis (SPICE) simulations. A mixture of central composite design and random samples are used for the design of experiments. **Table 1** shows the corners which are used for central composite design.

#### **2.3. Why is multivariate adaptive regression splines (MARSP) better**

Why is MARSP better than other methods in our application of standard cell characterization? Traditional methods like response surface methodology (RSM) use the same model to cover the entire parameter space. In our application where intra-gate variability is considered, the dimension of the parameter space is particularly high. When the number of input parameters is high, the parameter space is very high dimension. Using one single regression model to estimate gate delay (or slew time) over the whole parameter space is not sufficiently accurate, especially for a complex cell containing over 40 transistors. References [23, 24] proposed a clustering method which categorized transistors into switching/non-switching devices and on-transition/off-transition/non-transition devices. This method requires manual intervention to 'filter out' the negligible devices for each of the switching scenarios, which is quite cumbersome. Using MARSP, it can reduce the manual work and automatically capture the essential parameters in its intelligent process.
