**4. Harmonic elimination based on the phase shift**

Minimal configuration of the DC/AC multimodule converter includes two basic full-bridge modules with the output voltages connected in series. Their DC inputs may be connected in parallel to the same bus V0 or in series (this is used for HVDC lines to share input DC voltage according to the module maximum voltage rating).

To simplify analysis two identical modules are connected to the same DC bus, and their outputs are connected in series using two ideal output transformers TX1 and TX2 with transformer ratio 1:1 (**Figure 6**). The output voltages have identical amplitude and 50% duty cycle, and their relative position in time domain (delay or phase shift) is defined by the controller (not shown).

The relative phase shift (relative to the fundamental harmonic) equal to π/3 or 1/6 of the module operation period is shown in **Figure 7**. For the third harmonic, the relative phase shift is π, and combined output signal has the third harmonics subtracted or eliminated. All other odd harmonics like 9th, 15th, 21st, 27th, etc., which are multiples of three, are eliminated too.

Two identical periodic signals being combined with the phase shift *Φ* have eliminated harmonics *n* satisfying the following requirement:

$$
\Phi = \frac{\mathbf{x}}{\mathbf{n}} \tag{4}
$$

Two module output voltages shifted π/3 and combined output without 3rd, 9th, etc. harmonics are shown in **Figure 8**. When two signals with eliminated 3rd harmonic are added with phase shift π/5, their combined voltage has eliminated the 5th harmonic and also 15th, 25th, etc. To eliminate the fifth and seventh harmonics, this process should be repeated as shown in **Figure 9** where control signals to a set of eight modules are getting additional delay starting from sync pulse. This process may be continued to eliminate enough harmonics to comply with THD requirements or other special conditions [26–31].

Total delays (or phase shift) *αm* per module *m* of a set of modules *M* (**Figure 9**) may be calculated as scalar product of matrix *C* formed by assigned to each module *m* binary numbers (c = *m*-1) of the modules and set *Φ* of harmonic canceling delays *φ* = π/n:

$$\mathcal{a}\_m = \{\mathcal{c}\_m\} \cdot \{\Psi\} \tag{5}$$

**Figure 6.** Two module converter.

converters or be floating, for example, powered from the photovoltaic batteries, depending upon the application. Each module operates with high efficiency producing rectangular pulses with controlled timing. The control algorithm for timing calculations is a subject of this analysis. Commonly used control algorithms are based on the pulse-width modulated signals to control multiple modules. The module output voltages are added in series to form the ladder-style voltage with optimized width of each pulse to eliminate harmonics and to regulate output voltage as shown in **Figure 5** (left). The discussed method was developed to operate the identical modules, producing 50% duty cycle pulses with the fundamental frequency and equal amplitude, combining their outputs in series and controlled by the phase shift only (**Figure 5**, right).

Equal ON and OFF time operation of all power switches has the following advantages:

Minimal configuration of the DC/AC multimodule converter includes two basic full-bridge modules with the output voltages connected in series. Their DC inputs may be connected in

b) Guaranteed time to reset snubbers (if used to reduce switching losses)

**Figure 5.** Forming ladder-style voltage using PWM (left) and phase shift only (right).

18 Power System Harmonics - Analysis, Effects and Mitigation Solutions for Power Quality Improvement

d) Guaranteed time to recharge gate drivers (if needed)

**4. Harmonic elimination based on the phase shift**

c) Guaranteed time to build up the lagging current for soft switching (if needed)

a) Equal conductive losses

**Figure 7.** Third harmonic canceling.

Examples of delay/phase-shift calculation for the eight modules of MMC are provided in **Table 2**.

Number *M* of modules, needed for eliminating *K* harmonics

$$\mathbf{M} = \mathbf{2}^{\mathbf{K}} \tag{6}$$

The drawback of any kind of modulation is decreasing of the resulting fundamental harmonic

∏*n=3*

**nth harmonic phase shift in** 

**n = 7 n = 5 n = 3** 0 0 0 0 0 0 0 0 0 0 1 0 0 ϕ3 ϕ3 π/3 0 1 0 0 ϕ5 0 ϕ5 π/5 0 1 1 0 ϕ5 ϕ3 ϕ5 + ϕ3 π/5 + π/3 1 0 0 ϕ7 0 0 ϕ7 π/7 1 0 1 ϕ7 0 ϕ3 ϕ7 + ϕ3 π/7 + π/3 1 1 0 ϕ7 ϕ5 0 ϕ7 + ϕ5 π/7 + π/5 1 1 1 ϕ7 ϕ5 ϕ3 ϕ7 + ϕ5 + ϕ3 π/7 + π/5+ π/3

*<sup>k</sup> Sin*{ \_\_ <sup>2</sup>(*<sup>1</sup> <sup>−</sup> \_\_1*

*<sup>n</sup>*)} (8)

**shift (αm)**

**Total module phase** 

**Total module phase** 

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**shift**

**(α<sup>m</sup> = cm·Φ)**

first *k* higher harmonics are eliminated is calculated as

**module (ϕn = π/n)**

**Figure 9.** Topology for canceling the third, fifth and seventh harmonics.

*V1,k* <sup>=</sup> **<sup>4</sup>** *<sup>V</sup>*\_\_\_<sup>0</sup>

**Module's assigned binary code (cm = m-1)**

**Table 2.** Phase shift per module calculation.

. **Table 3** provides not only THD and maximum value of the biggest voltage harmonic left after multiple harmonic eliminations but also a change of the fundamental harmonic compared to expected value in case of all phase shifts, which were zero, and combined output voltage replicates 50% duty cycle output voltage of the single module multiplied by the number of modules. THD value vs. the number of eliminated harmonics starting from the third from Cases A to G is presented in **Figure 11**. The relative amplitude of the fundamental harmonic *V1,k* after the

*V*1

**Module number (m)**

To find THD dependence on the sequential selective harmonic elimination using phase shift, seven harmonic elimination circuitries with different numbers of modules, marked A to G, were simulated. Example of circuitry topology marked as A, B, C and D, reference A fullspectrum single module and with eliminated third (B-2 modules), third and fifth (C-4 modules) and third, fifth and seventh (D-8 modules) harmonics are provided in **Figure 10**. More complicated circuits (E-16 modules, F-32 modules and G-64 modules) were also simulated.

THD for each simulated case (A to G) was calculated based on the RMS value of the simulated output ladder-style voltage *Vout* and RMS value of the fundamental harmonic *V*<sup>1</sup> [25]:

$$\text{THD} = \frac{\sqrt{V\_{out}^2 - V\_t^2}}{V\_t} \tag{7}$$

**Figure 8.** Forming ladder voltage with two modules with canceled the third harmonic.

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**Figure 9.** Topology for canceling the third, fifth and seventh harmonics.

Examples of delay/phase-shift calculation for the eight modules of MMC are provided in

*M* = **2K** (6)

To find THD dependence on the sequential selective harmonic elimination using phase shift, seven harmonic elimination circuitries with different numbers of modules, marked A to G, were simulated. Example of circuitry topology marked as A, B, C and D, reference A fullspectrum single module and with eliminated third (B-2 modules), third and fifth (C-4 modules) and third, fifth and seventh (D-8 modules) harmonics are provided in **Figure 10**. More complicated circuits (E-16 modules, F-32 modules and G-64 modules) were also simulated.

THD for each simulated case (A to G) was calculated based on the RMS value of the simulated

*\_\_\_\_\_\_\_ Vout <sup>2</sup> − V1 2 \_\_\_\_\_\_ V1*

[25]:

(7)

output ladder-style voltage *Vout* and RMS value of the fundamental harmonic *V*<sup>1</sup>

**Figure 8.** Forming ladder voltage with two modules with canceled the third harmonic.

Number *M* of modules, needed for eliminating *K* harmonics

20 Power System Harmonics - Analysis, Effects and Mitigation Solutions for Power Quality Improvement

*THD* = *<sup>√</sup>*

**Table 2**.

**Figure 7.** Third harmonic canceling.

The drawback of any kind of modulation is decreasing of the resulting fundamental harmonic *V*1 . **Table 3** provides not only THD and maximum value of the biggest voltage harmonic left after multiple harmonic eliminations but also a change of the fundamental harmonic compared to expected value in case of all phase shifts, which were zero, and combined output voltage replicates 50% duty cycle output voltage of the single module multiplied by the number of modules.

THD value vs. the number of eliminated harmonics starting from the third from Cases A to G is presented in **Figure 11**. The relative amplitude of the fundamental harmonic *V1,k* after the first *k* higher harmonics are eliminated is calculated as

$$V\_{1,k} = \frac{4\,V\_0}{\pi} \prod\_{s=3}^{k} \text{Sim}\left\{\frac{\pi}{2} \left(1 - \frac{1}{\pi i}\right)\right\} \tag{8}$$


**Table 2.** Phase shift per module calculation.

**Figure 10.** Harmonic elimination topology and phase-shift control.

Multimodule converter with eliminated the first four harmonics (Case E, 16 modules) complies with IEEE 519 2014 [23] requirements for voltage <1 kV, with five eliminated harmonics (Case F) for 1 kV to 69 kV and with six eliminated harmonics (Case G) from 69 kV to 161 kV without using any output power line filters. Eq. (9) may be useful for approximate calculation of THD of the MMC output voltage after canceling the first *k* harmonics using this method:

$$\text{THD}\_k \approx \text{0.5} \ast e^{-0.5k} \tag{9}$$

Due to the buildup of the module output voltage phase shifts, the resulting quasi-sinusoidal voltage fundamental harmonic is shifted to *ϕref* as shown in **Figure 12** which should be taken

> *2* ∑ *m M*

MMC with fixed phase shifts produces low THD sinusoidal output voltage with the amplitude proportion to the DC bus voltage. To regulate the output voltage amplitude from zero to maxi-

*<sup>m</sup>* (10)

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into consideration and if necessary added to the carrier signal.

**Figure 12.** Buildup of the output voltage additional phase shift (case C vs. case a).

**Figure 11.** Voltage THD vs. the number of canceled harmonics starting with the third one.

*ref <sup>=</sup> \_\_1*

**5. Amplitude control**

The additional phase-shift value *ϕref* is calculated for MMC with M modules as


**Table 3.** Simulation results for voltage THD and maximum high harmonic left.

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**Figure 11.** Voltage THD vs. the number of canceled harmonics starting with the third one.

**Figure 12.** Buildup of the output voltage additional phase shift (case C vs. case a).

Due to the buildup of the module output voltage phase shifts, the resulting quasi-sinusoidal voltage fundamental harmonic is shifted to *ϕref* as shown in **Figure 12** which should be taken into consideration and if necessary added to the carrier signal.

The additional phase-shift value *ϕref* is calculated for MMC with M modules as

$$\mathbf{op}\_{mf} = \frac{1}{2} \sum\_{m}^{M} \mathbf{a}\_{m} \tag{10}$$
