**2. Electrostatic discharge (ESD)**

Electrostatic discharge (ESD) is a common form of component level failure from manufacturing, shipping, and handling. Today, the ESD models and performed for qualification and shipping of semiconductor components are as follows [4]:


Additional models that are still performed, but not used for qualification of components include [4]:


#### **2.1. Human body model (HBM)**

ESD pulse models have been established to quantify the interaction of semiconductor chips and human beings. An important model is the human body model (HBM). Today, HBM is the most widely established standard for the reliability and quality in the semiconductor industry [2–4, 6]. The HBM test is integrated into the qualification and release process of the quality and reliability teams for components in corporations, and foundries [6].

The human body model is regarded as an electrostatic discharge (ESD) event, not an electrical overstress (EOS) event [1–11]. HBM represents the interaction the electrical discharge from a human being and component. The model assumes that the human being is the initial condition.

The human body model (HBM) became of interest in early days in the mining industry in the 1950s. In the Bureau of Mines, investigation reports discussed the issue of electrostatic in the mining industry. A first publication was published by P.G. Guest, V.W. Sikora, and B.L. Lewis as the *Bureau of Mines, Report of Investigation 4833*, U.S. Department of Interior, January 1952 [7]. A second article of interest was published by D. Bulgin, referred as D. Bulgin. Static Electrofication*. British Journal of Applied Physics*, Supplemental 2, 1953 [8].

An early investigator of issues with the human body model standard was T. M. Madzy and L.A. Price II of IBM in 1979 discussed a test system titled "Module Electrostatic Discharge Simulator" [4]. In this article, it was discussed that the ESD simulator was used within IBM since 1974. In 1980, H. Calvin, H. Hyatt, H. Mellberg, and D. Pellinen proposed values for the resistance and capacitance for the human ESD event for the finger tip and field enhanced discharges in "Measurement of Fast Transients and Application to Human ESD," published in the 1980 Proceedings of the EOS/ESD Symposium [4, 10–11]. The proposed resistance for the finger tip was averaged 1920 Ω, and capacitance of 110 pF, whereas the field enhanced discharge was a resistance of 550 Ω, and 120 pF. In 1981, H. Hyatt, H. Calvin, and H. Mellberg investigated the human ESD event, published in the 1981 Proceedings of the EOS/ESD Symposium, titled "A closer look at the human ESD event" [4, 10–11].

**2. Electrostatic discharge (ESD)**

**Figure 1.** ESD, EOS, Latchup, EMI and EMC.

10 System of System Failures

• Human Body Model (HBM).

• Machine Model (MM).

• Transient Latchup.

include [4]:

• Latchup.

• Charged Device Model (CDM).

• Transmission Line Pulse (TLP).

**2.1. Human body model (HBM)**

• Very-Fast Transmission Line Pulse (VF-TLP).

shipping of semiconductor components are as follows [4]:

Electrostatic discharge (ESD) is a common form of component level failure from manufacturing, shipping, and handling. Today, the ESD models and performed for qualification and

Additional models that are still performed, but not used for qualification of components

ESD pulse models have been established to quantify the interaction of semiconductor chips and human beings. An important model is the human body model (HBM). Today, HBM is the most widely established standard for the reliability and quality in the semiconductor industry [2–4, 6]. The HBM test is integrated into the qualification and release process of the quality

and reliability teams for components in corporations, and foundries [6].

HBM failure mechanisms are associated with permanent damage on the peripheral circuitry of a semiconductor chip [3]. Additionally, HBM failures can occur power rails and ESD power clamps between the power rails. HBM failures can occur in both passive and active semiconductor devices. The failure signature is typically isolated to a single device, or a few elements. ESD circuits are designed to be "tuned" to be responsive to specific pulse widths; this is an issue for EOS events since they are not "tuned" for EOS events. For example, the RC-triggered ESD power clamp is tuned to the HBM pulse, not EOS events.

HBM ESD failures are also distinct from EOS events [1, 4]. HBM events will not typically cause failures in the package, printed circuit board (PCB), or single component devices mounted on a printed circuit board.

Human body model (HBM) failures can occur in diode and MOSFET structures. Integrated circuit diode structures fail at the contact interface, silicon surface, or junction region. Human body model failure occurs in a metal oxide semiconductor field effect transistor (MOSFET) structure. Integrated circuit MOSFET structures failure occurs from MOSFET source-to-drain, or at the MOSFET gate. From HBM failures, typically, the failure is MOSFET source-to-drain failures [2, 3].

An example of an ESD protection network is known as a dual-diode network [3]. The dualdiode ESD network is a commonly used network for complimentary metal oxide semiconductor (CMOS) technology. A first p-n diode element is formed in an n-well region where the p-anode is the p-diffusion implant of the p-channel MOSFET device and the n-cathode is the n-well region connected to the power supply VDD. This is sometimes referred to as the "up diode." A second p-n diode element is formed in an p-well or p-substrate region where the n-cathode is the n-diffusion implant of the n-channel MOSFET device, or the n+/n-well implant and the p-anode is the p-well region or p-substrate region connected to the power supply VSS. This is sometimes referred to as the "down diode." This circuit provides a "forward bias" ESD protection solution for positive and negative ESD pulse events to the two power rails VDD and VSS. An advantage of the dual-diode ESD network is that it is easily to migrate from technology generation to technology generation. In shallow trench isolation (STI) technology, this structure is scalable. A second advantage is that it has a low turn-on voltage of 0.7 V. A third advantage is that it can be designed with low capacitance, making it suitable for CMOS, advanced CMOS, and RF technologies. A fourth advantage is that it does not contain MOSFET gate dielectric failure mechanisms.

In the calibration and verification procedure, the JEDEC standard requires a 1 GHz oscilloscope, whereas the ESDA standard requires 3 GHz [13]. Both standards today are bandwidth limited signal since the CDM waveform is faster that 1 GHz. These oscilloscopes were chosen based on availability at the time. It is well know that the energy spectrum of the CDM pulse

System and Component Failure from Electrical Overstress and Electrostatic Discharge

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CDM event damage occurs in the semiconductor chip through the substrate. It can also occur through the power supply. Charge is stored on the package, and the substrate.; then the power supply rapidly discharges through the grounded pin. The CDM failure mechanism can be small "pin-hole" in a MOSFET gate structure; this can occur in receiver networks, as

The current path for charged device model (CDM) in components is significantly different from other electrostatic discharge (ESD) events. In the case of the charged device model (CDM), the package and/or chip substrate is charged through a power or ground rail. The component itself is charged slowly to a desired voltage state. As a result, the current flows from the component itself to the grounded pin during ESD testing. This is significantly from other ESD tests that ground a reference, and then apply an ESD event to a signal or power pin. As a result, the current path that a CDM event follows is from inside the component to pin that is grounded during test. To avoid CDM failures of the MOSFET gate structure, an additional charged device model (CDM) ESD network is used [3] The ESD network comprises of a first stage dual-diode network placed adjacent or in proximity of the signal pad. A second set of diodes (e.g. second stage network) are placed adjacent to the receiver circuit. A resistor is placed between the first and second stage. Three paths are possible for the CDM current from a charged ground rail (e.g. p-substrate) to the grounded receiver pin. For a positive charging of the substrate, the current flows from the substrate to any possible path that will reach the grounded signal pad node. A first path is through the n-channel MOSFET receiver circuit gate and to the second stage ESD diode. A second path is through the substrate to the second stage diode network. A

In the case of the first stage ESD protection circuit is far from the signal pad, the substrate resistance can be significant. For the third path, the total resistance from the grounded location to the grounded signal path is the sum of the substrate resistance and the ESD diode series resistance. In the case that the receiver network is adjacent to the second stage ESD network, the current will prefer to follow the second path instead of first path. When the impedance of the n-channel MOSFET receiver (e.g. Path A) is higher than resistance through the second path, the receiver gate structure can avoid rupturing of the MOSFET gate dielectric. To insure that the current flows through the second path through the second stage CDM ESD network, the circuit must be physically close to the receiver, and a low series resistance diode element.

Electrical overstress (EOS) has been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s, and continues to be an issue today [1]. EOS failures are occurring at the device manufacturer, supplier, assembly and the field. In the electronic

waveform can extend into the 5 GHz frequency.

third path is through the substrate to the first stage ESD network.

**3. Electrical overstress (EOS)**

well as metal interconnects.

*An example of a signal pin ESD network consisting of a grounded gate n-channel MOSFET device [3]. The grounded gate NMOS (also referred to as GGNMOS) ESD network is a commonly used network for complimentary metal oxide semiconductor (CMOS) technology. Typically, it is a n-channel MOS-FET whose MOSFET drain is connected to the signal pin, and whose MOSFET source and gate are connected to the ground power rail. This circuit remains "off" in normal operation. When the signal pin exceeds the MOSFET snapback voltage, this circuit discharges to the VSS power rail. When the signal pin is below the ground potential, the MOSFET drain forward biases to the p-well or p-substrate region. An advantage of the GGNMOS ESD network is that it is a natural scalable solution. As the technology scales, the MOSFET snapback voltage reduces, leading to an earlier turn-on of the MOSFET.*

#### **2.2. Charged device model (CDM)**

The charged device model is an electrostatic discharge (ESD) test method that is part of the qualification of semiconductor components [4]. The charged device model (CDM) standard is supported by ESD Association as ANSI/ESD ESD-STM5.3.1-1999 [12]. Presently, there are four CDM test standard (ESDA S5.3.1, JEDEC JESD22-C101, AEC-Q100-011 Rev. C, and JEITA ED-4701-300). Each require different test platform, testing, waveform, and calibration requirements [4]. The charged device model (CDM) event is associated with the charging of the semiconductor component substrate and package. The charging of the package occurs through direct contact charging, or field-induced charging process (e.g. the field-induced charge device model (FICDM)).

There is presently an effort to align the CDM standards between the ESD Association and the JEDEC organization, by establishing a joint ESDA/JEDEC standard. The ESDA/JEDEC joint standard (JS-002 2014) will replace existing CDM ESD standards JEDS22-C101 and ANSI/ESD S5.3.1. The new joint standard will preserve test systems in the field, and improve the waveform measurement process.

The charged device model (CDM) pulse is regarded as the fastest event of all the ESD events [4, 12–15]. Note that the CDM pulse waveform is influenced by the test platform and measurement metrology. The test platform is influenced by the field plate, field plate dielectric thickness and material type, and the probe assembly (e.g. test head, and ground plane). The metrology is influenced by the oscilloscope and verification module specifications.

First, the event is oscillatory. The CDM current pulse rise time is on the order of 250 ps, and with peak currents in the range of 10 A. The energy spectrum of the CDM pulse event extends to 5 GHz frequency. The CDM pulse waveform has a fast current pulse. The time scale of the CDM event is significantly lower than the thermal diffusion time; hence CDM events are in the "adiabatic regime" of a Wunsch-Bell power-to-failure curve [4].

In the calibration and verification procedure, the JEDEC standard requires a 1 GHz oscilloscope, whereas the ESDA standard requires 3 GHz [13]. Both standards today are bandwidth limited signal since the CDM waveform is faster that 1 GHz. These oscilloscopes were chosen based on availability at the time. It is well know that the energy spectrum of the CDM pulse waveform can extend into the 5 GHz frequency.

CDM event damage occurs in the semiconductor chip through the substrate. It can also occur through the power supply. Charge is stored on the package, and the substrate.; then the power supply rapidly discharges through the grounded pin. The CDM failure mechanism can be small "pin-hole" in a MOSFET gate structure; this can occur in receiver networks, as well as metal interconnects.

The current path for charged device model (CDM) in components is significantly different from other electrostatic discharge (ESD) events. In the case of the charged device model (CDM), the package and/or chip substrate is charged through a power or ground rail. The component itself is charged slowly to a desired voltage state. As a result, the current flows from the component itself to the grounded pin during ESD testing. This is significantly from other ESD tests that ground a reference, and then apply an ESD event to a signal or power pin. As a result, the current path that a CDM event follows is from inside the component to pin that is grounded during test.

To avoid CDM failures of the MOSFET gate structure, an additional charged device model (CDM) ESD network is used [3] The ESD network comprises of a first stage dual-diode network placed adjacent or in proximity of the signal pad. A second set of diodes (e.g. second stage network) are placed adjacent to the receiver circuit. A resistor is placed between the first and second stage. Three paths are possible for the CDM current from a charged ground rail (e.g. p-substrate) to the grounded receiver pin. For a positive charging of the substrate, the current flows from the substrate to any possible path that will reach the grounded signal pad node. A first path is through the n-channel MOSFET receiver circuit gate and to the second stage ESD diode. A second path is through the substrate to the second stage diode network. A third path is through the substrate to the first stage ESD network.

In the case of the first stage ESD protection circuit is far from the signal pad, the substrate resistance can be significant. For the third path, the total resistance from the grounded location to the grounded signal path is the sum of the substrate resistance and the ESD diode series resistance. In the case that the receiver network is adjacent to the second stage ESD network, the current will prefer to follow the second path instead of first path. When the impedance of the n-channel MOSFET receiver (e.g. Path A) is higher than resistance through the second path, the receiver gate structure can avoid rupturing of the MOSFET gate dielectric. To insure that the current flows through the second path through the second stage CDM ESD network, the circuit must be physically close to the receiver, and a low series resistance diode element.
