**System and Component Failure from Electrical Overstress and Electrostatic Discharge Overstress and Electrostatic Discharge**

**System and Component Failure from Electrical** 

DOI: 10.5772/intechopen.72677

Steven H. Voldman Steven H. Voldman Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.72677

#### **Abstract**

Electrical overstress (EOS) and electrostatic discharge (ESD) have been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s, and continued to be an issue to today. In this chapter, the issue of EOS and ESD will be discussed. The sources of both EOS and ESD failure history will be discussed. EOS and ESD physical models, failure mechanisms, testing methods and solutions will be shown. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices, and procedures, as well as EOS and ESD factory control programs. EOS sources also occur from design characteristics of devices, circuits, and systems.

**Keywords:** electrical overstress, electrostatic discharge, latchup, system failure, component failure

#### **1. Introduction**

Electrostatic discharge (ESD) and Electrical overstress (EOS) have been an issue with the coming of the electrical age, when electricity and electrical product were first introduced into the mainstream of society [1–5]. With the scaling of semiconductor components, electrostatic discharge (ESD) has been a growing issue [2]. With the introduction of electrical power systems, the telephone, and electronics, inventions such as circuit breakers, and fuses became the first type of electrical overstress protection concepts to avoid over-load of electronic systems [1, 16–25]. Electrostatic discharge (ESD) and electrical overstress (EOS) will be discussed in the following sections.

In electronic design, a plethora of electrical events can occur. **Figure 1** illustrates the type of topics including ESD, EOS, latchup as well as electromagnetic interference (EMI), and electromagnetic compatibility (EMC).

Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons

The human body model is regarded as an electrostatic discharge (ESD) event, not an electrical overstress (EOS) event [1–11]. HBM represents the interaction the electrical discharge from a human being and component. The model assumes that the human being is the initial condition. The human body model (HBM) became of interest in early days in the mining industry in the 1950s. In the Bureau of Mines, investigation reports discussed the issue of electrostatic in the mining industry. A first publication was published by P.G. Guest, V.W. Sikora, and B.L. Lewis as the *Bureau of Mines, Report of Investigation 4833*, U.S. Department of Interior, January 1952 [7]. A second article of interest was published by D. Bulgin, referred as D. Bulgin. Static

System and Component Failure from Electrical Overstress and Electrostatic Discharge

http://dx.doi.org/10.5772/intechopen.72677

11

An early investigator of issues with the human body model standard was T. M. Madzy and L.A. Price II of IBM in 1979 discussed a test system titled "Module Electrostatic Discharge Simulator" [4]. In this article, it was discussed that the ESD simulator was used within IBM since 1974. In 1980, H. Calvin, H. Hyatt, H. Mellberg, and D. Pellinen proposed values for the resistance and capacitance for the human ESD event for the finger tip and field enhanced discharges in "Measurement of Fast Transients and Application to Human ESD," published in the 1980 Proceedings of the EOS/ESD Symposium [4, 10–11]. The proposed resistance for the finger tip was averaged 1920 Ω, and capacitance of 110 pF, whereas the field enhanced discharge was a resistance of 550 Ω, and 120 pF. In 1981, H. Hyatt, H. Calvin, and H. Mellberg investigated the human ESD event, published in the 1981 Proceedings of the EOS/ESD

HBM failure mechanisms are associated with permanent damage on the peripheral circuitry of a semiconductor chip [3]. Additionally, HBM failures can occur power rails and ESD power clamps between the power rails. HBM failures can occur in both passive and active semiconductor devices. The failure signature is typically isolated to a single device, or a few elements. ESD circuits are designed to be "tuned" to be responsive to specific pulse widths; this is an issue for EOS events since they are not "tuned" for EOS events. For example, the RC-triggered

HBM ESD failures are also distinct from EOS events [1, 4]. HBM events will not typically cause failures in the package, printed circuit board (PCB), or single component devices mounted on

Human body model (HBM) failures can occur in diode and MOSFET structures. Integrated circuit diode structures fail at the contact interface, silicon surface, or junction region. Human body model failure occurs in a metal oxide semiconductor field effect transistor (MOSFET) structure. Integrated circuit MOSFET structures failure occurs from MOSFET source-to-drain, or at the MOSFET gate. From HBM failures, typically, the failure is MOSFET source-to-drain failures [2, 3]. An example of an ESD protection network is known as a dual-diode network [3]. The dualdiode ESD network is a commonly used network for complimentary metal oxide semiconductor (CMOS) technology. A first p-n diode element is formed in an n-well region where the p-anode is the p-diffusion implant of the p-channel MOSFET device and the n-cathode is the n-well region connected to the power supply VDD. This is sometimes referred to as the "up diode." A second p-n diode element is formed in an p-well or p-substrate region

Electrofication*. British Journal of Applied Physics*, Supplemental 2, 1953 [8].

Symposium, titled "A closer look at the human ESD event" [4, 10–11].

ESD power clamp is tuned to the HBM pulse, not EOS events.

a printed circuit board.

**Figure 1.** ESD, EOS, Latchup, EMI and EMC.
