6. Conclusions

It may be noted that this 1 � 1 scalar block can be seen as a particular case of the general ð Þ� 2K þ 1 ð Þ 2K þ 1 block of (42), if K ¼ 0 is assumed as the maximum harmonic order. Actually, given that df <sup>m</sup> <sup>b</sup>y t1,i ð Þ ð Þ ; <sup>t</sup><sup>2</sup> <sup>=</sup>dbyl <sup>t</sup>1,i ð Þ ; <sup>t</sup><sup>2</sup> is a constant function evidencing no fluctuations in the t<sup>2</sup> fast time scale, the last term of (42) will vanish and there will be no more necessity of

Since only fast-varying signals are converted into the frequency domain, this partitioned technique can be seen as a combination of multivariate envelope transient harmonic balance (by treating the fast-varying signals in a hybrid time-frequency framework) with a pure time marching simulation engine (by treating some of the signals in a pure time domain scheme). Thus, beyond the notorious significant vector and matrix size reductions above mentioned, there is another important advantage brought by this partitioned technique. For example, in complex heterogeneous RF systems strongly nonlinear regimes of operation are in general associated to digital or baseband blocks, whereas moderately nonlinear regimes are typical of RF blocks. With this partitioned technique signals in digital and baseband blocks are appropriately computed in the time domain, while signals in RF blocks are treated in the hybrid time-frequency framework.

Similar to what we have mentioned for the methods discussed in the previous sections, it will be of great utility if the simulator is able to automatically distinguish the fast-varying variables from the slowly varying ones. We now briefly review the approach addressed in [19] for that purpose, which splits the circuit into distinct blocks according to the time rates of change of

Let us consider the HB system of (39). As stated earlier, this system has to be solved with the iterative scheme of (41) for each artificial time line t1,i � ½ � 0; T<sup>2</sup> . The automatic partitioning strategy proposed in [19] consists in considering all the circuit's variables as fast on the first iteration of (41), that is, it consists in initially representing all the unknowns in the frequency domain as a set of 2ð Þ K þ 1 Fourier coefficients. This way, the algorithm starts by computing a

> <sup>T</sup>;Yb½ � <sup>1</sup> <sup>2</sup> ð Þ t1,i

½ � <sup>1</sup> ð Þ <sup>t</sup>1,i ; …;Yv,<sup>0</sup>

null (their absolute values stay under a very small prescribed tolerance) it will be classified as slow. Otherwise it will be classified as fast. After this classification, which will temporarily split the system into fast and slow subsystems, the simulator considers that signals in slow subsystems can be represented by a single Fourier coefficient for the remaining iterations needed

� �<sup>T</sup>

h i<sup>T</sup>

<sup>v</sup> ð Þ t1,i is then inspected. If its Fourier coefficients of order k 6¼ 0 are practically

<sup>T</sup>;…;Yb½ � <sup>1</sup>

½ � <sup>1</sup> ð Þ <sup>t</sup>1,i ;…;Yv,K

<sup>n</sup> ð Þ t1,i T

½ � <sup>1</sup> ð Þ <sup>t</sup>1,i

, (44)

: (45)

ð Þ t1,i

½ � 1 ð Þ t1,i

converting the right-hand side terms of (43) into the frequency domain.

5.3. Circuit-block partitioning strategy

38 Numerical Simulations in Engineering and Science

single iteration in (41) to evaluate <sup>Y</sup>b½ � <sup>1</sup>

Yb½ � 1

to compute the solution of (41).

Each of the <sup>Y</sup>b½ � <sup>1</sup>

Yb½ � 1

ð Þ¼ t1,i Yb<sup>1</sup>

where each Ybvð Þ t1,i , v ¼ 1, …, n, is a 2ð Þ� K þ 1 1 vector defined as

<sup>v</sup> ð Þ¼ t1,i Yv,�<sup>K</sup>

their voltages and currents.

In this chapter, we have briefly reviewed some powerful numerical simulation techniques based on partitioned stratagems. Such techniques were especially designed to cope with the simulation challenges brought by emerging electronic technologies to the EDA community, as is the case of complex heterogeneous electronic systems composed of a combination of different kinds of circuit blocks (analog, mixed-signal and digital blocks, or even radio frequency blocks) containing node voltages and brunch currents of very distinct formats and running on widely separated time scales. With these partitioned techniques signals within different blocks of the circuits are computed with distinct algorithms and/or step sizes. Considerable reductions on the computational cost have been registered in several experiments published in the scientific literature (in comparison to previously recognized techniques) without compromising the accuracy of the results.
