**1. Introduction**

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The Residue Number System (RNS) is an efficient alternative number system which has been attracted researchers for over three decades. In RNS, arithmetic operations such as addition and multiplication can be performed on residues without carry-propagation between them; resulting in parallel arithmetic and high-speed hardware implementations (Parhami, 2000; Mohan, 2002; Omondi & Premkumar, 2007). Due to this feature, many Digital Signal Processing architectures based on RNS have been introduced in the literature (Soderstrand et al., 1986; Diclaudio et al., 1995; Chaves et al., 2004). In particular, RNS is an efficient method for the implementation of high-speed finite-impulse response (FIR) filters, where dominant operations are addition and multiplication. Implementation issues of RNSbased FIR filters show that performance can be considerably increased, in comparison with traditional two's complement binary number system (Jenkins et al., 1977; Conway et al., 2004; Cardarilli et al., 2007).

As described in (Navi et al., 2011) a typical RNS system is based on a moduli set which is included some pair-wise relatively prime integers. The product of the moduli is defined as the dynamic range, and it denotes the interval of integers which can be distinctively represented in RNS. The main components of an RNS system are a forward converter, parallel arithmetic channels and a reverse converter. The forward converter encodes a weighted binary number into a residue represented number, with regard to the moduli set; where it can be easily realized using modular adders or look-up tables. Each arithmetic channel includes modular adder, subtractor and multiplier for each modulo of set. The reverse converter decodes a residue represented number into its equivalent weighted binary number. The arithmetic channels are working in a completely parallel architecture without any dependency, and this results in a considerable speed enhancement. However; the overhead of forward and reverse converters can counteract this speed gain, if they are not designed efficiently. The forward converters can be designed using efficient methods. In contrast, design of reverse converters have many complexities with many important factors such as conversion algorithm, type and number of moduli.

An efficient moduli set with moduli of the form of powers of two can greatly reduce the complexity of the reverse converter as well as arithmetic channels. Due to this, many different moduli sets have been proposed for RNS which can be categorized based on their

In order to design a reverse converter, we have to select appropriate moduli set with considering the required parallelism and dynamic range requirements. Next, the moduli should be substituted in one of mentioned conversion algorithm formulas, and the resulted conversion equations should be simplified using some modulo arithmetic properties to reduce hardware complexity. Finally, hardware implementation of the simplified equations can be done using binary hardware's such as full adders, half adders, logic gates or lock-up tables. In the following, we briefly review the formulas of reverse conversion algorithms for four-moduli RNSs. Hence, consider the moduli set (*P*1, *P*2, *P*3, *P*4) with corresponding RNS

By CRT (Parhami, 2000) the weighted number *X* can be calculated by

<sup>1</sup>

simple and efficient reverse conversion equations.

The *vi*'s coefficients are as follows

4

<sup>1</sup> *<sup>i</sup> ii i i M X xN MP*

 *M*=*P*1*P*2*P*3*P*<sup>4</sup> (3)

*M MP i i* (4)

*i iP* | |*<sup>i</sup>*

The CRT has capability of parallel implementation; however its final big modulo adder

v1=*x*<sup>1</sup> (7)

2 2 11 ( ) *<sup>P</sup> <sup>P</sup>*

3 3 11 22 (( ) ) *P P <sup>P</sup>*

4 4 11 22 33 ((( ) ) ) *PPP <sup>P</sup>*

Although MRC implies a sequential process, for two and three-moduli sets it can be lead to

The New CRT-I (Wang, 2000; Molahosseini et al., 2010) uses a more efficient conversion

results in inefficient hardware realization if it is considered in direct form. By MRC (Koc, 1989) the conversion can be done using the following equation:

¦ (2)

*N M* (5)

*X v PPP vPP v P v* 4321 321 21 1 (6)

*v x vP* (8)

*v x vP vP* (9)

<sup>2</sup> <sup>2</sup>

3 3 <sup>3</sup> 1 1

<sup>444</sup> <sup>4</sup>

<sup>234</sup> 1 1 1 2 1 22 3 2 323 4 3 ( )( ) ( ) *PPP X x P k x x kP x x kPP x x* (11)

*v x vP vP vP* (10)

111

1

number (*x*1, *x*2, *x*3, *x*4).

Where

formula

dynamic range. The most well-known 3*n*-bit dynamic range moduli set is {2*n*–1, 2*n*, 2*n*+1} (Gallaher et al., 1997; Bhardwaj et al., 1998; Wang et al., 2000; Wang et al., 2002). The main reasons for the popularity of this set are its well-form and balanced moduli. However, the modulo 2*n*+1 has lower performance than the other two moduli. Hence, some efforts have been done to substitute the modulo 2*n*+1 with other well-form RNS moduli, and the resulted moduli sets are {2*n*–1, 2*n*, 2*n-1*–1} (Hiasat & Abdel-Aty-Zohdy, 1998; Wang et al., 2000b), {2*n*–1, 2*n*, 2*n+1*–1} (Mohan, 2007; Lin et al., 2008).

The dynamic ranges provided by these three moduli sets are not adequate for recent applications which require higher performance. Two approaches have been proposed to solve this problem. First, using three-moduli sets to provide large dynamic range with some specific forms like {2*ǂ*, 2*ǃ* – 1, 2*ǃ* + 1} where *ǂ*<*ǃ* (Molahosseini et al., 2008) and {22*n*, 2*n*–1, 2*n*+1– 1} (Molahosseini et al., 2009). Second, using four and five moduli sets to increase dynamic range and parallelism in RNS arithmetic unit. The 4*n*-bit dynamic range four-moduli sets are {2*n*–1, 2*n*, 2*n*+1, 2*n*+1+1} (Bhardwaj et al., 1999; Mohan & Premkumar, 2007) and {2*n*–1, 2*n*, 2*n*+1, 2*n*+1–1} (Vinod et al., 2000; Mohan & Premkumar, 2007). Although, these four-moduli sets include relatively balanced moduli, their multiplicative inverses are very complicated, and this results in low-performance reverse converters. Furthermore, some recent applications require even more dynamic range than 4*n*-bit. This demand results in introducing new class of moduli sets which have been called *large dynamic range four-moduli sets*. The first one is the 5*n*-bit dynamic range moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} that was proposed by (Cao et al., 2003). Next, (Zhang et al., 2008) enhanced the dynamic range to 6*n*-bit, and introduced the set {2*<sup>n</sup>* – 1, 2*<sup>n</sup>* +1, 22*n*–2, 22*n*+1–3}. Moreover, (Molahosseini et al., 2010) proposed the fourmoduli sets {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} and {2*n*–1, 2*n*+1, 22*n*, 22*n*+1} in 5*n* and 6*n*-bit dynamic range, respectively.

In this chapter, after an introduction about RNS and reverse conversion algorithms, the architecture of the state-of-the-art reverse cnverters which have been designed for the efficient large dynamic range four-moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1}, {2*n*–1, 2*n*+1, 22*n*, 22*n*+1} and {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} will be investigated. Furthermore, a recent contribution about modified version of the four-moduli set {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} that is {2*n*–1, 2*n*+1, 22*n*, 22*n*+1–1} will be studied. Finally, we present performance comparison in terms of hardware requirements and conversion delays, between the investigated reverse converters.
