**8. References**

96 Applications of Digital Signal Processing

Three variants of a recent digital signal processing procedure for ultrasonic NDE, based on the scanning with a small number of transducers sized to work in near field conditions (located at two perpendicular planes to obtain different ultrasonic perspectives), are evaluated. They originate distinct techniques to fuse echo information coming from two planes: time-domain, linear time-frequency, and WVT based, 2D combination methods.

a) time domain, linear scale b) time domain, scale in dB

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c) wavelet, *L*=2, linear scale d) wavelet, *L*=2, scale in dB

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e) WVT, *L*=2, linear scale f) WVT, *L*=2, scale in dB Fig. 9. Different 2D representations after combination of real traces in experiments type-II,

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with linear scale (a, c, e) and logarithmic scale (b, d, f).

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**6. Conclusion** 

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**1. Introduction**

This chapter explores signal analysis of a circuit embedded in an LSI to probe the voltage fluctuation conditions, and is described as an example of digital signal processing1. As process scaling has continued steadily, the number of devices on a chip continues to grow according to Moore's Law and, subsequently, highly integrated LSIs such as multi-CPU-core processors and system-level integrated Systems-on-a-Chip (SoCs) have become available. This technology trend can also be applied to low-cost and low-power LSIs designed especially for mobile use. However, it is not the increase in device count alone that is making chip design difficult. Rather, it is the fact that parasitic effects of interconnects such as interconnect resistance now dominate the performance of the chip. Figure 1 shows the trends in sheet resistance and estimated power density of LSIs. These effects have greatly increased the

**In-Situ Supply-Noise Measurement in LSIs** 

**with Millivolt Accuracy and Nanosecond-Order** 

design complexity and made power-distribution design a considerable challenge.

**Ref. ITRS '05**

**Sheet resistance of power supply**

**2005 2007 2009 2011 2013**

**Year**

<sup>1</sup> © 2007 IEEE. Reprinted, with permission, from Yusuke Kanno et al, "In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution", IEEE Journal

**hp90 hp65 hp45 hp32**

**Estimated power density**

**0**

Fig. 1. Trends in sheet resistance and estimated power density.

of Solid-State Circuits, Volume: 42 , Issue: 4, April, 2007 (Kanno, et al., 2007).

**1**

**2**

**Relative value**

**compared with 2005**

**3**

**4**

Yusuke Kanno *Hitachi LTD.*

**Time Resolution** 

*Japan*

**5**

