**In-Situ Supply-Noise Measurement in LSIs with Millivolt Accuracy and Nanosecond-Order Time Resolution**

Yusuke Kanno *Hitachi LTD. Japan*

#### **1. Introduction**

98 Applications of Digital Signal Processing

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This chapter explores signal analysis of a circuit embedded in an LSI to probe the voltage fluctuation conditions, and is described as an example of digital signal processing1. As process scaling has continued steadily, the number of devices on a chip continues to grow according to Moore's Law and, subsequently, highly integrated LSIs such as multi-CPU-core processors and system-level integrated Systems-on-a-Chip (SoCs) have become available. This technology trend can also be applied to low-cost and low-power LSIs designed especially for mobile use. However, it is not the increase in device count alone that is making chip design difficult. Rather, it is the fact that parasitic effects of interconnects such as interconnect resistance now dominate the performance of the chip. Figure 1 shows the trends in sheet resistance and estimated power density of LSIs. These effects have greatly increased the design complexity and made power-distribution design a considerable challenge.

Fig. 1. Trends in sheet resistance and estimated power density.

<sup>1</sup> © 2007 IEEE. Reprinted, with permission, from Yusuke Kanno et al, "In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution", IEEE Journal of Solid-State Circuits, Volume: 42 , Issue: 4, April, 2007 (Kanno, et al., 2007).

**(a) On-chip sampling oscilloscope (b) Simple analog measurement**

**Probe**

**Digital** 

<sup>101</sup> In-Situ Supply-Noise Measurement in LSIs

**output VCO**

Fig. 3. Examples of on-chip voltage measurement scheme. (a) is an on-chip sampling oscilloscope (Takamiya et al., 2004) and (b) is a simple analog measurement (Okumoto et al.,

A small, simple analog measurement was reported in (Okumoto et al., 2004). This probe consists of a small first amplifier, and the output signal of the probe is sent to a second amplifier and then transmitted to the external part of the chip. Because the probe is very small and has the same layout height as standard cells and needs only one second amplifier, many probes can be implemented in a single LSI with minimal area overhead. This method, however, requires dedicated power supplies for measuring voltages that are different from

These measurements are therefore basically done under test-element-group (TEG) conditions, and they may find it difficult to capture supply noise at multiple points in product-level LSIs when actually running applications. To resolve this difficulty, an in-situ measurement scheme is proposed. This method requires only a CMOS digital process and can be applied to standard-cell based design. Thus, it is easy to apply to product-level LSIs. The effect was demonstrated on a 3G cellular phone processor (Hattori et al., 2006), and the measurement of power supply noise maps induced by running actual application programs

Three key points need to be considered in order to measure the power supply noise at multiple

Because the power-consumption sources are distributed over the chip and many independent power domains are integrated in an LSI, analyzing the power supply network for product-level LSIs is very complicated. To analyze these power-supply networks, many probes must be embedded in the LSI. Thus, the probes must be as small as possible. Minimal area overhead and high adaptability to process scaling and ready-made electrical design automation (EDA) tools are therefore very important factors regarding the probes.

It is impossible to transmit the measured voltage by using a single-ended signal, because

points on a chip: area overhead, transmission method, and dynamic range.

2. The second point is the method used to transmit the measured signal.

1. The first point is the area overhead of the measurement probes.

• **Small footprint**

**integration**

**such as**

• **Capability of many probes** 

**AVDD1**

**point PAD**

**AVSS1 AMP**

**AVSS n**

• **Requires equality of local ground** 

**AVDD**

**AVSS**

**AMP2**

**AVSS1 = … = AVSSn = AVSS**

• **Susceptible to noise**

**Block Diagram**

2004).

**Feature** • **Digitization in vicinity of measurement point**

**S/H**

**Voltage noise filter**

**Point PAD**

**Vref**

with Millivolt Accuracy and Nanosecond-Order Time Resolution

**Problem** •**Large footprint**

local power supplies *V*DD and *V*SS.

**1.2 Key points for an in-situ measurement**

was demonstrated.

**Probe**

Power supply integrity is thus a key for achieving higher performance of SoCs fabricated using an advanced process technology. This is because degradation of the power integrity causes a voltage drop across the power supply network, commonly referred to as the IR-drop, which, in turn, causes unpredictable timing violations or even logic failures (Saleh et al., 2000). To improve power integrity, highly accurate analysis of a power-supply network is required. However, sophisticated SoCs, such as those for mobile phones, have many IPs and many power domains to enable a partial-power-down mode in a single chip. Thus, many spots of concentrated power consumption, called "hot spots", appear at many places in the chip as shown in the Fig. 2. Analysis of the power-supply network is therefore becoming more difficult. To address these issues, it is necessary to understand the influence of supply noise in product-level LSIs, gain more knowledge of it, and improve evaluation accuracy in the design of power supply networks via this knowledge. Above all, this understanding is very important; therefore, in-situ measurement and analysis of supply-noise maps for product-level LSIs has become more important, and can provide valuable knowledge for establishing reliable design guidelines for power supplies.

Fig. 2. Hotspots in the LSIs. The hotspots are defined as heavy current consumption parts in the LSIs. The sophisticated LSI has many CPUs and hardware Intellectual Properties (HW-IPs) in it, so the many hotspots become appearing.

In-depth analysis of the power supply network based on this in-situ power supply noise measurement can be helpful in designing the power supply network, which is becoming requisite for 65-nm process technology and beyond.

#### **1.1 Related work**

Several on-chip voltage measurement schemes have recently been reported (Okumoto et al., 2004; Takamiya et al., 2004), and the features are illustrated in Fig. 3.

One such scheme involves the use of an on-chip sampling oscilloscope (Takamiya et al., 2004). This function accurately measures high-speed signal waveforms such as the clock signal in a chip. Achieving such high measurement accuracy requires a sample/hold circuit which consist of an analog-to-digital converter (ADC) in the vicinity of the measurement point. This method can effectively avoid the influence of the noise on the measurement. Therefore, a large chip footprint is required for implementing measurement circuits such as a voltage noise filter, a reference-voltage generator and a timing controller.

2 Will-be-set-by-IN-TECH

Power supply integrity is thus a key for achieving higher performance of SoCs fabricated using an advanced process technology. This is because degradation of the power integrity causes a voltage drop across the power supply network, commonly referred to as the IR-drop, which, in turn, causes unpredictable timing violations or even logic failures (Saleh et al., 2000). To improve power integrity, highly accurate analysis of a power-supply network is required. However, sophisticated SoCs, such as those for mobile phones, have many IPs and many power domains to enable a partial-power-down mode in a single chip. Thus, many spots of concentrated power consumption, called "hot spots", appear at many places in the chip as shown in the Fig. 2. Analysis of the power-supply network is therefore becoming more difficult. To address these issues, it is necessary to understand the influence of supply noise in product-level LSIs, gain more knowledge of it, and improve evaluation accuracy in the design of power supply networks via this knowledge. Above all, this understanding is very important; therefore, in-situ measurement and analysis of supply-noise maps for product-level LSIs has become more important, and can provide valuable knowledge for

**Hotspot:**

**circuits .**

**consumption.**

**Heavy current consumption part. e.g. high speed operation, or simultaneous operation of plural** 

**Power gating switch to reduce standby leakage current** 

establishing reliable design guidelines for power supplies.

**LSI**

2004; Takamiya et al., 2004), and the features are illustrated in Fig. 3.

Fig. 2. Hotspots in the LSIs. The hotspots are defined as heavy current consumption parts in the LSIs. The sophisticated LSI has many CPUs and hardware Intellectual Properties

In-depth analysis of the power supply network based on this in-situ power supply noise measurement can be helpful in designing the power supply network, which is becoming

Several on-chip voltage measurement schemes have recently been reported (Okumoto et al.,

One such scheme involves the use of an on-chip sampling oscilloscope (Takamiya et al., 2004). This function accurately measures high-speed signal waveforms such as the clock signal in a chip. Achieving such high measurement accuracy requires a sample/hold circuit which consist of an analog-to-digital converter (ADC) in the vicinity of the measurement point. This method can effectively avoid the influence of the noise on the measurement. Therefore, a large chip footprint is required for implementing measurement circuits such as a voltage noise filter,

**CPU1 CPU2 CPU3**

**HW-IP1 HW-IP2 HW-IP3**

(HW-IPs) in it, so the many hotspots become appearing.

requisite for 65-nm process technology and beyond.

a reference-voltage generator and a timing controller.

**1.1 Related work**


Fig. 3. Examples of on-chip voltage measurement scheme. (a) is an on-chip sampling oscilloscope (Takamiya et al., 2004) and (b) is a simple analog measurement (Okumoto et al., 2004).

A small, simple analog measurement was reported in (Okumoto et al., 2004). This probe consists of a small first amplifier, and the output signal of the probe is sent to a second amplifier and then transmitted to the external part of the chip. Because the probe is very small and has the same layout height as standard cells and needs only one second amplifier, many probes can be implemented in a single LSI with minimal area overhead. This method, however, requires dedicated power supplies for measuring voltages that are different from local power supplies *V*DD and *V*SS.

These measurements are therefore basically done under test-element-group (TEG) conditions, and they may find it difficult to capture supply noise at multiple points in product-level LSIs when actually running applications. To resolve this difficulty, an in-situ measurement scheme is proposed. This method requires only a CMOS digital process and can be applied to standard-cell based design. Thus, it is easy to apply to product-level LSIs. The effect was demonstrated on a 3G cellular phone processor (Hattori et al., 2006), and the measurement of power supply noise maps induced by running actual application programs was demonstrated.
