**8. Accuracy**

10-bit resolution of FADC in the high-gain channels (responsible for a trigger generation) implies the ranges of *X*¯ *<sup>k</sup>* coefficients given in the 2nd column of Table 1. Multiplications of integer values N by real scaling factors sf give floating-point results. In order to keep possible high speed of calculation and not to utilize resources spendthrift the fixed-point algorithm of processing has been chosen. N×sf were approximated on each pipeline stage again to the integer value. For almost all scaling factors: sf ≤ 1, N×sf has a representation of the same or less amount of bits. For sf ≥ 1, N×sf extends the representation on 1 or 2 bits. This approximation introduces errors. However, the width of the data in the internal pipeline stages is extended from the N at the shift register *x*15,...,*x*0, to N+1, N+2, N+3, N+4, N+5, N+7, N+8 in routines A, B, C, D, E, F, G, respectively (Fig. 8). This reduces approximation errors mostly to the LSB, apart the *X*¯ 15. This coefficient will not be used for a trigger.


Table 1. Ranges of *<sup>X</sup>*¯ *<sup>k</sup>* coefficients and relative errors for least significant bits of *<sup>X</sup>*¯ *<sup>k</sup>*. For k <sup>≤</sup> <sup>14</sup> the errors appear practically only in the LSB.

According to above estimations, the configuration with 3 "engines" does not support all *ξ<sup>k</sup>* sub-triggers due to limited amount of DSP blocks. However, for the next generation of the water Cherenkov detectors array, where probably only a single PMT will be used, 3 "engines" will be implemented to investigate and to detect 3 different shapes of FADC traces corresponding to i.e. different rise times of the rising edge.

#### **9. Preliminary tests**

Analysis of Auger ADC traces of very inclined showers shows that the maximum of the signal is mostly reach in a single time bin. The attenuation factor for a tail is in the range of *β* = (0.2 - 0.5). Fig. 12 shows shapes of signals with various attenuation factors with two first time bins on a pedestal level. For simplicity it has been set on zero. It does not reduce the generality of analysis, because the pedestal is irrelevant for DCT (k ≥ 1). The corresponding DCT coefficients are shown in upper Fig. 3 (Shape\_A). After a single clock cycle, when data is shifted in the registers chain, shifted signal with only one time bin on the pedestal level determines a new set of the DCT coefficients shown in lower Fig. 3 (Shape\_B). Pattern, which is going to be recognized, can be selected by a setting of DCT coefficient in the DCT engines.

18 Will-be-set-by-IN-TECH

of a signal requires a single clock cycle only. All routines are fast enough to work with 100 MHz sampling without an additional pipeline stages and they do not introduce an additional

10-bit resolution of FADC in the high-gain channels (responsible for a trigger generation) implies the ranges of *X*¯ *<sup>k</sup>* coefficients given in the 2nd column of Table 1. Multiplications of integer values N by real scaling factors sf give floating-point results. In order to keep possible high speed of calculation and not to utilize resources spendthrift the fixed-point algorithm of processing has been chosen. N×sf were approximated on each pipeline stage again to the integer value. For almost all scaling factors: sf ≤ 1, N×sf has a representation of the same or less amount of bits. For sf ≥ 1, N×sf extends the representation on 1 or 2 bits. This approximation introduces errors. However, the width of the data in the internal pipeline stages is extended from the N at the shift register *x*15,...,*x*0, to N+1, N+2, N+3, N+4, N+5, N+7, N+8 in routines A, B, C, D, E, F, G, respectively (Fig. 8). This reduces approximation errors

> k range of LSB 2*nd* 3*rd* and k range of LSB 2*nd* 3*rd* and *X*¯ *<sup>k</sup>* bit more *X*¯ *<sup>k</sup>* bit more 0...4092 0.0% 0.00% 0.00% 8 ± 2041 0.0% 0.00% 0.00% ± 2521 13.1% 0.00% 0.00% 9 ± 12224 23.8% 1.55% 0.00% ± 2581 8.7% 0.00% 0.00% 10 ± 4557 12.8% 0.00% 0.00% ± 2914 13.1% 0.00% 0.00% 11 ± 7519 17.7% 0.00% 0.00% ± 2348 4.8% 0.00% 0.00% 12 ± 5671 11.5% 0.00% 0.00% ± 4019 15.1% 0.00% 0.00% 13 ± 9605 24.3% 2.00% 0.00% ± 3045 8.6% 0.00% 0.00% 14 ± 12978 26.9% 2.86% 0.00% ± 10032 23.1% 1.10% 0.00% 15 ± 25597 30.9% 25.08% 6.83%

Table 1. Ranges of *<sup>X</sup>*¯ *<sup>k</sup>* coefficients and relative errors for least significant bits of *<sup>X</sup>*¯ *<sup>k</sup>*. For k <sup>≤</sup> <sup>14</sup>

According to above estimations, the configuration with 3 "engines" does not support all *ξ<sup>k</sup>* sub-triggers due to limited amount of DSP blocks. However, for the next generation of the water Cherenkov detectors array, where probably only a single PMT will be used, 3 "engines" will be implemented to investigate and to detect 3 different shapes of FADC traces

Analysis of Auger ADC traces of very inclined showers shows that the maximum of the signal is mostly reach in a single time bin. The attenuation factor for a tail is in the range of *β* = (0.2 - 0.5). Fig. 12 shows shapes of signals with various attenuation factors with two first time bins on a pedestal level. For simplicity it has been set on zero. It does not reduce the generality of analysis, because the pedestal is irrelevant for DCT (k ≥ 1). The corresponding DCT coefficients are shown in upper Fig. 3 (Shape\_A). After a single clock cycle, when data is shifted in the registers chain, shifted signal with only one time bin on the pedestal level determines a new set of the DCT coefficients shown in lower Fig. 3 (Shape\_B). Pattern, which is going to be recognized, can be selected by a setting of DCT coefficient in the DCT engines.

mostly to the LSB, apart the *X*¯ 15. This coefficient will not be used for a trigger.

the errors appear practically only in the LSB.

**9. Preliminary tests**

corresponding to i.e. different rise times of the rising edge.

latency.

**8. Accuracy**

Fig. 12. Shapes of signals with various attenuation factors and two first time bins on the pedestal level

All signals with first two time bins on the pedestal level for sure will be with only one time bin on the pedestal level in the next clock cycle. But, not vice versa. A signal with only a single time bin on the pedestal level before sharp rising edge can have significant contribution in the 2nd time bin before rising edge and it will not be recognized by a pattern recognition procedure tuned on the Shape\_A. A procedure recognizing Shape\_A is more restrictive and gives lower trigger rate than for the Shape\_B. Due to limited amount of the DSP blocks only 11 DCT coefficients can be analyzed simultaneously. For the Shape\_A the *X*¯ <sup>4</sup> and *X*¯ <sup>10</sup> are ignored and for the Shape\_B : *X*¯ <sup>6</sup> and *X*¯ 14, respectively, as weakly sensitive on changes of signal shapes. The trigger based only on the DCT pattern recognition gives too high rate, due to a contribution of very week signals with also appropriate shape, but usually treated as noise. In order to reduce and control the trigger rate, the veto threshold has been introduced. The calculation of the DCT coefficients in the pipeline chain and next the calculation of sub-triggers in multipliers and comparators block takes 12 clock cycles. The signal is synchronized with the DCT sub-triggers delayed the same time to be compared with the veto threshold, simultaneously with a generated DCT sub-triggers. If the signal is above the sum of the veto threshold and the pedestal, the sub-triggers are enabled to generated a final spectral trigger. The condition that all 11 DCT coefficients were inside the acceptance lane is too strong. The shapes are not ideal, noise introduces additional shape distortions. Similarly as in the ToT trigger only a part of "fired" sub-triggers (Occupancy ≤ 11 = max. number of sub-triggers) is enough to generate the final spectral trigger.

Fig. 13. Coefficients for signals with various attenuation factors and two first time bins (left) and only one time bin (right) on the pedestal level

Experiments 21

<sup>399</sup> An Optimization of 16-Point Discrete Cosine Transform Implemented into a FPGA as a Design for a Spectral First Level Surface Detector Trigger in Extensive Air Shower Experiments

> 0 10 20

Rates vs. time for 25-35 requirement

0 96 192 288 384 480 576 672 768 864 960

Contribution of the DCT sub-triggers to the final trigger for the Occ = 7

2 3 4 5 6 7 8 9 10 11 12 13 14

rate veto

time (s)

PMT1 : 15-25 PMT2 : 15-25 PMT3 : 15-25 PMT1 : 25-35 PMT2 : 25-35 PMT3 : 25 35

PMT3 : 25-35PMT1 : 35-45 PMT2 : 35-45 PMT3 : 35-45

B

Rates (Hz) &

to (ADC-counts)

veto

> 0 2

A

rate - 0.26 rate - 0.27

veto

time (s)

C

rate - 0.28 rate - 0.27 rate - 0.26 t 0 25

rate - 0.25veto

time (s)

and C). A comparison of a contribution of "fired" DCT coefficients generating the sub-triggers for all three PMT channels and for various trigger rates requirements

different PMT and various configuration of trigger rate requirements

surface detector, when the coincidence technique cannot be longer used.

other than the present Pierre Auger Observatory - only one PMT per station.

for arbitrarily selected acceptance lane of the spectral trigger rate.

Fig. 15. Rates obtained in the test detector during an auto-calibration process (graphs A, B

(right-down). There are no significant differences in a contribution of a fixed coefficients for

high and the attenuation factor has to be increased (the acceptance lane is narrowed down). The graph B shows the process, when the initial parameters are optimal and the acceptance lane is not modified (only the veto threshold is tuned). The graph C shows the process when the initial parameters give too low trigger rate and the acceptance lane is changed three times.

The pattern recognition technique implemented parallel with the standard threshold detection may improve an efficency of a registration of rare events, especially for a single PMT in the

The optimized algorithm of the spectral trigger based on the Discrete Cosine Transform with veto and auto-calibration procedure has been successfully implemented into the FPGA and showed the perfect stability in the real detector. Measurements in the test detector confirmed assumption for a selection of limited amount of DCT coefficients and a stability of algorithm

Although 6 surface detectors from the Pierre Auger Observatory have been used for the tests, the spectral trigger is being developed more generally for future ground EAS arrays using -

The author would like to thank the Pierre Auger Collaboration for being allowed to use a PAO infrastructure and a test-hexagon and for getting the data made available. The successful installation and preliminary tests of the new Front End Boards with the DCT trigger would

0 10 20

0 10 20

**10. Conclusion**

**11. Acknowledgement**

es (Hz) &

Rates veto (ADC-counts)

ADC-counts)

Rates vs. time for 15-25 Hz requirement

0 0 103 206 309 412 515 618 721 824 927

Rates vs. time for 35-45 Hz requirement

0 0 96 192 288 384 480 576 672 768 864 960

Rates (Hz) &

& veto

(ADC-counts)

Although the spectral trigger is being developed for the future and for a single detection channel (a single PMT), the DCT trigger in the Auger surface detector has been tested in a 2-fold coincidences of any 3 PMTs, to be close as possible for a comparison of the results with the standard Auger data.

Fig. 14. Rates for various acceptance lanes (from 0.20 - 1.00 till 0.30 - 1.50) and the veto threshold (0 - 80 ADC-counts) for the Occupancy = 6 (left) and 7 (right), respectively. Due to a possible saturation of a transmission channel, the rate of the spectral trigger should not exceed ca. 40 Hz.

Fig. 14 show the trigger rate for the Occupancy = 6 and 7, respectively. The T1 trigger rate is calibrated to ca. 100 Hz. Generally, the trigger rate for Occ = 6 is too high. In order not to saturate the microcontroller and the transmission chain the total (standard Auger + spectral) trigger rate should not exceed 150 Hz. This gives max. 40 - 50 Hz for the spectral trigger only. The Occupancy = 7 with a range of attenuation factors limited to *β* = (0.20 - 1.14) gives a trigger range on the reasonable level. The Occupancy = 8 reduces the trigger rate below 1 Hz and seems to be too restrictive. The FPGA contains internal counters counting the trigger rate and a contribution of DCT sub-triggers to the final trigger. The required trigger rate range can be set remotely from the Central Data Acquisition System (CDAS). The FPGA automatically tunes the veto threshold to get the required trigger rate. If the veto threshold is above 60 ADC-counts (ca. 1.2 VEM) the acceptance lane is modified. The attenuation factor *β* from the left side of the range is increased/decreased in the range of (0.20 - 0.40) by the fixed right boundary *β* = 1.3.

Fig. 15 show three calibration processes, when either initial parameters has been set ideally (B) or they have to be tuned to get required trigger rate (A and C). The tuning process typically does not exceed 3 minutes. In contrary to the standard Auger tuning procedure, when the thresholds for the Threshold trigger are calculated by the external microcontroller located on the Unified Board (UB), the thresholds for the acceptance DCT lane are initially calculated and next stored in the ROM inside the FPGA and they are only multiplexed. This allows a full autonomous FPGA calibration process without a support by any external microcontroller. The new Front-End Board samples analog signals with 80 MHz. Data is written via a left port in the dual-port RAM. Stored data are next read via the right port with 40 MHz. The new board is seen by the rest of electronics as the standard one. Only a additional flag informs the system on the type of the trigger. Internal FPGA counters allow counting a contribution of the DCT coefficients to the final spectral trigger. Fig. 15d shows a relative contribution of the DCT coefficients for the Shape\_A. The contribution of the *X*¯ <sup>5</sup> and *X*¯ <sup>9</sup> is a little bit lower than the rest ones. For the *X*¯ <sup>9</sup> the acceptance lane (compare Fig. 13A) is relatively narrow, so the lower contribution is not strange. *X*¯ <sup>5</sup> is probably more sensitive on signal noise and possible signal distortions. The graph A (Fig. 15) shows a process when the trigger rate is initially too

Fig. 15. Rates obtained in the test detector during an auto-calibration process (graphs A, B and C). A comparison of a contribution of "fired" DCT coefficients generating the sub-triggers for all three PMT channels and for various trigger rates requirements (right-down). There are no significant differences in a contribution of a fixed coefficients for different PMT and various configuration of trigger rate requirements

high and the attenuation factor has to be increased (the acceptance lane is narrowed down). The graph B shows the process, when the initial parameters are optimal and the acceptance lane is not modified (only the veto threshold is tuned). The graph C shows the process when the initial parameters give too low trigger rate and the acceptance lane is changed three times.
