**2. Background**

The fundamental part of RNS (Omondi & Premkumar, 2007) is the moduli set {*P*1,*P*2, …,*Pn*} where numbers are relatively-prime, i.e. gcd(*Pi*,*Pj*)=1 for *ij*. The binary weighted number *X* can be represented as *X*=(*x*1,*x*2, … ,*xn*), where

$$\mathbf{x}\_i = \mathbf{X} \bmod P\_i = \|\mathbf{X}\|\_{P\_i}, 0 \le \mathbf{x}\_i < P\_i \tag{1}$$

This representation is unique for any integer number *X* in the range [0,*M*-1], where *M*=*P*1*P*2…*Pn* is the dynamic range of the moduli set {*P*1,*P*2, …,*Pn*} (Taylor, 1984). Addition (subtraction) and multiplication on RNS numbers can be performed in parallel due to the absence of carry propagation between residues.

The famous algorithms for performing reverse conversion are Chinese remainder theorem (CRT), mixed-radix conversion (MRC) and new Chinese remainder theorems (New CRTs).

In order to design a reverse converter, we have to select appropriate moduli set with considering the required parallelism and dynamic range requirements. Next, the moduli should be substituted in one of mentioned conversion algorithm formulas, and the resulted conversion equations should be simplified using some modulo arithmetic properties to reduce hardware complexity. Finally, hardware implementation of the simplified equations can be done using binary hardware's such as full adders, half adders, logic gates or lock-up tables. In the following, we briefly review the formulas of reverse conversion algorithms for four-moduli RNSs. Hence, consider the moduli set (*P*1, *P*2, *P*3, *P*4) with corresponding RNS number (*x*1, *x*2, *x*3, *x*4).

By CRT (Parhami, 2000) the weighted number *X* can be calculated by

$$X = \left| \sum\_{i=1}^{4} \left| \mathbf{x}\_i \mathbf{N}\_i \right| \_{P\_i} \mathbf{M}\_i \right|\_{\mathcal{M}} \tag{2}$$

Where

338 Applications of Digital Signal Processing

dynamic range. The most well-known 3*n*-bit dynamic range moduli set is {2*n*–1, 2*n*, 2*n*+1} (Gallaher et al., 1997; Bhardwaj et al., 1998; Wang et al., 2000; Wang et al., 2002). The main reasons for the popularity of this set are its well-form and balanced moduli. However, the modulo 2*n*+1 has lower performance than the other two moduli. Hence, some efforts have been done to substitute the modulo 2*n*+1 with other well-form RNS moduli, and the resulted moduli sets are {2*n*–1, 2*n*, 2*n-1*–1} (Hiasat & Abdel-Aty-Zohdy, 1998; Wang et al., 2000b), {2*n*–1,

The dynamic ranges provided by these three moduli sets are not adequate for recent applications which require higher performance. Two approaches have been proposed to solve this problem. First, using three-moduli sets to provide large dynamic range with some specific forms like {2*ǂ*, 2*ǃ* – 1, 2*ǃ* + 1} where *ǂ*<*ǃ* (Molahosseini et al., 2008) and {22*n*, 2*n*–1, 2*n*+1– 1} (Molahosseini et al., 2009). Second, using four and five moduli sets to increase dynamic range and parallelism in RNS arithmetic unit. The 4*n*-bit dynamic range four-moduli sets are {2*n*–1, 2*n*, 2*n*+1, 2*n*+1+1} (Bhardwaj et al., 1999; Mohan & Premkumar, 2007) and {2*n*–1, 2*n*, 2*n*+1, 2*n*+1–1} (Vinod et al., 2000; Mohan & Premkumar, 2007). Although, these four-moduli sets include relatively balanced moduli, their multiplicative inverses are very complicated, and this results in low-performance reverse converters. Furthermore, some recent applications require even more dynamic range than 4*n*-bit. This demand results in introducing new class of moduli sets which have been called *large dynamic range four-moduli sets*. The first one is the 5*n*-bit dynamic range moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} that was proposed by (Cao et al., 2003). Next, (Zhang et al., 2008) enhanced the dynamic range to 6*n*-bit, and introduced the set {2*<sup>n</sup>* – 1, 2*<sup>n</sup>* +1, 22*n*–2, 22*n*+1–3}. Moreover, (Molahosseini et al., 2010) proposed the fourmoduli sets {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} and {2*n*–1, 2*n*+1, 22*n*, 22*n*+1} in 5*n* and 6*n*-bit dynamic

In this chapter, after an introduction about RNS and reverse conversion algorithms, the architecture of the state-of-the-art reverse cnverters which have been designed for the efficient large dynamic range four-moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1}, {2*n*–1, 2*n*+1, 22*n*, 22*n*+1} and {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} will be investigated. Furthermore, a recent contribution about modified version of the four-moduli set {2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1} that is {2*n*–1, 2*n*+1, 22*n*, 22*n*+1–1} will be studied. Finally, we present performance comparison in terms of hardware requirements and conversion delays, between the investigated reverse

The fundamental part of RNS (Omondi & Premkumar, 2007) is the moduli set {*P*1,*P*2, …,*Pn*} where numbers are relatively-prime, i.e. gcd(*Pi*,*Pj*)=1 for *ij*. The binary weighted number *X*

mod ,0 *<sup>i</sup>*

This representation is unique for any integer number *X* in the range [0,*M*-1], where *M*=*P*1*P*2…*Pn* is the dynamic range of the moduli set {*P*1,*P*2, …,*Pn*} (Taylor, 1984). Addition (subtraction) and multiplication on RNS numbers can be performed in parallel due to the

The famous algorithms for performing reverse conversion are Chinese remainder theorem (CRT), mixed-radix conversion (MRC) and new Chinese remainder theorems (New CRTs).

*xX PX xP <sup>i</sup> <sup>i</sup>*<sup>d</sup> *<sup>P</sup> i i* (1)

2*n*, 2*n+1*–1} (Mohan, 2007; Lin et al., 2008).

range, respectively.

converters.

**2. Background** 

can be represented as *X*=(*x*1,*x*2, … ,*xn*), where

absence of carry propagation between residues.

$$M \equiv P\_1 P\_2 P\_3 P\_4 \tag{3}$$

$$\mathbf{M}\_i = \mathbf{M}/\mathbf{P}\_i\tag{4}$$

$$\mathcal{N}\_i = \|\mathcal{M}\_i^{-1}\|\_{\mathcal{P}\_i} \tag{5}$$

The CRT has capability of parallel implementation; however its final big modulo adder results in inefficient hardware realization if it is considered in direct form.

By MRC (Koc, 1989) the conversion can be done using the following equation:

$$X = \upsilon\_4 P\_3 P\_2 P\_1 + \upsilon\_3 P\_2 P\_1 + \upsilon\_2 P\_1 + \upsilon\_1 \tag{6}$$

The *vi*'s coefficients are as follows

$$\mathbf{v}\_1 = \mathbf{x}\_1 \tag{7}$$

$$\upsilon\_2 = \left| (\upsilon\_2 - \upsilon\_1) \middle| P\_1^{-1} \right|\_{P\_2} \Bigg|\_{P\_2} \tag{8}$$

$$\left| \upsilon\_3 = \left| \left( \left( \chi\_3 - \upsilon\_1 \right) \middle| P\_1^{-1} \right|\_{P\_3} - \upsilon\_2 \right) \middle| P\_2^{-1} \right|\_{P\_3} \Bigg|\_{P\_3} \tag{9}$$

$$\boldsymbol{\upsilon}\_{4} = \left| \left( \left( \boldsymbol{\chi}\_{4} - \boldsymbol{\upsilon}\_{1} \right) \middle| \boldsymbol{P}\_{1}^{-1} \right|\_{\boldsymbol{P}\_{4}} - \left. \boldsymbol{\upsilon}\_{2} \right| \middle| \boldsymbol{P}\_{2}^{-1} \right|\_{\boldsymbol{P}\_{4}} - \left. \boldsymbol{\upsilon}\_{3} \right| \left| \boldsymbol{P}\_{3}^{-1} \right|\_{\boldsymbol{P}\_{4}} \Bigg|\_{\boldsymbol{P}\_{4}} \tag{10}$$

Although MRC implies a sequential process, for two and three-moduli sets it can be lead to simple and efficient reverse conversion equations.

The New CRT-I (Wang, 2000; Molahosseini et al., 2010) uses a more efficient conversion formula

$$X = \mathbf{x}\_1 + P\_1 \left| k\_1 (\mathbf{x}\_2 - \mathbf{x}\_1) + k\_2 P\_2 (\mathbf{x}\_3 - \mathbf{x}\_2) + k\_3 P\_2 P\_3 (\mathbf{x}\_4 - \mathbf{x}\_3) \right|\_{P\_2 P\_3 P\_4} \tag{11}$$

3 2 3, 3, 1 3,1 3,0 1 ( ) *n n n bits*

4 2 4,2 4,2 1 4,1 4,0 2 1 ( ) *n n n bits*

 

3 2 4 3

2 ( ) (2 2 2 )(2 1)( ) <sup>2</sup> 2 (2 1)(2 1)( ) *<sup>n</sup>*

This main conversion equation can be simplified based on the following two well-known

*Property 1*: The residue of a negative residue number (ï*v*) in modulo (2*<sup>n</sup>* ï 1) is the one's

*Property 2*: The multiplication of a residue number *v* by 2*P* in modulo (2*<sup>n</sup>* ï 1) is carried out

1 2*<sup>n</sup> Xx Z* (26)

Next, the binary vectors v*i*'s which have been simplified based on properties 1 and 2 are as

1 1,1 1,0 1, 1 1,1 1,0 1, 1 1,1 1,0 1, 1 1,1 1,0 1, 1 1,3 1,2 2 2 *nnnn n n nn*

> 31 3,1 3,0 3, 3,1 3,0 3, 3,3 3,2 1 1 21 1 1 11 1 11 *n n n n <sup>n</sup> <sup>n</sup>*

 

41 4, 4,1 4,0 4,2 4, 2 4, 1

 

0 00 *<sup>n</sup> n nn <sup>n</sup> n n v x xx x x x*

> 1 11 1 11 *<sup>n</sup> n n <sup>n</sup>*

*v xx x xx x xx*

1 11 *<sup>n</sup> <sup>n</sup> <sup>n</sup>*

1 2 1 1 0 000 000 *n n n n n n*

> 

> > <sup>1</sup> 2 1

 

 

 

*v xx x xx x xx x xx x xx*

 

2 2, 1 2,1 2,0

32 3, 3,1 3,0 3, 3,1 3,0

2 1 <sup>1</sup>

42 4,2 4,1 4,0

 

*v x xx*

*v x xx x xx*

*v x xx* 

 

*x x*

With substituting the required multiplicative inverses and values of moduli, i.e. *P*1=2*n*, *P*2=2*n*+1, *P*3=2*2n*+1 and *P*4=2*n*–1 in the New CRT-I formulas (11)-(14), we achieve the

(23)

(24)

4

(29)

 

(25)

(28)

(30)

(31)

(32)

(33)

1 4 2 1

1 2 31 32 41 42 <sup>4</sup> 2 1 *Zv v v v v v <sup>n</sup>* (27)

 

 

> 

3

 

*x x x xx* 

*x x x xx*

3 32 21 2

*x x x x X x*

*n n n nn*

1 2 2

complement of *v*, where 0*v*< 2*<sup>n</sup>* ï 1 (Hariri et al. 2008).

 

 

*nn n*

by *P* bit circular left shift, where *P* is a natural number (Hariri et al. 2008).

*n*

following conversion equation:

modulo (2*n*-1) arithmetic properties.

Now, (25) can be rewritten as follows

Where

below

Where

$$\left|k\_1 \times P\_1\right|\_{P\_2 P\_3 P\_4} = \mathbf{1} \tag{12}$$

$$\left|k\_2 \times P\_1 \times P\_2\right|\_{p\_3 p\_4} = 1\tag{13}$$

$$\left|k\_3 \times P\_1 \times P\_2 \times P\_3\right|\_{p\_4} = 1\tag{14}$$

Moreover, New CRT-II (Wang, 2000; Molahosseini et al., 2010) provides a tree-like architecture by using the following equations

$$X = Z + P\_1 P\_2 \left| k\_1(Y - Z) \right|\_{p\_3 p\_4} \tag{15}$$

$$Z = \boldsymbol{\mathfrak{x}}\_1 + P\_1 \left| k\_2 (\boldsymbol{\mathfrak{x}}\_2 - \boldsymbol{\mathfrak{x}}\_1) \right|\_{\boldsymbol{\mathfrak{p}}\_2} \tag{16}$$

$$Y = \boldsymbol{\varkappa}\_3 + P\_3 \left| k\_3 \left( \boldsymbol{\varkappa}\_4 - \boldsymbol{\varkappa}\_3 \right) \right|\_{P\_4} \tag{17}$$

Where

$$\left|k\_1 P\_1 P\_2\right|\_{P\_3 P\_4} = \mathbf{1} \tag{18}$$

$$\left\|k\_2 P\_1\right\|\_{P\_2} = 1\tag{19}$$

$$\left|k\_3 P\_3\right|\_{P\_4} = 1\tag{20}$$

The New CRTs have potentiality to create higher performance reverse converters than CRT and MRC particularly for some special four-moduli sets. Hence, many research have been done in the recent years to discover efficient four-moduli sets which can be fitted with properties of New CRTs. In the next sections, we investigate the reverse converters that are previously designed for these four-moduli sets.

#### **3. Reverse converter for the moduli set {2***<sup>n</sup>* **–1, 2***<sup>n</sup>* **, 2***<sup>n</sup>* **+1, 2***2n***+1}**

The moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} was introduced by (Cao et al., 2003). They have used New CRT-I to design a fully adder-based reverse converter. In the following, we briefly review the conversion formulas and hardware architecture of the converter of (Cao et al., 2003). First, consider the moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} with corresponding residues (*x*1, *x*2, *x*3, *x*4). The residues can be represented in bit-level as below

$$\mathfrak{X}\_1 = (\underbrace{\mathfrak{x}\_{1,n-1}\mathfrak{x}\_{1,n-2}\cdots\mathfrak{x}\_{1,1}\mathfrak{x}\_{1,0}}\_{n\text{ bits}})\_2 \tag{21}$$

$$\mathbf{x}\_2 = (\underbrace{\mathbf{x}\_{2,n-1}\mathbf{x}\_{2,n-2}\cdots\mathbf{x}\_{2,1}\mathbf{x}\_{2,0}}\_{n\text{ bits}})\_2\tag{22}$$

$$\mathfrak{X}\_3 = (\underbrace{\mathfrak{x}\_{3,n}\mathfrak{x}\_{3,n-1}\cdots\mathfrak{x}\_{3,1}\mathfrak{x}\_{3,0}}\_{n+1 \text{ bits}})\_2 \tag{23}$$

$$\mathfrak{X}\_4 = (\underbrace{\mathfrak{x}\_{4,2n}\mathfrak{x}\_{4,2n-1}\cdots\mathfrak{x}\_{4,1}\mathfrak{x}\_{4,0}}\_{2,n+1\text{ bits}})\_2 \tag{24}$$

With substituting the required multiplicative inverses and values of moduli, i.e. *P*1=2*n*, *P*2=2*n*+1, *P*3=2*2n*+1 and *P*4=2*n*–1 in the New CRT-I formulas (11)-(14), we achieve the following conversion equation:

$$X = \mathbf{x}\_1 + \mathbf{2}^n \begin{vmatrix} 2^{3n} (\mathbf{x}\_3 - \mathbf{x}\_2) + (2^{3n-2} + 2^{2n-1} - 2^{n-2})(2^n + 1)(\mathbf{x}\_4 - \mathbf{x}\_3) \\ + 2^{n-2}(2^n + 1)(2^{2n} + 1)(\mathbf{x}\_1 - \mathbf{x}\_4) \end{vmatrix}\_{2^{4n} - 1} \tag{25}$$

This main conversion equation can be simplified based on the following two well-known modulo (2*n*-1) arithmetic properties.

*Property 1*: The residue of a negative residue number (ï*v*) in modulo (2*<sup>n</sup>* ï 1) is the one's complement of *v*, where 0*v*< 2*<sup>n</sup>* ï 1 (Hariri et al. 2008).

*Property 2*: The multiplication of a residue number *v* by 2*P* in modulo (2*<sup>n</sup>* ï 1) is carried out by *P* bit circular left shift, where *P* is a natural number (Hariri et al. 2008).

Now, (25) can be rewritten as follows

$$X = \mathfrak{x}\_1 + \mathfrak{Z}^n Z \tag{26}$$

Where

340 Applications of Digital Signal Processing

Moreover, New CRT-II (Wang, 2000; Molahosseini et al., 2010) provides a tree-like

12 1( ) *P P*

1 12 2 1 ( ) *<sup>P</sup>*

3 33 4 3 ( ) *<sup>P</sup>*

3 4 <sup>112</sup> 1 *P P*

> 2 2 1 1 *P*

> 4 3 3 1 *P*

The New CRTs have potentiality to create higher performance reverse converters than CRT and MRC particularly for some special four-moduli sets. Hence, many research have been done in the recent years to discover efficient four-moduli sets which can be fitted with properties of New CRTs. In the next sections, we investigate the reverse converters that are

The moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} was introduced by (Cao et al., 2003). They have used New CRT-I to design a fully adder-based reverse converter. In the following, we briefly review the conversion formulas and hardware architecture of the converter of (Cao et al., 2003). First, consider the moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} with corresponding residues (*x*1,

> 1 2 1, 1 1, 2 1,1 1,0 ( ) *n n n bits x x x xx*

> 2 2 2, 1 2, 2 2,1 2,0 ( ) *n n n bits x x x xx*

**–1, 2***<sup>n</sup>*

**, 2***<sup>n</sup>*

architecture by using the following equations

previously designed for these four-moduli sets.

**3. Reverse converter for the moduli set {2***<sup>n</sup>*

*x*2, *x*3, *x*4). The residues can be represented in bit-level as below

<sup>234</sup> 1 1 <sup>1</sup> *PPP k P*u (12)

3 4 <sup>212</sup> <sup>1</sup> *P P k PP* <sup>u</sup> <sup>u</sup>(13)

<sup>4</sup> <sup>3123</sup> <sup>1</sup> *<sup>P</sup> k PPP* <sup>u</sup> uu (14)

*X Z PP k Y Z* (15)

*Z x Pk x x* (16)

*Y x Pk x x* (17)

*k PP* (18)

*k P* (19)

*k P* (20)

**+1, 2***2n***+1}** 

(21)

(22)

3 4

2

4

Where

Where

$$Z = \left| \upsilon\_1 + \upsilon\_2 + \upsilon\_{31} + \upsilon\_{32} + \upsilon\_{41} + \upsilon\_{42} \right|\_{2^{4\pi} - 1} \tag{27}$$

Next, the binary vectors v*i*'s which have been simplified based on properties 1 and 2 are as below

$$\boldsymbol{\upsilon}\_{1} = \underbrace{\boldsymbol{\chi}\_{1,1}\boldsymbol{\chi}\_{1,0}}\_{\frac{1}{2}}\underbrace{\boldsymbol{\chi}\_{1,n-1}\cdots\boldsymbol{\chi}\_{1,1}\boldsymbol{\chi}\_{1,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{1,n-1}\cdots\boldsymbol{\chi}\_{1,1}\boldsymbol{\chi}\_{1,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{1,n-1}\cdots\boldsymbol{\chi}\_{1,1}\boldsymbol{\chi}\_{1,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{1,n-1}\cdots\boldsymbol{\chi}\_{1,3}\boldsymbol{\chi}\_{1,2}}\_{n-2}\tag{28}$$

$$w\_2 = \underbrace{\overline{x}\_{2,n-1} \cdots \overline{x}\_{2,1} \overline{x}\_{2,0}}\_{n} \underbrace{1 \cdots 1 \mathbf{1}}\_{3n} \tag{29}$$

$$w\_{31} = \underbrace{\overline{x}\_{3,1}\overline{x}\_{3,0}}\_{2}\underbrace{1\cdots11}\_{n-1}\underbrace{\overline{x}\_{3,n}\cdots\overline{x}\_{3,1}\overline{x}\_{3,0}}\_{n+1}\underbrace{1\cdots11}\_{n-1}\underbrace{\overline{x}\_{3,n}\cdots\overline{x}\_{3,3}\overline{x}\_{3,2}}\_{n-1}\tag{30}$$

$$w\_{32} = \underbrace{0\propto\underbrace{\times\dots\times\times\_{3,1}\times\dots\times}\_{n+1}}\_{n+1}\underbrace{0\cdots00}\_{n-1}\underbrace{\times\dots\times\times\_{3,1}\times\dots}\_{n+1}\underbrace{0\cdots00}\_{n-2}\tag{31}$$

$$
\varpi\_{41} = \underbrace{\boldsymbol{\chi}\_{4,n} \cdots \boldsymbol{\chi}\_{4,1} \boldsymbol{\chi}\_{4,0}}\_{n+1} \underbrace{\boldsymbol{0} \cdots \boldsymbol{0} \boldsymbol{0}}\_{2n-1} \underbrace{\boldsymbol{\chi}\_{4,2n} \cdots \boldsymbol{\chi}\_{4,n+2} \boldsymbol{\chi}\_{4,n+1}}\_{n} \tag{32}
$$

$$\boldsymbol{\upsilon}\_{42} = \underbrace{\mathbf{1} \cdots \mathbf{1} \mathbf{1}}\_{n} \underbrace{\overline{\mathbf{1}} \mathbf{1}\_{4,2n} \cdots \overline{\mathbf{x}}\_{4,1} \overline{\mathbf{x}}\_{4,0}}\_{2n+1} \underbrace{\mathbf{1} \cdots \mathbf{1} \mathbf{1}}\_{n-1} \tag{33}$$

1 1,2 1 1,1 1,0 2,2 2,2 2,1 2 2 *n n*

31 3,1 3,0 3, 3,1 3,0 3, 3,3 3,2

 

4 4,1 4,0 4, 1 4,1 4,0 4, 1 4,1 4,0 4, 1 4,1 4,0 4, 1 4,3 4,2

Therefore, only five operands should be added using three CSAs with EAC followed by a CPA with EAC (Piestrak, 1994, 1995). Hence, in comparison with (Cao et al., 2003) which needed four CSAs, the (Molahosseini et al., 2010) results in reduction of one 4*n*-bit CSA with EAC; while providing larger dynamic range. The Fig. 2 shows the hardware implementation

Operand Preparation Unit

4*n*-bit CSA with EAC

4*n*-bit CSA with EAC

<sup>1</sup>*x* <sup>2</sup> *x* <sup>3</sup> *x* <sup>4</sup> *x*

*v xx x xx x xx x xx x xx*

 

Fig. 2. The converter for moduli set {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} (Molahosseini et al., 2010)

The main disadvantage of the moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} and {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} is the modulo 2*2n*+1. Because, performance of modulo arithmetic circuits for 2*2n*+1 is much

**–1, 2***<sup>n</sup>*

1*x*

 

4*n*-bit CSA with EAC

4*n*-bit CPA with EAC

*<sup>Z</sup>*

*X*

**, 2***<sup>n</sup>*

**+1, 22***n***+1–1}** 

**5. The reverse converter for the moduli set {2***<sup>n</sup>*

*nnnn*

*v xx x xx x xx*

 

32 2,0 3, 3,1 3,0 3, 3,1 3,0

*v x x xx x xx*

of this converter.

0 00 *n n* 0 00 *n n n n*

*v x xx x xx* 

2 2,2 2,1 2,0

 

*v x xx*

*n n*

2 1 2 1 *<sup>n</sup>* 0 00 *<sup>n</sup> <sup>n</sup>*

1 1 1 1

1 2 1 1 *n n* 1 11 1 11 *n n n n*

 

*n n nn*

 

 

 

 

  (37)

(38)

(39)

(40)

(41)

2

 

Therefore, these six operands should be added using a modulo (24*n*-1) multi-operand adder which can be realised by four carry-save adders (CSAs) with end-around carry (EAC) followed by a modulo (24*n*-1) carry propagate adder (CPA) with EAC (Piestrak, 1994, 1995). The hardware architecture of the resulted converter is shown in Fig. 1.

Fig. 1. The converter for moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} (Cao et al., 2003)

#### **4. Reverse converter for the moduli set {2***<sup>n</sup>* **–1, 2***<sup>n</sup>* **+1, 2<sup>2</sup>***<sup>n</sup>* **, 2***2n***+1}**

The moduli set {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} has been recently introduced by (Molahosseini et al., 2010) to provide large dyamic range (6*n*-bit), and high-speed reverse converter. Similar to (Cao et al., 2003), the New CRT-I has used to design converter but with different moduli order, i.e. {2*2n*, 2*2n*+1, 2*n*+1, 2*n*–1}. Therefore, by letting *P*1=2*2n*, *P*2=2*2n*+1, *P*3=2*n*+1 and *P*4=2*n*–1, and putting the multiplicative inverses in the New CRT-I formulas (11)-(14), we have the following main conversion equation (Molahosseini et al., 2010).

$$X = \boldsymbol{\chi}\_1 + 2^{2n} \begin{vmatrix} 2^{2n} (\boldsymbol{\chi}\_2 - \boldsymbol{\chi}\_1) + 2^{2n-1} (2^{2n} + 1)(\boldsymbol{\chi}\_3 - \boldsymbol{\chi}\_2) \\ + 2^{n-2} (2^{2n} + 1)(2^n + 1)(\boldsymbol{\chi}\_4 - \boldsymbol{\chi}\_3) \end{vmatrix}\_{2^{4n} - 1} \tag{34}$$

Simplification of this equation can be done as follows

$$\mathbf{X} = \mathbf{x}\_1 + \mathbf{2}^{\mathbf{2}n} \mathbf{Z} \tag{35}$$

Where

$$Z = \left| \upsilon\_1 + \upsilon\_2 + \upsilon\_{31} + \upsilon\_{32} + \upsilon\_4 \right|\_{2^{4\pi}-1} \tag{36}$$

342 Applications of Digital Signal Processing

Therefore, these six operands should be added using a modulo (24*n*-1) multi-operand adder which can be realised by four carry-save adders (CSAs) with end-around carry (EAC) followed by a modulo (24*n*-1) carry propagate adder (CPA) with EAC (Piestrak, 1994, 1995).

Operand Preparation Unit

<sup>1</sup>*x* <sup>2</sup> *x* <sup>3</sup> *x* <sup>4</sup> *x*

The hardware architecture of the resulted converter is shown in Fig. 1.

4*n*-bit CSA with EAC

4*n*-bit CSA with EAC

Fig. 1. The converter for moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} (Cao et al., 2003)

following main conversion equation (Molahosseini et al., 2010).

*n*

Simplification of this equation can be done as follows

<sup>2</sup>

1 2 2

**–1, 2***<sup>n</sup>*

 

4*n*-bit CSA with EAC

4*n*-bit CPA with EAC

*<sup>Z</sup>*

*X*

1*x*

The moduli set {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} has been recently introduced by (Molahosseini et al., 2010) to provide large dyamic range (6*n*-bit), and high-speed reverse converter. Similar to (Cao et al., 2003), the New CRT-I has used to design converter but with different moduli order, i.e. {2*2n*, 2*2n*+1, 2*n*+1, 2*n*–1}. Therefore, by letting *P*1=2*2n*, *P*2=2*2n*+1, *P*3=2*n*+1 and *P*4=2*n*–1, and putting the multiplicative inverses in the New CRT-I formulas (11)-(14), we have the

2 21 2

*nn n x x x x X x*

*n n n*

2 2 1 3 2

2 (2 1)(2 1)( ) *<sup>n</sup>*

*x x*

2 ( ) 2 (2 1)( ) <sup>2</sup>

**+1, 2<sup>2</sup>***<sup>n</sup>*

4*n*-bit CSA with EAC

**, 2***2n***+1}** 

4

(34)

4 3 2 1

<sup>1</sup> 2 *<sup>n</sup> Xx Z* (35)

1 2 31 32 4 <sup>4</sup> 2 1 *Zv v v v v <sup>n</sup>* (36)

**4. Reverse converter for the moduli set {2***<sup>n</sup>*

Where

$$
\overline{w}\_1 = \underbrace{\overline{\underline{\chi}}\_{1,2n-1} \cdots \overline{\underline{\chi}}\_{1,1} \overline{\underline{\chi}}\_{1,0}}\_{2n} \underbrace{\overline{\underline{\chi}}\_{2,2n} \cdots \overline{\underline{\chi}}\_{2,2} \overline{\underline{\chi}}\_{2,1}}\_{2n} \tag{37}
$$

$$
\omega\_2 = \underbrace{\varkappa\_{2,2n} \cdots \varkappa\_{2,1} \varkappa\_{2,0}}\_{2n+1} \underbrace{0 \cdots 0}\_{2n-1} \tag{38}
$$

$$
\omega\_{31} = \mathfrak{x}\_{3,1}\mathfrak{x}\_{3,0}\underbrace{\mathfrak{O}\cdots\mathfrak{O}\mathfrak{O}}\_{n-1}\underbrace{\mathfrak{x}\_{3,n}\cdots\mathfrak{x}\_{3,1}\mathfrak{x}\_{3,0}}\_{n+1}\underbrace{\mathfrak{O}\cdots\mathfrak{O}\mathfrak{O}}\_{n-1}\underbrace{\mathfrak{x}\_{3,n}\cdots\mathfrak{x}\_{3,3}\mathfrak{x}\_{3,2}}\_{n-1}\tag{39}
$$

$$
\sigma\_{32} = \overline{\mathfrak{X}}\_{2,0} \underbrace{\overline{\mathfrak{X}}\_{3,n} \cdots \overline{\mathfrak{X}}\_{3,1} \overline{\mathfrak{X}}\_{3,0}}\_{n+1} \underbrace{1 \cdots 11}\_{n-1} \underbrace{\overline{\mathfrak{X}}\_{3,n} \cdots \overline{\mathfrak{X}}\_{3,1} \overline{\mathfrak{X}}\_{3,0}}\_{n+1} \underbrace{1 \cdots 11}\_{n-2} \tag{40}
$$

$$\boldsymbol{\upsilon}\_{4} = \boldsymbol{\chi}\_{4,1}\boldsymbol{\chi}\_{4,0}\underbrace{\boldsymbol{\chi}\_{4,n-1}\cdots\boldsymbol{\chi}\_{4,1}\boldsymbol{\chi}\_{4,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{4,n-1}\cdots\boldsymbol{\chi}\_{4,1}\boldsymbol{\chi}\_{4,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{4,n-1}\cdots\boldsymbol{\chi}\_{4,1}\boldsymbol{\chi}\_{4,0}}\_{n}\underbrace{\boldsymbol{\chi}\_{4,n-1}\cdots\boldsymbol{\chi}\_{4,3}\boldsymbol{\chi}\_{4,2}}\_{n-2}\tag{41}$$

Therefore, only five operands should be added using three CSAs with EAC followed by a CPA with EAC (Piestrak, 1994, 1995). Hence, in comparison with (Cao et al., 2003) which needed four CSAs, the (Molahosseini et al., 2010) results in reduction of one 4*n*-bit CSA with EAC; while providing larger dynamic range. The Fig. 2 shows the hardware implementation of this converter.

Fig. 2. The converter for moduli set {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} (Molahosseini et al., 2010)

#### **5. The reverse converter for the moduli set {2***<sup>n</sup>* **–1, 2***<sup>n</sup>* **, 2***<sup>n</sup>* **+1, 22***n***+1–1}**

The main disadvantage of the moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} and {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1} is the modulo 2*2n*+1. Because, performance of modulo arithmetic circuits for 2*2n*+1 is much

*P H T T TT H H H* 

5 3, 1 3,1 3,0 3,

6 1 10 1 10 *n n n n v K KK K KK* 

7 1, 1 1,1 1,0 2

8 21 10 2 *n*

Therefore, two modulo adders needed to realize (46) and (50). Moreover, (55) can be implemented using three CSAs with EAC followed by a CPA with EAC. Note that some of the full adders (FAs) of these CPAs and CSAs are simplified to XOR/AND or XNOR/OR pairs due to the constant bits of the inputs. The final result, i.e. (53) can be obtained by a (4*n*+1)-bit binaryadder with '1' carry-in. Fig. 3 presents the reverse converter for the moduli

The moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} reduces the total delay of RNS arithmetic unit versus the moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} and {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1}. However, still the inter-channel delay of modulo 2*2n*+1–1 is larger than the other three moduli, i.e. 2*n*–1, 2*n* and 2*n*+1. Due to this, the moduli set {2*n*–1, 2*n*+1, 22*n*, 22*n*+1–1} has been recently proposed by (Molahosseini & Navi, 2010). The main advantage of this set is that it provides all of the merits of the moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} while providing larger dynamic range (6*n*-bit). Because, enhancing modulo 2*<sup>n</sup>*

The converter of (Molahosseini & Navi, 2010) has a two-level architecutre. In other words, they have used a combinatorial conversion algorithm; consisting both CRT and MRC. First, the previous CRT-Based design of reverse converter for the subset {22*n*, 2*n*–1, 2*n*+1} (Hiasat & Sweidan, 2004) is used to achieve the weighted equivalent of the residues (*x*1, *x*2, *x*3) as below

2

*n v H HH* 

 

 

*n n* 0 00 *<sup>n</sup> <sup>n</sup> v x xx x*

*n n* 1 11 *<sup>n</sup> <sup>n</sup> v x xx H*

 

2 1

2 *<sup>n</sup>*

Where

set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1}.

Where

**6. Reverse converter for the moduli set {2***<sup>n</sup>*

to 22*n* is not increasing the complexity of the reverse converter.

2 1 2 (2 1) 2 ( ) <sup>1</sup>

*n n n n*

*n n <sup>n</sup> X Z T x PT* (53)

5 678 <sup>2</sup> 2 1 *T v vvv <sup>n</sup>* (55)

(54)

(56)

(57)

(58)

(59)

**, 22***n***+1–1}** 

<sup>1</sup> 2 *<sup>n</sup> Zx Y* (60)

<sup>1234</sup> <sup>2</sup> 2 1 *Yvvvv <sup>n</sup>* (61)

 

2 1 10 2 1 0 2 2 1

1

 

1

**–1, 2***<sup>n</sup>*

**+1, 2<sup>2</sup>***<sup>n</sup>*

 

 

lower than the moduli 2*n*–1 and 2*n*+1. Hence, (Molahosseini et al., 2010) have been substituted 2*2n*+1 with well-formed number 2*2n*+1–1 that results in introducing the large dynamic range four-moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1}. Besides, they have used New CRT-II to design an efficient reverse converter for this moduli set as described below.

With considering *P*1=2*n*, *P*2=22*n*+1–1, *P*3=2*n*+1, *P*4=2*n*–1, and the New CRT-II formulas (15)- (17), we have the following conversion equations (Molahosseini et al., 2010)

$$X = Z + 2^n(2^{2n+1} - 1) \Big| 2^n(Y - Z) \Big|\_{2^{2n} - 1} \tag{42}$$

Where

$$Z = \boldsymbol{\chi}\_1 + \mathbf{2}^n \Big| \mathbf{2}^{n+1} (\boldsymbol{\chi}\_2 - \boldsymbol{\chi}\_1) \Big|\_{\mathbf{2}^{2n+1} - 1} \tag{43}$$

$$Y = \chi\_3 + (2^n + 1) \left| 2^{n-1} (\chi\_4 - \chi\_3) \right|\_{2^n - 1} \tag{44}$$

Simplified versions of these equations have been computed in (Molahosseini et al., 2010). Here, we briefly review the final simplified equations. First, (43) can be rewritten as

$$Z = \mathfrak{x}\_1 + \mathfrak{Z}^n H \tag{45}$$

Where

$$H = \left| \upsilon\_1 + \upsilon\_2 \right|\_{2^{2^{n+1}} - 1} \tag{46}$$

$$\mathcal{U}\_1 = \underbrace{\mathbb{X}\_{2,n-1} \cdots \mathbb{X}\_{2,1} \mathbb{X}\_{2,0}}\_{n} \underbrace{\mathbb{X}\_{2,2n} \cdots \mathbb{X}\_{2,n+1} \mathbb{X}\_{2,n}}\_{n+1} \tag{47}$$

$$\upsilon\_2 = \underbrace{\overline{\chi}\_{1,n-1} \cdots \overline{\chi}\_{1,1} \overline{\chi}\_{1,0}}\_{n} \underbrace{1 \cdots 1 \mathbf{1}}\_{n+1} \tag{48}$$

Next, for simplifying (44) we have

$$Y = \mathfrak{x}\_3 + (\mathfrak{Z}^n + 1)\mathcal{K} \tag{49}$$

Where

$$K = \left| \upsilon\_3 + \upsilon\_4 \right|\_{2^\ast - 1} \tag{50}$$

$$\boldsymbol{\sigma}\_{3} = \underbrace{\boldsymbol{\mathfrak{x}\_{4,0}\boldsymbol{\mathfrak{x}}\_{4,n-1}}\_{n} \cdots \boldsymbol{\mathfrak{x}\_{4,2}\boldsymbol{\mathfrak{x}}\_{4,1}}\_{n}}\_{n} \tag{51}$$

$$\boldsymbol{\sigma}\_{4} = \begin{cases} \frac{\overline{\boldsymbol{x}}\_{3,0} \overline{\boldsymbol{x}}\_{3,n-1} \cdots \overline{\boldsymbol{x}}\_{3,2} \overline{\boldsymbol{x}}\_{3,1}}{n} & \text{if } \ x\_{3,n} = 0\\ 0 \underbrace{\boldsymbol{1} \cdots \boldsymbol{1} \mathbf{1}}\_{n-1} & \text{if } \ x\_{3,n} = \mathbf{1} \end{cases} \tag{52}$$

Eventually, (42) can be computed as below

$$X = Z + \mathcal{Z}"\{\mathcal{Z}^{2n+1} - 1\}
\\
T = \mathcal{X}\_1 + \mathcal{Z}"\{P - T\}\tag{53}$$

Where

344 Applications of Digital Signal Processing

lower than the moduli 2*n*–1 and 2*n*+1. Hence, (Molahosseini et al., 2010) have been substituted 2*2n*+1 with well-formed number 2*2n*+1–1 that results in introducing the large dynamic range four-moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1}. Besides, they have used New CRT-II

With considering *P*1=2*n*, *P*2=22*n*+1–1, *P*3=2*n*+1, *P*4=2*n*–1, and the New CRT-II formulas (15)-

1 <sup>1</sup> 2 1 2 1 22 ( ) *<sup>n</sup> n n Zx x x* 

Simplified versions of these equations have been computed in (Molahosseini et al., 2010).

1 2, 1 2,1 2,0 2,2 2, 1 2,

3 4,0 4, 1 4,2 4,1 *n n v xx xx* 

3,0 3, 1 3,2 3,1 3

*xx xx x*

0 if 1

*n ,n*

N

*n*

1 1 11

°°

*n*

 

4

® ° °¯

*v*

Eventually, (42) can be computed as below

 

2 1, 1 1,1 1,0

 

*v x xx*

*n n nn n n v x xx x x x*

> *<sup>n</sup>* 1 11 *<sup>n</sup> <sup>n</sup>*

2 1 2 (2 1) 2 ( ) *<sup>n</sup>*

1 <sup>3</sup> 4 3 2 1 (2 1) 2 ( ) *<sup>n</sup>*

2 1

*nn n X Z Y Z*

*n n Y x x x*

Here, we briefly review the final simplified equations. First, (43) can be rewritten as

2

2 1

1

1

 

 

(42)

(43)

(44)

<sup>1</sup> 2*<sup>n</sup> Zx H* (45)

1 2 2 1 2 1 *Hvv <sup>n</sup>* (46)

<sup>3</sup> (2 1) *<sup>n</sup> Yx K* (49)

3 4 2 1 *Kvv <sup>n</sup>* (50)

3

*x*

*,n*

if 0

(47)

(48)

(51)

(52)

to design an efficient reverse converter for this moduli set as described below.

(17), we have the following conversion equations (Molahosseini et al., 2010)

Where

Where

Where

Next, for simplifying (44) we have

$$P = H + \mathfrak{L}^{2n+1}T = \underbrace{T\_{2n-1} \cdots T\_1 T\_0}\_{2n} \underbrace{H\_{2n} \cdots H\_1 H\_0}\_{2n+1} \tag{54}$$

$$T = \left| \upsilon\_5 + \upsilon\_6 + \upsilon\_7 + \upsilon\_8 \right|\_{2^{2^n} - 1} \tag{55}$$

$$
\upsilon\_5 = \underbrace{\varkappa\_{3,n-1} \cdots \varkappa\_{3,1} \varkappa\_{3,0}}\_{n} \underbrace{\mathbf{0} \cdots \mathbf{0} \mathbf{0}}\_{n-1} \varkappa\_{3,n} \tag{56}
$$

$$
\upsilon\_{\delta} = \underbrace{\mathbf{K}\_{n-1} \cdots \mathbf{K}\_1 \mathbf{K}\_0}\_{n} \underbrace{\mathbf{K}\_{n-1} \cdots \mathbf{K}\_1 \mathbf{K}\_0}\_{n} \tag{57}
$$

$$\upsilon\_7 = \underbrace{\overline{\chi}\_{1,n-1} \cdots \overline{\chi}\_{1,1} \overline{\chi}\_{1,0}}\_{n} \underbrace{1 \cdots 11}\_{n-1} \overline{H}\_{2n} \tag{58}$$

$$w\_8 = \underbrace{\overline{H}\_{2n-1} \cdots \overline{H}\_1 \overline{H}\_0}\_{2n} \tag{59}$$

Therefore, two modulo adders needed to realize (46) and (50). Moreover, (55) can be implemented using three CSAs with EAC followed by a CPA with EAC. Note that some of the full adders (FAs) of these CPAs and CSAs are simplified to XOR/AND or XNOR/OR pairs due to the constant bits of the inputs. The final result, i.e. (53) can be obtained by a (4*n*+1)-bit binaryadder with '1' carry-in. Fig. 3 presents the reverse converter for the moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1}.

#### **6. Reverse converter for the moduli set {2***<sup>n</sup>* **–1, 2***<sup>n</sup>* **+1, 2<sup>2</sup>***<sup>n</sup>* **, 22***n***+1–1}**

The moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} reduces the total delay of RNS arithmetic unit versus the moduli sets {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} and {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1}. However, still the inter-channel delay of modulo 2*2n*+1–1 is larger than the other three moduli, i.e. 2*n*–1, 2*n* and 2*n*+1. Due to this, the moduli set {2*n*–1, 2*n*+1, 22*n*, 22*n*+1–1} has been recently proposed by (Molahosseini & Navi, 2010). The main advantage of this set is that it provides all of the merits of the moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} while providing larger dynamic range (6*n*-bit). Because, enhancing modulo 2*<sup>n</sup>* to 22*n* is not increasing the complexity of the reverse converter.

The converter of (Molahosseini & Navi, 2010) has a two-level architecutre. In other words, they have used a combinatorial conversion algorithm; consisting both CRT and MRC. First, the previous CRT-Based design of reverse converter for the subset {22*n*, 2*n*–1, 2*n*+1} (Hiasat & Sweidan, 2004) is used to achieve the weighted equivalent of the residues (*x*1, *x*2, *x*3) as below

$$\mathbf{Z} = \mathbf{x}\_1 + \mathbf{2}^{2n}\mathbf{Y} \tag{60}$$

Where

$$Y = \left| \upsilon\_1 + \upsilon\_2 + \upsilon\_3 + \upsilon\_4 \right|\_{2^{2^n} - 1} \tag{61}$$

*nn n n n X Z x Z x Y TT*

5 1,2 2 1,1 1,0 1,2 1 2 1

> 2 *<sup>n</sup>* 0 *n v Y YY*

The hardware implementation of this converter relies on two modulo adders for realization of (61) and (67). In other words, (61) needed two 2*n*-bit CSAs with EAC and a 2*n*-bit CPA with EAC, and a (2*n*+1)-bit CPA with EAC is used to realize (67). Besides, (66) only requires one (4*n*+1)-bit regular binary adder; the required multiplications all can be done using shift

Table 1 presents the total hardware requirements and conversion delays of the reverse converters for the large dynamic range four-moduli sets in terms of logic gates and FAs. Note that *A*FA and *D*FA indicate the area and delay of one FA, respectively. It can be seen that the fastest converter is the converter for moduli set {2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1}. Because, the dynamic range of this set is 6*n*-bit while the dynamic range of moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1} is 5*n*-bit. Therefore, for providing the same dynamic range, the value of *n* for the first

**Moduli set Hardware Requirements Conversion Delay** 

+ (4*n*+1)AXNOR +(4*n*+1)AOR + (7*n*+1)ANOT + (*n*)AMUX2×1

(10*n*+3)AFA + (*n*+1)AXOR + (*n*+1)AAND + (3*n*–1)AXNOR +(*3n*–1)AOR + (7*n*+3)ANOT

(11*n*+6)AFA + (2*n*–1)AXOR + (2*n*–1)AAND + (4*n*)AXNOR +(4*n*)AOR + (5*n*+3)ANOT

(10*n*+6)AFA + (4*n*–3)AXOR + (4*n*–3)AAND + (2*n*–3)AXNOR +(2*n*–3)AOR + (6*n*+3)ANOT

Table 1. Hardware requirements and conversion delays of the reverse converters for the

(8*n*+2)AFA + (*n*–1)AXOR + (*n*–1)AAND

*n n n*

*n v x xx x* 

2 1

*n v x xx x x* 

*n n* 0

6 2 1 10

7 4,2 2 4,1 4,0 4,2 4,2 1

and concatenation. The converter has been depicted in Fig. 4.

**7. Complexity comparison** 

{2*n*–1, 2*n*, 2*n*+1, 22*n*+1–1}

{2*n*–1, 2*n*+1, 2*2n*, 2*2n*+1–1}

{2*n* –1,2*n*, 2*n* +1, 22*n* +1}

{2*n*–1, 2*n*+1, 22*n*, 22*n*+1}

large dynamic range four-moduli sets

Where

2 1 2 2 23 2 2 4 1 2 1 2 (2 1) 2 ( ) 2( 2 ) *<sup>n</sup>*

(66)

<sup>567</sup> 2 1 2 1 *Tvvv <sup>n</sup>* (67)

(68)

(69)

(70)

(12*n*+5)*D*FA+3*D*NOT+*D*MUX

(12*n*+6)*D*FA+2*D*NOT

(8*n*+3)*D*FA+*D*NOT

(8*n*+3)*D*FA+*D*NOT

Fig. 3. The converter for moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} (Molahosseini et al., 2010)

$$w\_1 = \underbrace{\overline{\underline{x}}\_{1,2n-1} \cdots \overline{\underline{x}}\_{1,1} \overline{\underline{x}}\_{1,0}}\_{2n} \tag{62}$$

$$\mathfrak{w}\_2 = \underbrace{\mathfrak{x}\_{2,0}\mathfrak{x}\_{2,n-1}\cdots\mathfrak{x}\_{2,1}}\_{n}\underbrace{\mathfrak{x}\_{2,0}\mathfrak{x}\_{2,n-1}\cdots\mathfrak{x}\_{2,1}}\_{n}\tag{63}$$

$$
\varpi\_3 = \chi\_{3,0} \underbrace{\overline{\chi}\_{3,n-1} \cdots \overline{\chi}\_{3,1} \overline{\chi}\_{3,0}}\_{n} \underbrace{\chi\_{3,n-1} \cdots \chi\_{3,2} \chi\_{3,1}}\_{n-1} \tag{64}
$$

$$
\sigma\_4 = \overline{\mathfrak{X}}\_{3,n} \underbrace{0 \cdots 0}\_{n-1} \chi\_{3,n} \underbrace{1 \cdots 1}\_{n-1} \, . \tag{65}
$$

Next, two-channel MRC (eqs. (6)-(8)) is used to derive the final result by considering the composite set {22*n*(22*n*–1), 22*n*+1–1} and corresponding numbers (*Z*, *x*4). The final conversion equation is as follows

$$\mathbf{X} = \mathbf{Z} + \mathbf{2}^{2n} (\mathbf{2}^{2n} - \mathbf{1}) \Big| - \mathbf{2}^{2n+3} (\mathbf{x}\_4 - \mathbf{Z}) \Big|\_{\mathbf{2}^{2n+1} - \mathbf{1}} = \mathbf{x}\_1 + \mathbf{2}^{2n} (\mathbf{Y} + \mathbf{2}^{2n} \mathbf{T} - \mathbf{T}) \tag{66}$$

Where

346 Applications of Digital Signal Processing

<sup>1</sup>*x* <sup>2</sup> *x* <sup>3</sup> *x* <sup>4</sup> *x*

Operand Preparation Unit 1

(2*n*+1)-bit CPA with EAC *n*-bit CPA with EAC

Operand Preparation Unit 2

2*n*-bit CSA with EAC

*H*

2*n*-bit CSA with EAC

2*n*-bit CPA with EAC

*T*

<sup>1</sup>*x* <sup>3</sup> *x*

*K*

*H*

1

Fig. 3. The converter for moduli set {2*n*–1, 2*n*, 2*n*+1, 2*2n*+1–1} (Molahosseini et al., 2010)

1 1,2 1 1,1 1,0 2 *n*

2 2,0 2, 1 2,1 2,0 2, 1 2,1 *n n n n v xx x xx x* 

3 3,0 3, 1 3,1 3,0 3, 1 3,2 3,1

*n n*

1 1 *n n* 0 00 1 11 *n n*

 

*n n*

 

Next, two-channel MRC (eqs. (6)-(8)) is used to derive the final result by considering the composite set {22*n*(22*n*–1), 22*n*+1–1} and corresponding numbers (*Z*, *x*4). The final conversion

*v x x xx x xx*

 

4 3, 3,

*vx x*

equation is as follows

*n v x xx* 

 

(4*n*+1)-bit CPA

 

*X*

1*x*

Operand Preparation Unit 3

1

 

(62)

(63)

(64)

. (65)

$$T = \left| \upsilon\_5 + \upsilon\_6 + \upsilon\_7 \right|\_{2^{2n+1}-1} \tag{67}$$

$$
\omega\_5 = \underbrace{\mathbb{1}\_{1,2n-2} \cdots \mathbb{1}\_{1,1} \mathbb{1}\_{1,0}}\_{2n-1} 0 \alpha\_{1,2n-1} \tag{68}
$$

$$
\upsilon\_6 = \underbrace{Y\_{2n-1} \cdots Y\_1 Y\_0}\_{2n} \mathbf{0} \tag{69}
$$

$$\upsilon\_7 = \underbrace{\overline{\chi}\_{4,2n-2} \cdots \overline{\chi}\_{4,1} \overline{\chi}\_{4,0}}\_{2n-1} \overline{\chi}\_{4,2n} \overline{\chi}\_{4,2n-1} \tag{70}$$

The hardware implementation of this converter relies on two modulo adders for realization of (61) and (67). In other words, (61) needed two 2*n*-bit CSAs with EAC and a 2*n*-bit CPA with EAC, and a (2*n*+1)-bit CPA with EAC is used to realize (67). Besides, (66) only requires one (4*n*+1)-bit regular binary adder; the required multiplications all can be done using shift and concatenation. The converter has been depicted in Fig. 4.
