**Introduction to Memristive HTM Circuits**

**Introduction to Memristive HTM Circuits**

Alex James, Timur Ibrayev, Olga Krestinskaya and Irina Dolzhikova and Irina Dolzhikova Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Alex James, Timur Ibrayev, Olga Krestinskaya

http://dx.doi.org/10.5772/intechopen.70123

#### **Abstract**

Hierarchical temporal memory (HTM) is a cognitive learning algorithm intended to mimic the working principles of neocortex, part of the human brain said to be responsible for data classification, learning, and making predictions. Based on the combination of various concepts of neuroscience, it has already been shown that the software realization of HTM is effective on different recognition, detection, and prediction making tasks. However, its distinctive features, expressed in terms of hierarchy, modularity, and sparsity, suggest that hardware realization of HTM can be attractive in terms of providing faster processing speed as well as small memory requirements, on-chip area, and total power consumption. Despite there are few works done on hardware realization for HTM, there are promising results which illustrate effectiveness of incorporating an emerging memristor device technology to solve this open-research problem. Hence, this chapter reviews hardware designs for HTM with specific focus on memristive HTM circuits.

DOI: 10.5772/intechopen.70123

**Keywords:** hierarchical temporal memory, spatial pooler, temporal memory, memristor, non-volatile memory, memristive crossbars

## **1. Introduction**

The ideas that created a basis for development of hierarchical temporal memory (HTM), a type of machine learning algorithm that emerged from the consideration of the Bayesian neural network (BNN) and spatial-temporal algorithm, was first introduced by Jeff Hawkins in 2004 in his book *On Intelligence* [1] written in collaboration with Sandra Blakeslee. One year later, in 2005, Hawkins launched Numenta company that worked on the implementation of HTM technology. The first version of the HTM algorithm implementation was developed in

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

2006 and is now known as HTM-Zeta1 [2]. Three more years of work on the improvement of the HTM-Zeta1 produced a new version of HTM algorithm that is based on the cortical learning algorithm (CLA) and is now presented in the updated white paper of Numenta [3].

The aim of this chapter is to familiarize the reader with one of the latest versions of the machine learning algorithms in the face of hierarchical temporal memory (HTM). The focus of the chapter is utilization of the nanoscale memristive devices for hardware implementations of the HTM. However, due to the complex background of the novel learning algorithm the authors purposefully start from the general descriptions and useful explanations of the major concepts. A variety of concrete examples of HTM realizations in both software and hardware is presented in this chapter. This is done to give the reader comprehensive understanding of the current situation in the HTM research area.

The chapter is organized as follows. We discuss the structure and main concepts of the HTM algorithm in Section 2. The description of the concepts closely follows the white paper documents of Numenta company. In addition to that, a high level overview of the mathematical formulation of HTM phases is given based on the framework that has been demonstrated by Mnatzaganian et al. [4]. Section 3 summarizes the existing implementations of the HTM in both software and hardware. This is followed by the short Section 5 that is dedicated to the memristive device, which is currently widely used for different application. Most importantly, memristor demonstrated a great potential to be especially useful for neuromorphic applications. One of such application is realization of the synaptic behavior in the circuits. This is what Section 5 is about. Finally, Section 6 summarizes the works that demonstrated the application of memristive devices for implementation of hardware designs of HTM.

**Figure 2** demonstrates how the concept of hierarchy could be used in the image recognition application. Here the single level is represented by the single region that composed of several nodes, where the number of nodes is reduced as we go from the bottom level to the top level. Reduced number of the nodes in the higher levels could be explained by the fact that as we go up, we combine certain elements to form the features. As an example let consider an input image that illustrates the face of the human. By looking at the image and using the top-down approach, we realize that the given image represents the human face that in turn has several apparent features, such as nose, eyes, and lips. We then can go deeper and consider the visible features of the eye that incorporate the iris and pupil. Finally, we might zoom in the image and realize that features of the images are formed by certain pixels. Thus, it could be seen that at different HTM levels we have access to different levels of details of the input information. Two mechanisms that allow the HTM to operate by searching for the common patterns in the spatial domain and determining the common temporal patterns are represented by the spatial pooler (SP) and temporal memory (TM), respectively [3]. Here the term spatial pattern means that there is the combination of the input bits, which is represented by the activation of certain cells in the column, often appearing together. Temporal patterns in turn consider how

**Figure 1.** Detailed demonstration of the HTM structure consisting of 3 levels, each composed of certain number of

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 211

For the realization of HTM, first of all, the SP is required to convert the binary form of the input data into sparse distributed representation (SDR). This type of representation is formed by activating only very small number of bits to illustrate a particular input. SDR in contrast to the dense representation reduces the requirements for the storage capacity because the input data is presented by highly distributed cells. In addition to that, the sparsity of the active bits

the sequence of the spatial patterns changes over time [3].

regions with 16 columns each having 4 cells.

leads to the improved robustness of the system to the noise.

## **2. Structure and basic concepts of HTM**

For the timely varying set of data to be analyzed the regular horizontal organization that is being utilized in the most of the conventional computer memories will not work. There should be a hierarchy notion that needs to be implemented. This is what the major idea of HTM is based on. As the name suggests the HTM memory utilizes the hierarchical structure with the cells being the primary elements [3]. **Figure 1** depicts an example of hierarchical structure of HTM consisting of three levels. The primary element of the HTM is a cell. These cells perform the function of artificial neurons that resembles the functionalities of the biological neuron. Several cells are grouped to form a node, which is also known as column. The set of columns are combined to form a region, and several regions are interconnected in a hierarchical manner, where the higher level in the hierarchy utilizes the patterns that were learned from the lower levels. The connectivity of the neurons in biology is established by synapses. Being inspired from this concept, HTM cells are interconnected using synapses. In the framework of HTM, the strength of the synapse is known as permanence [3]. The permanence value determines which of the synapses are strong enough to establish the connection for further communication that enables the learning from other cells and lower levels.

2006 and is now known as HTM-Zeta1 [2]. Three more years of work on the improvement of the HTM-Zeta1 produced a new version of HTM algorithm that is based on the cortical learning algorithm (CLA) and is now presented in the updated white paper of Numenta [3]. The aim of this chapter is to familiarize the reader with one of the latest versions of the machine learning algorithms in the face of hierarchical temporal memory (HTM). The focus of the chapter is utilization of the nanoscale memristive devices for hardware implementations of the HTM. However, due to the complex background of the novel learning algorithm the authors purposefully start from the general descriptions and useful explanations of the major concepts. A variety of concrete examples of HTM realizations in both software and hardware is presented in this chapter. This is done to give the reader comprehensive understanding of

The chapter is organized as follows. We discuss the structure and main concepts of the HTM algorithm in Section 2. The description of the concepts closely follows the white paper documents of Numenta company. In addition to that, a high level overview of the mathematical formulation of HTM phases is given based on the framework that has been demonstrated by Mnatzaganian et al. [4]. Section 3 summarizes the existing implementations of the HTM in both software and hardware. This is followed by the short Section 5 that is dedicated to the memristive device, which is currently widely used for different application. Most importantly, memristor demonstrated a great potential to be especially useful for neuromorphic applications. One of such application is realization of the synaptic behavior in the circuits. This is what Section 5 is about. Finally, Section 6 summarizes the works that demonstrated the

application of memristive devices for implementation of hardware designs of HTM.

communication that enables the learning from other cells and lower levels.

For the timely varying set of data to be analyzed the regular horizontal organization that is being utilized in the most of the conventional computer memories will not work. There should be a hierarchy notion that needs to be implemented. This is what the major idea of HTM is based on. As the name suggests the HTM memory utilizes the hierarchical structure with the cells being the primary elements [3]. **Figure 1** depicts an example of hierarchical structure of HTM consisting of three levels. The primary element of the HTM is a cell. These cells perform the function of artificial neurons that resembles the functionalities of the biological neuron. Several cells are grouped to form a node, which is also known as column. The set of columns are combined to form a region, and several regions are interconnected in a hierarchical manner, where the higher level in the hierarchy utilizes the patterns that were learned from the lower levels. The connectivity of the neurons in biology is established by synapses. Being inspired from this concept, HTM cells are interconnected using synapses. In the framework of HTM, the strength of the synapse is known as permanence [3]. The permanence value determines which of the synapses are strong enough to establish the connection for further

the current situation in the HTM research area.

210 Memristor and Memristive Neural Networks

**2. Structure and basic concepts of HTM**

**Figure 1.** Detailed demonstration of the HTM structure consisting of 3 levels, each composed of certain number of regions with 16 columns each having 4 cells.

**Figure 2** demonstrates how the concept of hierarchy could be used in the image recognition application. Here the single level is represented by the single region that composed of several nodes, where the number of nodes is reduced as we go from the bottom level to the top level. Reduced number of the nodes in the higher levels could be explained by the fact that as we go up, we combine certain elements to form the features. As an example let consider an input image that illustrates the face of the human. By looking at the image and using the top-down approach, we realize that the given image represents the human face that in turn has several apparent features, such as nose, eyes, and lips. We then can go deeper and consider the visible features of the eye that incorporate the iris and pupil. Finally, we might zoom in the image and realize that features of the images are formed by certain pixels. Thus, it could be seen that at different HTM levels we have access to different levels of details of the input information.

Two mechanisms that allow the HTM to operate by searching for the common patterns in the spatial domain and determining the common temporal patterns are represented by the spatial pooler (SP) and temporal memory (TM), respectively [3]. Here the term spatial pattern means that there is the combination of the input bits, which is represented by the activation of certain cells in the column, often appearing together. Temporal patterns in turn consider how the sequence of the spatial patterns changes over time [3].

For the realization of HTM, first of all, the SP is required to convert the binary form of the input data into sparse distributed representation (SDR). This type of representation is formed by activating only very small number of bits to illustrate a particular input. SDR in contrast to the dense representation reduces the requirements for the storage capacity because the input data is presented by highly distributed cells. In addition to that, the sparsity of the active bits leads to the improved robustness of the system to the noise.

**Figure 2.** Illustration of the HTM hierarchy based on the image recognition example.

Before talking about the advantage of SDR based systems in terms of storage capacity itself, let first clearly understand the difference between the dense representations and SDRs, the two methods that are utilized for information storage and processing by the traditional computers and brain, respectively.

An example of storing the information in the traditional computer is as follows. The computer uses 8, 32 or 64, bit word with all different combinations of 1's and 0's. By taking any individual bit from the word, one will not get any useful information. The combination of bits itself and position of the active and inactive bits (1's and 0's) with respect to each other, this is what plays an important role. As an example 11010101 is the dense representation of the letter "j" in the ASCII code. The problem might occur even if only single bit of the word is corrupted, such as the third bit from the left swept to the 1 and as a result the dense representation 1101**1**10 will demonstrate a totally different letter in ASCII code, which is "n."

A purely mathematical formalization of HTM SP was presented by Mnatzaganian et al. [4]. This mathematical framework was established to optimize the development of the HTM designs on hardware. Bellow we discuss the three phases of SP based on pseudocode that was

**Figure 3.** Example of (a) how SDR can be used to represent a bit stream and (b) how SDR is formed within HTM

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 213

Before the first phase of SP occurs, the initialization should be performed. During the initialization, the initial synapses are established for each column and their permanence value, which is analogous to the synapse weight concept in the neuroscience, is randomly chosen. The first phase of overlap is responsible for determination of the number of active connected synapses. The activity of the synapse is determined by the input to which it is connected, i.e. the high input would make a synapse active, while low input would result in inactive synapse. The connectivity of the synapse in turn is based on the weight of the synapse: only the weights higher than the threshold would make the synapse connected. The optimum threshold depends on the distribution of the data and application of HTM. The optimized threshold can be selected empirically. The example of the empirical selection of the threshold value for pattern recognition application, where the threshold depends on the intensity of the data features, is shown in Ref. [15]. The threshold is selected by testing the HTM method with various threshold values for different databases. The overlap of the individual synapse *α* is represented by Eq. (1). The value of *α* would be 1 only if two conditions are satisfied, namely

is 1 and weight of the weight of the synapse is higher than the threshold.

presented in the white paper of Numenta and the work of the Mnatzaganian.

hierarchy to represent different geometrical figures.

input bit *ui*

Contrary to this, the functionality of the brain is based on the SDR. This means that for the input consisting of the thousands of bits, at every instant only small portion of these bits is active (represented by 1), while others being 0. In contrast to dense representation, in SDR every bit has its meaning that defines some attribute that describes the information (for example in case of the letter the attribute could define upper-case or lower-case letter, whether it is vowel or consonant). **Figure 3a** demonstrates SDR of the 1000 bits with very small number of bits being 1. These representation can be stored by considering the positions of the 1's in the stream of bits, i.e. the indexes of active bits. Thus, the SDR on **Figure 3a** will be stored as [1, 11, 998] which requires very little space. The comprehensive description of the SDR in the HTM could be found in the technical report of Hawkins and George [2].

This idea of SDR is used in the HTM algorithm. **Figure 3b** shows an example how the input information representing the set of geometrical figures could be stored in the HTM hierarchy in the distributed way with very few of the cells in the region being activated. The realization of the SP requires consideration of the following three phases: overlap phase, inhibition phase and learning phase.

Before talking about the advantage of SDR based systems in terms of storage capacity itself, let first clearly understand the difference between the dense representations and SDRs, the two methods that are utilized for information storage and processing by the traditional com-

An example of storing the information in the traditional computer is as follows. The computer uses 8, 32 or 64, bit word with all different combinations of 1's and 0's. By taking any individual bit from the word, one will not get any useful information. The combination of bits itself and position of the active and inactive bits (1's and 0's) with respect to each other, this is what plays an important role. As an example 11010101 is the dense representation of the letter "j" in the ASCII code. The problem might occur even if only single bit of the word is corrupted, such as the third bit from the left swept to the 1 and as a result the dense representation 1101**1**10

Contrary to this, the functionality of the brain is based on the SDR. This means that for the input consisting of the thousands of bits, at every instant only small portion of these bits is active (represented by 1), while others being 0. In contrast to dense representation, in SDR every bit has its meaning that defines some attribute that describes the information (for example in case of the letter the attribute could define upper-case or lower-case letter, whether it is vowel or consonant). **Figure 3a** demonstrates SDR of the 1000 bits with very small number of bits being 1. These representation can be stored by considering the positions of the 1's in the stream of bits, i.e. the indexes of active bits. Thus, the SDR on **Figure 3a** will be stored as [1, 11, 998] which requires very little space. The comprehensive description of the SDR in the HTM

This idea of SDR is used in the HTM algorithm. **Figure 3b** shows an example how the input information representing the set of geometrical figures could be stored in the HTM hierarchy in the distributed way with very few of the cells in the region being activated. The realization of the SP requires consideration of the following three phases: overlap phase, inhibition phase

will demonstrate a totally different letter in ASCII code, which is "n."

**Figure 2.** Illustration of the HTM hierarchy based on the image recognition example.

could be found in the technical report of Hawkins and George [2].

puters and brain, respectively.

212 Memristor and Memristive Neural Networks

and learning phase.

**Figure 3.** Example of (a) how SDR can be used to represent a bit stream and (b) how SDR is formed within HTM hierarchy to represent different geometrical figures.

A purely mathematical formalization of HTM SP was presented by Mnatzaganian et al. [4]. This mathematical framework was established to optimize the development of the HTM designs on hardware. Bellow we discuss the three phases of SP based on pseudocode that was presented in the white paper of Numenta and the work of the Mnatzaganian.

Before the first phase of SP occurs, the initialization should be performed. During the initialization, the initial synapses are established for each column and their permanence value, which is analogous to the synapse weight concept in the neuroscience, is randomly chosen. The first phase of overlap is responsible for determination of the number of active connected synapses. The activity of the synapse is determined by the input to which it is connected, i.e. the high input would make a synapse active, while low input would result in inactive synapse. The connectivity of the synapse in turn is based on the weight of the synapse: only the weights higher than the threshold would make the synapse connected. The optimum threshold depends on the distribution of the data and application of HTM. The optimized threshold can be selected empirically. The example of the empirical selection of the threshold value for pattern recognition application, where the threshold depends on the intensity of the data features, is shown in Ref. [15]. The threshold is selected by testing the HTM method with various threshold values for different databases. The overlap of the individual synapse *α* is represented by Eq. (1). The value of *α* would be 1 only if two conditions are satisfied, namely input bit *ui* is 1 and weight of the weight of the synapse is higher than the threshold.

$$\begin{aligned} \text{Wenn:} & \text{wenn:} & \text{Wenn:} & \text{Wenn:} & \text{Wenn:} & \text{Wenn:} & \\\\ & \alpha\_i &= \begin{cases} 1 & \text{if } u\_i \times w\_i \ge \text{threshol} \\ 0 & \text{otherwise} \end{cases} \end{aligned} \tag{1}$$

The total overlap of the column that consists of *N* synapses is given by Eq. (2).

$$\text{Overlap} = \sum\_{1}^{N} a\_{i} \tag{2}$$

Despite it was originally developed as the software algorithm, promising results reported in the works listed above resulted in the rise of interest in a hardware realization of HTM. Limited number of works proposes various designs for the hardware realization of HTM within digital, analog, and mixed-signal domains. The work in Ref. [11] proposed conceptual application-specific integrated circuit (ASIC) design for HTM. The work in Ref. [12] proposed reconfigurable field-programmable gate array (FPGA) implementation. The work in Ref. [13] proposed non-volatile HTM spatial pooler design using flash memories. The work in Ref. [14] proposed mixed-signal design for HTM based on the combination of spin-neuron devices and memristor crossbars. The work in Ref. [15] proposed analog design for HTM utilizing

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 215

The works in Refs. [13–15] are based on the implementation of HTM using non-volatile memories. This is driven by the fact that, in order to compute large amount of data, HTM should have dense neuronal structures with considerations on area and power efficiency. Based on these parameters, the work in Ref. [16] provides data illustrating superior potential of memristor devices over flash memories conventionally used to implement brain-inspired architectures.

Memristor (memory resistor) is a non-linear device firstly proposed by Leon Chua in 1972 and firstly fabricated only in 2003 by HP Labs [17]. The main distinctive feature of the device is its ability to change its state not only according to the current input value, but also according to the history of the inputs. Moreover, additional advantages of memristors include low on-chip area, resulting from fabrication methods differing from methods used for silicon devices, and low power consumption, resulting from absence of leakage currents associated with high power dissipation in CMOS technology [17]. These properties of the device resulted in its applications in brain-inspired architectures. Single memristor may be used to represent synaptic connection (or, simply synapse) with its memristance value representing strength of the connection between pre- and post-synaptic neurons. Possibility to combine synaptic processing as well as memory storage within single device made memristors invaluable in the design of synapses, critical building blocks in architectures based on neuroscientific concepts. Nanoscale devices allow compact storage of many synapses as well as enable parallel process-

**5. Single synapse circuit realizations using memristor devices**

Single synapse is said to be a connection between two communicating neurons. In biology, in simple terms communication occurs when transmitting neuron, i.e. pre-synaptic neuron, sends information via signals to receive neuron, i.e. post-synaptic neuron, through synaptic connection. Because there are a huge number of neuronal interconnections, the receiving signal importance is said to be dependent on the strength (also called as the weight) of synaptic connection. It means that neuronal cell, receiving various signals from the number of presynaptic neurons, selects and processes important signal according to the weight of synapse.

memristor crossbar circuits.

**4. Memristor for HTM**

ing within architecture.

Based on the calculated overlap values the second stage determines the columns that will still be winners after the inhibition. The number of desired winning columns could be controlled with help of parameter *k* such that the winner is considered that column whose overlap value is greater than the *k*-th highest overlap value within the inhibition region that is represented in Eq. (3) by *γ*.

$$
\gamma = \text{kmax}(a, k)\tag{3}
$$

In the phase of learning the weight values that were higher than *γ* value are increased by the specified amount, while the other weight decreases its value [3]. Such an update of the weights allows the consideration of the previous state when treating a new input.

TM deals with the time variable of the learning process and could be used to predict what patterns will be followed the given pattern based on the previous observations. Ideally, the learning process occurs in both SP and TM. However, in the SP the learning is based on the connections between the input bits and columns, while in TM learning considers the establishment of the synapses (connections) between the cells of the same region. The TM learns the sequences by considering an active cell and the connection that it formed to the cells that were active in the previous time instant.

The input to the TM are the winning columns from the SP. Like SP, TM consists of three phases. In the first phase, the state of each cell of the columns is checked and the certain cells of the columns are activated. The second phase is responsible for the setting the cells of the columns in predictive state, while the last phase updates the permanence of the synapses [3].

## **3. Software and hardware realizations of HTM**

Despite HTM is classified as a type of cognitive learning algorithm, its fundamental concepts related to neuroscience and, particularly, to the working principles of neocortex make it like deep neural networks, which, in turn, have already shown significant results on a variety of real world problems. Combined with the distinctive features of the algorithm, expressed by its sparsity, hierarchy, and modularity, HTM algorithm attracted interest of various research groups. There is now several research works, which illustrate effectiveness of the algorithm on various recognition tasks. For example, work in Ref. [5] verifies HTM capability on abnormality detection, Refs. [6, 7] present results for pattern and object recognitions, in Ref. [8] HTM was used for object categorizations. Similarly, works in Refs. [9, 10] illustrate suitability of the algorithm for robotics and movement detection, respectively. However, these works were focused on the software realizations of HTM.

Despite it was originally developed as the software algorithm, promising results reported in the works listed above resulted in the rise of interest in a hardware realization of HTM. Limited number of works proposes various designs for the hardware realization of HTM within digital, analog, and mixed-signal domains. The work in Ref. [11] proposed conceptual application-specific integrated circuit (ASIC) design for HTM. The work in Ref. [12] proposed reconfigurable field-programmable gate array (FPGA) implementation. The work in Ref. [13] proposed non-volatile HTM spatial pooler design using flash memories. The work in Ref. [14] proposed mixed-signal design for HTM based on the combination of spin-neuron devices and memristor crossbars. The work in Ref. [15] proposed analog design for HTM utilizing memristor crossbar circuits.

The works in Refs. [13–15] are based on the implementation of HTM using non-volatile memories. This is driven by the fact that, in order to compute large amount of data, HTM should have dense neuronal structures with considerations on area and power efficiency. Based on these parameters, the work in Ref. [16] provides data illustrating superior potential of memristor devices over flash memories conventionally used to implement brain-inspired architectures.

## **4. Memristor for HTM**

*<sup>α</sup><sup>i</sup>* <sup>=</sup> {

214 Memristor and Memristive Neural Networks

were active in the previous time instant.

**3. Software and hardware realizations of HTM**

were focused on the software realizations of HTM.

in Eq. (3) by *γ*.

Overlap = ∑<sup>1</sup>

The total overlap of the column that consists of *N* synapses is given by Eq. (2).

Based on the calculated overlap values the second stage determines the columns that will still be winners after the inhibition. The number of desired winning columns could be controlled with help of parameter *k* such that the winner is considered that column whose overlap value is greater than the *k*-th highest overlap value within the inhibition region that is represented

*γ* = kmax(*α*, *k*) (3)

In the phase of learning the weight values that were higher than *γ* value are increased by the specified amount, while the other weight decreases its value [3]. Such an update of the

TM deals with the time variable of the learning process and could be used to predict what patterns will be followed the given pattern based on the previous observations. Ideally, the learning process occurs in both SP and TM. However, in the SP the learning is based on the connections between the input bits and columns, while in TM learning considers the establishment of the synapses (connections) between the cells of the same region. The TM learns the sequences by considering an active cell and the connection that it formed to the cells that

The input to the TM are the winning columns from the SP. Like SP, TM consists of three phases. In the first phase, the state of each cell of the columns is checked and the certain cells of the columns are activated. The second phase is responsible for the setting the cells of the columns in predictive state, while the last phase updates the permanence of the synapses [3].

Despite HTM is classified as a type of cognitive learning algorithm, its fundamental concepts related to neuroscience and, particularly, to the working principles of neocortex make it like deep neural networks, which, in turn, have already shown significant results on a variety of real world problems. Combined with the distinctive features of the algorithm, expressed by its sparsity, hierarchy, and modularity, HTM algorithm attracted interest of various research groups. There is now several research works, which illustrate effectiveness of the algorithm on various recognition tasks. For example, work in Ref. [5] verifies HTM capability on abnormality detection, Refs. [6, 7] present results for pattern and object recognitions, in Ref. [8] HTM was used for object categorizations. Similarly, works in Refs. [9, 10] illustrate suitability of the algorithm for robotics and movement detection, respectively. However, these works

weights allows the consideration of the previous state when treating a new input.

<sup>1</sup> if *ui* <sup>×</sup> *wi* <sup>≥</sup> threshold 0 otherwise (1)

*<sup>N</sup> α<sup>i</sup>* (2)

Memristor (memory resistor) is a non-linear device firstly proposed by Leon Chua in 1972 and firstly fabricated only in 2003 by HP Labs [17]. The main distinctive feature of the device is its ability to change its state not only according to the current input value, but also according to the history of the inputs. Moreover, additional advantages of memristors include low on-chip area, resulting from fabrication methods differing from methods used for silicon devices, and low power consumption, resulting from absence of leakage currents associated with high power dissipation in CMOS technology [17]. These properties of the device resulted in its applications in brain-inspired architectures. Single memristor may be used to represent synaptic connection (or, simply synapse) with its memristance value representing strength of the connection between pre- and post-synaptic neurons. Possibility to combine synaptic processing as well as memory storage within single device made memristors invaluable in the design of synapses, critical building blocks in architectures based on neuroscientific concepts. Nanoscale devices allow compact storage of many synapses as well as enable parallel processing within architecture.

## **5. Single synapse circuit realizations using memristor devices**

Single synapse is said to be a connection between two communicating neurons. In biology, in simple terms communication occurs when transmitting neuron, i.e. pre-synaptic neuron, sends information via signals to receive neuron, i.e. post-synaptic neuron, through synaptic connection. Because there are a huge number of neuronal interconnections, the receiving signal importance is said to be dependent on the strength (also called as the weight) of synaptic connection. It means that neuronal cell, receiving various signals from the number of presynaptic neurons, selects and processes important signal according to the weight of synapse. It is usually assumed that learning appears when the weight of the synapse increases or decreases, according to the importance of the information received through that particular synaptic connection. Hence, it is also crucial to consider effect of time-variance of the incoming data stream on the strength of synapse.

either not active (input bit value is low) or not connected (weight value is low), then the buffer will output low value. Finally, NMOS transistor is required to convert voltage signal into current signal to sum up all overlap values of individual synapses within single HTM column.

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 217

As HTM is a nascent area in brain inspired machine learning algorithms and architectures, a very small number of the HTM circuit configurations have been proposed. There are two major architectures proposed for the HTM hardware implementation with memristive circuits. These are memristor crossbar array-based HTM implementation integrated with CMOS circuits [15] and the HTM implementation using memristive arrays and spin-neuron devices

The memristor-CMOS circuit implementation of HTM has been proposed in Ref. [15]. In this work, the hardware implementation of the HTM SP, applied for face and speech recognition tasks, is presented. The main role of the HTM SP in the proposed system is to extract the most relevant spatial features from the images and remove irrelevant ones for further application for face and speech recognition using template matching method. The feature extraction relies on SDR of the features. The selection of the most relevant features from the sparse data depends on the threshold value shown in Eq. (1). The sparse features greater than

[14]. Both hardware configurations were tested for pattern recognition application.

**6. HTM circuit realizations using memristor devices**

**Figure 5.** HTM image processing method proposed in Ref. [15].

Based on the neuroscientific concepts, synapse, hence, is required not only to be able to process input value but also to store the weight value, determining its importance. Because the latter attribute is dependent on the time variance of the input data, memristor is attractive device, which can combine neuronal functions, such as memorization and data processing, within single unit. Depending on the input signal type, i.e. either current or voltage mode design, there are various possibilities of establishing synapse circuits using memristor devices and CMOS transistors. In particular, work in Ref. [16] presents basic synapse circuits.

The work in Ref. [18] proposed single synapse circuit with specific intentions to precisely model synapse as it is explained and used within HTM framework. **Figure 4** illustrates the circuit design of the single synapse, which can be divided into four parts: input current mirror, memristor, buffer, and voltage-to-current converting NMOS. First part is responsible for establishment of the pre-synaptic signal. The second part is responsible for storing the weight of the synapse, expressed by the memristance value of the memristor. These two parts are responsible for implementation of overlap phase of HTM, such that the voltage across memristor represents the product of the input signal (expressed by current value) and the weight of the synapse (expressed by the memristance value). The third part of the circuit is buffer and is responsible for activation function establishment. It means that buffer outputs voltage value of 1 V if the overlap value is higher than the threshold and outputs 0 V if it is not. Hence, if the input to that synapse is active connected, then the buffer will output high value, and if it is

**Figure 4.** Single synapse circuit design proposed in Ref. [18] designed specifically for HTM architecture.

either not active (input bit value is low) or not connected (weight value is low), then the buffer will output low value. Finally, NMOS transistor is required to convert voltage signal into current signal to sum up all overlap values of individual synapses within single HTM column.

## **6. HTM circuit realizations using memristor devices**

It is usually assumed that learning appears when the weight of the synapse increases or decreases, according to the importance of the information received through that particular synaptic connection. Hence, it is also crucial to consider effect of time-variance of the incom-

Based on the neuroscientific concepts, synapse, hence, is required not only to be able to process input value but also to store the weight value, determining its importance. Because the latter attribute is dependent on the time variance of the input data, memristor is attractive device, which can combine neuronal functions, such as memorization and data processing, within single unit. Depending on the input signal type, i.e. either current or voltage mode design, there are various possibilities of establishing synapse circuits using memristor devices

The work in Ref. [18] proposed single synapse circuit with specific intentions to precisely model synapse as it is explained and used within HTM framework. **Figure 4** illustrates the circuit design of the single synapse, which can be divided into four parts: input current mirror, memristor, buffer, and voltage-to-current converting NMOS. First part is responsible for establishment of the pre-synaptic signal. The second part is responsible for storing the weight of the synapse, expressed by the memristance value of the memristor. These two parts are responsible for implementation of overlap phase of HTM, such that the voltage across memristor represents the product of the input signal (expressed by current value) and the weight of the synapse (expressed by the memristance value). The third part of the circuit is buffer and is responsible for activation function establishment. It means that buffer outputs voltage value of 1 V if the overlap value is higher than the threshold and outputs 0 V if it is not. Hence, if the input to that synapse is active connected, then the buffer will output high value, and if it is

and CMOS transistors. In particular, work in Ref. [16] presents basic synapse circuits.

**Figure 4.** Single synapse circuit design proposed in Ref. [18] designed specifically for HTM architecture.

ing data stream on the strength of synapse.

216 Memristor and Memristive Neural Networks

As HTM is a nascent area in brain inspired machine learning algorithms and architectures, a very small number of the HTM circuit configurations have been proposed. There are two major architectures proposed for the HTM hardware implementation with memristive circuits. These are memristor crossbar array-based HTM implementation integrated with CMOS circuits [15] and the HTM implementation using memristive arrays and spin-neuron devices [14]. Both hardware configurations were tested for pattern recognition application.

The memristor-CMOS circuit implementation of HTM has been proposed in Ref. [15]. In this work, the hardware implementation of the HTM SP, applied for face and speech recognition tasks, is presented. The main role of the HTM SP in the proposed system is to extract the most relevant spatial features from the images and remove irrelevant ones for further application for face and speech recognition using template matching method. The feature extraction relies on SDR of the features. The selection of the most relevant features from the sparse data depends on the threshold value shown in Eq. (1). The sparse features greater than

**Figure 5.** HTM image processing method proposed in Ref. [15].

the threshold are stored in the memory. The example of the input image is shown in **Figure 5**. The image is divided into blocks with a certain number of pixels, which are the inputs to the crossbar slice circuits.

in the initial stage and later are updated only during the learning phase. When the synaptic connection is determined, the connection value (output from the read/write circuit) is fetched to the AND gate through the buffer, which performs thresholding operation, shown in synapse overlap calculation stage in **Figure 6**. The buffer converts the signal from read/write stage to the binary connectivity value, which is either 0 or 1. The single synapse overlap calculation is made by the AND gate, where one input is the binary synapse connectivity value and the other is the input signal from the processed pattern. The column overlap calculation is made by the sum-

After the overlap phase, the inhibition phase is executed, where the overlaps of the parallel columns are compared using WTA circuit, illustrated in **Figure 7**. The overlap values obtained from the summing amplifier are fetched to the WTA circuit and the highest value is selected and set to 1 with the help of bias current source and the comparators. The other values from the inhibition region are set to 0. The output of the WTA circuit is index of the winning columns, which are used for classification process. The circuit implementation results show the

with 2 synapses. The area and power required to process an individual synapse overlap are

After the HTM SP processing, the features are compared with the stored training patterns, and the classification of the input pattern is executed using a memristive pattern matcher shown in **Figure 8**. Memristive pattern matcher is based on memristive the XOR gate, which, in turn, consists of the memristive NOR gate and the CMOS inverter. The output of the mem-

The other research work representing memristive circuits-based HTM implementation is presented in Ref. [14]. In this work, memristive crossbar arrays are combined with spin-neuron devices. The system is tested on object and handwritten text recognition. It is assumed that

ristive pattern matcher is either 1 for the detected match or 0 for the mismatch.

and 31.56 uW, respectively. For the column overlap calculation the area of 4.325 um<sup>2</sup>

to process 2 column block

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 219

ming amplifier that is used for the summation of all single synapses.

power consumption of 31.567 uW and on-chip area of 2.735 um<sup>2</sup>

and the power of 160 uW are required.

**Figure 7.** Winner take all circuit as illustrated in Ref. [15].

1.37 um<sup>2</sup>

The number of crossbar slices corresponds to the number of the image blocks. Each crossbar slice refers to a single column in the set of serial columns in HTM. The number of synapses in the column corresponds to the number of synapses or pixels in the image blocks. Several image blocks form a single inhibition block. The number of inhibition blocks equals to the number of parallel columns in the HTM. Each inhibition region consists of several serial columns. The set of pixels in the serial column correspond to a single crossbar slice. The sum of the pixels within each crossbar slice is calculated. The outputs from the crossbar slices are fetched to the winner take all (WTA) circuit to produce the final set of the sparse image features. The highest value of crossbar slice outputs is selected by the WTA. Then, the inhibition region is binarized. The inhibition region component corresponding to the highest value of the crossbar slices is represented as 1, and the other components are set to 0. This binarized inhibition regions represent the final set of the sparse image features.

The overall architecture of the HTM crossbar slice circuit consists of the memristor crossbar, read and write circuits, synapse overlap calculation circuit and column overlap calculation circuit, shown in **Figure 6**. The memristors in the memristive crossbar array are used to represent the synapse weight and strength of the synaptic connection. The memristors in read/write part of the circuit implement the expected ideal permanence and determine the final connection of the column, which is either active or inactive. The memristors in the crossbar array are preprogramed

**Figure 6.** HTM circuit implementation [15].

in the initial stage and later are updated only during the learning phase. When the synaptic connection is determined, the connection value (output from the read/write circuit) is fetched to the AND gate through the buffer, which performs thresholding operation, shown in synapse overlap calculation stage in **Figure 6**. The buffer converts the signal from read/write stage to the binary connectivity value, which is either 0 or 1. The single synapse overlap calculation is made by the AND gate, where one input is the binary synapse connectivity value and the other is the input signal from the processed pattern. The column overlap calculation is made by the summing amplifier that is used for the summation of all single synapses.

the threshold are stored in the memory. The example of the input image is shown in **Figure 5**. The image is divided into blocks with a certain number of pixels, which are the inputs to the

The number of crossbar slices corresponds to the number of the image blocks. Each crossbar slice refers to a single column in the set of serial columns in HTM. The number of synapses in the column corresponds to the number of synapses or pixels in the image blocks. Several image blocks form a single inhibition block. The number of inhibition blocks equals to the number of parallel columns in the HTM. Each inhibition region consists of several serial columns. The set of pixels in the serial column correspond to a single crossbar slice. The sum of the pixels within each crossbar slice is calculated. The outputs from the crossbar slices are fetched to the winner take all (WTA) circuit to produce the final set of the sparse image features. The highest value of crossbar slice outputs is selected by the WTA. Then, the inhibition region is binarized. The inhibition region component corresponding to the highest value of the crossbar slices is represented as 1, and the other components are set to 0. This binarized

The overall architecture of the HTM crossbar slice circuit consists of the memristor crossbar, read and write circuits, synapse overlap calculation circuit and column overlap calculation circuit, shown in **Figure 6**. The memristors in the memristive crossbar array are used to represent the synapse weight and strength of the synaptic connection. The memristors in read/write part of the circuit implement the expected ideal permanence and determine the final connection of the column, which is either active or inactive. The memristors in the crossbar array are preprogramed

inhibition regions represent the final set of the sparse image features.

crossbar slice circuits.

218 Memristor and Memristive Neural Networks

**Figure 6.** HTM circuit implementation [15].

After the overlap phase, the inhibition phase is executed, where the overlaps of the parallel columns are compared using WTA circuit, illustrated in **Figure 7**. The overlap values obtained from the summing amplifier are fetched to the WTA circuit and the highest value is selected and set to 1 with the help of bias current source and the comparators. The other values from the inhibition region are set to 0. The output of the WTA circuit is index of the winning columns, which are used for classification process. The circuit implementation results show the power consumption of 31.567 uW and on-chip area of 2.735 um<sup>2</sup> to process 2 column block with 2 synapses. The area and power required to process an individual synapse overlap are 1.37 um<sup>2</sup> and 31.56 uW, respectively. For the column overlap calculation the area of 4.325 um<sup>2</sup> and the power of 160 uW are required.

After the HTM SP processing, the features are compared with the stored training patterns, and the classification of the input pattern is executed using a memristive pattern matcher shown in **Figure 8**. Memristive pattern matcher is based on memristive the XOR gate, which, in turn, consists of the memristive NOR gate and the CMOS inverter. The output of the memristive pattern matcher is either 1 for the detected match or 0 for the mismatch.

The other research work representing memristive circuits-based HTM implementation is presented in Ref. [14]. In this work, memristive crossbar arrays are combined with spin-neuron devices. The system is tested on object and handwritten text recognition. It is assumed that

**Figure 7.** Winner take all circuit as illustrated in Ref. [15].

**Figure 8.** Memristive pattern matcher presented in Ref. [15].

the training of the system is executed by the software and the hardware part of HTM is used for inference (testing) stage, where pattern classification is performed.

The overall HTM hardware configuration is illustrated in **Figure 9**. Image processing is performed in a hierarchical manner. The processed image is divided into 16 patches of the same size, which are fetched into separate HTM nodes in Level 1. Therefore, there are 16 HTM nodes in Level 1. The number of inputs to each Level 1 HTM node equals to the number of pixels in the patch. Level 1 nodes produce 16 outputs, which are divided into 4 groups of 4 Level 1 outputs. Each group of these outputs is fetched into particular Level 2 HTM node. Level 2 contains 4 HTM nodes producing 4 separate outputs. Level 2 outputs are input to Level 3 HTM node, which calculates the final output value.

digital to analog converter (DTCS DAC) based on the switching circuit is used. Next, the ana-

The example of 3 × 3 RCN circuit is shown in **Figure 11**. The RCN has a configuration of the memristive array. Such configuration enables calculation of the DP required for the SP as well as for the TM. Therefore, the pixels of the input image matrix are processed in parallel. The

conductance value within the raw *gij*. Then, the correlation between the stored patterns and

Next, the output current of each RCN column is detected and converted to the digital value using SAR ADC, which is based on spin neuron devices (shown in **Figure 12**). The performance of the spin neuron device is akin to the current mode comparator functionality. The

in a horizontal upper row is multiplied by each preprogramed memristor

*<sup>j</sup>* = ∑*<sup>i</sup> Vi* \* *gij* (4)

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 221

log DTCS ADC outputs are fetched to RCN circuit.

**Figure 9.** HTM hardware configuration proposed in Ref. [14].

*I*

the input signals is calculated as an output current using Eq. (4).

input voltage *Vi*

The overall architecture of the implemented HTM node consists of resistive crossbar network (RCN), successive approximation register analog to digital converter (SAR ADC) and winner take all (WTA) circuit. RCN is used to calculate dot products (DP) in the HTM SP part and the HTM TM part. RCN enables a parallel processing of all image pixels from a single image patch. The digital input pattern from the image patch is fetched into the HTM SP, where it is converted to analog form for the RCN processing. The RCN circuit performs the DP calculation producing an analog output vector. This vector is detected and converted to the digital form with the spin-neuron-based SAR ADC, which forms the output vector of the HTM SP. This output vector is sent to the HTM TM circuit, where it is converted into the analog form again followed by the DP calculation and SAR ADC processing, which forms the output vector of the HTM TM. The HTM TM output vector is fetched to WTA circuit, which identifies the index of the winner from temporal group.

The circuit example of RCN with a single digital input and three spin-neurons is shown in **Figure 10**. To convert digital RCN inputs to the analog form, a deep triode current source

**Figure 9.** HTM hardware configuration proposed in Ref. [14].

the training of the system is executed by the software and the hardware part of HTM is used

The overall HTM hardware configuration is illustrated in **Figure 9**. Image processing is performed in a hierarchical manner. The processed image is divided into 16 patches of the same size, which are fetched into separate HTM nodes in Level 1. Therefore, there are 16 HTM nodes in Level 1. The number of inputs to each Level 1 HTM node equals to the number of pixels in the patch. Level 1 nodes produce 16 outputs, which are divided into 4 groups of 4 Level 1 outputs. Each group of these outputs is fetched into particular Level 2 HTM node. Level 2 contains 4 HTM nodes producing 4 separate outputs. Level 2 outputs are input to Level 3 HTM node,

The overall architecture of the implemented HTM node consists of resistive crossbar network (RCN), successive approximation register analog to digital converter (SAR ADC) and winner take all (WTA) circuit. RCN is used to calculate dot products (DP) in the HTM SP part and the HTM TM part. RCN enables a parallel processing of all image pixels from a single image patch. The digital input pattern from the image patch is fetched into the HTM SP, where it is converted to analog form for the RCN processing. The RCN circuit performs the DP calculation producing an analog output vector. This vector is detected and converted to the digital form with the spin-neuron-based SAR ADC, which forms the output vector of the HTM SP. This output vector is sent to the HTM TM circuit, where it is converted into the analog form again followed by the DP calculation and SAR ADC processing, which forms the output vector of the HTM TM. The HTM TM output vector is fetched to WTA circuit, which identifies

The circuit example of RCN with a single digital input and three spin-neurons is shown in **Figure 10**. To convert digital RCN inputs to the analog form, a deep triode current source

for inference (testing) stage, where pattern classification is performed.

which calculates the final output value.

**Figure 8.** Memristive pattern matcher presented in Ref. [15].

220 Memristor and Memristive Neural Networks

the index of the winner from temporal group.

digital to analog converter (DTCS DAC) based on the switching circuit is used. Next, the analog DTCS ADC outputs are fetched to RCN circuit.

The example of 3 × 3 RCN circuit is shown in **Figure 11**. The RCN has a configuration of the memristive array. Such configuration enables calculation of the DP required for the SP as well as for the TM. Therefore, the pixels of the input image matrix are processed in parallel. The input voltage *Vi* in a horizontal upper row is multiplied by each preprogramed memristor conductance value within the raw *gij*. Then, the correlation between the stored patterns and the input signals is calculated as an output current using Eq. (4).

$$I\_{\parallel} = \sum\_{l} V\_{\parallel} ^\* \mathcal{g}\_{\parallel} \tag{4}$$

Next, the output current of each RCN column is detected and converted to the digital value using SAR ADC, which is based on spin neuron devices (shown in **Figure 12**). The performance of the spin neuron device is akin to the current mode comparator functionality. The

**Figure 10.** RCN with a single digital input and three spin-neurons [14].

spin-neuron may be switched with the particular current flowing through it; therefore it is suitable for the SAR ADC design. In the spin neuron SAR ADC, the DTCS DAC converts the digital value stored in the approximation register to the form of the analog current. Then, this current is compared with the RCN output current produced by the spin-neuron. Finally, a special latch is used to detect output stage. Having a advantage of low power consumption and high resolution, the spin neuron-based SAR ADC enables the conversion of the analog currents from RCN to the digital HTM SP and HTM TM outputs denoted as the input densities over the spatial patterns (HTM SP outputs) and the input densities over the temporal groups (HTM TM outputs) [14]. Finally, the WTA circuit determines the winner of each HTM block. If the HTM block is at the highest hierarchy level (output node), the WTA identifies the class index of an input pattern. Otherwise, if it is located at the non-output node, the WTA determines the winning index of a particular temporal group.

**7. Summary**

ested reader with the references for further reading.

HTM is a type of cortical learning algorithm that aims to resemble the functionalities of the neocortex. The great potential of the HTM for applications related to classification and prediction making pushed for consideration of hardware realizations of the algorithm. The objective of this chapter was to overview the major concepts of HTM and discuss the most recent implementations of HTM in hardware. Currently, there are different hardware implementations of HTM, including the designs based on FPGA and ASIC, that could be found in the literature. However, the discussion in this chapter is focused around the memristor based realizations of HTM. Despite this, for comprehensiveness of the chapter, the authors summarize the general state of the HTM in terms of other hardware implementations [11–13] and provide an inter-

**HTM implementation presented in** 

neuron device (SAR-ADC), spin-CMOS hybrid processing elements based on domain wall neuron (DWN)

Application Hand-written digit recognition Face and speech recognition

**HTM implementation presented in** 

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 223

50 × 50 nm memristive devices, 180

nm CMOS technology

**Ref. [15]**

**Figure 12.** Successive approximation register analog to digital converter (SAR ADC) [14].

**Ref. [14]**

Hardware implementation Analog/digital Purely analog

Architecture Crossbar Neuron units

Algorithm SP+TM SP

Technology Memristors (RCN), 20 × 2 nm spin

**Table 1.** The comparison of the existing hardware implementations of HTM.

The properties of memristors connected with the small feature size and negligible leakage current of the devices make them very attractive for large-scale circuit designs that reduces the overall on-chip area and power consumption. In addition to that, ability of the memristor

**Table 1** shows the comparison of two main implementations of HTM discussed in this Chapter.

**Figure 11.** RCN array [14].

**Figure 12.** Successive approximation register analog to digital converter (SAR ADC) [14].


**Table 1.** The comparison of the existing hardware implementations of HTM.

## **7. Summary**

spin-neuron may be switched with the particular current flowing through it; therefore it is suitable for the SAR ADC design. In the spin neuron SAR ADC, the DTCS DAC converts the digital value stored in the approximation register to the form of the analog current. Then, this current is compared with the RCN output current produced by the spin-neuron. Finally, a special latch is used to detect output stage. Having a advantage of low power consumption and high resolution, the spin neuron-based SAR ADC enables the conversion of the analog currents from RCN to the digital HTM SP and HTM TM outputs denoted as the input densities over the spatial patterns (HTM SP outputs) and the input densities over the temporal groups (HTM TM outputs) [14]. Finally, the WTA circuit determines the winner of each HTM block. If the HTM block is at the highest hierarchy level (output node), the WTA identifies the class index of an input pattern. Otherwise, if it is located at the non-output node, the WTA

**Table 1** shows the comparison of two main implementations of HTM discussed in this

determines the winning index of a particular temporal group.

**Figure 10.** RCN with a single digital input and three spin-neurons [14].

Chapter.

**Figure 11.** RCN array [14].

222 Memristor and Memristive Neural Networks

HTM is a type of cortical learning algorithm that aims to resemble the functionalities of the neocortex. The great potential of the HTM for applications related to classification and prediction making pushed for consideration of hardware realizations of the algorithm. The objective of this chapter was to overview the major concepts of HTM and discuss the most recent implementations of HTM in hardware. Currently, there are different hardware implementations of HTM, including the designs based on FPGA and ASIC, that could be found in the literature. However, the discussion in this chapter is focused around the memristor based realizations of HTM. Despite this, for comprehensiveness of the chapter, the authors summarize the general state of the HTM in terms of other hardware implementations [11–13] and provide an interested reader with the references for further reading.

The properties of memristors connected with the small feature size and negligible leakage current of the devices make them very attractive for large-scale circuit designs that reduces the overall on-chip area and power consumption. In addition to that, ability of the memristor to remember its state and change it based on history of applied voltages makes it suitable for neuromorphic designs. Thus, the nanoscale memristive devices could be used to mimic the synaptic connection of the neuron.

[9] Seok K.H., Kim Y.S. A new robot motion authoring method using HTM. In: Control, Automation and Systems, 2008. ICCAS 2008. International Conference on; IEEE; 2008.

Introduction to Memristive HTM Circuits http://dx.doi.org/10.5772/intechopen.70123 225

[10] Zhang S, Ang MH, Xiao W, Tham CK. Detection of activities for daily life surveillance: Eating and drinking. In: HealthCom 2008 - 10th International Conference on e-health Networking, Applications and Services; Singapore; 2008. pp. 171-176. DOI: 10.1109/

[11] Melis WJC, Chizuwa S, Kameyama M. Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture. In: 2009 39th International Symposium on Multiple-Valued Logic; Naha, Okinawa; 2009. pp. 233-238. DOI: 10.1109/

[12] Zyarah AM. Design and analysis of a reconfigurable hierarchical temporal memory architecture [thesis]. 1 Lomb Memorial Dr, Rochester, NY 14623: Rochester Institute of

[13] Streat L, Kudithipudi D, Gomez K. Non-volatile Hierarchical Temporal Memory:

[14] Fan D, Sharad M, Sengupta A, Roy K. Hierarchical temporal memory based on spinneurons and resistive memory for energy-efficient brain-inspired computing. IEEE Transactions on Neural Networks and Learning Systems. Sept. 2016;**27**(9):1907-1919.

[15] James AP, Fedorova I, Ibrayev T, Kudithipudi D. HTM spatial pooler with memristor crossbar circuits for sparse biometric recognition. IEEE Transactions on Biomedical

[16] Merkel C, and Kudithipudi D. Neuromemristive systems: A circuit design perspective. In: Advances in Neuromorphic Hardware Exploiting Emerging Nanoscale Devices.

[17] Strukov DB, Snider GS, Stewart DR, Williams RS. The missing memristor found. Nature.

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2016 IEEE International Symposium on; IEEE; 2016. pp. 1254-1257

Circuits and Systems. 2017;**PP**(99):1-12. DOI: 10.1109/TBCAS.2016.2641983

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After giving an introduction to the HTM concepts and the memritive devices the chapter presents designs of two recent HTM hardware implementations. One of the designs is based on the memristive arrays and spin-neuron devices [14], while the second one integrates the memristor crossbar array and memristor-CMOS circuits [15].

## **Author details**

Alex James\*, Timur Ibrayev, Olga Krestinskaya and Irina Dolzhikova

\*Address all correspondence to: apj@ieee.org

School of Engineering, Nazarbayev University, Astana,Kazakhstan

## **References**


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to remember its state and change it based on history of applied voltages makes it suitable for neuromorphic designs. Thus, the nanoscale memristive devices could be used to mimic the

After giving an introduction to the HTM concepts and the memritive devices the chapter presents designs of two recent HTM hardware implementations. One of the designs is based on the memristive arrays and spin-neuron devices [14], while the second one integrates the

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synaptic connection of the neuron.

224 Memristor and Memristive Neural Networks

\*Address all correspondence to: apj@ieee.org

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frobt.2016.00081

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**Author details**

**References**

memristor crossbar array and memristor-CMOS circuits [15].

Alex James\*, Timur Ibrayev, Olga Krestinskaya and Irina Dolzhikova

School of Engineering, Nazarbayev University, Astana,Kazakhstan


**Chapter 11**

**Provisional chapter**

**Review of Recently Progress on Neural Electronics and**

In this chapter, we focus on the recent process on memcomputing (memristor + computing)

section of the chapter, we investigate neuromorphic computing by mimicking the synaptic behaviors in integrating one-diode and one-resistive switching element (1D-1R) architecture. The power consumption can be minimized further in synaptic functions because sneak-path current has been suppressed and the capability for spike-induced synaptic behaviors has been demonstrated, representing critical milestones and achievements for the application

next section of chapter, we will discuss an implementation technique of implication opera-

function and its truth table have been implemented with the unipolar or nonpolar operation scheme. Furthermore, a circuit with 1D-1R architecture with a 4 × 4 crossbar array has been demonstrated, which realizes the functionality of a one-bit full adder as same as CMOS logic circuits with lower design area requirement. This chapter suggests that a simple, robust approach to realize memcomputing chips is quite compatible with large-scale CMOS manu-

**Keywords:** resistive switching, synaptic device, silicon oxide, neuromorphic computing





**Review of Recently Progress on Neural Electronics and** 

DOI: 10.5772/intechopen.68530

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

**Memcomputing Applications in Intrinsic SiO***x***-Based**

**Memcomputing Applications in Intrinsic SiO***x***-Based** 

**Resistive Switching Memory**

**Resistive Switching Memory**

Cheng-Chih Hsieh, Yao-Feng Chang,

Fei Zhou, Sungjun Kim, Burt Fowler,

Chang and Jack C. Lee

**Abstract**

in intrinsic SiO*<sup>x</sup>*

of conventional SiO*<sup>x</sup>*

Cheng-Chih Hsieh, Yao-Feng Chang,

http://dx.doi.org/10.5772/intechopen.68530

Sungjun Kim, Burt Fowler, Chih-Yang Lin,

Ying-Chen Chen, Xiaohan Wu, Meiqi Guo,

Chih-Yang Lin, Chih-Hung Pan, Ting-Chang

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Ying-Chen Chen, Xiaohan Wu, Meiqi Guo, Fei Zhou,

Chih-Hung Pan, Ting-Chang Chang and Jack C. Lee

tions for logic-in-memory computation by using a SiO*<sup>x</sup>*

facturing technology by using an intrinsic SiO*<sup>x</sup>*

**Provisional chapter**

## **Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic SiO***x***-Based Resistive Switching Memory Memcomputing Applications in Intrinsic SiO***x***-Based Resistive Switching Memory**

**Review of Recently Progress on Neural Electronics and** 

DOI: 10.5772/intechopen.68530

Cheng-Chih Hsieh, Yao-Feng Chang, Ying-Chen Chen, Xiaohan Wu, Meiqi Guo, Fei Zhou, Sungjun Kim, Burt Fowler, Chih-Yang Lin, Chih-Hung Pan, Ting-Chang Chang and Jack C. Lee Ying-Chen Chen, Xiaohan Wu, Meiqi Guo, Fei Zhou, Sungjun Kim, Burt Fowler, Chih-Yang Lin, Chih-Hung Pan, Ting-Chang Chang and Jack C. Lee Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.68530

Cheng-Chih Hsieh, Yao-Feng Chang,

#### **Abstract**

In this chapter, we focus on the recent process on memcomputing (memristor + computing) in intrinsic SiO*<sup>x</sup>* -based resistive switching memory (ReRAM or called memristor). In the first section of the chapter, we investigate neuromorphic computing by mimicking the synaptic behaviors in integrating one-diode and one-resistive switching element (1D-1R) architecture. The power consumption can be minimized further in synaptic functions because sneak-path current has been suppressed and the capability for spike-induced synaptic behaviors has been demonstrated, representing critical milestones and achievements for the application of conventional SiO*<sup>x</sup>* -based materials in future advanced neuromorphic computing. In the next section of chapter, we will discuss an implementation technique of implication operations for logic-in-memory computation by using a SiO*<sup>x</sup>* -based memristor. The implication function and its truth table have been implemented with the unipolar or nonpolar operation scheme. Furthermore, a circuit with 1D-1R architecture with a 4 × 4 crossbar array has been demonstrated, which realizes the functionality of a one-bit full adder as same as CMOS logic circuits with lower design area requirement. This chapter suggests that a simple, robust approach to realize memcomputing chips is quite compatible with large-scale CMOS manufacturing technology by using an intrinsic SiO*<sup>x</sup>* -based memristor.

**Keywords:** resistive switching, synaptic device, silicon oxide, neuromorphic computing

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

## **1. Background**

In recent 20 years, emerging memory has drawn a lot of interest and attention as a promising candidate for next generation nonvolatile memory (NVM) [1–3]. Traditional "charge"-based NVM (Flash) will face the potential scaling challenge below the 10 nm node with reliability and power consumption issues [4, 5]. Resistive switching (RS) memory, or we call resistive random access memory (ReRAM), operates by controlling device "resistance" with an external electrical bias [6–9], leading to better electrical performance, smaller design area (4F<sup>2</sup> ), and excellent cycling endurance [10] based on the 2015 International Technology Roadmap for Semiconductors (ITRS) (ReRAM is one of two recommended candidate technologies (the other one is the STT-MRAM) for emerging memory devices) [11]. Moreover, RS-based memories represent a new class of devices compatible with applications that go beyond traditional electronics configurations, for example, three-dimensional (3D) stacking, nanobatteries, neuroelectronics, and Boolean logic operations [12–17].

registers [32], and counters [32]. The advantages of memcomputing (memristor + computing) are not only to store and process information on the same physical platform, but also to allow

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic...

Otherwise, neuroelectronics and synaptic electronics are interesting applications for ReRAM that aim to build artificial synaptic devices that emulate the computations performed by biological synapses [15, 33]. These emerging fields of research potentially have better efficiency in solving complex problems and outperform real-time processing of unstructured data than conventional von Neumann computational systems [34]. There have been many studies of binary metal oxide-based and perovskite oxide-based resistance switching characteristics for synapse-like electronic device development [35, 36], which can have operating instability issues due to difficulty in controlling stoichiometric compositions [37, 38]. Therefore, a simple process that is compatible with conventional complementary metal-oxide semiconductor (CMOS) fabrication allows multilayer compositional engineering and provides good electrical stability and high yield, which are critical requirements for neuroelectronics

semiconductor field-effect transistors. In addition to excellent insulating properties, resistive

iors in vacuum, indicating that this traditional material can be converted to an active component by controlling the external electrical manipulation [43–45]. Several recent reports

[46–49]. We have further demonstrated a Si diode (1D) with low reverse-bias current inte-

Si diodes (1D) using conventional CMOS processing to demonstrate a 1D-1R device with synaptic behaviors. Compared with our previous work (in most cases investigating only the 1R device system), the Si diode provides low reverse-bias current and high power efficiency for future neuromorphic computing array architectures. Unlike other binary or complex metal

its excellent electrical isolation properties, low-cost, high chemical stability, compatibility with mainstream integrated circuit materials, high-throughput processing, and large-area production using chemical vapor deposition (CVD). A 1D-1R architecture fabricated at the wafer-scale using conventional CMOS processing can, therefore, be well controlled in thickness, size, and electrical characteristics by precisely controlling the doping levels of the diode layers and the temperature and flow-rate of the oxide CVD process [52]. Synaptic device performance is characterized in a prototype 1D-1R array configuration. Robust biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD), and spike-timing-dependent plasticity (STDP) are demonstrated with excellent uniformity, low

1967 by Simmons and Verderber [40–42]. Yao et al. also have reported SiO*<sup>x</sup>*

/N++ epitaxial Si wafer [50].

) has long been used as gate dielectrics for metal-oxide-

as the active switching medium in resistive switching memory devices



has been used in CMOS manufacturing for over 50 years due to

materials as early as 1962 by Hickmott and

http://dx.doi.org/10.5772/intechopen.68530

229


massively parallel computations in a simple crossbar array architecture.

realization [39]. Silicon oxide (SiO*<sup>x</sup>*

describe using SiO2

grated with a SiO*<sup>x</sup>*

**2. Introduction**

etching to pattern a P++/N+

In this chapter, first SiO*<sup>x</sup>*

oxide materials [51], SiO*<sup>x</sup>*

switching properties have been observed in SiO*<sup>x</sup>*

In 1971, Chua presented the theoretical basis for a passive two-terminal circuit device called a "memristor" (a contraction of memory and resistor) [18]. If realized, the memristor would then join the resistor, inductor, and capacitor to provide four basic circuit elements. In 2010, researchers in HP lab realized the memristor in nanoscale titanium dioxide (TiO2 ) cross-point structure [17], and the field has advanced quickly growth over the past decade as a result. Having demonstrated the existence of memristors in the lab, additional research efforts focused on the potential applications that this emerging new circuit element enables [19]. In recent years, memristors have been extensively studied as a nonvolatile memory called resistive random-access-memory (named ReRAM or RRAM) to potentially replace dynamic random-access-memory (DRAM) and flash memory [20]. Memristors have also gained tremendous interest in the field of neuroelectronics and synaptic electronics, which aims to build artificial synaptic devices that emulate the computations performed by biological synapses [21–25]. Jo et al. described possible applications in artificial intelligence using memristors as synapses in neuromorphic circuits [15]. Another interesting application is to use memristors for arithmetic/logic operations, such as an adder circuit or a multiplier circuit.

In the literature, arithmetic operations are proposed using the memristor as a: (1) switch, (2) programmable interconnect, and (3) computational element. In the first approach, crossbar arrays of memristor switches are connected to a row of weighting resistors and sensing logic to build an analog arithmetic processor [26]. The switches control the current flow (ON/OFF) through the weighting resistor, which then controls the analog voltage at the sensing amplifier end. The resistance of the weighting resistor assigns the appropriate bit significance to the each row's current contribution. The memristor-CMOS technology may be used to realize the same types of arithmetic circuits that are developed in CMOS/FPGA (field programmable gate array) technology [27, 28]. Last but not the least, a more universal approach for constructing the logic operations from memristors is via "material implication" (or an "IMP" operation). In 2010, researchers showed that all fundamental Boolean logic functions can be realized by using memristors with the IMP operation [17]. Later work built on these findings to construct larger logic blocks such as adders and multipliers [29–31], linear feedback shift registers [32], and counters [32]. The advantages of memcomputing (memristor + computing) are not only to store and process information on the same physical platform, but also to allow massively parallel computations in a simple crossbar array architecture.

Otherwise, neuroelectronics and synaptic electronics are interesting applications for ReRAM that aim to build artificial synaptic devices that emulate the computations performed by biological synapses [15, 33]. These emerging fields of research potentially have better efficiency in solving complex problems and outperform real-time processing of unstructured data than conventional von Neumann computational systems [34]. There have been many studies of binary metal oxide-based and perovskite oxide-based resistance switching characteristics for synapse-like electronic device development [35, 36], which can have operating instability issues due to difficulty in controlling stoichiometric compositions [37, 38]. Therefore, a simple process that is compatible with conventional complementary metal-oxide semiconductor (CMOS) fabrication allows multilayer compositional engineering and provides good electrical stability and high yield, which are critical requirements for neuroelectronics realization [39]. Silicon oxide (SiO*<sup>x</sup>* ) has long been used as gate dielectrics for metal-oxidesemiconductor field-effect transistors. In addition to excellent insulating properties, resistive switching properties have been observed in SiO*<sup>x</sup>* materials as early as 1962 by Hickmott and 1967 by Simmons and Verderber [40–42]. Yao et al. also have reported SiO*<sup>x</sup>* -based RS behaviors in vacuum, indicating that this traditional material can be converted to an active component by controlling the external electrical manipulation [43–45]. Several recent reports describe using SiO2 as the active switching medium in resistive switching memory devices [46–49]. We have further demonstrated a Si diode (1D) with low reverse-bias current integrated with a SiO*<sup>x</sup>* -based memory element (1R) using nanosphere lithography and deep Si etching to pattern a P++/N+ /N++ epitaxial Si wafer [50].

## **2. Introduction**

**1. Background**

228 Memristor and Memristive Neural Networks

In recent 20 years, emerging memory has drawn a lot of interest and attention as a promising candidate for next generation nonvolatile memory (NVM) [1–3]. Traditional "charge"-based NVM (Flash) will face the potential scaling challenge below the 10 nm node with reliability and power consumption issues [4, 5]. Resistive switching (RS) memory, or we call resistive random access memory (ReRAM), operates by controlling device "resistance" with an external electrical bias [6–9], leading to better electrical performance, smaller design area (4F<sup>2</sup>

and excellent cycling endurance [10] based on the 2015 International Technology Roadmap for Semiconductors (ITRS) (ReRAM is one of two recommended candidate technologies (the other one is the STT-MRAM) for emerging memory devices) [11]. Moreover, RS-based memories represent a new class of devices compatible with applications that go beyond traditional electronics configurations, for example, three-dimensional (3D) stacking, nanobatteries, neu-

In 1971, Chua presented the theoretical basis for a passive two-terminal circuit device called a "memristor" (a contraction of memory and resistor) [18]. If realized, the memristor would then join the resistor, inductor, and capacitor to provide four basic circuit elements. In 2010,

structure [17], and the field has advanced quickly growth over the past decade as a result. Having demonstrated the existence of memristors in the lab, additional research efforts focused on the potential applications that this emerging new circuit element enables [19]. In recent years, memristors have been extensively studied as a nonvolatile memory called resistive random-access-memory (named ReRAM or RRAM) to potentially replace dynamic random-access-memory (DRAM) and flash memory [20]. Memristors have also gained tremendous interest in the field of neuroelectronics and synaptic electronics, which aims to build artificial synaptic devices that emulate the computations performed by biological synapses [21–25]. Jo et al. described possible applications in artificial intelligence using memristors as synapses in neuromorphic circuits [15]. Another interesting application is to use memristors

In the literature, arithmetic operations are proposed using the memristor as a: (1) switch, (2) programmable interconnect, and (3) computational element. In the first approach, crossbar arrays of memristor switches are connected to a row of weighting resistors and sensing logic to build an analog arithmetic processor [26]. The switches control the current flow (ON/OFF) through the weighting resistor, which then controls the analog voltage at the sensing amplifier end. The resistance of the weighting resistor assigns the appropriate bit significance to the each row's current contribution. The memristor-CMOS technology may be used to realize the same types of arithmetic circuits that are developed in CMOS/FPGA (field programmable gate array) technology [27, 28]. Last but not the least, a more universal approach for constructing the logic operations from memristors is via "material implication" (or an "IMP" operation). In 2010, researchers showed that all fundamental Boolean logic functions can be realized by using memristors with the IMP operation [17]. Later work built on these findings to construct larger logic blocks such as adders and multipliers [29–31], linear feedback shift

researchers in HP lab realized the memristor in nanoscale titanium dioxide (TiO2

for arithmetic/logic operations, such as an adder circuit or a multiplier circuit.

roelectronics, and Boolean logic operations [12–17].

),

) cross-point

In this chapter, first SiO*<sup>x</sup>* -based resistive switching memory elements (1R) are integrated with Si diodes (1D) using conventional CMOS processing to demonstrate a 1D-1R device with synaptic behaviors. Compared with our previous work (in most cases investigating only the 1R device system), the Si diode provides low reverse-bias current and high power efficiency for future neuromorphic computing array architectures. Unlike other binary or complex metal oxide materials [51], SiO*<sup>x</sup>* has been used in CMOS manufacturing for over 50 years due to its excellent electrical isolation properties, low-cost, high chemical stability, compatibility with mainstream integrated circuit materials, high-throughput processing, and large-area production using chemical vapor deposition (CVD). A 1D-1R architecture fabricated at the wafer-scale using conventional CMOS processing can, therefore, be well controlled in thickness, size, and electrical characteristics by precisely controlling the doping levels of the diode layers and the temperature and flow-rate of the oxide CVD process [52]. Synaptic device performance is characterized in a prototype 1D-1R array configuration. Robust biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD), and spike-timing-dependent plasticity (STDP) are demonstrated with excellent uniformity, low operational variability, and good suppression of static power consumption [51]. A bioinspired proton exchange resistive switching model is used to help characterize this novel application for SiO*<sup>x</sup>* materials. The SET transition in the resistive switching memory is modeled as hydrogen (proton) release from the (Si-H)2 defect to generate a conductive hydrogen bridge, and the RESET transition is modeled as an electrochemical reaction (proton capture) that reforms nonconductive (SiH)2 . The synaptic behaviors exhibited by the 1D-1R device demonstrates good potential for using a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology.

Second, the application of SiO*<sup>x</sup>* -based memristors for material implication operations is examined. A bidirectional implication scheme is demonstrated and tested in an actual circuit using SiO*<sup>x</sup>* -based memristors. The symmetric unipolar memristive behavior of the SiO*<sup>x</sup>* -based memristor enables the use of two sets of implication voltage setups, one positive and the other negative, hence the name "bidirectional". Progressing one step further from the initial concept demonstrated by Borghetti et al. and our previous work, a one-bit full adder is realized by using the material implication technique on a crossbar structure with a one-diode onememristor (1D-1R) array. Several potential application problems such as sneak current paths within an array and using a select transistor as the load resistor are discussed in detail. The results suggest that a memristor-enabled logic circuit is most suitable for applications requiring low-speed, low-power, and high-density.

> to electroform devices and measure the DC/AC *I-V* response. The SET process programs the device to a conductive, low-resistance state (LRS). The RESET process programs each device to a low-conductance, high-resistance state (HRS). A Kratos Axis Ultra HSA X-ray photoelectron spectrometer (XPS) equipped with a monochromatized aluminum X-ray source was used to

> **Figure 1.** (a) Top-down SEM image of 1D-1R architecture. The 1R is adjacent to the 1D structure. The ground pad (0) is used to bias the substrate, the positive (+) and negative (−) terminals are for applying voltage to the 1D-1R device. (b) Tilted top-down SEM image of resistive memory device. (c) SEM cross-section image showing metal contact to

polysilicon top electrode, metal 1 (M1) and metal 2 (M2) layers, and polysilicon/SiO2

XPS spectra for PECVD oxide and thermal oxide. Figure reprinted by [19].

of the binding energy scale was set by fixing the C-(C,H) peak at 284.4 eV. **Figure 1d** shows XPS analysis results for the O-1s and Si-2p binding energies in thermal oxide grown by lowpressure chemical vapor deposition (LPCVD) and PECVD oxide. The existence of stoichio-

essentially no suboxide bonding being detected. In contrast, the PECVD oxide has nonstoichio-

switching layer, as indicated by the peak-binding energies in the XPS spectra (O: 530.5 eV; Si: 101.9 eV, and 100.9 eV) [54, 55], which may promote low-energy defect generation during the

devices fabricated by the conventional CMOS process. Voltage was applied to the 1D top electrode (p-type Si) with bottom 1R electrode (n-type Si) at ground. All testing was done in

**Figure 2a**–**d** show *I-V* characteristics for DC voltage sweeps applied to the SiO*<sup>x</sup>*

materials deposited in our laboratory using different methods. Calibration

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic...


/Si 1R device. (d) Si-2p2/3 and O-1s

http://dx.doi.org/10.5772/intechopen.68530

231

can be observed in thermal oxide (binding energy Si: 103.2 eV; O: 532.5 eV) with

(x is about 1.6 based on the peak position and orbital valence) composition in the

analyze several SiO*<sup>x</sup>*

electroforming process.

**4. Results and discussions**

metric SiO2

metric SiO*<sup>x</sup>*

## **3. Method and experiment**

Secondary electron microscopy (SEM) images show a top-down view of a 1D-1R test structure (**Figure 1a**), a tilted (45°) view of the 1R device (**Figure 1b**) and a cross-section image of the 1R device showing layer information (**Figure 1c**). The devices were fabricated at XFAB in Lubbock TX using the XC06 CMOS process technology. The 1R device was fabricated by first implanting the Si substrate to form an n-type lower electrode. The active SiO*<sup>x</sup>* memory layer was then deposited to a thickness of 40 nm using plasma-enhanced chemical vapor deposition (PECVD). This thickness is known to provide high electroforming yield and good memory endurance [53]. An n-type polysilicon layer was deposited onto the SiO*<sup>x</sup>* layer to form the top electrode. An opening in the polysilicon layer was made after all thermal oxidation and implant anneal steps are complete (**Figure 1b**). A first dielectric layer was then deposited over the polysilicon top electrode. Tungsten plugs were used to make electrical contact to the n-type Si lower electrode and the polysilicon top electrode. After all the back-end dielectrics and a passivation layer were deposited, the back-end dielectric layers were removed using reactive ion etch (RIE) to the Si substrate. This RIE step cleared-out the SiO*<sup>x</sup>* layer inside the hole, and created a SiO*<sup>x</sup>* sidewall where the memory device is formed (**Figure 1c**). Polymer residue that remained after the post-RIE cleaning steps was removed by a 30-s buffered oxide etch (BOE). The pn diode used in the 1D-1R test structures was formed by an implanted p-well inside a deep n-well with 40 V reverse-bias breakdown voltage, 1 nA reverse-bias leakage current and 0.5 V forward voltage. The active memory area of the 1R device is 2 × 2 μm2 and the overall size including metal interconnects is 21.9 × 21.9 μm2 . The overall size of the 1D device is 41 × 19 μm2 . A lake shore cryotronics vacuum probe chamber (<1 mTorr) and Agilent B1500A device analyzer were used Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic... http://dx.doi.org/10.5772/intechopen.68530 231

**Figure 1.** (a) Top-down SEM image of 1D-1R architecture. The 1R is adjacent to the 1D structure. The ground pad (0) is used to bias the substrate, the positive (+) and negative (−) terminals are for applying voltage to the 1D-1R device. (b) Tilted top-down SEM image of resistive memory device. (c) SEM cross-section image showing metal contact to polysilicon top electrode, metal 1 (M1) and metal 2 (M2) layers, and polysilicon/SiO2 /Si 1R device. (d) Si-2p2/3 and O-1s XPS spectra for PECVD oxide and thermal oxide. Figure reprinted by [19].

to electroform devices and measure the DC/AC *I-V* response. The SET process programs the device to a conductive, low-resistance state (LRS). The RESET process programs each device to a low-conductance, high-resistance state (HRS). A Kratos Axis Ultra HSA X-ray photoelectron spectrometer (XPS) equipped with a monochromatized aluminum X-ray source was used to analyze several SiO*<sup>x</sup>* materials deposited in our laboratory using different methods. Calibration of the binding energy scale was set by fixing the C-(C,H) peak at 284.4 eV. **Figure 1d** shows XPS analysis results for the O-1s and Si-2p binding energies in thermal oxide grown by lowpressure chemical vapor deposition (LPCVD) and PECVD oxide. The existence of stoichiometric SiO2 can be observed in thermal oxide (binding energy Si: 103.2 eV; O: 532.5 eV) with essentially no suboxide bonding being detected. In contrast, the PECVD oxide has nonstoichiometric SiO*<sup>x</sup>* (x is about 1.6 based on the peak position and orbital valence) composition in the switching layer, as indicated by the peak-binding energies in the XPS spectra (O: 530.5 eV; Si: 101.9 eV, and 100.9 eV) [54, 55], which may promote low-energy defect generation during the electroforming process.

#### **4. Results and discussions**

operational variability, and good suppression of static power consumption [51]. A bioinspired proton exchange resistive switching model is used to help characterize this novel

bridge, and the RESET transition is modeled as an electrochemical reaction (proton capture)

demonstrates good potential for using a simple and robust approach for large-scale integra-

ined. A bidirectional implication scheme is demonstrated and tested in an actual circuit using

ristor enables the use of two sets of implication voltage setups, one positive and the other negative, hence the name "bidirectional". Progressing one step further from the initial concept demonstrated by Borghetti et al. and our previous work, a one-bit full adder is realized by using the material implication technique on a crossbar structure with a one-diode onememristor (1D-1R) array. Several potential application problems such as sneak current paths within an array and using a select transistor as the load resistor are discussed in detail. The results suggest that a memristor-enabled logic circuit is most suitable for applications requir-

Secondary electron microscopy (SEM) images show a top-down view of a 1D-1R test structure (**Figure 1a**), a tilted (45°) view of the 1R device (**Figure 1b**) and a cross-section image of the 1R device showing layer information (**Figure 1c**). The devices were fabricated at XFAB in Lubbock TX using the XC06 CMOS process technology. The 1R device was fabricated by first implant-

deposited to a thickness of 40 nm using plasma-enhanced chemical vapor deposition (PECVD). This thickness is known to provide high electroforming yield and good memory endurance

An opening in the polysilicon layer was made after all thermal oxidation and implant anneal steps are complete (**Figure 1b**). A first dielectric layer was then deposited over the polysilicon top electrode. Tungsten plugs were used to make electrical contact to the n-type Si lower electrode and the polysilicon top electrode. After all the back-end dielectrics and a passivation layer were deposited, the back-end dielectric layers were removed using reactive ion etch (RIE)

sidewall where the memory device is formed (**Figure 1c**). Polymer residue that remained after the post-RIE cleaning steps was removed by a 30-s buffered oxide etch (BOE). The pn diode used in the 1D-1R test structures was formed by an implanted p-well inside a deep n-well with 40 V reverse-bias breakdown voltage, 1 nA reverse-bias leakage current and 0.5 V forward volt-

cryotronics vacuum probe chamber (<1 mTorr) and Agilent B1500A device analyzer were used

. The overall size of the 1D device is 41 × 19 μm2


materials. The SET transition in the resistive switching memory is mod-

defect to generate a conductive hydrogen


memory layer was then

layer to form the top electrode.

layer inside the hole, and created a SiO*<sup>x</sup>*

and the overall size including metal

. A lake shore

. The synaptic behaviors exhibited by the 1D-1R device


application for SiO*<sup>x</sup>*

SiO*<sup>x</sup>*

eled as hydrogen (proton) release from the (Si-H)2

ing low-speed, low-power, and high-density.

**3. Method and experiment**

tion of programmable neuromorphic chips using CMOS technology.

ing the Si substrate to form an n-type lower electrode. The active SiO*<sup>x</sup>*

[53]. An n-type polysilicon layer was deposited onto the SiO*<sup>x</sup>*

to the Si substrate. This RIE step cleared-out the SiO*<sup>x</sup>*

age. The active memory area of the 1R device is 2 × 2 μm2

interconnects is 21.9 × 21.9 μm2

that reforms nonconductive (SiH)2

Second, the application of SiO*<sup>x</sup>*

230 Memristor and Memristive Neural Networks

**Figure 2a**–**d** show *I-V* characteristics for DC voltage sweeps applied to the SiO*<sup>x</sup>* -based 1D-1R devices fabricated by the conventional CMOS process. Voltage was applied to the 1D top electrode (p-type Si) with bottom 1R electrode (n-type Si) at ground. All testing was done in

resistive states by modulating the voltage sweep range continuously during the SET and RESET (inset) process, respectively. Specifically, SET and RESET voltages were changed from 3.5 to 9.5 V in 0.5 V increments and from 11 to 18 V in 0.5 V decrements, respectively, thus potentially enabling multilevel programming in a single memory cell and demonstrate the status stability before/after sweeps. It may be noted that the electroforming voltages measured here (~ 28 V) are somewhat higher than those measured in previous work on metal-oxide-semiconductor device architectures or nanopillar type 1D-1R architectures [50,

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic...

a result of the fabrication process. For example, several high temperature steps (>650°C)

levels, increase the soft breakdown threshold, and thus increase the filament formation energy during the subsequent electroforming process (resulting in forming voltage increase). Interestingly, the RESET voltage (the voltage at which LRS current begins to decrease) has been found to be greater than or equal to the SET voltage (where HRS current increases

materials systems [36, 58]. The difference between RESET and SET voltages can potentially be controlled by optimizing the series resistance in the circuit, choice of electrode materials, and by doping effects that modulate the interfacial contact resistance [59]. The switching

SET voltage from 3 to 9 V. The readout current of LRS and HRS is measured at 1 V every 60 s after each programming operation. Although the state's stability still needs to be improved (no equal split of resistance states), the retention reliability test demonstrates ` operation by

possible proton exchange model consistent with the observed resistive switching *I-V* response has been proposed, as shown in **Figure 2f** [59, 60]. Several studies have used transmission electron microscopy (TEM) to document the presence of Si nanocrystals within the CF [43, 61, 62], but it is not yet clear whether resistive switching (RS) is the result of an overall increase in nanocrystal size or whether switching occurs in "GAP" regions in between nanocrystals. Most models of ReRAM switching involve the drift or diffusion of O2− ions (or oxygen vacancy defects) [39], but these models cannot explain the unconventional *I-V* response. For example, the backward scan effect (see **Figure 2a**, backward scan) is very difficult to explain using a simple oxygen vacancy-switching model. The backward scan effect is a phenomenon where the duration of the reverse sweep during electroforming or RESET determines whether a state change occurs, and has been characterized using DC and AC pulse response in a previous study investigating our resistive switching model [57]. In addition, ambient effects on resistive switching suggest that the defects responsible for switching are hydrogen-passivated or are in some way protected from direct reaction with ambient oxygen and water until a switching events occurs [56, 63]. The detailed interactions between ambient gases and proton (or cation) mobility is an important topic that may provide a deeper understanding of resistive switching mechanisms [64–68], specifically those in oxide-based valence change memory (VCM)-type ReRAMs [69–71]. The models used here to describe the possible

using different SET voltages, and no degradation is observed for more than 10<sup>3</sup>

deposition, namely: polysilicon deposition, thermal oxidation,


layer, reduce the as-deposited defect

http://dx.doi.org/10.5772/intechopen.68530


thickness. **Figure 2e** shows multilevel


sidewall as

233

s, thus con-

56, 57], which may be due to fewer electrically active defects being near the SiO*<sup>x</sup>*

were done after PECVD SiO2

retention performance of SiO*<sup>x</sup>*

and implant anneals, which might densify the SiO2

sharply), which is a unique characteristic of the SiO*<sup>x</sup>*

voltage is largely independent of device size and SiO*<sup>x</sup>*

firming the stable, nonvolatile nature of the SiO*<sup>x</sup>*

**Figure 2.** DC sweep resistive switching behaviors of 1D-1R architecture: (a) Forward/backward voltage sweeps during electroforming process averaged for 256 devices in a 16 × 16 array (gray curves). The electroforming voltage (*V*Delta Current) is defined as the voltage where maximum current change occurs during the forward sweep. (b) 10 I-V resistive switching SET/RESET cycles. The inset shows the average of 100 measurement cycles of diode I-V behavior. (c) Effects of voltage modulation on I-V curves in SET process plotted on linear-scale, where the applied SET voltage sweep increases from 3.5 to 9.5 V in 0.5 V steps. The inset shows effects of voltage modulation on I-V curves in RESET process plotted on log-scale, where the applied RESET voltage sweep increases from 11.0 to 18.0 V in 0.5 V steps. (d) The resistance states of initial fresh device, SET DC voltage modulation, and RESET DC voltage modulation. For SET voltage sweep, increases from 3.5 to 10 V in 0.5 V steps; for RESET voltage sweep, increases from 11 to 20 V in 0.5 V steps. The resistance reads at 1V for each state. (e) Retention measurement results of multi-state programming obtained by controlling the SET voltage. (f) Proton exchange induced resistive switching model and defect transitions. Figure reprinted by [19].

vacuum. To establish reversible resistive switching in each SiO*<sup>x</sup>* -based 1R ReRAM device, a forward/backward voltage sweep (**Figure 2a**) was used to electroform each device, where current is observed to increase dramatically at 22.5 ± 2.9 V during the forward voltage sweep. Electroforming is completed during the backward voltage sweep from the maximum sweeping voltage to 0 V, resulting in the formation of a conductive filament (CF) and setting the device to a LRS. After electroformation, RS performance of 1D-1R can be stabilized by 10 times cycles (**Figure 2b**). For SET process, a 10 V forward/backward sweep is applied without any compliance current limitation (CCL) to change the device from HRS to LRS; for RESET process, a 17 V, single sweep is done to change the device from LRS to HRS. The HRS/ LRS resistance ratio can be read out at 1 V bias with satisfying sensing requirements (~103 ) [3, 26]. For diode characteristics, the forward current can reach 100 mA at 2 V (current density 1.15 × 10−5 A/μm2 at 1 V), which indicates a forward current level high enough to support the RESET process. The reverse current is below 1 × 10−12 A at −5 V. Compared with Schottky diodes (potentially useful for 3D arrays), the advantages of Si-based PN diodes include low reverse current, high reverse-bias breakdown voltage, and fewer stability issues [45]. The quality of the Si-based PN diode can dramatically affect diode reverse or forward current characteristics, as well as power consumption (describe below). Also, the chosen Si-based PN diode configuration has high reverse breakdown voltage (>40 V), which is important for SiO*<sup>x</sup>* -based ReRAM operating in an array. **Figure 2c** demonstrates the gradual change of resistive states by modulating the voltage sweep range continuously during the SET and RESET (inset) process, respectively. Specifically, SET and RESET voltages were changed from 3.5 to 9.5 V in 0.5 V increments and from 11 to 18 V in 0.5 V decrements, respectively, thus potentially enabling multilevel programming in a single memory cell and demonstrate the status stability before/after sweeps. It may be noted that the electroforming voltages measured here (~ 28 V) are somewhat higher than those measured in previous work on metal-oxide-semiconductor device architectures or nanopillar type 1D-1R architectures [50, 56, 57], which may be due to fewer electrically active defects being near the SiO*<sup>x</sup>* sidewall as a result of the fabrication process. For example, several high temperature steps (>650°C) were done after PECVD SiO2 deposition, namely: polysilicon deposition, thermal oxidation, and implant anneals, which might densify the SiO2 layer, reduce the as-deposited defect levels, increase the soft breakdown threshold, and thus increase the filament formation energy during the subsequent electroforming process (resulting in forming voltage increase). Interestingly, the RESET voltage (the voltage at which LRS current begins to decrease) has been found to be greater than or equal to the SET voltage (where HRS current increases sharply), which is a unique characteristic of the SiO*<sup>x</sup>* -based ReRAM as compared to other materials systems [36, 58]. The difference between RESET and SET voltages can potentially be controlled by optimizing the series resistance in the circuit, choice of electrode materials, and by doping effects that modulate the interfacial contact resistance [59]. The switching voltage is largely independent of device size and SiO*<sup>x</sup>* thickness. **Figure 2e** shows multilevel retention performance of SiO*<sup>x</sup>* -based 1D-1R devices obtained by controlling the maximum SET voltage from 3 to 9 V. The readout current of LRS and HRS is measured at 1 V every 60 s after each programming operation. Although the state's stability still needs to be improved (no equal split of resistance states), the retention reliability test demonstrates ` operation by using different SET voltages, and no degradation is observed for more than 10<sup>3</sup> s, thus confirming the stable, nonvolatile nature of the SiO*<sup>x</sup>* -based 1D-1R devices. In recent studies, a possible proton exchange model consistent with the observed resistive switching *I-V* response has been proposed, as shown in **Figure 2f** [59, 60]. Several studies have used transmission electron microscopy (TEM) to document the presence of Si nanocrystals within the CF [43, 61, 62], but it is not yet clear whether resistive switching (RS) is the result of an overall increase in nanocrystal size or whether switching occurs in "GAP" regions in between nanocrystals. Most models of ReRAM switching involve the drift or diffusion of O2− ions (or oxygen vacancy defects) [39], but these models cannot explain the unconventional *I-V* response. For example, the backward scan effect (see **Figure 2a**, backward scan) is very difficult to explain using a simple oxygen vacancy-switching model. The backward scan effect is a phenomenon where the duration of the reverse sweep during electroforming or RESET determines whether a state change occurs, and has been characterized using DC and AC pulse response in a previous study investigating our resistive switching model [57]. In addition, ambient effects on resistive switching suggest that the defects responsible for switching are hydrogen-passivated or are in some way protected from direct reaction with ambient oxygen and water until a switching events occurs [56, 63]. The detailed interactions between ambient gases and proton (or cation) mobility is an important topic that may provide a deeper understanding of resistive switching mechanisms [64–68], specifically those in oxide-based valence change memory (VCM)-type ReRAMs [69–71]. The models used here to describe the possible

vacuum. To establish reversible resistive switching in each SiO*<sup>x</sup>*

Proton exchange induced resistive switching model and defect transitions. Figure reprinted by [19].

1.15 × 10−5 A/μm2

232 Memristor and Memristive Neural Networks

SiO*<sup>x</sup>*

forward/backward voltage sweep (**Figure 2a**) was used to electroform each device, where current is observed to increase dramatically at 22.5 ± 2.9 V during the forward voltage sweep. Electroforming is completed during the backward voltage sweep from the maximum sweeping voltage to 0 V, resulting in the formation of a conductive filament (CF) and setting the device to a LRS. After electroformation, RS performance of 1D-1R can be stabilized by 10 times cycles (**Figure 2b**). For SET process, a 10 V forward/backward sweep is applied without any compliance current limitation (CCL) to change the device from HRS to LRS; for RESET process, a 17 V, single sweep is done to change the device from LRS to HRS. The HRS/ LRS resistance ratio can be read out at 1 V bias with satisfying sensing requirements (~103

**Figure 2.** DC sweep resistive switching behaviors of 1D-1R architecture: (a) Forward/backward voltage sweeps during electroforming process averaged for 256 devices in a 16 × 16 array (gray curves). The electroforming voltage (*V*Delta Current) is defined as the voltage where maximum current change occurs during the forward sweep. (b) 10 I-V resistive switching SET/RESET cycles. The inset shows the average of 100 measurement cycles of diode I-V behavior. (c) Effects of voltage modulation on I-V curves in SET process plotted on linear-scale, where the applied SET voltage sweep increases from 3.5 to 9.5 V in 0.5 V steps. The inset shows effects of voltage modulation on I-V curves in RESET process plotted on log-scale, where the applied RESET voltage sweep increases from 11.0 to 18.0 V in 0.5 V steps. (d) The resistance states of initial fresh device, SET DC voltage modulation, and RESET DC voltage modulation. For SET voltage sweep, increases from 3.5 to 10 V in 0.5 V steps; for RESET voltage sweep, increases from 11 to 20 V in 0.5 V steps. The resistance reads at 1V for each state. (e) Retention measurement results of multi-state programming obtained by controlling the SET voltage. (f)

26]. For diode characteristics, the forward current can reach 100 mA at 2 V (current density

RESET process. The reverse current is below 1 × 10−12 A at −5 V. Compared with Schottky diodes (potentially useful for 3D arrays), the advantages of Si-based PN diodes include low reverse current, high reverse-bias breakdown voltage, and fewer stability issues [45]. The quality of the Si-based PN diode can dramatically affect diode reverse or forward current characteristics, as well as power consumption (describe below). Also, the chosen Si-based PN diode configuration has high reverse breakdown voltage (>40 V), which is important for


at 1 V), which indicates a forward current level high enough to support the


) [3,

SiO*<sup>x</sup>* -based RS mechanisms differ from most conventional models by considering that the defects responsible for RS may remain localized within the switching region so that resistive switching occurs when a collection of defects are driven between conductive and nonconductive forms [56]. A thorough review of the reported electrical and structural properties of known SiO*<sup>x</sup>* defects has identified a plausible model for the conductive filament that is similar to models used to describe stress-induced leakage current and breakdown in SiO*<sup>x</sup>* materials, where defect concentration increases as a result of electrical stress to the point where percolation pathways capable of conducting appreciable current (>1 uA) are formed [59]. Incorporating known proton exchange reactions that can dramatically alter the conductivity of specific defects further leads to a model where the LRS has a large concentration of conductive defects within the switching region, and, conversely, when the device is programmed to the HRS, most of the defects are converted to their nonconductive form. The electrically conductive hydrogen bridge (Si-H-Si) is viewed as the most likely defect responsible for the LRS due to the location of its energy levels relative to the oxide conduction band and its small effective bandgap energy [59, 60]. Adding a proton to Si-H-Si forms the nonconductive (SiH)2 defect and proton desorption from (SiH)2 reforms Si-H-Si, which are wellunderstood electrochemical reactions that could enable localized switching without incorporating ion diffusion or drift mechanisms into the model. The SET transition voltage from HRS to LRS occurs at ~2.5 V in the I-V response, and is very near the activation energy for proton desorption from SiH (~2.5 eV), thus making the defect transformation from (SiH)2 to Si-H-Si a logical assignment for the SET transition [59, 60]. In this model, the proton that is lost from (SiH)2 reacts electrochemically with (SiOH)2 , which is simply chemisorbed H2 O, to form the fixed positive charged H<sup>3</sup> O+ defect. The transition from LRS to HRS is modeled as being initiated by electron injection into H3 O+ that induces proton release and electrochemical reaction with Si-H-Si to reform (SiH)2 [59, 60]. The localized proton exchange switching model can thus be written as (SiH)<sup>2</sup> + (SiOH)2 ↔ Si-H-Si + Si2 =O-H3 O+ , where a voltage drop of ~2.5 V across the switching is required to drive the reversible reaction. The RS model not only provides insights into multilevel operational characteristics but also implies a possible biomimetic chemical reaction similar to reactive oxygen species (ROS-like) production for future device characterizations [72].

**Figure 3a**–**h** show contour plots of the current-change ratio achieved by modulating the AC pulse height and pulse width applied to 1D-1R devices for both SET and RESET switching events, leading to optimized waveform designs for a biological synaptic device. The current-change ratio is defined as log10 (IFINAL/IINITIAL), where IINITIAL and IFINAL are the currents measured at 1 V before and after applying the programing waveform, respectively. The SET/RESET sweeps from same initial resistance state (precondition programming) is to eliminate the accumulating SET/RESET effect after each cycle. One can observe by inspecting the contour lines in **Figure 3** that when larger pulse heights (higher voltages) are applied to the device, shorter pulse widths are needed to achieve a similar current-change ratio. In general, we find that a single 1R device operates at higher speed and requires lower programming voltages as compared to a 1D-1R device. The higher operating voltages and lower operating speed of the integrated 1D-1R device may result from higher parasitic resistance in the Si electrodes, their contacts and the diode, as well as higher parasitic capacitance in the diode, all of which can act to degrade the pulse mapping results shown in **Figure 3a** and **b**. It should be noted that current sneak-path issues in arrays and writing disturbance of 1R devices would cause misread problems and state disturbance, and substantially increase standby power consumption and information instability. The 1D-1R devices are used to suppress sneak-path currents, and perform much better than 1R devices in an array architecture (potential 1 Gbit array support in 10% readout-margin at 1V read). From **Figure 3a** and **b**, it can be calculated that the switching energies to achieve at least a one-order-of-magnitude change in resistance in the 1D-1R architecture are about 0.01 pJ for SET and 1.54 nJ for RESET operations. However, due to the suppression of sneak-path current, the standby power during a 1 V read operation can be dramatically reduced in 1D-1R devices (1 pW) as compared to 1R devices (1 μW, due to 1R nonpolar switching behaviors) [73]. Minimizing the total power consumption due to sneak-path current is as crucial as

**Figure 3.** AC pulse mapping contour plots of current-change ratio by modulating pulse height and pulse width to demonstrate synaptic behaviors in 1D-1R architectures: (a) SET (S) and (b) RESET (R) mapping results of 1D-1R device. (c) and (e) Long-term potentiation (LTP) and (d) and (f) long-term depression (LTD) using the identical pulse method as a function of pulse width. For the identical pulse method, pulse height and pulse width are fixed. For LTP, the pulse height modulation changes from 11 to 17 V in 0.3 V increments for each loop, and pulse widths are fixed at 10 μs. The mapping results of using the identical pulse method for LTP are show in (e). By selection of final states (after 20 pulses), the conductance change is highly dependent on the pulse height. For LTD, the pulse height modulation changes from 4 to 10 V in 0.3 V increments for each loop, and pulse widths are fixed at 10 μs. The mapping results (f) are similar and the conductance change for LTD is also highly dependent on the pulse height rather than pulse width. (g) and (h) show the LTP and LTD using the non-identical pulse method as a function of pulse width, respectively. For the non-identical pulse method, pulse height modulation changes continuously from 4 to 10 V in 0.3 V increments (for a total of 21 steps) for LTP, and changes continuously from 11 to 17 V in 0.3 V increments (for a total of 21 steps) for LTD. The initial states for LTP and LTD mapping are determined by fixed DC conditions: a 17 V single sweep for HRS and a 10V double-sweep for LRS, respectively. "S" and "R" denote the increment/decrement of current state changes after applying the AC pulse (defined as Log10 (In/Initial), where In/IInitial is current ratio measured at 1 V after/before the pulse is applied). Figure reprinted by [19].

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic...

http://dx.doi.org/10.5772/intechopen.68530

235

Most importantly, the pulse mapping results not only demonstrate the potential for multilevel programming by properly designing the pulse waveforms for SET and RESET operations, but also demonstrate the potential to realize biological synaptic behaviors. **Figure 3c**–**h**demonstrate

reducing the synaptic dissipation.

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic... http://dx.doi.org/10.5772/intechopen.68530 235

SiO*<sup>x</sup>*

erties of known SiO*<sup>x</sup>*

234 Memristor and Memristive Neural Networks

ductive (SiH)2

is lost from (SiH)2

to form the fixed positive charged H<sup>3</sup>

as being initiated by electron injection into H3

switching model can thus be written as (SiH)<sup>2</sup>

production for future device characterizations [72].


is similar to models used to describe stress-induced leakage current and breakdown in SiO*<sup>x</sup>* materials, where defect concentration increases as a result of electrical stress to the point where percolation pathways capable of conducting appreciable current (>1 uA) are formed [59]. Incorporating known proton exchange reactions that can dramatically alter the conductivity of specific defects further leads to a model where the LRS has a large concentration of conductive defects within the switching region, and, conversely, when the device is programmed to the HRS, most of the defects are converted to their nonconductive form. The electrically conductive hydrogen bridge (Si-H-Si) is viewed as the most likely defect responsible for the LRS due to the location of its energy levels relative to the oxide conduction band and its small effective bandgap energy [59, 60]. Adding a proton to Si-H-Si forms the noncon-

understood electrochemical reactions that could enable localized switching without incorporating ion diffusion or drift mechanisms into the model. The SET transition voltage from HRS to LRS occurs at ~2.5 V in the I-V response, and is very near the activation energy for proton desorption from SiH (~2.5 eV), thus making the defect transformation from (SiH)2 to Si-H-Si a logical assignment for the SET transition [59, 60]. In this model, the proton that

O+

chemical reaction with Si-H-Si to reform (SiH)2 [59, 60]. The localized proton exchange

voltage drop of ~2.5 V across the switching is required to drive the reversible reaction. The RS model not only provides insights into multilevel operational characteristics but also implies a possible biomimetic chemical reaction similar to reactive oxygen species (ROS-like)

**Figure 3a**–**h** show contour plots of the current-change ratio achieved by modulating the AC pulse height and pulse width applied to 1D-1R devices for both SET and RESET switching events, leading to optimized waveform designs for a biological synaptic device. The current-change ratio is defined as log10 (IFINAL/IINITIAL), where IINITIAL and IFINAL are the currents measured at 1 V before and after applying the programing waveform, respectively. The SET/RESET sweeps from same initial resistance state (precondition programming) is to eliminate the accumulating SET/RESET effect after each cycle. One can observe by inspecting the contour lines in **Figure 3** that when larger pulse heights (higher voltages) are applied to the device, shorter pulse widths are needed to achieve a similar current-change ratio. In general, we find that a single 1R device operates at higher speed and requires lower programming voltages as compared to a 1D-1R device. The higher operating voltages and lower operating speed of the integrated 1D-1R device may result from higher parasitic resistance in the Si electrodes, their contacts and the diode, as well as higher parasitic

defect and proton desorption from (SiH)2

reacts electrochemically with (SiOH)2

O+

defects has identified a plausible model for the conductive filament that

reforms Si-H-Si, which are well-

, which is simply chemisorbed H2

=O-H3 O+

that induces proton release and electro-

defect. The transition from LRS to HRS is modeled

+ (SiOH)2 ↔ Si-H-Si + Si2

O,

, where a

**Figure 3.** AC pulse mapping contour plots of current-change ratio by modulating pulse height and pulse width to demonstrate synaptic behaviors in 1D-1R architectures: (a) SET (S) and (b) RESET (R) mapping results of 1D-1R device. (c) and (e) Long-term potentiation (LTP) and (d) and (f) long-term depression (LTD) using the identical pulse method as a function of pulse width. For the identical pulse method, pulse height and pulse width are fixed. For LTP, the pulse height modulation changes from 11 to 17 V in 0.3 V increments for each loop, and pulse widths are fixed at 10 μs. The mapping results of using the identical pulse method for LTP are show in (e). By selection of final states (after 20 pulses), the conductance change is highly dependent on the pulse height. For LTD, the pulse height modulation changes from 4 to 10 V in 0.3 V increments for each loop, and pulse widths are fixed at 10 μs. The mapping results (f) are similar and the conductance change for LTD is also highly dependent on the pulse height rather than pulse width. (g) and (h) show the LTP and LTD using the non-identical pulse method as a function of pulse width, respectively. For the non-identical pulse method, pulse height modulation changes continuously from 4 to 10 V in 0.3 V increments (for a total of 21 steps) for LTP, and changes continuously from 11 to 17 V in 0.3 V increments (for a total of 21 steps) for LTD. The initial states for LTP and LTD mapping are determined by fixed DC conditions: a 17 V single sweep for HRS and a 10V double-sweep for LRS, respectively. "S" and "R" denote the increment/decrement of current state changes after applying the AC pulse (defined as Log10 (In/Initial), where In/IInitial is current ratio measured at 1 V after/before the pulse is applied). Figure reprinted by [19].

capacitance in the diode, all of which can act to degrade the pulse mapping results shown in **Figure 3a** and **b**. It should be noted that current sneak-path issues in arrays and writing disturbance of 1R devices would cause misread problems and state disturbance, and substantially increase standby power consumption and information instability. The 1D-1R devices are used to suppress sneak-path currents, and perform much better than 1R devices in an array architecture (potential 1 Gbit array support in 10% readout-margin at 1V read). From **Figure 3a** and **b**, it can be calculated that the switching energies to achieve at least a one-order-of-magnitude change in resistance in the 1D-1R architecture are about 0.01 pJ for SET and 1.54 nJ for RESET operations. However, due to the suppression of sneak-path current, the standby power during a 1 V read operation can be dramatically reduced in 1D-1R devices (1 pW) as compared to 1R devices (1 μW, due to 1R nonpolar switching behaviors) [73]. Minimizing the total power consumption due to sneak-path current is as crucial as reducing the synaptic dissipation.

Most importantly, the pulse mapping results not only demonstrate the potential for multilevel programming by properly designing the pulse waveforms for SET and RESET operations, but also demonstrate the potential to realize biological synaptic behaviors. **Figure 3c**–**h**demonstrate the optimization waveform design for biological synaptic behaviors in 1D-1R SiO*<sup>x</sup>* -based resistive switching memories. The long-term potentiation (LTP) and long-term depression (LTD) are a long-lasting enhancement/reduction in signal transmission between two neurons (similar with long-lasting conductance increase/decrease between HRS and LRS for resistive-type memory devices), which can be realized by designing the SET and RESET pulse waveform to use either identical (fixed pulse width and pulse height, as shown in **Figure 3c**–**f**) or nonidentical (variable pulse width or pulse height, as shown in **Figure 3g** and **h**) pulsing techniques. The trade-offs between high dynamic range and gradual multilevel programming performance (**Figure 3e**–**h**) needed to be considered, and it was found that the nonidentical pulse waveform method may have the advantages (larger than identical pulse waveform method). Although nonidentical pulsing might require a more complex neuromorphic circuit, our results show that this approach enables more efficient programming to target states while maintaining a larger dynamic range (**Figure 3g**–**h**). The use of nonidentical pulse heights ranging from 4 to 10 V in 0.3 V increments (for LTP) and ranging from 11 to 17 V in 0.3 V decrements (for LTD) allow the dynamic range to be mapped for pulse widths ranging from 100 ns to 1 ms, thereby realizing biological synapse behaviors in the SiO*<sup>x</sup>* -based 1D-1R architecture (**Figure 3g**–**h**). The switching energy is defined as *I* × *V* × *δt*, where *δt* is the pulse width. For *δt* = 100 ns, the smallest switching energies are ~6 and ~130 pJ for LTP and LTD, respectively. The larger energy for LTD is mainly due to the lower resistance of the LRS (~93 kΩ) compared to the HRS (~260 MΩ), which results in higher switching current (118.28 μA) for the RESET process than for the SET process (15.38 nA). In order to minimize synaptic energy consumption all three components programming current (~nA level switching), pulse amplitude (<1 V) and programming time (<10 ns)—need to be minimized. In SiO*<sup>x</sup>* -based ReRAM and in other material systems, an exponential voltage–time relationship is commonly observed. A small increase in programming voltage will decrease programming time exponentially, as shown in **Figure 3a**. For RESET process (both 1R and 1D-1R structures, **Figure 3b**), the process integration may result in certain level of distortion (parasitic resistance/capacitance and possible parasitic depletion region capacitance from 1D) to affect the pulse mapping results. Hence, low programming energy is obtained by minimizing the programming time (traded off by increasing the pulse amplitude slightly) for ReRAM. Further decreases in synaptic energy consumption during the switching process to fJ levels will be challenging but important to build very large-scale systems (the designed pulse waveform optimization and generation is in process).

detail with the aid of the electron energy band diagrams shown in **Figure 4b**, which were constructed using the thermodynamic and switching charge-state energy levels reported by Blochl in 2000 [74]. The ideal energy band diagrams in **Figure 4b** represent only a single electron pathway through the memory device, whereas in reality there are likely many such percolation pathways in parallel. The SET transition is modeled as being the result of trap-

assisted tunneling can only occur when the bias across the switching region is ≥2.6 V, which is

voltage of ~2.5 V in the *I-V* response [59, 60]. The RESET transition is modeled as being the

Joule heating due to large current flow through the filament) that stimulates proton release

grams shown in **Figure 4b** are found to be consistent with measured electron energy barriers

decrement voltage steps (0.1, 0.2, and 0.3 V) by non-identical pulse form. For the non-identical pulse method, pulse height modulation changes continuously from 4 V to 10 V for LTP, and changes continuously from 11 to 17 V for LTD. Pulse width is fixed at 10 μs in both cases. (b) Energy band diagrams: For HRS and SET process, showing theoretical

and trap-assisted-tunneling SET transition (green arrow). Barrier height to electron transport is *φ* ~ 0.8 eV. For the LRS

Fowler-Nordheim tunneling RESET transition (red arrow). (c–d) A pulse waveform design using the non-identical pulse method for demonstration of spike-timing-dependent plasticity (STDP) as a function of spike pulse width intervals. For the potentiation of conductance strength change, the overall pulse waveform (pulse width fixed at 10 μs in this case) based on the delay of spike timing between neurons is shown in (c). Similarly, for the depression of conductance strength change, the overall pulse waveform (pulse width fixed at 10 μs in this case) based on the delay of spike timing between neurons is shown in (d). (e–f) A demonstration of spike-timing-dependent plasticity (STDP) using the non-identical pulse method with different spike widths. Each colored bar shows the average of 3~5 measurements. (e) Emphasizes potentiation direction of STDP with positive delta time (45° tilted). (f) Emphasizes depression direction of STDP with negative delta time (225° tilted). The definition of conductance change is as Log10 (In/Initial), where In/IInitial is current ratio

O+

to form conductive Si-H-Si and H3

Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic...

and (SiOH)2

defects (a voltage-triggered mechanism, due to

defect and compares well with the observed minimum SET

O+


*GAP*, theoretical bandgap of Si-H-Si defects outside the gap region,

energy level, switching region of length *l*

*SW*, and

O+

http://dx.doi.org/10.5772/intechopen.68530

defect (possibly current-induced

(**Figure 2f**) [60]. The band dia-

desorption and reaction

(**Figure 2f**). Trap-

237

assisted electron tunneling through (SiH)2

with absorbed water (SiOH)2

the effective bandgap of the (SiH)<sup>2</sup>

**Figure 4.** Demonstration of a SiOx

bandgap of (SiH)2

of H+

less current flow in the initial stage of SET process) that stimulates H<sup>+</sup>

[60] and electroluminescence results reported for similar devices [62].

result of Fowler-Nordheim electron tunneling into the H3

defect within gap region of length *l*

measured at 1 V after/before the pulse is applied. Figure reprinted by [19].

and RESET process, showing theoretical bandgap of Si-H-Si, H3

and electrochemical reactions to reform (SiH)2

Such flexible artificial control built with synaptic devices could provide a suitable platform for a broad range of computing applications, as shown **Figure 4**. Some of the advantages that SiO*<sup>x</sup>* -based synaptic devices provide over other resistive switching materials include a higher dynamic range (~104 ) [57] and the potential to achieve as many as 10–60 multilevel states (depend on the stability) in both LTP and LTD by changing the increment/decrement of the voltage step, as shown in **Figure 4a**. These advantages may arise as the result of there being a large number of defects within the switching region of the memory device. Switching is modeled as a change in conductivity of a group of defects within the switching region. In this framework, defects are not created or destroyed, but are simply driven between conductive and nonconductive forms by proton exchange reactions that are known to occur in SiO*<sup>x</sup>* materials (**Figure 2f**) [60]. The SET and RESET switching transitions can be described in more detail with the aid of the electron energy band diagrams shown in **Figure 4b**, which were constructed using the thermodynamic and switching charge-state energy levels reported by Blochl in 2000 [74]. The ideal energy band diagrams in **Figure 4b** represent only a single electron pathway through the memory device, whereas in reality there are likely many such percolation pathways in parallel. The SET transition is modeled as being the result of trapassisted electron tunneling through (SiH)2 defects (a voltage-triggered mechanism, due to less current flow in the initial stage of SET process) that stimulates H<sup>+</sup> desorption and reaction of H+ with absorbed water (SiOH)2 to form conductive Si-H-Si and H3 O+ (**Figure 2f**). Trapassisted tunneling can only occur when the bias across the switching region is ≥2.6 V, which is the effective bandgap of the (SiH)<sup>2</sup> defect and compares well with the observed minimum SET voltage of ~2.5 V in the *I-V* response [59, 60]. The RESET transition is modeled as being the result of Fowler-Nordheim electron tunneling into the H3 O+ defect (possibly current-induced Joule heating due to large current flow through the filament) that stimulates proton release and electrochemical reactions to reform (SiH)2 and (SiOH)2 (**Figure 2f**) [60]. The band diagrams shown in **Figure 4b** are found to be consistent with measured electron energy barriers [60] and electroluminescence results reported for similar devices [62].

the optimization waveform design for biological synaptic behaviors in 1D-1R SiO*<sup>x</sup>*

realizing biological synapse behaviors in the SiO*<sup>x</sup>*

(<10 ns)—need to be minimized. In SiO*<sup>x</sup>*

236 Memristor and Memristive Neural Networks

that SiO*<sup>x</sup>*

higher dynamic range (~104

tive switching memories. The long-term potentiation (LTP) and long-term depression (LTD) are a long-lasting enhancement/reduction in signal transmission between two neurons (similar with long-lasting conductance increase/decrease between HRS and LRS for resistive-type memory devices), which can be realized by designing the SET and RESET pulse waveform to use either identical (fixed pulse width and pulse height, as shown in **Figure 3c**–**f**) or nonidentical (variable pulse width or pulse height, as shown in **Figure 3g** and **h**) pulsing techniques. The trade-offs between high dynamic range and gradual multilevel programming performance (**Figure 3e**–**h**) needed to be considered, and it was found that the nonidentical pulse waveform method may have the advantages (larger than identical pulse waveform method). Although nonidentical pulsing might require a more complex neuromorphic circuit, our results show that this approach enables more efficient programming to target states while maintaining a larger dynamic range (**Figure 3g**–**h**). The use of nonidentical pulse heights ranging from 4 to 10 V in 0.3 V increments (for LTP) and ranging from 11 to 17 V in 0.3 V decrements (for LTD) allow the dynamic range to be mapped for pulse widths ranging from 100 ns to 1 ms, thereby

switching energy is defined as *I* × *V* × *δt*, where *δt* is the pulse width. For *δt* = 100 ns, the smallest switching energies are ~6 and ~130 pJ for LTP and LTD, respectively. The larger energy for LTD is mainly due to the lower resistance of the LRS (~93 kΩ) compared to the HRS (~260 MΩ), which results in higher switching current (118.28 μA) for the RESET process than for the SET process (15.38 nA). In order to minimize synaptic energy consumption all three components programming current (~nA level switching), pulse amplitude (<1 V) and programming time

nential voltage–time relationship is commonly observed. A small increase in programming voltage will decrease programming time exponentially, as shown in **Figure 3a**. For RESET process (both 1R and 1D-1R structures, **Figure 3b**), the process integration may result in certain level of distortion (parasitic resistance/capacitance and possible parasitic depletion region capacitance from 1D) to affect the pulse mapping results. Hence, low programming energy is obtained by minimizing the programming time (traded off by increasing the pulse amplitude slightly) for ReRAM. Further decreases in synaptic energy consumption during the switching process to fJ levels will be challenging but important to build very large-scale systems (the

Such flexible artificial control built with synaptic devices could provide a suitable platform for a broad range of computing applications, as shown **Figure 4**. Some of the advantages

states (depend on the stability) in both LTP and LTD by changing the increment/decrement of the voltage step, as shown in **Figure 4a**. These advantages may arise as the result of there being a large number of defects within the switching region of the memory device. Switching is modeled as a change in conductivity of a group of defects within the switching region. In this framework, defects are not created or destroyed, but are simply driven between conductive and nonconductive forms by proton exchange reactions that are known to occur in SiO*<sup>x</sup>* materials (**Figure 2f**) [60]. The SET and RESET switching transitions can be described in more


) [57] and the potential to achieve as many as 10–60 multilevel

designed pulse waveform optimization and generation is in process).




**Figure 4.** Demonstration of a SiOx -based synaptic device. (a) Sequential LTP/LTD behaviors as a function of increment/ decrement voltage steps (0.1, 0.2, and 0.3 V) by non-identical pulse form. For the non-identical pulse method, pulse height modulation changes continuously from 4 V to 10 V for LTP, and changes continuously from 11 to 17 V for LTD. Pulse width is fixed at 10 μs in both cases. (b) Energy band diagrams: For HRS and SET process, showing theoretical bandgap of (SiH)2 defect within gap region of length *l GAP*, theoretical bandgap of Si-H-Si defects outside the gap region, and trap-assisted-tunneling SET transition (green arrow). Barrier height to electron transport is *φ* ~ 0.8 eV. For the LRS and RESET process, showing theoretical bandgap of Si-H-Si, H3 O+ energy level, switching region of length *l SW*, and Fowler-Nordheim tunneling RESET transition (red arrow). (c–d) A pulse waveform design using the non-identical pulse method for demonstration of spike-timing-dependent plasticity (STDP) as a function of spike pulse width intervals. For the potentiation of conductance strength change, the overall pulse waveform (pulse width fixed at 10 μs in this case) based on the delay of spike timing between neurons is shown in (c). Similarly, for the depression of conductance strength change, the overall pulse waveform (pulse width fixed at 10 μs in this case) based on the delay of spike timing between neurons is shown in (d). (e–f) A demonstration of spike-timing-dependent plasticity (STDP) using the non-identical pulse method with different spike widths. Each colored bar shows the average of 3~5 measurements. (e) Emphasizes potentiation direction of STDP with positive delta time (45° tilted). (f) Emphasizes depression direction of STDP with negative delta time (225° tilted). The definition of conductance change is as Log10 (In/Initial), where In/IInitial is current ratio measured at 1 V after/before the pulse is applied. Figure reprinted by [19].

**Figure 4c**–**f** demonstrate that the SiO*<sup>x</sup>* -based 1D-1R architecture can mimic spike-timingdependent plasticity (STDP), a biological process that adjusts the strength of connections between two neurons in a synapse gap junction region that is an electrically conductive link between the pre- and postsynaptic neurons. Two pulse generator sources are used to simulate the pre- and postsynaptic neurons. This provides the pulse waveforms using the nonidentical pulse method (also used in various types of emerging memory devices or materials systems) for demonstration of STDP. By design of pre-neuron and postneuron spikes in neuromorphic circuits, the strength of the conductance change can be modulated based on the spike-timing delta (∆t) between the two neurons (**Figure 4c**–**d**). **Figure 4e**–**f** demonstrates a total of 10 different states of STDP biological behavior for depression and potentiation with *n* = 2, 4, 6, 8, 10 and as a function of spike width modulation, ranging from 100 ns to 1 ms. For example, the depression of conductance change strength can be achieved by using multistep spike heights from −4 to 0 V in the preneuron state and a single spike height fixed at 13 V in the postneuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs, as shown in **Figure 4e**–**f**. When the time delay difference is −10 × (n−1) μs, where n is an even number, the total spike waveform (postneuron spike minus preneuron spike) applied to the synapse gap junction region can adjust the conductance ratio between two neurons over the range from 10−3 to 0.1 in the depression direction (RESET process) as compared with the initial LRS conductance (**Figure 4f**). Similarly, the potentiation of conductance change strength can be achieved by using multistep spike heights from 4 to 8 V in the preneuron state and a single spike height also fixed at 13 V in the postneuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs. When the time delay difference is 10 × (n−1) μs, where n is an even number, the total spike waveform (postneuron spike minus preneuron spike) applied to the synapse gap junction region can in this case adjust the conductance ratio between neurons over the range from 103 to 0.01 in the potentiation direction (SET process) as compared with the initial HRS conductance (**Figure 4e**). It may be noted that the 1D-1R architecture not only avoids sneak-path issues and lowers standby power consumption, but also helps to realize STDP behaviors. Without the 1D rectification characteristics in reversebias polarity, the above spiking forms cannot be implemented due to the unipolar nature of the 1R device, specifically in the potentiation behaviors under negative bias. In the 1R case, an applied voltage above the RESET threshold voltage (for example, −9 V) can trigger the RESET process and induce depression behaviors instead of potentiation behaviors. Also, for depression behaviors, when the time delay difference is smaller than the spiking width, the remaining 4 V spike height in this case would not fire the synapse toward a LRS in the depression direction (see **Figure 3h**). Therefore, by carefully designing the firing pulses between neurons in the neuromorphic circuit, a biological synapse behavior can be demonstrated with 1D-1R SiO*<sup>x</sup>* -based resistive switching memories.

(IMP) has been performed by two SiO*<sup>x</sup>*

**Figure 6.** (a) Circuit for the implication scheme including two SiOx

results shown in red square. Figure reprinted by [75].

logic control.

memristors and a 5.7 kΩ standalone resistor are config-

memristor and one load resistor, with bias voltages

ured as shown in **Figure 6a**. Furthermore, three memristors connected in the circuit shown in **Figure 6b** and two steps of IMP are required to perform a NAND operation. It may be noted

and conducting currents marked out, and truth table for material implication [75]. (b) Circuit to perform NAND operation, and Truth table for NAND operation. Two steps performing NAND operation via implication with final

**Figure 5.** (a) Bio-inspired and mixed-signal information processing: hybrid CMOS/ReRAM circuits may also enable efficient analog dot-product computation, which is a key operation in artificial neural networks and many other information processing tasks. (b) A fabricated 8 × 8 artificial neural network array combined with CMOS transistors and

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The 1D-1R architecture with SiO*<sup>x</sup>* -based resistance switching devices and the structure of artificial neural networks map naturally onto hybrid CMOS/synapse circuits that can be designed on a single chip (**Figure 5**) to provide predictable results with an ultimate scaling potential of CMOS technology to the sub-10-nm level, which could possibly challenge the complexity and connectivity of the human brain.

The other topic is material implication operations by using the same device architecture in SiO*<sup>x</sup>* -based memristor (**Figures 1** and **5**). Based on our recent reports, implication operation Review of Recently Progress on Neural Electronics and Memcomputing Applications in Intrinsic... http://dx.doi.org/10.5772/intechopen.68530 239

**Figure 4c**–**f** demonstrate that the SiO*<sup>x</sup>*

238 Memristor and Memristive Neural Networks

between neurons over the range from 103


The 1D-1R architecture with SiO*<sup>x</sup>*

connectivity of the human brain.

SiO*<sup>x</sup>*

SiO*<sup>x</sup>*


to 0.01 in the potentiation direction (SET process)


dependent plasticity (STDP), a biological process that adjusts the strength of connections between two neurons in a synapse gap junction region that is an electrically conductive link between the pre- and postsynaptic neurons. Two pulse generator sources are used to simulate the pre- and postsynaptic neurons. This provides the pulse waveforms using the nonidentical pulse method (also used in various types of emerging memory devices or materials systems) for demonstration of STDP. By design of pre-neuron and postneuron spikes in neuromorphic circuits, the strength of the conductance change can be modulated based on the spike-timing delta (∆t) between the two neurons (**Figure 4c**–**d**). **Figure 4e**–**f** demonstrates a total of 10 different states of STDP biological behavior for depression and potentiation with *n* = 2, 4, 6, 8, 10 and as a function of spike width modulation, ranging from 100 ns to 1 ms. For example, the depression of conductance change strength can be achieved by using multistep spike heights from −4 to 0 V in the preneuron state and a single spike height fixed at 13 V in the postneuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs, as shown in **Figure 4e**–**f**. When the time delay difference is −10 × (n−1) μs, where n is an even number, the total spike waveform (postneuron spike minus preneuron spike) applied to the synapse gap junction region can adjust the conductance ratio between two neurons over the range from 10−3 to 0.1 in the depression direction (RESET process) as compared with the initial LRS conductance (**Figure 4f**). Similarly, the potentiation of conductance change strength can be achieved by using multistep spike heights from 4 to 8 V in the preneuron state and a single spike height also fixed at 13 V in the postneuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs. When the time delay difference is 10 × (n−1) μs, where n is an even number, the total spike waveform (postneuron spike minus preneuron spike) applied to the synapse gap junction region can in this case adjust the conductance ratio

as compared with the initial HRS conductance (**Figure 4e**). It may be noted that the 1D-1R architecture not only avoids sneak-path issues and lowers standby power consumption, but also helps to realize STDP behaviors. Without the 1D rectification characteristics in reversebias polarity, the above spiking forms cannot be implemented due to the unipolar nature of the 1R device, specifically in the potentiation behaviors under negative bias. In the 1R case, an applied voltage above the RESET threshold voltage (for example, −9 V) can trigger the RESET process and induce depression behaviors instead of potentiation behaviors. Also, for depression behaviors, when the time delay difference is smaller than the spiking width, the remaining 4 V spike height in this case would not fire the synapse toward a LRS in the depression direction (see **Figure 3h**). Therefore, by carefully designing the firing pulses between neurons in the neuromorphic circuit, a biological synapse behavior can be demonstrated with 1D-1R

ficial neural networks map naturally onto hybrid CMOS/synapse circuits that can be designed on a single chip (**Figure 5**) to provide predictable results with an ultimate scaling potential of CMOS technology to the sub-10-nm level, which could possibly challenge the complexity and

The other topic is material implication operations by using the same device architecture in


**Figure 5.** (a) Bio-inspired and mixed-signal information processing: hybrid CMOS/ReRAM circuits may also enable efficient analog dot-product computation, which is a key operation in artificial neural networks and many other information processing tasks. (b) A fabricated 8 × 8 artificial neural network array combined with CMOS transistors and logic control.

(IMP) has been performed by two SiO*<sup>x</sup>* memristors and a 5.7 kΩ standalone resistor are configured as shown in **Figure 6a**. Furthermore, three memristors connected in the circuit shown in **Figure 6b** and two steps of IMP are required to perform a NAND operation. It may be noted

**Figure 6.** (a) Circuit for the implication scheme including two SiOx memristor and one load resistor, with bias voltages and conducting currents marked out, and truth table for material implication [75]. (b) Circuit to perform NAND operation, and Truth table for NAND operation. Two steps performing NAND operation via implication with final results shown in red square. Figure reprinted by [75].

that the final logic value pNANDq is stored as the last value of memristor s, or s″ in **Figure 6b**. This row of three memristors, namely P, Q, S, can be expanded to a row consisting of more memristors all sharing the same load resistor. Implication operations can be performed on any two memristors in the row, as long as the rest of the memristors are kept unbiased. Since we are able to perform implication on one row, similarly, implication can be done on one column.

are biased on three of the four lines depending on the configuration, and the voltage applied to each line is labeled as follows, *V*bit\_up, *V*bit\_down, *V*word\_left, and *V*word\_right. The gate of each select transistor is also independently biased, to either isolate the bit lines/word lines from the implication voltages or provide that implication voltage to one particular bit line/word line.

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To perform M13 IMP M33 (negative voltage implication operation performed along bit line 3): Assuming all memristors are initialized to HRS, bias *V*bit\_up = 2 V, *V*word\_left = − 1.5 V, *V*word\_right = 0 V, *V*word\_1r, and *V*word\_3l = Vfull\_on, *V*bit\_3u = VIMP, with all other transistor gate voltages at Vfull\_off. The equivalent circuit is shown in **Figure 5a** with the path of conduction current flow marked. In **Figure 5a**–**e**, P is M13, Q is M33, and the transistor bit\_3u is used as the load resistor. The implication is a negative voltage scheme. All transistors that are biased at fully OFF states are covered by red squares, effectively keeping the voltages of irrelevant columns/rows floating; to perform M11 IMP M12 (positive voltage implication operation performed along word line 1): Assuming all memristors are initialized to HRS, Bias *V*bit\_up = 0 V, *V*bit\_down = 1.5 V, *V*word\_left = − 2 V, *V*bit\_1u, and Vbit\_2d = Vfull\_on, Vword\_1l = VIMP, with all other transistor gate voltages at Vfull\_off. This equivalent circuit is shown in **Figure 5b** with the current flow path marked. In **Figure 5b**, P is M11, Q is M12, and the transistor word\_1l is used as the load resistor. In this case, the implication uses a positive voltage scheme. As before, all transistors biased to fully OFF states (covered by red squares) effectively keep the voltages of irrelevant

In **Figures 1a** and **5a**, each memristor is placed in series with a pn diode in order to avoid current sneak-path problems. Originating from the crossbar device structure itself, the sneakpath problem has been identified and analyzed by many previous researchers [20, 76–122]. Because the bit line or word line select transistor raises the voltage across the whole bit or word, a group of memristors in the LRS may form a highly conductive path and cause misreading of certain memristors. The solution to the sneak-path problem is using a selection element together with a memory element, as shown in **Figure 5f**. Such a selection element is used to allow current conduction in one direction while suppressing current flow in the other direction. The most common selection element is a low-leakage pn diode, limiting the current flowing through the sneak paths down to reverse the bias leakage current level and reducing

In summary, we have demonstrated potentiation, depression and spike-timing-dependent

hydrogen bridge, Si-H-Si, and the RESET transition is modeled as proton release and capture

ogy has good potential for providing a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology, and represent a critical

future synthetic biological computing applications. Moreover, a logic circuit consisting of a


defect to generate the conductive

memory element were discussed, where the SET


[82–89]. The electrical results demonstrate that the technol-

columns/rows floating.

**5. Summary**

the power consumption during implication operations.

plasticity in a synaptic device built using a SiO*<sup>x</sup>*

threshold is modeled as proton desorption from the (SiH)2

resistive switching behaviors in the SiO*<sup>x</sup>*

milestone regarding the potential use of SiO2

to reform nonconductive (SiH)2

However, when we put multiple rows and columns together to form a crossbar array, several problems arise. The first issue is providing multiple voltage signals as well as a common load resistor to an arbitrary pair of memristor on the same row or column. Based on the crossbar RRAM structure, the bit-line/word-line selection transistor can serve as the common resistor. By varying the gate voltage bias of the select transistor, it can serve as an ON state switch, OFF state switch or a resistor with channel resistance of RLoad. From **Figure 6**, it is noted that four voltage signals (VP , VQ, VS , and VLoad) are required during an implication operation, two different voltages along the same bit-line/word-line. Therefore, a total of four voltage lines, each connected to all NMOS select transistor, will provide voltage signals for implication operation.

The concepts are demonstrated by a 4 × 4 memristor crossbar array (**Figure 7a** and **b**) and a circuit with an 8 × 8 memristor crossbar array. In addition to 1D-1R device arrays (**Figure 5a**), the hybrid CMOS/1D-1R device architecture shown in **Figure 5e** has been successfully demonstrated as shown in **Figure 5f** by the *I-V* resistive switching plots. Using the NMOS/PMOS transistor also fabricated on the same chip (**Figure 5e**), an implication circuit is realized using two 1D1R memory elements and a transistor. In **Figure 7a** and **b**, the design is quite different from the RRAM crossbar array architecture, the circuit consists of two rows of bit select transistors for the same column of memristors, one on the top, and one on the bottom. Similarly, there are two column word select transistors for the same row of memristors, one on the left and one on the right. This redundancy ensures two distinctive voltage signals can be applied on any pair of memristors on the same bit line/word line. The implication voltages (*V*<sup>P</sup> , *V*Q, *V*R)

**Figure 7.** (a) and (b) demonstrate 4 × 4 crossbar structure memristor arrays with select transistors to achieve a one-bit full adder function. The implication circuit performs (a) M13 IMP M33 and (b) M11 IMP M12 on a 4 × 4 crossbar structure memristor array. Blue arrows show the current flow directions, and red solid squares cover all OFF-state transistors. Voltage signals and memristor numbers are labeled.

are biased on three of the four lines depending on the configuration, and the voltage applied to each line is labeled as follows, *V*bit\_up, *V*bit\_down, *V*word\_left, and *V*word\_right. The gate of each select transistor is also independently biased, to either isolate the bit lines/word lines from the implication voltages or provide that implication voltage to one particular bit line/word line.

To perform M13 IMP M33 (negative voltage implication operation performed along bit line 3): Assuming all memristors are initialized to HRS, bias *V*bit\_up = 2 V, *V*word\_left = − 1.5 V, *V*word\_right = 0 V, *V*word\_1r, and *V*word\_3l = Vfull\_on, *V*bit\_3u = VIMP, with all other transistor gate voltages at Vfull\_off. The equivalent circuit is shown in **Figure 5a** with the path of conduction current flow marked. In **Figure 5a**–**e**, P is M13, Q is M33, and the transistor bit\_3u is used as the load resistor. The implication is a negative voltage scheme. All transistors that are biased at fully OFF states are covered by red squares, effectively keeping the voltages of irrelevant columns/rows floating; to perform M11 IMP M12 (positive voltage implication operation performed along word line 1): Assuming all memristors are initialized to HRS, Bias *V*bit\_up = 0 V, *V*bit\_down = 1.5 V, *V*word\_left = − 2 V, *V*bit\_1u, and Vbit\_2d = Vfull\_on, Vword\_1l = VIMP, with all other transistor gate voltages at Vfull\_off. This equivalent circuit is shown in **Figure 5b** with the current flow path marked. In **Figure 5b**, P is M11, Q is M12, and the transistor word\_1l is used as the load resistor. In this case, the implication uses a positive voltage scheme. As before, all transistors biased to fully OFF states (covered by red squares) effectively keep the voltages of irrelevant columns/rows floating.

In **Figures 1a** and **5a**, each memristor is placed in series with a pn diode in order to avoid current sneak-path problems. Originating from the crossbar device structure itself, the sneakpath problem has been identified and analyzed by many previous researchers [20, 76–122]. Because the bit line or word line select transistor raises the voltage across the whole bit or word, a group of memristors in the LRS may form a highly conductive path and cause misreading of certain memristors. The solution to the sneak-path problem is using a selection element together with a memory element, as shown in **Figure 5f**. Such a selection element is used to allow current conduction in one direction while suppressing current flow in the other direction. The most common selection element is a low-leakage pn diode, limiting the current flowing through the sneak paths down to reverse the bias leakage current level and reducing the power consumption during implication operations.

## **5. Summary**

that the final logic value pNANDq is stored as the last value of memristor s, or s″ in **Figure 6b**. This row of three memristors, namely P, Q, S, can be expanded to a row consisting of more memristors all sharing the same load resistor. Implication operations can be performed on any two memristors in the row, as long as the rest of the memristors are kept unbiased. Since we are able to perform implication on one row, similarly, implication can be done on one column. However, when we put multiple rows and columns together to form a crossbar array, several problems arise. The first issue is providing multiple voltage signals as well as a common load resistor to an arbitrary pair of memristor on the same row or column. Based on the crossbar RRAM structure, the bit-line/word-line selection transistor can serve as the common resistor. By varying the gate voltage bias of the select transistor, it can serve as an ON state switch, OFF state switch or a resistor with channel resistance of RLoad. From **Figure 6**, it is noted that four

ferent voltages along the same bit-line/word-line. Therefore, a total of four voltage lines, each connected to all NMOS select transistor, will provide voltage signals for implication operation. The concepts are demonstrated by a 4 × 4 memristor crossbar array (**Figure 7a** and **b**) and a circuit with an 8 × 8 memristor crossbar array. In addition to 1D-1R device arrays (**Figure 5a**), the hybrid CMOS/1D-1R device architecture shown in **Figure 5e** has been successfully demonstrated as shown in **Figure 5f** by the *I-V* resistive switching plots. Using the NMOS/PMOS transistor also fabricated on the same chip (**Figure 5e**), an implication circuit is realized using two 1D1R memory elements and a transistor. In **Figure 7a** and **b**, the design is quite different from the RRAM crossbar array architecture, the circuit consists of two rows of bit select transistors for the same column of memristors, one on the top, and one on the bottom. Similarly, there are two column word select transistors for the same row of memristors, one on the left and one on the right. This redundancy ensures two distinctive voltage signals can be applied

on any pair of memristors on the same bit line/word line. The implication voltages (*V*<sup>P</sup>

**Figure 7.** (a) and (b) demonstrate 4 × 4 crossbar structure memristor arrays with select transistors to achieve a one-bit full adder function. The implication circuit performs (a) M13 IMP M33 and (b) M11 IMP M12 on a 4 × 4 crossbar structure memristor array. Blue arrows show the current flow directions, and red solid squares cover all OFF-state transistors.

, and VLoad) are required during an implication operation, two dif-

, *V*Q, *V*R)

voltage signals (VP

240 Memristor and Memristive Neural Networks

, VQ, VS

Voltage signals and memristor numbers are labeled.

In summary, we have demonstrated potentiation, depression and spike-timing-dependent plasticity in a synaptic device built using a SiO*<sup>x</sup>* -based 1D-1R architecture. Proton-induced resistive switching behaviors in the SiO*<sup>x</sup>* memory element were discussed, where the SET threshold is modeled as proton desorption from the (SiH)2 defect to generate the conductive hydrogen bridge, Si-H-Si, and the RESET transition is modeled as proton release and capture to reform nonconductive (SiH)2 [82–89]. The electrical results demonstrate that the technology has good potential for providing a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology, and represent a critical milestone regarding the potential use of SiO2 -based resistive memory as a synaptic device in future synthetic biological computing applications. Moreover, a logic circuit consisting of a 4 × 4 array of crossbar structure memristor 1D1R memory elements and select transistors are proposed together with bidirectional implication schemes. Then a one-bit full adder is theoretically realized with a total of 48 operation steps performed on the circuit. A comparison between CMOS-enabled logic circuits and memristor-enabled circuits shows advantages in real estate and power consumption, as well as disadvantages in speed. This result suggests the memristor-enabled logic circuit is most suitable for high-speed, low-power, high-density applications. Further study is still required to make a few steps in various implication schemes as well as lower power consumption in synaptic computations.

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## **Author details**

Cheng-Chih Hsieh1 , Yao-Feng Chang1 \*, Ying-Chen Chen1 , Xiaohan Wu1 , Meiqi Guo1 , Fei Zhou1 , Sungjun Kim2 , Burt Fowler1 , Chih-Yang Lin3 , Chih-Hung Pan3 , Ting-Chang Chang3 and Jack C. Lee1

\*Address all correspondence to: yfchang@utexas.edu

1 Microelectronics Research Center, the University of Texas at Austin, Austin, TX, USA

2 Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea

3 Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan

## **References**


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4 × 4 array of crossbar structure memristor 1D1R memory elements and select transistors are proposed together with bidirectional implication schemes. Then a one-bit full adder is theoretically realized with a total of 48 operation steps performed on the circuit. A comparison between CMOS-enabled logic circuits and memristor-enabled circuits shows advantages in real estate and power consumption, as well as disadvantages in speed. This result suggests the memristor-enabled logic circuit is most suitable for high-speed, low-power, high-density applications. Further study is still required to make a few steps in various implication

\*, Ying-Chen Chen1

, Chih-Yang Lin3

1 Microelectronics Research Center, the University of Texas at Austin, Austin, TX, USA

2 Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical

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, Yao-Feng Chang1

and Jack C. Lee1

\*Address all correspondence to: yfchang@utexas.edu

, Burt Fowler1

and Computer Engineering, Seoul National University, Seoul, Korea

3 Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan

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Ting-Chang Chang3

, Sungjun Kim2

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Fei Zhou1

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**Chapter 12**

Provisional chapter

**Memristor Neural Network Design**

Memristor Neural Network Design

Anping Huang, Xinjiang Zhang, Runmiao Li and

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Neural network, a powerful learning model, has archived amazing results. However, the current Von Neumann computing system–based implementations of neural networks are suffering from memory wall and communication bottleneck problems ascribing to the Complementary Metal Oxide Semiconductor (CMOS) technology scaling down and communication gap. Memristor, a two terminal nanosolid state nonvolatile resistive switching, can provide energy-efficient neuromorphic computing with its synaptic behavior. Crossbar architecture can be used to perform neural computations because of its high density and parallel computation. Thus, neural networks based on memristor crossbar will perform better in real world applications. In this chapter, the design of different neural network architectures based on memristor is introduced, including spiking neural networks, multilayer neural networks, convolution neural networks, and recurrent neural networks. And the brief introduction, the architecture, the computing circuits, and the training algorithm of each kind of neural networks are presented by instances. The potential applications and the prospects of memristor-based

DOI: 10.5772/intechopen.69929

Keywords: memristors, neural networks, deep learning, neuromorphic computing, analog

Neural networks, composing multiple processing layers, have achieved amazing results, such as AlphaGo, DNC and WaveNet. However conventional neural networks based on Von Neumann systems have many challenges [1]. In Von Neumann computing system, the computing process and external memory are separated by a shared bus between data and program memory as shown in Figure 1, which is so called Von Neumann bottleneck. In Von Neumann computing system, a single processor has to simulate many neurons and the synapses between neurons. In addition, the bottleneck leads the energy-hungry data communication when

> © The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Anping Huang, Xinjiang Zhang, Runmiao Li

http://dx.doi.org/10.5772/intechopen.69929

neural network system are discussed.

Yu Chi

and Yu Chi

Abstract

computing

1. Introduction


Provisional chapter

## **Memristor Neural Network Design** Memristor Neural Network Design

Anping Huang, Xinjiang Zhang, Runmiao Li and Yu Chi Anping Huang, Xinjiang Zhang, Runmiao Li

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69929

#### Abstract

and Yu Chi

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10.1149/06905.0149ecst

VLSI-TSA.2015.7117558

IEDM.2014.7047013

DRC.2014.6872388

10.1109/DRC.2014.6872370

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Neural network, a powerful learning model, has archived amazing results. However, the current Von Neumann computing system–based implementations of neural networks are suffering from memory wall and communication bottleneck problems ascribing to the Complementary Metal Oxide Semiconductor (CMOS) technology scaling down and communication gap. Memristor, a two terminal nanosolid state nonvolatile resistive switching, can provide energy-efficient neuromorphic computing with its synaptic behavior. Crossbar architecture can be used to perform neural computations because of its high density and parallel computation. Thus, neural networks based on memristor crossbar will perform better in real world applications. In this chapter, the design of different neural network architectures based on memristor is introduced, including spiking neural networks, multilayer neural networks, convolution neural networks, and recurrent neural networks. And the brief introduction, the architecture, the computing circuits, and the training algorithm of each kind of neural networks are presented by instances. The potential applications and the prospects of memristor-based neural network system are discussed.

DOI: 10.5772/intechopen.69929

Keywords: memristors, neural networks, deep learning, neuromorphic computing, analog computing

#### 1. Introduction

Neural networks, composing multiple processing layers, have achieved amazing results, such as AlphaGo, DNC and WaveNet. However conventional neural networks based on Von Neumann systems have many challenges [1]. In Von Neumann computing system, the computing process and external memory are separated by a shared bus between data and program memory as shown in Figure 1, which is so called Von Neumann bottleneck. In Von Neumann computing system, a single processor has to simulate many neurons and the synapses between neurons. In addition, the bottleneck leads the energy-hungry data communication when

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

2.2. Memristor merits

2.2.1. Memristor as synapse

Figure 2. Biological neuron and synapse.

Memristor as the forth device, comparing with conventional computing system such as CPU and GPU, has many advantages. First, memristor is a two-terminal nonvolatile device, resulting in the low power consumption [7]. Second, memristor is compatible with the CMOS, and it can be integrated with higher density [4]. Third, the size of memristor is in nanoscale, such that the switching speed fast [8]. These characteristics make memristor become a promising candidate for neuromorphic computing. In recent years, many researchers have performed

Human brain can perform complex tasks such as unstructured data classification and image recognition. In human brain, excitatory and inhibitory postsynaptic potentials are delivered from presynaptic neuron to postsynaptic neuron through chemical and electrical signal at synapses, driving the change of synaptic weight, as shown in Figure 2. The synaptic weight is precisely adjusted by the ionic flow through the neurons. In neural networks, this mechanism can be simulated by memristors. There are many samples that memristor used as synapse. In

As shown in Figure 3, a memristor acts as a synapse between two CMOSs neuron, which acts as pre-/postsynaptic neurons, respectively. The input signal of presynaptic neurons reached the postsynaptic neurons through the synapse. When a presynaptic spike is triggered before a postsynaptic spike, equivalently there is a positive voltage applied on the memristor, and then

Δt ¼ tpre � tpost (3)

Memristor Neural Network Design

251

http://dx.doi.org/10.5772/intechopen.69929

various experiments in neural network with memristor for synapse and neurons.

this section, we use SNN as a sample to explain how memristor used as synapse.

the synaptic weight is increased and vice versa, which is [6] explained as

Figure 1. Von Neumann computing system bottleneck.

updating the neurons states and retrieving the synapse states, and when simulates a largescale neural networks, the massages among processors will explode [2]. These defects make the Von Neumann computing system based neural network power hungrier, low density, and slow speed. In order to overcome these defects, a novel Nano device and computing architecture need proposing. Memristor crossbar is considered to be the most promising candidate to solve these problems [3]. Memristor crossbar is a high density, power efficiency computing-inmemory architecture. Thus, this chapter presents different design paradigm of memristorbased neural networks, including spiking neural networks (SNNs), multilayer neural networks (MNNs), convolutional neural networks (CNNs), and recurrent neural networks (RNNs).

## 2. Memristor neural networks

#### 2.1. Memristor

Memristor was conceived by Leon Chua according to the symmetry of circuit theory in 1971 [4] and funded by HP lab in 2008 [5]. Memristor is a nano two-terminal nonvolatile device, with a Lissajous' IV curve. In mathematical, the model of memristor can be express as (take an example of HP memristor) [6]

$$\mathbf{i(t)} = \frac{1}{\mathbf{R\_{ON}w(t)} + \mathbf{R\_{OFF}(1 - w(t))}} \mathbf{v(t)}\tag{1}$$

$$\dot{\mathbf{u}}(\mathbf{t}) = \mathbf{G}(\boldsymbol{\varrho}(\mathbf{t})) \mathbf{v}(\mathbf{t}) \tag{2}$$

Here, w(t) stands for the normalized position of the conduction front between the O2� vacancy-rich and O2� vacancy-poor regions. The range of w(t) is from 0 to 1. G(φðtÞ) is the conductance. The conductance of memristor can be continuous changing when applied control pulse on the memristor. When the negative pulse is applied, the O2� vacancy moves to O2� vacancy-rich region, which cause the conductance decrease, and vice versa. This result is similar to the phenomenon in biological synapse, such that memristor can simulate the dynamic of synapse.

#### 2.2. Memristor merits

Memristor as the forth device, comparing with conventional computing system such as CPU and GPU, has many advantages. First, memristor is a two-terminal nonvolatile device, resulting in the low power consumption [7]. Second, memristor is compatible with the CMOS, and it can be integrated with higher density [4]. Third, the size of memristor is in nanoscale, such that the switching speed fast [8]. These characteristics make memristor become a promising candidate for neuromorphic computing. In recent years, many researchers have performed various experiments in neural network with memristor for synapse and neurons.

#### 2.2.1. Memristor as synapse

updating the neurons states and retrieving the synapse states, and when simulates a largescale neural networks, the massages among processors will explode [2]. These defects make the Von Neumann computing system based neural network power hungrier, low density, and slow speed. In order to overcome these defects, a novel Nano device and computing architecture need proposing. Memristor crossbar is considered to be the most promising candidate to solve these problems [3]. Memristor crossbar is a high density, power efficiency computing-inmemory architecture. Thus, this chapter presents different design paradigm of memristorbased neural networks, including spiking neural networks (SNNs), multilayer neural networks (MNNs), convolutional neural networks (CNNs), and recurrent neural networks (RNNs).

Memristor was conceived by Leon Chua according to the symmetry of circuit theory in 1971 [4] and funded by HP lab in 2008 [5]. Memristor is a nano two-terminal nonvolatile device, with a Lissajous' IV curve. In mathematical, the model of memristor can be express as (take an

Here, w(t) stands for the normalized position of the conduction front between the O2� vacancy-rich and O2� vacancy-poor regions. The range of w(t) is from 0 to 1. G(φðtÞ) is the conductance. The conductance of memristor can be continuous changing when applied control pulse on the memristor. When the negative pulse is applied, the O2� vacancy moves to O2� vacancy-rich region, which cause the conductance decrease, and vice versa. This result is similar to the phenomenon in biological synapse, such that memristor can simulate the

RONw tð Þþ ROFFð Þ <sup>1</sup> � w tð Þ v tð Þ (1)

i tðÞ¼ Gð Þ φð Þt v tð Þ (2)

i tðÞ¼ <sup>1</sup>

2. Memristor neural networks

Figure 1. Von Neumann computing system bottleneck.

250 Memristor and Memristive Neural Networks

example of HP memristor) [6]

dynamic of synapse.

2.1. Memristor

Human brain can perform complex tasks such as unstructured data classification and image recognition. In human brain, excitatory and inhibitory postsynaptic potentials are delivered from presynaptic neuron to postsynaptic neuron through chemical and electrical signal at synapses, driving the change of synaptic weight, as shown in Figure 2. The synaptic weight is precisely adjusted by the ionic flow through the neurons. In neural networks, this mechanism can be simulated by memristors. There are many samples that memristor used as synapse. In this section, we use SNN as a sample to explain how memristor used as synapse.

As shown in Figure 3, a memristor acts as a synapse between two CMOSs neuron, which acts as pre-/postsynaptic neurons, respectively. The input signal of presynaptic neurons reached the postsynaptic neurons through the synapse. When a presynaptic spike is triggered before a postsynaptic spike, equivalently there is a positive voltage applied on the memristor, and then the synaptic weight is increased and vice versa, which is [6] explained as

$$
\Delta t = t\_{pre} - t\_{post} \tag{3}
$$

Figure 2. Biological neuron and synapse.

Figure 3. A paradigm of memristor based synapse.

where tpreðtpostÞ is the pule weight the presynaptic neuron (postsynaptic neuron) spikes. Δt is the difference between neurons spike time. That means, when Δt > 0, the synapse weight is increased, and when Δt < 0, the synaptic weight is decreased.

In neural networks, memristor crossbar has three operations such as read, write, and training. In this section, we use a sample to illustrate how the memristor crossbar read, write and

In memristor crossbar, the conductance of a single memristor can be read individually. As shown in Figure 5, we assume that we will read the mij memristor, which is the crosspoint of ith

and bottom wires are grounded. In this situation, only the mij memristor is applied the V bias,

Similar to reading operation, the conductance of mij memristor can be written individually. We assume that we will write the mij memristor. Different amplitude and duration of writing

th bottom wires. The voltage V is applied on the ith top wire, and other top wires

th bottom wire. According to Ohm's law, the conductance

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training.

2.3.1. Read operation

Figure 4. Memristor crossbar.

2.3.2. Write operation

Figure 5. Memristor crossbar readout.

the current i can be collected on the j

of mij memristor M is caculated by M¼V/i [11].

top wires and j

#### 2.2.2. Memristor as neuron

In biology, the membrane separates the inter-cell ions and enter-cell ions. Based on the electrochemical mechanism, the potential on the sides of membrane is balanced. When the excitatory and inhibitory postsynaptic potentials are arrived, the signals through the dendrites of the neurons and the balance will be destroyed. When the potential surpasses a threshold, the neuron is fired. Emulating these neuronal mechanism, including maintaining the balance of potential, the instantaneous mechanism, and the process of neurotransmission, is the key to implement biological plausible neuromorphic computing system [9].

When a memristor is used to act as a neuron in neural networks, it is not essential that the conductance of memristor implement continuous change, instead to achieve accumulative behavior. When competent pulses applied, the neuron is fired. These pulses can change the conductance state of memristor.

#### 2.3. Memristor crossbar

Memristor crossbar consists of two perpendicular nanowire layers, which act as top electrode and bottom electrode, respectively. The memristive material is laid between two nanowire layers; as a result, memristor is formed at each crosspoint [11]. The schematic diagram of memristor crossbar is shown in Figure 4.

Memristor crossbar is suitable for large-scale neural networks implementations. First, it is high density, since crossbar can be vertical stack, and each crosspoint is a memristor. In addition, memristor is nonvolatile, nanoscale and multistate. Second, it is low power consumption, since the crossbar allow memory and computation integrating [10], and memristor is nonvolatile device with a low operation voltage. These advantage of memristor crossbar such that this architecture applied in a wide range of neural networks.

Figure 4. Memristor crossbar.

where tpreðtpostÞ is the pule weight the presynaptic neuron (postsynaptic neuron) spikes. Δt is the difference between neurons spike time. That means, when Δt > 0, the synapse weight is

In biology, the membrane separates the inter-cell ions and enter-cell ions. Based on the electrochemical mechanism, the potential on the sides of membrane is balanced. When the excitatory and inhibitory postsynaptic potentials are arrived, the signals through the dendrites of the neurons and the balance will be destroyed. When the potential surpasses a threshold, the neuron is fired. Emulating these neuronal mechanism, including maintaining the balance of potential, the instantaneous mechanism, and the process of neurotransmission, is the key to

When a memristor is used to act as a neuron in neural networks, it is not essential that the conductance of memristor implement continuous change, instead to achieve accumulative behavior. When competent pulses applied, the neuron is fired. These pulses can change the

Memristor crossbar consists of two perpendicular nanowire layers, which act as top electrode and bottom electrode, respectively. The memristive material is laid between two nanowire layers; as a result, memristor is formed at each crosspoint [11]. The schematic diagram of

Memristor crossbar is suitable for large-scale neural networks implementations. First, it is high density, since crossbar can be vertical stack, and each crosspoint is a memristor. In addition, memristor is nonvolatile, nanoscale and multistate. Second, it is low power consumption, since the crossbar allow memory and computation integrating [10], and memristor is nonvolatile device with a low operation voltage. These advantage of memristor crossbar such that this

increased, and when Δt < 0, the synaptic weight is decreased.

implement biological plausible neuromorphic computing system [9].

2.2.2. Memristor as neuron

Figure 3. A paradigm of memristor based synapse.

252 Memristor and Memristive Neural Networks

conductance state of memristor.

memristor crossbar is shown in Figure 4.

architecture applied in a wide range of neural networks.

2.3. Memristor crossbar

In neural networks, memristor crossbar has three operations such as read, write, and training. In this section, we use a sample to illustrate how the memristor crossbar read, write and training.

#### 2.3.1. Read operation

In memristor crossbar, the conductance of a single memristor can be read individually. As shown in Figure 5, we assume that we will read the mij memristor, which is the crosspoint of ith top wires and j th bottom wires. The voltage V is applied on the ith top wire, and other top wires and bottom wires are grounded. In this situation, only the mij memristor is applied the V bias, the current i can be collected on the j th bottom wire. According to Ohm's law, the conductance of mij memristor M is caculated by M¼V/i [11].

#### 2.3.2. Write operation

Similar to reading operation, the conductance of mij memristor can be written individually. We assume that we will write the mij memristor. Different amplitude and duration of writing

Figure 5. Memristor crossbar readout.

pulses will be directly applied on the target memristor. The ith top wire is applied voltage V, and the j th bottom wire is grounded. Other top wires and bottom wires are applied voltage V/2, then, only the mij memristor is applied the full voltage V, which is above the threshold and can change the conductance of target memristor. The conductance of other memristors is not changed because the voltage applied on them is 0 [12].

#### 2.3.3. Training operation

Based on the read and write operation, the memristor neural networks are trained to implement practical neural networks. We use a single-layer neural network to explain the training process of neural network. As shown in Figure 6, the relationship between input vectors U and output vectors Y can be illustrated as [12]:

$$\mathcal{Y}\_n = \mathcal{W}\_{n \times m} \times \mathcal{U}\_m \tag{4}$$

3. Design of memristor neural networks

and the instance.

3.1.1. SNN concept

mechanism [14].

3.1.2. SNN architecture

output neurons are multiple spikes, i.e., spikes trains.

by the weights for synapses that transmit these input spikes.

time of each spike is denoted as ℊ<sup>i</sup> ¼ t

neuron is expressed as

the neuron prior to the current time t (>0) is t

3.1. Spiking neural networks

This section discusses different memristor-based neural network design paradigm, including spiking neural networks (SNN), multilayer neural networks (MNN), convolutional neural networks (CNN), and recurrent neural networks (RNN). Each part of these neural networks consists of five subsections, which are the concepts, the architecture, the algorithm, the circuits,

Spiking neural network (SNN), a neural network of neurons interchange information using spikes [13], is neural network based on individual spikes [14]. SNN is a brain-like architecture. The signal in SNNs uses pulse coding rather than rate coding, and allows multiplexing of information as frequency and amplitude. In some electronic SNNs, spikes have the similar waveform shape than biological spikes, but normally in electronic systems spikes are much simpler being represented by a square digital pulse [13]. In SNN, the presence and timing of individual spikes are considered as the means of communication and neural computation. The basic idea on biology is that the more intensive the input, the earlier the spike transmission. Hence, a network of spiking neurons can be designed with n input neurons Ni whose firing times are determined through some external

In this section, we use a three-layer neural network to illustrate the structure of SNN. In this structure, as shown in Figure 7, the multilayer SNNs are fully connected feedforward networks; all neurons between two adjacent layers are connected. All the input neurons and

In this structure, neurons have a model. Spike response model describes the response of both the sending and receiving neuron to a spike. In this model, the spikes of sending neuron transmitted from presynaptic neurons via synapses to postsynaptic neurons. When all spikes arrive, a postsynaptic potential is accumulated in receiving neuron. The internal state of neuron is defined as the sum of postsynaptic potential induced by all the spikes and affected

Suppose an input neuron has N input synapses. The ith synapse transmits Gi spikes. The arrival

ðf rÞ

<sup>i</sup> . The time of the most recent output spike of

. Then the internal state of the postsynaptic

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1 <sup>i</sup> , t<sup>2</sup> <sup>i</sup> ……t g

Here, the weight matrix Wn�<sup>m</sup> represents the synaptic strengths between the two-neuron groups, which are represented by the conductance of corresponding memristors. When we train a memristor crossbar, we first assume we have a set of data. We input the training data, the synaptic weight matrix W is updated repeatedly until the difference between the output y and the target output y\* become minimum. In each repetition, W is adjusted across the gradient of the output error |y-y\*| as [12]

$$
\Delta w\_{\vec{\eta}} = \mu \left( \frac{\partial (y - y^\*)^2}{\partial w\_{\vec{\eta}}} \right) \tag{5}
$$

Here, wij is the synaptic weight in the W connecting the neuron i and j, Δwij is the change of wij during per update. μ is the training rate.

Figure 6. A single layer neural network [12].

## 3. Design of memristor neural networks

This section discusses different memristor-based neural network design paradigm, including spiking neural networks (SNN), multilayer neural networks (MNN), convolutional neural networks (CNN), and recurrent neural networks (RNN). Each part of these neural networks consists of five subsections, which are the concepts, the architecture, the algorithm, the circuits, and the instance.

#### 3.1. Spiking neural networks

## 3.1.1. SNN concept

pulses will be directly applied on the target memristor. The ith top wire is applied voltage V,

V/2, then, only the mij memristor is applied the full voltage V, which is above the threshold and can change the conductance of target memristor. The conductance of other memristors is not

Based on the read and write operation, the memristor neural networks are trained to implement practical neural networks. We use a single-layer neural network to explain the training process of neural network. As shown in Figure 6, the relationship between input vectors U and

Here, the weight matrix Wn�<sup>m</sup> represents the synaptic strengths between the two-neuron groups, which are represented by the conductance of corresponding memristors. When we train a memristor crossbar, we first assume we have a set of data. We input the training data, the synaptic weight matrix W is updated repeatedly until the difference between the output y and the target output y\* become minimum. In each repetition, W is adjusted across the

∂ðy � y�Þ

∂wij !

Here, wij is the synaptic weight in the W connecting the neuron i and j, Δwij is the change of wij

2

Δwij ¼ μ

changed because the voltage applied on them is 0 [12].

output vectors Y can be illustrated as [12]:

gradient of the output error |y-y\*| as [12]

during per update. μ is the training rate.

Figure 6. A single layer neural network [12].

th bottom wire is grounded. Other top wires and bottom wires are applied voltage

Yn ¼ Wn�<sup>m</sup> � Um (4)

(5)

and the j

2.3.3. Training operation

254 Memristor and Memristive Neural Networks

Spiking neural network (SNN), a neural network of neurons interchange information using spikes [13], is neural network based on individual spikes [14]. SNN is a brain-like architecture. The signal in SNNs uses pulse coding rather than rate coding, and allows multiplexing of information as frequency and amplitude. In some electronic SNNs, spikes have the similar waveform shape than biological spikes, but normally in electronic systems spikes are much simpler being represented by a square digital pulse [13]. In SNN, the presence and timing of individual spikes are considered as the means of communication and neural computation. The basic idea on biology is that the more intensive the input, the earlier the spike transmission. Hence, a network of spiking neurons can be designed with n input neurons Ni whose firing times are determined through some external mechanism [14].

#### 3.1.2. SNN architecture

In this section, we use a three-layer neural network to illustrate the structure of SNN. In this structure, as shown in Figure 7, the multilayer SNNs are fully connected feedforward networks; all neurons between two adjacent layers are connected. All the input neurons and output neurons are multiple spikes, i.e., spikes trains.

In this structure, neurons have a model. Spike response model describes the response of both the sending and receiving neuron to a spike. In this model, the spikes of sending neuron transmitted from presynaptic neurons via synapses to postsynaptic neurons. When all spikes arrive, a postsynaptic potential is accumulated in receiving neuron. The internal state of neuron is defined as the sum of postsynaptic potential induced by all the spikes and affected by the weights for synapses that transmit these input spikes.

Suppose an input neuron has N input synapses. The ith synapse transmits Gi spikes. The arrival time of each spike is denoted as ℊ<sup>i</sup> ¼ t 1 <sup>i</sup> , t<sup>2</sup> <sup>i</sup> ……t g <sup>i</sup> . The time of the most recent output spike of the neuron prior to the current time t (>0) is t ðf rÞ . Then the internal state of the postsynaptic neuron is expressed as

Figure 7. The architecture of SNNs.

$$\mathbf{u}(\mathbf{t}) = \sum\_{i=1}^{N} \sum\_{\substack{\mathbf{t}\_i^{(g)} \in \mathcal{G}\_i \\ \mathbf{t}\_i^{(g)} > t^{(f\tau)}}} \mathbf{t}\_i^{(g)} \epsilon\_{\mathcal{G}\_i} \mathbf{u}\left(t - \mathbf{t}\_i^{(g)}\right) + \eta(t - t^{(f\tau)}) \tag{6}$$

where wi is the weight for the ith synapse. The postsynaptic potential induced by one spike is determined by the spike response function ε(t), expressed as

$$\varepsilon(\mathbf{t}) = \begin{cases} \frac{t}{\tau} e^{1 - \frac{t}{\tau}} & \text{if } t > 0 \\ 0 & \text{if } t \le 0 \end{cases} \tag{7}$$

3.1.3. SNN algorithm

shown in Figure 9.

a postsynaptic spike as shown in Figure 8.

Figure 8. Experimentally measured STDP function on biological synapses [13].

Figure 9. Ideal STDP update function used in computational models of STDP synaptic learning [13].

Spike-Timing Dependent Plasticity (STDP) is the synapse strength changing mechanism according to the precise timing of individual pre- and/or postsynaptic spikes. As illustrate in Section 2, the sign of the difference between the pre-/postsynaptic neurons times determines the synaptic weight whether increased. STDP learning in biology is inherently asynchronous and online which means that synaptic incremental update occurs while neurons and synapses transmit spikes and perform computations. In experiment, the synaptic strength is a function of relative timing between the arrival time of a presynaptic spike and the time of generation of

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Although the data show stochasticity, we can infer an underlying interpolated function as

In additional to the model of postsynaptic neuron, SNN has a model, too. For convenience, we assume that the layers are numbered backwards starting from the output layer numbered as layer 1 to the input layer. Every two neurons in adjacent layers connected by K synapses with different transmit delays and weights. The delay of the kth synapse is denoted as d<sup>k</sup> .

We assume that there are Nlþ<sup>1</sup> neurons in layer l þ 1 and neuron i, belongs to the layer l þ 1, has emitted a spike train composed of Fi spikes, the times of firing are denoted Fi ¼ ti, the time of the ti spike which through the kth synapse arrive at postsynaptic neuron j which is in layer l is ti <sup>þ</sup> dk . At time t, the internal state of the jth postsynaptic neuron in layer l can be expressed by

$$u\_{\boldsymbol{f}}(\mathbf{t}) = \sum\_{i=1}^{N\_{l+1}} \sum\_{k=1}^{K} \sum\_{\substack{\mathbf{t}\_i^{(f)} \ c \mathcal{F}\_i \\ \mathbf{t}\_i^{(f)} + d^k > t\_{\boldsymbol{f}}^{(f\_r)} + R\_d}} \boldsymbol{t}\_i^{(f)} \boldsymbol{c}\_{\boldsymbol{f}} \boldsymbol{\varepsilon} \left(\mathbf{t} - \mathbf{t}\_i^{(f)} - \mathbf{d}^k\right) + \eta (\mathbf{t} - \mathbf{t}\_{\boldsymbol{f}}^{(f\_r)}) \tag{8}$$

where w<sup>k</sup> ij is the weight of the kth synapse between presynaptic neuron i and postsynaptic neuron j; t ðf <sup>r</sup>Þ <sup>j</sup> is the time of the most recent output spike for neuron j prior to the current time t [15].

#### 3.1.3. SNN algorithm

u tðÞ¼ <sup>X</sup> N

Figure 7. The architecture of SNNs.

256 Memristor and Memristive Neural Networks

ti <sup>þ</sup> dk

where w<sup>k</sup>

j; t ðf <sup>r</sup>Þ ujðÞ¼ <sup>t</sup> <sup>X</sup> Nlþ<sup>1</sup>

i¼1

X K

X

t ð Þf <sup>i</sup> <sup>þ</sup> dk <sup>&</sup>gt; <sup>t</sup>

k¼1

i¼1

determined by the spike response function ε(t), expressed as

X

t ð Þg <sup>i</sup> Eℊ<sup>i</sup>

εðÞ¼ t

wiε t � t

<sup>τ</sup> if t > 0 0 if t ≤ 0

where wi is the weight for the ith synapse. The postsynaptic potential induced by one spike is

In additional to the model of postsynaptic neuron, SNN has a model, too. For convenience, we assume that the layers are numbered backwards starting from the output layer numbered as layer 1 to the input layer. Every two neurons in adjacent layers connected by K synapses with

We assume that there are Nlþ<sup>1</sup> neurons in layer l þ 1 and neuron i, belongs to the layer l þ 1, has emitted a spike train composed of Fi spikes, the times of firing are denoted Fi ¼ ti, the time of the ti spike which through the kth synapse arrive at postsynaptic neuron j which is in layer l is

. At time t, the internal state of the jth postsynaptic neuron in layer l can be expressed by

wk ijε t � t

ij is the weight of the kth synapse between presynaptic neuron i and postsynaptic neuron

ð Þj <sup>i</sup> � dk � �

þ ηðt � t

ðf <sup>r</sup>Þ

<sup>j</sup> Þ (8)

t τ e <sup>1</sup>�<sup>t</sup>

(

different transmit delays and weights. The delay of the kth synapse is denoted as d<sup>k</sup>

t ð Þf <sup>i</sup> EF<sup>i</sup>

> ðf <sup>r</sup>Þ <sup>j</sup> þ Ra

<sup>j</sup> is the time of the most recent output spike for neuron j prior to the current time t [15].

ð Þg i � �

þ ηðt � t

ðf rÞ

Þ (6)

.

(7)

t ð Þg <sup>i</sup> > t ðf rÞ Spike-Timing Dependent Plasticity (STDP) is the synapse strength changing mechanism according to the precise timing of individual pre- and/or postsynaptic spikes. As illustrate in Section 2, the sign of the difference between the pre-/postsynaptic neurons times determines the synaptic weight whether increased. STDP learning in biology is inherently asynchronous and online which means that synaptic incremental update occurs while neurons and synapses transmit spikes and perform computations. In experiment, the synaptic strength is a function of relative timing between the arrival time of a presynaptic spike and the time of generation of a postsynaptic spike as shown in Figure 8.

Although the data show stochasticity, we can infer an underlying interpolated function as shown in Figure 9.

Figure 8. Experimentally measured STDP function on biological synapses [13].

Figure 9. Ideal STDP update function used in computational models of STDP synaptic learning [13].

$$\xi \Delta \mathbf{T} = \begin{cases} a^+ e^{-\Delta T/\tau^+} & \text{if } \Delta T > 0 \\ -a^- e^{\Delta T/\tau^-} & \text{if } \Delta T < 0 \end{cases} \tag{9}$$

A and B are the parameters which depend upon the memristor material, thickness, size, and it

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In this section, we verify the STDP properties of the memristor-based synapses. Figure 11 is the proposed spike shape, which is similar to the biological spikes. Figure 12 shows the STDP curves produced by the proposed spike shape. In Figure 12, the vertical axis shows the average

Figure 11. Proposed spike shape used for processing and learning purposed [17].

Figure 12. Simulated curve using proposed spike shape [17].

fabrication method.

#### 3.1.4. SNN circuits

SNN with three layers of neurons and two fully connected inter-layer meshes of memristors is shown in Figure 10. The neuron layers are fabricated with CMOS devices, and the inter-layer meshes of memristors are made with nanowires on the top of a CMOS substrate [16]. In Figure 10, triangles represent the neuron soma, being the flat side its input(dendrites) and the sharp side the output (axon). Dark rectangles are memristors, representing each one synaptic junction. Each neuron controls the voltage at its input and output nodes.

In this SNN circuit, the CMOS-based spiking neurons work basically the same as conventional integrate-and-fire neuron, and use proposed spike shape and specific spike back-propagation. The total current of receiving neuron is given by Ohm's Law by conductance, g, of connected synapses and the voltage drop across the synapses. SNN training process needs building external circuit. In external circuit, the input signals are prepared, and the output signal will be measured in the external circuit.

#### 3.1.5. SNN instances

Memristor behavior is more likely to a bidirectional exponentially grow with voltage, and many mathematical formulations can be used to simulate it. Here, we use a voltage-controlled device as a synapse, whose synaptic weight is represented by the conductance g of memristor. The function of the device is "sinh-like" in the voltage Vmem. The nano device satisfied the formulation as expressed follow

$$\frac{d\mathbf{g}}{dt} = A \sinh(V\_{mcm}) \tag{10}$$

Figure 10. Memristor crossbar based SNNs paradigm [13].

A and B are the parameters which depend upon the memristor material, thickness, size, and it fabrication method.

In this section, we verify the STDP properties of the memristor-based synapses. Figure 11 is the proposed spike shape, which is similar to the biological spikes. Figure 12 shows the STDP curves produced by the proposed spike shape. In Figure 12, the vertical axis shows the average

Figure 11. Proposed spike shape used for processing and learning purposed [17].

<sup>ξ</sup>Δ<sup>T</sup> <sup>¼</sup> <sup>a</sup>þe�ΔT=τ<sup>þ</sup>

(

junction. Each neuron controls the voltage at its input and output nodes.

3.1.4. SNN circuits

258 Memristor and Memristive Neural Networks

be measured in the external circuit.

formulation as expressed follow

Figure 10. Memristor crossbar based SNNs paradigm [13].

3.1.5. SNN instances

�a�e<sup>Δ</sup>T=τ�

SNN with three layers of neurons and two fully connected inter-layer meshes of memristors is shown in Figure 10. The neuron layers are fabricated with CMOS devices, and the inter-layer meshes of memristors are made with nanowires on the top of a CMOS substrate [16]. In Figure 10, triangles represent the neuron soma, being the flat side its input(dendrites) and the sharp side the output (axon). Dark rectangles are memristors, representing each one synaptic

In this SNN circuit, the CMOS-based spiking neurons work basically the same as conventional integrate-and-fire neuron, and use proposed spike shape and specific spike back-propagation. The total current of receiving neuron is given by Ohm's Law by conductance, g, of connected synapses and the voltage drop across the synapses. SNN training process needs building external circuit. In external circuit, the input signals are prepared, and the output signal will

Memristor behavior is more likely to a bidirectional exponentially grow with voltage, and many mathematical formulations can be used to simulate it. Here, we use a voltage-controlled device as a synapse, whose synaptic weight is represented by the conductance g of memristor. The function of the device is "sinh-like" in the voltage Vmem. The nano device satisfied the

dt <sup>¼</sup> AsinhðVmem<sup>Þ</sup> (10)

dg

if ΔT > 0

if ΔT < 0

(9)

Figure 12. Simulated curve using proposed spike shape [17].

change of memristor conductance. The horizontal axis represents the difference between preand postsynaptic spike timings Δt. Here, the default spike parameters are eV� ¼ 0:45V volt, t þ ail ¼ 11 ms, t � ail ¼ 0:3 ms. The result are provided for memristors with Vth� ≈ � 0:5 V volt. The value of parameters A and B are 2 and 4, respectively [18, 19].

<sup>ε</sup>MSE <sup>¼</sup> <sup>X</sup>

be obtained by the following equation:

wijxi, yj ¼ f zj

� �, <sup>x</sup><sup>0</sup>

i

activation function. For Eq. (3) we get

<sup>j</sup> � δ<sup>j</sup> ¼ yj � tj

network. As shown in Figure 14.

where zj <sup>¼</sup> <sup>X</sup>

where δ<sup>ð</sup>L<sup>Þ</sup>

respectively.

3.2.4. MNN circuits

∂ε ∂wij <sup>¼</sup> <sup>∂</sup><sup>ε</sup> ∂yj

� �, <sup>δ</sup><sup>j</sup> <sup>¼</sup> E y \_ <sup>j</sup>

∂yj ∂zj

∂zj ∂wij

� � \_ f zj

∂ ∈ ∂w<sup>ð</sup>k<sup>Þ</sup> ij

<sup>i</sup> are input signals, and <sup>δ</sup><sup>L</sup>

using the potential of postsynaptic V and the corresponding conductance G.

<sup>j</sup> yj � tj � �<sup>2</sup>

wij represents the weight between two layers of neurons, the neurons of the previous layer are indexed with i, and the next layer of neurons is indexed with j. The derivation of the error can

> ¼ ∈\_ yj � � \_ f zj

Moreover, it is assumed that the multilayer neural network uses sigmoid as a nonlinear

¼ x ðk�1Þ <sup>i</sup> <sup>δ</sup><sup>ð</sup>K<sup>Þ</sup>

In this section, we enumerate an example of a memristor implementation of a two-layer neural

In hybrid-circuit based neural networks [26–28], memristors are integrated into crossbar circuits to implement density-critical analog weights (i.e., synapses). In this scheme, each artificial synapse is represented by memristors, so the weight of the synapse is equal to the conductance of the memristor. For the multilayer neural network mentioned above, each weight is represented by two memristors, so that the memristor crossbar can easily account for both "excitatory" and "inhibitory" states of the synapses. The number of memristor in the hidden layer is arranged in an 8 � 1 grid array as shown in Figure 14. The value of each weight W ¼ G<sup>þ</sup> � G�, where G<sup>þ</sup> and G� is the effective conductance of each memristor. In the simplest case, neuron output x is encoded by voltages V and synaptic weight w by memristor conductance G. With virtually grounded neuron's input, the current was given by Ohm's law

The memristor crossbar combined with CMOS circuitry, which implements neuron functionality and other peripheral functions. The artificial neuron body (soma) was implemented in the circuit by an op-amp based differential adder and a voltage divider with a MOSFET controlled by the output of the summator [24]. This element executed the basic neuron functions in terms of information processing—summation and threshold. The differential summator performing <sup>y</sup> <sup>¼</sup> <sup>X</sup>wixi function is required to separate different classes of input combinations, where y is the output voltage of the summator, wi, xi – the ith input voltage and the corresponding weight

<sup>j</sup> � <sup>X</sup> i wð Þ <sup>k</sup> ji <sup>δ</sup>ð Þ <sup>k</sup> i \_ f zð Þ <sup>k</sup>�<sup>1</sup> j � �. (11)

261

� �xi <sup>¼</sup> <sup>δ</sup>jx<sup>i</sup> (12)

Memristor Neural Network Design

http://dx.doi.org/10.5772/intechopen.69929

<sup>j</sup> (13)

## 3.2. Multilayer neural networks

#### 3.2.1. MNN concepts

Multilayer neural networks, also known as multilayer perception, are the quintessential deep networks. The advantage of MNN better than the single-layer perceptron overcomes the weaknesses that the perceptron cannot classify linearly indivisible data. To realize large scale learning tasks, MNNs can perform impressively well and produce state-of-the-art results when massive computational power is available [20, 21]. Learning in multilayer neural networks (MNNs) relies on continuous updating of large matrices of synaptic weights by local rules [22, 23]. The BP algorithm is a common algorithm in local learning, which is widely used in the training of MNNs.

#### 3.2.2. MNN architecture

In MNN architecture, neurons of upper and lower layers are fully connected, no neuron connection exists between the same layer, and no cross layer connects to the neural network. As a quintessential deep network, multilayer neural network consists of an input layer, an output layer, and a hidden layer. MNN is the evolution of the single-layer perceptron. Figure 13 is a double layer neural network.

The X1, X2 may represent the inputs single, W is the value of the weight between layers, Y is the output value. For the two-layer neural network shown above, the input signal is represented as x1,… xj , xn (N represents the number of input neurons), bi is represented for bias, so the result of the signal from the input layer to the hidden layer is N11¼f(x1w<sup>11</sup> þ x2w<sup>21</sup> þ bÞ, and Y1¼f (N11w<sup>11</sup> þ N12w21þb), in which f is an activation function.

#### 3.2.3. MNN algorithm

In this section, we give a short sketch of the back-propagation technique [25, 23]. The actual output value of the neural network is denoted by yj and the ideal tag value is denoted by tj, and we can use the mean square error as an error function

Figure 13. Logic scheme of the implemented neural network with two inputs, two hidden and one output neurons [24].

$$\varepsilon \mathbf{MSE} = \sum\_{j} \left( y\_j - \mathbf{t}\_j \right)^2 \tag{11}$$

wij represents the weight between two layers of neurons, the neurons of the previous layer are indexed with i, and the next layer of neurons is indexed with j. The derivation of the error can be obtained by the following equation:

$$\frac{\partial \epsilon}{\partial w\_{i\dot{\jmath}}} = \frac{\partial \epsilon}{\partial y\_{\dot{\jmath}}} \frac{\partial y\_{\dot{\jmath}}}{\partial z\_{\dot{\jmath}}} \frac{\partial z\_{\dot{\jmath}}}{\partial w\_{i\dot{\jmath}}} = \dot{\in} \left(y\_{\dot{\jmath}}\right) \dot{f}(z\_{\dot{\jmath}}) x\_i = \delta\_{\dot{\jmath}} x\_i \tag{12}$$

where zj <sup>¼</sup> <sup>X</sup> i wijxi, yj ¼ f zj � �, <sup>δ</sup><sup>j</sup> <sup>¼</sup> E y \_ <sup>j</sup> � � \_ f zj

Moreover, it is assumed that the multilayer neural network uses sigmoid as a nonlinear activation function. For Eq. (3) we get

$$\frac{\mathfrak{d}\in}{\mathfrak{d}w\_{ij}^{(k)}} = \mathfrak{x}\_i^{(k-1)} \mathfrak{d}\_j^{(K)} \tag{13}$$

$$\text{where } \boldsymbol{\delta}\_{j}^{(L)} \equiv \boldsymbol{\delta}\_{j} = \left(\boldsymbol{y}\_{j} - \boldsymbol{t}\_{j}\right), \mathbf{x}\_{i}^{\mathsf{0}} \text{ are input signals, and } \boldsymbol{\delta}\_{j}^{L} \equiv \sum\_{i} \boldsymbol{w}\_{ji}^{(k)} \boldsymbol{\delta}\_{i}^{(k)} \dot{f}\left(\boldsymbol{z}\_{j}^{(k-1)}\right).$$

#### 3.2.4. MNN circuits

change of memristor conductance. The horizontal axis represents the difference between preand postsynaptic spike timings Δt. Here, the default spike parameters are eV� ¼ 0:45V volt,

Multilayer neural networks, also known as multilayer perception, are the quintessential deep networks. The advantage of MNN better than the single-layer perceptron overcomes the weaknesses that the perceptron cannot classify linearly indivisible data. To realize large scale learning tasks, MNNs can perform impressively well and produce state-of-the-art results when massive computational power is available [20, 21]. Learning in multilayer neural networks (MNNs) relies on continuous updating of large matrices of synaptic weights by local rules [22, 23]. The BP algorithm is a common algorithm in local learning, which is widely used in the training of MNNs.

In MNN architecture, neurons of upper and lower layers are fully connected, no neuron connection exists between the same layer, and no cross layer connects to the neural network. As a quintessential deep network, multilayer neural network consists of an input layer, an output layer, and a hidden layer. MNN is the evolution of the single-layer perceptron.

The X1, X2 may represent the inputs single, W is the value of the weight between layers, Y is the output value. For the two-layer neural network shown above, the input signal is represented as

of the signal from the input layer to the hidden layer is N11¼f(x1w<sup>11</sup> þ x2w<sup>21</sup> þ bÞ, and Y1¼f

In this section, we give a short sketch of the back-propagation technique [25, 23]. The actual output value of the neural network is denoted by yj and the ideal tag value is denoted by tj,

Figure 13. Logic scheme of the implemented neural network with two inputs, two hidden and one output neurons [24].

, xn (N represents the number of input neurons), bi is represented for bias, so the result

value of parameters A and B are 2 and 4, respectively [18, 19].

ail ¼ 0:3 ms. The result are provided for memristors with Vth� ≈ � 0:5 V volt. The

t þ

ail ¼ 11 ms, t

3.2.1. MNN concepts

3.2.2. MNN architecture

3.2.3. MNN algorithm

x1,… xj

Figure 13 is a double layer neural network.

(N11w<sup>11</sup> þ N12w21þb), in which f is an activation function.

and we can use the mean square error as an error function

�

260 Memristor and Memristive Neural Networks

3.2. Multilayer neural networks

In this section, we enumerate an example of a memristor implementation of a two-layer neural network. As shown in Figure 14.

In hybrid-circuit based neural networks [26–28], memristors are integrated into crossbar circuits to implement density-critical analog weights (i.e., synapses). In this scheme, each artificial synapse is represented by memristors, so the weight of the synapse is equal to the conductance of the memristor. For the multilayer neural network mentioned above, each weight is represented by two memristors, so that the memristor crossbar can easily account for both "excitatory" and "inhibitory" states of the synapses. The number of memristor in the hidden layer is arranged in an 8 � 1 grid array as shown in Figure 14. The value of each weight W ¼ G<sup>þ</sup> � G�, where G<sup>þ</sup> and G� is the effective conductance of each memristor. In the simplest case, neuron output x is encoded by voltages V and synaptic weight w by memristor conductance G. With virtually grounded neuron's input, the current was given by Ohm's law using the potential of postsynaptic V and the corresponding conductance G.

The memristor crossbar combined with CMOS circuitry, which implements neuron functionality and other peripheral functions. The artificial neuron body (soma) was implemented in the circuit by an op-amp based differential adder and a voltage divider with a MOSFET controlled by the output of the summator [24]. This element executed the basic neuron functions in terms of information processing—summation and threshold. The differential summator performing <sup>y</sup> <sup>¼</sup> <sup>X</sup>wixi function is required to separate different classes of input combinations, where y is the output voltage of the summator, wi, xi – the ith input voltage and the corresponding weight respectively.

Compared with traditional neural networks, such as fully connected NN, where each neuron is connected to all neurons of the prelayer via a large number of synapses,convolutional neural networks take advantages in weight sharing, which reduces the number of parameters need to be trained [29]. CNNs are inspired from visual cortex structure, where neurons are sensitive to small subregions of the input space, called receptive fields, exploiting the strong spatially local correlation present in images [35]. CNNs, exploiting the spatial structure of input images, has significantly fewer parameters than a fully connected network of a similar size are better suited

Memristor Neural Network Design

263

http://dx.doi.org/10.5772/intechopen.69929

for visual document tasks than other NN topologies such as fully connected NNs [36].

on servers with plenty of resources [37].

ation. Convolution operation can be expressed as [37]

3.3.2. CNN architectures

connected layers (Figure 15).

Figure 15. CNN block diagram.

Software implementations of artificial convolutional neural networks, which require powerhungry CPU/GPU to perform convolution operations, are at the state of the art for pattern recognition applications. While achieving high performance, CNN-based methods is based on computationally expensive sums of multiplications, which is demand much more computation and memory resources than traditional classification methods. This hinders their integration in portable devices. As a result, most CNN-based algorithms and methods have to be processed

The overall architecture of a typical CNN consists of two main parts, the feature extractor and classifier [38, 39]. The feature extractor layers composed of two types of layers convolutional layers and pooling layers. A series of convolution and pooling are stacked, followed by fully

In the feature extraction layers, each layer of the network receives an input from the immediate previous layer [39, 40]. Convolution neural networks are often used to handle image processing and recognition tasks. The image signal was processed by the input layer of the convolutional neural network and then enters the convolution layer for the convolution oper-

Figure 14. Circuit diagram of the ANN memristor-based hardware.

#### 3.2.5. MNN instance

Conclusion all the experiments, we selected the image data of the MNIST data set to train and test the two-layer neural network, with the batch size 100 to speed up calculations [28]. The initial weights were selected randomly from the uniform distribution; in the experiment, the learning rate is changed depending on the training set error, and the learning rate is only constant at a level close to 0.0035.

#### 3.3. Convolutional neural networks

#### 3.3.1. CNN concepts

Convolutional neural network is taking inspiration from the study of biology neural science. A classical architecture of convolutional neural network was first proposed by Lecun et al. [29, 30]. As a kind of deep learning neural network, several powerful applications of CNNs were reported including pattern recognition and classification, such as human face recognition [31], traffic sign recognition [32], and object recognition [33]. Recently, in the field of image classification accuracy, convolution neural network (CNN) achieved a state-of-the art result, which can classify more than a million images into 1000 different classes [29, 34, 35].

Compared with traditional neural networks, such as fully connected NN, where each neuron is connected to all neurons of the prelayer via a large number of synapses,convolutional neural networks take advantages in weight sharing, which reduces the number of parameters need to be trained [29]. CNNs are inspired from visual cortex structure, where neurons are sensitive to small subregions of the input space, called receptive fields, exploiting the strong spatially local correlation present in images [35]. CNNs, exploiting the spatial structure of input images, has significantly fewer parameters than a fully connected network of a similar size are better suited for visual document tasks than other NN topologies such as fully connected NNs [36].

Software implementations of artificial convolutional neural networks, which require powerhungry CPU/GPU to perform convolution operations, are at the state of the art for pattern recognition applications. While achieving high performance, CNN-based methods is based on computationally expensive sums of multiplications, which is demand much more computation and memory resources than traditional classification methods. This hinders their integration in portable devices. As a result, most CNN-based algorithms and methods have to be processed on servers with plenty of resources [37].

#### 3.3.2. CNN architectures

3.2.5. MNN instance

262 Memristor and Memristive Neural Networks

3.3.1. CNN concepts

constant at a level close to 0.0035.

Figure 14. Circuit diagram of the ANN memristor-based hardware.

3.3. Convolutional neural networks

Conclusion all the experiments, we selected the image data of the MNIST data set to train and test the two-layer neural network, with the batch size 100 to speed up calculations [28]. The initial weights were selected randomly from the uniform distribution; in the experiment, the learning rate is changed depending on the training set error, and the learning rate is only

Convolutional neural network is taking inspiration from the study of biology neural science. A classical architecture of convolutional neural network was first proposed by Lecun et al. [29, 30]. As a kind of deep learning neural network, several powerful applications of CNNs were reported including pattern recognition and classification, such as human face recognition [31], traffic sign recognition [32], and object recognition [33]. Recently, in the field of image classification accuracy, convolution neural network (CNN) achieved a state-of-the art result,

which can classify more than a million images into 1000 different classes [29, 34, 35].

The overall architecture of a typical CNN consists of two main parts, the feature extractor and classifier [38, 39]. The feature extractor layers composed of two types of layers convolutional layers and pooling layers. A series of convolution and pooling are stacked, followed by fully connected layers (Figure 15).

In the feature extraction layers, each layer of the network receives an input from the immediate previous layer [39, 40]. Convolution neural networks are often used to handle image processing and recognition tasks. The image signal was processed by the input layer of the convolutional neural network and then enters the convolution layer for the convolution operation. Convolution operation can be expressed as [37]

Figure 15. CNN block diagram.

$$\log(\mathbf{x}, \mathbf{y}, \mathbf{z}) = \sum\_{i=0}^{c-1} \sum\_{j=0}^{c-1} \sum\_{k=1}^{l} f(\mathbf{x} + i, \mathbf{y} + j, k) \cdot \mathbf{c}\_z(i, j, k) = \overrightarrow{f} \cdot \overrightarrow{c}\_z \tag{14}$$

∂E ∂kl ij

<sup>¼</sup> rot180ðconv<sup>2</sup> xl�<sup>1</sup>

down x<sup>l</sup>�<sup>1</sup> j � � <sup>þ</sup> <sup>b</sup><sup>l</sup>

∂E ∂k l ij

> <sup>j</sup> <sup>¼</sup> <sup>f</sup>ðβ<sup>l</sup> j

> > lþ1 j � �, 0 f ull<sup>0</sup>

<sup>j</sup> <sup>¼</sup> downðxl�<sup>1</sup>

xl

<sup>j</sup> <sup>¼</sup> <sup>f</sup> <sup>X</sup> Nin

> X i

i¼1

∂E ∂βj

<sup>¼</sup> <sup>X</sup> u;v ðδl <sup>j</sup> <sup>∘</sup> dl j

Meanwhile, it is better to provide an output map that involves a sum over several convolutions of different input maps. Generally, the input maps combined to form a given output map are typically chosen by hand. However, such combinations can be learned during training. Let αij represents the weight given to input map i when forming output map j. Then output map j is

> <sup>α</sup>ijðxl�<sup>1</sup> <sup>i</sup> � <sup>K</sup><sup>l</sup> i Þ þ bl j

By setting the αij variables equal to the softmax over a set of unconstrained weights cij, these

k

expðcijÞ

<sup>α</sup>ij <sup>¼</sup> <sup>X</sup>

!

<sup>j</sup> , rot180 k

smaller. More formally, xl

<sup>Þ</sup><sup>∘</sup> conv2ðδ<sup>l</sup>þ<sup>1</sup>

backpropagation. Defining d<sup>l</sup>

constraints can be enforced

u, <sup>v</sup> <sup>δ</sup><sup>l</sup> j � �

calculated by

where

δl <sup>j</sup> ¼ f , ðul j

∂E <sup>∂</sup>bj <sup>¼</sup> <sup>X</sup> <sup>¼</sup> <sup>X</sup> u, <sup>v</sup>

δl j � �

A subsampling layer produces down sampled versions of the input maps. If there are N input maps, then there will be exactly N output maps, although the output maps will be

function, which sum over each distinct n-by-n block in the input image so that the output image is n-times smaller along both spatial dimensions. Each output map has multiplicative bias β and an additive bias b. Since every other sample in the image

computed. The additive bias is again just the sum over the elements of the sensitivity map

generated by the current layer during the forward propagation. Therefore, the maps generated during the forward propagation should be saved, to aviod recomputing them during

uv. The multiplicative bias <sup>β</sup> will involve the original down-sampled map

j

uvðPl�<sup>1</sup>

<sup>i</sup> , rot180 δ<sup>l</sup>

j � �, 'valid'

<sup>i</sup> Þuv (17)

http://dx.doi.org/10.5772/intechopen.69929

Memristor Neural Network Design

265

� �<sup>Þ</sup> (18)

Þ, where down(�) represents a subsampling

Þuv (19)

(20)

Þ can be thrown away, the gradients of b and β can be

<sup>j</sup> Þ, then the gradient of β can be represented as

αij ¼ 1, and 0 ≤ αij ≤ 1 (21)

expðckj<sup>Þ</sup> (22)

where the vector f ! and g ! respectively represent the input and output feature map in the form of 3D matrix; Cz! is one convolution kernel with the size of C � C; and i is the channel number of the convolution kernel and the input feature map.

This operation could extract different features of input images when using different convolutional kernels [29]. The input image signal will have dot product operation with kernel, and through the nonlinear transformation, the final output feature map. Then will be the subsampling process. Nonlinear neuron will be operated attached after the convolution kernel. And then, pooling computation is operated after the nonlinear neurons in order to reduce the data amount and keep the local invariance. A typical pooling unit computes the maximum of a local patch of units in one feature map (or in a few feature maps) [41]. Fully connected layers are the final layers of the CNN that all layers are fully connected by weights [37]. A feed forward neural network is usually used as a classifier in this work because it has been shown to provide the best performance compared to neural networks [42, 43].

#### 3.3.3. CNN algorithm

In this section, the backpropagation learning algorithm for CNNs will be introduced [36]. The input of a convolution layer is the previous layer's feature maps, and the output feature map is generated by a learnable kernels and the activation function, which may combine the kernel convolutions with multiple input maps. In general, we have that

$$\mathbf{x}\_{j}^{l} = f\left(\sum\_{i \in M\_{j}} \mathbf{x}\_{i}^{l-1} \ast \mathbf{k}\_{ij}^{l} + \mathbf{b}\_{j}^{l}\right) \tag{15}$$

We can repeat the same computation for each map j in the convolutional layer, pairing it with the corresponding map in the subsampling layer:

$$\delta\_{\dot{j}} = \beta\_{\dot{j}}^{l+1} \left( f' \left( u\_{\dot{j}}^l \right) \bullet \upmu p \left( \delta\_{\dot{j}}^{l+1} \right) \right) \tag{16}$$

where up(�) denotes an up sampling operation that simply tiles each pixel in the input horizontally and vertically n times in the output if the subsampling layer subsamples by a factor of n. One possible way to implement this function efficiently is to use the Kronecker product, upðxÞ � X⨂1<sup>n</sup>�<sup>n</sup>. Since the sensitivities of a given map are known, the bias gradient can be immediately computed by simply summing over all the entries in δ<sup>l</sup> j , <sup>∂</sup><sup>E</sup> <sup>∂</sup>bj <sup>¼</sup> <sup>X</sup> u, <sup>v</sup> <sup>ð</sup>δ<sup>l</sup> j Þuv.

Finally, the gradients of the kernel weights are computed using backpropagation. Then, the gradient of a given weight is summed over all the connections that mention this weight

Memristor Neural Network Design http://dx.doi.org/10.5772/intechopen.69929 265

$$\frac{\partial E}{\partial \mathbf{k}\_{ij}^{l}} = \sum\_{u\_{\prime}v} \left(\delta\_{j}^{l}\right)\_{uv} (P\_{i}^{l-1})\_{uv} \tag{17}$$

$$\frac{\partial E}{\partial \mathbf{k}\_{ij}^{l}} = rot180(conv2\left(\mathbf{x}\_{i}^{l-1}, rot180\left(\delta\_{j}^{l}\right), 'valid'\right))\tag{18}$$

A subsampling layer produces down sampled versions of the input maps. If there are N input maps, then there will be exactly N output maps, although the output maps will be smaller. More formally, xl <sup>j</sup> <sup>¼</sup> <sup>f</sup>ðβ<sup>l</sup> j down x<sup>l</sup>�<sup>1</sup> j � � <sup>þ</sup> <sup>b</sup><sup>l</sup> j Þ, where down(�) represents a subsampling function, which sum over each distinct n-by-n block in the input image so that the output image is n-times smaller along both spatial dimensions. Each output map has multiplicative bias β and an additive bias b. Since every other sample in the image δl <sup>j</sup> ¼ f , ðul j <sup>Þ</sup><sup>∘</sup> conv2ðδ<sup>l</sup>þ<sup>1</sup> <sup>j</sup> , rot180 k lþ1 j � �, 0 f ull<sup>0</sup> Þ can be thrown away, the gradients of b and β can be computed. The additive bias is again just the sum over the elements of the sensitivity map ∂E <sup>∂</sup>bj <sup>¼</sup> <sup>X</sup> u, <sup>v</sup> <sup>δ</sup><sup>l</sup> j � � uv. The multiplicative bias <sup>β</sup> will involve the original down-sampled map generated by the current layer during the forward propagation. Therefore, the maps generated during the forward propagation should be saved, to aviod recomputing them during backpropagation. Defining d<sup>l</sup> <sup>j</sup> <sup>¼</sup> downðxl�<sup>1</sup> <sup>j</sup> Þ, then the gradient of β can be represented as

$$\frac{\partial E}{\partial \beta\_j} = \sum\_{u,v} (\delta^l\_j \bullet d^l\_j)\_{uv} \tag{19}$$

Meanwhile, it is better to provide an output map that involves a sum over several convolutions of different input maps. Generally, the input maps combined to form a given output map are typically chosen by hand. However, such combinations can be learned during training. Let αij represents the weight given to input map i when forming output map j. Then output map j is calculated by

$$\mathbf{x}\_{j}^{l} = f\left(\sum\_{i=1}^{N\_{in}} \alpha\_{i\bar{\jmath}} (\mathbf{x}\_{i}^{l-1} \* \mathbf{K}\_{i}^{l}) + b\_{j}^{l}\right) \tag{20}$$

where

g x, <sup>y</sup>, <sup>z</sup> � � <sup>¼</sup> <sup>X</sup><sup>c</sup>�<sup>1</sup>

of the convolution kernel and the input feature map.

where the vector f

of 3D matrix; Cz!

works [42, 43].

3.3.3. CNN algorithm

! and g

264 Memristor and Memristive Neural Networks

i¼0

convolutions with multiple input maps. In general, we have that

the corresponding map in the subsampling layer:

xl

δl <sup>j</sup> <sup>¼</sup> <sup>β</sup><sup>l</sup>þ<sup>1</sup> <sup>j</sup> f , ul j � �

immediately computed by simply summing over all the entries in δ<sup>l</sup>

<sup>j</sup> <sup>¼</sup> <sup>f</sup> <sup>X</sup> i∈ Mj

0 @

Xc�1 j¼0

X l

f xð þ i, y þ j, kÞ � czð Þ¼ i, j, k f

is one convolution kernel with the size of C � C; and i is the channel number

! respectively represent the input and output feature map in the form

! � cz

! (14)

k¼1

This operation could extract different features of input images when using different convolutional kernels [29]. The input image signal will have dot product operation with kernel, and through the nonlinear transformation, the final output feature map. Then will be the subsampling process. Nonlinear neuron will be operated attached after the convolution kernel. And then, pooling computation is operated after the nonlinear neurons in order to reduce the data amount and keep the local invariance. A typical pooling unit computes the maximum of a local patch of units in one feature map (or in a few feature maps) [41]. Fully connected layers are the final layers of the CNN that all layers are fully connected by weights [37]. A feed forward neural network is usually used as a classifier in this work because it has been shown to provide the best performance compared to neural net-

In this section, the backpropagation learning algorithm for CNNs will be introduced [36]. The input of a convolution layer is the previous layer's feature maps, and the output feature map is generated by a learnable kernels and the activation function, which may combine the kernel

> xl�<sup>1</sup> <sup>i</sup> � k l ij <sup>þ</sup> <sup>b</sup><sup>l</sup> j

We can repeat the same computation for each map j in the convolutional layer, pairing it with

where up(�) denotes an up sampling operation that simply tiles each pixel in the input horizontally and vertically n times in the output if the subsampling layer subsamples by a factor of n. One possible way to implement this function efficiently is to use the Kronecker product, upðxÞ � X⨂1<sup>n</sup>�<sup>n</sup>. Since the sensitivities of a given map are known, the bias gradient can be

Finally, the gradients of the kernel weights are computed using backpropagation. Then, the gradient of a given weight is summed over all the connections that mention this weight

∘ up δ<sup>l</sup>þ<sup>1</sup> j

� � � �

1

A (15)

u, <sup>v</sup> <sup>ð</sup>δ<sup>l</sup> j Þuv.

j , <sup>∂</sup><sup>E</sup> <sup>∂</sup>bj <sup>¼</sup> <sup>X</sup> (16)

$$\sum\_{i} \alpha\_{i\backslash} = 1, \text{ and } 0 \le \alpha\_{i\backslash} \le 1 \tag{21}$$

By setting the αij variables equal to the softmax over a set of unconstrained weights cij, these constraints can be enforced

$$\alpha\_{i\circ} = \frac{\exp(c\_{i\circ})}{\sum\_{k} \exp(c\_{k\circ})} \tag{22}$$

Since each set of weights cij for fixed j are independent of all other such sets for any other j, only the updates of a single map need considering and the subscript j can be dropped. Each map is updated in the same way, except with different j indices. The derivative of α<sup>k</sup> with respect to the α<sup>i</sup> variables at layer is the derivative of the softmax function is given by

$$\frac{\partial \alpha\_k}{\partial \mathbf{c}\_i} = \delta\_{ki}\alpha\_i - \alpha\_i\alpha\_k \tag{23}$$

∂ E fn ∂ci

memristor crossbar structure is shown in Figure 16.

the output voltage and implements the sigmoid activation function.

3.3.4. CNN circuits

f P i

layer [39].

ðG<sup>þ</sup> � G�ÞVi

memristor crossbars.

the CNN image identification system.

step 1. First convolution layer(l ¼ 2)

<sup>¼</sup> <sup>∂</sup>E<sup>n</sup> ∂ci þ ∂Ω ∂ci

This part introduces the construction and operation of the memristor neural networks circuit. First of all, we introduce how a single column within a memristor crossbar can be used to perform a convolution operation. Pooling operation can be seen as a simpler conversation operation [39]. The circuit diagram of each column for the convolution operation of the

Each crosspoint of the circuit was composed of memristors, which is represented for synapses. The kernel (k) was represented by the conductivity value (G) in the crossbar circuit. Some extra manipulation include converting kernel matrix into two parallel column to express the positive and negative value of the kernel and converting kernel matrix to conductivity values (δ�) [39] that fall within the bounded range of a memristor crossbar. The op-amp circuit is used to scale

The convolution computation operation in memristor crossbar is the same as the matrix convolution operation. That mainly is a result of the dot-production about the matrixes of kernels and inputs. The first step is the multiplication of voltage (V) and conductance (G <sup>¼</sup> <sup>x</sup>�1) [29], which is following ohm's law (I <sup>¼</sup> <sup>V</sup>�G). Second, it will follow Kirchhoff'<sup>s</sup> current law (KCL), which describes that the circuit flowing out the node will be equal to the sum of current flowing into that node. Based on KCL, novel computation architecture for implementing pot-product is implemented [29]. And then, the lower end of the op amp circuit performs activation function. As a result, each neuron of hidden and output layers implements

� �, where f is a kind of activation function. Figure 17 shows the flow chart of

where L is the number of layers of the CNN recognition system, the input layer (L ¼ 1) holds a testing set of 500 MNIST images, whose size of data set is 28 � 28. L ¼ 2 is the first convolution

The signal size from the front input layer is 28 � 28. In this layer, an input image will be convolved with six different 5 � 5 size kernels on the memristor crossbar. According with the front description, each column is the kernel value of 5 � 5. And the 2D kernel was broken into two arrays in the memristor crossbar to easily account for negative values in the kernel arrays. The total number of a column in the crossbar structure is 2 � 25 þ 1, in which "1" is the value of bias. Since we are using a memristor crossbar to perform the convolution operations, we can generate all six of these output maps in parallel. So, the crossbar circuit exist six parallel columns in a row. Therefore, this layer requires a 51 � 6

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where δ is used as the Kronecker delta.

Use δ<sup>l</sup> represents the sensitivity map corresponding to an output map with inputs u. Again, the convolution is the "valid" type so that the result will match the size of the sensitivity map. Now, the gradients of the error function with respect to the underlying weights ci can be computed by the chain rule

$$\frac{\partial E}{\partial \alpha\_i} = \frac{\partial E}{\partial u^l} \frac{\partial u^l}{\partial \alpha\_i} = \sum\_{u,v} \left( \delta^l \bullet \left( \mathbf{x}\_i^{l-1} \ast \mathbf{K}\_i^l \right) \right)\_{uv} \tag{24}$$

In addition, the sparseness constraints on the distribution of weights α<sup>i</sup> for a given map can also been imposed by adding a regularization penalty Ω(α) to the final error function. Therefore, some weights will be zero. That means, only a few input maps would contribute significantly to a given output map, as opposed to all of them. The error for a single pattern can be written as

$$\frac{\partial E}{\partial c\_i} = \sum\_k \frac{\partial E}{\partial \alpha\_k} \frac{\partial \alpha\_k}{\partial c\_i} = \alpha\_i (\frac{\partial E}{\partial \alpha\_i} - \sum\_k \frac{\partial E}{\partial \alpha\_k} \alpha\_k) \tag{25}$$

$$
\widetilde{E}'' = E'' + \lambda \sum\_{i,j} |\alpha\_{ij}| \tag{26}
$$

This will find the contribution of the regularization term to the gradient for the weights ci. The user defined parameter λ controls the trade-off between minimizing the fit of the network to the training data, and ensures that the weights mentioned in the regularization term are small according to the 1-norm. Again, only the weights α<sup>i</sup> for a given output map need considering and the subscript j can be dropped. First, there is

$$\frac{\partial \mathcal{Q}}{\partial \alpha\_i} = \lambda \text{sign}(\alpha\_i) \tag{27}$$

Combining this result with Eq. (24), the derivation of the contribution is

$$\frac{\partial \mathcal{Q}}{\partial \mathbf{c}\_{i}} = \sum\_{k} \frac{\partial \mathcal{Q}}{\partial \alpha\_{k}} \frac{\partial \alpha\_{k}}{\partial \mathbf{c}\_{i}} = \lambda (|\alpha\_{i}| - \alpha\_{i} \sum\_{k} |\alpha\_{k}|) \tag{28}$$

The final gradients for the weights ci when using the penalized error function Eq. (11) can be computed using Eqs. (13) and (9)

$$
\partial \frac{\widehat{E''}}{\partial \mathbf{c}\_i} = \frac{\partial E''}{\partial \mathbf{c}\_i} + \frac{\partial \mathcal{Q}}{\partial \mathbf{c}\_i} \tag{29}
$$

#### 3.3.4. CNN circuits

Since each set of weights cij for fixed j are independent of all other such sets for any other j, only the updates of a single map need considering and the subscript j can be dropped. Each map is updated in the same way, except with different j indices. The derivative of α<sup>k</sup> with respect to

Use δ<sup>l</sup> represents the sensitivity map corresponding to an output map with inputs u. Again, the convolution is the "valid" type so that the result will match the size of the sensitivity map. Now, the gradients of the error function with respect to the underlying weights ci can be

> <sup>¼</sup> <sup>X</sup> u;v ðδl ∘ xl�<sup>1</sup> <sup>i</sup> � <sup>K</sup><sup>l</sup> i

In addition, the sparseness constraints on the distribution of weights α<sup>i</sup> for a given map can also been imposed by adding a regularization penalty Ω(α) to the final error function. Therefore, some weights will be zero. That means, only a few input maps would contribute significantly to a given output map, as opposed to all of them. The error for a single pattern can be written as

> ¼ αið ∂E ∂α<sup>i</sup>

This will find the contribution of the regularization term to the gradient for the weights ci. The user defined parameter λ controls the trade-off between minimizing the fit of the network to the training data, and ensures that the weights mentioned in the regularization term are small according to the 1-norm. Again, only the weights α<sup>i</sup> for a given output map need considering

X i, j

¼ λðjαij � α<sup>i</sup>

X k

�<sup>X</sup> k

∂E ∂α<sup>k</sup>

¼ δkiα<sup>i</sup> � αiα<sup>k</sup> (23)

� �Þuv (24)

αkÞ (25)

jαkjÞ (28)

jαijj (26)

¼ λsignðαiÞ (27)

the α<sup>i</sup> variables at layer is the derivative of the softmax function is given by

∂E ∂α<sup>i</sup>

∂E ∂ci

and the subscript j can be dropped. First, there is

computed using Eqs. (13) and (9)

<sup>¼</sup> <sup>X</sup> k

∂E ∂α<sup>k</sup> ∂α<sup>k</sup> ∂ci

<sup>E</sup>e<sup>n</sup> <sup>¼</sup> <sup>E</sup><sup>n</sup> <sup>þ</sup> <sup>λ</sup>

∂Ω ∂α<sup>i</sup>

Combining this result with Eq. (24), the derivation of the contribution is

∂Ω ∂α<sup>k</sup> ∂α<sup>k</sup> ∂ci

The final gradients for the weights ci when using the penalized error function Eq. (11) can be

<sup>¼</sup> <sup>X</sup> k

∂Ω ∂ci

<sup>¼</sup> <sup>∂</sup><sup>E</sup> ∂ul ∂ul ∂α<sup>i</sup>

where δ is used as the Kronecker delta.

computed by the chain rule

266 Memristor and Memristive Neural Networks

∂α<sup>k</sup> ∂ci

This part introduces the construction and operation of the memristor neural networks circuit. First of all, we introduce how a single column within a memristor crossbar can be used to perform a convolution operation. Pooling operation can be seen as a simpler conversation operation [39]. The circuit diagram of each column for the convolution operation of the memristor crossbar structure is shown in Figure 16.

Each crosspoint of the circuit was composed of memristors, which is represented for synapses. The kernel (k) was represented by the conductivity value (G) in the crossbar circuit. Some extra manipulation include converting kernel matrix into two parallel column to express the positive and negative value of the kernel and converting kernel matrix to conductivity values (δ�) [39] that fall within the bounded range of a memristor crossbar. The op-amp circuit is used to scale the output voltage and implements the sigmoid activation function.

The convolution computation operation in memristor crossbar is the same as the matrix convolution operation. That mainly is a result of the dot-production about the matrixes of kernels and inputs. The first step is the multiplication of voltage (V) and conductance (G <sup>¼</sup> <sup>x</sup>�1) [29], which is following ohm's law (I <sup>¼</sup> <sup>V</sup>�G). Second, it will follow Kirchhoff'<sup>s</sup> current law (KCL), which describes that the circuit flowing out the node will be equal to the sum of current flowing into that node. Based on KCL, novel computation architecture for implementing pot-product is implemented [29]. And then, the lower end of the op amp circuit performs activation function. As a result, each neuron of hidden and output layers implements f P i ðG<sup>þ</sup> � G�ÞVi � �, where f is a kind of activation function. Figure 17 shows the flow chart of the CNN image identification system.

where L is the number of layers of the CNN recognition system, the input layer (L ¼ 1) holds a testing set of 500 MNIST images, whose size of data set is 28 � 28. L ¼ 2 is the first convolution layer [39].

step 1. First convolution layer(l ¼ 2)

The signal size from the front input layer is 28 � 28. In this layer, an input image will be convolved with six different 5 � 5 size kernels on the memristor crossbar. According with the front description, each column is the kernel value of 5 � 5. And the 2D kernel was broken into two arrays in the memristor crossbar to easily account for negative values in the kernel arrays. The total number of a column in the crossbar structure is 2 � 25 þ 1, in which "1" is the value of bias. Since we are using a memristor crossbar to perform the convolution operations, we can generate all six of these output maps in parallel. So, the crossbar circuit exist six parallel columns in a row. Therefore, this layer requires a 51 � 6 memristor crossbars.

Figure 16. (a) A column circuit of MCNN circuit diagram that is capable of performing convolutional operation and (b) a shorthand depiction for this circuit.

the summation of all the product of inputs and kernels and operate activation function. According to Ohm's law and Kirchhoff's law, every single output value in this time is the input value and the kernel value of the inner product results. After the signal is input, the memristor and op-amp circuits are output later. When all 6 24 � 24 sizes of feature map are obtained, the first convolution operation was finished,the output is the input value of the next

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Following the first convolution layer, a smoothing operation is performed on the six generated feature maps. Pooling operation can be seen as a simpler conversation operation, with all

neuron that will be applied in pooling operation process.

Figure 17. Flowchart describing the CNN recognition system [39].

Step 2. First smoothing layer (l ¼ 3)

kernel applied to each feature map is

So far, we have got the memristor crossbar structure, which simulates the synapses and stores the value of kernels in it. The circuit perform the first convolution operation is shown in Figure 18.

Each image contains 784 pixel, but the image is applied 25 pixels at a time where each 25 pixel section generates a single output value. After these convolution kernels applied, a data array that has a size of 24 24 6 will be generated in the memristor crossbar and then will be operated in the next layer. For each column in the memristor crossbar structure,memristor is used to simulate synapses of neural networks. And, the circuit simulates neurons to produce

Figure 17. Flowchart describing the CNN recognition system [39].

the summation of all the product of inputs and kernels and operate activation function. According to Ohm's law and Kirchhoff's law, every single output value in this time is the input value and the kernel value of the inner product results. After the signal is input, the memristor and op-amp circuits are output later. When all 6 24 � 24 sizes of feature map are obtained, the first convolution operation was finished,the output is the input value of the next neuron that will be applied in pooling operation process.

## Step 2. First smoothing layer (l ¼ 3)

So far, we have got the memristor crossbar structure, which simulates the synapses and stores the value of kernels in it. The circuit perform the first convolution operation is shown in

Figure 16. (a) A column circuit of MCNN circuit diagram that is capable of performing convolutional operation and (b) a

Each image contains 784 pixel, but the image is applied 25 pixels at a time where each 25 pixel section generates a single output value. After these convolution kernels applied, a data array that has a size of 24 24 6 will be generated in the memristor crossbar and then will be operated in the next layer. For each column in the memristor crossbar structure,memristor is used to simulate synapses of neural networks. And, the circuit simulates neurons to produce

Figure 18.

shorthand depiction for this circuit.

268 Memristor and Memristive Neural Networks

Following the first convolution layer, a smoothing operation is performed on the six generated feature maps. Pooling operation can be seen as a simpler conversation operation, with all kernel applied to each feature map is

Figure 18. Circuit used to perform the convolution operations for the second (l ¼ 2) in the CNN recognition system.

$$\mathbf{K} = \begin{bmatrix} 0.25 & 0.25 \\ 0.25 & 0.25 \end{bmatrix}$$

one. The circuit design of the second convolution layer is shown in Figure 20. Each column represents six different feature map convolution processes, and will be operated with 12

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Figure 19. The group of convolution circuits that is used to implement the smoothing operation.

Following the second convolution layer, another smoothing layer is following the second convolution layer to further reduce the size of the data array. The circuit in this layer will be identical to that displayed in Figure 7. With 12 feature maps will be operated, so required 12 parallel single column crossbars. After second layers of pool will produce 4 � 4 of the size of 12

Following the front feature extraction operations, a fully connected layer is used to classify the feature maps. The classification layer is generally a single layer perceptron or multilayer neural

The circuit used to complete this operation can be seen in Figure 21. The memristor crossbar used in classification layer is to store a weight matrix, which is different with storing a set of convolution kernels arrays in convolution circuits. The crossbar consists of 192\*2+1 rows which represent 192 inputs (one input for each of the 16 value in each of the 12 outputs maps), and 10 columns which represent 10 outputs (one for each MNIST digit). So the total numbers of memristors in this

Following every convolution layer, a digital layer was placed at the output of each convolution. The digital storage layer reduces the amount of analog circuit error that is transmitted

feature map, the input to the next layer, classification layer (l ¼ 6).

different kernels in parallel methods.

Step 4. Second smoothing layer(l ¼ 5)

Step 5. Classification layer

layers is (192 þ 1) � 10.

Step 6. Digital storage layers

network.

Be similar with the convolution process, each column of the crossbar represents a kernel. So the memristor numbers of a single column of the crossbar is 4 � 2 þ 1, and six column for with all six feature maps be operated in parallel, Therefore this layer requires a 6 � (2 � 4 þ 1) memristor crossbars. But different with the convolution layers, the conductivities corresponding to negative elements in the kernel matrix in this layer are meaningless because all components of the pooling kernel are positive. The following circuit is shown that has pooling operation on the 6 � 24 � 24 size of feature map which the convolution layer is derived (Figure 19).

In the pooling operation, six different feature maps obtained from the convolution layers applied to every corresponding column respectively and obtain another sets of feature maps.

A subsampling operation is performed following each of the smoothing crossbars that reduce the size of each feature map by a square factor of 2. This could be design in to place a single-bit counter on the memory array where the data output from the smoothing operation is stored. The memory address would only update for every other sample so all unwanted data would be overwritten during the smoothing step.

Step 3. Second convolutional layer (l¼4)

Following the polling and subsample, operation is the second convolution operation. Different with the first one, inputs of the second convolution layers are six feature maps with 12 � 12 size, and it exists 12 outputs instead of six in the front one. Because the different number and size of input and output single, the structure of the second layer is distinctly different from the

Figure 19. The group of convolution circuits that is used to implement the smoothing operation.

one. The circuit design of the second convolution layer is shown in Figure 20. Each column represents six different feature map convolution processes, and will be operated with 12 different kernels in parallel methods.

Step 4. Second smoothing layer(l ¼ 5)

Following the second convolution layer, another smoothing layer is following the second convolution layer to further reduce the size of the data array. The circuit in this layer will be identical to that displayed in Figure 7. With 12 feature maps will be operated, so required 12 parallel single column crossbars. After second layers of pool will produce 4 � 4 of the size of 12 feature map, the input to the next layer, classification layer (l ¼ 6).

#### Step 5. Classification layer

<sup>K</sup> <sup>¼</sup> <sup>0</sup>:25 0:<sup>25</sup> 0:25 0:25 

Figure 18. Circuit used to perform the convolution operations for the second (l ¼ 2) in the CNN recognition system.

Be similar with the convolution process, each column of the crossbar represents a kernel. So the memristor numbers of a single column of the crossbar is 4 � 2 þ 1, and six column for with all six feature maps be operated in parallel, Therefore this layer requires a 6 � (2 � 4 þ 1) memristor crossbars. But different with the convolution layers, the conductivities corresponding to negative elements in the kernel matrix in this layer are meaningless because all components of the pooling kernel are positive. The following circuit is shown that has pooling operation on the 6 � 24 � 24 size of feature map which the convolution layer is derived

In the pooling operation, six different feature maps obtained from the convolution layers applied to every corresponding column respectively and obtain another sets of feature maps. A subsampling operation is performed following each of the smoothing crossbars that reduce the size of each feature map by a square factor of 2. This could be design in to place a single-bit counter on the memory array where the data output from the smoothing operation is stored. The memory address would only update for every other sample so all unwanted data would

Following the polling and subsample, operation is the second convolution operation. Different with the first one, inputs of the second convolution layers are six feature maps with 12 � 12 size, and it exists 12 outputs instead of six in the front one. Because the different number and size of input and output single, the structure of the second layer is distinctly different from the

(Figure 19).

270 Memristor and Memristive Neural Networks

be overwritten during the smoothing step.

Step 3. Second convolutional layer (l¼4)

Following the front feature extraction operations, a fully connected layer is used to classify the feature maps. The classification layer is generally a single layer perceptron or multilayer neural network.

The circuit used to complete this operation can be seen in Figure 21. The memristor crossbar used in classification layer is to store a weight matrix, which is different with storing a set of convolution kernels arrays in convolution circuits. The crossbar consists of 192\*2+1 rows which represent 192 inputs (one input for each of the 16 value in each of the 12 outputs maps), and 10 columns which represent 10 outputs (one for each MNIST digit). So the total numbers of memristors in this layers is (192 þ 1) � 10.

Step 6. Digital storage layers

Following every convolution layer, a digital layer was placed at the output of each convolution. The digital storage layer reduces the amount of analog circuit error that is transmitted

Figure 20. The circuit that is used to implement the second convolution layer.

between layers. We chose to store an entire image between layers because any benefit gained by a systematically reduced memory size would likely be outweighed by the complexity of a data controller of this nature [44].

#### 3.3.4.1. CNN instance

The CNN algorithm purely in simulation under these training conditions results in 92% classification accuracy as shown in Figure 22. And, the simulation process is to test the accuracy of the memristor based CNN recognition system described in the previous section. When testing the simulated memristor crossbars, an accuracy of 91.8% was achieved.

different time steps [40, 42]. And, others, in recurrent neural networks, lengths history represented by neurons with recurrent connections, and history length is unlimited. Also recurrent networks can learn to compress whole history in low dimensional space, while feedforward networks compress (project) just single word recurrent networks have possibility to form short term memory, so they can better deal with position invariance [45] RNN archi-

Figure 21. Circuit that is used to implement the classification layer of the CNN recognition system.

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Figure 22. Error present when training the CNN algorithm is software [39].

The simplest architecture of RNNs is illustrated in Figure 23 [40]. The left of Figure 24 shows the ordinary recurrent network circuit with weight matrices U, V, W denoting three different kind of connection (input-to-hidden, hidden-to-output, and hidden-to-hidden,

tecture.

#### 3.4. Recurrent neural networks

#### 3.4.1. RNN concept

Recurrent neural networks, or RNNs, are the main tool for handling sequential data, which involve variable length inputs or outputs [40]. Compared with multilayer network, the weights in an RNN are shared across different instances of the artificial neurons, each associated with

Figure 21. Circuit that is used to implement the classification layer of the CNN recognition system.

Figure 22. Error present when training the CNN algorithm is software [39].

between layers. We chose to store an entire image between layers because any benefit gained by a systematically reduced memory size would likely be outweighed by the complexity of a

The CNN algorithm purely in simulation under these training conditions results in 92% classification accuracy as shown in Figure 22. And, the simulation process is to test the accuracy of the memristor based CNN recognition system described in the previous section.

Recurrent neural networks, or RNNs, are the main tool for handling sequential data, which involve variable length inputs or outputs [40]. Compared with multilayer network, the weights in an RNN are shared across different instances of the artificial neurons, each associated with

When testing the simulated memristor crossbars, an accuracy of 91.8% was achieved.

data controller of this nature [44].

272 Memristor and Memristive Neural Networks

Figure 20. The circuit that is used to implement the second convolution layer.

3.4. Recurrent neural networks

3.3.4.1. CNN instance

3.4.1. RNN concept

different time steps [40, 42]. And, others, in recurrent neural networks, lengths history represented by neurons with recurrent connections, and history length is unlimited. Also recurrent networks can learn to compress whole history in low dimensional space, while feedforward networks compress (project) just single word recurrent networks have possibility to form short term memory, so they can better deal with position invariance [45] RNN architecture.

The simplest architecture of RNNs is illustrated in Figure 23 [40]. The left of Figure 24 shows the ordinary recurrent network circuit with weight matrices U, V, W denoting three different kind of connection (input-to-hidden, hidden-to-output, and hidden-to-hidden,

respectively). Each circle indicates a whole vector of activations. The right of Figure 24 is a time-unfolded flow graph, where each node is now associated with one particular time

Memristor-based Hopfield networks (MHN), which is an ideal model for the case where the memristor-based circuit network exhibits complex switching phenomena, and is frequently encountered in the applications [46]. A Hopfield network consists of a set of interconnected artificial neurons and synapses. In this case, a nine synapses Hopfield network is realized with six memristors and three neurons. As shown in Figure 25, the artificial neuron has three inputs and each input, Ni ¼ (i ¼ 1, 2, and 3), is connected to a synapse with synaptic weight of wi. The

3

i¼1

sign Nð Þ¼ <sup>1</sup> if N <sup>≥</sup> <sup>0</sup>

An artificial neuron was constructed, as shown in Figure 26. An operational amplifier is used to sum the inputs. The switches, S1, S2, and S3, are controlled by external signals to obtain positive or negative synaptic weights. The synaptic weights corresponding to input N1, N2,

resistance of the memristors, respectively, and the resistance of R is fixed at 3 MΩ). In the circuit shown in Figure 26, transmission gates B1, B2, and B3 reform signals without modifying

The architecture of a 3-bit MHN implemented with nine synapses is shown in Figure 27. The synaptic weight from neuron i to neuron j is denoted as wi,j, which is mapped to resistance of the corresponding memristor Mi,j,. Mi,j, and wi,<sup>j</sup> are represented by the resistance matrix,

M2þ<sup>R</sup> and W3 ¼ � M3

�

wiNi � θ !

0 if N < 0

M3þ<sup>R</sup>, respectively (M1, M2, and M3 are the

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<sup>y</sup> <sup>¼</sup> sign <sup>X</sup>

instance.

3.4.2. A Hopfield neural network design

and N3 are w1 ¼ � M1

respectively

output of the three-input binary artificial neuron is expressed as

where y is the neuron's threshold; and the sign function is defined as

its polarity, inverters I1, I2 and I3 generate negative synaptic weights.

M1þ<sup>R</sup>, W2 ¼ � M2

Figure 25. Mathematical abstraction of the neuron model.

Figure 23. The architecture of recurrent neural networks.

Figure 24. General class of recurrent neural network circuit.

respectively). Each circle indicates a whole vector of activations. The right of Figure 24 is a time-unfolded flow graph, where each node is now associated with one particular time instance.

#### 3.4.2. A Hopfield neural network design

Figure 23. The architecture of recurrent neural networks.

274 Memristor and Memristive Neural Networks

Figure 24. General class of recurrent neural network circuit.

Memristor-based Hopfield networks (MHN), which is an ideal model for the case where the memristor-based circuit network exhibits complex switching phenomena, and is frequently encountered in the applications [46]. A Hopfield network consists of a set of interconnected artificial neurons and synapses. In this case, a nine synapses Hopfield network is realized with six memristors and three neurons. As shown in Figure 25, the artificial neuron has three inputs and each input, Ni ¼ (i ¼ 1, 2, and 3), is connected to a synapse with synaptic weight of wi. The output of the three-input binary artificial neuron is expressed as

$$\mathbf{y} = \text{sign}\left(\sum\_{i=1}^{3} w\_i \mathbf{N}\_i - \theta\right) \tag{30}$$

where y is the neuron's threshold; and the sign function is defined as

$$\text{sign}(\mathbf{N}) = \begin{cases} 1 & \text{if} N \ge 0 \\ 0 & \text{if} N < 0 \end{cases}$$

An artificial neuron was constructed, as shown in Figure 26. An operational amplifier is used to sum the inputs. The switches, S1, S2, and S3, are controlled by external signals to obtain positive or negative synaptic weights. The synaptic weights corresponding to input N1, N2, and N3 are w1 ¼ � M1 M1þ<sup>R</sup>, W2 ¼ � M2 M2þ<sup>R</sup> and W3 ¼ � M3 M3þ<sup>R</sup>, respectively (M1, M2, and M3 are the resistance of the memristors, respectively, and the resistance of R is fixed at 3 MΩ). In the circuit shown in Figure 26, transmission gates B1, B2, and B3 reform signals without modifying its polarity, inverters I1, I2 and I3 generate negative synaptic weights.

The architecture of a 3-bit MHN implemented with nine synapses is shown in Figure 27. The synaptic weight from neuron i to neuron j is denoted as wi,j, which is mapped to resistance of the corresponding memristor Mi,j,. Mi,j, and wi,<sup>j</sup> are represented by the resistance matrix, respectively

Figure 25. Mathematical abstraction of the neuron model.

Figure 26. Circuit schematic of the designed 3-bit neuron.

Xð Þ¼ t þ 1 signðXð Þ<sup>t</sup> � W � TÞ (31)

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where t represents the number of updating cycles and when t ¼ 0, X(0) represents initial states vector. In one updating cycle, new states of the neurons are asynchronously updated from X1,

Hardware implementation of deep neural networks is accomplished by using neuron-synapse circuits and future devices can make deep neural networks (NNs) design and fabrication more efficient. The full power of NNs has not yet been realized, but the release of commercial chips implementing arbitrary neural networks, more efficient algorithms will no doubt be realized in these domains where neural networks can improve the performance dramatically. Memristorbased NNs promote and solve many A.I. problems such as machine translation, intelligent question-and-answer, and game play, and in the future, memristor-based NNs can be used in neuromorphic computation, brain-computer interface or computer-brain interface, cell phone

Different memristor-based neural network design paradigms are described. With regard to neural network systems, the current neural network implementations are not sufficient but

X2 to X3 in three stages, which are defined as stages a, b, and c, respectively [46].

Figure 28. Architecture of the MHN with symmetrical configuration consisting of six memristors.

4. Potential applications and prospects

A.I. application, autopilot and environment monitor.

5. Conclusions

Figure 27. Architecture of the 3-bit MHN consisting of nine memristors.

$$\mathbf{M} = \begin{bmatrix} M\_{11} & M\_{12} & M\_{13} \\ M\_{21} & M\_{22} & M\_{23} \\ M\_{31} & M\_{32} & M\_{33} \end{bmatrix}, \ \mathbf{W} = \begin{bmatrix} W\_{11} & W\_{12} & W\_{13} \\ W\_{21} & W\_{22} & W\_{23} \\ W\_{31} & W\_{32} & W\_{33} \end{bmatrix}.$$

Due to the symmetry of Hopfield network, M12 ¼ M21, M23 ¼ M32, and M13 ¼ M31, the implementation of the network only needs six memristors. The schematic of this circuit is shown in Figure 28, and all the demonstration below is based on this circuit. The threshold vector T ¼ (θ1, θ2, θ3) represents the threshold of the artificial neurons (neurons 1, 2, and 3), and the state vector X ¼ (X1, X2, X3) represents the states of the three neurons, respectively. In each updating cycle, new states of the neurons are updated by the following function

Figure 28. Architecture of the MHN with symmetrical configuration consisting of six memristors.

$$\mathbf{X}(\mathbf{t}+\mathbf{1}) = \text{sign}(X\_{(t)} \cdot \mathbf{W} - \mathbf{T}) \tag{31}$$

where t represents the number of updating cycles and when t ¼ 0, X(0) represents initial states vector. In one updating cycle, new states of the neurons are asynchronously updated from X1, X2 to X3 in three stages, which are defined as stages a, b, and c, respectively [46].

#### 4. Potential applications and prospects

Hardware implementation of deep neural networks is accomplished by using neuron-synapse circuits and future devices can make deep neural networks (NNs) design and fabrication more efficient. The full power of NNs has not yet been realized, but the release of commercial chips implementing arbitrary neural networks, more efficient algorithms will no doubt be realized in these domains where neural networks can improve the performance dramatically. Memristorbased NNs promote and solve many A.I. problems such as machine translation, intelligent question-and-answer, and game play, and in the future, memristor-based NNs can be used in neuromorphic computation, brain-computer interface or computer-brain interface, cell phone A.I. application, autopilot and environment monitor.

## 5. Conclusions

M ¼

Figure 26. Circuit schematic of the designed 3-bit neuron.

276 Memristor and Memristive Neural Networks

2 4

Figure 27. Architecture of the 3-bit MHN consisting of nine memristors.

M<sup>11</sup> M<sup>12</sup> M<sup>13</sup> M<sup>21</sup> M<sup>22</sup> M<sup>23</sup> M<sup>31</sup> M<sup>32</sup> M<sup>33</sup> 3

5, W ¼

Due to the symmetry of Hopfield network, M12 ¼ M21, M23 ¼ M32, and M13 ¼ M31, the implementation of the network only needs six memristors. The schematic of this circuit is shown in Figure 28, and all the demonstration below is based on this circuit. The threshold vector T ¼ (θ1, θ2, θ3) represents the threshold of the artificial neurons (neurons 1, 2, and 3), and the state vector X ¼ (X1, X2, X3) represents the states of the three neurons, respectively. In

each updating cycle, new states of the neurons are updated by the following function

2 4

W<sup>11</sup> W<sup>12</sup> W<sup>13</sup> W<sup>21</sup> W<sup>22</sup> W<sup>23</sup> W<sup>31</sup> W<sup>32</sup> W<sup>33</sup> 3 5,

> Different memristor-based neural network design paradigms are described. With regard to neural network systems, the current neural network implementations are not sufficient but

fortunately, memristor-based systems provide the potential solution. The basic concepts of memristor-based implementation, such as memristor-based synapse, memristor-based neuron, and memristor crossbar based neuromorphic computing engine, are discussed. The memristor-based neural networks, including SNNs, MNNs, CNNs, and RNNs, are possible and efficient and are expected to spur future development of A.I. It is expected that memristorbased neural networks will take the lead.

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Memristor Neural Network Design

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## Acknowledgements

The work was jointly financially supported by the National Natural Science Foundation of China under grant nos. 11574017 and 51372008, and the Special Foundation of Beijing Municipal Science & Technology Commission (Grant No. Z161100000216149).

## Author details

Anping Huang\*, Xinjiang Zhang, Runmiao Li and Yu Chi

\*Address all correspondence to: aphuang@buaa.edu.cn

School of Physics and Nuclear Energy Engineering, Beihang University, Beijing, China

## References


[7] Ali S, Bae J, Lee CH, et al. Ultra-low power non-volatile resistive crossbar memory based on pull up resistors. Organic Electronics. 2017;41:73-78

fortunately, memristor-based systems provide the potential solution. The basic concepts of memristor-based implementation, such as memristor-based synapse, memristor-based neuron, and memristor crossbar based neuromorphic computing engine, are discussed. The memristor-based neural networks, including SNNs, MNNs, CNNs, and RNNs, are possible and efficient and are expected to spur future development of A.I. It is expected that memristor-

The work was jointly financially supported by the National Natural Science Foundation of China under grant nos. 11574017 and 51372008, and the Special Foundation of Beijing Munic-

School of Physics and Nuclear Energy Engineering, Beihang University, Beijing, China

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**Chapter 13**

**Provisional chapter**

**Spike‐Timing‐Dependent Plasticity in Memristors**

**Spike**‐**Timing**‐**Dependent Plasticity in Memristors**

DOI: 10.5772/intechopen.69535

The spike‐timing‐dependent plasticity (STDP) characteristic of the memristor plays an important role in the development of neuromorphic network computing in the future. The STDP characteristics were observed in different memristors based on different kinds of materials. The investigation regarding the influences of device hysteresis character‐ istic, the initial conductance of the memristors, and the waveform of the voltage pulses applied to the memristor as preneuron voltage spike and postneuron voltage spike on the

The state‐of‐the‐art artificial intelligence based on traditional von Neumann computation paradigm has shown remarkable learning and thinking abilities, for instance, AlphaGo created by the Google‐owned company Deep Mind beat the top Go player Lee Sedol by 4:1 recently [1]. However, the information processing through the digital von Neumann computation paradigm is much less efficient as compared to human brains, which is the major bottleneck of von Neumann computation paradigm. Synapse plays the key role in learning, thinking, and memorizing for a human being, and there are approximately 1014 synapses in a human's brain [2]. A synapse is formed between two neuron cells [3], and the synapse weight can be precisely tuned by the ionic flowing through them. It is well known that the adaptation of the synapse weight between two neurons it connects with makes the biological systems functional [4]. In order to build up a system that behaves in

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

Yao Shuai, Xinqiang Pan and Xiangyu Sun

Yao Shuai, Xinqiang Pan and Xiangyu Sun

Additional information is available at the end of the chapter

STDP behavior of memristors are reviewed.

**Keywords:** Memristor, Spike‐timing‐dependent plasticity

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69535

**Abstract**

**1. Introduction**

**Provisional chapter**
