Preface

Chapter 8 **Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models 167**

Chapter 9 **Mathematical Modeling of Memristors 187**

**Section 3 Memristor Neuromorphic Applications 207**

Chapter 10 **Introduction to Memristive HTM Circuits 209**

**Switching Memory 227**

Chapter 12 **Memristor Neural Network Design 249**

Chapter 11 **Review of Recently Progress on Neural Electronics and**

Chapter 13 **Spike‐Timing‐Dependent Plasticity in Memristors 283** Yao Shuai, Xinqiang Pan and Xiangyu Sun

Chapter 14 **Neural Network-Based Analog-to-Digital Converters 297** Aigerim Tankimanova and Alex Pappachen James

Chih-Hung Pan, Ting-Chang Chang and Jack C. Lee

Anping Huang, Xinjiang Zhang, Runmiao Li and Yu Chi

Eshraghian

**VI** Contents

Yasin Oğuz

Jason Kamran Jr Eshraghian, Herbert H.C. Iu and Kamran

Alex James, Timur Ibrayev, Olga Krestinskaya and Irina Dolzhikova

**Memcomputing Applications in Intrinsic SiOx-Based Resistive**

Cheng-Chih Hsieh, Yao-Feng Chang, Ying-Chen Chen, Xiaohan Wu, Meiqi Guo, Fei Zhou, Sungjun Kim, Burt Fowler, Chih-Yang Lin,

The growth in internet of things, devices and systems has resulted in the need to develop energy-efficient near-sensor processing devices and circuits. This requires the development of alternative computing implementations such as neuromorphic computing, quantum com‐ puting and approximate computing. Memristor devices and their natural properties to change states can be used to mimic neural circuits and neural networks. It is estimated that these networks can be scaled in the future to create large-scale neurocomputing solution.

This book covers a range of models, circuits and systems built with memristor devices and networks in applications to neural networks. It is divided into three parts: (1) Devices, (2) Models and (3) Applications. The resistive switching property is an important aspect of the memristors, and there are several designs of this discussed in this book, such as in metal oxide/organic semiconductor nonvolatile memories, nanoscale switching and degradation of resistive random access memory and graphene oxide-based memristor. The modelling of the memristors is required to ensure that the devices can be put to use and improve emerg‐ ing application. In this book, various memristor models are discussed, from a mathematical framework to implementations in SPICE and verilog, that will be useful for the practitioners and researchers to get a grounding on the topic. The applications of the memristor models in various neuromorphic networks are discussed covering various neural network models, im‐ plementations in A/D converter and hierarchical temporal memories.

This book is a response to the growing field of memristor networks and applications, pro‐ viding insights into a collection of topics in memristor devices, circuits and systems. It is suitable for the introductory studies and equally useful for the researchers to discuss the emerging topics in the memristor networks.

> **Alex Pappachen James** Nazarbayev University Kazakhstan

**Section 1**

**Memristor Devices**

**Section 1**

**Memristor Devices**

**Chapter 1**

Provisional chapter

**Physical Models for Resistive Switching Devices**

DOI: 10.5772/intechopen.69025

We present a classification and description of the principal resistive switching and transport mechanisms in chalcogonides materials. We classify the model according to how many material dimensions are involved in the resistive switching mechanism. In this way, we describe the phase change model (3D), the interface modulation model (2D) and models where the switching mechanism depends on the formation of a conduction filament (1D). Among the conduction filament models, we include the thermochemical oxygen diffusion mechanism, the oxidation/reduction mechanism and the quantum point

Typically, a resistive switching material changes its resistance between two states: High Resistive State (HRS or OFF-state) and Low Resistive State (LRS or ON-state). The most common structure for a resistive switching devices is an insulator between two metals or metal/insulator/metal (MIM) structure. One of the most important applications of these kind of devices is

The metal elements of the MIM structure are called top and bottom electrodes. An electrical stimulus is necessary to apply between these electrodes to change the resistive state of the insulator material. In order to determine the resistive state (HRS or LRS), a low voltage is applied on the electrodes, and the current, which flows through the insulator, is measured (IHRS or ILRS). There are several orders of magnitudes of difference between IHRS and ILRS currents. The change from the HRS to the LRS is called SET process and the change from the

Depending on the voltage polarity applied on the electrodes, there are two schemes to change the resistive state: unipolar and bipolar. On the one hand, in the unipolar scheme, the resistive state change does not depend on the voltage polarity and there are two threshold voltages: one

> © The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Keywords: chalcogonides, resistive switching, physical models

for non-volatile memories or Resistive RAMs (ReRAMs).

LRS to the HRS is called RESET process.

Physical Models for Resistive Switching Devices

Luis‐Miguel Procel‐Moya

Luis-Miguel Procel-Moya

Abstract

effect.

1. Introduction

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69025

#### **Physical Models for Resistive Switching Devices** Physical Models for Resistive Switching Devices

DOI: 10.5772/intechopen.69025

#### Luis‐Miguel Procel‐Moya Luis-Miguel Procel-Moya

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69025

#### Abstract

We present a classification and description of the principal resistive switching and transport mechanisms in chalcogonides materials. We classify the model according to how many material dimensions are involved in the resistive switching mechanism. In this way, we describe the phase change model (3D), the interface modulation model (2D) and models where the switching mechanism depends on the formation of a conduction filament (1D). Among the conduction filament models, we include the thermochemical oxygen diffusion mechanism, the oxidation/reduction mechanism and the quantum point effect.

Keywords: chalcogonides, resistive switching, physical models

## 1. Introduction

Typically, a resistive switching material changes its resistance between two states: High Resistive State (HRS or OFF-state) and Low Resistive State (LRS or ON-state). The most common structure for a resistive switching devices is an insulator between two metals or metal/insulator/metal (MIM) structure. One of the most important applications of these kind of devices is for non-volatile memories or Resistive RAMs (ReRAMs).

The metal elements of the MIM structure are called top and bottom electrodes. An electrical stimulus is necessary to apply between these electrodes to change the resistive state of the insulator material. In order to determine the resistive state (HRS or LRS), a low voltage is applied on the electrodes, and the current, which flows through the insulator, is measured (IHRS or ILRS). There are several orders of magnitudes of difference between IHRS and ILRS currents. The change from the HRS to the LRS is called SET process and the change from the LRS to the HRS is called RESET process.

Depending on the voltage polarity applied on the electrodes, there are two schemes to change the resistive state: unipolar and bipolar. On the one hand, in the unipolar scheme, the resistive state change does not depend on the voltage polarity and there are two threshold voltages: one

for the RESET process (VRESET) and one for the SET process (VSET) with the same polarity as we can see in Figure 1. On the other hand, in the bipolar scheme, VRESET and VSET have different polarities (Figure 2).

There is no universal theory or model which explains the electron conduction in the two resistive states and the SET and RESET processes because there are many factors that affect the switching behaviour, such as the type of the insulator material, fabrication process, nature of the dielectric breakdown, among others. However, Waser and Wutting proposed a classification based on the type of the resistive switching mechanisms, such as nanochemical materials, ferroelectric tunnelling, electrostatics effects, phase change mechanism, thermochemical mechanism, redox-based effect, electrochemical effect, molecular switching effect and magnetoresistive effect [1].

Chalcogonides are one of the most used materials in the fabrication of resistive memory devices. The switching mechanisms related to these materials are: phase change memory effect, thermochemical memory effect, redox-based memory effect and interface defect modulation. The phase change mechanism affects the complete volume of the insulator material and it is considered as a 3D mechanism. A 2D resistive switching mechanism is the modulation of the defect density at the metal/insulator interface. Finally, when the resistivity material depends on the formation of a conduction filament (CF), 1D mechanisms are involved in the resistive switching process. Thermochemical diffusion of oxygen, reduction/oxidation of the CF and quantum point contact effects are typical 1D mechanisms.

2. Phase change model

Figure 2. SET and RESET process for bipolar behaviour.

vice versa) to have different resistivity and reflectivity.

Heavier chalcogonides, such as tellurides and selenides, show different electrical and optical properties in their amorphous and crystalline phases (Figure 3). The resistive switching of these materials is unipolar. On the one hand, the amorphous phase of these materials has high resistivity and low reflectivity and, on the other hand, crystalline phase has low resistivity and high reflectivity [2]. These properties are being exploited in the development of optical storage

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 5

Figure 3. Phase change mechanism: the phase material changes from (a) amorphous phase to (b) crystalline phase (and

Figure 1. SET and RESET process for unipolar behaviour.

Figure 2. SET and RESET process for bipolar behaviour.

## 2. Phase change model

for the RESET process (VRESET) and one for the SET process (VSET) with the same polarity as we can see in Figure 1. On the other hand, in the bipolar scheme, VRESET and VSET have different

There is no universal theory or model which explains the electron conduction in the two resistive states and the SET and RESET processes because there are many factors that affect the switching behaviour, such as the type of the insulator material, fabrication process, nature of the dielectric breakdown, among others. However, Waser and Wutting proposed a classification based on the type of the resistive switching mechanisms, such as nanochemical materials, ferroelectric tunnelling, electrostatics effects, phase change mechanism, thermochemical mechanism, redox-based effect, electrochemical effect, molecular switching effect and magne-

Chalcogonides are one of the most used materials in the fabrication of resistive memory devices. The switching mechanisms related to these materials are: phase change memory effect, thermochemical memory effect, redox-based memory effect and interface defect modulation. The phase change mechanism affects the complete volume of the insulator material and it is considered as a 3D mechanism. A 2D resistive switching mechanism is the modulation of the defect density at the metal/insulator interface. Finally, when the resistivity material depends on the formation of a conduction filament (CF), 1D mechanisms are involved in the resistive switching process. Thermochemical diffusion of oxygen, reduction/oxidation of the

CF and quantum point contact effects are typical 1D mechanisms.

Figure 1. SET and RESET process for unipolar behaviour.

polarities (Figure 2).

4 Memristor and Memristive Neural Networks

toresistive effect [1].

Heavier chalcogonides, such as tellurides and selenides, show different electrical and optical properties in their amorphous and crystalline phases (Figure 3). The resistive switching of these materials is unipolar. On the one hand, the amorphous phase of these materials has high resistivity and low reflectivity and, on the other hand, crystalline phase has low resistivity and high reflectivity [2]. These properties are being exploited in the development of optical storage

Figure 3. Phase change mechanism: the phase material changes from (a) amorphous phase to (b) crystalline phase (and vice versa) to have different resistivity and reflectivity.

products, such as compact disks (CD), digital versatile disks (DVD), high-definition digital versatile disks (HD-DVD) and Blu-ray disks (BR). The first kind of materials used for optical storage were good glasses, such as Te-based alloys like Te85Ge13 doped with Sb, S and P. These materials show good electrical switching properties in the amorphous and crystalline phases but the crystallization time was in the order of microseconds, too high to be considered for optical storage. The second generation of these materials shows shorter crystallization time and good optical properties. Among these materials, we have GeTe, Ge11Te80Sn4Au23, GeTe-Sb2Te3, GeBiTe and GeInSbTe. After, a third family of materials was later discovered which includes alloys of Sb2Te doped with Ag, In and Ge [2].

3. Metal/insulator interface modulation model

this behaviour is the Nb-doped SrTiO3 [3].

contact [3].

In this model, the resistive switching is presented at the metal/insulator interface. In other words, there is a contact resistance switching behaviour. This interface depending mechanism is presented in Peroskite oxides in which the material resistivity strongly depends on the interface area and the switching mechanism is always bipolar. A typical material that shows

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 7

The origin of this resistivity change can be understood by examining the metal/insulator interface band diagram as shown in Figure 4. The insulator oxide is usually doped with different metals. Depending of doped metal and its density, the insulator behaves as semiconductor at the interface. This provokes a Schottky barrier contact instead of a pure ohmic

An electric field applied on the metal electrodes can electrochemically modify the oxygen vacancy density at the interface. For an n-type semiconductor, an increment of the oxygen vacancies density reduces the depletion layer, Wd, in the energy band diagram provoking an increment of the tunnel electron conduction and, therefore, a decrement of the contact

Figure 4. Band diagrams at the Metal/Insulator interfaces. For a p-type semiconductor, the presence of oxygen vacancies

increases Wd. For an n-type semiconductor, the presence of oxygen vacancies decreases Wd.

There are two important temperature thresholds in these materials: the melting temperature (Tm) and the glass-transition temperature (Tg) with T<sup>m</sup> > Tg. The process to change the material phase from crystalline to amorphous and vice versa is as follows [2]:


For electrical storage devices, the resistive switching property is fundamental and all these materials have it. However, not all these materials have the reflectivity switching property. To have this property, a very short time (few tens of nanoseconds) is needed for cooling down the material from the liquid phase to amorphous phase (step 2) [2].

When a low voltage is applied to the material in the amorphous phase, a very low current is measured due to the high resistance. When the voltage reaches a value around 0.7 V, the resistivity decreases and the material reach the so-called ON-amorphous phase [1, 2]. In these phases, the current increases significantly and enables enough heat to recrystallize the material. During the phase change, material defects play an important role. In the amorphous phase, the current is controlled by the Pool-Frenkel conduction, where carriers are trapped in defect sites according to the following equation (electron hopping mechanism) [1]:

$$I = 2qAN\_T \frac{\Delta z}{\tau\_0} e^{-(E\_C - E\_\delta)/kT} \sinh\left(\frac{qV\Delta z}{2kTt\_h}\right) \tag{1}$$

where A is the contact area, V the applied voltage, N<sup>T</sup> the integral of the trap distribution, Δz the intertrap distance, τ<sup>0</sup> the scape time for a trapping electron, E<sup>F</sup> the Fermi energy, E<sup>C</sup> the conduction band energy, q the elementary electron charge and t<sup>h</sup> the thickness of the material. Because of the total conduction is presented in the complete material volume, this mechanism is called 3D. Experimental results show that the defect density in the material is very high and most of the defects are negative U-centres [1]. On the other hand, computational simulations show that in the crystalline phase, vacancy defects predominate with a concentration of 25% [1].

## 3. Metal/insulator interface modulation model

products, such as compact disks (CD), digital versatile disks (DVD), high-definition digital versatile disks (HD-DVD) and Blu-ray disks (BR). The first kind of materials used for optical storage were good glasses, such as Te-based alloys like Te85Ge13 doped with Sb, S and P. These materials show good electrical switching properties in the amorphous and crystalline phases but the crystallization time was in the order of microseconds, too high to be considered for optical storage. The second generation of these materials shows shorter crystallization time and good optical properties. Among these materials, we have GeTe, Ge11Te80Sn4Au23, GeTe-Sb2Te3, GeBiTe and GeInSbTe. After, a third family of materials was later discovered which

There are two important temperature thresholds in these materials: the melting temperature (Tm) and the glass-transition temperature (Tg) with T<sup>m</sup> > Tg. The process to change the material

• To write a bit, a short high-pulse laser or current is applied on the crystalline material to

• The material is cooling down rapidly with a rate higher than 109 K/s. In a very short time, the material reaches the amorphous phase without passing through the crystalline one. • To erase the bit, a long short-pulse laser or current is applied on the amorphous material. The material temperature increases over Tg. There is an increment of the electron mobility

For electrical storage devices, the resistive switching property is fundamental and all these materials have it. However, not all these materials have the reflectivity switching property. To have this property, a very short time (few tens of nanoseconds) is needed for cooling down the

When a low voltage is applied to the material in the amorphous phase, a very low current is measured due to the high resistance. When the voltage reaches a value around 0.7 V, the resistivity decreases and the material reach the so-called ON-amorphous phase [1, 2]. In these phases, the current increases significantly and enables enough heat to recrystallize the material. During the phase change, material defects play an important role. In the amorphous phase, the current is controlled by the Pool-Frenkel conduction, where carriers are trapped in

where A is the contact area, V the applied voltage, N<sup>T</sup> the integral of the trap distribution, Δz the intertrap distance, τ<sup>0</sup> the scape time for a trapping electron, E<sup>F</sup> the Fermi energy, E<sup>C</sup> the conduction band energy, q the elementary electron charge and t<sup>h</sup> the thickness of the material. Because of the total conduction is presented in the complete material volume, this mechanism is called 3D. Experimental results show that the defect density in the material is very high and most of the defects are negative U-centres [1]. On the other hand, computational simulations show that in the

�ðEC�EFÞ=kTsinh qVΔ<sup>z</sup>

2kTth 

ð1Þ

defect sites according to the following equation (electron hopping mechanism) [1]:

Δz τ0 e

crystalline phase, vacancy defects predominate with a concentration of 25% [1].

includes alloys of Sb2Te doped with Ag, In and Ge [2].

and the material changes to the crystalline phase.

material from the liquid phase to amorphous phase (step 2) [2].

I ¼ 2qANT

reach Tm temperature.

6 Memristor and Memristive Neural Networks

phase from crystalline to amorphous and vice versa is as follows [2]:

In this model, the resistive switching is presented at the metal/insulator interface. In other words, there is a contact resistance switching behaviour. This interface depending mechanism is presented in Peroskite oxides in which the material resistivity strongly depends on the interface area and the switching mechanism is always bipolar. A typical material that shows this behaviour is the Nb-doped SrTiO3 [3].

The origin of this resistivity change can be understood by examining the metal/insulator interface band diagram as shown in Figure 4. The insulator oxide is usually doped with different metals. Depending of doped metal and its density, the insulator behaves as semiconductor at the interface. This provokes a Schottky barrier contact instead of a pure ohmic contact [3].

An electric field applied on the metal electrodes can electrochemically modify the oxygen vacancy density at the interface. For an n-type semiconductor, an increment of the oxygen vacancies density reduces the depletion layer, Wd, in the energy band diagram provoking an increment of the tunnel electron conduction and, therefore, a decrement of the contact

Figure 4. Band diagrams at the Metal/Insulator interfaces. For a p-type semiconductor, the presence of oxygen vacancies increases Wd. For an n-type semiconductor, the presence of oxygen vacancies decreases Wd.

resistance (LRS). If an electric field is applied on the opposite direction, the number of oxygen vacancies in the n-type semiconductor decreases and provokes an increment of W<sup>d</sup> and, therefore, the contact resistance increases (HRS). On the other hand, for a p-type semiconductor, the increment of oxygen vacancies increases W<sup>d</sup> and the contact resistance (HRS), and a diminution of the oxygen vacancies decreases W<sup>d</sup> and the contact resistance (LRS). In this model, the metal work function plays a very important role because the band bending strongly depends on this parameter.

starts to decrease but not in a permanent way. In this process, the material temperature increases up to certain value (related to a threshold voltage) when a local redox reaction begins and causes

The voltage polarity to change states in cells with CF can be unipolar or bipolar. For unipolar behaviour, the electron conduction mechanism is related to thermochemical changes in the filament due to the Joule-heating effect. On the other hand, for bipolar behaviour, the electron conduction through the CF depends on redox effects or quantum point contact effects. In both cases, the switching mechanisms (SET and RESET processes) are related to the thermochemical oxygen diffusion in the CF. We can consider the CF as a 1D parameter because the material resistivity is area independent. It is very important to note that in CF programmable devices,

Ielmeni, Nardi and Cagli have been developed a physical model for NiO cells with very good concordance with experimental results [4]. In this material, the RESET process happens in small steps, whereas the change of states occurs suddenly during the SET process. The VRESETand IRESET parameters depend on the resistance material in the HRS. IRESET always decreases when the resistance increases. On the other hand, the VRESET in function of R curve has an U behaviour. That is, for low values of R, VRESET decreases when R increases, and for high values of R, VRESET increases when R increases. For the RESET process, the CF tempera-

T ¼ T<sup>0</sup> þ

VRESET ¼

where T<sup>0</sup> is the room temperature and Rth is the effective thermal resistance. By using Eq. (2),

where ΔTRESET is the critical temperature increment for the onset oxidation. The ratio R/Rth is almost constant according to the Wiedemann-Franz law for metals [4]. This means that VRESET is almost constant and IRESET decreases with respect to R. This is not true in experimental results. For explaining the increment of VRESET with respect to high values of R, we have to study the sizedependent Joule-heating effect. The parameter Rth is the parallel of two resistances: Rth<sup>0</sup> and Rth<sup>00</sup>, where Rth<sup>0</sup> only depends on the CF and Rth<sup>00</sup> depends on the rest of the material (bulk oxide). Rth<sup>0</sup> can be computed by considering the thermal nanofilament conductivity, kth, as follows [4]:

<sup>R</sup>th<sup>0</sup> <sup>¼</sup> th

where t<sup>h</sup> is the oxide thickness and ACF is CF area. As Rth is inverse proportional to ACF, for

of ACF, we have that Rth ≈ Rth<sup>00</sup>. As well, when kth increases, Rth<sup>0</sup> predominates over Rth<sup>00</sup>.

8kthACF

Rth

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi RΔTRESET Rth <sup>s</sup>

<sup>R</sup> <sup>V</sup><sup>2</sup> <sup>ð</sup>2<sup>Þ</sup>

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 9

. On the other hand, for low values

ð3Þ

ð4Þ

there exist a variability problem because not all filaments are equal or similar [5].

structural defects (grain boundaries or dislocations) [4].

4.1. Thermochemical oxygen diffusion model

we can obtain the VRESET voltage:

ture depends on the square of the applied voltage as follows [4]:

high values of ACF (low resistance) Rth is approximately Rth<sup>0</sup>

Sawa showed very good resistive switching results for Ti/Pr07Ca0.3MnO3/SrRuO3 (Ti/PCMO/ SRO) cells, where SRO has metal properties and PCMO acts as p-type semiconductor. As well, the SRO/SrTi0.99Nb0.01O3/Ag (SRO/Nb:STO/Ag) cell showed a good resistive switching behaviour where Nb:STO acts as an n-type semiconductor [3].

Another way to change the contact resistance is by adding a thin semiconductor layer of an oxide material between the metal and the insulator materials [3]. The semiconductor layer transforms the contact resistance from ohmic to a Schottky barrier. Without this layer, there is no switching resistance for some insulators. Sawa shows experimental results for Ti/ Sm0.7Ca0.3MnO3(n unit cells)/La0.7Sr0.3MnO3/SRO (Ti/SCMO(n)/LSMO/SRO) where SCMO is a p-type semiconductor [3]. It was demonstrated that for n ¼ 5 unit cells, there was a very good hysteresis in the I-V curve. As well, the SRO/SrTiO3/SrTi0.99Nb0.01O3/Ag (SRO/STO/Nb:STO) cell showed a resistivity changes but not a good hysteresis in the I-V curve [3].

## 4. One dimensional models for resistive switching materials

In several transition metal oxides, when a voltage is applied on the electrodes of a pristine MIM cell, the current measured is very low. When the voltage increases up to a threshold value, the electric field applied provokes a dielectric breakdown. When this occurs, a conduction filament (CF) is formed in the insulator as shown in Figure 5. The necessary potential to form this filament is called forming voltage (VF). The CF is formed due to the Joule-heating effect, which leads a temperature increment in the insulator. The dielectric breakdown is driven by a thermal runway. When a voltage is applied on a transition metal oxide, the resistance

Figure 5. Left: virgin cell. Right: Cell with conduction filament formed.

starts to decrease but not in a permanent way. In this process, the material temperature increases up to certain value (related to a threshold voltage) when a local redox reaction begins and causes structural defects (grain boundaries or dislocations) [4].

The voltage polarity to change states in cells with CF can be unipolar or bipolar. For unipolar behaviour, the electron conduction mechanism is related to thermochemical changes in the filament due to the Joule-heating effect. On the other hand, for bipolar behaviour, the electron conduction through the CF depends on redox effects or quantum point contact effects. In both cases, the switching mechanisms (SET and RESET processes) are related to the thermochemical oxygen diffusion in the CF. We can consider the CF as a 1D parameter because the material resistivity is area independent. It is very important to note that in CF programmable devices, there exist a variability problem because not all filaments are equal or similar [5].

#### 4.1. Thermochemical oxygen diffusion model

resistance (LRS). If an electric field is applied on the opposite direction, the number of oxygen vacancies in the n-type semiconductor decreases and provokes an increment of W<sup>d</sup> and, therefore, the contact resistance increases (HRS). On the other hand, for a p-type semiconductor, the increment of oxygen vacancies increases W<sup>d</sup> and the contact resistance (HRS), and a diminution of the oxygen vacancies decreases W<sup>d</sup> and the contact resistance (LRS). In this model, the metal work function plays a very important role because the band bending strongly

Sawa showed very good resistive switching results for Ti/Pr07Ca0.3MnO3/SrRuO3 (Ti/PCMO/ SRO) cells, where SRO has metal properties and PCMO acts as p-type semiconductor. As well, the SRO/SrTi0.99Nb0.01O3/Ag (SRO/Nb:STO/Ag) cell showed a good resistive switching behav-

Another way to change the contact resistance is by adding a thin semiconductor layer of an oxide material between the metal and the insulator materials [3]. The semiconductor layer transforms the contact resistance from ohmic to a Schottky barrier. Without this layer, there is no switching resistance for some insulators. Sawa shows experimental results for Ti/ Sm0.7Ca0.3MnO3(n unit cells)/La0.7Sr0.3MnO3/SRO (Ti/SCMO(n)/LSMO/SRO) where SCMO is a p-type semiconductor [3]. It was demonstrated that for n ¼ 5 unit cells, there was a very good hysteresis in the I-V curve. As well, the SRO/SrTiO3/SrTi0.99Nb0.01O3/Ag (SRO/STO/Nb:STO)

In several transition metal oxides, when a voltage is applied on the electrodes of a pristine MIM cell, the current measured is very low. When the voltage increases up to a threshold value, the electric field applied provokes a dielectric breakdown. When this occurs, a conduction filament (CF) is formed in the insulator as shown in Figure 5. The necessary potential to form this filament is called forming voltage (VF). The CF is formed due to the Joule-heating effect, which leads a temperature increment in the insulator. The dielectric breakdown is driven by a thermal runway. When a voltage is applied on a transition metal oxide, the resistance

cell showed a resistivity changes but not a good hysteresis in the I-V curve [3].

4. One dimensional models for resistive switching materials

depends on this parameter.

8 Memristor and Memristive Neural Networks

iour where Nb:STO acts as an n-type semiconductor [3].

Figure 5. Left: virgin cell. Right: Cell with conduction filament formed.

Ielmeni, Nardi and Cagli have been developed a physical model for NiO cells with very good concordance with experimental results [4]. In this material, the RESET process happens in small steps, whereas the change of states occurs suddenly during the SET process. The VRESETand IRESET parameters depend on the resistance material in the HRS. IRESET always decreases when the resistance increases. On the other hand, the VRESET in function of R curve has an U behaviour. That is, for low values of R, VRESET decreases when R increases, and for high values of R, VRESET increases when R increases. For the RESET process, the CF temperature depends on the square of the applied voltage as follows [4]:

$$T = T\_0 + \frac{R\_{\text{th}}}{R}V^2\tag{2}$$

where T<sup>0</sup> is the room temperature and Rth is the effective thermal resistance. By using Eq. (2), we can obtain the VRESET voltage:

$$V\_{RESET} = \sqrt{\frac{R\Delta T\_{RESET}}{R\_{th}}}\tag{3}$$

where ΔTRESET is the critical temperature increment for the onset oxidation. The ratio R/Rth is almost constant according to the Wiedemann-Franz law for metals [4]. This means that VRESET is almost constant and IRESET decreases with respect to R. This is not true in experimental results. For explaining the increment of VRESET with respect to high values of R, we have to study the sizedependent Joule-heating effect. The parameter Rth is the parallel of two resistances: Rth<sup>0</sup> and Rth<sup>00</sup>, where Rth<sup>0</sup> only depends on the CF and Rth<sup>00</sup> depends on the rest of the material (bulk oxide). Rth<sup>0</sup> can be computed by considering the thermal nanofilament conductivity, kth, as follows [4]:

$$R\_{\rm th} \,' = \frac{t\_{\rm th}}{8k\_{\rm th}A\_{\rm CF}} \tag{4}$$

where t<sup>h</sup> is the oxide thickness and ACF is CF area. As Rth is inverse proportional to ACF, for high values of ACF (low resistance) Rth is approximately Rth<sup>0</sup> . On the other hand, for low values of ACF, we have that Rth ≈ Rth<sup>00</sup>. As well, when kth increases, Rth<sup>0</sup> predominates over Rth<sup>00</sup>.

For explaining the behaviour of the VRESET-R curve for low values of R, we have to consider that the ratio R/Rth is almost constant in Eq. (3) and ΔTRESET must increase in order to obtain a metal diffusion in the filament, which is a filament area dependent process. Hence, VRESET increases for low values of R. This size-dependent diffusion is considering in following Arrhenius expression developed in Ref. [4]:

$$T\_{RESET} = \frac{E\_A}{k \log\left(\frac{t\_{RESET}}{t\_0} \left(\frac{\rho\_0}{\rho}\right)^2\right)}\tag{5}$$

data, that necessary power for the setting process (PSET) is directly proportional to R�0.5, which

<sup>¼</sup> ffiffiffiffiffiffiffiffiffiffiffiffi

r

The tendencies for VSET and ISET parameters in function of R were experimentally confirmed

In bipolar cells, the transition between the LRS and the HRS is commonly related to the formation and rupture of the CF. A typical material which presents a CF with bipolar behaviour is the HfO2. As well as in unipolar cells, oxygen vacancies play an important role. The most accepted theory for forming the CF in a virgin cell is that the oxygen atoms migrate from the CF to the insulator/metal interface due to the Joule-heating effect. When the CF is already formed, to change from the LRS to the HRS, the CF is oxidized (oxygen atoms migrate from the electrode to the CF), whereas to change from the HRS to the LRS, the CF is reduced leaving oxygen vacancies and forming percolation paths (oxygen atoms migrate from the CF to the

Guan, Yu and Wong have developed a model for explaining the carrier conduction through the CF in bipolar cells where the principal transport mechanism is the trap-assisted-tunnelling (TAT). The continuity transport equation in the oxide region is given by Guan et al. [6]:

where f<sup>n</sup> is the electron occupation probability of the nth trap, Rmn is the electron hopping rate

Rmnð<sup>1</sup> � <sup>f</sup> <sup>n</sup>ÞþðRiL

iR the electron hopping rate from the right/left electrode to trap n. It is well known that

<sup>n</sup> <sup>þ</sup> <sup>R</sup>iR

X N

�

n¼1

<sup>n</sup> <sup>þ</sup> RiR

oR are the electron hopping rate from trap n to the right/left electrode

<sup>n</sup> Þð<sup>1</sup> � <sup>f</sup> <sup>n</sup>Þ�ðRoL

<sup>ð</sup><sup>1</sup> � <sup>f</sup> <sup>n</sup>ÞRiR

<sup>n</sup> Þð<sup>1</sup> � <sup>f</sup> <sup>n</sup>Þ�ðRoL

<sup>n</sup> <sup>þ</sup> RoR

<sup>n</sup> � <sup>f</sup> <sup>n</sup>RoR n �

<sup>n</sup> <sup>þ</sup> <sup>R</sup>oR <sup>n</sup> Þf <sup>n</sup>

<sup>n</sup> Þf <sup>n</sup> ¼ 0 ð12Þ

ð11Þ

ð13Þ

ffiffiffiffiffiffiffiffiffi PSET R

<sup>P</sup>SET<sup>R</sup> <sup>p</sup> <sup>∝</sup> <sup>R</sup><sup>0</sup>:<sup>25</sup> <sup>ð</sup>9<sup>Þ</sup>

<sup>∝</sup>R�0:<sup>75</sup> <sup>ð</sup>10<sup>Þ</sup>

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 11

<sup>V</sup>SET <sup>¼</sup> <sup>P</sup>SET ISET

<sup>I</sup>SET <sup>¼</sup> <sup>P</sup>SET VSET ¼

means that [4]:

electrode).

df <sup>n</sup>

and R<sup>n</sup>

dt ¼ ð<sup>1</sup> � <sup>f</sup> <sup>n</sup><sup>Þ</sup> <sup>X</sup>

from trap m to trap n, R<sup>n</sup>

N

<sup>m</sup>¼<sup>1</sup>, <sup>m</sup>6¼<sup>n</sup>

I ¼ I <sup>L</sup> <sup>¼</sup> <sup>I</sup>

iL/R<sup>n</sup>

<sup>ð</sup><sup>1</sup> � <sup>f</sup> <sup>n</sup><sup>Þ</sup> <sup>X</sup>

N

<sup>m</sup>¼<sup>1</sup>, <sup>m</sup>6¼<sup>n</sup>

Rmnf <sup>m</sup> � f <sup>n</sup>

X N

<sup>m</sup>¼<sup>1</sup>, <sup>m</sup>6¼<sup>n</sup>

oL/R<sup>n</sup>

Rmnf <sup>m</sup> � f <sup>n</sup>

<sup>R</sup> ¼ �<sup>q</sup>

X N

n¼1

X N

<sup>m</sup>¼<sup>1</sup>, <sup>m</sup>6¼<sup>n</sup>

oxygen vacancies contribute to the TAT. In quasi-steady state, Eq. (11) transform to [6]:

The current can be computed by evaluating the electron flow near the electrode:

<sup>ð</sup><sup>1</sup> � <sup>f</sup> <sup>n</sup>ÞRiL

Rmnð<sup>1</sup> � <sup>f</sup> <sup>n</sup>ÞþðRiL

<sup>n</sup> � <sup>f</sup> <sup>n</sup>RoL n

� � ¼ �<sup>q</sup>

the Ielmini group in Ref. [4].

4.2. Trap-assisted-tunnelling model

where E<sup>A</sup> is the activation energy, k the Boltzmann constant, t<sup>0</sup> and ϕ<sup>0</sup> are constants, ϕ is the CF diameter and tRESET¼ 1s is the reset time. Ielmini et al. showed very good results between their model and experimental data of NiO devices [4].

The electron conduction mechanism in the LRS strongly depends on the activation energy. For low values of EA, the filament has a metallic behaviour and the resistance is given by:

$$R = R\_{0m}(1 + \alpha(T - T\_0))\tag{6}$$

where T<sup>0</sup> is the room temperature, R0m is the metallic resistant at T<sup>0</sup> and α is the temperature coefficient. On the other hand, for high values of EA, electron conduction is driven by the Pool-Frenkel model in semiconductors and the resistance follows the following equation:

$$R = R\_{0s} \exp\left(\frac{E\_{A\mathcal{C}}}{kT}\right) \tag{7}$$

where R0s is the extrapolated resistance at infinite T, k is the Boltzmann constant and EAC is the activation energy for conduction. Both conduction behaviours are related to position of Fermi level (EF). Inside the CF filament, there are oxygen vacancies, whereas the bulk oxide is doped by oxygen. An insulator doped by oxygen behaves as a p-type semiconductor and, on the other hand, oxygen vacancies provoke an n-type behaviour. Therefore, the conduction filament in LRS behaves as an n-type semiconductor and the electron conduction is modulated by the concentration of oxygen vacancies, which is directly related to the E<sup>F</sup> position. When the oxygen vacancies concentration is too high, the CF behaves as a degenerately doped semiconductor and E<sup>F</sup> is very close or above the conduction band [4].

As was mentioned before, the SET process happens suddenly and it strongly depends on the resistance of the HRS (before the SET process). The HRS resistance can be described by the Pool-Frenkel model and is given by Ielmini et al. [4]:

$$R = \frac{kT\tau\_0 t\_h}{q^2 A\_{\text{CF}} N\_T \Delta z^2} \exp\left(\frac{E\_{A\text{C}}}{kT}\right) \tag{8}$$

where τ<sup>0</sup> is the attempt-to-escape characteristic time for a carrier from a specific state, t<sup>h</sup> is the material thickness (or filament length), NT is the dopant density, ACF is the filament area and Δz is the distance between positive charged defects. Ielmini et al. showed, from experimental data, that necessary power for the setting process (PSET) is directly proportional to R�0.5, which means that [4]:

$$V\_{\rm SET} = \frac{P\_{\rm SET}}{I\_{\rm SET}} = \sqrt{P\_{\rm SET}R} \propto R^{0.25} \tag{9}$$

$$I\_{\rm SET} = \frac{P\_{\rm SET}}{V\_{\rm SET}} = \sqrt{\frac{P\_{\rm SET}}{R}} \propto R^{-0.75} \tag{10}$$

The tendencies for VSET and ISET parameters in function of R were experimentally confirmed the Ielmini group in Ref. [4].

#### 4.2. Trap-assisted-tunnelling model

For explaining the behaviour of the VRESET-R curve for low values of R, we have to consider that the ratio R/Rth is almost constant in Eq. (3) and ΔTRESET must increase in order to obtain a metal diffusion in the filament, which is a filament area dependent process. Hence, VRESET increases for low values of R. This size-dependent diffusion is considering in following Arrhe-

> <sup>k</sup>log tRESET t0

where E<sup>A</sup> is the activation energy, k the Boltzmann constant, t<sup>0</sup> and ϕ<sup>0</sup> are constants, ϕ is the CF diameter and tRESET¼ 1s is the reset time. Ielmini et al. showed very good results between their

The electron conduction mechanism in the LRS strongly depends on the activation energy. For

where T<sup>0</sup> is the room temperature, R0m is the metallic resistant at T<sup>0</sup> and α is the temperature coefficient. On the other hand, for high values of EA, electron conduction is driven by the Pool-

where R0s is the extrapolated resistance at infinite T, k is the Boltzmann constant and EAC is the activation energy for conduction. Both conduction behaviours are related to position of Fermi level (EF). Inside the CF filament, there are oxygen vacancies, whereas the bulk oxide is doped by oxygen. An insulator doped by oxygen behaves as a p-type semiconductor and, on the other hand, oxygen vacancies provoke an n-type behaviour. Therefore, the conduction filament in LRS behaves as an n-type semiconductor and the electron conduction is modulated by the concentration of oxygen vacancies, which is directly related to the E<sup>F</sup> position. When the oxygen vacancies concentration is too high, the CF behaves as a degenerately doped semicon-

As was mentioned before, the SET process happens suddenly and it strongly depends on the resistance of the HRS (before the SET process). The HRS resistance can be described by the

<sup>q</sup><sup>2</sup>ACFNTΔz<sup>2</sup> exp

where τ<sup>0</sup> is the attempt-to-escape characteristic time for a carrier from a specific state, t<sup>h</sup> is the material thickness (or filament length), NT is the dopant density, ACF is the filament area and Δz is the distance between positive charged defects. Ielmini et al. showed, from experimental

EAC kT � �

<sup>R</sup> <sup>¼</sup> kTτ0th

EAC kT � �

low values of EA, the filament has a metallic behaviour and the resistance is given by:

Frenkel model in semiconductors and the resistance follows the following equation:

R ¼ R0<sup>s</sup> exp

φ0 φ

� �<sup>2</sup> ! <sup>ð</sup>5<sup>Þ</sup>

R ¼ R0mð Þ 1 þ αð Þ T � T<sup>0</sup> ð6Þ

ð7Þ

ð8Þ

TRESET <sup>¼</sup> EA

nius expression developed in Ref. [4]:

10 Memristor and Memristive Neural Networks

model and experimental data of NiO devices [4].

ductor and E<sup>F</sup> is very close or above the conduction band [4].

Pool-Frenkel model and is given by Ielmini et al. [4]:

In bipolar cells, the transition between the LRS and the HRS is commonly related to the formation and rupture of the CF. A typical material which presents a CF with bipolar behaviour is the HfO2. As well as in unipolar cells, oxygen vacancies play an important role. The most accepted theory for forming the CF in a virgin cell is that the oxygen atoms migrate from the CF to the insulator/metal interface due to the Joule-heating effect. When the CF is already formed, to change from the LRS to the HRS, the CF is oxidized (oxygen atoms migrate from the electrode to the CF), whereas to change from the HRS to the LRS, the CF is reduced leaving oxygen vacancies and forming percolation paths (oxygen atoms migrate from the CF to the electrode).

Guan, Yu and Wong have developed a model for explaining the carrier conduction through the CF in bipolar cells where the principal transport mechanism is the trap-assisted-tunnelling (TAT). The continuity transport equation in the oxide region is given by Guan et al. [6]:

$$\frac{df\_n}{dt} = (1 - f\_n) \sum\_{m=1, m \neq n}^{N} R\_{nm} f\_m - f\_n \sum\_{m=1, m \neq n}^{N} R\_{nm} (1 - f\_n) + (R\_n^{\text{IL}} + R\_n^{\text{iR}}) (1 - f\_n) - (R\_n^{\text{oL}} + R\_n^{\text{aR}}) f\_n \tag{11}$$

where f<sup>n</sup> is the electron occupation probability of the nth trap, Rmn is the electron hopping rate from trap m to trap n, R<sup>n</sup> oL/R<sup>n</sup> oR are the electron hopping rate from trap n to the right/left electrode and R<sup>n</sup> iL/R<sup>n</sup> iR the electron hopping rate from the right/left electrode to trap n. It is well known that oxygen vacancies contribute to the TAT. In quasi-steady state, Eq. (11) transform to [6]:

$$(1 - f\_n) \sum\_{m=1, m \neq n}^{N} R\_{m} f\_m - f\_n \sum\_{m=1, m \neq n}^{N} R\_{m} (1 - f\_n) + (R\_n^{\text{il}} + R\_n^{\text{il}}) (1 - f\_n) - (R\_n^{\text{ol}} + R\_n^{\text{ol}}) f\_n = 0 \quad (12)$$

The current can be computed by evaluating the electron flow near the electrode:

$$I = I^L = I^R = -q\sum\_{n=1}^{N} \left( (1 - f\_n)R\_n^{\text{il}} - f\_n R\_n^{\text{ol}} \right) = -q\sum\_{n=1}^{N} \left( (1 - f\_n)R\_n^{\text{il}} - f\_n R\_n^{\text{ol}} \right) \tag{13}$$

The hopping rate can be computed by the Mott hopping model as [7]:

$$R\_{mn} = R\_0 \exp\left(-\frac{r\_{mn}}{a\_0} + \frac{qV\_{mn}^H}{kT}\right) \tag{14}$$

According to Guan et al. model, the generation oxygen vacancies are given by [7]:

t0

<sup>R</sup> <sup>¼</sup> PGðFeq <sup>¼</sup> <sup>0</sup>,T, tÞ ¼ <sup>t</sup>

where the time, <sup>t</sup>, is within the interval [τ, <sup>τ</sup> <sup>þ</sup> <sup>t</sup>], Feq is the local electric field of an ion, 1/t0<sup>≈</sup> 1013Hz is the oxygen vibration frequency, E<sup>a</sup> ≈ 1eV is a parameter related to the height of the potential barrier and γ is a coefficient which represents the local enhancement due to the

On the other hand, during the equilibrium state (absence of Feq), the oxygen vacancy recombi-

PR <sup>¼</sup> <sup>β</sup>P<sup>0</sup> R

where β is a parameter related to concentration of oxygen ions which can be computed by the

where L<sup>p</sup> is decaying length of ion concentration, u(x,t) is a function related to the oxygen diffusion and can be approximated by the complementary error function. v is velocity of the

where a is the lattice constant, E<sup>m</sup> is the migration barrier, γdrift is the enhancement coefficient related to the dielectric material and F is the electric field left by an oxygen ion. Eq. (13) is coupled with the solution of the Poisson equation to obtain the potential distribution in

�∇<sup>2</sup>

<sup>V</sup> <sup>¼</sup> <sup>ρ</sup>

where ρ is the volumetric charge density and ε is the material permittivity. The border conditions for Eq. (24) are: <sup>V</sup>(x¼0)¼V<sup>L</sup> and <sup>V</sup>(x¼L)¼VR. Guan et al. showed very god results of their

<sup>β</sup>ðx, tÞ ¼ <sup>β</sup><sup>0</sup> exp � vt

t0

Lp

exp �ðEa � <sup>γ</sup>jFeq ðÞ ð jÞ=kT <sup>20</sup><sup>Þ</sup>

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 13

exp ð Þ �Ea=kT ð21Þ

<sup>u</sup>ðx, tÞ ð22<sup>Þ</sup>

<sup>ε</sup> <sup>ð</sup>24<sup>Þ</sup>

exp ð Þ �Em=kT sinh <sup>q</sup>γdrif tF=kT <sup>ð</sup>23<sup>Þ</sup>

PGðFeq,T, tÞ ¼ <sup>t</sup>

electric field. This rate dominates the SET process.

P0

Therefore, the recombination rate for a non-equilibrium state is [7]:

nation rate is given by Guan et al. [6]:

following approximation [6]:

the cell:

oxygen ions waveform given by Yu et al. [7]:

model for experimental data of HfOx devices [7].

<sup>v</sup> <sup>¼</sup> <sup>a</sup> t0

where <sup>R</sup><sup>0</sup> <sup>≈</sup> 1012Hz is the vibration electron frequency, <sup>r</sup>mn <sup>¼</sup> <sup>|</sup>rm�rn| is the distance between vacancies <sup>n</sup> and <sup>m</sup>, <sup>a</sup><sup>0</sup> is the attenuation length wave function, <sup>V</sup>mnH<sup>≈</sup> �FH(rm�rn) <sup>≈</sup> <sup>V</sup>H(rm)� VH(rn) is the barrier change due to an external electric field and VH(rn) is the homogeneous component of the potential solution of the Poisson equation. The hopping rates from a trap to an electrode are [6]:

$$\begin{aligned} R\_{\boldsymbol{n}}^{\mathcal{U},R} &= R\_{\text{tunnel}}^{0} N^{L,R}(E\_{\boldsymbol{v}}^{+}) F\_{\text{in}}^{L,R}(E\_{\boldsymbol{v}}^{+}) T\_{\boldsymbol{n}}^{L,R,+} \\ R\_{\boldsymbol{n}}^{\mathcal{U},R} &= R\_{\text{tunnel}}^{0} N^{L,R}(E\_{\boldsymbol{v}}^{\bullet}) F\_{\text{out}}^{L,R}(E\_{\boldsymbol{v}}^{\bullet}) T\_{\boldsymbol{n}}^{L,R,\bullet} \end{aligned} \tag{15}$$

where e R0 tunnel is the tunnel coupling strength between a trap and an electrode, NL,R is the number of states at a given energy in an electrode and E<sup>v</sup> <sup>þ</sup>/E<sup>v</sup> • are the energy of an empty/ filled trap given by Guan et al. [6]:

$$E\_v^{+,\bullet}(r\_n) = E\_v^{+,\bullet} - qV^H(r\_n) \tag{16}$$

Tn L,R,þ• is the tunnel probability from the left/right electrode into a trap given by the Wentzel-Kramers-Brilloin approximation [6]:

$$\begin{aligned} T\_{n}^{L+,\bullet} &= \exp\left[ \int\_{0}^{x\_{n}} \frac{1}{h} \sqrt{2m^{\*}\left[E\_{\mathbb{C}} - E\_{v0}^{+,\bullet} - qV^{H}(\mathbf{x}\_{n})\right]} d\mathbf{x} \right], \quad E\_{v}^{\pm} < E\_{\mathbb{C}} - qV^{H}(\mathbf{x}) \\\ T\_{n}^{R+,\bullet} &= \exp\left[ \int\_{x\_{n}}^{L} \frac{1}{h} \sqrt{2m^{\*}\left[E\_{\mathbb{C}} - E\_{v0}^{+,\bullet} - qV^{H}(\mathbf{x}\_{n})\right]} d\mathbf{x} \right], \quad E\_{v}^{\pm} < E\_{\mathbb{C}} - qV^{H}(\mathbf{x}) \end{aligned} \tag{17}$$

where xn is the xth component of rn, L is the oxide thickness and m\* is the tunnelling effective mass in the oxide. Fin L,R is the Fermi integral which represents the filled states in an electrode above E<sup>v</sup> þ and takes into account the inject electrons from the electrode into the trap n:

$$F\_{\dot{m}}^{L,R}(E\_v^+) = \int\_{E\_{\rm out}^+ - qV(\mathbf{x}\_v)}^{+\alpha} f\left(E - (E\_F^{L,R} - qV^{L,R})\right) dE = \int\_{E\_{\rm out}^+ - qV(\mathbf{x}\_v)}^{+\alpha} \frac{1}{1 + \exp\left((E - (E\_F^{L,R} - qV^{L,R})/kT)\right)} dE \tag{18}$$

where E<sup>F</sup> L,R is the Fermi level of the right/left electrode and VL,R is the applied voltage on the left/right electrode. On the other hand, FoutL,R is the Fermi integral which takes into account the number of empty states in an electrode bellow E<sup>v</sup> � which can accept electrons from the trap n:

$$F\_{\rm out}^{L,R}(E\_v^-) = \int\_{-\infty}^{E\_0 - qV(\mathbf{x}\_n)} \left[1 - f\left(\mathbf{E} - (E\_F^{L,R} - qV^{L,R})\right)\right] d\mathbf{E} = \int\_{-\infty}^{E\_0 - qV(\mathbf{x}\_n)} \frac{1}{1 + \exp\left((E\_F^{L,R} - qV^{L,R}) - E/kT\right)} d\mathbf{E} \tag{19}$$

According to Guan et al. model, the generation oxygen vacancies are given by [7]:

The hopping rate can be computed by the Mott hopping model as [7]:

<sup>R</sup>iL,R <sup>n</sup> <sup>¼</sup> <sup>R</sup><sup>0</sup>

RoL,R <sup>n</sup> <sup>¼</sup> <sup>R</sup><sup>0</sup>

E<sup>þ</sup>,•

<sup>2</sup>m� EC � <sup>E</sup><sup>þ</sup>,•

<sup>2</sup>m� EC � <sup>E</sup><sup>þ</sup>,•

<sup>F</sup> � qVL,R � �dE <sup>¼</sup>

<sup>F</sup> � qVL,R � � � � dE <sup>¼</sup>

number of states at a given energy in an electrode and E<sup>v</sup>

ðxn 0 1 h

ðL xn 1 h

f E � ðEL,R

number of empty states in an electrode bellow E<sup>v</sup>

<sup>1</sup> � f E � ðEL,R

an electrode are [6]:

12 Memristor and Memristive Neural Networks

filled trap given by Guan et al. [6]:

Kramers-Brilloin approximation [6]:

<sup>T</sup><sup>L</sup>þ,• <sup>n</sup> <sup>¼</sup> exp

<sup>T</sup><sup>R</sup>þ,• <sup>n</sup> <sup>¼</sup> exp

þ ð∞

Eþ <sup>v</sup>0�qVðxnÞ

ð E� <sup>v</sup>0�qVðxnÞ

�∞

mass in the oxide. Fin

above E<sup>v</sup>

FL,R in ðE<sup>þ</sup> <sup>v</sup> Þ ¼

where E<sup>F</sup>

FL,R out ðE� <sup>v</sup> Þ ¼

where e R0

Tn

Rmn <sup>¼</sup> <sup>R</sup><sup>0</sup> exp � rmn

a0

<sup>v</sup> <sup>Þ</sup>FL,R in ðE<sup>þ</sup>

<sup>v</sup> <sup>Þ</sup>FL,R outðE•

tunnel is the tunnel coupling strength between a trap and an electrode, NL,R is the

<sup>v</sup> <sup>Þ</sup>TL,R,<sup>þ</sup> <sup>n</sup>

<sup>v</sup> <sup>Þ</sup>TL,R,• <sup>n</sup>

<sup>þ</sup>/E<sup>v</sup>

, E�

; E�

<sup>1</sup> <sup>þ</sup> exp <sup>ð</sup><sup>E</sup> � ðEL,R

<sup>1</sup> <sup>þ</sup> exp <sup>ð</sup>EL,R

L,R is the Fermi integral which represents the filled states in an electrode

where <sup>R</sup><sup>0</sup> <sup>≈</sup> 1012Hz is the vibration electron frequency, <sup>r</sup>mn <sup>¼</sup> <sup>|</sup>rm�rn| is the distance between vacancies <sup>n</sup> and <sup>m</sup>, <sup>a</sup><sup>0</sup> is the attenuation length wave function, <sup>V</sup>mnH<sup>≈</sup> �FH(rm�rn) <sup>≈</sup> <sup>V</sup>H(rm)� VH(rn) is the barrier change due to an external electric field and VH(rn) is the homogeneous component of the potential solution of the Poisson equation. The hopping rates from a trap to

tunnelNL,RðE<sup>þ</sup>

tunnelNL,RðE•

<sup>v</sup> <sup>ð</sup>rnÞ ¼ <sup>E</sup><sup>þ</sup>,•

L,R,þ• is the tunnel probability from the left/right electrode into a trap given by the Wentzel-

<sup>v</sup><sup>0</sup> � qV<sup>H</sup>ðxn<sup>Þ</sup>

<sup>v</sup><sup>0</sup> � qV<sup>H</sup>ðxn<sup>Þ</sup>

where xn is the xth component of rn, L is the oxide thickness and m\* is the tunnelling effective

þ and takes into account the inject electrons from the electrode into the trap n:

Eþ <sup>v</sup>0�qVðxnÞ

left/right electrode. On the other hand, FoutL,R is the Fermi integral which takes into account the

þ ð∞

L,R is the Fermi level of the right/left electrode and VL,R is the applied voltage on the

ð E� <sup>v</sup>0�qVðxnÞ

�∞

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

<sup>q</sup> � �dx � �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

<sup>q</sup> � �dx � �

<sup>þ</sup> qV<sup>H</sup> mn kT

ð14Þ

ð15Þ

ð17Þ

ð18Þ

ð19Þ

• are the energy of an empty/

<sup>v</sup> � qV<sup>H</sup>ðrnÞ ð16<sup>Þ</sup>

<sup>v</sup> <sup>&</sup>lt; EC � qV<sup>H</sup>ðx<sup>Þ</sup>

<sup>v</sup> <sup>&</sup>lt; EC � qV<sup>H</sup>ðx<sup>Þ</sup>

1

� which can accept electrons from the trap n:

1

<sup>F</sup> � qVL,RÞ � <sup>E</sup>=kT � � dE

<sup>F</sup> � qVL,RÞ=kT � � dE

� �

$$P\_G(F^{\mathrm{eq}}, T, t) = \frac{t}{t\_0} \exp\left(-(E\_d - \gamma |F^{\mathrm{eq}}|) / kT\right) \tag{20}$$

where the time, <sup>t</sup>, is within the interval [τ, <sup>τ</sup> <sup>þ</sup> <sup>t</sup>], Feq is the local electric field of an ion, 1/t0<sup>≈</sup> 1013Hz is the oxygen vibration frequency, E<sup>a</sup> ≈ 1eV is a parameter related to the height of the potential barrier and γ is a coefficient which represents the local enhancement due to the electric field. This rate dominates the SET process.

On the other hand, during the equilibrium state (absence of Feq), the oxygen vacancy recombination rate is given by Guan et al. [6]:

$$P\_R^0 = P\_G(F^{\neq} = 0, T, t) = \frac{t}{t\_0} \exp\left(-E\_a/kT\right) \tag{21}$$

Therefore, the recombination rate for a non-equilibrium state is [7]:

$$P\_{\mathbb{R}} = \beta P\_{\mathbb{R}}^0$$

where β is a parameter related to concentration of oxygen ions which can be computed by the following approximation [6]:

$$\beta(\mathbf{x},t) = \beta\_0 \exp\left(-\frac{vt}{L\_p}\right) \mu(\mathbf{x},t) \tag{22}$$

where L<sup>p</sup> is decaying length of ion concentration, u(x,t) is a function related to the oxygen diffusion and can be approximated by the complementary error function. v is velocity of the oxygen ions waveform given by Yu et al. [7]:

$$v = \frac{a}{t\_0} \exp\left(-E\_m/kT\right) \sinh\left(q\gamma^{d\dot{r}\dot{f}t}F/kT\right) \tag{23}$$

where a is the lattice constant, E<sup>m</sup> is the migration barrier, γdrift is the enhancement coefficient related to the dielectric material and F is the electric field left by an oxygen ion. Eq. (13) is coupled with the solution of the Poisson equation to obtain the potential distribution in the cell:

$$-\nabla^2 V = \frac{\rho}{\varepsilon} \tag{24}$$

where ρ is the volumetric charge density and ε is the material permittivity. The border conditions for Eq. (24) are: <sup>V</sup>(x¼0)¼V<sup>L</sup> and <sup>V</sup>(x¼L)¼VR. Guan et al. showed very god results of their model for experimental data of HfOx devices [7].

#### 4.3. Quantum point contact model

The complete quantum point contact (QPC) model was developed by Miranda and Suñe [8]. Originally, the model was developed for explaining the soft and hard-dielectric-breakdown in SiO2. If the dimension of the narrowest point of the CF is in the order of the Fermi wavelength, λF, quantum point contact effects are presented. There are some experimental works, where the QPC model could explain well the transport conduction in the HRS and LRS for HfO2 devices [9–11].

potential barrier. By assuming a parabolic potential barrier in the narrow constriction and by using the Landauer formalism for 1D quantum conductors and the zero-temperature limit for

> ð<sup>e</sup>ðV�IRÞ=<sup>2</sup> �eðV�IRÞ=2

where T(E) is the electron transmission probability, N is the number of active channels in the filament and h is the Planck's constant. For a parabolic potential barrier, there is an analytical

where α is a shape parameter related to tB. By integrating over the total energy window, we

If we consider V ≫ IR and only one active filament for the HRS (not multiple filaments), we

For the LRS, we suppose an ideally ballistic transport that (T(E) ≈ 1) and the current is [9, 10]:

We show in Figure 7 experimental results of I-V curves for the HRS and LRS and its fitting with the QPC model for HfO2 cells. We have found in Ref. [10] that <sup>α</sup>∝Φ<sup>n</sup> with <sup>n</sup> ¼ �0.35.

where m\* is the electron effective mass in the constriction. Moreover, the constriction radius, rB,

where z0¼ 2.404 is the first zero of the Bessel function J0. In Ref. [10], we have experimentally found that rB¼ 1.14 nm with a standard deviation of 0.06 nm for bipolar HfO2 cells, which

rB <sup>¼</sup> hzo

ffiffiffiffiffiffi 2Φ m�

r

2π ffiffiffiffiffiffiffiffiffiffiffiffiffiffi

<sup>I</sup> <sup>≈</sup> NGo

There is a QPC expression which relates Φ and α by considering t<sup>B</sup> constant [9, 10]:

tB <sup>¼</sup> <sup>h</sup><sup>α</sup> 2π<sup>2</sup>

� � � �

ln <sup>1</sup> <sup>þ</sup> exp f g <sup>α</sup>½ � <sup>Φ</sup> � eV=<sup>2</sup> 1 þ exp f g α½ � Φ þ eV=2

� � � �

TðEÞdE ð25Þ

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025

ð27Þ

15

ð28Þ

ð30Þ

<sup>T</sup>ðEÞ ¼ <sup>1</sup> <sup>þ</sup> exp ð�αð Þ <sup>E</sup> � <sup>Φ</sup> � ��<sup>1</sup> <sup>ð</sup>26<sup>Þ</sup>

<sup>1</sup> <sup>þ</sup> NGoR <sup>V</sup> <sup>ð</sup>29<sup>Þ</sup>

<sup>2</sup><sup>m</sup> � <sup>Φ</sup> <sup>p</sup> <sup>ð</sup>31<sup>Þ</sup>

ln <sup>1</sup> <sup>þ</sup> exp f g <sup>α</sup>½ � <sup>Φ</sup> � <sup>e</sup>ð<sup>V</sup> � IRÞ=<sup>2</sup> 1 þ exp f g α½ � Φ þ eðV � IRÞ=2

the parabolic potential barrier, the current through the filament is [9, 10]:

<sup>I</sup> <sup>¼</sup> <sup>2</sup><sup>e</sup> h N

expression for T(E):

obtain [9, 10]:

where <sup>G</sup>0<sup>¼</sup> <sup>2</sup>q<sup>2</sup>

have that the filament current is [9, 10]:

<sup>I</sup> <sup>¼</sup> <sup>2</sup>eN

<sup>h</sup> <sup>e</sup>ð<sup>V</sup> � IRÞ þ <sup>1</sup>

<sup>h</sup> eV <sup>þ</sup>

/h is the quantum conductance unit.

can be extracted by using another QPC equation [9, 10]:

<sup>I</sup> <sup>≈</sup> <sup>2</sup><sup>e</sup>

α

1 α

According to the QPC model, the first quantized sub-band behaves as a potential barrier for the incoming electrons as shown in Figure 6. We used a parabolic potential as potential barrier with the following physical parameters: Φ being the potential barrier height measured at the Fermi level, t<sup>B</sup> is the potential thickness at the Fermi level, R is a series resistance external to the constriction, V is the applied voltage on the electrodes, q is the elementary electron charge and I is the filament current that flows in the x direction.

The potential barrier height is defined by the cross-sectional area of the constriction and determines two conduction states. For the HRS, the top of the potential barrier is above or inside the energy window and the dominant conduction mechanism is tunnelling (this description is valid only for low-voltages). On the other hand, if the top of the potential barrier is below the energy window, the cell is in the LRS and the conduction mechanism is essentially ballistic (transmission probability close to 1). The conduction in the LRS is independent of the

Figure 6. Energy band diagram of the narrow constriction, where V is the applied voltage on the electrodes, R is an external series resistance that takes into account the non-idealities of the model, I is the filament current, e(V-IR) is the energy window associated to the electron conduction (shaded region), EF is the Fermi level, Φ is the potential height with respect to EF, tB is the potential thickness at EF and e is the elementary electron charge. The conduction is in the x direction. The top of the potential barrier is above or inside the energy window for the HRS and below for the LRS.

potential barrier. By assuming a parabolic potential barrier in the narrow constriction and by using the Landauer formalism for 1D quantum conductors and the zero-temperature limit for the parabolic potential barrier, the current through the filament is [9, 10]:

$$I = \frac{2\varepsilon}{h} N \int\_{-\epsilon(V - IR)/2}^{\epsilon(V - IR)/2} T(E)dE \tag{25}$$

where T(E) is the electron transmission probability, N is the number of active channels in the filament and h is the Planck's constant. For a parabolic potential barrier, there is an analytical expression for T(E):

$$T(E) = \left(1 + \exp\left(-a(E-\Phi)\right)\right)^{-1} \tag{26}$$

where α is a shape parameter related to tB. By integrating over the total energy window, we have that the filament current is [9, 10]:

$$I = \frac{2eN}{h} \left\{ e(V - IR) + \frac{1}{\alpha} \ln \left[ \frac{1 + \exp\left\{ a[\Phi - e(V - IR)/2] \right\}}{1 + \exp\left\{ a[\Phi + e(V - IR)/2] \right\}} \right] \right\} \tag{27}$$

If we consider V ≫ IR and only one active filament for the HRS (not multiple filaments), we obtain [9, 10]:

$$I \approx \frac{2e}{h} \left\{ eV + \frac{1}{\alpha} \ln \left[ \frac{1 + \exp\left\{ \alpha [\Phi - eV/2] \right\}}{1 + \exp\left\{ \alpha [\Phi + eV/2] \right\}} \right] \right\} \tag{28}$$

For the LRS, we suppose an ideally ballistic transport that (T(E) ≈ 1) and the current is [9, 10]:

$$I \approx \frac{NG\_o}{1 + NG\_oR}V\tag{29}$$

where <sup>G</sup>0<sup>¼</sup> <sup>2</sup>q<sup>2</sup> /h is the quantum conductance unit.

4.3. Quantum point contact model

14 Memristor and Memristive Neural Networks

is the filament current that flows in the x direction.

devices [9–11].

The complete quantum point contact (QPC) model was developed by Miranda and Suñe [8]. Originally, the model was developed for explaining the soft and hard-dielectric-breakdown in SiO2. If the dimension of the narrowest point of the CF is in the order of the Fermi wavelength, λF, quantum point contact effects are presented. There are some experimental works, where the QPC model could explain well the transport conduction in the HRS and LRS for HfO2

According to the QPC model, the first quantized sub-band behaves as a potential barrier for the incoming electrons as shown in Figure 6. We used a parabolic potential as potential barrier with the following physical parameters: Φ being the potential barrier height measured at the Fermi level, t<sup>B</sup> is the potential thickness at the Fermi level, R is a series resistance external to the constriction, V is the applied voltage on the electrodes, q is the elementary electron charge and I

The potential barrier height is defined by the cross-sectional area of the constriction and determines two conduction states. For the HRS, the top of the potential barrier is above or inside the energy window and the dominant conduction mechanism is tunnelling (this description is valid only for low-voltages). On the other hand, if the top of the potential barrier is below the energy window, the cell is in the LRS and the conduction mechanism is essentially ballistic (transmission probability close to 1). The conduction in the LRS is independent of the

Figure 6. Energy band diagram of the narrow constriction, where V is the applied voltage on the electrodes, R is an external series resistance that takes into account the non-idealities of the model, I is the filament current, e(V-IR) is the energy window associated to the electron conduction (shaded region), EF is the Fermi level, Φ is the potential height with respect to EF, tB is the potential thickness at EF and e is the elementary electron charge. The conduction is in the x direction. The top of the potential barrier is above or inside the energy window for the HRS and below for the LRS.

We show in Figure 7 experimental results of I-V curves for the HRS and LRS and its fitting with the QPC model for HfO2 cells. We have found in Ref. [10] that <sup>α</sup>∝Φ<sup>n</sup> with <sup>n</sup> ¼ �0.35. There is a QPC expression which relates Φ and α by considering t<sup>B</sup> constant [9, 10]:

$$t\_B = \frac{h\alpha}{2\pi^2} \sqrt{\frac{2\Phi}{m\*}}\tag{30}$$

where m\* is the electron effective mass in the constriction. Moreover, the constriction radius, rB, can be extracted by using another QPC equation [9, 10]:

$$r\_B = \frac{hz\_0}{2\pi\sqrt{2m\*\Phi}}\tag{31}$$

where z0¼ 2.404 is the first zero of the Bessel function J0. In Ref. [10], we have experimentally found that rB¼ 1.14 nm with a standard deviation of 0.06 nm for bipolar HfO2 cells, which

Figure 7. Experimental and theoretical I-V characteristics for the (a) HRS and (b) LRS. The QPC model (Eqs. (28) and (29)) was used for theoretical curves.

agrees with the quantum approach of this model. Miranda et al. showed that Φ has a linear dependence with respect to the temperature given by Avellán et al. [12]:

$$
\Phi(T) = \Phi\_0 - \gamma T \tag{32}
$$

The principal component of 1D models is the presence of a conduction filament. The filament is formed in a virgin cell by applying a certain threshold voltage. Depending on the cell polarity, the transport mechanisms can be: thermochemical diffusion of oxygen, filament oxidation-reduction or quantum point contact. For unipolar cells (like NiO cells), the resistive switching and the carrier conduction are controlled by the thermochemical diffusion of oxygen in the CF due to the Joule-heating effect. For bipolar cells (like HfO2), the switching mechanism is related to the oxidation/reduction of CF. If the CF radius at the narrowest part of the CF is in the order of the Fermi wavelength, the transport is driven by the quantum point contact effect,

Physical Models for Resistive Switching Devices http://dx.doi.org/10.5772/intechopen.69025 17

Instituto de Micro-Nanoelectrónica, Universidad San Francisco de Quito, Quito, Ecuador

[1] Waser R, Wuttig M. Function by defects at the atomic scale - new concepts for nonvolatile memories. In: Proceedings of ESSCIRC; IEEE.org, USA. Athens, Greece. 14–18

[2] Wuttig M, Yamada N. Phase-change materials for rewriteable data storage. Nature Mate-

[3] Sawa A. Resistive switching in transition metal oxides. Materials Today. 2008;11:28-36

[4] Ielmini D, Nardi F, Cagli C. Physical models of size-dependent nanofilament formation and rupture in NiO resistive switching memories. Nanotechnology. 2011;22:254022-1-

[5] Degraeve R, Fantini A, Raghavan N, Goux L, Clima S, Govoreanu B, Belmonte A, Linten D, Jurczak M. Causes and consequences of the stochastic aspect of filamentary RRAM.

[6] Guan X, Yu S, Philip Wong H -S. On the switching parameter variation of metal-oxide RRAM—Part I: Physical modeling and simulation methodology. Transactions on Electron

[7] Yu S, Guan X, Philip Wong H-S. On the switching parameter variation of metal oxide RRAM—Part II: Model corroboration and device design strategy. IEEE Transactions on

otherwise the transport depends on the oxidation/reduction of CF.

Address all correspondence to: lprocel@usfq.edu.ec

Microelectronic Engineering. 2015;147:171-175

Author details

References

Luis-Miguel Procel-Moya

November 2009. pp. 65-72

Devices. 2012;59:1172-1182

Electron Devices. 2012;59:1183-1188

rials. 2007;6:824-832

254022-12

where Φ<sup>0</sup> is a potential height at a T<sup>0</sup> temperature (a given temperature) and γ is a temperature coefficient. For extracting γ, we can use the following expression [12]:

$$\frac{d(\log[I/1A])}{dT}\ln(10) = a\gamma\tag{33}$$

This dependence has been probed in experimental results of HfO2 cells in Ref. [10].

#### 5. Conclusions

We have presented a classification of physical models for explaining the resistive switching mechanisms in chalcogonides materials. In the literature, there are many physical models proposed for explaining the electron conduction and switching mechanism in specific materials and fabrication process conditions. In the present work, we divide the models according to the number of material dimensions involved on the resistive switching mechanism. The phase change mechanism (PCM) is presented in some Te-alloys used an optical storage devices. In this switching mechanism, the material changes from the amorphous phase to the crystalline phase. Because of the resistivity affects the complete cell volume, the phase change mechanism is considered a 3D model. On the other hand, the modulation of the resistive contact is a 2D model because the defect concentration only affects the metal/insulator interface. This mechanism is presented in some perovskite materials.

The principal component of 1D models is the presence of a conduction filament. The filament is formed in a virgin cell by applying a certain threshold voltage. Depending on the cell polarity, the transport mechanisms can be: thermochemical diffusion of oxygen, filament oxidation-reduction or quantum point contact. For unipolar cells (like NiO cells), the resistive switching and the carrier conduction are controlled by the thermochemical diffusion of oxygen in the CF due to the Joule-heating effect. For bipolar cells (like HfO2), the switching mechanism is related to the oxidation/reduction of CF. If the CF radius at the narrowest part of the CF is in the order of the Fermi wavelength, the transport is driven by the quantum point contact effect, otherwise the transport depends on the oxidation/reduction of CF.

## Author details

Luis-Miguel Procel-Moya

Address all correspondence to: lprocel@usfq.edu.ec

Instituto de Micro-Nanoelectrónica, Universidad San Francisco de Quito, Quito, Ecuador

## References

agrees with the quantum approach of this model. Miranda et al. showed that Φ has a linear

Figure 7. Experimental and theoretical I-V characteristics for the (a) HRS and (b) LRS. The QPC model (Eqs. (28) and (29))

where Φ<sup>0</sup> is a potential height at a T<sup>0</sup> temperature (a given temperature) and γ is a temperature

We have presented a classification of physical models for explaining the resistive switching mechanisms in chalcogonides materials. In the literature, there are many physical models proposed for explaining the electron conduction and switching mechanism in specific materials and fabrication process conditions. In the present work, we divide the models according to the number of material dimensions involved on the resistive switching mechanism. The phase change mechanism (PCM) is presented in some Te-alloys used an optical storage devices. In this switching mechanism, the material changes from the amorphous phase to the crystalline phase. Because of the resistivity affects the complete cell volume, the phase change mechanism is considered a 3D model. On the other hand, the modulation of the resistive contact is a 2D model because the defect concentration only affects the metal/insulator inter-

ΦðTÞ ¼ Φ<sup>0</sup> � γT ð32Þ

dT lnð10Þ ¼ αγ <sup>ð</sup>33<sup>Þ</sup>

dependence with respect to the temperature given by Avellán et al. [12]:

coefficient. For extracting γ, we can use the following expression [12]:

face. This mechanism is presented in some perovskite materials.

5. Conclusions

was used for theoretical curves.

16 Memristor and Memristive Neural Networks

dðlog½I=1A�Þ

This dependence has been probed in experimental results of HfO2 cells in Ref. [10].


[8] Miranda E, Suñé J. Analytic modeling of leakage current through multiple breakdown paths in SiO2 films. In: IEEE International Proceedings Reliability Physics Symposium. IEEE.org, USA; Orlando. USA. 30 April–3 May 2001. pp. 367-379

**Chapter 2**

**Provisional chapter**

**Graphene Oxide-Based Memristor**

Geetika Khurana, Nitu Kumar, James F. Scott

**Graphene Oxide-Based Memristor**

DOI: 10.5772/intechopen.69752

A memristor is the memory extension to the concept of resistor. With unique superior properties, memristors have prospective promising applications in non‐volatile memory (NVM). Resistive random access memory (RRAM) is a non‐volatile memory using a mate‐ rial whose resistance changes under electrical stimulus can be seen as the most promising candidate for next generation memory both as embedded memory and a stand‐alone memory due to its high speed, long retention time, low power consumption, scalability and simple structure. Among carbon‐based materials, graphene has emerged as wonder material with remarkable properties. In contrast to metallic nature of graphene, the gra‐ phene oxide (GO) is good insulating/semiconducting material and suitable for RRAM devices. The advantage of being atomically thin and the two‐dimensional of GO permits scaling beyond the current limits of semiconductor technology, which is a key aspect for high‐density fabrication. Graphene oxide‐based resistive memory devices have several advantages over other oxide materials, such as easy synthesis and cost‐effective device fabrication, scaling down to few nanometre and compatibility for flexible device appli‐ cations. In this chapter, we discuss the GO‐based RRAM devices, which have shown the properties of forming free, thermally stable, multi‐bit storage, flexible and high on/ off ratio at low voltage, which boost up the research and development to accelerate the

Geetika Khurana, Nitu Kumar, James F. Scott and

GO‐based RRAM devices for future memory applications.

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

**Keywords:** memristor, graphene oxide, forming free, multi‐bit storage, flexible devices

The memristor (contraction for memory resistor) acclaimed as the fourth fundamental cir‐ cuit element together with already known the capacitor, the inductor and the resistor was theoretically predicted by Chua in 1971 [1]. But it attracted much attention in 2008, when a

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69752

Ram S. Katiyar

and Ram S. Katiyar

**Abstract**

**1. Introduction**


**Provisional chapter**

## **Graphene Oxide-Based Memristor**

Geetika Khurana, Nitu Kumar, James F. Scott

**Graphene Oxide-Based Memristor**

Geetika Khurana, Nitu Kumar, James F. Scott and Ram S. Katiyar and Ram S. Katiyar Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69752

#### **Abstract**

[8] Miranda E, Suñé J. Analytic modeling of leakage current through multiple breakdown paths in SiO2 films. In: IEEE International Proceedings Reliability Physics Symposium.

[9] Miranda E, Walczyk C, Wenger C, Schroeder T. Model for the resistive switching effect in HfO2 MIM structures based on the transmission properties of narrow constrictions. IEEE

[10] Procel LM, Trojman L, Moreno J, Crupi F, Maccaronio V, Degraeve R, Goux L, Simoen E. Experimental evidence of the quantum point contact theory in the conduction mechanism of bipolar HfO2-based resistive random access memories. Journal of Applied Phys-

[11] Degraeve R, Roussel Ph, Goux L, Wouters D, Kittl J, Altimime L, Jurczak M, Groeseneken G Generic learning of TDDB applied to RRAM for improved understanding of conduction and switching mechanism through multiple filaments. In: IEEE International Electron Devices Meeting. IEEE.org, USA; San Francisco. USA. 6–8 December 2010. pp. 632-635 [12] Avellán A, Miranda E, Schroeder D, Krautschneider W Model for the voltage and temperature dependence of the soft breakdown current in ultrathin gate oxides. Journal of

IEEE.org, USA; Orlando. USA. 30 April–3 May 2001. pp. 367-379

Electron Device Letters. 2010;31:609-611

Applied Physics. 2005;014104:014104-1-014104-5

ics. 2012;074509:074509 (1-5)

18 Memristor and Memristive Neural Networks

A memristor is the memory extension to the concept of resistor. With unique superior properties, memristors have prospective promising applications in non‐volatile memory (NVM). Resistive random access memory (RRAM) is a non‐volatile memory using a mate‐ rial whose resistance changes under electrical stimulus can be seen as the most promising candidate for next generation memory both as embedded memory and a stand‐alone memory due to its high speed, long retention time, low power consumption, scalability and simple structure. Among carbon‐based materials, graphene has emerged as wonder material with remarkable properties. In contrast to metallic nature of graphene, the gra‐ phene oxide (GO) is good insulating/semiconducting material and suitable for RRAM devices. The advantage of being atomically thin and the two‐dimensional of GO permits scaling beyond the current limits of semiconductor technology, which is a key aspect for high‐density fabrication. Graphene oxide‐based resistive memory devices have several advantages over other oxide materials, such as easy synthesis and cost‐effective device fabrication, scaling down to few nanometre and compatibility for flexible device appli‐ cations. In this chapter, we discuss the GO‐based RRAM devices, which have shown the properties of forming free, thermally stable, multi‐bit storage, flexible and high on/ off ratio at low voltage, which boost up the research and development to accelerate the GO‐based RRAM devices for future memory applications.

DOI: 10.5772/intechopen.69752

**Keywords:** memristor, graphene oxide, forming free, multi‐bit storage, flexible devices

## **1. Introduction**

The memristor (contraction for memory resistor) acclaimed as the fourth fundamental cir‐ cuit element together with already known the capacitor, the inductor and the resistor was theoretically predicted by Chua in 1971 [1]. But it attracted much attention in 2008, when a

TiO<sup>2</sup> ‐based crossbar memory array was developed by the HP Labs, and the cross‐point storage element was recognized as the memristor [2]. Recently, a rather deep analysis has been pro‐ vided concerning memristors [3], which shows conclusively that the memristor is not the long‐ sought fourth circuit element but the memory extension to the concept of resistor. With unique superior properties, memristors have promising applications in non‐volatile memory (NVM), artificial neural networks, programmable logic devices, signal processing and pattern recog‐ nition circuits. Random access memory (RAM) is an important form of computer data stor‐ age. However, due to the technological and physical limitations imposed by dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory towards low power, small size, fast speed, high density and non‐volatility, there is an urgent need of upcoming NVM technologies with low power, high density, high read/write endurance and scalability. In a memristor, a new memory device to solve these problems, a resistive random access memory (RRAM) is a good direction for the development of future memory technology. RRAM is a memory using a material whose resistance changes under electrical stimulus and can be seen as the most promising candidate for next generation memory both as embedded memory and a stand‐alone memory due to its high speed, long retention time, low power con‐ sumption, scalability and simple structure [4]. Typically, RRAM is a two‐terminal device that the switching medium is sandwiched between top and bottom electrodes (**Figure 1**) and the resistance of the switching medium can be modulated by applying electrical signal (current or voltage) to the electrodes. Appropriate value of programming voltage pulse can set the device from high‐resistance state (HRS) to low‐resistance state (LRS) known as SET or writing pro‐ cess. Similarly, switching back of the device from LRS to HRS using a voltage pulse known as RESET or erase process. Based on the voltage polarity used, RRAM can be categorized into two types: unipolar and bipolar resistive switching [5]. The switching operation is called unipolar, if the SET and RESET processes occur at the same voltage polarity. In the SET process, the current is usually constrained by current compliance. Whereas, the switching is bipolar if the SET and RESET processes occur at reversed polarity of voltages. In both switching modes, two resistance states are distinguished from each other at a small read‐out voltage, therefore read operation has no influence on the resistance state. However, the attractive properties of RRAM are low fabrication costs, scalability into the nanometre regime, fast write and read access, low power consumption and low threshold voltages.

The resistive switching effect has been explored until now in several materials including tran‐ sition metal oxides, perovskite oxides, organic materials and carbon‐based materials. Carbon‐ based materials have been researched extensively as an important class of materials for many years to defeat the technological barriers of conventional semiconductor electronics [6–8]. Previously, the efforts have been made to fabricate the field effect transistor (FET) devices [9, 10] based on carbon materials. Therefore, it is highly demandable to fabricate carbon‐based memory devices to integrate logic and memory devices based on same material. This chapter introduces RRAM properties of the carbon compound known as graphene oxide (GO). It is basically a wrinkled two‐dimensional carbon sheet with various oxygenated functional groups attached to its basal plane and peripheries, with the thickness of around 1 nm and lateral dimensions varying between a few nanometres and several microns. Graphene oxide has been synthesized by various chemical methods, such as Hummers' method and its modification, Brodie method and Staudenmaier method. In contrast to the metallic nature of graphene, the graphene oxide is good insulating/semiconducting material, which can be readily obtained by oxidizing graphite with strong oxidants.GO sheets are heavily oxygenated, bearing hydroxyl and epoxide functional groups on their basal planes, in addition to carbonyl and carboxyl groups located at the sheet edges. Furthermore, the ability of these sheets to form covalent as well as non‐covalent (based on interactions) bonds encourages the fabrication of a wide vari‐ ety of hybrid structures such as transistors, sensors, optoelectronic and memory devices etc. [11, 12]. The two dimensionality of GO permits scaling beyond the current limits of semicon‐ ductor technology, which is a key aspect for high‐density fabrication. Out of tremendous appli‐ cations of graphene oxide, this chapter focuses on the memory device application. Graphene oxide (GO) with an ultrathin thickness is attractive due to its unique physical‐chemical prop‐ erties. GO can be readily obtained through oxidizing graphite in mixtures of strong oxidants, followed by an exfoliation process. The presence of these functional groups makes GO sheets electrically insulating, with characteristics comparable to other thin‐layered oxide materials, with the advantage of being atomically thin, which makes GO the perfect candidate for the fabrication of memristive devices [13, 14]. As GO is water soluble which makes it facile to transfer onto any substrate in thin film form by simple methods of spin coating, drop‐casting, Langmuir‐Blodgett (LB) and vacuum filtration. The as‐deposited GO thin films can be further processed into functional devices using standard lithography processes without degrading the film properties [15, 16]. Furthermore, the band structure and electronic properties of GO can be modulated by changing the quantity of chemical functionalities attached to the surface.

Graphene Oxide-Based Memristor

21

http://dx.doi.org/10.5772/intechopen.69752

Therefore, GO is potentially useful for microelectronics production.

Graphene oxide‐based resistive memory devices have several advantages, such as easy syn‐ thesis and cost‐effective device fabrication, scaling down to few nanometres and compatibility for flexible device applications. Reliable and reproducible resistive switching behaviour was first reported in graphene oxide thin films prepared by the vacuum filtration method by He et al. in 2009 [17]. They observed very low switching voltages and low on/off ratio of about 20 in

**2. Status of graphene oxide‐based RRAM devices**

**Figure 1.** Schematic and electrical configuration of a two‐terminal RRAM cell.

The resistive switching effect has been explored until now in several materials including tran‐ sition metal oxides, perovskite oxides, organic materials and carbon‐based materials. Carbon‐ based materials have been researched extensively as an important class of materials for many years to defeat the technological barriers of conventional semiconductor electronics [6–8]. Previously, the efforts have been made to fabricate the field effect transistor (FET) devices [9, 10] based on carbon materials. Therefore, it is highly demandable to fabricate carbon‐based memory devices to integrate logic and memory devices based on same material. This chapter introduces RRAM properties of the carbon compound known as graphene oxide (GO). It is basically a wrinkled two‐dimensional carbon sheet with various oxygenated functional groups attached to its basal plane and peripheries, with the thickness of around 1 nm and lateral dimensions varying between a few nanometres and several microns. Graphene oxide has been synthesized by various chemical methods, such as Hummers' method and its modification, Brodie method and Staudenmaier method. In contrast to the metallic nature of graphene, the graphene oxide is good insulating/semiconducting material, which can be readily obtained by oxidizing graphite with strong oxidants.GO sheets are heavily oxygenated, bearing hydroxyl and epoxide functional groups on their basal planes, in addition to carbonyl and carboxyl groups located at the sheet edges. Furthermore, the ability of these sheets to form covalent as well as non‐covalent (based on interactions) bonds encourages the fabrication of a wide vari‐ ety of hybrid structures such as transistors, sensors, optoelectronic and memory devices etc. [11, 12]. The two dimensionality of GO permits scaling beyond the current limits of semicon‐ ductor technology, which is a key aspect for high‐density fabrication. Out of tremendous appli‐ cations of graphene oxide, this chapter focuses on the memory device application. Graphene oxide (GO) with an ultrathin thickness is attractive due to its unique physical‐chemical prop‐ erties. GO can be readily obtained through oxidizing graphite in mixtures of strong oxidants, followed by an exfoliation process. The presence of these functional groups makes GO sheets electrically insulating, with characteristics comparable to other thin‐layered oxide materials, with the advantage of being atomically thin, which makes GO the perfect candidate for the fabrication of memristive devices [13, 14]. As GO is water soluble which makes it facile to transfer onto any substrate in thin film form by simple methods of spin coating, drop‐casting, Langmuir‐Blodgett (LB) and vacuum filtration. The as‐deposited GO thin films can be further processed into functional devices using standard lithography processes without degrading the film properties [15, 16]. Furthermore, the band structure and electronic properties of GO can be modulated by changing the quantity of chemical functionalities attached to the surface. Therefore, GO is potentially useful for microelectronics production.

## **2. Status of graphene oxide‐based RRAM devices**

TiO<sup>2</sup>

20 Memristor and Memristive Neural Networks

power consumption and low threshold voltages.

**Figure 1.** Schematic and electrical configuration of a two‐terminal RRAM cell.

‐based crossbar memory array was developed by the HP Labs, and the cross‐point storage element was recognized as the memristor [2]. Recently, a rather deep analysis has been pro‐ vided concerning memristors [3], which shows conclusively that the memristor is not the long‐ sought fourth circuit element but the memory extension to the concept of resistor. With unique superior properties, memristors have promising applications in non‐volatile memory (NVM), artificial neural networks, programmable logic devices, signal processing and pattern recog‐ nition circuits. Random access memory (RAM) is an important form of computer data stor‐ age. However, due to the technological and physical limitations imposed by dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory towards low power, small size, fast speed, high density and non‐volatility, there is an urgent need of upcoming NVM technologies with low power, high density, high read/write endurance and scalability. In a memristor, a new memory device to solve these problems, a resistive random access memory (RRAM) is a good direction for the development of future memory technology. RRAM is a memory using a material whose resistance changes under electrical stimulus and can be seen as the most promising candidate for next generation memory both as embedded memory and a stand‐alone memory due to its high speed, long retention time, low power con‐ sumption, scalability and simple structure [4]. Typically, RRAM is a two‐terminal device that the switching medium is sandwiched between top and bottom electrodes (**Figure 1**) and the resistance of the switching medium can be modulated by applying electrical signal (current or voltage) to the electrodes. Appropriate value of programming voltage pulse can set the device from high‐resistance state (HRS) to low‐resistance state (LRS) known as SET or writing pro‐ cess. Similarly, switching back of the device from LRS to HRS using a voltage pulse known as RESET or erase process. Based on the voltage polarity used, RRAM can be categorized into two types: unipolar and bipolar resistive switching [5]. The switching operation is called unipolar, if the SET and RESET processes occur at the same voltage polarity. In the SET process, the current is usually constrained by current compliance. Whereas, the switching is bipolar if the SET and RESET processes occur at reversed polarity of voltages. In both switching modes, two resistance states are distinguished from each other at a small read‐out voltage, therefore read operation has no influence on the resistance state. However, the attractive properties of RRAM are low fabrication costs, scalability into the nanometre regime, fast write and read access, low

> Graphene oxide‐based resistive memory devices have several advantages, such as easy syn‐ thesis and cost‐effective device fabrication, scaling down to few nanometres and compatibility for flexible device applications. Reliable and reproducible resistive switching behaviour was first reported in graphene oxide thin films prepared by the vacuum filtration method by He et al. in 2009 [17]. They observed very low switching voltages and low on/off ratio of about 20 in

Cu/GO/Pt structure. Soon after that there were many reports published showing high on/off ratios in GO‐based RRAM devices [18, 19]. Mechanism for the resistive switching characteris‐ tics in GO‐based RRAM was found to be due to the oxygen migration, oxygen vacancies and the electrode diffusion [20, 21]. Furthermore, Jeong et al. presented a GO‐based memory that can be easily fabricated using a room temperature spin‐casting method on flexible substrates and has reliable memory performance in terms of retention and endurance [22]. Resistive switching effect was shown in Ni‐doped graphene oxide by Pinto et al. [23]. Transparent non‐ volatile memory device based on SiO*x* and graphene was also reported which features high transparency, long retention time and low programming currents [24]. Zhuge et al. reported the forming voltage dependence on GO film thickness and on different top electrodes [20]. Forming process is the application of initial high voltages to the devices to initiate the switch‐ ing process, which is detrimental to the device structure and operation. Forming‐free GO RRAM devices having high on/off ratio with good retention and endurance properties are potential candidates for non‐volatile RRAM. Therefore, in this chapter, we will be discussing RRAM properties of the GO‐based devices, which are forming free, thermally stable, multi‐bit storage, flexible, having high on/off ratio at low operating voltages that boost up the research and development to accelerate the GO‐based RRAM devices for future memory applications.

To observe the switching characteristics of the device, I‐V measurements for the Pt/GO/ITO device at 300 and 500 K were performed as shown in **Figure 3a** and **b**). The Pt/GO/ITO device was found initially in low‐resistance state having resistance value of ∼40 ohm. **Figure 3** shows that as the positive voltage was increased, a sudden fall in current was observed at a voltage of ∼3.2 V indicating abrupt increase in the resistance of the device. This is known as RESET process and device transformed from its initial low‐resistance state (LRS) to high‐resistance

The low‐resistance state of GO‐based MIM devices once obtained persisted even when the applied voltage was reduced to zero indicating non‐volatility. In high‐resistance state, when the voltage was swept a sudden increase in current was observed at a voltage of approxi‐ mately −1.2 V indicating abrupt decrease in the resistance of device and switching from high‐ resistance state to low‐resistance state as shown in **Figure 3a**. This is known as the SET process which switched the MIM device in LRS or ON state. The LRS of device remained preserved even when the applied bias voltage was removed. During this set process, current compliance was kept fixed at 100 mA to avoid the breakdown of GO film due to high current flow in low‐ resistance state. By repeating the set and reset processes over 100 cycles, it was observed that the reset voltage was larger than the set voltage and spread over a small window of voltage between ∼3 and 3.4 V, whereas the set voltage had a spread between approximately −1.2 and −1.8 V. Thus, the device showed a typical bipolar resistive switching (BRS) behaviour with an

studied at elevated temperature of 500 K (as shown in **Figure 3b**). Reduction in the value of reset voltage at 500 K was observed which could be attributed to enhanced diffusivity of oxy‐ gen ions at elevated temperature compared to that of room temperature. However, contrary to that we found increment in the set voltage at elevated temperature. Further at high tem‐

sufficient for operation of memory devices. Low‐ and high‐resistance states were stable up to

seconds and up to 100 cycles indicating good retention and endurance characteristics of

perature of 500 K, the on/off ratio of the device was found to decrease up to ∼102

**Figure 3.** Current‐voltage characteristics of the Pt/GO/ITO device at (a) 300 K and (b) 500 K [26].

over 100 test cycles. Switching characteristics of the device were also

; however, this ratio of high‐ and low‐resistance states is

compared

Graphene Oxide-Based Memristor

23

http://dx.doi.org/10.5772/intechopen.69752

state (HRS) also known as OFF state.

on/off current ratio of 10<sup>4</sup>

10<sup>4</sup>

to its value at 300 K which was ∼10<sup>4</sup>

the device at elevated temperature of 500 K.

#### **2.1. Graphene oxide‐based RRAM devices**

Synthesis of graphene oxide presented in this chapter has been carried out by modified Hummers method [25, 26]. In brief, highly oriented pyrolytic graphite (HOPG, 2 g) was oxi‐ dized using potassium permanganate (KMnO4 , 7 g) in the presence of concentrated H<sup>2</sup> SO4 (50 ml) in ice bath. After the reaction, excess distilled water was added to the solution. With continuous stirring a 30 wt.% of hydrogen peroxide (H2 O2 ) was added slowly until the gas evolution had stopped. Further 15 more‐minute stirring was done to the resultant mixture, and then it was filtered through nylon membrane. Repeated washing was done by distilled water and 5% HCl solution until the filtrate was neutral. Finally, the obtained dark brown slurry was dried for 24 hour in a vacuum oven at 60°C. A colloidal suspension of GO was prepared in distilled water by sonicating graphite oxide in water for 2 hour. Such a solution of GO was used to fabricate the thin films by spin coating process on ITO/Glass substrate. To construct metal‐insulator‐metal (MIM) devices, platinum top electrodes with an area of 40 × 40 μm2 were deposited by DC sputtering utilizing a shadow mask. The schematic representa‐ tion of fabricated Pt/graphene oxide/imdium‐tin oxide (GO/ITO) is shown in **Figure 2**.

**Figure 2.** Schematic representation of GO‐based MIM devices [26].

To observe the switching characteristics of the device, I‐V measurements for the Pt/GO/ITO device at 300 and 500 K were performed as shown in **Figure 3a** and **b**). The Pt/GO/ITO device was found initially in low‐resistance state having resistance value of ∼40 ohm. **Figure 3** shows that as the positive voltage was increased, a sudden fall in current was observed at a voltage of ∼3.2 V indicating abrupt increase in the resistance of the device. This is known as RESET process and device transformed from its initial low‐resistance state (LRS) to high‐resistance state (HRS) also known as OFF state.

Cu/GO/Pt structure. Soon after that there were many reports published showing high on/off ratios in GO‐based RRAM devices [18, 19]. Mechanism for the resistive switching characteris‐ tics in GO‐based RRAM was found to be due to the oxygen migration, oxygen vacancies and the electrode diffusion [20, 21]. Furthermore, Jeong et al. presented a GO‐based memory that can be easily fabricated using a room temperature spin‐casting method on flexible substrates and has reliable memory performance in terms of retention and endurance [22]. Resistive switching effect was shown in Ni‐doped graphene oxide by Pinto et al. [23]. Transparent non‐ volatile memory device based on SiO*x* and graphene was also reported which features high transparency, long retention time and low programming currents [24]. Zhuge et al. reported the forming voltage dependence on GO film thickness and on different top electrodes [20]. Forming process is the application of initial high voltages to the devices to initiate the switch‐ ing process, which is detrimental to the device structure and operation. Forming‐free GO RRAM devices having high on/off ratio with good retention and endurance properties are potential candidates for non‐volatile RRAM. Therefore, in this chapter, we will be discussing RRAM properties of the GO‐based devices, which are forming free, thermally stable, multi‐bit storage, flexible, having high on/off ratio at low operating voltages that boost up the research and development to accelerate the GO‐based RRAM devices for future memory applications.

Synthesis of graphene oxide presented in this chapter has been carried out by modified Hummers method [25, 26]. In brief, highly oriented pyrolytic graphite (HOPG, 2 g) was oxi‐

(50 ml) in ice bath. After the reaction, excess distilled water was added to the solution. With

evolution had stopped. Further 15 more‐minute stirring was done to the resultant mixture, and then it was filtered through nylon membrane. Repeated washing was done by distilled water and 5% HCl solution until the filtrate was neutral. Finally, the obtained dark brown slurry was dried for 24 hour in a vacuum oven at 60°C. A colloidal suspension of GO was prepared in distilled water by sonicating graphite oxide in water for 2 hour. Such a solution of GO was used to fabricate the thin films by spin coating process on ITO/Glass substrate. To construct metal‐insulator‐metal (MIM) devices, platinum top electrodes with an area of 40 ×

were deposited by DC sputtering utilizing a shadow mask. The schematic representa‐

tion of fabricated Pt/graphene oxide/imdium‐tin oxide (GO/ITO) is shown in **Figure 2**.

, 7 g) in the presence of concentrated H<sup>2</sup>

) was added slowly until the gas

O2

SO4

**2.1. Graphene oxide‐based RRAM devices**

22 Memristor and Memristive Neural Networks

dized using potassium permanganate (KMnO4

40 μm2

continuous stirring a 30 wt.% of hydrogen peroxide (H2

**Figure 2.** Schematic representation of GO‐based MIM devices [26].

The low‐resistance state of GO‐based MIM devices once obtained persisted even when the applied voltage was reduced to zero indicating non‐volatility. In high‐resistance state, when the voltage was swept a sudden increase in current was observed at a voltage of approxi‐ mately −1.2 V indicating abrupt decrease in the resistance of device and switching from high‐ resistance state to low‐resistance state as shown in **Figure 3a**. This is known as the SET process which switched the MIM device in LRS or ON state. The LRS of device remained preserved even when the applied bias voltage was removed. During this set process, current compliance was kept fixed at 100 mA to avoid the breakdown of GO film due to high current flow in low‐ resistance state. By repeating the set and reset processes over 100 cycles, it was observed that the reset voltage was larger than the set voltage and spread over a small window of voltage between ∼3 and 3.4 V, whereas the set voltage had a spread between approximately −1.2 and −1.8 V. Thus, the device showed a typical bipolar resistive switching (BRS) behaviour with an on/off current ratio of 10<sup>4</sup> over 100 test cycles. Switching characteristics of the device were also studied at elevated temperature of 500 K (as shown in **Figure 3b**). Reduction in the value of reset voltage at 500 K was observed which could be attributed to enhanced diffusivity of oxy‐ gen ions at elevated temperature compared to that of room temperature. However, contrary to that we found increment in the set voltage at elevated temperature. Further at high tem‐ perature of 500 K, the on/off ratio of the device was found to decrease up to ∼102 compared to its value at 300 K which was ∼10<sup>4</sup> ; however, this ratio of high‐ and low‐resistance states is sufficient for operation of memory devices. Low‐ and high‐resistance states were stable up to 10<sup>4</sup> seconds and up to 100 cycles indicating good retention and endurance characteristics of the device at elevated temperature of 500 K.

**Figure 3.** Current‐voltage characteristics of the Pt/GO/ITO device at (a) 300 K and (b) 500 K [26].

Based on the conduction mechanism, it was observed that GO device contains conducting paths between top and bottom electrode perhaps due to the presence of oxygen vacancies and electron traps in graphene oxide layer forming electron hopping path [27]. Presence of oxygen vacancies in graphene oxide indicates partial reduction of GO and dominance of sp<sup>2</sup> character over sp3 character providing high conducting channel in GO film and initial low‐resistance state without any forming process. In Pt/GO/ITO devices, the bottom electrode ITO acts as a source/reservoir of oxygen ions [28]. To ascertain the presence of sp<sup>2</sup> and sp3 characters of carbon, Raman spectroscopy measurements were carried out on the Pt/GO/ITO devices both in LRS and HRS and are shown in **Figure 4**. As can be seen in **Figure 4** that in case of as‐grown device and the device in LRS, the presence of G peak signifying the sp<sup>2</sup> character is larger in intensity compared to the same peak when the device was switched into HRS by the application of suitable bias voltage. This indicates that the sp<sup>2</sup> character dominates in LRS. While in case of HRS, the sp<sup>2</sup> character is suppressed. These RRAM devices based on GO layer fabricated by a simple process of spin coating show a forming free bipolar resistive switch‐ ing (BRS) in Pt/GO/ITO structure with high on/off ratio of 10<sup>4</sup> exhibiting good retention and endurance properties at room and elevated temperatures.

performance of the organic memories can be greatly enhanced by forming hybrid organic struc‐ tures [39], organic/inorganic composites [40] or by dispersing nanomaterials [41, 42]. Among all other organic polymers, polyvinylidene fluoride (PVDF) was used due to its non‐reactive nature, better heat resistance, flexibility and low weight. As mentioned above, hybrid struc‐ tures of organic memory devices provide enhanced memory characteristics; therefore, hetero‐ structure of PVDF was fabricated using a charge trapping element in it. In this study, reduced graphene oxide nanoflakes (GR) were used as a charge trapping layer owing to their unique chemical structure and exceptional properties [6, 43–47] that make it ideal for charge trapping [48] and storage [49] for memory applications. Also, the defects (vacancy, interstitial sites, etc.) present in GR also work as the charge trapping nodes [50]. Tri‐layer structure was fabricated by assembling graphene nanoflakes (GR) between PVDF polymer layers [51] through spin coating process on ITO/glass substrate as shown in **Figure 5**. DC sputtering was used to deposit plati‐ num top electrode having area (100 μm × 100 μm) through shadow mask to obtain devices from

Graphene Oxide-Based Memristor

25

http://dx.doi.org/10.5772/intechopen.69752

As the voltage was increased, multi‐stage SET and RESET were observed in positive and nega‐ tive polarities, respectively, as shown in **Figure 6a**. This process was repeatable for a number of cycles, which established the device as a non‐volatile memory with multilevel conductance states. The multilevel SET process occurring in the device can be due to multi‐channels forma‐ tion as trapping sites in graphene bear different threshold potentials. Electrons occupied these trapping sites even if the applied voltage is removed, thus preserving the non‐volatile nature of the device in ON state. When negative voltage is applied to the device, current firstly increases with voltage due to the presence of trapped charges in the nodes. At a particular negative bias, current jumps to low value due to the de‐trapping of electrons from the trapping nodes which initiates the breaking of conducting channels. Further at a particular negative bias, when most of the electrons de‐trapped and ejected back to ITO, the conducting path completely disrupts and the device transits to OFF state bearing high resistance. The multi‐channel RESET process occurring in the device is also due to the same mechanism as discussed in the SET process. In brief, it may be due to the breaking of multi‐channels at different potentials. Reports have shown that the intermediate stage present in the device revealing multi‐level switching is due to the formation of multi‐filaments [52] having different threshold potentials [53]. The device

**Figure 5.** Schematic diagram of the layer‐by‐layer fabricated Pt/PVDF/rGO/PVDF/ITO memory devices. Top electrode

was deposited using DC sputtering [51].

the stacked structure.

of platinum (Pt) having area 100 × 100 μm2

#### **2.2. Graphene oxide‐based multi‐layer structures for high‐density data storage**

Organic memory devices have gained much attention as future information and storage compo‐ nents owing to their low weight, flexibility, inexpensive and facile fabrication methods [29, 30]. Recent reports have shown that organic memory devices have been developed through layer stacking [31] and using advanced memory architectures [32–35]. However, the most organic memory devices are suffering with slow switching [36] and low storage capacity [37, 38]. RRAM

**Figure 4.** Raman spectra for Pt/GO/ITO device in LRS (upper curve) and HRS (lower curve) [26].

performance of the organic memories can be greatly enhanced by forming hybrid organic struc‐ tures [39], organic/inorganic composites [40] or by dispersing nanomaterials [41, 42]. Among all other organic polymers, polyvinylidene fluoride (PVDF) was used due to its non‐reactive nature, better heat resistance, flexibility and low weight. As mentioned above, hybrid struc‐ tures of organic memory devices provide enhanced memory characteristics; therefore, hetero‐ structure of PVDF was fabricated using a charge trapping element in it. In this study, reduced graphene oxide nanoflakes (GR) were used as a charge trapping layer owing to their unique chemical structure and exceptional properties [6, 43–47] that make it ideal for charge trapping [48] and storage [49] for memory applications. Also, the defects (vacancy, interstitial sites, etc.) present in GR also work as the charge trapping nodes [50]. Tri‐layer structure was fabricated by assembling graphene nanoflakes (GR) between PVDF polymer layers [51] through spin coating process on ITO/glass substrate as shown in **Figure 5**. DC sputtering was used to deposit plati‐ num top electrode having area (100 μm × 100 μm) through shadow mask to obtain devices from the stacked structure.

Based on the conduction mechanism, it was observed that GO device contains conducting paths between top and bottom electrode perhaps due to the presence of oxygen vacancies and electron traps in graphene oxide layer forming electron hopping path [27]. Presence of oxygen

state without any forming process. In Pt/GO/ITO devices, the bottom electrode ITO acts as

of carbon, Raman spectroscopy measurements were carried out on the Pt/GO/ITO devices both in LRS and HRS and are shown in **Figure 4**. As can be seen in **Figure 4** that in case of

is larger in intensity compared to the same peak when the device was switched into HRS by

fabricated by a simple process of spin coating show a forming free bipolar resistive switch‐

Organic memory devices have gained much attention as future information and storage compo‐ nents owing to their low weight, flexibility, inexpensive and facile fabrication methods [29, 30]. Recent reports have shown that organic memory devices have been developed through layer stacking [31] and using advanced memory architectures [32–35]. However, the most organic memory devices are suffering with slow switching [36] and low storage capacity [37, 38]. RRAM

character providing high conducting channel in GO film and initial low‐resistance

character is suppressed. These RRAM devices based on GO layer

character

characters

character

and sp3

character dominates in LRS.

exhibiting good retention and

vacancies in graphene oxide indicates partial reduction of GO and dominance of sp<sup>2</sup>

as‐grown device and the device in LRS, the presence of G peak signifying the sp<sup>2</sup>

**2.2. Graphene oxide‐based multi‐layer structures for high‐density data storage**

**Figure 4.** Raman spectra for Pt/GO/ITO device in LRS (upper curve) and HRS (lower curve) [26].

a source/reservoir of oxygen ions [28]. To ascertain the presence of sp<sup>2</sup>

the application of suitable bias voltage. This indicates that the sp<sup>2</sup>

ing (BRS) in Pt/GO/ITO structure with high on/off ratio of 10<sup>4</sup>

endurance properties at room and elevated temperatures.

over sp3

While in case of HRS, the sp<sup>2</sup>

24 Memristor and Memristive Neural Networks

As the voltage was increased, multi‐stage SET and RESET were observed in positive and nega‐ tive polarities, respectively, as shown in **Figure 6a**. This process was repeatable for a number of cycles, which established the device as a non‐volatile memory with multilevel conductance states. The multilevel SET process occurring in the device can be due to multi‐channels forma‐ tion as trapping sites in graphene bear different threshold potentials. Electrons occupied these trapping sites even if the applied voltage is removed, thus preserving the non‐volatile nature of the device in ON state. When negative voltage is applied to the device, current firstly increases with voltage due to the presence of trapped charges in the nodes. At a particular negative bias, current jumps to low value due to the de‐trapping of electrons from the trapping nodes which initiates the breaking of conducting channels. Further at a particular negative bias, when most of the electrons de‐trapped and ejected back to ITO, the conducting path completely disrupts and the device transits to OFF state bearing high resistance. The multi‐channel RESET process occurring in the device is also due to the same mechanism as discussed in the SET process. In brief, it may be due to the breaking of multi‐channels at different potentials. Reports have shown that the intermediate stage present in the device revealing multi‐level switching is due to the formation of multi‐filaments [52] having different threshold potentials [53]. The device

**Figure 5.** Schematic diagram of the layer‐by‐layer fabricated Pt/PVDF/rGO/PVDF/ITO memory devices. Top electrode of platinum (Pt) having area 100 × 100 μm2 was deposited using DC sputtering [51].

**Figure 6.** Typical I‐V characteristic curves plotted in semi‐logarithmic scale of Pt/PVDF/rGO/PVDF/ITO device (a) showing the presence of intermediate state. (b) Under different compliance currents of 1, 10 and 100 μA showing different low‐resistance states corresponding to the compliance current applied [51].

was further subjected to different compliance currents of 1, 10 and 100 μA during the SET process and correspondingly obtained different low‐resistance states as shown in **Figure 6b**.

demands for the need for materials which can be grown on these substrates at room tempera‐ ture. Obeying this condition, GO is readily oxidizable and water soluble, which qualifies to be fabricated in thin films on flexible substrates at room/moderate temperatures. There are reports which have shown that integration of nanomaterials into oxides is helpful in enhancing the resistive switching properties of the devices [60–62]. In this work [63], ZnO nanorods (ZNs) were grown in horizontal direction on GO sheets to maximize the contact area between the nanorods and GO sheets [64, 65]. The consequence of this was observed in significant reduc‐ tion in switching voltages in comparison to GO alone. The solution of GOZNs was spin coated to ITO‐coated polyethylene terephthalate (indium‐tin oxide on polyester film (ITOPET)) sub‐ strates to fabricate the films. Initially, the Al/GOZNs/ITOPET devices were in high‐resistance state (HRS). In the very first cycle, a forming voltage around 5 V with current compliance of 2 mA was applied to activate these devices. Device showed SET and RESET processes on posi‐ tive and negative voltages having non‐volatile nature. To investigate the effect of ZNs addition into the GO matrix, another device Al/GO/ITOPET was fabricated following the same process except the incorporation of ZNs in it, and this device showed comparatively higher values of

**Figure 7.** Resistances of the device in all LRS and HRS under different compliance currents of 1, 10 and 100 μA with read voltage of 0.1 V. (a) Endurance properties over 150 cycles with enough margin between the states. (b) Retention

Graphene Oxide-Based Memristor

27

http://dx.doi.org/10.5772/intechopen.69752

seconds for all four states [51].

I‐V measurements performed on both devices, shown in **Figure 8**, have clearly shown that SET and RESET voltages in the device containing ZNs were severely reduced to approximately half in comparison to the device containing no ZNs. To further understand the effect of changing ZNs ratio in GO matrix on resistive switching, the I‐V characteristics of different compositions (10:1, 5:1, 3:1 and 2:1) were studied and found that 3:1 was the best among all. In Al/GOZNs/ ITOPET devices, we propose that the conducting filament formation during the SET process is due to the oxygen vacancies. Oxygen concentration gradient exists at the interface of GO, and Al has high oxidation tendency. Therefore, oxygen ions from GO move towards and react with Al forming a new interfacial Al oxide layer [66]; also this process induces the oxygen vacancies into the GO region. With the positive bias is applied to the top electrode, these induced oxygen vacancies are deeply inserted into the GO matrix and providing the conductive paths during the SET process. With the negative polarity these oxygen vacancies are pushed back resulting

SET and RESET voltages.

characteristics over 10<sup>4</sup>

When the highest value of ICC was imposed, the device was observed in lowest resistance state. However, the HRS value for different ICC was almost the same. All four different states including one HRS and three LRS were observed in the device. It was proposed that with the highest compliance current applied during SET process, maximum number of trapping nodes are filled and hence maximum number of conductive channels are formed resulting in the lowest resistance state, while with the application of the lowest compliance current, small number of trapping nodes are filled having less number of conducting channels, leading to higher resistance state. To observe the performance and stability of the memory device, its endurance and retention properties were studied. **Figure 7a** represents the endurance char‐ acteristics of the device for all the four resistance states tested against number of cycles. As can be seen from **Figure 7a**, the four different states including one HRS and three LRS (LRS1, LRS2 and LRS3) were stable with no overlapping of resistances tested over the 150 number of cycles. **Figure 7b** shows the retention properties observed in the device where the resistance of all four states were measured using a read voltage of 0.1 V over a period of 10<sup>4</sup> seconds. The graph shows well‐differentiated resistance states of HRS and three LRS with no degradation in resistance values over the long time. These measurements for retention and endurance for the device showed that it has well performance and good stability. This tri‐layer structure fab‐ ricated by simple spin coating method can be seen as a potential candidate for future memory devices qualifying the need for high‐density storage media.

#### **2.3. Graphene oxide composite with ZnO nanorods for flexible memory devices**

Flexible RRAM devices have shown good potential for bendable memory systems [54–58]. These memories are in much demand due to the qualities of inexpensive, low weight, portability and user‐friendly interfaces over conventional rigid silicon technology [59]. The substrates for flexible memories could not bear high temperatures used in growth techniques, this limitation

**Figure 7.** Resistances of the device in all LRS and HRS under different compliance currents of 1, 10 and 100 μA with read voltage of 0.1 V. (a) Endurance properties over 150 cycles with enough margin between the states. (b) Retention characteristics over 10<sup>4</sup> seconds for all four states [51].

was further subjected to different compliance currents of 1, 10 and 100 μA during the SET process and correspondingly obtained different low‐resistance states as shown in **Figure 6b**. When the highest value of ICC was imposed, the device was observed in lowest resistance state. However, the HRS value for different ICC was almost the same. All four different states including one HRS and three LRS were observed in the device. It was proposed that with the highest compliance current applied during SET process, maximum number of trapping nodes are filled and hence maximum number of conductive channels are formed resulting in the lowest resistance state, while with the application of the lowest compliance current, small number of trapping nodes are filled having less number of conducting channels, leading to higher resistance state. To observe the performance and stability of the memory device, its endurance and retention properties were studied. **Figure 7a** represents the endurance char‐ acteristics of the device for all the four resistance states tested against number of cycles. As can be seen from **Figure 7a**, the four different states including one HRS and three LRS (LRS1, LRS2 and LRS3) were stable with no overlapping of resistances tested over the 150 number of cycles. **Figure 7b** shows the retention properties observed in the device where the resistance

**Figure 6.** Typical I‐V characteristic curves plotted in semi‐logarithmic scale of Pt/PVDF/rGO/PVDF/ITO device (a) showing the presence of intermediate state. (b) Under different compliance currents of 1, 10 and 100 μA showing

different low‐resistance states corresponding to the compliance current applied [51].

26 Memristor and Memristive Neural Networks

of all four states were measured using a read voltage of 0.1 V over a period of 10<sup>4</sup>

**2.3. Graphene oxide composite with ZnO nanorods for flexible memory devices**

devices qualifying the need for high‐density storage media.

graph shows well‐differentiated resistance states of HRS and three LRS with no degradation in resistance values over the long time. These measurements for retention and endurance for the device showed that it has well performance and good stability. This tri‐layer structure fab‐ ricated by simple spin coating method can be seen as a potential candidate for future memory

Flexible RRAM devices have shown good potential for bendable memory systems [54–58]. These memories are in much demand due to the qualities of inexpensive, low weight, portability and user‐friendly interfaces over conventional rigid silicon technology [59]. The substrates for flexible memories could not bear high temperatures used in growth techniques, this limitation

seconds. The

demands for the need for materials which can be grown on these substrates at room tempera‐ ture. Obeying this condition, GO is readily oxidizable and water soluble, which qualifies to be fabricated in thin films on flexible substrates at room/moderate temperatures. There are reports which have shown that integration of nanomaterials into oxides is helpful in enhancing the resistive switching properties of the devices [60–62]. In this work [63], ZnO nanorods (ZNs) were grown in horizontal direction on GO sheets to maximize the contact area between the nanorods and GO sheets [64, 65]. The consequence of this was observed in significant reduc‐ tion in switching voltages in comparison to GO alone. The solution of GOZNs was spin coated to ITO‐coated polyethylene terephthalate (indium‐tin oxide on polyester film (ITOPET)) sub‐ strates to fabricate the films. Initially, the Al/GOZNs/ITOPET devices were in high‐resistance state (HRS). In the very first cycle, a forming voltage around 5 V with current compliance of 2 mA was applied to activate these devices. Device showed SET and RESET processes on posi‐ tive and negative voltages having non‐volatile nature. To investigate the effect of ZNs addition into the GO matrix, another device Al/GO/ITOPET was fabricated following the same process except the incorporation of ZNs in it, and this device showed comparatively higher values of SET and RESET voltages.

I‐V measurements performed on both devices, shown in **Figure 8**, have clearly shown that SET and RESET voltages in the device containing ZNs were severely reduced to approximately half in comparison to the device containing no ZNs. To further understand the effect of changing ZNs ratio in GO matrix on resistive switching, the I‐V characteristics of different compositions (10:1, 5:1, 3:1 and 2:1) were studied and found that 3:1 was the best among all. In Al/GOZNs/ ITOPET devices, we propose that the conducting filament formation during the SET process is due to the oxygen vacancies. Oxygen concentration gradient exists at the interface of GO, and Al has high oxidation tendency. Therefore, oxygen ions from GO move towards and react with Al forming a new interfacial Al oxide layer [66]; also this process induces the oxygen vacancies into the GO region. With the positive bias is applied to the top electrode, these induced oxygen vacancies are deeply inserted into the GO matrix and providing the conductive paths during the SET process. With the negative polarity these oxygen vacancies are pushed back resulting

**Figure 8.** Typical I‐V switching characteristics in Al/GOZNs/ITOPET devices. Inset shows the I‐V characteristics for Al/ GO/ITOPET device [63].

reliability test was also performed by constantly flexing the device many times to the bending radius of 6 mm and the resistance was plotted against number of bending cycles as shown in **Figure 10b**. The HRS and LRS resistances show no noticeable degradation even up to 1000 times of repeated bending. The measurements performed on the Al/GOZNs/ITOPET device show excellent flexibility and mechanical endurance results and provide the data which show that the devices are capable for flexible memory applications. This study shows that the devices based on ZNs embedded in GO are potential candidate for future flexible non‐volatile

**Figure 10.** (a) Flexibility test for various bending radius on Al/GOZNs/ITOPET RRAM device. (b) Mechanical bending

endurance of device at bending radius of 6 mm on Al/GOZNs/ITOPET RRAM device [63].

**Figure 9.** (a) Comparative XPS spectra of GO and GOZNs for C1S peak. (b) XPS spectra of ZNs and GOZns showing O1S

Graphene Oxide-Based Memristor

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peak resolved into two components O1 and O2. (c) Zn2p spectra of ZNs and GOZNs samples [63].

memory applications.

in rupture of the conducting channel during the RESET process. But with the incorporation of ZNs into the GO matrix, significant reduction in the switching voltages was observed and this is due to the desorption/adsorption of oxygen at the interface of GO and ZNs, which stimulates the formation/rupture of conducting paths on the application of suitable polarity voltages. This mechanism based on oxygen vacancies is well supported by the X‐ray photo‐ emission spectroscopy (XPS) measurements of these samples shown in **Figure 9**.

**Figure 9a** is the XPS graph for C1s peak in GO and GOZNs samples. The C1s graph of GO contains sp<sup>2</sup> and C─O─C peaks, whereas for the GOZNs sample, the C─O─C peak has disap‐ peared having only sp<sup>2</sup> peak in the spectra. The XPS study showed the reduction in oxygen content with the disappeared C─O─C peak for the GO matrix having ZNs, which dem‐ onstrates that GO has become comparatively less resistive having sp<sup>2</sup> character dominant. However, ZNs are well known for chemisorption of oxygen at its periphery and it can be evi‐ denced by the fitted O2 peak for O1s spectra in **Figure 9b**. Also, the peak positions for these O1 and O2 in GOZNs sample were found to be little shifted towards lower energy. Furthermore, a noticeable increment in the intensity of O2 peak was also observed in GOZNs in comparison to ZNs. The O1s peak was also found to be shifted to lower binding energy due to the addi‐ tional oxygen absorbed by ZNs as shown in **Figure 9b** [67]. Further, the presence of excess oxygen can also be clearly observed in **Figure 9c** which shows the shift in the Zn 2p peak towards lower energy in GOZNs sample in comparison to ZNs sample [67]. The performance of flexible electronic devices can be tested through flexibility and mechanical endurance mea‐ surements. The flexibility measurements were done on the Al/GOZNs/ITOPET devices and the value of resistance was plotted as a function of bending radii as shown in **Figure 10a**. The resistance was measured up to the maximum bending radius of 4 mm and amazingly found that the LRS and HRS were widely separated and can be well distinguished. The mechanical

**Figure 9.** (a) Comparative XPS spectra of GO and GOZNs for C1S peak. (b) XPS spectra of ZNs and GOZns showing O1S peak resolved into two components O1 and O2. (c) Zn2p spectra of ZNs and GOZNs samples [63].

reliability test was also performed by constantly flexing the device many times to the bending radius of 6 mm and the resistance was plotted against number of bending cycles as shown in **Figure 10b**. The HRS and LRS resistances show no noticeable degradation even up to 1000 times of repeated bending. The measurements performed on the Al/GOZNs/ITOPET device show excellent flexibility and mechanical endurance results and provide the data which show that the devices are capable for flexible memory applications. This study shows that the devices based on ZNs embedded in GO are potential candidate for future flexible non‐volatile memory applications.

in rupture of the conducting channel during the RESET process. But with the incorporation of ZNs into the GO matrix, significant reduction in the switching voltages was observed and this is due to the desorption/adsorption of oxygen at the interface of GO and ZNs, which stimulates the formation/rupture of conducting paths on the application of suitable polarity voltages. This mechanism based on oxygen vacancies is well supported by the X‐ray photo‐

**Figure 8.** Typical I‐V switching characteristics in Al/GOZNs/ITOPET devices. Inset shows the I‐V characteristics for Al/

**Figure 9a** is the XPS graph for C1s peak in GO and GOZNs samples. The C1s graph of GO

content with the disappeared C─O─C peak for the GO matrix having ZNs, which dem‐

However, ZNs are well known for chemisorption of oxygen at its periphery and it can be evi‐ denced by the fitted O2 peak for O1s spectra in **Figure 9b**. Also, the peak positions for these O1 and O2 in GOZNs sample were found to be little shifted towards lower energy. Furthermore, a noticeable increment in the intensity of O2 peak was also observed in GOZNs in comparison to ZNs. The O1s peak was also found to be shifted to lower binding energy due to the addi‐ tional oxygen absorbed by ZNs as shown in **Figure 9b** [67]. Further, the presence of excess oxygen can also be clearly observed in **Figure 9c** which shows the shift in the Zn 2p peak towards lower energy in GOZNs sample in comparison to ZNs sample [67]. The performance of flexible electronic devices can be tested through flexibility and mechanical endurance mea‐ surements. The flexibility measurements were done on the Al/GOZNs/ITOPET devices and the value of resistance was plotted as a function of bending radii as shown in **Figure 10a**. The resistance was measured up to the maximum bending radius of 4 mm and amazingly found that the LRS and HRS were widely separated and can be well distinguished. The mechanical

and C─O─C peaks, whereas for the GOZNs sample, the C─O─C peak has disap‐

peak in the spectra. The XPS study showed the reduction in oxygen

character dominant.

emission spectroscopy (XPS) measurements of these samples shown in **Figure 9**.

onstrates that GO has become comparatively less resistive having sp<sup>2</sup>

contains sp<sup>2</sup>

peared having only sp<sup>2</sup>

GO/ITOPET device [63].

28 Memristor and Memristive Neural Networks

**Figure 10.** (a) Flexibility test for various bending radius on Al/GOZNs/ITOPET RRAM device. (b) Mechanical bending endurance of device at bending radius of 6 mm on Al/GOZNs/ITOPET RRAM device [63].

#### **2.4. Nanoparticles embedded graphene oxide RRAM devices for low operating voltages and high on/off ratio**

were deposited by thermal evaporation method through a shadow mask having diameter of 200 μm. Thus, the device structure formed was Al/GOAu/ITO/glass. Another sample was also fabricated using GOAu solution by spin coating on ITO/glass substrate for XPS study. To know the chemical composition of as‐grown GOAu films by electrophoresis, XPS study was performed as shown in **Figure 12**. These XPS measurements were done to illustrate the amount of oxygen functional groups present in electrodeposited GOAu films (**Figure 12a**) and spin coated GOAu films (**Figure 12b**) (XPS for spin coating films was performed to compare the amount of oxy groups). The peaks corresponding to C1s spectra as depicted in **Figure 12** are C─C, C─O and C═O which are at respective binding energies of 284.6, 286.5 and 288.4 eV. In electrodeposited film, the C─O peak has low intensity in comparison to the C─C peak which shows that the oxygen content is less in the film. The lower oxygen content or presence of oxygen vacancies is favourable for as‐deposited films to be in low‐resistance and hence eliminating the need of forming voltages. Inset of **Figure 12a** shows the presence of Au 4f7/2and

To demonstrate the effect of Au Nps in GO devices, another film of GO having no Au Nps on ITO/glass by electrophoresis keeping same deposition parameters having Al top electrodes (Al/GO/ITO) was fabricated and measured its switching characteristics. **Figure 13a** shows typical I‐V switching characteristics of Al/GO/ITO (inset) and Al/GOAu/ITO devices, respec‐

Ω without Au Nps. Therefore, the initial resistance of the device incorporated with Au Nps was found to be 100 times lower than that of the pristine GO device. The on/off ratio between LRS and HRS in pristine GO devices is very low and that too at high voltages. GOAu devices have enhanced on/off ratio at very low switching voltages as compared to pristine GO devices which is due to the presence of Au Nps, which are working as charge trapping centres.

**Figure 12.** (a) XPS spectra for C1s peak of GOAu film grown by electrophoresis. Inset shows Au peaks for the GOAu film.

(b) C1s peak of spin‐coated GOAu film [71].

Ω with Au Nps and 1.3 × 10<sup>6</sup>

Graphene Oxide-Based Memristor

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http://dx.doi.org/10.5772/intechopen.69752

Au 4f5/2 peaks at their respective binding energies of 84 and 87.5 eV.

tively. The initial resistance of the devices was found 3.5 × 10<sup>4</sup>

RRAM devices based on oxide have good switching characteristics, but still there are two major downsides with these memories: first one is the need of an initial forming voltage [68–70] to ini‐ tiate the switching mechanism, which is detrimental to device performance, however, this issue can be resolved by manipulating the deposition and growth process and the other problem is the uncontrolled position of conductive channels formation during repetitive applied bias. To address the problem of initial forming in graphene oxide (GO)‐based devices, we adopted the method of electrophoresis to deposit the device structure [71]. Reports have shown that the graphene oxide films grown by electrophoresis are conducted or reduced in nature [72, 73].As the oxygen functional groups attached to its basal plane get removed, the graphene oxide films become semiconducting having localized π‐π electrons network. These functional groups can be eliminated by passing the current during electrophoresis deposition process, resulting GO to be reduced or semiconducting in nature. In this study, the films were deposited by electropho‐ resis and as deposited films were found to be in low‐resistance state; therefore, no high forming voltages were required to initiate the switching process. To resolve the problem of confined conducting channels, we have to understand that there is random formation of conductive fila‐ ments at nanoscale with applied bias in un‐doped films, and it is hard to confine their position precisely. The reports for RRAM devices based on transition metal oxides infused with metal‐ lic nanoparticles have shown enhancement in switching properties with the addition of metal nanoparticles [61, 74]. The present study is focused on improved switching characteristics of graphene oxide films embedded with gold nanoparticles (Au Nps), which helps to confine the conducting filaments during numerous sweep cycles. A colloidal suspension of GO with Au Nps was obtained by sonication. The films were deposited by electrophoresis process using the sonicated GO with Au Nps (GOAu) solution [71]. Electrophoresis was performed using a home‐ built assembly with a pair of ITO/glass as electrodes and a Keithley current source. GOAu films were deposited at room temperature by varying the current value ranging from 0.1 to 1.0 mA for 1–10 minutes having 1.5 cm distance between the electrodes as shown in **Figure 11**.

The thickness of deposited GOAu film was measured to be ∼85 nm. The GO layers were in the size range of 3–5 μm and Au Nps were found in the range of 10–15 nm. The switch‐ ing matrix constitutes the stack of GO layers with Au Nps. Aluminium (Al) top electrodes

**Figure 11.** GO films grown by electrophoresis process.

were deposited by thermal evaporation method through a shadow mask having diameter of 200 μm. Thus, the device structure formed was Al/GOAu/ITO/glass. Another sample was also fabricated using GOAu solution by spin coating on ITO/glass substrate for XPS study. To know the chemical composition of as‐grown GOAu films by electrophoresis, XPS study was performed as shown in **Figure 12**. These XPS measurements were done to illustrate the amount of oxygen functional groups present in electrodeposited GOAu films (**Figure 12a**) and spin coated GOAu films (**Figure 12b**) (XPS for spin coating films was performed to compare the amount of oxy groups). The peaks corresponding to C1s spectra as depicted in **Figure 12** are C─C, C─O and C═O which are at respective binding energies of 284.6, 286.5 and 288.4 eV. In electrodeposited film, the C─O peak has low intensity in comparison to the C─C peak which shows that the oxygen content is less in the film. The lower oxygen content or presence of oxygen vacancies is favourable for as‐deposited films to be in low‐resistance and hence eliminating the need of forming voltages. Inset of **Figure 12a** shows the presence of Au 4f7/2and Au 4f5/2 peaks at their respective binding energies of 84 and 87.5 eV.

**2.4. Nanoparticles embedded graphene oxide RRAM devices for low operating voltages** 

RRAM devices based on oxide have good switching characteristics, but still there are two major downsides with these memories: first one is the need of an initial forming voltage [68–70] to ini‐ tiate the switching mechanism, which is detrimental to device performance, however, this issue can be resolved by manipulating the deposition and growth process and the other problem is the uncontrolled position of conductive channels formation during repetitive applied bias. To address the problem of initial forming in graphene oxide (GO)‐based devices, we adopted the method of electrophoresis to deposit the device structure [71]. Reports have shown that the graphene oxide films grown by electrophoresis are conducted or reduced in nature [72, 73].As the oxygen functional groups attached to its basal plane get removed, the graphene oxide films become semiconducting having localized π‐π electrons network. These functional groups can be eliminated by passing the current during electrophoresis deposition process, resulting GO to be reduced or semiconducting in nature. In this study, the films were deposited by electropho‐ resis and as deposited films were found to be in low‐resistance state; therefore, no high forming voltages were required to initiate the switching process. To resolve the problem of confined conducting channels, we have to understand that there is random formation of conductive fila‐ ments at nanoscale with applied bias in un‐doped films, and it is hard to confine their position precisely. The reports for RRAM devices based on transition metal oxides infused with metal‐ lic nanoparticles have shown enhancement in switching properties with the addition of metal nanoparticles [61, 74]. The present study is focused on improved switching characteristics of graphene oxide films embedded with gold nanoparticles (Au Nps), which helps to confine the conducting filaments during numerous sweep cycles. A colloidal suspension of GO with Au Nps was obtained by sonication. The films were deposited by electrophoresis process using the sonicated GO with Au Nps (GOAu) solution [71]. Electrophoresis was performed using a home‐ built assembly with a pair of ITO/glass as electrodes and a Keithley current source. GOAu films were deposited at room temperature by varying the current value ranging from 0.1 to 1.0 mA

for 1–10 minutes having 1.5 cm distance between the electrodes as shown in **Figure 11**.

**Figure 11.** GO films grown by electrophoresis process.

The thickness of deposited GOAu film was measured to be ∼85 nm. The GO layers were in the size range of 3–5 μm and Au Nps were found in the range of 10–15 nm. The switch‐ ing matrix constitutes the stack of GO layers with Au Nps. Aluminium (Al) top electrodes

**and high on/off ratio**

30 Memristor and Memristive Neural Networks

To demonstrate the effect of Au Nps in GO devices, another film of GO having no Au Nps on ITO/glass by electrophoresis keeping same deposition parameters having Al top electrodes (Al/GO/ITO) was fabricated and measured its switching characteristics. **Figure 13a** shows typical I‐V switching characteristics of Al/GO/ITO (inset) and Al/GOAu/ITO devices, respec‐ tively. The initial resistance of the devices was found 3.5 × 10<sup>4</sup> Ω with Au Nps and 1.3 × 10<sup>6</sup> Ω without Au Nps. Therefore, the initial resistance of the device incorporated with Au Nps was found to be 100 times lower than that of the pristine GO device. The on/off ratio between LRS and HRS in pristine GO devices is very low and that too at high voltages. GOAu devices have enhanced on/off ratio at very low switching voltages as compared to pristine GO devices which is due to the presence of Au Nps, which are working as charge trapping centres.

**Figure 12.** (a) XPS spectra for C1s peak of GOAu film grown by electrophoresis. Inset shows Au peaks for the GOAu film. (b) C1s peak of spin‐coated GOAu film [71].

**Figure 13.** (a) Typical I‐V characteristics of the Al/GOAu/ITO device in semi‐log scale; inset shows I‐V characteristics for the Al/GO/ITO device. (b) log‐log I‐V plot for the GOAu device [71].

Followed by an initial random charging, the charge carriers around a single Au Np may increase due to trapping process, which results in increasing the capacitive coupling and finally increases the coulomb repulsion. Au Nps embedded in GO matrix act as small capaci‐ tors having large capacitance due to their big surface/volume area and the associated interfa‐ cial polarization. An additional barrier will be created by these metal‐island capacitors which prevent the movement of electrons in the matrix and the charge transfer through these small metal‐islands, below a particular threshold voltage gets blocked (charges get trapped) leading to an increase in resistance as well. Therefore, in GOAu devices, achieving such a huge resis‐ tance in HRS can be attributed to the coulomb blockade effect imparted by the Au Nps which

**Figure 14.** (a) Retention, (b) endurance properties and (c) statistical distribution over different cells of GOAu device in

Graphene Oxide-Based Memristor

33

http://dx.doi.org/10.5772/intechopen.69752

is associated to the quantum effect of metal nanoparticles [79, 80].

**Figure 15.** C‐V curves of (a) GO and (b) GOAu devices in LRS and HRS [71].

LRS and HRS [71].

The slope of the I‐V curve in LRS was found to be ∼1 as shown in **Figure 13b**; however, this linear current‐voltage relationship need not be ohmic: It can be Schottky‐limited conduction in the Simmons' limit of short electron mean free paths [75],while in the high voltage regime of HRS, the slope was found to be ∼4.4, which reveals that a strong space charge limited cur‐ rent (SCLC) mechanism also known as trapped charge limited current (TCLC) mechanism is prevailing in the device [76]. The TCLC behaviour of the films is in agreement with the pres‐ ence of Au Nps in the films, which are working as charge trapping centres. Hence the charges get trapped in one voltage polarity transiting the device to HRS and detrapped in the opposite polarity rendering back the device to LRS again. Therefore, the device shows bipolar switch‐ ing behaviour exhibiting trapping/detrapping mechanism. GO sheets have different types of defects, such as oxygen vacancies, dislocations etc. [77, 78]. The defects and trapping nodes present in GO sheets play a significant role in switching behaviour. Initially, the device was in LRS due to the presence of large number of oxygen vacancies and the Au Nps. The device performed well in both states showing retention, endurance and statistical distribution over different cells as shown in **Figure 14a**–**c**.

As discussed above, Au Nps dispersed in GO layers trap the charge, resulting in capacitive behaviour of the devices. In order to test this scenario, capacitance‐voltage (C‐V) measure‐ ments were carried out. **Figure 15a** and **b** shows the C‐V curves of the Al/GO/ITO and Al/ GOAu/ITO devices. The measured capacitance was found to be ∼3.4 pF in LRS and ∼11.2 pF in HRS in GO device, whereas it was ∼9 pF in LRS and ∼350 pF in HRS in the GOAu device. It was observed that in both the resistance states, capacitance values were increased by a factor of ∼10 in HRS/LRS in GOAu devices in comparison to GO devices, which is mainly due to the charge trapping process by Au Nps. In GO matrix having Au Nps, this can be explained as follows: the array of Au Nps induces the coupling capacitance and the trapping energy levels are set by the work function of Au Nps.

**Figure 14.** (a) Retention, (b) endurance properties and (c) statistical distribution over different cells of GOAu device in LRS and HRS [71].

Followed by an initial random charging, the charge carriers around a single Au Np may increase due to trapping process, which results in increasing the capacitive coupling and finally increases the coulomb repulsion. Au Nps embedded in GO matrix act as small capaci‐ tors having large capacitance due to their big surface/volume area and the associated interfa‐ cial polarization. An additional barrier will be created by these metal‐island capacitors which prevent the movement of electrons in the matrix and the charge transfer through these small metal‐islands, below a particular threshold voltage gets blocked (charges get trapped) leading to an increase in resistance as well. Therefore, in GOAu devices, achieving such a huge resis‐ tance in HRS can be attributed to the coulomb blockade effect imparted by the Au Nps which is associated to the quantum effect of metal nanoparticles [79, 80].

**Figure 15.** C‐V curves of (a) GO and (b) GOAu devices in LRS and HRS [71].

The slope of the I‐V curve in LRS was found to be ∼1 as shown in **Figure 13b**; however, this linear current‐voltage relationship need not be ohmic: It can be Schottky‐limited conduction in the Simmons' limit of short electron mean free paths [75],while in the high voltage regime of HRS, the slope was found to be ∼4.4, which reveals that a strong space charge limited cur‐ rent (SCLC) mechanism also known as trapped charge limited current (TCLC) mechanism is prevailing in the device [76]. The TCLC behaviour of the films is in agreement with the pres‐ ence of Au Nps in the films, which are working as charge trapping centres. Hence the charges get trapped in one voltage polarity transiting the device to HRS and detrapped in the opposite polarity rendering back the device to LRS again. Therefore, the device shows bipolar switch‐ ing behaviour exhibiting trapping/detrapping mechanism. GO sheets have different types of defects, such as oxygen vacancies, dislocations etc. [77, 78]. The defects and trapping nodes present in GO sheets play a significant role in switching behaviour. Initially, the device was in LRS due to the presence of large number of oxygen vacancies and the Au Nps. The device performed well in both states showing retention, endurance and statistical distribution over

**Figure 13.** (a) Typical I‐V characteristics of the Al/GOAu/ITO device in semi‐log scale; inset shows I‐V characteristics for

As discussed above, Au Nps dispersed in GO layers trap the charge, resulting in capacitive behaviour of the devices. In order to test this scenario, capacitance‐voltage (C‐V) measure‐ ments were carried out. **Figure 15a** and **b** shows the C‐V curves of the Al/GO/ITO and Al/ GOAu/ITO devices. The measured capacitance was found to be ∼3.4 pF in LRS and ∼11.2 pF in HRS in GO device, whereas it was ∼9 pF in LRS and ∼350 pF in HRS in the GOAu device. It was observed that in both the resistance states, capacitance values were increased by a factor of ∼10 in HRS/LRS in GOAu devices in comparison to GO devices, which is mainly due to the charge trapping process by Au Nps. In GO matrix having Au Nps, this can be explained as follows: the array of Au Nps induces the coupling capacitance and the trapping energy levels

different cells as shown in **Figure 14a**–**c**.

the Al/GO/ITO device. (b) log‐log I‐V plot for the GOAu device [71].

32 Memristor and Memristive Neural Networks

are set by the work function of Au Nps.

## **3. Conclusions**

In summary, graphene oxide is a promising material for RRAM devices due to its high scalability and unique physical‐chemical properties. Fabrication of GO and its films, composites and het‐ erostructures are very cost effective and opens up the direction for commercialization. Showing forming‐free behaviour is an excellent property of GO devices over other oxide‐based devices that require initial high voltages to start the switching process. Multi‐level switching in GO‐ based heterostructures has the potential of high‐density data storage, which is the need of future non‐volatile memories. Flexibility and mechanical endurance observed in GO‐based composite RRAM devices have prospects in portable and flexible devices which is advantageous over the rigid silicon technology. Gold nanoparticles embedded in GO have shown enhanced switching properties with very high on/off resistance ratio and very low switching voltages, which are suit‐ able for low power resistive memory devices. The mechanism underlying the graphene oxide‐ based memories is the formation of conductive filaments due to the roles played by oxygen ions and vacancies. Therefore, GO‐based RRAM devices have enough potential to become one of the important non‐volatile memories due to their encouraging properties of forming free, multi‐bit data storage and low power flexible devices. However, further research is still needed towards scaling of these devices below 10 nm node and that too having fast switching speeds to establish graphene oxide‐based non‐volatile resistive devices achieve a niche in memory industry.

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## **Acknowledgements**

The authors acknowledge the financial support from DOD Grant (AFOSR‐FA9550‐16‐1‐0295) and IFN‐NSF Grant (EPS‐01002410) for travel support.

## **Author details**

Geetika Khurana1 \*, Nitu Kumar1 , James F. Scott2,3 and Ram S. Katiyar1

\*Address all correspondence to: geetkhurana84@gmail.com


## **References**

[1] Chua LO. Memristor – The missing circuit element. IEEE Transactions Circuit Theory CT‐18. 1971;**18**:507‐519

[2] Strukov DB, Snider GS, Stewart DR, Williams RS. The missing memristor found. Nature. 2008;**453**:80‐83

**3. Conclusions**

34 Memristor and Memristive Neural Networks

**Acknowledgements**

**Author details**

Geetika Khurana1

**References**

CT‐18. 1971;**18**:507‐519

and IFN‐NSF Grant (EPS‐01002410) for travel support.

\*, Nitu Kumar1

1 University of Puerto Rico, San Juan, Puerto Rico

\*Address all correspondence to: geetkhurana84@gmail.com

2 Department of Chemistry, University of St Andrews, St Andrews, UK

3 Department of Physics, University of St Andrews, St Andrews, UK

In summary, graphene oxide is a promising material for RRAM devices due to its high scalability and unique physical‐chemical properties. Fabrication of GO and its films, composites and het‐ erostructures are very cost effective and opens up the direction for commercialization. Showing forming‐free behaviour is an excellent property of GO devices over other oxide‐based devices that require initial high voltages to start the switching process. Multi‐level switching in GO‐ based heterostructures has the potential of high‐density data storage, which is the need of future non‐volatile memories. Flexibility and mechanical endurance observed in GO‐based composite RRAM devices have prospects in portable and flexible devices which is advantageous over the rigid silicon technology. Gold nanoparticles embedded in GO have shown enhanced switching properties with very high on/off resistance ratio and very low switching voltages, which are suit‐ able for low power resistive memory devices. The mechanism underlying the graphene oxide‐ based memories is the formation of conductive filaments due to the roles played by oxygen ions and vacancies. Therefore, GO‐based RRAM devices have enough potential to become one of the important non‐volatile memories due to their encouraging properties of forming free, multi‐bit data storage and low power flexible devices. However, further research is still needed towards scaling of these devices below 10 nm node and that too having fast switching speeds to establish graphene oxide‐based non‐volatile resistive devices achieve a niche in memory industry.

The authors acknowledge the financial support from DOD Grant (AFOSR‐FA9550‐16‐1‐0295)

, James F. Scott2,3 and Ram S. Katiyar1

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**Chapter 3**

**Provisional chapter**

**Emulator Circuits and Resistive Switching Parameters**

Chua predicted the existence of the fundamental circuit element, which provides the linkage of flux (*ϕ*) and charge (*q*). The new circuit element that is called memristor (memory + resistor) was demonstrated by Hewlett Packard (HP) researchers in 2008. Researchers focused on memristor fabrication, modeling, and its application with other circuit elements. Researchers could not find the commercially memristor devices in the market because of some fabrication difficulties. For this reason, researchers focused on the memristor modeling to analyze its characteristics with other circuit elements. This chapter presents a review of the general information of memristor and its device parameters. The chapter is continued with the details of memristor mathematical and SPICE

**Keywords:** memristor, memristor models, SPICE, memristor emulator, active circuit

Both active circuit elements and passive circuit elements are used in circuit design, and the first circuit elements that come to mind are passive circuit elements: resistor, capacitor, and inductor. Resistor, capacitor, and inductor define the relationship between the voltage and current, voltage and charge, and current and flux, respectively. Leon Chua from the University of California (Berkeley) showed the missing relationship as shown in **Figure 1** between flux and

At the same time, Chua called the missing circuit element as a memristor (memory + resistor) and presented the mathematical equations of the new circuit element. But the seminal paper

models and memristor emulators based on the other circuit elements.

**Emulator Circuits and Resistive Switching Parameters** 

DOI: 10.5772/intechopen.71903

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

**of Memristor**

**Abstract**

**1. Introduction**

current in 1971 and 1976 [1, 2].

**of Memristor**

Abdullah Yesil, Fatih Gül and Yunus Babacan

Additional information is available at the end of the chapter

Abdullah Yesil, Fatih Gül and Yunus Babacan

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.71903

element-based memristors


**Provisional chapter**

## **Emulator Circuits and Resistive Switching Parameters of Memristor of Memristor**

**Emulator Circuits and Resistive Switching Parameters** 

DOI: 10.5772/intechopen.71903

Abdullah Yesil, Fatih Gül and Yunus Babacan

[77] Khurana G, Kumar N, Kotnala RK, Nautiyal T, Katiyar RS. Temperature tuned defect induced magnetism in reduced graphene oxide. Nanoscale. 2013;**5**:3346‐3351

[78] Rozada R, Paredes JI, Villar‐Rodil S, Martínez‐Alonso A, Tascón JMD. Towards full repair of defects in reduced graphene oxide films by two‐step graphitization. Nano

[79] Lu J, Moon KS, Xu J, Wong CP. Synthesis and dielectric properties of novel high‐K poly‐ mer composites containing in‐situ formed silver nanoparticles for embedded capacitor

[80] Feng Q, Dang Z, Li N, Cao X. Preparation and dielectric property of Ag‐PVA nano‐com‐

applications. Journal of Materials Chemistry. 2006;**16**:1543‐1548

posite. Materials Science and Engineering: B. 2003;**99**:325‐328

Research. 2013;**6**:216‐233

40 Memristor and Memristive Neural Networks

Abdullah Yesil, Fatih Gül and Yunus Babacan Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.71903

#### **Abstract**

Chua predicted the existence of the fundamental circuit element, which provides the linkage of flux (*ϕ*) and charge (*q*). The new circuit element that is called memristor (memory + resistor) was demonstrated by Hewlett Packard (HP) researchers in 2008. Researchers focused on memristor fabrication, modeling, and its application with other circuit elements. Researchers could not find the commercially memristor devices in the market because of some fabrication difficulties. For this reason, researchers focused on the memristor modeling to analyze its characteristics with other circuit elements. This chapter presents a review of the general information of memristor and its device parameters. The chapter is continued with the details of memristor mathematical and SPICE models and memristor emulators based on the other circuit elements.

**Keywords:** memristor, memristor models, SPICE, memristor emulator, active circuit element-based memristors

#### **1. Introduction**

Both active circuit elements and passive circuit elements are used in circuit design, and the first circuit elements that come to mind are passive circuit elements: resistor, capacitor, and inductor. Resistor, capacitor, and inductor define the relationship between the voltage and current, voltage and charge, and current and flux, respectively. Leon Chua from the University of California (Berkeley) showed the missing relationship as shown in **Figure 1** between flux and current in 1971 and 1976 [1, 2].

At the same time, Chua called the missing circuit element as a memristor (memory + resistor) and presented the mathematical equations of the new circuit element. But the seminal paper

main structures which are named doped and undoped region as shown in **Figure 3**, and the

Memristor acts as a conductor if the thickness of the doped region becomes wide as shown in **Figure 3b**. Undoped region becomes wide as shown in **Figure 3c**, and memristor behaves as a

*dt* <sup>=</sup> *μv <sup>R</sup>* \_\_\_\_\_*ON*

*dt* <sup>=</sup> *μv <sup>R</sup>* \_\_\_\_\_*ON*

 **(a) (b)** 

**D**

**(c)** 

**Figure 3.** Memristor (a) initial state, (b) low-resistance state, and (c) high-resistance state.

Undoped Region

Doped Region,w

The first function which is called window function is presented by HP research team [3] as

 is the electron mobility, and *w* and *D* denote the doped area of memristor and thickness of the memristor, respectively. The resistances of the high and low dopant concentrations are symbolized with *RON* and *ROFF*, respectively. Researchers added a function to the memristor mathematical model to take into account the nonlinear dopant effect [3, 5–7]. Equation (3) is

], (*<sup>x</sup>* <sup>=</sup> \_\_*<sup>w</sup>*

*<sup>D</sup>*) (2)

*<sup>D</sup>*<sup>2</sup> *<sup>i</sup>*(*t*) (3)

Emulator Circuits and Resistive Switching Parameters of Memristor

http://dx.doi.org/10.5772/intechopen.71903

43

*<sup>D</sup>*<sup>2</sup> *<sup>i</sup>*(*t*)*f*(*x*) (4)

*<sup>D</sup>* (5)

Undoped Region

Doped Region

**D**

**w**

memristance changes the ratios of the doped region and device thickness.

*M*(*x*) = [*RON x* + *ROFF*(1 − *x*)

Memristance is as below:

rearranged as follows:

shown below:

The *μv*

The change of the *x* value is depicted:

\_\_\_ *dx*

\_\_\_ *dx*

Doped Region

**w**

*<sup>f</sup>*(*x*) <sup>=</sup> \_\_\_\_\_ *<sup>x</sup>*(<sup>1</sup> <sup>−</sup> *<sup>x</sup>*)

**D**

Undoped Region

high-resistance element when the input signal applied in an opposite direction.

**Figure 1.** The fundamental two-terminal passive circuit elements.

**Figure 2.** The scanning tunneling microscope image of the memristor [4].

of Chua could not find attentions among the researchers because of the technical fabrication difficulties of the memristor. Therefore, researchers did not focus on the memristor and its application until its first fabrication of memristor by HP researchers in 2008 [3]. The first memristor is made from TiO<sup>2</sup> thin film and has crossbar structure as shown in **Figure 2**.

The HP research team also presented the mathematical model of TiO2 memristor, and currentvoltage relationship is defined by

$$V = \begin{bmatrix} M(\mathbf{x}\_{1'}, \mathbf{x}\_{2'}, \dots, \mathbf{x}\_n) \end{bmatrix} I \tag{1}$$

where *V* is the voltage and *I* is the current. Here, *M* is the resistance of memristor and memristance and depends on *xi* state variables. Memristance which performs nonlinear characteristics depends on frequency and applied input signal. The TiO2 memristor consists of two main structures which are named doped and undoped region as shown in **Figure 3**, and the memristance changes the ratios of the doped region and device thickness.

Memristor acts as a conductor if the thickness of the doped region becomes wide as shown in **Figure 3b**. Undoped region becomes wide as shown in **Figure 3c**, and memristor behaves as a high-resistance element when the input signal applied in an opposite direction.

Memristance is as below:

of Chua could not find attentions among the researchers because of the technical fabrication difficulties of the memristor. Therefore, researchers did not focus on the memristor and its application until its first fabrication of memristor by HP researchers in 2008 [3]. The first

, *x*2

where *V* is the voltage and *I* is the current. Here, *M* is the resistance of memristor and mem-

The HP research team also presented the mathematical model of TiO2

**Figure 2.** The scanning tunneling microscope image of the memristor [4].

teristics depends on frequency and applied input signal. The TiO2

thin film and has crossbar structure as shown in **Figure 2**.

state variables. Memristance which performs nonlinear charac-

memristor, and current-

memristor consists of two

, …*xn*)]*I* (1)

memristor is made from TiO<sup>2</sup>

ristance and depends on *xi*

voltage relationship is defined by

*V* = [*M*(*x*<sup>1</sup>

**Figure 1.** The fundamental two-terminal passive circuit elements.

42 Memristor and Memristive Neural Networks

$$M(\mathbf{x}) = \begin{bmatrix} \mathbb{R}\_{\text{cov}} \mathbf{x} + \mathbb{R}\_{\text{cov}} (1 - \mathbf{x}) \end{bmatrix}\_{\prime} \begin{pmatrix} \mathbf{x} = \frac{w}{D} \end{pmatrix} \tag{2}$$

The change of the *x* value is depicted:

*<sup>f</sup>*(*x*) <sup>=</sup> \_\_\_\_\_ *<sup>x</sup>*(<sup>1</sup> <sup>−</sup> *<sup>x</sup>*)

$$\frac{d\mathbf{x}}{dt} = \frac{\mu\_v R\_{\text{ON}}}{D^2} \mathbf{i}(t) \tag{3}$$

The *μv* is the electron mobility, and *w* and *D* denote the doped area of memristor and thickness of the memristor, respectively. The resistances of the high and low dopant concentrations are symbolized with *RON* and *ROFF*, respectively. Researchers added a function to the memristor mathematical model to take into account the nonlinear dopant effect [3, 5–7]. Equation (3) is rearranged as follows:

$$\frac{d\mathbf{x}}{dt} = \frac{\mu\_\nu R\_{\rm ON}}{D^2} \mathbf{i}(\mathbf{t}) \mathbf{f}(\mathbf{x}) \tag{4}$$

*<sup>D</sup>* (5)

The first function which is called window function is presented by HP research team [3] as shown below:

**Figure 3.** Memristor (a) initial state, (b) low-resistance state, and (c) high-resistance state.

**Figure 4.** Window function presented by Wolf and Joglekar [5].

The HP model is linear and very simple; so Wolf and Joglekar [5] depicted the new window function as shown below:

$$f(\mathbf{x}) = \mathbf{1} - (2\mathbf{x} - \mathbf{1})^{2p} \tag{6}$$

Model function of Prodromakis et al. becomes higher than the value of 1 unlike previous win-

Emulator Circuits and Resistive Switching Parameters of Memristor

http://dx.doi.org/10.5772/intechopen.71903

45

Researchers suggested various mathematical memristor models such as nonlinear ion-drift model [8], Simmons' tunnel barrier model [9], and ThrEshold Adaptive Memristor (TEAM) model [10] different from the linear HP model. The chapter is continued with memristor

The pinched hysteresis loops serve as a fingerprint in the characterization of memristors [11] as shown in **Figure 7**. It is to say that, if any two-terminal device is showing pinched hysteresis loop, a memristor regardless of the device material is accepted. Resistive switching (or memristive behavior) in metal-oxide semiconductor was first observed by Hickmott in 1962, but it was interpreted as the current anomaly [12]. As in resistive switching devices, a typical pinched hysteresis loop is seen at the first and third quadrants of the current-voltage (I-V) curves [13]. Put differently, all memristors can be accepted as resistive switching devices

**a) b)**

**Figure 7.** (a) Schematic representation of a memristor device and (b) typical pinched hysteresis current-voltage loop of

dow functions. The function depends on the various *p*-values shown in **Figure 6**.

**2. Memristor switching device parameters**

Boom Electrode

Top Electrodes

Acve Layer or Layers

memristor devices.

**Figure 6.** Window function presented by Prodromakis et al. [7].

regardless of the operating mechanisms and the device material [14].

device.

The function is starting to similar the rectangular shape when *p*-value becomes higher, namely, dopant drift is decreasing as shown in **Figure 4**.

Biolek et al. [6] modified the model of Wolf and Joglekar:

$$f(\mathbf{x}) = \mathbf{1} - (\mathbf{x} - \text{stp}(-i))^{2\rho} \tag{7a}$$

$$stp(\mathbf{j}) = \begin{cases} 1, i \ge 0 \\ 0, i < 0 \end{cases} \tag{7b}$$

The window function which is presented by Biolek is shown in **Figure 5**.

Prodromakis et al. [7] depict the versatile model as the following:

$$f(\mathbf{x}) = j(1 - [(\mathbf{x} - 0.5)^2 + 0.75]^\circ) \tag{8}$$

**Figure 5.** Window function presented by Biolek et al. [6].

**Figure 6.** Window function presented by Prodromakis et al. [7].

The HP model is linear and very simple; so Wolf and Joglekar [5] depicted the new window

*f*(*x*) = 1 − (2*x* − 1)2*<sup>p</sup>* (6)

The function is starting to similar the rectangular shape when *p*-value becomes higher,

*f*(*x*) = 1 − (*x* − *stp*(−*i*))2*<sup>p</sup>* (7a)

*f*(*x*) = *j*(1 − [(*x* − 0.5)<sup>2</sup> + 0.75]*p*) (8)

The window function which is presented by Biolek is shown in **Figure 5**.

Prodromakis et al. [7] depict the versatile model as the following:

1, *i* ≥ 0

<sup>0</sup>, *<sup>i</sup>* <sup>&</sup>lt; <sup>0</sup> (7b)

function as shown below:

44 Memristor and Memristive Neural Networks

namely, dopant drift is decreasing as shown in **Figure 4**. Biolek et al. [6] modified the model of Wolf and Joglekar:

**Figure 4.** Window function presented by Wolf and Joglekar [5].

*stp*(*i*) <sup>=</sup> {

**Figure 5.** Window function presented by Biolek et al. [6].

Model function of Prodromakis et al. becomes higher than the value of 1 unlike previous window functions. The function depends on the various *p*-values shown in **Figure 6**.

Researchers suggested various mathematical memristor models such as nonlinear ion-drift model [8], Simmons' tunnel barrier model [9], and ThrEshold Adaptive Memristor (TEAM) model [10] different from the linear HP model. The chapter is continued with memristor device.

#### **2. Memristor switching device parameters**

The pinched hysteresis loops serve as a fingerprint in the characterization of memristors [11] as shown in **Figure 7**. It is to say that, if any two-terminal device is showing pinched hysteresis loop, a memristor regardless of the device material is accepted. Resistive switching (or memristive behavior) in metal-oxide semiconductor was first observed by Hickmott in 1962, but it was interpreted as the current anomaly [12]. As in resistive switching devices, a typical pinched hysteresis loop is seen at the first and third quadrants of the current-voltage (I-V) curves [13]. Put differently, all memristors can be accepted as resistive switching devices regardless of the operating mechanisms and the device material [14].

**Figure 7.** (a) Schematic representation of a memristor device and (b) typical pinched hysteresis current-voltage loop of memristor devices.

#### **2.1. Active layer material and top/bottom electrode**

The semiconductor-based memristor devices usually consist of an active layer sandwiched between a top and a bottom electrode (TE/BE) depicted in **Figure 7**. The first physical implementation of the memristor was achieved by HP labs using TiO2 metal-oxide active layer [3]. After that, several physical memristor devices suggested the use of different materials and production methods. Most metal-oxide semiconductors exhibit memristor characteristics, including TiO<sup>2</sup> , ZnO, HfO2 , VO2 , TaOx , and so on [13, 15, 16]. There are two types of contact in semiconductor: one is of Schottky (rectifying), and the other one is ohmic. Several electrode materials can be used as TE or BE including Pt, Au, Ag, Al, etc. In one diode-one resistor (1D1R) type memory cell memristor device, one of the electrodes must be a Schottky contact [17].

in the active layer. Both types of mechanisms can be observed in the memristor devices as

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It is well known that reversible switching between a low-resistance state (LRS) or ON (SET) and a high-resistance state (HRS) or OFF (RESET) can be achieved by applying a certain voltage [18]. Operation voltage is also an important value for CMOS or other device integrations for memristor devices. Another criterion for the memristor devices is the power consumption related to the operation current. With the aim of escape permanent damage from over current, the compliance or limit current (CC) must be set in both unipolar and bipolar operations [13]. The compliance current is also related to power consumption of a memristor device [19].

The memristor has two states when used as a switching device: the high-resistance state (HRS) or OFF (RESET) state and the low-resistance state (LRS) or ON (SET) state [13]. The ON/OFF ratio defined as the proportion between resistances in HRS and LRS is some of the

The time to hold ON/OFF state is an important criterion when memristor device used a resistive switching memory or ReRAM element [20]. It is expected that the memristor device's distribution of the HRS or LRS state which is shown in **Figure 10** has acceptable values besides its ON/OFF ratio [19]. Since the memory unit needs to be repeatedly read or written by the other control units, cycling endurance is one of the main importance of memristor-based memory

Some of recent memristor devices which are composed of various materials are compared according to the some important parameters as shown in **Table 1** [19, 22–24]. The chapter is

**Figure 9.** Typical current-voltage curves of memristor devices: (a) filamentary and (b) homogenous transitions on

most important parameters when memristors are used as switching device [18].

continued with memristor emulators based on the active circuit elements.

shown in **Figure 9** and depend on the material and fabrication methods [18].

**2.4. Operation current-voltage**

**2.6. Retention time and endurance**

**2.5. ON/OFF ratio**

devices [18].

bipolar operation [19].

#### **2.2. Unipolar or bipolar operation**

The unipolar and bipolar operation of memristor devices which are shown in **Figure 8** can be categorized in according with current-voltage characteristics. In unipolar operation characteristics depend only on the amplitude of the applied voltage, whereas bipolar operations are resolved by polarity and amplitude of the applied voltage [13]. Unipolar operation is more striking than bipolar operation in memristor switching devices, since it needs simple circuits. But then, bipolar operation has generally high uniformity and more endurance compared to unipolar operation [18].

#### **2.3. Physical mechanism**

There are two types of physical working mechanisms in the explanation of the time-dependent current-voltage characteristics, based on molecular or ionic models: the homogeneous interface type and the filamentary (conduction path) type [13, 16]. In the homogeneous type, the migration of oxygen vacancies as the majority carriers causes change of resistance. The filament-type mechanism is associated with the formation and rupture of conductive filaments

**Figure 8.** Typical current-voltage curves of memristor devices (a) unipolar and (b) bipolar.

in the active layer. Both types of mechanisms can be observed in the memristor devices as shown in **Figure 9** and depend on the material and fabrication methods [18].

#### **2.4. Operation current-voltage**

It is well known that reversible switching between a low-resistance state (LRS) or ON (SET) and a high-resistance state (HRS) or OFF (RESET) can be achieved by applying a certain voltage [18]. Operation voltage is also an important value for CMOS or other device integrations for memristor devices. Another criterion for the memristor devices is the power consumption related to the operation current. With the aim of escape permanent damage from over current, the compliance or limit current (CC) must be set in both unipolar and bipolar operations [13]. The compliance current is also related to power consumption of a memristor device [19].

#### **2.5. ON/OFF ratio**

**2.1. Active layer material and top/bottom electrode**

, ZnO, HfO2

**2.2. Unipolar or bipolar operation**

46 Memristor and Memristive Neural Networks

unipolar operation [18].

**2.3. Physical mechanism**

including TiO<sup>2</sup>

mentation of the memristor was achieved by HP labs using TiO2

, TaOx

**Figure 8.** Typical current-voltage curves of memristor devices (a) unipolar and (b) bipolar.

, VO2

The semiconductor-based memristor devices usually consist of an active layer sandwiched between a top and a bottom electrode (TE/BE) depicted in **Figure 7**. The first physical imple-

After that, several physical memristor devices suggested the use of different materials and production methods. Most metal-oxide semiconductors exhibit memristor characteristics,

in semiconductor: one is of Schottky (rectifying), and the other one is ohmic. Several electrode materials can be used as TE or BE including Pt, Au, Ag, Al, etc. In one diode-one resistor (1D1R) type memory cell memristor device, one of the electrodes must be a Schottky contact [17].

The unipolar and bipolar operation of memristor devices which are shown in **Figure 8** can be categorized in according with current-voltage characteristics. In unipolar operation characteristics depend only on the amplitude of the applied voltage, whereas bipolar operations are resolved by polarity and amplitude of the applied voltage [13]. Unipolar operation is more striking than bipolar operation in memristor switching devices, since it needs simple circuits. But then, bipolar operation has generally high uniformity and more endurance compared to

There are two types of physical working mechanisms in the explanation of the time-dependent current-voltage characteristics, based on molecular or ionic models: the homogeneous interface type and the filamentary (conduction path) type [13, 16]. In the homogeneous type, the migration of oxygen vacancies as the majority carriers causes change of resistance. The filament-type mechanism is associated with the formation and rupture of conductive filaments

metal-oxide active layer [3].

, and so on [13, 15, 16]. There are two types of contact

The memristor has two states when used as a switching device: the high-resistance state (HRS) or OFF (RESET) state and the low-resistance state (LRS) or ON (SET) state [13]. The ON/OFF ratio defined as the proportion between resistances in HRS and LRS is some of the most important parameters when memristors are used as switching device [18].

#### **2.6. Retention time and endurance**

The time to hold ON/OFF state is an important criterion when memristor device used a resistive switching memory or ReRAM element [20]. It is expected that the memristor device's distribution of the HRS or LRS state which is shown in **Figure 10** has acceptable values besides its ON/OFF ratio [19]. Since the memory unit needs to be repeatedly read or written by the other control units, cycling endurance is one of the main importance of memristor-based memory devices [18].

Some of recent memristor devices which are composed of various materials are compared according to the some important parameters as shown in **Table 1** [19, 22–24]. The chapter is continued with memristor emulators based on the active circuit elements.

**Figure 9.** Typical current-voltage curves of memristor devices: (a) filamentary and (b) homogenous transitions on bipolar operation [19].

**Figure 10.** Typical endurance test of a memristor device @0.1 V for 100 cycles [21].


**Table 1.** Comparison table of some recent memristor devices.

#### **3. Memristor models and emulators**

Many SPICE models and emulators are presented by researchers [6, 25–47]. The first and applicable memristor model has been presented by Biolek and co-workers [6]. This model takes into account the boundary conditions using window function, and the feedback-controlled integrator is used to implement memory effect of the memristor. The block diagram of memristor and its SPICE model is shown in **Figure 11**. All simulation results which are shown in **Figure 12** are completed using SPICE codes as shown below. Each curve is compatible with TiO<sup>2</sup> memristor, and boundary effects are taken into account (**Table 2**).

Another active circuit element-based grounded memristor emulator [36] has been implemented by using current backward transconductance amplifier (CBTA). This emulator consists of two different circuits such as decremental and incremental type given in **Figure 14**. Each memristor emulator is composed of a single CBTA, two resistors, one grounded capacitor, and single analog multiplier. In order to validate the feasibility of the presented memris-

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**Figure 12.** Charge-flux, current-voltage, current-voltage-time, and x-time curves for memristor model [6].

The generalized mutator structure based on adder and subtractor has been proposed by Minaei et al. [37]. As far as connection ports are concerned, the generalized structure employs memristor, meminductor, and memcapacitor without using analog multiplier. By selecting an inductor to port 3, a capacitor to port 4, and a nonlinear resistor such as a diode to port 1, the generalized structure given in **Figure 15** is utilized as memristor. Nonetheless, so as to verify

the workableness of the presented structure, the SPICE simulation results are given.

tor, only SPICE simulation results have been given.

**Figure 11.** (a) Block diagram and (b) SPICE model of the memristor [6].

Researchers are not able to reach the memristor devices in the market because of some production problems of the memristor. For this reason, researchers focused on the designing of memristor emulators to use with other circuit elements. Yener and Kuntman reported full active device-based memristor emulator which is consisting of differential difference current conveyor (DDCC) [35]. The proposed grounded memristor emulator consists of four circuit blocks based on DDCC as shown in **Figure 13**. Furthermore, there are no experimental results; however, its SPICE simulation results are given.

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**Figure 11.** (a) Block diagram and (b) SPICE model of the memristor [6].

**3. Memristor models and emulators**

**Table 1.** Comparison table of some recent memristor devices.

**TE/BE Operation mode**

48 Memristor and Memristive Neural Networks

**Figure 10.** Typical endurance test of a memristor device @0.1 V for 100 cycles [21].

**Operation mechanism**

however, its SPICE simulation results are given.

TiO<sup>2</sup>

**Active layer material**

Many SPICE models and emulators are presented by researchers [6, 25–47]. The first and applicable memristor model has been presented by Biolek and co-workers [6]. This model takes into account the boundary conditions using window function, and the feedback-controlled integrator is used to implement memory effect of the memristor. The block diagram of memristor and its SPICE model is shown in **Figure 11**. All simulation results which are shown in **Figure 12** are completed using SPICE codes as shown below. Each curve is compatible with

**Operation voltage**

ZnO Al/Al Bipolar Homogenous −1.5 V/+1.5 V 5 × 10<sup>1</sup> N/A 100 [19] TiO<sup>2</sup> Al/Al Bipolar Filamentary −3 V/+1.5 V 8 × 102 N/A 1012 [22] HfO2 Pt/Ti Bipolar Filamentary −3.5 V/+2 V 10<sup>3</sup> 10<sup>4</sup> 1000 [23] TaOx Pt/Pt Unipolar Filamentary −1.5 V/+1 V 10<sup>1</sup> N/A 1000 [24]

**ON/OFF ratio**

**Retention time**

**Endurance Ref.**

Researchers are not able to reach the memristor devices in the market because of some production problems of the memristor. For this reason, researchers focused on the designing of memristor emulators to use with other circuit elements. Yener and Kuntman reported full active device-based memristor emulator which is consisting of differential difference current conveyor (DDCC) [35]. The proposed grounded memristor emulator consists of four circuit blocks based on DDCC as shown in **Figure 13**. Furthermore, there are no experimental results;

memristor, and boundary effects are taken into account (**Table 2**).

**Figure 12.** Charge-flux, current-voltage, current-voltage-time, and x-time curves for memristor model [6].

Another active circuit element-based grounded memristor emulator [36] has been implemented by using current backward transconductance amplifier (CBTA). This emulator consists of two different circuits such as decremental and incremental type given in **Figure 14**. Each memristor emulator is composed of a single CBTA, two resistors, one grounded capacitor, and single analog multiplier. In order to validate the feasibility of the presented memristor, only SPICE simulation results have been given.

The generalized mutator structure based on adder and subtractor has been proposed by Minaei et al. [37]. As far as connection ports are concerned, the generalized structure employs memristor, meminductor, and memcapacitor without using analog multiplier. By selecting an inductor to port 3, a capacitor to port 4, and a nonlinear resistor such as a diode to port 1, the generalized structure given in **Figure 15** is utilized as memristor. Nonetheless, so as to verify the workableness of the presented structure, the SPICE simulation results are given.


**Table 2.** SPICE codes of modeled memristor [6].

Kim and co-workers presented the active circuit element-based memristor emulator [38]. This circuit is also implemented on the bread board using discrete circuit elements that are ADL1116PAL for NMOS transistors, ADL1117PAL for PMOS transistors, TL082 for OPAMP, and AD633 for analog multiplier and passive elements. There are three important tasks to implement memristor emulator: memory effect, frequency-/voltage-dependent characteristics, and nonlinearity. Memory effect and frequency/voltage dependency characteristics are implemented by using a capacitor like many other previous emulator circuits. Nonlinear characteristic of the memristor is obtained using multiplier circuit block. But each used block gives rise to extra power dissipation and more complex circuit (**Figure 16**).

Another active circuit-based memristor emulators which are shown in **Figure 17** have been presented by Abuelma'atti and Khalifa [39]. Each emulator which is based on current-feedback operational amplifier (CFOA) enjoys operating two different types like decremental and incremental memristor emulators. This situation is a disadvantage of the emulator besides its grounded structure. Each circuit comprises three CFOAs, four resistors, two capacitors, and germanium diode without using an analog multiplier. Nonlinear characteristic is provided by germanium diode. CFOA which is an active element is modeled by AD844 commercially

**Figure 14.** CBTA-based memristor emulator (a) decremental structure and (b) incremental structure [36].

V1 **(+)**

I1

**(-)**

**Subtractor**

V3

I3

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**Adder**

**(+)**

**(-)**

I4 V4

available active devices, and experimental results have been investigated.

V2

**Figure 15.** Generalized mutator structure based on adder and subtractor [37].

I2

**Figure 13.** DDCC-based memristor emulator which is presented by Yener and Kuntman [35].

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**Figure 14.** CBTA-based memristor emulator (a) decremental structure and (b) incremental structure [36].

**Figure 15.** Generalized mutator structure based on adder and subtractor [37].

Kim and co-workers presented the active circuit element-based memristor emulator [38]. This circuit is also implemented on the bread board using discrete circuit elements that are ADL1116PAL for NMOS transistors, ADL1117PAL for PMOS transistors, TL082 for OPAMP, and AD633 for analog multiplier and passive elements. There are three important tasks to implement memristor emulator: memory effect, frequency-/voltage-dependent characteristics, and nonlinearity. Memory effect and frequency/voltage dependency characteristics are implemented by using a capacitor like many other previous emulator circuits. Nonlinear characteristic of the memristor is obtained using multiplier circuit block. But each used block

**DDCC**

**Multiplier**

**DDCC Summer**

**DDCC**

**Multiplier**

**Memristor**

\* RESISTIVE PORT OF THE MEMRISTOR \*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Eflux flux 0 value = {SDT(V(plus,minus))} \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Echarge charge 0 value = {SDT(I(Emem))} \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\* FOR NONLINEAR DRIFT MODELING \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*window function, according to Joglekar

Emem plus aux value = {−I(Emem)\*V(x)\*(Roff-Ron)}

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

Roff aux minus {Roff}

\*Flux computation\*

\*Charge computation\*

\* WINDOW FUNCTIONS

.func f(x,p) = {1-(2\*x-1)^(2\*p)} \*proposed window function ;.func f(x,i,p) = {1-(x-stp(−i))^(2\*p)}

.ENDS memristor

gives rise to extra power dissipation and more complex circuit (**Figure 16**).

Im(t)

Vm(t)

\* HP Memristor SPICE Model \* For Transient Analysis only \* created by Zdenek and Dalibor Biolek

\* Ron, Roff - Resistance in ON/OFF States

50 Memristor and Memristive Neural Networks

\* p - Parameter of the WINDOW-function \* for modeling nonlinear boundary conditions \* x - W/D Ratio, W is the actual width \* of the doped area (from 0 to D)

.SUBCKT memristor Plus Minus PARAMS:

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \* DIFFERENTIAL EQUATION MODELING \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Gx 0 x value = {I(Emem)\*uv\*Ron/D^2\*f(V(x),p)} Cx x 0 1 IC = {(Roff-Rinit)/(Roff-Ron)}

**Table 2.** SPICE codes of modeled memristor [6].

+ Ron = 1 K Roff = 100 K Rinit = 80 K D = 10 N uv = 10F p = 1

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*

Raux x 0 1T

\* Rinit - Resistance at T = 0 \* D - Width of the thin film \* uv - Migration coefficient

**DDCC**

**α**

**Integrator**

**Figure 13.** DDCC-based memristor emulator which is presented by Yener and Kuntman [35].

Another active circuit-based memristor emulators which are shown in **Figure 17** have been presented by Abuelma'atti and Khalifa [39]. Each emulator which is based on current-feedback operational amplifier (CFOA) enjoys operating two different types like decremental and incremental memristor emulators. This situation is a disadvantage of the emulator besides its grounded structure. Each circuit comprises three CFOAs, four resistors, two capacitors, and germanium diode without using an analog multiplier. Nonlinear characteristic is provided by germanium diode. CFOA which is an active element is modeled by AD844 commercially available active devices, and experimental results have been investigated.

**Figure 16.** Voltage-controlled memristor emulator which is presented by Kim and co-workers [38].

Sánchez-López and Aguila-Cuapio proposed the charge-controlled memristor emulator circuit [40]. This circuit which is shown in **Figure 18** is grounded; hence, application areas of the presented memristor emulator are limited in circuit designs. Moreover, it is implemented with discrete circuit element such as AD844 and AD633 besides its disadvantages.

can be adjusted by biasing current of the OTA. The change of the memristance value can be controlled by changing resistor (R) value. Average memristance value can be controlled using OTA-gm value because of the fact that OTA is used as controllable resistor by connecting the negative output terminal to the positive input terminal. In order to demonstrate the performance of OTA-based memristor emulator, both SPICE simulation results and experimental results have been performed. For experimental results, the memristor emulator is built using passive elements and commercially available active devices such as OPA860 for MO-OTA and

+Vdd +Vdd

Z X2

W X1

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Y3

Emulator Circuits and Resistive Switching Parameters of Memristor

Y4



Yesil and co-workers suggested only one DDCC-based memristor emulator which can be operated in high-frequency regions [42]. It is observed from **Figure 20** that the capacitor provides the memory effect and the multiplication of both capacitor and resistor voltages is connected to the Y terminal of the active device. The resistance of memristor emulator circuit decreases when the Z terminal of the DDCC device is chosen as positive terminal (ZP). Consequently, the circuit shows decremental memristor characteristics. For another state, an

R C

VR

P

VP

ZP ZN

ZP,N ZP

**MO-OTA**

**Figure 19.** OT-based memristor emulator which is presented by Babacan and co-workers [41].

VC VN

N

AD633 for the analog multiplier.

IIN VIN

Vm(t)

**Figure 18.** Memristor emulator based on AD844 [40].

Y

Z

W

Ca C1 R1 Rx Rz Rb

X

Babacan and co-workers presented new memristor emulator based on multi-output operational transconductance amplifier (OTA) [41]. This emulator shown in **Figure 19** is a derivative of the DDCC-based memristor emulator [42], but memristance value of this emulator

**Figure 17.** CFOA-based memristor emulator with (a) decremental and (b) incremental characteristic [39].

**Figure 18.** Memristor emulator based on AD844 [40].

Sánchez-López and Aguila-Cuapio proposed the charge-controlled memristor emulator circuit [40]. This circuit which is shown in **Figure 18** is grounded; hence, application areas of the presented memristor emulator are limited in circuit designs. Moreover, it is implemented

Babacan and co-workers presented new memristor emulator based on multi-output operational transconductance amplifier (OTA) [41]. This emulator shown in **Figure 19** is a derivative of the DDCC-based memristor emulator [42], but memristance value of this emulator

with discrete circuit element such as AD844 and AD633 besides its disadvantages.

**Figure 16.** Voltage-controlled memristor emulator which is presented by Kim and co-workers [38].

w

<sup>x</sup> <sup>z</sup> <sup>y</sup>

**(a)**

CFOA2 CFOA3

**(b)** 

**Figure 17.** CFOA-based memristor emulator with (a) decremental and (b) incremental characteristic [39].

<sup>x</sup> <sup>z</sup> <sup>w</sup> <sup>y</sup>

CFOA2 CFOA3

w <sup>x</sup> <sup>z</sup>

w <sup>x</sup> <sup>z</sup>

y

52 Memristor and Memristive Neural Networks

y

w <sup>x</sup> <sup>z</sup> <sup>y</sup>

Vm

CFOA1

w <sup>x</sup> <sup>z</sup> <sup>y</sup>

Vm

CFOA1

can be adjusted by biasing current of the OTA. The change of the memristance value can be controlled by changing resistor (R) value. Average memristance value can be controlled using OTA-gm value because of the fact that OTA is used as controllable resistor by connecting the negative output terminal to the positive input terminal. In order to demonstrate the performance of OTA-based memristor emulator, both SPICE simulation results and experimental results have been performed. For experimental results, the memristor emulator is built using passive elements and commercially available active devices such as OPA860 for MO-OTA and AD633 for the analog multiplier.

Yesil and co-workers suggested only one DDCC-based memristor emulator which can be operated in high-frequency regions [42]. It is observed from **Figure 20** that the capacitor provides the memory effect and the multiplication of both capacitor and resistor voltages is connected to the Y terminal of the active device. The resistance of memristor emulator circuit decreases when the Z terminal of the DDCC device is chosen as positive terminal (ZP). Consequently, the circuit shows decremental memristor characteristics. For another state, an

**Figure 19.** OT-based memristor emulator which is presented by Babacan and co-workers [41].

**Figure 20.** DDCC-based memristor emulator which is presented by Yesil and co-workers [42].

incremental memristor can be obtained when the Z terminal of DDCC is chosen as negative terminal (ZN). This emulator consists of the third terminal (Vsum) to provide the floating characteristic. Serial connected memristors split applied voltage such as resistor if these memristors carry out a voltage; accordingly, the third terminal is connected to the output terminal. Just as DDCC-based [35], CBTA-based [36], and adder-and-subtractor [37]-based memristor, the performance of [42] is confirmed by SPICE simulations results.

Babacan and Kacar suggested new memristor emulator which does not need any multiplication block as shown in **Figure 23** [45]. This emulator is also fully floating, namely, has two terminals, and input signal can be applied in both terminals. The nonlinearity is provided by transistors which are operated in the subthreshold region. The presented memristor emulator includes single-ended OTA, one grounded capacitor, and two PMOS transistors. Note that the bulk terminals of PMOS transistors are connected to drain terminals of relevant

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The first memristor model which accounts for spike-timing-dependent plasticity (STDP) mechanism is proposed by Li and co-workers [46]. The model which is shown in **Figure 24** consists of five circuit models, and each model depends on the previous model so this model

Babacan and Kacar suggested real-time fully floating memristor emulator which is accounted for synaptic activity [47]. Both memristive and STDP characteristics are obtained from the

is complex and does not have any circuit implementation.

**Figure 23.** Fully floating memristor emulator based on OTA [45].

**Figure 22.** Floating flux-controlled memristor emulator based on CCII [44].

transistors.

Sozen and Cam proposed new floating memristor emulator based on OTA and CCII as shown in **Figure 21** [43]. This emulator is made up of three OTAs, four CCIIs, and seven passive elements. Both SPICE simulation results and experimental results of the presented memristor emulator have been given to confirm its workableness and feasibility. Commercially available active devices CA3080 and AD844 have been utilized instead of OTA and CCII, respectively.

Sánchez-López et al. proposed second-generation current conveyor (CCII)-based flux-controlled memristor emulator which is shown in **Figure 22** [44]. The presented emulator comprises of four CCIIs, a multiplier circuit, five resistors, and single grounded capacitor. AD844 and AD633 are used instead of CCII and analog multiplier in the flux-controlled memristor emulator, respectively. So as to indicate the performance of flux-controlled memristor emulator, both SPICE simulation results and experimental results have been exhibited.

**Figure 21.** OTA- and CCII-based memristor emulator [43].

Emulator Circuits and Resistive Switching Parameters of Memristor http://dx.doi.org/10.5772/intechopen.71903 55

**Figure 22.** Floating flux-controlled memristor emulator based on CCII [44].

incremental memristor can be obtained when the Z terminal of DDCC is chosen as negative terminal (ZN). This emulator consists of the third terminal (Vsum) to provide the floating characteristic. Serial connected memristors split applied voltage such as resistor if these memristors carry out a voltage; accordingly, the third terminal is connected to the output terminal. Just as DDCC-based [35], CBTA-based [36], and adder-and-subtractor [37]-based memristor,

**VR**

**OUTPUT**

**CT RT**

**VC**

Sozen and Cam proposed new floating memristor emulator based on OTA and CCII as shown in **Figure 21** [43]. This emulator is made up of three OTAs, four CCIIs, and seven passive elements. Both SPICE simulation results and experimental results of the presented memristor emulator have been given to confirm its workableness and feasibility. Commercially available active devices CA3080 and AD844 have been utilized instead of OTA and CCII, respectively. Sánchez-López et al. proposed second-generation current conveyor (CCII)-based flux-controlled memristor emulator which is shown in **Figure 22** [44]. The presented emulator comprises of four CCIIs, a multiplier circuit, five resistors, and single grounded capacitor. AD844 and AD633 are used instead of CCII and analog multiplier in the flux-controlled memristor emulator, respectively. So as to indicate the performance of flux-controlled memristor emula-

tor, both SPICE simulation results and experimental results have been exhibited.

the performance of [42] is confirmed by SPICE simulations results.

**VINPUT**

**Figure 21.** OTA- and CCII-based memristor emulator [43].

**Vsum**

54 Memristor and Memristive Neural Networks

**INPUT**

**RS IINPUT**

**X**

**Figure 20.** DDCC-based memristor emulator which is presented by Yesil and co-workers [42].

**Y3 Y2**

**ZN1 ZP,N**

**DDCC**

**<sup>Y</sup> ZN2 <sup>1</sup>**

Babacan and Kacar suggested new memristor emulator which does not need any multiplication block as shown in **Figure 23** [45]. This emulator is also fully floating, namely, has two terminals, and input signal can be applied in both terminals. The nonlinearity is provided by transistors which are operated in the subthreshold region. The presented memristor emulator includes single-ended OTA, one grounded capacitor, and two PMOS transistors. Note that the bulk terminals of PMOS transistors are connected to drain terminals of relevant transistors.

The first memristor model which accounts for spike-timing-dependent plasticity (STDP) mechanism is proposed by Li and co-workers [46]. The model which is shown in **Figure 24** consists of five circuit models, and each model depends on the previous model so this model is complex and does not have any circuit implementation.

Babacan and Kacar suggested real-time fully floating memristor emulator which is accounted for synaptic activity [47]. Both memristive and STDP characteristics are obtained from the

**Figure 23.** Fully floating memristor emulator based on OTA [45].

**Figure 24.** Memristor model which is accounted for STDP mechanism [46].

circuit which is shown in **Figure 25**. It is observed from **Figure 25** that fully floating memristor emulator consists of a few numbers of MOS transistors and capacitors without using analog multiplier. Furthermore, STDP is experimentally demonstrated in memristive devices [48–50].

In summary, the comparison of the memristor emulator circuits is according to some important design parameters such as used circuit elements, electronically controllability, power supply value, etc. Each emulator has superior properties among the other emulators. Researchers can prefer appropriate emulator circuit for their memristor-based circuit designs (**Table 3**).

**4. Conclusion**

**Reference No. of** 

**floating passive elements**

[35] *—* 10 DDCCs, 8

[37] 1 L, 1 C 1 adder and 1

[38] 1 R 2 OPAMPs, 1

[40] 1 R 1 CCII(AD844), 1

[44] 2 R 4 CCIIs (AD844), 1

**Table 3.** Comparison of memristor emulator circuits.

[41] *— 1 MO-OTA, 1* 

transistors

subtractor

multiplier, 10 transistors

multiplier (AD633)

multiplier (AD633)

*multiplier*

**No. of active comp No. of** 

**grounded passive elements**

[36] 1 R 1 CBTA, 1 multiplier 1 R, 1 C Sim. No Grounded ±0.9 V

[39] 2 R, 1 D 3 CFOAs (AD844) 2 R, 2 C Exp. No Grounded NA

[42] 1 R 1 DDCC, 1 multiplier 1 R, 1 C Sim. No Floating ±1.5 [43] 3 R 3 OTAs, 4 CCIIs 3 R, 1 C Both *Yes* Floating ±15

[45] — 1 OTA, 2 transistors 1 C Sim. No Floating ±1 V [47] — 10 transistors 3 C Sim. No Floating —

**Sim./exp Electronically controllable**

4 R, 1 C Sim. No Grounded ±1.25 V

1 D Sim. No Grounded ±1.25 V

1 C Both No Grounded ±10 V

3 R, 1 C Both No Floating ±10 V

*1 R, 1 C* Both *Yes* Grounded *±1.25 V/±5 V*

1 R, 1 C Both No Grounded/

**Floating/ grounded memristor emulator**

http://dx.doi.org/10.5772/intechopen.71903

Emulator Circuits and Resistive Switching Parameters of Memristor

floating

**Power supply**

57

±5 V

ing-dependent plasticity mechanism.

In this chapter, memristor devices, models, and emulators have been referred. Memristors have nonlinear characteristics; therefore, high-order mathematical equations should be used to create a mathematical model of the memristor. Active circuit elements are essential to build memristor emulators because of the fact that active elements are versatile and suitable for nonlinear circuit element designs. Nowadays, memristors can exhibit different characteristics when they are fabricated using various materials. Important characteristics such as switching mechanism, synaptic behavior, and operating frequency region are directly depending on the memristor structure. Hence, there is an essential to implement various models and circuits to emulate real memristors. Some emulator circuits exhibit hard-switching characteristics, other emulators exhibit smooth-switching characteristics, or some emulators account for spike-tim-

As a result, researchers are not able to reach real memristor easily so all emulator models and circuits are important to exhibit real memristors. Memristors are ultradense devices

**Figure 25.** Memristor circuit which is accounted for STDP mechanism [47].


**Table 3.** Comparison of memristor emulator circuits.

## **4. Conclusion**

circuit which is shown in **Figure 25**. It is observed from **Figure 25** that fully floating memristor emulator consists of a few numbers of MOS transistors and capacitors without using analog multiplier. Furthermore, STDP is experimentally demonstrated in memristive

**Figure 24.** Memristor model which is accounted for STDP mechanism [46].

**VA1**

T1

T2

**Vtau Cpot**

T3

**Cdep Vtau**

**Figure 25.** Memristor circuit which is accounted for STDP mechanism [47].

T6

**VA2**

T4

T5

In summary, the comparison of the memristor emulator circuits is according to some important design parameters such as used circuit elements, electronically controllability, power supply value, etc. Each emulator has superior properties among the other emulators. Researchers can prefer appropriate emulator circuit for their memristor-based circuit designs (**Table 3**).

T7

**VDD** 

TA

TB

**CA**

T8

devices [48–50].

56 Memristor and Memristive Neural Networks

In this chapter, memristor devices, models, and emulators have been referred. Memristors have nonlinear characteristics; therefore, high-order mathematical equations should be used to create a mathematical model of the memristor. Active circuit elements are essential to build memristor emulators because of the fact that active elements are versatile and suitable for nonlinear circuit element designs. Nowadays, memristors can exhibit different characteristics when they are fabricated using various materials. Important characteristics such as switching mechanism, synaptic behavior, and operating frequency region are directly depending on the memristor structure. Hence, there is an essential to implement various models and circuits to emulate real memristors. Some emulator circuits exhibit hard-switching characteristics, other emulators exhibit smooth-switching characteristics, or some emulators account for spike-timing-dependent plasticity mechanism.

As a result, researchers are not able to reach real memristor easily so all emulator models and circuits are important to exhibit real memristors. Memristors are ultradense devices and consume very low energy; that is why it is not only important to emulate real emulator. Researchers need also emulator circuits which have minimum energy consumption and simple structure.

[10] Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: Threshold adaptive memristor model. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;**60**:211-

Emulator Circuits and Resistive Switching Parameters of Memristor

http://dx.doi.org/10.5772/intechopen.71903

59

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## **Author details**

Abdullah Yesil<sup>1</sup> , Fatih Gül2 and Yunus Babacan<sup>3</sup> \*

\*Address all correspondence to: yunusbabacan@gmail.com

1 Department of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul University, Balikesir, Turkey

2 Department of Software Engineering, Gumushane University, Gumushane, Turkey

3 Department of Electrical and Electronic Engineering, Erzincan University, Erzincan, Turkey

## **References**


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and consume very low energy; that is why it is not only important to emulate real emulator. Researchers need also emulator circuits which have minimum energy consumption and sim-

\*

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1 Department of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul

2 Department of Software Engineering, Gumushane University, Gumushane, Turkey 3 Department of Electrical and Electronic Engineering, Erzincan University, Erzincan,

and Yunus Babacan<sup>3</sup>

\*Address all correspondence to: yunusbabacan@gmail.com

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**Chapter 4**

**Provisional chapter**

**Nanoscale Switching and Degradation of Resistive**

**Random Access Memory Studied by** *In Situ* **Electron** 

**Nanoscale Switching and Degradation of Resistive** 

DOI: 10.5772/intechopen.69024

**Random Access Memory Studied by** *In Situ* **Electron**

The metal-filament-type resistive random access memories (ReRAMs) with copper were investigated from the point of view of dynamical microstructure evolution in the repetitive switching operations using *in situ* transmission electron microscopy (*in situ* TEM). Through a series of experiments for uncovered solid electrolyte films, stacked devices, and nanofabricated cells, formation and erasure of the copper filaments and deposits were confirmed. The behavior of the filament and deposit depended on the switching condition and history. Based on these *in situ* TEM results, the switching schematics and

**Keywords:** *in situ* transmission electron microscopy, resistive random access memory, ReRAM, conductive bridge random access memory, CBRAM, memristor, conductive

The resistive random access memory (ReRAM) has great potential as a candidate of the nextgeneration nonvolatile memory because of the high-speed operation, the wide memory window, and the high-density storage per cost [1]. In addition, its capability of the multilevel or analogue memory control and its hysteretic nonlinear current-to-voltage (*I–V*) characteristics are suitable for the operation of the artificial neural network hardware using memristors, and this research field is very active especially in these years [2–5]. Because of these advantageous properties, vast numbers of works on ReRAMs have been reported as described in numerous review

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

Masashi Arita, Atsushi Tsurumaki-Fukuchi and

Masashi Arita, Atsushi Tsurumaki-Fukuchi

Additional information is available at the end of the chapter

the degradation process were discussed.

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69024

**Microscopy**

**Microscopy**

Yasuo Takahashi

**Abstract**

filament

**1. Introduction**

and Yasuo Takahashi

**Provisional chapter**

## **Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by** *In Situ* **Electron Microscopy Random Access Memory Studied by** *In Situ* **Electron Microscopy**

**Nanoscale Switching and Degradation of Resistive** 

DOI: 10.5772/intechopen.69024

Masashi Arita, Atsushi Tsurumaki-Fukuchi and Yasuo Takahashi and Yasuo Takahashi Additional information is available at the end of the chapter

Masashi Arita, Atsushi Tsurumaki-Fukuchi

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69024

#### **Abstract**

The metal-filament-type resistive random access memories (ReRAMs) with copper were investigated from the point of view of dynamical microstructure evolution in the repetitive switching operations using *in situ* transmission electron microscopy (*in situ* TEM). Through a series of experiments for uncovered solid electrolyte films, stacked devices, and nanofabricated cells, formation and erasure of the copper filaments and deposits were confirmed. The behavior of the filament and deposit depended on the switching condition and history. Based on these *in situ* TEM results, the switching schematics and the degradation process were discussed.

**Keywords:** *in situ* transmission electron microscopy, resistive random access memory, ReRAM, conductive bridge random access memory, CBRAM, memristor, conductive filament

## **1. Introduction**

The resistive random access memory (ReRAM) has great potential as a candidate of the nextgeneration nonvolatile memory because of the high-speed operation, the wide memory window, and the high-density storage per cost [1]. In addition, its capability of the multilevel or analogue memory control and its hysteretic nonlinear current-to-voltage (*I–V*) characteristics are suitable for the operation of the artificial neural network hardware using memristors, and this research field is very active especially in these years [2–5]. Because of these advantageous properties, vast numbers of works on ReRAMs have been reported as described in numerous review

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

articles [6–14]. In these years, highly integrated memory chips have been reported [15–17], and a 16 Gbits chip with 180 MB/s write and 900 MB/s read performance fabricated at the 27 nm node has already been demonstrated using the Cu-based ReRAM [18]. Commercialized or nearly commercialized ReRAM chips have also been reported [19–21]. However, there are still ambiguous issues of the switching and device degradation mechanisms, while basic principles of the ReRAM operations have been discussed using the electrochemistry of solid materials.

To overcome this problem, *in situ* transmission electron microscopy (*in situ* TEM) has been applied on a variety of ReRAMs [12, 14, 23, 24] including CBRAMs [25–29] and other families [30–37], which enable real space observations during ReRAM switching. In some examples, formation and erasure of a Cu or Ag filament were confirmed at quick switching of CBRAM [25, 27]. In another report, the filament growth scheme was categorized in terms of its dependence on the cation mobility and the reduction rate [38]. Comprehension of the filament formation has been much advanced with the sake of *in situ* TEM. On the other hand, *in situ* TEM works on RESET and the multiple operations are still rare, although they are quite important

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

http://dx.doi.org/10.5772/intechopen.69024

65

For filling the lack of this knowledge, we have performed *in situ* TEM of SET/RESET and/or multiple switching cycles for an uncovered solid electrolyte, stacked CBRAMs, and nanofabricated CBRAM cells. In this contribution, we will review our work in these years [25, 29, 39–44] and discuss the role of the filament at SET/RESET, the filament growth/erasure mode influenced by the switching history, the CBRAM degradation, and the localization of the fila-

A schematic diagram of the *in situ* TEM system is shown in **Figure 2(a)**. The TEM (10−5 Pa) was equipped with a home-made TEM piezoholder, a piezocontrol system, a current measurement unit, and a CCD camera system (30 frames/s) [45]. The Pt-Ir electrode set in the TEM holder is movable to select the location of the fixed ReRAM sample to be measured (**Figure 2(b)**). The TEM experiments were performed with the beam current density much

The *I–V* measurements were carried out using a source measure unit (SMU). The sweeping rate was typically between 0.3 and 1.6 V/s. The pulse switching operation (pulse width of

**Figure 2.** Schematics of (a) the *in situ* TEM system and (b) the geometry of the sample and the probe.

(typical current density for our high-resolution TEM observations).

for development of reliable ReRAM devices.

**2. Experimental procedure of** *in situ* **TEM**

ment to achieve stable switching.

less than the 170 fA/nm<sup>2</sup>

The ReRAM operation is performed by simply applying voltage to the device having a capacitor structure with a switching layer between the top and bottom electrodes (TE and BE) as shown in **Figure 1(a)**. The initial state of the device is typically the high-resistance state (HRS). It converts into the low-resistance state (LRS) by applying voltage (SET or "Forming" for the first SET). Subsequent voltage returns the resistance to HRS (RESET) as shown in **Figure 1(b)**. The *I–V* curves are hysteretic with the resistance ratio HRS/LRS typically 10<sup>2</sup> or larger (**Figure 1(c)**). The operation is called "bipolar" when the voltage polarity for SET and RESET should be reversed, while it is "unipolar" without polarity change. The ReRAM families energetically investigated have been the valence change memory (VCM) composed of a thin oxide layer between two noble electrodes, and the conductive bridging RAM (CBRAM; there are also other naming) composed of a solid electrolyte with an electrochemically active electrode (Cu or Ag) and an inactive electrode (Pt or TiN). In this report, we study some CBRAMs showing the bipolar switching as shown in **Figure 1(b)**.

The CBRAM operation has been explained based on electrical measurements and electronic and electrochemical discussions [8, 10, 14, 22]. Assuming that the TE is Cu, positive voltage to the TE generates Cu cations through oxidation of the electrode at the interface with the solid electrolyte. These cations move along the electric field and are metallized after receiving electrons at the BE interface. A Cu filament is formed there and grows toward the TE. When this filament connects two electrodes, SET switching is completed. Voltage reversal induces the opposite reaction, and the filament is ruptured (RESET). This simple model based on the results of the electrical measurements is plausible, which is an analogical model of electroplating. However, the switching details like filament evolution at SET/RESET and the behavior of the filament during device degradation are hard to be accomplished only with electrical measurements, which are important for usage of ReRAM with guaranteed reliability as the actual electronic device in the circuit.

**Figure 1.** (a) Schematic structure of ReRAM, and typical experimental data of (b) an *I–V* switching curve and (c) a cyclic endurance graph of Cu/WOx /TiN CBRAM cells.

To overcome this problem, *in situ* transmission electron microscopy (*in situ* TEM) has been applied on a variety of ReRAMs [12, 14, 23, 24] including CBRAMs [25–29] and other families [30–37], which enable real space observations during ReRAM switching. In some examples, formation and erasure of a Cu or Ag filament were confirmed at quick switching of CBRAM [25, 27]. In another report, the filament growth scheme was categorized in terms of its dependence on the cation mobility and the reduction rate [38]. Comprehension of the filament formation has been much advanced with the sake of *in situ* TEM. On the other hand, *in situ* TEM works on RESET and the multiple operations are still rare, although they are quite important for development of reliable ReRAM devices.

For filling the lack of this knowledge, we have performed *in situ* TEM of SET/RESET and/or multiple switching cycles for an uncovered solid electrolyte, stacked CBRAMs, and nanofabricated CBRAM cells. In this contribution, we will review our work in these years [25, 29, 39–44] and discuss the role of the filament at SET/RESET, the filament growth/erasure mode influenced by the switching history, the CBRAM degradation, and the localization of the filament to achieve stable switching.

## **2. Experimental procedure of** *in situ* **TEM**

articles [6–14]. In these years, highly integrated memory chips have been reported [15–17], and a 16 Gbits chip with 180 MB/s write and 900 MB/s read performance fabricated at the 27 nm node has already been demonstrated using the Cu-based ReRAM [18]. Commercialized or nearly commercialized ReRAM chips have also been reported [19–21]. However, there are still ambiguous issues of the switching and device degradation mechanisms, while basic principles of the

The ReRAM operation is performed by simply applying voltage to the device having a capacitor structure with a switching layer between the top and bottom electrodes (TE and BE) as shown in **Figure 1(a)**. The initial state of the device is typically the high-resistance state (HRS). It converts into the low-resistance state (LRS) by applying voltage (SET or "Forming" for the first SET). Subsequent voltage returns the resistance to HRS (RESET) as shown in **Figure 1(b)**.

(**Figure 1(c)**). The operation is called "bipolar" when the voltage polarity for SET and RESET should be reversed, while it is "unipolar" without polarity change. The ReRAM families energetically investigated have been the valence change memory (VCM) composed of a thin oxide layer between two noble electrodes, and the conductive bridging RAM (CBRAM; there are also other naming) composed of a solid electrolyte with an electrochemically active electrode (Cu or Ag) and an inactive electrode (Pt or TiN). In this report, we study some CBRAMs show-

The CBRAM operation has been explained based on electrical measurements and electronic and electrochemical discussions [8, 10, 14, 22]. Assuming that the TE is Cu, positive voltage to the TE generates Cu cations through oxidation of the electrode at the interface with the solid electrolyte. These cations move along the electric field and are metallized after receiving electrons at the BE interface. A Cu filament is formed there and grows toward the TE. When this filament connects two electrodes, SET switching is completed. Voltage reversal induces the opposite reaction, and the filament is ruptured (RESET). This simple model based on the results of the electrical measurements is plausible, which is an analogical model of electroplating. However, the switching details like filament evolution at SET/RESET and the behavior of the filament during device degradation are hard to be accomplished only with electrical measurements, which are important for usage of ReRAM with guaranteed reliability as the

**Figure 1.** (a) Schematic structure of ReRAM, and typical experimental data of (b) an *I–V* switching curve and (c) a cyclic

/TiN CBRAM cells.

or larger

ReRAM operations have been discussed using the electrochemistry of solid materials.

The *I–V* curves are hysteretic with the resistance ratio HRS/LRS typically 10<sup>2</sup>

ing the bipolar switching as shown in **Figure 1(b)**.

64 Memristor and Memristive Neural Networks

actual electronic device in the circuit.

endurance graph of Cu/WOx

A schematic diagram of the *in situ* TEM system is shown in **Figure 2(a)**. The TEM (10−5 Pa) was equipped with a home-made TEM piezoholder, a piezocontrol system, a current measurement unit, and a CCD camera system (30 frames/s) [45]. The Pt-Ir electrode set in the TEM holder is movable to select the location of the fixed ReRAM sample to be measured (**Figure 2(b)**). The TEM experiments were performed with the beam current density much less than the 170 fA/nm<sup>2</sup> (typical current density for our high-resolution TEM observations).

The *I–V* measurements were carried out using a source measure unit (SMU). The sweeping rate was typically between 0.3 and 1.6 V/s. The pulse switching operation (pulse width of

**Figure 2.** Schematics of (a) the *in situ* TEM system and (b) the geometry of the sample and the probe.

100–500 μs) was occasionally performed. The measurements were done with current compliance of SMU to prevent sample destruction. However, this current compliance was occasionally insufficient because of the parasitic capacitance of the system. In some cases, a MOSFET was installed in the piezoholder to control the compliance current (*I* comp) strictly. To investigate the microstructural change, the TEM images were recorded simultaneously with the current measurements by using a charge coupled device (CCD) video camera. The video contrast was occasionally enhanced nonlinearly to enable a clear identification of the faint contrast. Frame averaging was also used to reduce the noise.

## **3. Filament formation and erasure in chalcogenide containing Cu**

Filament formation and erasure will be demonstrated using GeS containing copper (Cu:GeS) [25, 39]. Though the switching speed and the retention property were not good enough for actual devices, this material is good for easy investigation of the filament evolution. The Cu:GeS thin film was sputter deposited at room temperature (RT) on a wedge-shaped Pt-Ir substrate that acted as the electrode. The film was 8–60 nm thick and was amorphous including Ge nanocrystals. A sharp Pt-Ir probe (the counterelectrode) contacted the Cu:GeS layer, and the *I–V* measurements were performed. The probe was grounded, and the substrate was biased. In this sample, the Cu ion source was Cu:GeS itself. The atomic composition estimated using EDX was Cu:Ge:S = 4:4:2. Though the PtIr/Cu:GeS/PtIr structure was electrochemically symmetric, it showed the asymmetric ReRAM switching (i.e., bipolar switching) because of the shape difference between the substrate and the probe.

properties of the electrodes but to the asymmetry of the electric field caused by the shape difference of the electrodes. Because of the concentrated electric field, Cu ions accumulate at the probe when the substrate is positive. On the other hand, electric flux disperses toward the substrate when the polarity is reversed. Even though Cu is thought to accumulate at the substrate-

**Figure 3.** The switching curve (left panel) and TEM images extracted from a video (right panel) of a Cu:GeS film. The

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

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67

Selected area diffractometry (SAD) and energy dispersive X-ray spectroscopy (EDX) were performed in real time during the operation (but other area than **Figure 3**). In this subsection, the results are briefly summarized. Detailed experimental data are seen in Refs.

The crystal structure of the filament was studied using *in situ* SAD. When a deposit was formed, sharp spots appeared in the patterns. They twinkled like stars. This indicates that nanocrystals were formed, and their orientation frequently changed during the voltage scan. The 1152 frames of the SAD video (35 s) were summed, and Debye rings were identified. The estimated *d*-values were those of Cu reflections. For the elemental analysis, the EDX of the filament was performed with voltage application (+1 V). The Cu peak was greatly enhanced relative to the initial state. The composition estimated using the thin foil approximation was Cu:Ge:S = 7:2:1, while the region containing no filaments showed 4:4:2. The filament was an agglomeration of nanocrystals with a relatively large amount of Cu; probably metallic Cu or

film interface, its density is low for filament formation.

images (a)–(i) correspond to the states marked in the switching curve.

**3.2. SAD and EDX of the conductive filament**

its alloy with either Ge and/or S.

[25, 39].

#### **3.1.** *In situ* **SET and RESET operation**

The *I–V* curve is plotted in the left panel of **Figure 3**, where the current compliance was *I*comp = 500 nA. Clear hysteretic curve was seen as investigated in other studies of solid electrolytes [6, 10, 46, 47]. TEM video images are presented in the right panel of **Figure 3** where each image corresponds to the states (a)–(i) marked in the *I–V* graph. There was no special contrast just before the voltage sweep started (**Figure 3(a)**). The current gradually increased until about 2.5 V, and a deposit-like dark contrast grew from the probe (cathode with this voltage polarity) (**Figure 3(b)–(c)**). Afterward, the current quickly reached *I*comp. This is SET giving LRS. Correspondingly, the deposit was enlarged (**Figure 3(d)–(e)**) and contacted the substrate. In RESET with negative biasing of the substrate, there were sudden jumps at −0.5 and −2 V, which are abnormal with the usual bipolar switching. This is special for the sample without the Cu electrode (thus, amount of Cu is limited) and was neither conventional SET nor RESET [8, 10, 14, 22]. In **Figure 3(f)–(g)**, the deposit was contracted with negative voltage from the substrate (cathode) to the probe (anode). The deposit detached from the substrate in **Figure 3(h)**, and the resistance returned to HRS. This was the RESET switching. At the end of this cycle, the image reverted almost to that of the original (**Figure 3(i)**).

The deposit size and the current corresponded; therefore, this deposit is expected to act as the conductive filament. The polarity dependence may be attributed not to the electrochemical

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*... http://dx.doi.org/10.5772/intechopen.69024 67

**Figure 3.** The switching curve (left panel) and TEM images extracted from a video (right panel) of a Cu:GeS film. The images (a)–(i) correspond to the states marked in the switching curve.

properties of the electrodes but to the asymmetry of the electric field caused by the shape difference of the electrodes. Because of the concentrated electric field, Cu ions accumulate at the probe when the substrate is positive. On the other hand, electric flux disperses toward the substrate when the polarity is reversed. Even though Cu is thought to accumulate at the substratefilm interface, its density is low for filament formation.

#### **3.2. SAD and EDX of the conductive filament**

100–500 μs) was occasionally performed. The measurements were done with current compliance of SMU to prevent sample destruction. However, this current compliance was occasionally insufficient because of the parasitic capacitance of the system. In some cases, a MOSFET

the microstructural change, the TEM images were recorded simultaneously with the current measurements by using a charge coupled device (CCD) video camera. The video contrast was occasionally enhanced nonlinearly to enable a clear identification of the faint contrast. Frame

Filament formation and erasure will be demonstrated using GeS containing copper (Cu:GeS) [25, 39]. Though the switching speed and the retention property were not good enough for actual devices, this material is good for easy investigation of the filament evolution. The Cu:GeS thin film was sputter deposited at room temperature (RT) on a wedge-shaped Pt-Ir substrate that acted as the electrode. The film was 8–60 nm thick and was amorphous including Ge nanocrystals. A sharp Pt-Ir probe (the counterelectrode) contacted the Cu:GeS layer, and the *I–V* measurements were performed. The probe was grounded, and the substrate was biased. In this sample, the Cu ion source was Cu:GeS itself. The atomic composition estimated using EDX was Cu:Ge:S = 4:4:2. Though the PtIr/Cu:GeS/PtIr structure was electrochemically symmetric, it showed the asymmetric ReRAM switching (i.e., bipolar switching) because of

The *I–V* curve is plotted in the left panel of **Figure 3**, where the current compliance was *I*comp = 500 nA. Clear hysteretic curve was seen as investigated in other studies of solid electrolytes [6, 10, 46, 47]. TEM video images are presented in the right panel of **Figure 3** where each image corresponds to the states (a)–(i) marked in the *I–V* graph. There was no special contrast just before the voltage sweep started (**Figure 3(a)**). The current gradually increased until about 2.5 V, and a deposit-like dark contrast grew from the probe (cathode with this voltage polarity) (**Figure 3(b)–(c)**). Afterward, the current quickly reached *I*comp. This is SET giving LRS. Correspondingly, the deposit was enlarged (**Figure 3(d)–(e)**) and contacted the substrate. In RESET with negative biasing of the substrate, there were sudden jumps at −0.5 and −2 V, which are abnormal with the usual bipolar switching. This is special for the sample without the Cu electrode (thus, amount of Cu is limited) and was neither conventional SET nor RESET [8, 10, 14, 22]. In **Figure 3(f)–(g)**, the deposit was contracted with negative voltage from the substrate (cathode) to the probe (anode). The deposit detached from the substrate in **Figure 3(h)**, and the resistance returned to HRS. This was the RESET switching. At the end of this cycle, the image reverted almost to that

The deposit size and the current corresponded; therefore, this deposit is expected to act as the conductive filament. The polarity dependence may be attributed not to the electrochemical

**3. Filament formation and erasure in chalcogenide containing Cu**

comp) strictly. To investigate

was installed in the piezoholder to control the compliance current (*I*

the shape difference between the substrate and the probe.

**3.1.** *In situ* **SET and RESET operation**

of the original (**Figure 3(i)**).

averaging was also used to reduce the noise.

66 Memristor and Memristive Neural Networks

Selected area diffractometry (SAD) and energy dispersive X-ray spectroscopy (EDX) were performed in real time during the operation (but other area than **Figure 3**). In this subsection, the results are briefly summarized. Detailed experimental data are seen in Refs. [25, 39].

The crystal structure of the filament was studied using *in situ* SAD. When a deposit was formed, sharp spots appeared in the patterns. They twinkled like stars. This indicates that nanocrystals were formed, and their orientation frequently changed during the voltage scan. The 1152 frames of the SAD video (35 s) were summed, and Debye rings were identified. The estimated *d*-values were those of Cu reflections. For the elemental analysis, the EDX of the filament was performed with voltage application (+1 V). The Cu peak was greatly enhanced relative to the initial state. The composition estimated using the thin foil approximation was Cu:Ge:S = 7:2:1, while the region containing no filaments showed 4:4:2. The filament was an agglomeration of nanocrystals with a relatively large amount of Cu; probably metallic Cu or its alloy with either Ge and/or S.

#### **3.3. Decrease of the SET voltage and the residue of the filament**

The SET voltage usually goes down after forming. This was considered to be caused by the wreckage of the filament [8, 10, 14, 22]. To understand this phenomenon, we performed three continuous SET cycles from the initial state. Because of a short retention of this sample, the deposit disappeared automatically without negative voltage. Thus, only the positive cycles were investigated. The SET voltage in the 1st, 2nd, and 3rd cycles decreased from 2.25 to 1.83 V (2nd) and 1.50 V (3rd). In this experiment, the probe position was changed as seen in **Figure 4**, where the arrows indicate the point where the probe hit in the 1st cycle. A filament appeared and disappeared at the probe in the 1st cycle (**Figure 4(a1, a2)**). Afterward, the probe was shifted as seen in **Figure 4(b1)**. When positive voltage was applied, a filament appeared elongating into the region where the 1st filament was formed. In the 3rd cycle, measurement was conducted without changing the probe position from the 2nd cycle (**Figure 4(c1)**). A filament was formed at the same place (**Figure 4 (c2)**). The region where the filament has been formed has priority in subsequent switching. Residuals of the filament should remain as extremely small metallic nanocrystals, which cannot easily be detected by SAD or conventional TEM. They are thought to act as nuclei of the filaments and to reduce the SET voltage.

**4. CBRAM having the stacked structure with the Cu electrode**

through repetitive ReRAM operations with increase of the switching current.

achieved for multilayered CBRAMs. In Sections 5 and 6, MoOx

LRS was limited by the serially connected resistance of TiN/Si.

**Figure 5.** (a) TEM image and (b) EDX mapping of a Pt/Cu/WOx

corresponded well to each other. (e) EDX spectra from the MoOx

*I–V* switching curve of (c) a TEM sample (size: 350 nm) and (d) a microdevice (size: 16 μm) of Pt/Cu/MoOx

filament (Reg-3). Enhancement of the Cu signal was clearly seen in Reg-3. Inset is the TEM image showing the analyzed

the O<sup>2</sup>

areas.

tive RF sputtering (Ar-20% O<sup>2</sup>

The special constitution of CBRAM was used in Section 3 for easy performance of experiments, such as a tip-shaped electrode and nonuse of Cu electrode. Operation was slow, and the current was much less than μA. This is satisfactory for a characterization of conductive filaments. However, to understand realistic operation, the multiple switching cycles should be

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

electrochemically active Cu and inactive TiN electrodes are demonstrated. The dynamics of filament growth/shrinkage (Section 5) and device degradation (Section 6) are discussed

The CBRAMs studied are Pt(100)/Cu(30)/MoOx(50) and Pt(100)/Cu(30)/WOx(20) on TiN/Si substrates, where the numbers denote the thicknesses in nm. Here, the TiN surface was oxidized due to

depositions were done at RT without any heat treatment, and both oxides were amorphous. Typical TEM image and EDX map are shown in **Figure 5(a) and (b)**. The layer structure is clearly identified, and the overall switching area is observable. Samples for *in situ* TEM were processed using the ion-shadow method [48], where many cone-shaped small devices were formed. The device diameter was less than 500 nm as shown in **Figure 5(a)**. The current for switching was measured between the biased Pt/Cu and grounded TiN/Si. The current in the

plasma treatment for cleaning. The oxide switching layers were prepared using reac-

and WOx

/TiN sample where clear layer stacking was seen. The

layer without the filament (Reg-1 and Reg-2) and the

/TiN. They

) of metal targets, while the others were by Ar RF sputtering. All

sandwiched between

69

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#### **3.4. Summary**

The fundamental behavior of the conductive filament in Cu:GeS was demonstrated by using *in situ* TEM, *in situ* SAD, and *in situ* EDX. The switching scheme is understood as follows.

When the substrate is positively biased, Cu ions in GeS move to the cathode (probe) and a metallic deposit appears there. It consists of Cu-based nanocrystals. The deposit expanded and finally touched the anode (substrate), and the resistance state is LRS. Even in this stage, the microstructure changes with voltage application. The deposit dissolves by polarity reversal, and it shrinks from the cathode (substrate) to the anode (probe). This process gives HRS. The formation/erasure of the deposit clearly corresponded to SET/RESET. Therefore, the conductive filament must be formed in the deposit. This behavior of the filament follows the electrochemical model [8, 10, 14, 22]. With the continuation of the switching cycle, the SET voltage decreased. This is caused by the residuals (probably Cu nanocrystals) that remain even in HRS. These residues are thought to act as nuclei of the filaments.

**Figure 4.** *In situ* TEM images of the (a) 1st, (b) 2nd, and (c) 3rd switching cycle of a Cu:GeS film. Images (a1), (b1), and (c1) are before the SET cycle, and those of (a2), (b2), and (c2) are after SET. The probe position was shifted between (a) and (b), while it was unchanged between (b) and (c). The arrow marks the potion where the probe was contacted in the 1st cycle.

## **4. CBRAM having the stacked structure with the Cu electrode**

**3.3. Decrease of the SET voltage and the residue of the filament**

68 Memristor and Memristive Neural Networks

**3.4. Summary**

The SET voltage usually goes down after forming. This was considered to be caused by the wreckage of the filament [8, 10, 14, 22]. To understand this phenomenon, we performed three continuous SET cycles from the initial state. Because of a short retention of this sample, the deposit disappeared automatically without negative voltage. Thus, only the positive cycles were investigated. The SET voltage in the 1st, 2nd, and 3rd cycles decreased from 2.25 to 1.83 V (2nd) and 1.50 V (3rd). In this experiment, the probe position was changed as seen in **Figure 4**, where the arrows indicate the point where the probe hit in the 1st cycle. A filament appeared and disappeared at the probe in the 1st cycle (**Figure 4(a1, a2)**). Afterward, the probe was shifted as seen in **Figure 4(b1)**. When positive voltage was applied, a filament appeared elongating into the region where the 1st filament was formed. In the 3rd cycle, measurement was conducted without changing the probe position from the 2nd cycle (**Figure 4(c1)**). A filament was formed at the same place (**Figure 4 (c2)**). The region where the filament has been formed has priority in subsequent switching. Residuals of the filament should remain as extremely small metallic nanocrystals, which cannot easily be detected by SAD or conventional TEM. They are thought to act as nuclei of the filaments and to reduce the SET voltage.

The fundamental behavior of the conductive filament in Cu:GeS was demonstrated by using *in situ* TEM, *in situ* SAD, and *in situ* EDX. The switching scheme is understood as follows.

When the substrate is positively biased, Cu ions in GeS move to the cathode (probe) and a metallic deposit appears there. It consists of Cu-based nanocrystals. The deposit expanded and finally touched the anode (substrate), and the resistance state is LRS. Even in this stage, the microstructure changes with voltage application. The deposit dissolves by polarity reversal, and it shrinks from the cathode (substrate) to the anode (probe). This process gives HRS. The formation/erasure of the deposit clearly corresponded to SET/RESET. Therefore, the conductive filament must be formed in the deposit. This behavior of the filament follows the electrochemical model [8, 10, 14, 22]. With the continuation of the switching cycle, the SET voltage decreased. This is caused by the residuals (probably Cu nanocrystals) that remain

**Figure 4.** *In situ* TEM images of the (a) 1st, (b) 2nd, and (c) 3rd switching cycle of a Cu:GeS film. Images (a1), (b1), and (c1) are before the SET cycle, and those of (a2), (b2), and (c2) are after SET. The probe position was shifted between (a) and (b), while it was unchanged between (b) and (c). The arrow marks the potion where the probe was contacted in the 1st cycle.

even in HRS. These residues are thought to act as nuclei of the filaments.

The special constitution of CBRAM was used in Section 3 for easy performance of experiments, such as a tip-shaped electrode and nonuse of Cu electrode. Operation was slow, and the current was much less than μA. This is satisfactory for a characterization of conductive filaments. However, to understand realistic operation, the multiple switching cycles should be achieved for multilayered CBRAMs. In Sections 5 and 6, MoOx and WOx sandwiched between electrochemically active Cu and inactive TiN electrodes are demonstrated. The dynamics of filament growth/shrinkage (Section 5) and device degradation (Section 6) are discussed through repetitive ReRAM operations with increase of the switching current.

The CBRAMs studied are Pt(100)/Cu(30)/MoOx(50) and Pt(100)/Cu(30)/WOx(20) on TiN/Si substrates, where the numbers denote the thicknesses in nm. Here, the TiN surface was oxidized due to the O<sup>2</sup> plasma treatment for cleaning. The oxide switching layers were prepared using reactive RF sputtering (Ar-20% O<sup>2</sup> ) of metal targets, while the others were by Ar RF sputtering. All depositions were done at RT without any heat treatment, and both oxides were amorphous. Typical TEM image and EDX map are shown in **Figure 5(a) and (b)**. The layer structure is clearly identified, and the overall switching area is observable. Samples for *in situ* TEM were processed using the ion-shadow method [48], where many cone-shaped small devices were formed. The device diameter was less than 500 nm as shown in **Figure 5(a)**. The current for switching was measured between the biased Pt/Cu and grounded TiN/Si. The current in the LRS was limited by the serially connected resistance of TiN/Si.

**Figure 5.** (a) TEM image and (b) EDX mapping of a Pt/Cu/WOx /TiN sample where clear layer stacking was seen. The *I–V* switching curve of (c) a TEM sample (size: 350 nm) and (d) a microdevice (size: 16 μm) of Pt/Cu/MoOx /TiN. They corresponded well to each other. (e) EDX spectra from the MoOx layer without the filament (Reg-1 and Reg-2) and the filament (Reg-3). Enhancement of the Cu signal was clearly seen in Reg-3. Inset is the TEM image showing the analyzed areas.

Multiple switching was realized during the TEM observation. An example of the *I–V* curve measured in TEM is **Figure 5(c)**. The current gradually increased with positive voltage, and then the resistance was quickly converted to LRS. In the negative voltage region, the current exhibited jumps giving HRS. This is the typical bipolar switching as seen in **Figure 5(d)** of a conventional CBRAM device fabricated on a Si wafer using the lithography technique. The similarity of fundamental features of these graphs indicates that the vacuum environment in the TEM and electron beam irradiation had no negative effects.

model [8, 10, 14, 22]. This behavior has been observed in other switching materials like SiO<sup>2</sup>

additional voltage application (over-SET named in this report), the filament grew further and changed its contact position with the Cu electrode toward the left (**Figure 6(g)**). Even after bridging, the filament shape continued to change. Finally, the resistance changed from 500 to

The growth direction reversed in the subsequent SET cycle (**Figure 7**). The switching started at states-(c) and (d). At this moment, there was no dramatic change in the TEM image (**Figure 7(b)–(d)**). When the current increased rapidly at state-(e), a small dark contrast appeared near the cathode (TiN). This is thought to be the nucleus of the filament. It grew, and a 35 nm thick filament bound two electrodes (**Figure 7(f)–(g)**). After the nucleus appeared, the

To discuss the filament growing direction, five images sequentially extracted from the video (30 ms intervals) are shown in **Figure 8**. The nucleus of the filament appeared near the BE (TiN, cathode) and grew toward the TE (Cu, anode). This fits well with the electrochemical switching model [8, 10, 14, 22]. Based on the discussion in a previous report [38], the Cu ion mobility must be high in this case. This was the SET cycle after **Figure 6** (and RESET). Thus,

ion mobility. In addition, the Joule heat also can increase the ion mobility since large compli-

The growth scheme from the cathode to the anode was seen also in another sample having

was small (700 kΩ), and Cu dissolution had happened already in the initial state. This may be caused by a temperature increase during ion milling for TEM sample preparation as seen in

Three *I–V* curves from the initial state are shown in **Figure 9(a)**. The nonhysteretic curve of the 1st cycle started to be hysteretic in the 2nd cycle. Though the resistance decreased to 400 kΩ, there was no change in the video image. In the 3rd cycle, a clear hysteresis was identified, the resistance decreased to be 30 kΩ after SET, and RESET occurred. Corresponding images (**Figure 9(b)–(d)**)

bridging was completed within 200 ms. The resistance decreased from 750 to 8 kΩ.

[42] that are thought not to dilute much Cu (or Ag). During the

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71

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

at the starting of this SET. It may influence the Cu

/TiN device when the switching

/TiN interface in the initial state. In this case, the initial resistance

[28], ZrO<sup>2</sup>

[27], and WOx

tiny Cu residuals were expected in MoOx

A was used here.

**Figure 7.** (a) The SET curve and (b)-(g) corresponding *in situ* TEM images of a Cu/MoOx

layer was expected to contain a certain amount of Cu dissolution after the cycle in **Figure 6**.

/BE [49].

ance current of > 10<sup>2</sup>

heat-treated Cu/SiO<sup>2</sup>

Cu deposits near the MoOx

8 kΩ. The LRS retention time was longer than 5 min.

Checking *in situ* TEM videos, filament-like dark contrast grew in the SET cycle and shrank/ vanished in the RESET cycle. Here, this darker contrast in the oxide layer is assumed to be the Cu-based conductive filament. This assumption was confirmed by EDX for regions with/ without the filament (**Figure 5(e)**). The filament was made up largely of Cu.

## **5. Switching operation of stacked CBRAM**

In this section, the filament dynamics and its mechanism are demonstrated. The CBRAM discussed here is mainly the device having the MoOx [29, 41, 43, 44].

#### **5.1. Filament formation in the SET process**

An example of the SET cycle is shown in **Figure 6**, where the *I–V* graph (**Figure 6(a)**) and the TEM video images (**Figure 6(b)–(g)**) are compared. The initial resistance was 40 MΩ, and thus the Cu inclusion level in MoOx was small. For initialization, 15 positive/negative cycles were done, and the resistance decreased to 500 kΩ. Clear SET/RESET switching started after this treatment. Here, the gray contrast on the right of the image is unrelated to the switching because it showed no change of note. Increasing the voltage from state-(b), the current increased gradually. In **Figure 6(c)**, a slight change was seen near the central area. The current increased greatly at 3 V (state-(d)), and a dark contrast appeared abruptly in a wide area from the Cu electrode (**Figure 6(d)**). This gathered to be a clear contrast and connected two electrodes in **Figure 6(e)–(f)**. Its growth direction was from the anode (Cu) to the cathode (TiN), and this is opposite to the direction expected in the conventional electrochemical CBRAM

**Figure 6.** (a) The SET curve and (b)-(g) corresponding *in situ* TEM images of a Cu/MoOx /TiN device with little Cu inclusion. The filament quickly grew from TE to BE.

model [8, 10, 14, 22]. This behavior has been observed in other switching materials like SiO<sup>2</sup> [28], ZrO<sup>2</sup> [27], and WOx [42] that are thought not to dilute much Cu (or Ag). During the additional voltage application (over-SET named in this report), the filament grew further and changed its contact position with the Cu electrode toward the left (**Figure 6(g)**). Even after bridging, the filament shape continued to change. Finally, the resistance changed from 500 to 8 kΩ. The LRS retention time was longer than 5 min.

Multiple switching was realized during the TEM observation. An example of the *I–V* curve measured in TEM is **Figure 5(c)**. The current gradually increased with positive voltage, and then the resistance was quickly converted to LRS. In the negative voltage region, the current exhibited jumps giving HRS. This is the typical bipolar switching as seen in **Figure 5(d)** of a conventional CBRAM device fabricated on a Si wafer using the lithography technique. The similarity of fundamental features of these graphs indicates that the vacuum environment in

Checking *in situ* TEM videos, filament-like dark contrast grew in the SET cycle and shrank/ vanished in the RESET cycle. Here, this darker contrast in the oxide layer is assumed to be the Cu-based conductive filament. This assumption was confirmed by EDX for regions with/

In this section, the filament dynamics and its mechanism are demonstrated. The CBRAM

An example of the SET cycle is shown in **Figure 6**, where the *I–V* graph (**Figure 6(a)**) and the TEM video images (**Figure 6(b)–(g)**) are compared. The initial resistance was 40 MΩ, and

were done, and the resistance decreased to 500 kΩ. Clear SET/RESET switching started after this treatment. Here, the gray contrast on the right of the image is unrelated to the switching because it showed no change of note. Increasing the voltage from state-(b), the current increased gradually. In **Figure 6(c)**, a slight change was seen near the central area. The current increased greatly at 3 V (state-(d)), and a dark contrast appeared abruptly in a wide area from the Cu electrode (**Figure 6(d)**). This gathered to be a clear contrast and connected two electrodes in **Figure 6(e)–(f)**. Its growth direction was from the anode (Cu) to the cathode (TiN), and this is opposite to the direction expected in the conventional electrochemical CBRAM

[29, 41, 43, 44].

was small. For initialization, 15 positive/negative cycles

/TiN device with little Cu

the TEM and electron beam irradiation had no negative effects.

**5. Switching operation of stacked CBRAM**

discussed here is mainly the device having the MoOx

**5.1. Filament formation in the SET process**

thus the Cu inclusion level in MoOx

70 Memristor and Memristive Neural Networks

inclusion. The filament quickly grew from TE to BE.

without the filament (**Figure 5(e)**). The filament was made up largely of Cu.

**Figure 6.** (a) The SET curve and (b)-(g) corresponding *in situ* TEM images of a Cu/MoOx

The growth direction reversed in the subsequent SET cycle (**Figure 7**). The switching started at states-(c) and (d). At this moment, there was no dramatic change in the TEM image (**Figure 7(b)–(d)**). When the current increased rapidly at state-(e), a small dark contrast appeared near the cathode (TiN). This is thought to be the nucleus of the filament. It grew, and a 35 nm thick filament bound two electrodes (**Figure 7(f)–(g)**). After the nucleus appeared, the bridging was completed within 200 ms. The resistance decreased from 750 to 8 kΩ.

To discuss the filament growing direction, five images sequentially extracted from the video (30 ms intervals) are shown in **Figure 8**. The nucleus of the filament appeared near the BE (TiN, cathode) and grew toward the TE (Cu, anode). This fits well with the electrochemical switching model [8, 10, 14, 22]. Based on the discussion in a previous report [38], the Cu ion mobility must be high in this case. This was the SET cycle after **Figure 6** (and RESET). Thus, tiny Cu residuals were expected in MoOx at the starting of this SET. It may influence the Cu ion mobility. In addition, the Joule heat also can increase the ion mobility since large compliance current of > 10<sup>2</sup> A was used here.

The growth scheme from the cathode to the anode was seen also in another sample having Cu deposits near the MoOx /TiN interface in the initial state. In this case, the initial resistance was small (700 kΩ), and Cu dissolution had happened already in the initial state. This may be caused by a temperature increase during ion milling for TEM sample preparation as seen in heat-treated Cu/SiO<sup>2</sup> /BE [49].

Three *I–V* curves from the initial state are shown in **Figure 9(a)**. The nonhysteretic curve of the 1st cycle started to be hysteretic in the 2nd cycle. Though the resistance decreased to 400 kΩ, there was no change in the video image. In the 3rd cycle, a clear hysteresis was identified, the resistance decreased to be 30 kΩ after SET, and RESET occurred. Corresponding images (**Figure 9(b)–(d)**)

**Figure 7.** (a) The SET curve and (b)-(g) corresponding *in situ* TEM images of a Cu/MoOx /TiN device when the switching layer was expected to contain a certain amount of Cu dissolution after the cycle in **Figure 6**.

**Figure 8.** Details of the SET process in **Figure 7**, where the subsequent TEM video frames (images-1 to 5) were shown with the interval of 30 ms. The image-2 corresponds to **Figure 7(e)**. The Cu filament grew apparently from BE to TE.

showed a slight contrast change. The Cu deposit near ox-TiN/TiN (arrows) grew during SET (**Figure 9(c)**), and it disappeared during RESET (**Figure 9(d)**). This Cu deposit must play an important role in ReRAM.

Clear and abrupt current jumps began after the 4th and 5th cycles. The SET operation in the 6th cycle is shown in **Figure 10(a)** compared with the *in situ* TEM images (**Figure 10(b)–(g)**). A Cu deposit that grew in the 5th cycle (round contrast) was identified when the voltage sweep started (**Figure 10(b)**). There is an abrupt current jump at states-(c) and (d). However, the deposit did not show a clear change (**Figure 10(c)–(d)**). It then grew from the cathode (TiN) to the anode (Cu) with the current flow after the SET switching (over-SET) (**Figure 10(e)–(g)**). The deposit did not bridge two electrodes, although the resistance was reduced much.

it continued to shrink (but still not large change), toward the anode (TiN), giving roundish contrast (**Figure 11(f)** and **(g)**). The shrinkage direction fits the filament model [8, 10, 14, 22].

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/TiN), where the filament did not connect to the Cu

**Figure 10.** The 6th SET cycle performed after **Figure 9** (Cu/MoOx

video images. Growth of the filament from BE to TE was identified.

**Figure 11.** The 6th RESET cycle performed just after **Figure 10** (Cu/MoOx

**Figure 12** is another example of RESET with nonbridging (or weakly bridging) filament. In this example, the filament vanished due to large negative current (−600 μA, **Figure 12(a)**). The image at starting of the voltage sweep (**Figure 12(b)**) was not changed by RESET switching at state-(c) (**Figure 12(c)**). At state-(d) during over-RESET, an unexpected negative SET with large current occurred, and the filament began to shrink (**Figure 12(d)–(e)**). The filament vanished from the cathode (Cu) to the anode (TiN) (**Figure 12(f)–(g)**). Dissolution of the Cu filament was seen not only at the apex. A small precipitate near the Cu electrode (left of the images) also vanished in **Figure 12(g)**. The current spread widely and contributed to the erasure of the filament and the precipitate nearby. Although the negative SET was abnormal, we can conclude that the large negative current was required for a complete erasure of the filament.

TE. (a) *I–V* switching curve and (b)–(g) corresponding video images. Shrinkage of the filament from TE to BE was identified.

Summarizing shortly, there were two SET modes with filament growths from the cathode or from the anode depending on the amount of Cu in the MoOx layer.

#### **5.2. Filament shrinkage and erasure in the RESET process**

The RESET process after **Figure 10** is shown in **Figure 11**, where the filament had not bridged. At the states-(b) to (d) in **Figure 11(a)**, the TEM images (**Figure 11(b)–(d)**) maintained the contrast just after SET. A clear RESET switching occurred between states-(d) and (e), but the deposit shrank only slightly (**Figure 11(e)**). Continuing current flow (over-RESET named in this report),

**Figure 9.** (a) Three *I–V* switching cycles and (b)–(d) TEM images in the 3rd cycle of a MoOx CBRAM. The images showed appearance/disappearance of a deposit as indicated using arrows in (b) before SET, (c) after SET, and (d) after RESET.

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**Figure 10.** The 6th SET cycle performed after **Figure 9** (Cu/MoOx /TiN). (a) *I–V* switching curve and (b)–(g) corresponding video images. Growth of the filament from BE to TE was identified.

showed a slight contrast change. The Cu deposit near ox-TiN/TiN (arrows) grew during SET (**Figure 9(c)**), and it disappeared during RESET (**Figure 9(d)**). This Cu deposit must play an

**Figure 8.** Details of the SET process in **Figure 7**, where the subsequent TEM video frames (images-1 to 5) were shown with the interval of 30 ms. The image-2 corresponds to **Figure 7(e)**. The Cu filament grew apparently from BE to TE.

Clear and abrupt current jumps began after the 4th and 5th cycles. The SET operation in the 6th cycle is shown in **Figure 10(a)** compared with the *in situ* TEM images (**Figure 10(b)–(g)**). A Cu deposit that grew in the 5th cycle (round contrast) was identified when the voltage sweep started (**Figure 10(b)**). There is an abrupt current jump at states-(c) and (d). However, the deposit did not show a clear change (**Figure 10(c)–(d)**). It then grew from the cathode (TiN) to the anode (Cu) with the current flow after the SET switching (over-SET) (**Figure 10(e)–(g)**). The deposit did not bridge two electrodes, although the resistance was reduced much.

Summarizing shortly, there were two SET modes with filament growths from the cathode or

The RESET process after **Figure 10** is shown in **Figure 11**, where the filament had not bridged. At the states-(b) to (d) in **Figure 11(a)**, the TEM images (**Figure 11(b)–(d)**) maintained the contrast just after SET. A clear RESET switching occurred between states-(d) and (e), but the deposit shrank only slightly (**Figure 11(e)**). Continuing current flow (over-RESET named in this report),

layer.

CBRAM. The images showed

from the anode depending on the amount of Cu in the MoOx

**5.2. Filament shrinkage and erasure in the RESET process**

**Figure 9.** (a) Three *I–V* switching cycles and (b)–(d) TEM images in the 3rd cycle of a MoOx

appearance/disappearance of a deposit as indicated using arrows in (b) before SET, (c) after SET, and (d) after RESET.

important role in ReRAM.

72 Memristor and Memristive Neural Networks

it continued to shrink (but still not large change), toward the anode (TiN), giving roundish contrast (**Figure 11(f)** and **(g)**). The shrinkage direction fits the filament model [8, 10, 14, 22].

**Figure 12** is another example of RESET with nonbridging (or weakly bridging) filament. In this example, the filament vanished due to large negative current (−600 μA, **Figure 12(a)**). The image at starting of the voltage sweep (**Figure 12(b)**) was not changed by RESET switching at state-(c) (**Figure 12(c)**). At state-(d) during over-RESET, an unexpected negative SET with large current occurred, and the filament began to shrink (**Figure 12(d)–(e)**). The filament vanished from the cathode (Cu) to the anode (TiN) (**Figure 12(f)–(g)**). Dissolution of the Cu filament was seen not only at the apex. A small precipitate near the Cu electrode (left of the images) also vanished in **Figure 12(g)**. The current spread widely and contributed to the erasure of the filament and the precipitate nearby. Although the negative SET was abnormal, we can conclude that the large negative current was required for a complete erasure of the filament.

**Figure 11.** The 6th RESET cycle performed just after **Figure 10** (Cu/MoOx /TiN), where the filament did not connect to the Cu TE. (a) *I–V* switching curve and (b)–(g) corresponding video images. Shrinkage of the filament from TE to BE was identified.

**Figure 12.** The RESET operation of a Cu/MoOx /TiN where the filament did not show clear connection to the Cu TE. (a) *I–V* switching curve and (b)–(g) corresponding video images. The filament was overall erased from TE to BE during over-RESET while it did now show any change to note at the moment of RESET switching (state c).

**Figure 13** is an example to show what happens for the bridging filament, which is the RESET process of **Figure 7**. With negative voltage sweep, the LRS was weakly changed by RESET before (c). The resistance further increased after another weak RESET between state-(c) and (d). However, the image of **Figure 13(d)** did not change from **Figure 13(b)–(c)**. This suggests that the RESET switching occurred locally in the filament, probably at the ends of filaments touching the electrodes [50, 51]. Through over-RESET with large negative current, the filament started to shrink (**Figure 13(e)**) and was diminished in **Figure 13(f)**. It was erased in **Figure 13(g)** although some residuals remained. A clear hysteresis was seen, and the resistance changed from 9 to 200 kΩ. The details are shown in **Figure 14** with 30 ms intervals. The filament shrank from the anode (TiN) to the cathode (Cu). This behavior did not fit with the reported filament model [8, 10, 14, 22]. The TiN surface was oxidized in this experiment, which must have higher resistance than the filament. The Joule heat concentrated in this region may assist the Cu dissolution there, and the Cu ions moved along the electric field and are adsorbed by the Cu TE.

as well as the data retention of LRS. In this subsection, the relation between the switching

**Figure 14.** Details of the RESET process in **Figure 13**, where the subsequent TEM video frames (images-1 to 24) were

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To investigate the filament growth, five successive SET/RESET cycles were measured (**Figure 15**),

over-RESET was used to prevent shrinkage of the filament. As identified in **Figure 15(a)**, the resistance gradually decreased. Corresponding TEM images acquired after SET operations are shown in **Figure 15(b)–(f)**. The filament grew step-by-step from the cathode (TiN) to the anode (Cu) with the increase of the injection power at SET. Though the resistance did not show drastic change even when the filament reached the Cu TE, it was because the resistance of TiN/Si seri-

There is a set of data with large SET current in **Figure 16**, where enough over-RESET was done

1 mA, at which the device was destructed. **Figure 16(a)–(d)** shows the TEM images taken just

curves and the video images after SET in the (b) 9th, (c) 10th, (d) 11th, (e) 12th and (f) 13th cycles. The filament grew step

comp. Here, almost no

comp was stepwise increased to

/TiN). (a) The switching

comp = 200 μA was thin, and it became thick

power at SET and the filament size will be discussed using *in situ* TEM results.

where the over-SET process was gradually strengthened with increasing *I*

shown with the interval of 30 ms. The Cu filament shrank apparently from BE to TE.

ally connected to the switching layer limited the current.

after each SET. The filament in the 1st SET with *I*

with *I*comp (**Figure 16(e)**) as expected earlier [51, 52].

by step, and the resistance decreased.

to erase the filament in each cycle. During SET/RESET cycles, *I*

**Figure 15.** The 9th to 13th SET operations with increasing the compliance current (Cu/MoOx

#### **5.3. Switching power and filament size**

The current flow during RESET is an important factor to control the filament. This is true also for SET to form the conductive filament. The filament size is a key factor to affect the resistance

**Figure 13.** The RESET operation of a Cu/MoOx /TiN when the filament bridged two electrodes. (a) *I–V* switching curve and (b)–(g) corresponding video images.

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**Figure 14.** Details of the RESET process in **Figure 13**, where the subsequent TEM video frames (images-1 to 24) were shown with the interval of 30 ms. The Cu filament shrank apparently from BE to TE.

**Figure 13** is an example to show what happens for the bridging filament, which is the RESET process of **Figure 7**. With negative voltage sweep, the LRS was weakly changed by RESET before (c). The resistance further increased after another weak RESET between state-(c) and (d). However, the image of **Figure 13(d)** did not change from **Figure 13(b)–(c)**. This suggests that the RESET switching occurred locally in the filament, probably at the ends of filaments touching the electrodes [50, 51]. Through over-RESET with large negative current, the filament started to shrink (**Figure 13(e)**) and was diminished in **Figure 13(f)**. It was erased in **Figure 13(g)** although some residuals remained. A clear hysteresis was seen, and the resistance changed from 9 to 200 kΩ. The details are shown in **Figure 14** with 30 ms intervals. The filament shrank from the anode (TiN) to the cathode (Cu). This behavior did not fit with the reported filament model [8, 10, 14, 22]. The TiN surface was oxidized in this experiment, which must have higher resistance than the filament. The Joule heat concentrated in this region may assist the Cu dissolution there, and the Cu ions moved along the electric field and

*I–V* switching curve and (b)–(g) corresponding video images. The filament was overall erased from TE to BE during

over-RESET while it did now show any change to note at the moment of RESET switching (state c).

/TiN where the filament did not show clear connection to the Cu TE. (a)

/TiN when the filament bridged two electrodes. (a) *I–V* switching curve

The current flow during RESET is an important factor to control the filament. This is true also for SET to form the conductive filament. The filament size is a key factor to affect the resistance

are adsorbed by the Cu TE.

**5.3. Switching power and filament size**

**Figure 13.** The RESET operation of a Cu/MoOx

and (b)–(g) corresponding video images.

**Figure 12.** The RESET operation of a Cu/MoOx

74 Memristor and Memristive Neural Networks

as well as the data retention of LRS. In this subsection, the relation between the switching power at SET and the filament size will be discussed using *in situ* TEM results.

To investigate the filament growth, five successive SET/RESET cycles were measured (**Figure 15**), where the over-SET process was gradually strengthened with increasing *I* comp. Here, almost no over-RESET was used to prevent shrinkage of the filament. As identified in **Figure 15(a)**, the resistance gradually decreased. Corresponding TEM images acquired after SET operations are shown in **Figure 15(b)–(f)**. The filament grew step-by-step from the cathode (TiN) to the anode (Cu) with the increase of the injection power at SET. Though the resistance did not show drastic change even when the filament reached the Cu TE, it was because the resistance of TiN/Si serially connected to the switching layer limited the current.

There is a set of data with large SET current in **Figure 16**, where enough over-RESET was done to erase the filament in each cycle. During SET/RESET cycles, *I* comp was stepwise increased to 1 mA, at which the device was destructed. **Figure 16(a)–(d)** shows the TEM images taken just after each SET. The filament in the 1st SET with *I* comp = 200 μA was thin, and it became thick with *I*comp (**Figure 16(e)**) as expected earlier [51, 52].

**Figure 15.** The 9th to 13th SET operations with increasing the compliance current (Cu/MoOx /TiN). (a) The switching curves and the video images after SET in the (b) 9th, (c) 10th, (d) 11th, (e) 12th and (f) 13th cycles. The filament grew step by step, and the resistance decreased.

**Figure 16.** (a)-(d) *In situ* TEM images after SET with increasing the compliance current (a: 200, b: 400, c: 400 and d: 600 μA). After each SET, strong over-RESET was done to erase the filament. (e) Filament diameter increased with the compliance current. In addition, the filament position changed very much.

#### **5.4. Summary of the switching schematics**

Based on the results described above, SET/RESET operations are classified in **Figure 17**. There are two SET modes and two RESET modes.

and becomes thin overall due to widely spread current leakage. This tendency is thought to be enhanced with temperature increase during over-RESET with high current. In contrast, the filament bridging two electrodes ruptures in a region contacting with the anode (TiN); RESET-2. This is caused by the thin ox-TiN layer. The Joule heat is preferably generated near this area because of its high resistance, and Cu of the lower part of the filament is preferably dissolved

the heat generated in the filament must play an important role to the electrochemical processes. Strictly speaking, the discussion here addresses filament formation/shrinkage during over-SET/over-RESET. Sharp resistance switching in stable *I–V* cycles can occur without such large changes. Even when the filament showed a remarkable change, this change did not occur at

As described above, large geometrical change of the filament (or deposit) was not identified at

(**Figure 18**), where nonbridging deposit (area marked with "p" in **Figure 18(b-7)**) had been

switching current was less than 50 μA to prevent over-SET and over-RESET. While there was no change until **Figure 18(b2)**, the bottom edge of the Cu deposit swelled out downward into ox-TiN in state-3 after the SET switching (arrow in **Figure 18(b3)**). This faint contrast of the filament appeared to bridge the deposit and TiN as seen in **Figure 18(b4)–(b5)**. After the

–ox-TiN/TiN interface. In the *I–V* measurement of **Figure 18(a)**, the

layer was observed

the moment of sharp SET/RESET switching. Stable switching occurs very locally.

the switching moment. To check this phenomenon, the lower part of MoOx

**Figure 17.** Switching schematics. There were two SET modes and two RESET modes.

. The dissolved ions move along the widely spread electric field. In both RESET modes,

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in MoOx

**5.5. Role of the interface region**

segregated at the MoOx

When the MoOx layer contains little Cu inclusions, a high SET voltage is required. The Cu of the anode moves quickly into MoOx and generates deposits in a wide area, and they gather to form the filament (SET-1). When enough Cu has been dissolved in the initial state or during *I–V* cycles, the deposit appears on the TiN cathode and grows toward the Cu anode (SET-2). For enough resistance decrease, the filament connecting two electrodes is not necessarily required. The Cu*<sup>z</sup>*<sup>+</sup> ions, oxygen vacancies and/or electrons are thought to contribute the total current. Connection of electrodes is achieved with sufficient over-SET.

There is a report on oxide CBRAMs with Ag [38]. When the Ag mobility in the oxide is low compared with the reduction rate, Ag ions are reduced to be metal before drifting for long distances, and the filament grows from the anode (Ag) to the cathode. SET-1 is categorized as this type as reported in ZrO<sup>2</sup> [27], SiO<sup>2</sup> [28] and WOx [42]. On the other hand, when MoOx contains sufficient Cu ions, the filament formation at the MoOx –cathode interface can be discussed using the conventional electrochemical model [8, 10, 14, 22]. The Cu ions near the cathode can quickly reach the cathode and easily initiate the filament formation. At the same time, Cu ions are continuously generated by oxidation of the Cu electrode and supplied into MoOx . As the result, the filament grows toward the anode (Cu). This is a plausible explanation for SET-2. A similar discussion was conducted in a previous report [53].

There are two RESET modes. The nonbridging filament tends to shrink toward the cathode (TiN). This is RESET-1. In this case, the filament acts as the anode. This transition is explained using the conventional model [8, 10, 14, 22]. The Cu filament is electrochemically dissolved in MoOx

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**Figure 17.** Switching schematics. There were two SET modes and two RESET modes.

and becomes thin overall due to widely spread current leakage. This tendency is thought to be enhanced with temperature increase during over-RESET with high current. In contrast, the filament bridging two electrodes ruptures in a region contacting with the anode (TiN); RESET-2. This is caused by the thin ox-TiN layer. The Joule heat is preferably generated near this area because of its high resistance, and Cu of the lower part of the filament is preferably dissolved in MoOx . The dissolved ions move along the widely spread electric field. In both RESET modes, the heat generated in the filament must play an important role to the electrochemical processes.

Strictly speaking, the discussion here addresses filament formation/shrinkage during over-SET/over-RESET. Sharp resistance switching in stable *I–V* cycles can occur without such large changes. Even when the filament showed a remarkable change, this change did not occur at the moment of sharp SET/RESET switching. Stable switching occurs very locally.

#### **5.5. Role of the interface region**

**5.4. Summary of the switching schematics**

compliance current. In addition, the filament position changed very much.

are two SET modes and two RESET modes.

Connection of electrodes is achieved with sufficient over-SET.

[27], SiO<sup>2</sup>

similar discussion was conducted in a previous report [53].

sufficient Cu ions, the filament formation at the MoOx

the anode moves quickly into MoOx

76 Memristor and Memristive Neural Networks

When the MoOx

type as reported in ZrO<sup>2</sup>

The Cu*<sup>z</sup>*<sup>+</sup>

Based on the results described above, SET/RESET operations are classified in **Figure 17**. There

**Figure 16.** (a)-(d) *In situ* TEM images after SET with increasing the compliance current (a: 200, b: 400, c: 400 and d: 600 μA). After each SET, strong over-RESET was done to erase the filament. (e) Filament diameter increased with the

form the filament (SET-1). When enough Cu has been dissolved in the initial state or during *I–V* cycles, the deposit appears on the TiN cathode and grows toward the Cu anode (SET-2). For enough resistance decrease, the filament connecting two electrodes is not necessarily required.

There is a report on oxide CBRAMs with Ag [38]. When the Ag mobility in the oxide is low compared with the reduction rate, Ag ions are reduced to be metal before drifting for long distances, and the filament grows from the anode (Ag) to the cathode. SET-1 is categorized as this

using the conventional electrochemical model [8, 10, 14, 22]. The Cu ions near the cathode can quickly reach the cathode and easily initiate the filament formation. At the same time, Cu ions

result, the filament grows toward the anode (Cu). This is a plausible explanation for SET-2. A

There are two RESET modes. The nonbridging filament tends to shrink toward the cathode (TiN). This is RESET-1. In this case, the filament acts as the anode. This transition is explained using the conventional model [8, 10, 14, 22]. The Cu filament is electrochemically dissolved in MoOx

[28] and WOx

are continuously generated by oxidation of the Cu electrode and supplied into MoOx

ions, oxygen vacancies and/or electrons are thought to contribute the total current.

layer contains little Cu inclusions, a high SET voltage is required. The Cu of

and generates deposits in a wide area, and they gather to

[42]. On the other hand, when MoOx

–cathode interface can be discussed

contains

. As the

As described above, large geometrical change of the filament (or deposit) was not identified at the switching moment. To check this phenomenon, the lower part of MoOx layer was observed (**Figure 18**), where nonbridging deposit (area marked with "p" in **Figure 18(b-7)**) had been segregated at the MoOx –ox-TiN/TiN interface. In the *I–V* measurement of **Figure 18(a)**, the switching current was less than 50 μA to prevent over-SET and over-RESET. While there was no change until **Figure 18(b2)**, the bottom edge of the Cu deposit swelled out downward into ox-TiN in state-3 after the SET switching (arrow in **Figure 18(b3)**). This faint contrast of the filament appeared to bridge the deposit and TiN as seen in **Figure 18(b4)–(b5)**. After the

The reason can be discussed using **Figure 16** in Section 5.3. Five SET/RESET cycles were

formed in each SET was well erased using over-RESET. A filament appeared in the 1st SET of

at the position shifted along the left (**Figure 16(b)**). Its position changed again to the right in the 3rd SET (**Figure 16(c)**). In the 4th SET, it moved to the left (**Figure 16(d)**). In the example of Section 3.3 (without over-RESET), the filament kept the position, and the tiny filament nuclei were expected as residues. On the other hand, the nuclei must be removed after the strong over-RESET in **Figure 16**. Complete erasure of the filament can give a higher resistance value in HRS, and a large memory window can be achieved. However, at the same time, it possibly induces a position change of the filament and switching instability. Power control of RESET to maintain filament residuals is thought to be important for the stable switching operation.

Strong over-RESET induces switching instability. Therefore, the SET/RESET switching cycles

from 20 to 300 μA. A large current may increase temperature and induce widely spread leakage current. Therefore, these experiments are "accelerated aging tests" under severe condi-

Typical *I–V* curves measured in TEM are shown in **Figure 19(a)–(d)**. The characteristics of these curves are quite similar to that of a conventional device (**Figure 1(b)**, 4 μm in diameter), both of which showed the sharp bipolar switching. The difference of the switching voltage from the conventional device is caused by the small device size of the TEM sample (~210 nm).

/TiN without performing over-RESET for 10 times, where the

comp) and the RESET currents (|−*I*max|) are summarized in

/TiN during *in situ* TEM observations. (a)–(d) Examples of *I–V*

max|, and (f) the

max| tended to increase with *I*comp as pointed out in earlier reports

**Figure 16(a)**, and it was erased. In the 2nd cycle with larger *I*

voltage was back to 0 V after the RESET switching occurred. The *I*

tions, which is usually done before practical use of electronic devices.

switching, (e) the relation between the compliance current *I*comp and the maximum RESET current |−*I*

cyclic endurance graph where the resistances were evaluated using the *I–V* graphs both in the SET and RESET processes.

/TiN CBRAM until device destruction for *I*

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

comp = 1 mA. The filament

79

comp, a thicker filament appeared

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comp was increased stepwise

repeated using a Cu/MoOx

**6.2. HRS endurance failure**

were investigated on Cu/WOx

The maximum SET current (*I*

**Figure 19.** The SET/RESET operations of Cu/WOx

**Figure 19(e)**. The current |−*I*

**Figure 18.** The SET/RESET operation showing formation/erasure of a nanofilament in thin ox-TiN at the MoOx /TiN interface. The states 1–7 in (a) the *I–V* switching curve and (b) TEM images correspond to each other.

RESET switching around −1.5 V, this faint contrast disappeared (**Figure 18(b6)** and **(b7)**). This filament appearance/disappearance was observed at the same position also in another switching cycle. Its width was roughly 3–5 nm. Such a small filament contributes to ReRAM switching without over-SET and over-RESET. The filament in ox-TiN appeared from Cu to TiN and disappeared from TiN to Cu. The inconsistency of this phenomenon with the conventional model [8, 10, 14, 22] can be discussed with the reduction/oxidation of the Cu ions within the oxide layer [27, 28, 54] or the doping/dedoping effect [55].

This device structure is classified as a CBRAM with double switching layers like CuTe or Cu:MoOx with GdOx [56, 57] showing stable operation. The thick filament in the solid electrolyte may act as a narrow electrode limiting the switching region. Power control not to erase the thick filament in the solid electrolyte layer is important for stable switching repetition.

## **6. Device degradation**

Majority of *in situ* TEM works has been done to study the switching mechanism (especially SET). They were low power switching because the slow operation makes easy observations. Considering realistic devices, studies of device reliability like data retention, endurance [58–60], and switching stability are required. For this purpose, multiple switching cycles with various currents should be performed. In this section, two device degradation tests will be demonstrated using Cu/MoOx /TiN and Cu/WOx /TiN. In both the examples, the operation was gradually strengthened in repetitive cycles to execute the accelerated aging tests [29, 42, 44].

#### **6.1. Position instability of the filament after over-RESET**

For an actual operation, a large resistance ratio HRS/LRS is needed. The high HRS resistance satisfies this demand. This can be achieved using over-RESET. However, the switching cycle was fatally damaged, while the stable cycle continued without it.

The reason can be discussed using **Figure 16** in Section 5.3. Five SET/RESET cycles were repeated using a Cu/MoOx /TiN CBRAM until device destruction for *I* comp = 1 mA. The filament formed in each SET was well erased using over-RESET. A filament appeared in the 1st SET of **Figure 16(a)**, and it was erased. In the 2nd cycle with larger *I* comp, a thicker filament appeared at the position shifted along the left (**Figure 16(b)**). Its position changed again to the right in the 3rd SET (**Figure 16(c)**). In the 4th SET, it moved to the left (**Figure 16(d)**). In the example of Section 3.3 (without over-RESET), the filament kept the position, and the tiny filament nuclei were expected as residues. On the other hand, the nuclei must be removed after the strong over-RESET in **Figure 16**. Complete erasure of the filament can give a higher resistance value in HRS, and a large memory window can be achieved. However, at the same time, it possibly induces a position change of the filament and switching instability. Power control of RESET to maintain filament residuals is thought to be important for the stable switching operation.

#### **6.2. HRS endurance failure**

RESET switching around −1.5 V, this faint contrast disappeared (**Figure 18(b6)** and **(b7)**). This filament appearance/disappearance was observed at the same position also in another switching cycle. Its width was roughly 3–5 nm. Such a small filament contributes to ReRAM switching without over-SET and over-RESET. The filament in ox-TiN appeared from Cu to TiN and disappeared from TiN to Cu. The inconsistency of this phenomenon with the conventional model [8, 10, 14, 22] can be discussed with the reduction/oxidation of the Cu ions within the

**Figure 18.** The SET/RESET operation showing formation/erasure of a nanofilament in thin ox-TiN at the MoOx

interface. The states 1–7 in (a) the *I–V* switching curve and (b) TEM images correspond to each other.

This device structure is classified as a CBRAM with double switching layers like CuTe or

lyte may act as a narrow electrode limiting the switching region. Power control not to erase the thick filament in the solid electrolyte layer is important for stable switching repetition.

Majority of *in situ* TEM works has been done to study the switching mechanism (especially SET). They were low power switching because the slow operation makes easy observations. Considering realistic devices, studies of device reliability like data retention, endurance [58–60], and switching stability are required. For this purpose, multiple switching cycles with various currents should be performed. In this section, two device degradation tests will be demonstrated

For an actual operation, a large resistance ratio HRS/LRS is needed. The high HRS resistance satisfies this demand. This can be achieved using over-RESET. However, the switching cycle

strengthened in repetitive cycles to execute the accelerated aging tests [29, 42, 44].

[56, 57] showing stable operation. The thick filament in the solid electro-

/TiN

/TiN. In both the examples, the operation was gradually

oxide layer [27, 28, 54] or the doping/dedoping effect [55].

/TiN and Cu/WOx

**6.1. Position instability of the filament after over-RESET**

was fatally damaged, while the stable cycle continued without it.

Cu:MoOx

with GdOx

78 Memristor and Memristive Neural Networks

**6. Device degradation**

using Cu/MoOx

Strong over-RESET induces switching instability. Therefore, the SET/RESET switching cycles were investigated on Cu/WOx /TiN without performing over-RESET for 10 times, where the voltage was back to 0 V after the RESET switching occurred. The *I* comp was increased stepwise from 20 to 300 μA. A large current may increase temperature and induce widely spread leakage current. Therefore, these experiments are "accelerated aging tests" under severe conditions, which is usually done before practical use of electronic devices.

Typical *I–V* curves measured in TEM are shown in **Figure 19(a)–(d)**. The characteristics of these curves are quite similar to that of a conventional device (**Figure 1(b)**, 4 μm in diameter), both of which showed the sharp bipolar switching. The difference of the switching voltage from the conventional device is caused by the small device size of the TEM sample (~210 nm). The maximum SET current (*I* comp) and the RESET currents (|−*I*max|) are summarized in **Figure 19(e)**. The current |−*I* max| tended to increase with *I*comp as pointed out in earlier reports

**Figure 19.** The SET/RESET operations of Cu/WOx /TiN during *in situ* TEM observations. (a)–(d) Examples of *I–V* switching, (e) the relation between the compliance current *I*comp and the maximum RESET current |−*I* max|, and (f) the cyclic endurance graph where the resistances were evaluated using the *I–V* graphs both in the SET and RESET processes.

[61, 62]. The cyclic endurance is summarized in **Figure 19(f)**. The HRS/LRS resistance ratio was around 10<sup>2</sup> . All of these properties satisfy switching fundamentals of the CBRAM devices. Thus, the *in situ* TEM results below can reflect the general ReRAM degradation property.

This may induce switching instability. The power balance of SET and RESET is important

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

Localization of the switching area may be effective to satisfy this requirement because the low power switching can be achieved without large change and easy power control of SET and RESET is expected. The nanofabricated multistacked device has a possibility to satisfy this requirement as used in the VCM [14, 63]. In this section, there is an example of *in situ* TEM of such devices [40, 41]. The evolution of the filament and Cu condensation are discussed in the

**Figure 21(a)** is a schematic of the TEM sample. Nine devices were fabricated on a Si chip. Each CBRAM cell is composed of a Cu–Te-based solid electrolyte layer between the TE and the bottom insulator in the contact hole (30 or 70 nm). For *in situ* TEM, the device was processed by the focused ion beam technique (FIB). The current was measured between the biased TE and the grounded Si. Repetitive *I–V* cycles during *in situ* TEM are shown in **Figure 21(b)**, where 60 cycles were confirmed without degradation. The most important point is that the TEM

The *I–V* switching curves and TEM images of the 30-nm cell are tabulated in **Figure 22** where

clear and sharp ReRAM switching was realized. In the main part of this table, the contact hole

change due to filament formation/rupture is seen inside the insulator layer (triangle) while it could not be identified without the contrast enhancement. Other dark contrasts visible in the insulator, which did not show any change, are not related to the resistive switching and

**Figure 21.** (a) Schematics of the nanofabricated device for *in situ* TEM, and (b) repetitive *I–V* switching (60 SET/RESET

comp. In all cases, the

comp was larger than 125 μA, contrast

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81

**7.** *In situ* **TEM of nanofabricated CBRAM devices**

nanometer range. Data retention and pulse endurance are also discussed.

sample reproduced the same characteristics as actual devices on memory chips.

the data before and after SET and after RESET are compared for different *I*

**7.1.** *I–V* **switching current and filament size**

cycles) achieved in TEM.

area was magnified with contrast enhancement. When *I*

to avoid this degradation.

The resistance in the HRS gradually decreased in this graph, although the resistance ratio was still large. Here, the behavior of LRS could not be discussed because it was limited by the resistance of the serially connected substrate. Continuing the switching cycles, the device would reach HRS endurance failure as in conventional devices [58–60]. Corresponding TEM images in the initial state and after SET/RESET operations are listed in **Figure 20(a)** and **(b)–(h)**, respectively. After switching from the initial state, a filament was formed at the position marked with a triangle in **Figure 20(b)**. In the subsequent operations in **Figure 20(c)–(d)**, clear change of the filament was not identified. Afterward, small deposits grew on TiN as seen in **Figure 20(e)–(g)** with the increase of the SET current. When *I* comp was 300 μA, a thick filament appeared at another position (**Figure 20(h)**). With the advancement of the cycles with increasing *I* comp, the WOx layer became thin. This indicates that current widely spread in WOx when *I* comp was high. The Cu moved along this current leakage and was deposited widely at the interface. Even after the filament formation, the switching layer other than the filament changes. This must be the origin of the HRS endurance failure. This failure that occurred in the operation with weak RESET was proposed to be caused by the ruptured filament tip [58, 60]. However, based on the result here, Cu tends to accumulate at the interface not only around the conductive filament.

#### **6.3. Summary**

The switching characteristics are influenced by the electric power injected into the device. High SET current enhances the filament growth and lowering of the LRS resistance as seen in **Figure 15**. Although the resistance decrease in this figure was hindered behind the substrate resistance, it will be clearly seen in **Figure 24(a)** in the next section. High HRS/LRS resistance ratio is expected in this condition. However, strong SET (or over-SET) induces unexpected Cu deposition around the filament due to Cu dissolution and movement along the widely spread current leakage. This makes the switching layer thin and the HRS endurance failure may occur. The strong RESET (or over-RESET) can recover this failure [58], which erases the filament (and deposits) and moves Cu inclusion back to the Cu electrode. However, the filament position tends to change in the next switching cycle.

**Figure 20.** TEM images during device degradation of Cu/WOx /TiN. The *I–V* switching cycles were performed with no over-RESET. (a) Initial, after SET/RESET of the (b) 1st (*I*comp = 20 μA), (c) 2nd (50 μA), (d) 4th (100 μA), (e) 6th (150 μA), (f) 8th (200 μA), (g) 9th (250 μA), and (h) 10th (300 μA) cycles. The first filament was formed at the triangle in (b). The bright region corresponding to the WOx became thin.

This may induce switching instability. The power balance of SET and RESET is important to avoid this degradation.

## **7.** *In situ* **TEM of nanofabricated CBRAM devices**

[61, 62]. The cyclic endurance is summarized in **Figure 19(f)**. The HRS/LRS resistance ratio

The resistance in the HRS gradually decreased in this graph, although the resistance ratio was still large. Here, the behavior of LRS could not be discussed because it was limited by the resistance of the serially connected substrate. Continuing the switching cycles, the device would reach HRS endurance failure as in conventional devices [58–60]. Corresponding TEM images in the initial state and after SET/RESET operations are listed in **Figure 20(a)** and **(b)–(h)**, respectively. After switching from the initial state, a filament was formed at the position marked with a triangle in **Figure 20(b)**. In the subsequent operations in **Figure 20(c)–(d)**, clear change of the filament was not identified. Afterward, small deposits grew on TiN as seen in **Figure 20(e)–(g)**

Thus, the *in situ* TEM results below can reflect the general ReRAM degradation property.

another position (**Figure 20(h)**). With the advancement of the cycles with increasing *I*

The Cu moved along this current leakage and was deposited widely at the interface. Even after the filament formation, the switching layer other than the filament changes. This must be the origin of the HRS endurance failure. This failure that occurred in the operation with weak RESET was proposed to be caused by the ruptured filament tip [58, 60]. However, based on the result here, Cu tends to accumulate at the interface not only around the conductive filament.

The switching characteristics are influenced by the electric power injected into the device. High SET current enhances the filament growth and lowering of the LRS resistance as seen in **Figure 15**. Although the resistance decrease in this figure was hindered behind the substrate resistance, it will be clearly seen in **Figure 24(a)** in the next section. High HRS/LRS resistance ratio is expected in this condition. However, strong SET (or over-SET) induces unexpected Cu deposition around the filament due to Cu dissolution and movement along the widely spread current leakage. This makes the switching layer thin and the HRS endurance failure may occur. The strong RESET (or over-RESET) can recover this failure [58], which erases the filament (and deposits) and moves Cu inclusion back to the Cu electrode. However, the filament position tends to change in the next switching cycle.

over-RESET. (a) Initial, after SET/RESET of the (b) 1st (*I*comp = 20 μA), (c) 2nd (50 μA), (d) 4th (100 μA), (e) 6th (150 μA), (f) 8th (200 μA), (g) 9th (250 μA), and (h) 10th (300 μA) cycles. The first filament was formed at the triangle in (b). The bright

layer became thin. This indicates that current widely spread in WOx

. All of these properties satisfy switching fundamentals of the CBRAM devices.

comp was 300 μA, a thick filament appeared at

/TiN. The *I–V* switching cycles were performed with no

when *I*

comp, the

comp was high.

was around 10<sup>2</sup>

80 Memristor and Memristive Neural Networks

WOx

**6.3. Summary**

with the increase of the SET current. When *I*

**Figure 20.** TEM images during device degradation of Cu/WOx

became thin.

region corresponding to the WOx

Localization of the switching area may be effective to satisfy this requirement because the low power switching can be achieved without large change and easy power control of SET and RESET is expected. The nanofabricated multistacked device has a possibility to satisfy this requirement as used in the VCM [14, 63]. In this section, there is an example of *in situ* TEM of such devices [40, 41]. The evolution of the filament and Cu condensation are discussed in the nanometer range. Data retention and pulse endurance are also discussed.

**Figure 21(a)** is a schematic of the TEM sample. Nine devices were fabricated on a Si chip. Each CBRAM cell is composed of a Cu–Te-based solid electrolyte layer between the TE and the bottom insulator in the contact hole (30 or 70 nm). For *in situ* TEM, the device was processed by the focused ion beam technique (FIB). The current was measured between the biased TE and the grounded Si. Repetitive *I–V* cycles during *in situ* TEM are shown in **Figure 21(b)**, where 60 cycles were confirmed without degradation. The most important point is that the TEM sample reproduced the same characteristics as actual devices on memory chips.

## **7.1.** *I–V* **switching current and filament size**

The *I–V* switching curves and TEM images of the 30-nm cell are tabulated in **Figure 22** where the data before and after SET and after RESET are compared for different *I* comp. In all cases, the clear and sharp ReRAM switching was realized. In the main part of this table, the contact hole area was magnified with contrast enhancement. When *I* comp was larger than 125 μA, contrast change due to filament formation/rupture is seen inside the insulator layer (triangle) while it could not be identified without the contrast enhancement. Other dark contrasts visible in the insulator, which did not show any change, are not related to the resistive switching and

**Figure 21.** (a) Schematics of the nanofabricated device for *in situ* TEM, and (b) repetitive *I–V* switching (60 SET/RESET cycles) achieved in TEM.

**Figure 22.** The *I–V* switching curve and TEM images of the 30-nm cell for various compliance current *I* comp. The images in HRS before SET, LRS after SET, and HRS after RESET are compared. With large *I*comp, the filament appeared and disappeared in the insulator layer (triangle).

the insulator by the electric field at SET. This is consistent with the filament formation shown in **Figure 22** and the model predicted in a previous report of the similar double-layer CBRAM device [56]. These results prove that resistive switching here was a result of a formation pro-

**Figure 23.** TEM images and EDX maps (Cu and Te) of three devices. Initial state and two SET processes with different *I*comp are compared. In the right column, the square region in the TEM image was analyzed by EDX. When current was large, Cu movement into the insulator layer was identified. Note the magnification of the EDX maps are not constant..

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current generating very thin filament that was hard to be observed, a good retention could be achieved when the filament was localized in the thin insulator. The HRS retention capability was also confirmed to be more than 3 months because it is more stable than LRS. An additional issue can be discussed using **Figure 24(a)**. The resistance just after SET decreased with

Repeatable pulse-voltage operation is another issue to be investigated. A pulse endurance

achieved inside the TEM without any damage. These results clearly show that CBRAMs

Considering the practical application, the switching operations of nanofabricated Cu-Te cells were explained in this section. Adopting the structure with double switching layers, the Cu

comp. This was caused by the thickened filament with large *I*comp as shown in **Figure 22**.

comp is shown in **Figure 24(a)**. The LRS formed with

s = 3 months). Even with a small SET

pulse switching cycles were

cess of the Cu filament as discussed in the previous section.

comp ≥ 40 μA showed a good retention (more than 3 × 10<sup>6</sup>

graph during *in situ* TEM is shown in **Figure 24(b)**. About 10<sup>5</sup>

worked normally even during TEM experiments.

**7.3. Data retention and pulse endurance**

Resistance variation after SET for various *I*

*I*

*I*

**7.4. Summary**

thought to be wreckages of the solid electrolyte and/or electrodes appeared during the FIB process. The filament appeared and vanished at the same position near the edge of the contact hole. Electric field enhancement at the edge played an important role. On the other hand, no remarkable change was seen with low *I* comp, while the SET/RESET switching was clearly seen. Very fine filaments must be formed in these cases.

#### **7.2. Accumulation of Cu**

To perform the elementary analyses, the EDX mapping was done. The results are shown in **Figure 23**, where the data in the initial state and after the SET with *I*comp = 60 μA of the 70-nm cell, and after SET with *I* comp = 450 μA of the 30-nm cell are compared.

In the initial state, both Cu and Te maps showed uniform distribution in the solid electrolyte layer. Little change in the distribution was observed for either Cu or Te after SET (60 μA) where a clear filament could not be seen in the TEM image. However, gathering of Cu was observed at the left end of the contact hole at SET with *I* comp = 450 μA. In addition, the Cu moved and accumulated in the insulator layer. This was not seen in the Te map, where the insulator layer with a white contrast is still visible. This suggests that only Cu ions moved into

**Figure 23.** TEM images and EDX maps (Cu and Te) of three devices. Initial state and two SET processes with different *I*comp are compared. In the right column, the square region in the TEM image was analyzed by EDX. When current was large, Cu movement into the insulator layer was identified. Note the magnification of the EDX maps are not constant..

the insulator by the electric field at SET. This is consistent with the filament formation shown in **Figure 22** and the model predicted in a previous report of the similar double-layer CBRAM device [56]. These results prove that resistive switching here was a result of a formation process of the Cu filament as discussed in the previous section.

#### **7.3. Data retention and pulse endurance**

Resistance variation after SET for various *I* comp is shown in **Figure 24(a)**. The LRS formed with *I* comp ≥ 40 μA showed a good retention (more than 3 × 10<sup>6</sup> s = 3 months). Even with a small SET current generating very thin filament that was hard to be observed, a good retention could be achieved when the filament was localized in the thin insulator. The HRS retention capability was also confirmed to be more than 3 months because it is more stable than LRS. An additional issue can be discussed using **Figure 24(a)**. The resistance just after SET decreased with *I* comp. This was caused by the thickened filament with large *I*comp as shown in **Figure 22**.

Repeatable pulse-voltage operation is another issue to be investigated. A pulse endurance graph during *in situ* TEM is shown in **Figure 24(b)**. About 10<sup>5</sup> pulse switching cycles were achieved inside the TEM without any damage. These results clearly show that CBRAMs worked normally even during TEM experiments.

#### **7.4. Summary**

thought to be wreckages of the solid electrolyte and/or electrodes appeared during the FIB process. The filament appeared and vanished at the same position near the edge of the contact hole. Electric field enhancement at the edge played an important role. On the other hand, no

in HRS before SET, LRS after SET, and HRS after RESET are compared. With large *I*comp, the filament appeared and

**Figure 22.** The *I–V* switching curve and TEM images of the 30-nm cell for various compliance current *I*

To perform the elementary analyses, the EDX mapping was done. The results are shown in **Figure 23**, where the data in the initial state and after the SET with *I*comp = 60 μA of the 70-nm

comp = 450 μA of the 30-nm cell are compared. In the initial state, both Cu and Te maps showed uniform distribution in the solid electrolyte layer. Little change in the distribution was observed for either Cu or Te after SET (60 μA) where a clear filament could not be seen in the TEM image. However, gathering of Cu was

moved and accumulated in the insulator layer. This was not seen in the Te map, where the insulator layer with a white contrast is still visible. This suggests that only Cu ions moved into

comp, while the SET/RESET switching was clearly seen.

comp = 450 μA. In addition, the Cu

comp. The images

remarkable change was seen with low *I*

disappeared in the insulator layer (triangle).

82 Memristor and Memristive Neural Networks

**7.2. Accumulation of Cu**

cell, and after SET with *I*

Very fine filaments must be formed in these cases.

observed at the left end of the contact hole at SET with *I*

Considering the practical application, the switching operations of nanofabricated Cu-Te cells were explained in this section. Adopting the structure with double switching layers, the Cu

became conspicuous, and unexpected Cu deposits were formed widely at the interface. This reduced the effective thickness of the switching layer and lead to the HRS endurance failure. While strong RESET may prevent this degradation, the filament position changed under this condition, and the switching became unstable. The switching powers at SET and RESET

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This was realized by adopting miniaturized CBRAM cells with double switching layers. The thin filament in nm range was localized in a thin insulator layer, while thicker Cu condensation occurred in the solid electrolyte, which could act as a protrusion of the electrode. Sharp and stable switching was performed with low current, and less degree of Cu movement was expected. This sharp switching property is applicable for conventional binary memories. On the other hand, the sharp switching is not ideal for application of the artificial neural networks that require multilevel or analogue control of the resistance. Further device designing

The operation failure is the critical issue to ensure the practical application of ReRAMs. It is indispensable to clarify main origins of the malfunction and to guarantee device reliability. We demonstrated many *in situ* TEM functions that are available for reliability tests: *I–V* characteristics, pulse switching, endurance, and data retention. While the time resolution is limited by the video frame rate (30 ms/frame in usual cases), other functions like TEM or scanning TEM (STEM) imaging as well as the elementary or chemical analyses using EDX or electron energy loss spectroscopy (EELS) are possible. *In situ* TEM is applicable to character-

We acknowledge the financial support from the Japan Society for the Promotion of Science (JSPS, KAKENHI, 15H01706, 16H0433906, and 16K18073). This work was partly performed under the Nanotechnology Platform Program (Hokkaido Univ. and Kyushu Univ.) organized by the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), Japan. Part of this work was carried out under the collaboration with the Semiconductor Technology Academic Research Center (STARC) as well as Sony Corp. We are grateful to Messer Kouichi Hamada and Yuji Mori for development of the experimental setup, especially piezo-TEM holders. Finally, we would like to emphasize that the works reviewed here could not be

should be balanced for clear and stable ReRAM switching.

is needed to perform stable operation for this type of devices.

ize nanometer-scale ReRAM cells expected for gigabit scale integration.

accomplished without the collaboration with our laboratory members.

Masashi Arita\*, Atsushi Tsurumaki-Fukuchi and Yasuo Takahashi

Laboratory of Nanomaterial Engineering, Graduate School of Information Science and

\*Address all correspondence to: arita@nano.ist.hokudai.ac.jp

Technology, Hokkaido University, Sapporo, Japan

**Acknowledgements**

**Author details**

**Figure 24.** Reliability test performed during *in situ* TEM. (a) The LRS retention graph after SET with various compliance currents, where the read voltage was +0.2 V. (b) The pulse endurance graph. The pulse voltage and width were +3.0 V and 500 μs (for SET) or −1.5 V and 100 μs (for RESET).

nanofilament can be localized in the thin insulator, and a sharp switching can be achieved with a low current. The accumulation of Cu in the Cu-Te layer forms a thicker filament than the one in the insulator, and it acts as a miniaturized Cu electrode that limits the switching area. Increasing the switching current, the filament becomes thick for easy TEM observations, and the retention property improves. Selecting optimum operation condition, the 10<sup>5</sup> pulse switching and long retention over 3 months are possible during *in situ* TEM. The double-layer CBRAM can limit the switching area with short amount of Cu movement. This must be the key factor to realize stable and sharp switching properties.

## **8. Concluding remarks**

In this contribution, we reviewed our recent *in situ* TEM works of various CBRAMs; uncovered Cu:GeS contacted with a needle-shaped electrode, stacked Cu/MoOx /TiN or Cu/WOx / TiN, and the nanofabricated Cu–Te-based ReRAM cell.

In all cases, the Cu conductive filament appeared in the SET process and shrank/vanished in the RESET process. There were two SET modes and two RESET modes. The growth/erasure direction of the filament depended on the switching history especially the amount of Cu dissolved in the switching layer. However, in the *I–V* switching cycles, the filament did not necessarily show remarkable change in geometry at the SET/RESET switching moment. The local area near the electrode is thought to contribute this switching. *In situ* TEM in nanometer or subnanometer scale is necessary for a detailed understanding of the filament evolution.

The Cu filament grew/shrank much during over-SET/over-RESET. For such a large change, the operation current (and accompanied temperature increase) seems to play an important role. With a current increase at SET, the filament became thick and the LRS resistance decreased. However, when strong RESET was not operated, influence of widely spread leakage current became conspicuous, and unexpected Cu deposits were formed widely at the interface. This reduced the effective thickness of the switching layer and lead to the HRS endurance failure. While strong RESET may prevent this degradation, the filament position changed under this condition, and the switching became unstable. The switching powers at SET and RESET should be balanced for clear and stable ReRAM switching.

This was realized by adopting miniaturized CBRAM cells with double switching layers. The thin filament in nm range was localized in a thin insulator layer, while thicker Cu condensation occurred in the solid electrolyte, which could act as a protrusion of the electrode. Sharp and stable switching was performed with low current, and less degree of Cu movement was expected. This sharp switching property is applicable for conventional binary memories. On the other hand, the sharp switching is not ideal for application of the artificial neural networks that require multilevel or analogue control of the resistance. Further device designing is needed to perform stable operation for this type of devices.

The operation failure is the critical issue to ensure the practical application of ReRAMs. It is indispensable to clarify main origins of the malfunction and to guarantee device reliability. We demonstrated many *in situ* TEM functions that are available for reliability tests: *I–V* characteristics, pulse switching, endurance, and data retention. While the time resolution is limited by the video frame rate (30 ms/frame in usual cases), other functions like TEM or scanning TEM (STEM) imaging as well as the elementary or chemical analyses using EDX or electron energy loss spectroscopy (EELS) are possible. *In situ* TEM is applicable to characterize nanometer-scale ReRAM cells expected for gigabit scale integration.

## **Acknowledgements**

pulse

/

/TiN or Cu/WOx

nanofilament can be localized in the thin insulator, and a sharp switching can be achieved with a low current. The accumulation of Cu in the Cu-Te layer forms a thicker filament than the one in the insulator, and it acts as a miniaturized Cu electrode that limits the switching area. Increasing the switching current, the filament becomes thick for easy TEM observations, and the retention property improves. Selecting optimum operation condition, the 10<sup>5</sup>

**Figure 24.** Reliability test performed during *in situ* TEM. (a) The LRS retention graph after SET with various compliance currents, where the read voltage was +0.2 V. (b) The pulse endurance graph. The pulse voltage and width were +3.0 V

switching and long retention over 3 months are possible during *in situ* TEM. The double-layer CBRAM can limit the switching area with short amount of Cu movement. This must be the

In this contribution, we reviewed our recent *in situ* TEM works of various CBRAMs; uncov-

In all cases, the Cu conductive filament appeared in the SET process and shrank/vanished in the RESET process. There were two SET modes and two RESET modes. The growth/erasure direction of the filament depended on the switching history especially the amount of Cu dissolved in the switching layer. However, in the *I–V* switching cycles, the filament did not necessarily show remarkable change in geometry at the SET/RESET switching moment. The local area near the electrode is thought to contribute this switching. *In situ* TEM in nanometer or subnanometer scale is necessary for a detailed understanding of the filament evolution.

The Cu filament grew/shrank much during over-SET/over-RESET. For such a large change, the operation current (and accompanied temperature increase) seems to play an important role. With a current increase at SET, the filament became thick and the LRS resistance decreased. However, when strong RESET was not operated, influence of widely spread leakage current

ered Cu:GeS contacted with a needle-shaped electrode, stacked Cu/MoOx

key factor to realize stable and sharp switching properties.

and 500 μs (for SET) or −1.5 V and 100 μs (for RESET).

84 Memristor and Memristive Neural Networks

TiN, and the nanofabricated Cu–Te-based ReRAM cell.

**8. Concluding remarks**

We acknowledge the financial support from the Japan Society for the Promotion of Science (JSPS, KAKENHI, 15H01706, 16H0433906, and 16K18073). This work was partly performed under the Nanotechnology Platform Program (Hokkaido Univ. and Kyushu Univ.) organized by the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), Japan. Part of this work was carried out under the collaboration with the Semiconductor Technology Academic Research Center (STARC) as well as Sony Corp. We are grateful to Messer Kouichi Hamada and Yuji Mori for development of the experimental setup, especially piezo-TEM holders. Finally, we would like to emphasize that the works reviewed here could not be accomplished without the collaboration with our laboratory members.

## **Author details**

Masashi Arita\*, Atsushi Tsurumaki-Fukuchi and Yasuo Takahashi

\*Address all correspondence to: arita@nano.ist.hokudai.ac.jp

Laboratory of Nanomaterial Engineering, Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan

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90 Memristor and Memristive Neural Networks


**Chapter 5**

**Provisional chapter**

**Resistive Switching in Metal Oxide/Organic**

**Resistive Switching in Metal Oxide/Organic** 

DOI: 10.5772/intechopen.69023

Diodes incorporating a bilayer of a metal oxide and an organic semiconductor can show unipolar, nonvolatile memory behavior after electroforming. Electroforming involves dielectric breakdown induced by prolonged bias voltage stress. When the power dissipated during breakdown is limited, electroforming is reversible and involves formation of defects at the organic-oxide interface that can heal spontaneously. When the power dissipation during breakdown exceeds a certain threshold, electroforming becomes irreversible. The fully electroformed diodes show electrical bistability, featuring (meta) stable states with low and high conduction that can be programmed by voltage pulses. The high conduction results from current flowing via filamentary paths. The bistability is explained by the coexistence of two thermodynamically stable phases at the interface between semiconductor and oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with low work function give rise to current filaments. In the filaments, Joule heating will raise temperature locally. When the temperature exceeds the critical temperature, the filament will switch off. The switching involves a collective recombination of charge carriers trapped at the defects as evidenced

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

Metal-insulator-metal (MIM) systems often show electrically induced resistive switching. Diodes of this type have therefore been proposed as replacement of standard NAND-flash

**Keywords:** nonvolatile electronic memory, electroforming, unipolar resistive switching,

**Semiconductor Nonvolatile Memories**

**Semiconductor Nonvolatile Memories**

Henrique L. Gomes, Dago M. de Leeuw and

Henrique L. Gomes, Dago M. de Leeuw and

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69023

by bursts of electroluminescence.

phase transition, critical point

**1. Introduction**

Stefan C.J. Meskers

**Abstract**

Stefan C.J. Meskers

**Provisional chapter**

## **Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories Semiconductor Nonvolatile Memories**

**Resistive Switching in Metal Oxide/Organic** 

DOI: 10.5772/intechopen.69023

Henrique L. Gomes, Dago M. de Leeuw and Stefan C.J. Meskers Stefan C.J. Meskers Additional information is available at the end of the chapter

Henrique L. Gomes, Dago M. de Leeuw and

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69023

#### **Abstract**

Diodes incorporating a bilayer of a metal oxide and an organic semiconductor can show unipolar, nonvolatile memory behavior after electroforming. Electroforming involves dielectric breakdown induced by prolonged bias voltage stress. When the power dissipated during breakdown is limited, electroforming is reversible and involves formation of defects at the organic-oxide interface that can heal spontaneously. When the power dissipation during breakdown exceeds a certain threshold, electroforming becomes irreversible. The fully electroformed diodes show electrical bistability, featuring (meta) stable states with low and high conduction that can be programmed by voltage pulses. The high conduction results from current flowing via filamentary paths. The bistability is explained by the coexistence of two thermodynamically stable phases at the interface between semiconductor and oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with low work function give rise to current filaments. In the filaments, Joule heating will raise temperature locally. When the temperature exceeds the critical temperature, the filament will switch off. The switching involves a collective recombination of charge carriers trapped at the defects as evidenced by bursts of electroluminescence.

**Keywords:** nonvolatile electronic memory, electroforming, unipolar resistive switching, phase transition, critical point

## **1. Introduction**

Metal-insulator-metal (MIM) systems often show electrically induced resistive switching. Diodes of this type have therefore been proposed as replacement of standard NAND-flash

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

nonvolatile electronic memory [1]. In their pristine state, the materials in the MIM diodes are usually high-resistivity insulators. Before the diodes show memory properties, they have to be electroformed by applying a high electric field in a current-voltage sweep with an appropriate current compliance. This induces a so-called soft breakdown. The electroformed device can be switched between a high conductance on-state and a low conductance off-state as shown in **Figure 1**. The resulting bistable current-voltage (I-V) characteristics can be applied as a nonvolatile memory. A surprisingly large variety of materials and material combinations can give rise to resistive switching [2–9], which indicates that the mechanism of the resistive switching may be very general.

Resistive switching was first reported in 1962 when Hickmott described a hysteretic I-V characteristic in thin anodic films [10]. A large negative resistance was observed for thin films

reviewed by Dearnaley et al. [11], by Oxley [12], and by Pagnia and Sotnik [13]. In the 1990s attention shifted from binary oxides to complex metal oxides and has been reviewed by Sawa

The switching mechanism of electroformed diodes can be unipolar or bipolar depending on the type of oxide and the electroforming procedure applied [3]. In unipolar switching, the switching direction depends on the magnitude of applied bias but not on the polarity. The I-V curves of both the on-state and the off-state are symmetric, and the type of electrode is relatively unimportant. In contrast, the switching is called bipolar or antisymmetric when the set of voltage for the on-state occurs at one voltage polarity, while the reset to the off-state occurs at the reversed polarity. The I-V curves are asymmetric and depend on the type of electrode.

. Early research up to the 1980s has been thoroughly

Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories

O3

http://dx.doi.org/10.5772/intechopen.69023

95

O3

and a semiconducting polymer

. The distrib-

O3

. In order to fabri-

layer in series with

O3 layer

, and TiO2

Here, we focus on unipolar switching in diodes containing a layer of Al2

a semiconducting layer is needed. The yield of active memories made with only an Al2

is extremely low. Electroforming then almost inevitably leads to hard shorts, irrespective of the set of current compliance or of the type of forming, for example, pulsed or voltage sweep. The electrodes melt or even evaporate. Already for the memories made in the 1960s and 1970s, it turned out that an unidentified layer of carbon enhances the reproducibility. Diodes made in high vacuum did not show switching. Oil vapor contamination from a rotary pump was

Reproducible memories with a yield of about unity could be fabricated by adding a welldefined, thin layer of a semiconducting polymer [16]. The devices therefore are often called polymer RRAMs. The type of electrodes turned out to be irrelevant. After electroforming, the I-V characteristics are symmetric. A narrow voltage region with a negative differential resistance (NDR) is observed in both polarities. The device can be switched between a high conductance on-state and a low conductance off-state at biases corresponding to the

uted series resistance of the polymer prevents thermal runaway when a local filament is turned on. Polymer/oxide diodes are then expected not only to exhibit a better control of the switching properties but also to have superior endurance as compared to oxide-only based memristors. In this feature we will show that the semiconducting polymer not only acts as a current-limiting series resistance but that the polymer also plays a crucial role by providing a charged layer of trapped electrons at the polymer/oxide interface. This charge layer enhances the tunneling across the oxide and tunes the formation of electrically bistable

This contribution is an explanatory account of electroforming and unipolar switching in MIM

O3

top and bottom of the NDR. The switching is unipolar and due to the Al<sup>2</sup>

diodes with an internal bilayer structure consisting of Al2

cate reproducible memories, a bilayer comprised of a thin insulating Al2

of SiOx

defects.

, Al2 O3 , Ta2 O5 , ZrO2

[14] and by Waser and Aono [15].

needed to make reliable memories [13].

The electric fields needed to induce the electroforming are usually close to the critical field for dielectric breakdown. In practice, the electroforming needs to be tightly controlled by, for example, programming a current compliance limit in the external circuit, in order to avoid permanent shorting and breakdown of the MIM diodes. The yield of active memory cells in the electroforming step is crucial for the success of memristors as a device technology. A detailed understanding of processes happening during electroforming is therefore of paramount importance.

**Figure 1.** Diode layout. (a) Photograph of device containing several diodes. The devices with an active area of 9 mm2 were encapsulated to exclude O2 and H2 O. (b) Typical nominal e-only diode layout where the Al2 O3 thickness is varied. (c) Flat band diagram where numbers are in eV. (d) J-V characteristics after forming showing a pronounced negative differential resistance.

Resistive switching was first reported in 1962 when Hickmott described a hysteretic I-V characteristic in thin anodic films [10]. A large negative resistance was observed for thin films of SiOx , Al2 O3 , Ta2 O5 , ZrO2 , and TiO2 . Early research up to the 1980s has been thoroughly reviewed by Dearnaley et al. [11], by Oxley [12], and by Pagnia and Sotnik [13]. In the 1990s attention shifted from binary oxides to complex metal oxides and has been reviewed by Sawa [14] and by Waser and Aono [15].

nonvolatile electronic memory [1]. In their pristine state, the materials in the MIM diodes are usually high-resistivity insulators. Before the diodes show memory properties, they have to be electroformed by applying a high electric field in a current-voltage sweep with an appropriate current compliance. This induces a so-called soft breakdown. The electroformed device can be switched between a high conductance on-state and a low conductance off-state as shown in **Figure 1**. The resulting bistable current-voltage (I-V) characteristics can be applied as a nonvolatile memory. A surprisingly large variety of materials and material combinations can give rise to resistive switching [2–9], which indicates that the mechanism of the resistive

The electric fields needed to induce the electroforming are usually close to the critical field for dielectric breakdown. In practice, the electroforming needs to be tightly controlled by, for example, programming a current compliance limit in the external circuit, in order to avoid permanent shorting and breakdown of the MIM diodes. The yield of active memory cells in the electroforming step is crucial for the success of memristors as a device technology. A detailed understanding of processes happening during electroforming is

**Figure 1.** Diode layout. (a) Photograph of device containing several diodes. The devices with an active area of 9 mm2

(c) Flat band diagram where numbers are in eV. (d) J-V characteristics after forming showing a pronounced negative

O. (b) Typical nominal e-only diode layout where the Al2

O3

thickness is varied.

switching may be very general.

94 Memristor and Memristive Neural Networks

therefore of paramount importance.

were encapsulated to exclude O2

differential resistance.

and H2

The switching mechanism of electroformed diodes can be unipolar or bipolar depending on the type of oxide and the electroforming procedure applied [3]. In unipolar switching, the switching direction depends on the magnitude of applied bias but not on the polarity. The I-V curves of both the on-state and the off-state are symmetric, and the type of electrode is relatively unimportant. In contrast, the switching is called bipolar or antisymmetric when the set of voltage for the on-state occurs at one voltage polarity, while the reset to the off-state occurs at the reversed polarity. The I-V curves are asymmetric and depend on the type of electrode.

Here, we focus on unipolar switching in diodes containing a layer of Al2 O3 . In order to fabricate reproducible memories, a bilayer comprised of a thin insulating Al2 O3 layer in series with a semiconducting layer is needed. The yield of active memories made with only an Al2 O3 layer is extremely low. Electroforming then almost inevitably leads to hard shorts, irrespective of the set of current compliance or of the type of forming, for example, pulsed or voltage sweep. The electrodes melt or even evaporate. Already for the memories made in the 1960s and 1970s, it turned out that an unidentified layer of carbon enhances the reproducibility. Diodes made in high vacuum did not show switching. Oil vapor contamination from a rotary pump was needed to make reliable memories [13].

Reproducible memories with a yield of about unity could be fabricated by adding a welldefined, thin layer of a semiconducting polymer [16]. The devices therefore are often called polymer RRAMs. The type of electrodes turned out to be irrelevant. After electroforming, the I-V characteristics are symmetric. A narrow voltage region with a negative differential resistance (NDR) is observed in both polarities. The device can be switched between a high conductance on-state and a low conductance off-state at biases corresponding to the top and bottom of the NDR. The switching is unipolar and due to the Al<sup>2</sup> O3 . The distributed series resistance of the polymer prevents thermal runaway when a local filament is turned on. Polymer/oxide diodes are then expected not only to exhibit a better control of the switching properties but also to have superior endurance as compared to oxide-only based memristors. In this feature we will show that the semiconducting polymer not only acts as a current-limiting series resistance but that the polymer also plays a crucial role by providing a charged layer of trapped electrons at the polymer/oxide interface. This charge layer enhances the tunneling across the oxide and tunes the formation of electrically bistable defects.

This contribution is an explanatory account of electroforming and unipolar switching in MIM diodes with an internal bilayer structure consisting of Al2 O3 and a semiconducting polymer and is organized as follows. In Section 2 we describe investigations into the trapping of charges in pristine diodes and the dielectric breakdown and electroforming that occurs at high bias. In Section 3 we discuss the filamentary nature of the conduction in the diodes and the experimental evidence for this heterogeneous conduction from noise measurements. Finally, Section 4 is devoted to the switching process in the electroformed diodes.

sweeping the bias voltage over the forward bias range, a much large hysteresis is observed. When the voltage is swept over a certain range for the first time, a very large capacitance is obtained, which we denote *C*oxide. Scanning the voltage over the same range but now either in the reverse direction or for a second time in the same direction, the capacitance measured is

first scans, we note that under forward bias electrons can be injected into the semiconducting polymer. These electrons can migrate through the polymer layer under the influence of the applied bias and subsequently get trapped at the polymer/oxide interface. The trap sites are relatively deep, and spontaneous detrapping of the electrons is found to occur on the time scale of days. Detrapping of electrons can be accelerated by illumination with light of photon

By varying the thickness of the oxide layer, it can be shown that the anomalous capacitance is inversely proportional to the thickness of the oxide [18, 19]. From the QSCV and optical detrapping experiments [20], it follows that the density of trap sites at the interface exceeds 10<sup>17</sup> m−2. Due to the accumulation of electrons at the polymer/oxide interface, the potential difference applied to the diodes as a whole mainly drops over the oxide layer. When increasing the bias voltage over the diode, one will eventually come to a point where the electric field in the oxide exceeds the critical field strength for electrical breakdown, which is estimated at 10<sup>9</sup> V/m for

 [21]. This could lead to catastrophic failure of the diode. In the case of the polymer/ oxide diodes, however, the layer of semiconducting polymer acts as current-limiting element,

A subtle way of inducing "soft" electrical breakdown in the polymer/oxide diodes is to subject the structure to so-called constant current stress [22]. This is illustrated in **Figure 3**. In the

voltage needed to maintain this current is monitored over time. As can be seen, the voltage that needs to be applied builds up rather quickly over the course of less than a second. This time scale corresponds to complete filling of the trap sites in the diode. When the voltage over the 10-nm-thick oxide reaches 10 V, the critical dielectric strength of the aluminum oxide exceeds, and a sudden, "soft" breakdown occurs. The dielectric breakdown allows the current

An intriguing aspect of the "soft" dielectric breakdown shown in **Figure 3** is that the damaged insulator shows spontaneous repair. This "self-healing" is illustrated in **Figure 4**. When monitoring the leakage current through the damaged diode at a relative low applied bias voltage, one finds that the current decreases over time, following a power-law decay. Curiously, the self-healing can be temporarily inhibited, by first emptying the trap sites optically and then keeping the diode at short circuit. After 25 h, the self-healing process can be reactivated by refilling the traps and proceeds with the same kinetics as in the case without inhibition.

The dielectric breakdown under constant current stress has been investigated in more detail. We find that when the electrical power that is dissipated during the breakdown is limited to

breakdown and the subsequent self-healing to quasi-reversible formation of oxygen vacancy

, the breakdown is fully reversible. In a tentative explanation, we attribute the

particular example shown, the diode is subjected to a constant current of 1 μA/cm2

through the diode to be maintained at much lower applied bias (*V* < 1 V).

energy above the bandgap of the semiconducting polymer (3.1 eV).

preventing complete or "hard" breakdown of the diodes.

. To account for the anomalously high capacitance values in the

Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories

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97

, and the

low and practically equal to *C*<sup>0</sup>

Al2 O3

0.1 mW/cm2

## **2. Charge trapping and electroforming**

Pristine diodes consisting of an Al/Al2 O3 /polyspirofluorene/Ba/Al stack have a large density of empty trap sites for electrons which are located at the interface between the semiconducting polymers. The trap sites can be studied by quasi-static capacitance-voltage (QSCV) measurements [17] and optical detrapping investigations. These measurements provide information on the position and number density of the trap sites.

The QSCV method is ideally suited to study traps that fill quickly but empty slowly. During the measurement, the bias voltage is swept over a certain voltage range and by integrating the current; one keeps track of the number of charges that enter the diode. From the voltage and charge, the capacitance is calculated. **Figure 2** shows the cyclic QSCV scans. First, the voltage is swept over the reverse bias range (V < 0). In this range a practically constant capacitance of 30 nF/cm2 is recorded which we interpret as the geometrical capacitance, *C*<sup>0</sup> . The minor hysteresis in the reverse bias range is due to a small leakage current. When subsequently

**Figure 2.** Sequential QSCV characteristics for a Al/Al2 O3 (40 nm)/polymer(80 nm)/Ba/Al diode measured using an integration time of 4 s and a voltage step of 100 mV. For negative bias voltage V, no charge is injected into the polymer. Both oxide and polymer act as insulators. For positive bias, electrons are injected into the polymer and trapped near the polymer/oxide interface.

sweeping the bias voltage over the forward bias range, a much large hysteresis is observed. When the voltage is swept over a certain range for the first time, a very large capacitance is obtained, which we denote *C*oxide. Scanning the voltage over the same range but now either in the reverse direction or for a second time in the same direction, the capacitance measured is low and practically equal to *C*<sup>0</sup> . To account for the anomalously high capacitance values in the first scans, we note that under forward bias electrons can be injected into the semiconducting polymer. These electrons can migrate through the polymer layer under the influence of the applied bias and subsequently get trapped at the polymer/oxide interface. The trap sites are relatively deep, and spontaneous detrapping of the electrons is found to occur on the time scale of days. Detrapping of electrons can be accelerated by illumination with light of photon energy above the bandgap of the semiconducting polymer (3.1 eV).

and is organized as follows. In Section 2 we describe investigations into the trapping of charges in pristine diodes and the dielectric breakdown and electroforming that occurs at high bias. In Section 3 we discuss the filamentary nature of the conduction in the diodes and the experimental evidence for this heterogeneous conduction from noise measurements.

of empty trap sites for electrons which are located at the interface between the semiconducting polymers. The trap sites can be studied by quasi-static capacitance-voltage (QSCV) measurements [17] and optical detrapping investigations. These measurements provide information

The QSCV method is ideally suited to study traps that fill quickly but empty slowly. During the measurement, the bias voltage is swept over a certain voltage range and by integrating the current; one keeps track of the number of charges that enter the diode. From the voltage and charge, the capacitance is calculated. **Figure 2** shows the cyclic QSCV scans. First, the voltage is swept over the reverse bias range (V < 0). In this range a practically constant capacitance

is recorded which we interpret as the geometrical capacitance, *C*<sup>0</sup>

hysteresis in the reverse bias range is due to a small leakage current. When subsequently

O3

integration time of 4 s and a voltage step of 100 mV. For negative bias voltage V, no charge is injected into the polymer. Both oxide and polymer act as insulators. For positive bias, electrons are injected into the polymer and trapped near the

/polyspirofluorene/Ba/Al stack have a large density

(40 nm)/polymer(80 nm)/Ba/Al diode measured using an

. The minor

Finally, Section 4 is devoted to the switching process in the electroformed diodes.

O3

**2. Charge trapping and electroforming**

on the position and number density of the trap sites.

**Figure 2.** Sequential QSCV characteristics for a Al/Al2

polymer/oxide interface.

Pristine diodes consisting of an Al/Al2

96 Memristor and Memristive Neural Networks

of 30 nF/cm2

By varying the thickness of the oxide layer, it can be shown that the anomalous capacitance is inversely proportional to the thickness of the oxide [18, 19]. From the QSCV and optical detrapping experiments [20], it follows that the density of trap sites at the interface exceeds 10<sup>17</sup> m−2.

Due to the accumulation of electrons at the polymer/oxide interface, the potential difference applied to the diodes as a whole mainly drops over the oxide layer. When increasing the bias voltage over the diode, one will eventually come to a point where the electric field in the oxide exceeds the critical field strength for electrical breakdown, which is estimated at 10<sup>9</sup> V/m for Al2 O3 [21]. This could lead to catastrophic failure of the diode. In the case of the polymer/ oxide diodes, however, the layer of semiconducting polymer acts as current-limiting element, preventing complete or "hard" breakdown of the diodes.

A subtle way of inducing "soft" electrical breakdown in the polymer/oxide diodes is to subject the structure to so-called constant current stress [22]. This is illustrated in **Figure 3**. In the particular example shown, the diode is subjected to a constant current of 1 μA/cm2 , and the voltage needed to maintain this current is monitored over time. As can be seen, the voltage that needs to be applied builds up rather quickly over the course of less than a second. This time scale corresponds to complete filling of the trap sites in the diode. When the voltage over the 10-nm-thick oxide reaches 10 V, the critical dielectric strength of the aluminum oxide exceeds, and a sudden, "soft" breakdown occurs. The dielectric breakdown allows the current through the diode to be maintained at much lower applied bias (*V* < 1 V).

An intriguing aspect of the "soft" dielectric breakdown shown in **Figure 3** is that the damaged insulator shows spontaneous repair. This "self-healing" is illustrated in **Figure 4**. When monitoring the leakage current through the damaged diode at a relative low applied bias voltage, one finds that the current decreases over time, following a power-law decay. Curiously, the self-healing can be temporarily inhibited, by first emptying the trap sites optically and then keeping the diode at short circuit. After 25 h, the self-healing process can be reactivated by refilling the traps and proceeds with the same kinetics as in the case without inhibition.

The dielectric breakdown under constant current stress has been investigated in more detail. We find that when the electrical power that is dissipated during the breakdown is limited to 0.1 mW/cm2 , the breakdown is fully reversible. In a tentative explanation, we attribute the breakdown and the subsequent self-healing to quasi-reversible formation of oxygen vacancy

**Figure 3.** Breakdown under constant current stress. The voltage across the Al/Al2 O3 (20 nm)/polyspirofluorene(80 nm)Ba/ Al capacitor as a function of time under a constant current stress of 1 μA/cm2 . An abrupt voltage drop is observed at 10 V. The inset shows the corresponding change in capacitance estimated from the change in slope of the voltage.

empty space left by the oxygen anion. When the electron leaves the vacancy, the *F*-center is

, and the superoxide ion, O2− are presented by the lemniscates. The first electrons are trapped at the polymer/ oxide interface. When the bias is larger than the flat band voltage, holes are injected into the oxide, and a highly polarized electric double layer is formed at the polymer/oxide interface. In dielectric breakdown oxygen vacancies, F-centers are formed. In self-healing, superoxide ions, O2−, react with a neutral and charged oxygen vacancy to reform a defect-free

Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories

http://dx.doi.org/10.5772/intechopen.69023

diffuse into the polymer layer, escape from the electroformed device, or even form oxygen interstitials, depending on the dissipated power used in the electroforming. As long as the

molecules formed in the breakdown process remain close to the interface, we expect the

electrons. The formed superoxide ions, O2−, react with a neutral and charged oxygen vacancy

We note that binding of neutral molecular oxygen to *n*-type metal oxides is a process that occurs in mainly oxides [16, 24, 25], allowing one to monitor oxygen partial pressure through measurement of the electrical resistance. Reversible, electrically induced formation of anion vacancy sites (*F*-center) in ionic-wide bandgap semiconductors has also been demonstrated

As mentioned above, when the power dissipated during the electrical breakdown is high, the process becomes irreversible, and the diodes are electroformed. We find that the electrical resistance of the electroformed diodes can be switched reversibly by applying voltage pulses.

The electrical current in memristor devices is not homogeneous but transported through localized paths or filaments. Evidences have been provided by scanning probe measurement

molecules may

lattice. Neutral

99

O3

molecules trap

+ O2<sup>−</sup> → □ (1)

ionized (*F*+). The ionized *F*+ center can be regarded as a trapped hole. The O2

**Figure 5.** Self-healing mechanism. The hatched and filled spheres represent Al3+ and O2− ions of the Al2

breakdown to be reversible [23]. Due to their large electronegativity, the O2

lattice, indicated by the open square, as

O2

Al2 O3 lattice.

oxygen, O2

to a defect-free Al2

O3

F+ + F+

for alkali halide-polymer diodes [26–29].

**3. Filamentary conduction and noise measurements**

sites in the oxide near the polymer/oxide interface. This mechanism is described in **Figure 5**. Upon injection of positive charge carriers into the oxide, two oxygen ions dimerize into an O2 molecule, whereby the electrons are annihilated by the trapped holes. The oxygen vacancies, also referred to as *F*-centers, can exist in a charge neutral state where an electron occupies the

**Figure 4.** Inhibition of self-healing. Current-time plots for a capacitor electroformed with constant low current stress of 1 μA. (a) The post-breakdown current probed at 0.5 V bias. The current decays with a power-law dependence on time. (b) The current decay in the same electroformed but now after emptying electron traps with 1000 s illumination with a blue LED (350 ≤ *λ* ≤ 650 nm, *λ*max = 440 nm). After *t* = 25 h triggers, the self-healing process can be reactivated by application of a brief 0–5V voltage ramp to refill the traps.

**Figure 5.** Self-healing mechanism. The hatched and filled spheres represent Al3+ and O2− ions of the Al2 O3 lattice. Neutral oxygen, O2 , and the superoxide ion, O2− are presented by the lemniscates. The first electrons are trapped at the polymer/ oxide interface. When the bias is larger than the flat band voltage, holes are injected into the oxide, and a highly polarized electric double layer is formed at the polymer/oxide interface. In dielectric breakdown oxygen vacancies, F-centers are formed. In self-healing, superoxide ions, O2−, react with a neutral and charged oxygen vacancy to reform a defect-free Al2 O3 lattice.

empty space left by the oxygen anion. When the electron leaves the vacancy, the *F*-center is ionized (*F*+). The ionized *F*+ center can be regarded as a trapped hole. The O2 molecules may diffuse into the polymer layer, escape from the electroformed device, or even form oxygen interstitials, depending on the dissipated power used in the electroforming. As long as the O2 molecules formed in the breakdown process remain close to the interface, we expect the breakdown to be reversible [23]. Due to their large electronegativity, the O2 molecules trap electrons. The formed superoxide ions, O2−, react with a neutral and charged oxygen vacancy to a defect-free Al2 O3 lattice, indicated by the open square, as

$$\rm{F}^{+} + \rm{F}^{+} + \rm{O}^{2-} \rightarrow \rm{\tiny\tiny\tiny\tag{1}}$$

We note that binding of neutral molecular oxygen to *n*-type metal oxides is a process that occurs in mainly oxides [16, 24, 25], allowing one to monitor oxygen partial pressure through measurement of the electrical resistance. Reversible, electrically induced formation of anion vacancy sites (*F*-center) in ionic-wide bandgap semiconductors has also been demonstrated for alkali halide-polymer diodes [26–29].

As mentioned above, when the power dissipated during the electrical breakdown is high, the process becomes irreversible, and the diodes are electroformed. We find that the electrical resistance of the electroformed diodes can be switched reversibly by applying voltage pulses.

### **3. Filamentary conduction and noise measurements**

sites in the oxide near the polymer/oxide interface. This mechanism is described in **Figure 5**. Upon injection of positive charge carriers into the oxide, two oxygen ions dimerize into an O2 molecule, whereby the electrons are annihilated by the trapped holes. The oxygen vacancies, also referred to as *F*-centers, can exist in a charge neutral state where an electron occupies the

**Figure 4.** Inhibition of self-healing. Current-time plots for a capacitor electroformed with constant low current stress of 1 μA. (a) The post-breakdown current probed at 0.5 V bias. The current decays with a power-law dependence on time. (b) The current decay in the same electroformed but now after emptying electron traps with 1000 s illumination with a blue LED (350 ≤ *λ* ≤ 650 nm, *λ*max = 440 nm). After *t* = 25 h triggers, the self-healing process can be reactivated by

The inset shows the corresponding change in capacitance estimated from the change in slope of the voltage.

O3

(20 nm)/polyspirofluorene(80 nm)Ba/

. An abrupt voltage drop is observed at 10 V.

**Figure 3.** Breakdown under constant current stress. The voltage across the Al/Al2

Al capacitor as a function of time under a constant current stress of 1 μA/cm2

98 Memristor and Memristive Neural Networks

application of a brief 0–5V voltage ramp to refill the traps.

The electrical current in memristor devices is not homogeneous but transported through localized paths or filaments. Evidences have been provided by scanning probe measurement which confirm the existence of conducting filaments in Al<sup>2</sup> O3 [30, 31] and by an IR-enhanced CCD camera [32]. The spatially resolved thermal images show, in the on-state, hot spots due to highly conductive paths. In the off-state, the spots disappear. However, the spots are not created and destroyed upon switching. Upon repeated switching between the on- and off-states, the same original hot spots were detected in the thermal image. From these observations it has been concluded that upon switching, filaments are neither generated nor destroyed but that individual filaments are turned on and off, like switches.

This mechanism is a switching-on and switching-off of conducting channels, at the Al<sup>2</sup>

records show large discrete current fluctuations that can reach about 45 nA.

The current fluctuations change their frequency in a random way.

random telegraph noise (RTN).

the COMSOL Multiphysics simulator.

after the start of the measurements (elapsed time).

can occur.

tact. That process dominates the 1/*f* spectrum and the observed slope of the spectrum (1/*f*

Finally, very near to the onset of the NDR region, the noise shows discrete fluctuations like a

Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories

Typical time traces from a continuous measurement are presented in **Figure 7**. The time

Discrete fluctuations in current-voltage or current-time characteristics appear when charge transport is controlled by the statistical capture/emission of electrons at electron trap sites. Especially when transport occurs through current-carrying filaments, large current fluctuations

The large discrete current fluctuations allow us to quantify the time that a filament is turned on, *τ*on, and turned off, *τ*off. The first and second traces in **Figure 7** exhibit a filamentary path that is most of the time active and only once in a while switches off, with *τ*off *~* 0.7 ms. The third trace shows the filament being turned on and turned off at similar time scales of about 1.7 ms.

**Slow response upon repeating switching**. When a memory device is in a high conductive state, there is a large ensemble of filaments. We will show here that when filaments are in relatively close proximity, the switching-on and switching-off of an individual filament not be a totally independent of a filament in the neighborhood. Filaments can interact with each other and contribute to turn on more filaments or even promote a cascade of switching-off events. It is instructive at this point to investigate the changes in potential distribution and current flow patterns in the diode in the vicinity of a conducting filament. This was achieved using

In **Figure 8** the device is represented by a simple two-layer structure composed of a thin, high-resistivity oxide layer supporting a thicker, more conductive polymer layer. The color (online) maps represent the potential distributions (blue = −10 V, pink = 0 V) which are further emphasized by superimposed contour lines. In (a) the device is in the off-state; leakage current

**Figure 7.** Electrical noise of a memristor programmed in the on-state at *T*= 220 K. The time traces show the current RTN fluctuations under an applied bias near the onset of the NDR region. The time traces were recorded at different times

O3 con-

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3/2).

101

Relevant information about filament properties is obtained from a detailed electrical characterization. In oxide-/polymer-based memristors, three different behaviors are directly caused by filamentary conduction:


In the next paragraphs, we discuss in detail all the electrical characteristics caused by filamentary conduction.

**Electrical noise**. Polymer/oxide memristor devices when operating in the on-state show different types of electrical noise depending on the bias point of the I-V curve where it is recorded [33]. For a bias of 0.5 V (ohmic region), the noise follows the 1/*f* dependence (see **Figure 6**). When the diode is biased at higher voltages, in a space-charge-limited (SCL) region, the noise follows a 1/*f* 3/2 dependence. Hence, a new physical mechanism becomes active at high bias.

**Figure 6.** Current noise spectrum in the transition from ohmic to SCL region, indicating a diffusion mechanism at higher bias.

This mechanism is a switching-on and switching-off of conducting channels, at the Al<sup>2</sup> O3 contact. That process dominates the 1/*f* spectrum and the observed slope of the spectrum (1/*f* 3/2). Finally, very near to the onset of the NDR region, the noise shows discrete fluctuations like a random telegraph noise (RTN).

which confirm the existence of conducting filaments in Al<sup>2</sup>

individual filaments are turned on and off, like switches.

by filamentary conduction:

100 Memristor and Memristive Neural Networks

conduction.

follows a 1/*f*

O3

CCD camera [32]. The spatially resolved thermal images show, in the on-state, hot spots due to highly conductive paths. In the off-state, the spots disappear. However, the spots are not created and destroyed upon switching. Upon repeated switching between the on- and off-states, the same original hot spots were detected in the thermal image. From these observations it has been concluded that upon switching, filaments are neither generated nor destroyed but that

Relevant information about filament properties is obtained from a detailed electrical characterization. In oxide-/polymer-based memristors, three different behaviors are directly caused

**a. Electrical noise**: Filaments cause discrete current fluctuations that generate random tel-

**b. Slow response upon repeating switching**: Filaments interact with nearby filaments, and

**c. Anomalous temperature dependence of the current**: The mechanism to turn on filaments

In the next paragraphs, we discuss in detail all the electrical characteristics caused by filamentary

**Electrical noise**. Polymer/oxide memristor devices when operating in the on-state show different types of electrical noise depending on the bias point of the I-V curve where it is recorded [33]. For a bias of 0.5 V (ohmic region), the noise follows the 1/*f* dependence (see **Figure 6**). When the diode is biased at higher voltages, in a space-charge-limited (SCL) region, the noise

**Figure 6.** Current noise spectrum in the transition from ohmic to SCL region, indicating a diffusion mechanism at higher bias.

3/2 dependence. Hence, a new physical mechanism becomes active at high bias.

egraph like noise and affect the memory reproducibility and scalability.

this interaction may slow down the switching speed of a memory device.

may lead to a counter-intuitive temperature dependence of the current.

[30, 31] and by an IR-enhanced

Typical time traces from a continuous measurement are presented in **Figure 7**. The time records show large discrete current fluctuations that can reach about 45 nA.

Discrete fluctuations in current-voltage or current-time characteristics appear when charge transport is controlled by the statistical capture/emission of electrons at electron trap sites. Especially when transport occurs through current-carrying filaments, large current fluctuations can occur.

The large discrete current fluctuations allow us to quantify the time that a filament is turned on, *τ*on, and turned off, *τ*off. The first and second traces in **Figure 7** exhibit a filamentary path that is most of the time active and only once in a while switches off, with *τ*off *~* 0.7 ms. The third trace shows the filament being turned on and turned off at similar time scales of about 1.7 ms. The current fluctuations change their frequency in a random way.

**Slow response upon repeating switching**. When a memory device is in a high conductive state, there is a large ensemble of filaments. We will show here that when filaments are in relatively close proximity, the switching-on and switching-off of an individual filament not be a totally independent of a filament in the neighborhood. Filaments can interact with each other and contribute to turn on more filaments or even promote a cascade of switching-off events.

It is instructive at this point to investigate the changes in potential distribution and current flow patterns in the diode in the vicinity of a conducting filament. This was achieved using the COMSOL Multiphysics simulator.

In **Figure 8** the device is represented by a simple two-layer structure composed of a thin, high-resistivity oxide layer supporting a thicker, more conductive polymer layer. The color (online) maps represent the potential distributions (blue = −10 V, pink = 0 V) which are further emphasized by superimposed contour lines. In (a) the device is in the off-state; leakage current

**Figure 7.** Electrical noise of a memristor programmed in the on-state at *T*= 220 K. The time traces show the current RTN fluctuations under an applied bias near the onset of the NDR region. The time traces were recorded at different times after the start of the measurements (elapsed time).

materials decreases with increasing temperature: a relevant example is soft breakdown in SiO<sup>2</sup> films a few nanometers thick [34]. We postulate that as the applied bias increases, a combination of increasing oxide field and high temperature in the vicinity of the conducting filament triggers the switching of a nearby filament. **Figure 8(d)** and **(e)** shows that the region of disturbed potential and high current density now expands triggering further switching. This process is expected to continue until two local hot spots overlap or expansion becomes limited by the process(es) leading to the NDR. Even if further filamentary conduction is not initiated, additional thermally induced currents will flow in both the polymer and oxide leading to a

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**Anomalous temperature dependence of the current.** The I-V characteristics for the onstate show a large increase in the magnitude of the current upon lowering the temperature of the diodes. This behavior is illustrated in **Figure 9**. The increase of current is more pronounced at higher bias voltages, in the voltage range below the sharp onset of the

To further explore this unusual temperature dependence, a diode was programmed into the onstate at room temperature and then cooled down until 120 K. Meanwhile, the current transient was recorded while applying a continuous bias voltage (2 V). The magnitude of the current increases more than double in a temperature range of 200°C, as illustrated in **Figure 10**. This observation corresponds to a positive temperature coefficient (PTC) [35–37] of the electrical resistivity, α ≈ 0.01 K−1, an anomalously large value when compared with typical values for metals (α = 0.0039 K−1 for Cu). On the basis of the anomalously large PTC, it contradicts the

The large and stepwise increase in current indicates that by lowering the temperature some filaments can be activated. In the next section, we provide a tentative explanation for this

**Figure 9.** Temperature dependence of the I-V curve of a diode programmed into the on-state.

similar expansion of the hot spot.

explanations based on a metallic type of conduction.

remarkable experimental observation.

NDR.

**Figure 8.** COMSOL simulations showing potential distributions represented both in color (blue = −10 V, pink = 0 V) and by superimposed contour lines (a), (b), (d), and current streamlines (c) and (e) in our two-layer capacitor model. The upper layer represents the polymer and the lower a thin oxide film. (a) Potential distribution in a device in the HRS. The corresponding current streamlines will be vertical and of low density. The changes in potential distribution and current streamlines arising from a single conducting filament in the oxide are shown in (b) and (c). The corresponding distributions for two adjacent filaments are given in (d) and (e).

through the oxide is minimal so that virtually all the applied voltage appears across the oxide layer owing to the higher conductivity of the polymer. Next, we include a conducting filament in the oxide. This results in significant changes in the local potential (b) and in the current density profile (c). We note two important changes:


In the case of low on-currents, conducting filaments are isolated and well separated. The nonuniform potential distribution (**Figure 8(b)** and **(c)**) allows electrons to be drawn through the polymer from a relatively large area of the electrode. The critical filament current required to effect efficient recombination and turn off the filaments is achieved at relatively low voltages.

For high on-currents, a large number of conducting paths are turned on, many in the neighborhood of an originating filament as discussed above. As seen in **Figure 8(d)** and **(e)**, the electrode area from which electrons are drawn does not increase in proportion to the number of neighboring filaments. Higher voltages will be required then to provide the critical electron current through the polymer for extinguishing these filaments. Consequently, within a volume extending out from the filament into the polymer, considerable Joule heating will occur. Significantly, it is well known that the electrical breakdown strength of most insulating materials decreases with increasing temperature: a relevant example is soft breakdown in SiO<sup>2</sup> films a few nanometers thick [34]. We postulate that as the applied bias increases, a combination of increasing oxide field and high temperature in the vicinity of the conducting filament triggers the switching of a nearby filament. **Figure 8(d)** and **(e)** shows that the region of disturbed potential and high current density now expands triggering further switching. This process is expected to continue until two local hot spots overlap or expansion becomes limited by the process(es) leading to the NDR. Even if further filamentary conduction is not initiated, additional thermally induced currents will flow in both the polymer and oxide leading to a similar expansion of the hot spot.

**Anomalous temperature dependence of the current.** The I-V characteristics for the onstate show a large increase in the magnitude of the current upon lowering the temperature of the diodes. This behavior is illustrated in **Figure 9**. The increase of current is more pronounced at higher bias voltages, in the voltage range below the sharp onset of the NDR.

To further explore this unusual temperature dependence, a diode was programmed into the onstate at room temperature and then cooled down until 120 K. Meanwhile, the current transient was recorded while applying a continuous bias voltage (2 V). The magnitude of the current increases more than double in a temperature range of 200°C, as illustrated in **Figure 10**. This observation corresponds to a positive temperature coefficient (PTC) [35–37] of the electrical resistivity, α ≈ 0.01 K−1, an anomalously large value when compared with typical values for metals (α = 0.0039 K−1 for Cu). On the basis of the anomalously large PTC, it contradicts the explanations based on a metallic type of conduction.

The large and stepwise increase in current indicates that by lowering the temperature some filaments can be activated. In the next section, we provide a tentative explanation for this remarkable experimental observation.

through the oxide is minimal so that virtually all the applied voltage appears across the oxide layer owing to the higher conductivity of the polymer. Next, we include a conducting filament in the oxide. This results in significant changes in the local potential (b) and in the current

**Figure 8.** COMSOL simulations showing potential distributions represented both in color (blue = −10 V, pink = 0 V) and by superimposed contour lines (a), (b), (d), and current streamlines (c) and (e) in our two-layer capacitor model. The upper layer represents the polymer and the lower a thin oxide film. (a) Potential distribution in a device in the HRS. The corresponding current streamlines will be vertical and of low density. The changes in potential distribution and current streamlines arising from a single conducting filament in the oxide are shown in (b) and (c). The corresponding

(i) The potential at the polymer/oxide interface decreases giving rise to lateral electric fields and extensive distortion of the potential in both the polymer and oxide layers.

(ii) The current tunnels through the polymer into the filament from a circular area of the

In the case of low on-currents, conducting filaments are isolated and well separated. The nonuniform potential distribution (**Figure 8(b)** and **(c)**) allows electrons to be drawn through the polymer from a relatively large area of the electrode. The critical filament current required to effect efficient recombination and turn off the filaments is achieved at relatively low voltages. For high on-currents, a large number of conducting paths are turned on, many in the neighborhood of an originating filament as discussed above. As seen in **Figure 8(d)** and **(e)**, the electrode area from which electrons are drawn does not increase in proportion to the number of neighboring filaments. Higher voltages will be required then to provide the critical electron current through the polymer for extinguishing these filaments. Consequently, within a volume extending out from the filament into the polymer, considerable Joule heating will occur. Significantly, it is well known that the electrical breakdown strength of most insulating

density profile (c). We note two important changes:

distributions for two adjacent filaments are given in (d) and (e).

102 Memristor and Memristive Neural Networks

electrode whose radius exceeds the polymer film thickness.

**Figure 9.** Temperature dependence of the I-V curve of a diode programmed into the on-state.

**Figure 10.** Temperature dependence of the I-V curve of a diode programmed into the on-state monitored at 2 V. The cooling speed is 1 K/min.

allows current to flow at already low bias voltages. The local spots on the oxide layer where the effective work function has been altered give rise to current filamentary currents in the diode (see **Figure 12**). We note that formation of charged double layers near metal electrodes

**Figure 11.** Electroluminescence. (Upper panel) current density (J) and (lower panel) electroluminescence (EL) intensity

(10 nm)/polyfluorene (80 nm)/Ba/Al diode during a voltage

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O3

To explain the electrical bistability of the nonvolatile memories, we propose the coexistence of two thermodynamically stable phases in the electroformed oxide layer [26]. The two phases occur in the quasi-two-dimensional double layer consisting of trapped electrons in the organic semiconductor and holes trapped at defects in the metal oxide. One phase containing mainly ionized defects has a low work function. The other phase comprises mainly defects in their neutral state and has a high work function. In the diodes, domains of the phase with low work

**Figure 12.** Schematic representation of current filament. In the electroformed diode, ionizable defects are present near the oxide/organic semiconductor interface with a number density above a critical limit. Due to cooperative interaction between the defects, the diode is electrically bistable. Arrays of mainly neutral defects have a high work function and constitute the off-state. Arrays of mainly ionized defects have a low work function and constitute the on-state.

is well known in wet electrochemistry [41, 42].

recorded simultaneously for an electroformed ITO/Al2

sweep from 0 V→16 V→0 V.

function constitute current filaments.

## **4. Electroluminescence and filament model**

A key experimental observation in unraveling the mechanism of the nonvolatile electronic memory effects in aluminum oxide has been the occurrence of *electroluminescence* in the visible range of the spectrum during the switching [10, 38]. This observation provides direct experimental evidence that recombination of positive and negative charge carriers takes place at defects in the oxide. Furthermore, it has also been reported that electroformed oxide layers can emit electrons into the vacuum [11]. The latter observations show that an electroformed oxide layer on a metal can dramatically alter the work function of the underlying metal [39, 40].

In **Figure 11** we illustrate the occurrence of electroluminescence in electroformed Al2 O3 /polyfluorene diodes during switching. Starting at zero bias in the high conduction state, the current density rises rapidly with increasing bias. For voltages above 4 V, the diode shows negative differential resistance (NDR), and the current density actually decreases with increasing bias voltage. In the voltage range corresponding to the NDR behavior, the diode also shows irregular electroluminescence. Light is emitted during a series of short bursts. At high bias voltage (V > 10 V), the diodes show more steady light emission.

In order to account for the filamentary conduction and the electroluminescence, we propose that in the diode clusters of charged defects at the polymer/oxide interface are present. We propose a charged bilayer arrangement of charges with, for example, positively charged defects in the oxide compensated by trapped electrons on the polymer side of the interface. The double-layer arrangement locally changes the work function of the electrodes and

**Figure 11.** Electroluminescence. (Upper panel) current density (J) and (lower panel) electroluminescence (EL) intensity recorded simultaneously for an electroformed ITO/Al2 O3 (10 nm)/polyfluorene (80 nm)/Ba/Al diode during a voltage sweep from 0 V→16 V→0 V.

allows current to flow at already low bias voltages. The local spots on the oxide layer where the effective work function has been altered give rise to current filamentary currents in the diode (see **Figure 12**). We note that formation of charged double layers near metal electrodes is well known in wet electrochemistry [41, 42].

**4. Electroluminescence and filament model**

(V > 10 V), the diodes show more steady light emission.

metal [39, 40].

cooling speed is 1 K/min.

104 Memristor and Memristive Neural Networks

A key experimental observation in unraveling the mechanism of the nonvolatile electronic memory effects in aluminum oxide has been the occurrence of *electroluminescence* in the visible range of the spectrum during the switching [10, 38]. This observation provides direct experimental evidence that recombination of positive and negative charge carriers takes place at defects in the oxide. Furthermore, it has also been reported that electroformed oxide layers can emit electrons into the vacuum [11]. The latter observations show that an electroformed oxide layer on a metal can dramatically alter the work function of the underlying

**Figure 10.** Temperature dependence of the I-V curve of a diode programmed into the on-state monitored at 2 V. The

In **Figure 11** we illustrate the occurrence of electroluminescence in electroformed Al2

fluorene diodes during switching. Starting at zero bias in the high conduction state, the current density rises rapidly with increasing bias. For voltages above 4 V, the diode shows negative differential resistance (NDR), and the current density actually decreases with increasing bias voltage. In the voltage range corresponding to the NDR behavior, the diode also shows irregular electroluminescence. Light is emitted during a series of short bursts. At high bias voltage

In order to account for the filamentary conduction and the electroluminescence, we propose that in the diode clusters of charged defects at the polymer/oxide interface are present. We propose a charged bilayer arrangement of charges with, for example, positively charged defects in the oxide compensated by trapped electrons on the polymer side of the interface. The double-layer arrangement locally changes the work function of the electrodes and

O3 /polyTo explain the electrical bistability of the nonvolatile memories, we propose the coexistence of two thermodynamically stable phases in the electroformed oxide layer [26]. The two phases occur in the quasi-two-dimensional double layer consisting of trapped electrons in the organic semiconductor and holes trapped at defects in the metal oxide. One phase containing mainly ionized defects has a low work function. The other phase comprises mainly defects in their neutral state and has a high work function. In the diodes, domains of the phase with low work function constitute current filaments.

**Figure 12.** Schematic representation of current filament. In the electroformed diode, ionizable defects are present near the oxide/organic semiconductor interface with a number density above a critical limit. Due to cooperative interaction between the defects, the diode is electrically bistable. Arrays of mainly neutral defects have a high work function and constitute the off-state. Arrays of mainly ionized defects have a low work function and constitute the on-state.

In order to better explain the proposed thermodynamic bistability, we draw on an analogy with saturated salt solutions. Charged ions in such a system can be present in two phases, one where the ions are dispersed throughout the solutions and another phase where ions of opposite charge have condensed into a crystal. As is well, cooperative interactions between the oppositely charged ions give rise to crystallization of salt, for example, NaCl.

**5. Conclusion**

**Author details**

Unipolar switching in Al2

O3

coexistence is also low. At temperatures *T* > *T*<sup>c</sup>

on as soon as the temperature drops below the *T*<sup>c</sup>

over the now largely random process of defect formation.

3 Smart Materials, Delft University of Technology, The Netherlands

Eindhoven University of Technology, Eindhoven, The Netherlands

4 Molecular Materials and Nanosystems and Institute for Complex Molecular Systems,

Henrique L. Gomes1,2\*, Dago M. de Leeuw3

2 Universidade do Algarve, Faro, Portugal

\*Address all correspondence to: hgomes@ualg.pt 1 Instituto de Telecomunicações, Lisboa, Portugal

diodes involves defects that are created during the electroform-

Resistive Switching in Metal Oxide/Organic Semiconductor Nonvolatile Memories

http://dx.doi.org/10.5772/intechopen.69023

, phase coexistence is not possible, and the memory

associated with the locale defect density near the

for phase

107

ing step. The density of defects is critical to the memory operation. Reproducible electroforming is possible by including in the device a well-defined thin layer of a semiconducting polymer. In their pristine state, the polymer/oxide diodes are insulating. The purpose of the polymer layer is threefold. Firstly, the polymer layer acts as a current-limiting series resistance that prevents thermal runaway during electroforming. Secondly, the presence of the polymer introduces an internal polymer/oxide interface, where electrons can accumulate. The trapped electrons stabilize positively charged defects that are generated during electroforming by electrostatic interactions. The trapped electrons promote injection of holes into the oxide, yielding a soft breakdown. Molecular oxygen is expelled and oxygen vacancies are formed. The third

The experimental evidence indicates that the density of defects in the metal-insulator-metal diodes is of crucial importance to obtain a memory diode with nonvolatile memory properties. If the defect

diode does not show electrical bistability. Upon cooling down, additional filaments should switch

filament. This prediction is supported by the experiments in Section 2. Noise measurements prove a unique tool to characterize the dynamics of the defect ionization and neutralization. The onset of discrete fluctuations and random telegraph signals may serve as a diagnostic to determine the difference between the actual defect density and the desired concentration for memory operation. In summary, unipolar resistive switching poses a unique challenge to the materials that scientists design, deposit, and characterize with appropriate electronic structure, defect ordering, and internal charge carrier dynamics. This challenge seems parallel to development of, e.g., materials for high-temperature superconductivity. Fortunately, in the case of memristors, we have already the certainty from the present state of the art involving the electroforming that relatively simple materials exist with the required properties. The challenge is to gain control

and Stefan C.J. Meskers<sup>4</sup>

purpose of the polymer in the diode is to buffer the molecular oxygen formed.

density is too high, the diode will be low. If the density is too low, the critical temperature *T*<sup>c</sup>

In rock salt, the positive and negative ions are packed in a cubic lattice (see **Figure 13**). If we however cut the crystal under an oblique angle, for example, parallel to the (1 1 1) plane, one sees that the crystal actually consists of layers of oppositely charged ions.

For the electroformed oxide layers, we argue that, provided neutral defect sites which are available with sufficient density, electrical charges that have been injected into the diode may condense spontaneously at the polymer/oxide interface due to their mutual electrostatic stabilization. By detailed consideration of the Coulomb interaction potentials of the charge defects, it can be shown that also the image charges in the nearby metal electrode contribute to the stabilization. The condensation of the charges can be mapped onto the 2D Ising model. Based on the 2D Ising model, one predicts that in analogy to ferromagnetism, a critical temperature *T*<sup>c</sup> should exist. For temperatures lower than *T*<sup>c</sup> , the coexistence of two thermodynamically stable phases is predicted. One of the phases should have mainly ionized defects and the other predominantly neutral defects. The magnitude of *T*<sup>c</sup> depends on the strength of the interactions between the sites and should therefore be influenced by the density of defect states.

In order to explain the switching-off of current filaments, we argue that Joule heating associated with the current through the filaments in the oxide will cause the temperature in the oxide layer to rise locally. Once the temperature is above *T*<sup>c</sup> , the mutual stabilization of charges is compromised, and sudden massive recombination of charges occurs. This recombination may account for the bursts of electroluminescence that can be observed during the switching process (see **Figure 11**). Furthermore, recombination of charges in the oxide layer will result in changes in the effective internal work function of the electrodes. This may account for the experimental observation of changes in the built-in potential of an electroluminescent diode during electrically induced breakdown [43].

**Figure 13.** Crystal structure of rock salt (NaCl). Ions of the same charge are packed in layers that lie parallel to the (1 1 1) plane.

## **5. Conclusion**

In order to better explain the proposed thermodynamic bistability, we draw on an analogy with saturated salt solutions. Charged ions in such a system can be present in two phases, one where the ions are dispersed throughout the solutions and another phase where ions of opposite charge have condensed into a crystal. As is well, cooperative interactions between the oppositely charged ions give rise to crystallization of salt, for

In rock salt, the positive and negative ions are packed in a cubic lattice (see **Figure 13**). If we however cut the crystal under an oblique angle, for example, parallel to the (1 1 1) plane, one

For the electroformed oxide layers, we argue that, provided neutral defect sites which are available with sufficient density, electrical charges that have been injected into the diode may condense spontaneously at the polymer/oxide interface due to their mutual electrostatic stabilization. By detailed consideration of the Coulomb interaction potentials of the charge defects, it can be shown that also the image charges in the nearby metal electrode contribute to the stabilization. The condensation of the charges can be mapped onto the 2D Ising model. Based on the 2D Ising model, one predicts that in analogy to ferromagnetism,

should exist. For temperatures lower than *T*<sup>c</sup>

thermodynamically stable phases is predicted. One of the phases should have mainly ion-

the strength of the interactions between the sites and should therefore be influenced by the

In order to explain the switching-off of current filaments, we argue that Joule heating associated with the current through the filaments in the oxide will cause the temperature in the

is compromised, and sudden massive recombination of charges occurs. This recombination may account for the bursts of electroluminescence that can be observed during the switching process (see **Figure 11**). Furthermore, recombination of charges in the oxide layer will result in changes in the effective internal work function of the electrodes. This may account for the experimental observation of changes in the built-in potential of an electroluminescent diode

**Figure 13.** Crystal structure of rock salt (NaCl). Ions of the same charge are packed in layers that lie parallel to the (1 1 1)

ized defects and the other predominantly neutral defects. The magnitude of *T*<sup>c</sup>

oxide layer to rise locally. Once the temperature is above *T*<sup>c</sup>

during electrically induced breakdown [43].

, the coexistence of two

, the mutual stabilization of charges

depends on

sees that the crystal actually consists of layers of oppositely charged ions.

example, NaCl.

106 Memristor and Memristive Neural Networks

a critical temperature *T*<sup>c</sup>

density of defect states.

plane.

Unipolar switching in Al2 O3 diodes involves defects that are created during the electroforming step. The density of defects is critical to the memory operation. Reproducible electroforming is possible by including in the device a well-defined thin layer of a semiconducting polymer. In their pristine state, the polymer/oxide diodes are insulating. The purpose of the polymer layer is threefold. Firstly, the polymer layer acts as a current-limiting series resistance that prevents thermal runaway during electroforming. Secondly, the presence of the polymer introduces an internal polymer/oxide interface, where electrons can accumulate. The trapped electrons stabilize positively charged defects that are generated during electroforming by electrostatic interactions. The trapped electrons promote injection of holes into the oxide, yielding a soft breakdown. Molecular oxygen is expelled and oxygen vacancies are formed. The third purpose of the polymer in the diode is to buffer the molecular oxygen formed.

The experimental evidence indicates that the density of defects in the metal-insulator-metal diodes is of crucial importance to obtain a memory diode with nonvolatile memory properties. If the defect density is too high, the diode will be low. If the density is too low, the critical temperature *T*<sup>c</sup> for phase coexistence is also low. At temperatures *T* > *T*<sup>c</sup> , phase coexistence is not possible, and the memory diode does not show electrical bistability. Upon cooling down, additional filaments should switch on as soon as the temperature drops below the *T*<sup>c</sup> associated with the locale defect density near the filament. This prediction is supported by the experiments in Section 2. Noise measurements prove a unique tool to characterize the dynamics of the defect ionization and neutralization. The onset of discrete fluctuations and random telegraph signals may serve as a diagnostic to determine the difference between the actual defect density and the desired concentration for memory operation.

In summary, unipolar resistive switching poses a unique challenge to the materials that scientists design, deposit, and characterize with appropriate electronic structure, defect ordering, and internal charge carrier dynamics. This challenge seems parallel to development of, e.g., materials for high-temperature superconductivity. Fortunately, in the case of memristors, we have already the certainty from the present state of the art involving the electroforming that relatively simple materials exist with the required properties. The challenge is to gain control over the now largely random process of defect formation.

## **Author details**

Henrique L. Gomes1,2\*, Dago M. de Leeuw3 and Stefan C.J. Meskers<sup>4</sup>


4 Molecular Materials and Nanosystems and Institute for Complex Molecular Systems, Eindhoven University of Technology, Eindhoven, The Netherlands

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**Section 2**

**Memristor Modelling**

**Memristor Modelling**

**Chapter 6**

Provisional chapter

**Memristor Emulator Circuit Design and Applications**

DOI: 10.5772/intechopen.69291

Memristor Emulator Circuit Design and Applications

This chapter introduces a design guide of memristor emulator circuits, from conceptual idea until experimental tests. Three topologies of memristor emulator circuits in their incremental and decremental versions are analysed and designed at low and high frequency. The behavioural model of each topology is derived and programmed at SIMULINK under the MATLAB environment. An offset compensation technique is also described in order to achieve the frequency-dependent pinched hysteresis loop that is on the origin and when the memristor emulator circuit is operating at high frequency. Furthermore, from these topologies, a technique to transform normal non-linear resistors to inverse non-linear resistors is also addressed. HSPICE numerical simulations for each topology are also shown. Finally, three real analogue applications based on memristors are analysed and explained at the behavioural level of abstraction.

Keywords: memristor, pinched hysteresis loop, current conveyor, non-linear

Memristors have turned out to be of considerable importance in several areas of research and application, such as analogue circuits, non-linear (chaotic) circuits, sensors, control systems, storage systems, cellular neural networks, logic circuits, power systems, neuromorphic circuits, etc. [1]. In order to research all those applications, the first step is understanding and modelling the behaviour of a memristor. In this scenario, there are, basically, three approaches:

> © The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Carlos Sánchez-López, Illiani Carro-Pérez,

Carlos Sánchez-López, Illiani Carro-Pérez, Victor Hugo Carbajal-Gómez, Miguel Angel Carrasco-Aguilar and Francisco Epimenio

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Victor Hugo Carbajal-Gómez,

Morales-López

Abstract

1. Introduction

Miguel Angel Carrasco-Aguilar and Francisco Epimenio Morales-López

http://dx.doi.org/10.5772/intechopen.69291

resistor, behavioural modelling

Provisional chapter

## **Memristor Emulator Circuit Design and Applications** Memristor Emulator Circuit Design and Applications

DOI: 10.5772/intechopen.69291

Carlos Sánchez-López, Illiani Carro-Pérez, Victor Hugo Carbajal-Gómez, Miguel Angel Carrasco-Aguilar and Francisco Epimenio Morales-López Carlos Sánchez-López, Illiani Carro-Pérez, Victor Hugo Carbajal-Gómez, Miguel Angel Carrasco-Aguilar and Francisco Epimenio

Additional information is available at the end of the chapter Morales-López

http://dx.doi.org/10.5772/intechopen.69291 Additional information is available at the end of the chapter

#### Abstract

This chapter introduces a design guide of memristor emulator circuits, from conceptual idea until experimental tests. Three topologies of memristor emulator circuits in their incremental and decremental versions are analysed and designed at low and high frequency. The behavioural model of each topology is derived and programmed at SIMULINK under the MATLAB environment. An offset compensation technique is also described in order to achieve the frequency-dependent pinched hysteresis loop that is on the origin and when the memristor emulator circuit is operating at high frequency. Furthermore, from these topologies, a technique to transform normal non-linear resistors to inverse non-linear resistors is also addressed. HSPICE numerical simulations for each topology are also shown. Finally, three real analogue applications based on memristors are analysed and explained at the behavioural level of abstraction.

Keywords: memristor, pinched hysteresis loop, current conveyor, non-linear resistor, behavioural modelling

#### 1. Introduction

Memristors have turned out to be of considerable importance in several areas of research and application, such as analogue circuits, non-linear (chaotic) circuits, sensors, control systems, storage systems, cellular neural networks, logic circuits, power systems, neuromorphic circuits, etc. [1]. In order to research all those applications, the first step is understanding and modelling the behaviour of a memristor. In this scenario, there are, basically, three approaches:

© The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

behavioural modelling, SPICE type models and emulator circuits. In the former case, smooth continuous cubic non-linear functions [2], square non-linear functions [3], piecewise linear models [4] and hyperbolic sine models [5, 6] have been proposed to emulate the Hewlett-Packard (HP) memristor behaviour. Examples of this type of modelling are TEAM model [7], VTEM model [8] and Simmons tunnelling model [9]. Although these models are approaching the HP memristor behaviour with a level of error relatively low, a full custom software is required for solving the mathematical models [10]. Furthermore, this task becomes cumbersome when applications with several memristors are addressed, since a large set of equations must first be established according to the topology, and next, the system of equations must be numerically solved. In the second approach, SPICE models have also been developed in order to model the HP memristor, principally [11–16]. It is worth mentioning that the memristive effect is not limited to TiO2, and this effect has also been glimpsed on nickel oxide [1], Ag-loaded Si films [17], TiO2 sol-gel solutions [18], and other materials. Although this type of modelling is interesting, since the capabilities of commercially available tools are exploited, its major disadvantage is that numerical simulations of circuits based on memristors can only be done. In the latter, several emulator circuits have been proposed in the literature, which use different design methodologies and different topologies. In this way, grounded and floating memristor emulator circuits working at incremental or decremental mode and built with operational amplifiers and analogue multipliers have been proposed in [19–24]. Other interesting topologies were reported in [25, 26], where digital and analogue mixed circuits were used. More recently, other active devices such as current feedback operational amplifiers, positive second-generation current conveyors (CCII+) and differential difference current conveyor, see [27–33] and the references cited therein, have also been used to design a memristor emulator circuit. However, some of them not only become complex and bulky, requiring rigid conditions to operate, but also some emulators do not exhibit those fingerprints that are useful to affirm that the emulator circuit is a memristor or memristive device. With this in mind and depending on the application, any emulator circuit must accomplish some properties, some of them are: the frequency-dependent pinched hysteresis loop for any kind of flux- or charge-controlled incremental or decremental memristor/memductor, in its version grounded or floating, must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions; the possibility for controlling the initial state of the emulator circuit, i.e. adjust of the initial conditions, non-volatility, memristive/memductive behaviour at high-frequency and without offset, etc. All in all, the design of memristor emulator circuits is also important in order to study and research real applications as those mentioned above. As a consequence, a lot of emulator circuits using off-the-shelf components have been developed to imitate not only the real behaviour of a memristor but also the real behaviour of meminductors and memcapacitors [1].

crossing point does not deviate of the origin. Since a memristor is basically a charge- or fluxcontrolled resistor, we describe how to transform a non-linear resistor with its normal pinched hysteresis loop to an inverse behaviour. Therefore, the main difference of an inverse non-linear resistor with respect to normal resistors is that the behaviour of frequency-dependent pinched hysteresis loop becomes a straight line when the operating frequency of the signal source

Unlike behavioural models and SPICE type models, an emulator circuit is very useful, since real applications based on memristors can be researched and built. In this section, we describe

The topology shown in Figure 1(a) was reported in [28]. By a straightforward analysis, the

From Figure 1(a), the S switch is connected to I to obtain a memristor emulator circuit operating at incremental mode, whereas if S is connected to D, then a decremental behaviour is obtained.

> R1R4A<sup>m</sup> 10R2R3Czω

From Eq. (2), one can observe that the memristance is composed by a linear time-invariant resistor and a linear time-varying resistor. The relationship between both resistors is described

<sup>R</sup>2R3Czω<sup>10</sup> <sup>¼</sup> <sup>1</sup>

<sup>R</sup>4A<sup>m</sup> is the time constant of the emulator circuit and <sup>T</sup> <sup>¼</sup> <sup>1</sup>

vm(t). In order to hold the pinched hysteresis loop in several operating frequencies, one can observe in Eq. (3) that τ must be updated according to f, since k<sup>n</sup> will decrease as the frequency increases. Thus, the numeric value of τ can be updated by R<sup>3</sup> or Cz. On the other hand, Eq. (3)

1. k<sup>n</sup> ! 0 when f ! ∞ or A<sup>m</sup> ! 0. Hence, Eq. (1) is dominated by its linear time-invariant

<sup>τ</sup><sup>f</sup> <sup>¼</sup> <sup>T</sup>

These behaviours correspond to the signs + and � at Eq. (1), respectively. Assuming that

vm(t) = Amsin(ωt), where A<sup>m</sup> is the amplitude and ω = 2 πf in rad/s, we obtain:

<sup>k</sup><sup>n</sup> <sup>¼</sup> <sup>R</sup>4A<sup>m</sup>

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

R1R<sup>4</sup> 10R2R3Cz ðt 0

vmðτÞdτ ð1Þ

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 117

cosðωt � πÞ ð2Þ

<sup>τ</sup> <sup>ð</sup>3<sup>Þ</sup>

<sup>f</sup> is the period of

decreases. Finally, some real analogue applications are described.

2. Analogue memristor emulators

2.1. Floating memristor emulator circuit

by the ratio of their amplitudes, given as

where <sup>τ</sup> <sup>¼</sup> <sup>20</sup>πR2R3C<sup>z</sup>

reveals that:

part.

vmðtÞ

<sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>M</sup>ðφmðtÞÞ ¼ <sup>R</sup><sup>1</sup> �

three memristor emulator circuits.

behaviour equation is given by:

In this chapter, we discuss the design of three memristor emulator circuits. The aim is to show the conceptual idea on the design of an emulator, passing for numerical simulations and until experimental tests. Each behavioural model is derived and programmed at SIMULINK under MATLAB environment. From a circuit-design perspective and of the knowledge gained, a design guide is described in order to design a memristor emulator circuit in a systematic way. Then, we introduce a novel technique for achieving the frequency-dependent pinched hysteresis loop associated to a memristor emulator circuit that is operating at high frequency, and the crossing point does not deviate of the origin. Since a memristor is basically a charge- or fluxcontrolled resistor, we describe how to transform a non-linear resistor with its normal pinched hysteresis loop to an inverse behaviour. Therefore, the main difference of an inverse non-linear resistor with respect to normal resistors is that the behaviour of frequency-dependent pinched hysteresis loop becomes a straight line when the operating frequency of the signal source decreases. Finally, some real analogue applications are described.

### 2. Analogue memristor emulators

behavioural modelling, SPICE type models and emulator circuits. In the former case, smooth continuous cubic non-linear functions [2], square non-linear functions [3], piecewise linear models [4] and hyperbolic sine models [5, 6] have been proposed to emulate the Hewlett-Packard (HP) memristor behaviour. Examples of this type of modelling are TEAM model [7], VTEM model [8] and Simmons tunnelling model [9]. Although these models are approaching the HP memristor behaviour with a level of error relatively low, a full custom software is required for solving the mathematical models [10]. Furthermore, this task becomes cumbersome when applications with several memristors are addressed, since a large set of equations must first be established according to the topology, and next, the system of equations must be numerically solved. In the second approach, SPICE models have also been developed in order to model the HP memristor, principally [11–16]. It is worth mentioning that the memristive effect is not limited to TiO2, and this effect has also been glimpsed on nickel oxide [1], Ag-loaded Si films [17], TiO2 sol-gel solutions [18], and other materials. Although this type of modelling is interesting, since the capabilities of commercially available tools are exploited, its major disadvantage is that numerical simulations of circuits based on memristors can only be done. In the latter, several emulator circuits have been proposed in the literature, which use different design methodologies and different topologies. In this way, grounded and floating memristor emulator circuits working at incremental or decremental mode and built with operational amplifiers and analogue multipliers have been proposed in [19–24]. Other interesting topologies were reported in [25, 26], where digital and analogue mixed circuits were used. More recently, other active devices such as current feedback operational amplifiers, positive second-generation current conveyors (CCII+) and differential difference current conveyor, see [27–33] and the references cited therein, have also been used to design a memristor emulator circuit. However, some of them not only become complex and bulky, requiring rigid conditions to operate, but also some emulators do not exhibit those fingerprints that are useful to affirm that the emulator circuit is a memristor or memristive device. With this in mind and depending on the application, any emulator circuit must accomplish some properties, some of them are: the frequency-dependent pinched hysteresis loop for any kind of flux- or charge-controlled incremental or decremental memristor/memductor, in its version grounded or floating, must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions; the possibility for controlling the initial state of the emulator circuit, i.e. adjust of the initial conditions, non-volatility, memristive/memductive behaviour at high-frequency and without offset, etc. All in all, the design of memristor emulator circuits is also important in order to study and research real applications as those mentioned above. As a consequence, a lot of emulator circuits using off-the-shelf components have been developed to imitate not only the real behaviour of a memristor but also the real behaviour of meminductors

In this chapter, we discuss the design of three memristor emulator circuits. The aim is to show the conceptual idea on the design of an emulator, passing for numerical simulations and until experimental tests. Each behavioural model is derived and programmed at SIMULINK under MATLAB environment. From a circuit-design perspective and of the knowledge gained, a design guide is described in order to design a memristor emulator circuit in a systematic way. Then, we introduce a novel technique for achieving the frequency-dependent pinched hysteresis loop associated to a memristor emulator circuit that is operating at high frequency, and the

and memcapacitors [1].

116 Memristor and Memristive Neural Networks

Unlike behavioural models and SPICE type models, an emulator circuit is very useful, since real applications based on memristors can be researched and built. In this section, we describe three memristor emulator circuits.

#### 2.1. Floating memristor emulator circuit

The topology shown in Figure 1(a) was reported in [28]. By a straightforward analysis, the behaviour equation is given by:

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = M(\varphi\_{\rm m}(t)) = R\_1 \pm \frac{R\_1 R\_4}{10 R\_2 R\_3 C\_z} \int\_0^t v\_{\rm m}(\tau) d\tau \tag{1}$$

From Figure 1(a), the S switch is connected to I to obtain a memristor emulator circuit operating at incremental mode, whereas if S is connected to D, then a decremental behaviour is obtained. These behaviours correspond to the signs + and � at Eq. (1), respectively. Assuming that

vm(t) = Amsin(ωt), where A<sup>m</sup> is the amplitude and ω = 2 πf in rad/s, we obtain:

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_1 R\_4 A\_{\rm m}}{10 R\_2 R\_3 C\_{\rm x} \omega} \cos(\omega t - \pi) \tag{2}$$

From Eq. (2), one can observe that the memristance is composed by a linear time-invariant resistor and a linear time-varying resistor. The relationship between both resistors is described by the ratio of their amplitudes, given as

$$k\_n = \frac{R\_4 A\_m}{R\_2 R\_3 C\_z \omega 10} = \frac{1}{\tau f} = \frac{T}{\tau} \tag{3}$$

where <sup>τ</sup> <sup>¼</sup> <sup>20</sup>πR2R3C<sup>z</sup> <sup>R</sup>4A<sup>m</sup> is the time constant of the emulator circuit and <sup>T</sup> <sup>¼</sup> <sup>1</sup> <sup>f</sup> is the period of vm(t). In order to hold the pinched hysteresis loop in several operating frequencies, one can observe in Eq. (3) that τ must be updated according to f, since k<sup>n</sup> will decrease as the frequency increases. Thus, the numeric value of τ can be updated by R<sup>3</sup> or Cz. On the other hand, Eq. (3) reveals that:

1. k<sup>n</sup> ! 0 when f ! ∞ or A<sup>m</sup> ! 0. Hence, Eq. (1) is dominated by its linear time-invariant part.

2. k<sup>n</sup> ! 1 when f ! 1/τ or A<sup>m</sup> is monotonically increased. Therefore, the maximum pinched hysteresis loop is obtained.

Figure 1(a) was also simulated at HSPICE by using the macro-models associated to each active device and numerical results are shown in Figure 2(a) (dash-dot line). In order to validate the previous results, Figure 1(a) was experimentally tested, and the results are shown in Figure 2(a) (dot-dash line). On the other hand, when the operating frequency increases, the pinched hysteresis loop is gradually lost and the memristor behaviour becomes a straight line for all cases, as depicted in Figure 2(b). Furthermore, the frequency-dependent pinched hysteresis loop is a necessary condition but not sufficient for claiming that the emulator circuit is emulating the real memristor behaviour. In this case, tests of non-volatility are necessary. Since capacitors and inductors are the solely elements that are storing energy, the non-volatility property is indirectly measured across C<sup>z</sup> of Figure 1(a). Thus, Figure 3 shows experimental tests of non-volatility of Figure 1(a) when a narrow pulse train of 1.2 V of amplitude and 2.4 μs of pulse width (yellow line) is applied. According to Figure 3, one can observe that once programmed the incremental and decremental memristance, its value is keeping when the input signal is not applied. Note that during non-pulse period, the memristance is non-volatile, and its variation is negligible. For incremental topology, the memristance increases according to the amplitude and pulse width, as depicted in Figure 3 (pink line), whereas for the decremental topology, the memristance decreases (blue line). It is important to point out that memristive behaviour in each operation

mode can be reverted to its last value, when a negative pulse of the same size is applied.

emulator circuit described in [32] and shown in Figure 4(a) is given by

R<sup>1</sup> þ Rx

<sup>¼</sup> <sup>W</sup>ðqmðtÞÞ ¼ <sup>1</sup>

Recently in [28, 31, 32], floating and grounded memristor emulator circuits based on CCII+ were proposed. In this way, the behavioural model of the charge-controlled grounded memductor

> AvAi 10ðR<sup>m</sup> þ RxÞðC<sup>m</sup> þ CaÞ

ðt 0

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 119

imðτÞdτ ð4Þ

�

where R<sup>x</sup> and C<sup>a</sup> are the parasitic resistance and capacitance connected in x- and z-terminal,

Figure 3. Experimental results of non-volatility property for incremental (pink line) and (blue line) decremental

2.2. Grounded memristor emulator circuit I

imðtÞ vmðtÞ

memristor. Pulse signal at yellow line.

3. k<sup>n</sup> ! ≥1 when f ≤ 1/τ or A<sup>m</sup> increases too much. Here, the hysteresis loop is lost.

In order to ensure the behaviour of the frequency-dependent pinched hysteresis loop, the numerical value of k<sup>n</sup> must be in the interval (0, 1). Once the behavioural model of the memristor has been deduced, numerical simulations can be realized. The numerical value of each element of Figure 1(a) used during numerical simulations and experimental tests can be found in [28]. Therefore, Figure 2(a) (solid line) shows only the incremental pinched hysteresis loop behaviour obtained of Figure 1(b) when a sinusoidal waveform operating to 16 Hz is applied. For this case and that follows, the direction of the hysteresis loop is clockwise, whereas for a decremental mode, the direction is counterclockwise. Therefore, a similar behaviour is obtained for the decremental case, as illustrated in Figure 2(a).

Figure 1. (a) Flux-controlled floating memristor emulator circuit taken from [28] and (b) SIMULINK model of Eq. (1).

Figure 2. Numerical, HSPICE and experimental results of Figure 1(a) operating at: (a) 16 Hz and (b) 100 Hz.

Figure 1(a) was also simulated at HSPICE by using the macro-models associated to each active device and numerical results are shown in Figure 2(a) (dash-dot line). In order to validate the previous results, Figure 1(a) was experimentally tested, and the results are shown in Figure 2(a) (dot-dash line). On the other hand, when the operating frequency increases, the pinched hysteresis loop is gradually lost and the memristor behaviour becomes a straight line for all cases, as depicted in Figure 2(b). Furthermore, the frequency-dependent pinched hysteresis loop is a necessary condition but not sufficient for claiming that the emulator circuit is emulating the real memristor behaviour. In this case, tests of non-volatility are necessary. Since capacitors and inductors are the solely elements that are storing energy, the non-volatility property is indirectly measured across C<sup>z</sup> of Figure 1(a). Thus, Figure 3 shows experimental tests of non-volatility of Figure 1(a) when a narrow pulse train of 1.2 V of amplitude and 2.4 μs of pulse width (yellow line) is applied. According to Figure 3, one can observe that once programmed the incremental and decremental memristance, its value is keeping when the input signal is not applied. Note that during non-pulse period, the memristance is non-volatile, and its variation is negligible. For incremental topology, the memristance increases according to the amplitude and pulse width, as depicted in Figure 3 (pink line), whereas for the decremental topology, the memristance decreases (blue line). It is important to point out that memristive behaviour in each operation mode can be reverted to its last value, when a negative pulse of the same size is applied.

#### 2.2. Grounded memristor emulator circuit I

2. k<sup>n</sup> ! 1 when f ! 1/τ or A<sup>m</sup> is monotonically increased. Therefore, the maximum pinched

In order to ensure the behaviour of the frequency-dependent pinched hysteresis loop, the numerical value of k<sup>n</sup> must be in the interval (0, 1). Once the behavioural model of the memristor has been deduced, numerical simulations can be realized. The numerical value of each element of Figure 1(a) used during numerical simulations and experimental tests can be found in [28]. Therefore, Figure 2(a) (solid line) shows only the incremental pinched hysteresis loop behaviour obtained of Figure 1(b) when a sinusoidal waveform operating to 16 Hz is applied. For this case and that follows, the direction of the hysteresis loop is clockwise, whereas for a decremental mode, the direction is counterclockwise. Therefore, a similar behav-

Figure 1. (a) Flux-controlled floating memristor emulator circuit taken from [28] and (b) SIMULINK model of Eq. (1).

Figure 2. Numerical, HSPICE and experimental results of Figure 1(a) operating at: (a) 16 Hz and (b) 100 Hz.

3. k<sup>n</sup> ! ≥1 when f ≤ 1/τ or A<sup>m</sup> increases too much. Here, the hysteresis loop is lost.

iour is obtained for the decremental case, as illustrated in Figure 2(a).

hysteresis loop is obtained.

118 Memristor and Memristive Neural Networks

Recently in [28, 31, 32], floating and grounded memristor emulator circuits based on CCII+ were proposed. In this way, the behavioural model of the charge-controlled grounded memductor emulator circuit described in [32] and shown in Figure 4(a) is given by

$$\frac{i\_{\rm m}(t)}{v\_{\rm m}(t)} = W(q\_{\rm m}(t)) = \frac{1}{R\_1 + R\_{\rm x}} \pm \frac{A\_v A\_i}{10(R\_{\rm m} + R\_{\rm x})(\mathcal{C}\_{\rm m} + \mathcal{C}\_{\rm a})} \int\_0^t i\_{\rm m}(\tau) d\tau \tag{4}$$

where R<sup>x</sup> and C<sup>a</sup> are the parasitic resistance and capacitance connected in x- and z-terminal,

Figure 3. Experimental results of non-volatility property for incremental (pink line) and (blue line) decremental memristor. Pulse signal at yellow line.

Figure 4. (a) Charge-controlled grounded memductor emulator circuit taken from [32] and (b) SIMULINK model of Eqs. (4) and (5).

respectively; A<sup>v</sup> and A<sup>i</sup> are the voltage and current gains between y- and x-terminal and x- and z-terminal of CCII+. Similarly as in Subsection 2.1, an incremental behaviour is obtained when the S switch is connected to I and a decremental behaviour is obtained if S is connected to D. Each behaviour corresponds to the sign + and � at Eq. (4), respectively. According to the behaviour of the frequency-dependent pinched hysteresis loop, this is composed by two lobes with symmetric areas. Since the hysteresis loop is represented on the v-i plane, the average current occurs when the area of both lobes is zero, and hence, the hysteresis loop tends to be a straight line as f ! ∞. This last effect is achieved when the linear time-varying part of the memductor is zero, and hence, from Eq. (4), we get

$$i\_{\mathbf{m}}(t) = \frac{v\_{\mathbf{m}}(t)}{R\_{\mathbf{m}} + R\_{\mathbf{x}}} \tag{5}$$

In this manner, the behaviour of the frequency-dependent pinched hysteresis loop can be kept over a broad range of frequencies and amplitude Am, when the numerical value of k<sup>n</sup> is in the interval (0, 1) [32]. This means that τ must be updated according to f and Am, respectively. The numerical value of each element of Figure 4(a) for different operating frequencies and ampli-

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 121

According to [32], Figure 4(a) was configured for working at 16 Hz in both operation modes. Henceforth, numerical results of the incremental topology will be shown below in the left side, whereas the decremental topology will be shown in the right side. From Figure 4(b), numerical results for each topology are depicted in Figure 5(a) and (b) (solid lines). Let us now increase monotonically the operating frequency of vm(t) until f = 500 Hz. As depicted in Figure 5(c) and (d) (solid lines), the frequency-dependent pinched hysteresis loop for both topologies becomes dominated by the linear time-invariant admittance. In this stage, for widening the hysteresis loop of each topology and keeping f = 500 Hz, C<sup>m</sup> or R<sup>1</sup> must be adjusted. Afterwards, each topology shown in Figure 4(a) was simulated at HSPICE and numerical results are illustrated in Figure 5(a) and (b) (dash-dot lines) operating at 16 Hz, respectively. Similarly as above, the operating

Figure 5. Numerical, HSPICE and experimental results of Figure 4(a) operating at: (a) 16 Hz and (c) 500 Hz, for

incremental mode; (b) 16 Hz and (d) 500 Hz, for decremental mode.

tudes can be found in [32].

From Eqs. (4) and (5), a SIMULINK model can be easily built, as shown in Figure 4(b). Note that to obtain a decremental memductor, the input-terminal second of the block, shown in Figure 4(b), must be negative. Considering vm(t) = Amsin(ωt) and substituting Eq. (5) in Eq. (4), we get

$$\frac{i\_{\rm m}(t)}{w\_{\rm m}(t)} = \frac{1}{R\_{\rm m} + R\_{\rm x}} \pm \frac{A\_{\rm v} A\_{\rm i} A\_{\rm m}}{10\omega (R\_{\rm m} + R\_{\rm x})^2 (\mathcal{C}\_{\rm m} + \mathcal{C}\_{\rm a})} \cos(\omega t - \pi) \tag{6}$$

and the kn parameter is given by

$$k\_{\rm n} = \frac{A\_{\rm v} A\_{\rm i} A\_{\rm m}}{10\omega (R\_{\rm m} + R\_{\rm x})(C\_{\rm m} + C\_{\rm a})} = \frac{1}{\tau f} = \frac{T}{\tau} \tag{7}$$

where <sup>τ</sup> <sup>¼</sup> <sup>20</sup>πðRmþRxÞðCmþCa<sup>Þ</sup> <sup>A</sup>vAiA<sup>m</sup> . From Eq. (7), one can intuit that k<sup>n</sup> will decrease as the frequency increases, but Eq. (7) also reveals that


In this manner, the behaviour of the frequency-dependent pinched hysteresis loop can be kept over a broad range of frequencies and amplitude Am, when the numerical value of k<sup>n</sup> is in the interval (0, 1) [32]. This means that τ must be updated according to f and Am, respectively. The numerical value of each element of Figure 4(a) for different operating frequencies and amplitudes can be found in [32].

According to [32], Figure 4(a) was configured for working at 16 Hz in both operation modes. Henceforth, numerical results of the incremental topology will be shown below in the left side, whereas the decremental topology will be shown in the right side. From Figure 4(b), numerical results for each topology are depicted in Figure 5(a) and (b) (solid lines). Let us now increase monotonically the operating frequency of vm(t) until f = 500 Hz. As depicted in Figure 5(c) and (d) (solid lines), the frequency-dependent pinched hysteresis loop for both topologies becomes dominated by the linear time-invariant admittance. In this stage, for widening the hysteresis loop of each topology and keeping f = 500 Hz, C<sup>m</sup> or R<sup>1</sup> must be adjusted. Afterwards, each topology shown in Figure 4(a) was simulated at HSPICE and numerical results are illustrated in Figure 5(a) and (b) (dash-dot lines) operating at 16 Hz, respectively. Similarly as above, the operating

respectively; A<sup>v</sup> and A<sup>i</sup> are the voltage and current gains between y- and x-terminal and x- and z-terminal of CCII+. Similarly as in Subsection 2.1, an incremental behaviour is obtained when the S switch is connected to I and a decremental behaviour is obtained if S is connected to D. Each behaviour corresponds to the sign + and � at Eq. (4), respectively. According to the behaviour of the frequency-dependent pinched hysteresis loop, this is composed by two lobes with symmetric areas. Since the hysteresis loop is represented on the v-i plane, the average current occurs when the area of both lobes is zero, and hence, the hysteresis loop tends to be a straight line as f ! ∞. This last effect is achieved when the linear time-varying part of the

Figure 4. (a) Charge-controlled grounded memductor emulator circuit taken from [32] and (b) SIMULINK model of

<sup>i</sup>mðtÞ ¼ <sup>v</sup>mðt<sup>Þ</sup>

From Eqs. (4) and (5), a SIMULINK model can be easily built, as shown in Figure 4(b). Note that to obtain a decremental memductor, the input-terminal second of the block, shown in Figure 4(b),

must be negative. Considering vm(t) = Amsin(ωt) and substituting Eq. (5) in Eq. (4), we get

10ωðR<sup>m</sup> þ RxÞ

10ωðR<sup>m</sup> þ RxÞðC<sup>m</sup> þ CaÞ

1. kn ! 0 when f ! ∞ or A<sup>m</sup> ! 0. Therefore, Eq. (6) becomes dominated by its linear time-

2. k<sup>n</sup> ! 1 when f ! 1/τ or A<sup>m</sup> is monotonically increased. Hence, the maximum frequency-

3. k<sup>n</sup> ! ≥1 when f ≤ 1/τ or A<sup>m</sup> increases too much. For this case, the hysteresis loop is lost.

�

<sup>k</sup><sup>n</sup> <sup>¼</sup> <sup>A</sup>vAiA<sup>m</sup>

R<sup>m</sup> þ R<sup>x</sup>

AvAiA<sup>m</sup>

2

ðC<sup>m</sup> þ CaÞ

¼ 1 <sup>τ</sup><sup>f</sup> <sup>¼</sup> <sup>T</sup>

<sup>A</sup>vAiA<sup>m</sup> . From Eq. (7), one can intuit that k<sup>n</sup> will decrease as the frequency

ð5Þ

cosðωt � πÞ ð6Þ

<sup>τ</sup> <sup>ð</sup>7<sup>Þ</sup>

memductor is zero, and hence, from Eq. (4), we get

imðtÞ vmðtÞ

and the kn parameter is given by

Eqs. (4) and (5).

120 Memristor and Memristive Neural Networks

where <sup>τ</sup> <sup>¼</sup> <sup>20</sup>πðRmþRxÞðCmþCa<sup>Þ</sup>

invariant admittance.

increases, but Eq. (7) also reveals that

<sup>¼</sup> <sup>1</sup> R<sup>m</sup> þ R<sup>x</sup>

dependent pinched hysteresis loop is obtained.

Figure 5. Numerical, HSPICE and experimental results of Figure 4(a) operating at: (a) 16 Hz and (c) 500 Hz, for incremental mode; (b) 16 Hz and (d) 500 Hz, for decremental mode.

frequency was increased until 500 Hz and, as a consequence, both pinched hysteresis loops become a straight line, as depicted in Figure 5(c) and (d) (dash-dot lines). In order to demonstrate the real behaviour of the memductor emulator circuit, Figure 4(a) was built with off-the-shelf devices.

In this way, Figure 5(a) and (b) (dashed lines) illustrate the pinched hysteresis loops for both operation modes and the upper and lower lobe area of both hysteresis loops becomes zero when the operating frequency increases and hence the hysteresis loop tends to be a straight line, as illustrated in Figure 5(c) and (d) (dashed lines), confirming the theory described before. To experimentally test the non-volatility of the memductor emulator circuit, the voltage across C<sup>m</sup> of Figure 4(a) was measured for each incremental and decremental configuration. In both cases, a rectangular pulse train of 5 V of amplitude with 82 μs was applied in the input of Figure 4(a). Therefore, Figure 6(a) shows the behaviour of vCm(t) for the incremental case, whereas Figure 6(b) shows the decremental case. From Figure 6, one can observe that the variation of vCm(t) is more pronounced for the decremental case. Observe, also, that the voltage is kept during non-pulse period. Again, the memductive behaviour in each operation mode can be reverted to its last value, whether a negative pulse of the same size is applied [32].

#### 2.3. Grounded memristor emulator circuit II

As last example, we discuss the charge-controlled grounded memristor emulator circuit reported in [31] and illustrated in Figure 7(a). Simple analysis of Figure 7(a) allows us to obtain the memristive behaviour given by

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = M(q\_{\rm m}(t)) = R\_1 \pm \frac{R\_2}{40\mathcal{C}\_1} \int\_0^t i\_{\rm m}(\tau)d\tau \tag{8}$$

done. According to Eq. (8), the average current will occur when the linear time-varying resistor

Figure 7. (a) Charge-controlled grounded memristor emulator circuit taken from [31] and (b) SIMULINK model of

<sup>i</sup>mðtÞ ¼ <sup>v</sup>mðt<sup>Þ</sup> R1

By merging Eqs. (8) and (9), a SIMULINK model can be built, as depicted in Figure 7(b). In this figure, the input-terminal second of the adder block must be negative to obtain a decremental

> R2A<sup>m</sup> 40R1C1ω

> > <sup>1</sup>C1<sup>ω</sup> <sup>¼</sup> <sup>1</sup>

In the same way as in previous subsections, k<sup>n</sup> will decrease as the operating frequency increases, and for holding the hysteresis loop at a particular frequency, the numeric value of τ

2. k<sup>n</sup> ! 1 when f ! 1/τ or A<sup>m</sup> is monotonically increased. Thus, we see that the maximum

3. k<sup>n</sup> ! ≥1 when f ≤ 1/τ or A<sup>m</sup> increases too much. For this case, the hysteresis loop is lost. According to [31], the memristor emulator circuit was configured to operate at 16 Hz in both operation modes. By using Figure 7(b), the hysteresis loop for each topology shown in Figure 7(a) is obtained, as depicted in Figure 8(a) and (b) (solid lines), respectively. By monotonically increasing the operating frequency of vm(t) until 100 Hz, both hysteresis loops become dominated by R1,

<sup>τ</sup><sup>f</sup> <sup>¼</sup> <sup>T</sup>

behaviour. Assuming vm(t) = Amsin(ωt) and substituting Eq. (9) in Eq. (8), we obtain

<sup>k</sup><sup>n</sup> <sup>¼</sup> <sup>R</sup>2A<sup>m</sup> 40R<sup>2</sup>

<sup>R</sup>2A<sup>m</sup> is the time constant of the emulator circuit and <sup>T</sup> <sup>¼</sup> <sup>1</sup>

must be updated by C1. Analysing Eq. (11) for both configurations, we have

1. k<sup>n</sup> ! 0 when f ! ∞ or A<sup>m</sup> ! 0. Therefore, Eq. (10) becomes dominated by R1.

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> � ð9Þ

123

cos ðωt � πÞ ð10Þ

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291

<sup>τ</sup> <sup>ð</sup>11<sup>Þ</sup>

<sup>f</sup> is the period of vm(t).

is zero and hence from Eq. (8) we get:

It follows from Eq. (10) that

<sup>1</sup>C<sup>1</sup>

pinched hysteresis loop is achieved.

where <sup>τ</sup> <sup>¼</sup> <sup>40</sup>πR<sup>2</sup>

Eqs. (8) and (9).

It is notable to point out that the positive sign in Eq. (8) correspond to the S switch connected to I in Figure 7(a) and hence, an incremental behaviour is obtained; whereas the negative sign is obtained when S is connected to D and hence a decremental behaviour. Again, following the idea described in previous subsections and reported in [28, 31], a frequency analysis can be

Figure 6. Experimental results of non-volatility property for: (a) incremental mode and (b) decremental mode.

Figure 7. (a) Charge-controlled grounded memristor emulator circuit taken from [31] and (b) SIMULINK model of Eqs. (8) and (9).

done. According to Eq. (8), the average current will occur when the linear time-varying resistor is zero and hence from Eq. (8) we get:

$$i\_{\mathfrak{m}}(t) = \frac{v\_{\mathfrak{m}}(t)}{R\_1} \tag{9}$$

By merging Eqs. (8) and (9), a SIMULINK model can be built, as depicted in Figure 7(b). In this figure, the input-terminal second of the adder block must be negative to obtain a decremental behaviour. Assuming vm(t) = Amsin(ωt) and substituting Eq. (9) in Eq. (8), we obtain

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_2 A\_{\rm m}}{40 R\_1 C\_1 \omega} \cos\left(\omega t - \pi\right) \tag{10}$$

It follows from Eq. (10) that

frequency was increased until 500 Hz and, as a consequence, both pinched hysteresis loops become a straight line, as depicted in Figure 5(c) and (d) (dash-dot lines). In order to demonstrate the real behaviour of the memductor emulator circuit, Figure 4(a) was built with off-the-shelf

In this way, Figure 5(a) and (b) (dashed lines) illustrate the pinched hysteresis loops for both operation modes and the upper and lower lobe area of both hysteresis loops becomes zero when the operating frequency increases and hence the hysteresis loop tends to be a straight line, as illustrated in Figure 5(c) and (d) (dashed lines), confirming the theory described before. To experimentally test the non-volatility of the memductor emulator circuit, the voltage across C<sup>m</sup> of Figure 4(a) was measured for each incremental and decremental configuration. In both cases, a rectangular pulse train of 5 V of amplitude with 82 μs was applied in the input of Figure 4(a). Therefore, Figure 6(a) shows the behaviour of vCm(t) for the incremental case, whereas Figure 6(b) shows the decremental case. From Figure 6, one can observe that the variation of vCm(t) is more pronounced for the decremental case. Observe, also, that the voltage is kept during non-pulse period. Again, the memductive behaviour in each operation mode can be reverted to its last value, whether a negative pulse of the same size is applied [32].

As last example, we discuss the charge-controlled grounded memristor emulator circuit reported in [31] and illustrated in Figure 7(a). Simple analysis of Figure 7(a) allows us to obtain the

It is notable to point out that the positive sign in Eq. (8) correspond to the S switch connected to I in Figure 7(a) and hence, an incremental behaviour is obtained; whereas the negative sign is obtained when S is connected to D and hence a decremental behaviour. Again, following the idea described in previous subsections and reported in [28, 31], a frequency analysis can be

Figure 6. Experimental results of non-volatility property for: (a) incremental mode and (b) decremental mode.

R2 40C<sup>1</sup> ðt 0

imðτÞdτ ð8Þ

<sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>M</sup>ðqmðtÞÞ ¼ <sup>R</sup><sup>1</sup> �

devices.

122 Memristor and Memristive Neural Networks

2.3. Grounded memristor emulator circuit II

vmðtÞ

memristive behaviour given by

$$k\_{\rm n} = \frac{R\_2 A\_{\rm m}}{40 R\_1^2 C\_1 \omega} = \frac{1}{\tau f} = \frac{T}{\tau} \tag{11}$$

where <sup>τ</sup> <sup>¼</sup> <sup>40</sup>πR<sup>2</sup> <sup>1</sup>C<sup>1</sup> <sup>R</sup>2A<sup>m</sup> is the time constant of the emulator circuit and <sup>T</sup> <sup>¼</sup> <sup>1</sup> <sup>f</sup> is the period of vm(t). In the same way as in previous subsections, k<sup>n</sup> will decrease as the operating frequency increases, and for holding the hysteresis loop at a particular frequency, the numeric value of τ must be updated by C1. Analysing Eq. (11) for both configurations, we have


According to [31], the memristor emulator circuit was configured to operate at 16 Hz in both operation modes. By using Figure 7(b), the hysteresis loop for each topology shown in Figure 7(a) is obtained, as depicted in Figure 8(a) and (b) (solid lines), respectively. By monotonically increasing the operating frequency of vm(t) until 100 Hz, both hysteresis loops become dominated by R1,

devices. Therefore, Figure 8(a) and (b) (dot-square lines) show the experimental results for each topology and at each fundamental operating frequency; whereas Figure 8(c) and (d) (dotsquare lines) show that the hysteresis loops become dominated by R1, confirming the theory described above. A notable fingerprint of any memristor emulator circuit is the non-volatility of its memristance. This means that the memristance once programmed, its last value must be kept for a long time. In order to verify this property, the voltage across C<sup>1</sup> was first experimentally measured and next, by using Eq. (8), a post-processing was done for getting the memristance variation for each topology, as depicted in Figure 9 (top figure). The memristance variations were obtained when a pulse train of 5 V of amplitude and 0.5 ms of pulse width was applied to

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 125

As one can observe in Figure 9, the memristance range for both emulator circuits is 7 kΩ, and although the pulse train is applied indefinitely, the maximum memristance achieved is 19 kΩ; whereas the minimum memristance for the decremental case is 5 kΩ. On the other hand, if the pulse train with �5 V of amplitude and same pulse width is applied, then the memristive

behaviour is inverted for each topology shown in the top of Figure 9 [31].

According to Section 2, one can observe that Eqs. (1), (4) and (8) have the form

� a<sup>n</sup> � b<sup>n</sup>

where yn(t) is the current or voltage output signal, x(t) is the voltage or current input signal and z (t) is the voltage or current control signal; a<sup>n</sup> represents the linear time-invariant gain and b<sup>n</sup> represents the linear time-varying gain, which is associated with the time constant of the emulator circuit [28, 31, 32]. Assuming that z(t) = Amsin(ωt + θ), where θ is the phase in degrees, we

Figure 9. Experimental results of non-volatile memristance for incremental mode (black line) and decremental mode (red

ðt 0 zðτÞdτ �

ð12Þ

ynðtÞ ¼ xðtÞ

Figure 7(a), as illustrated in Figure 9 (lower figure).

3. Design guide

line). In the figure below, vm(t) as pulse train.

obtain

Figure 8. Numerical, HSPICE and experimental results of Figure 7(a) operating at: (a) 16 Hz and (c) 100 Hz, for incremental mode; (b) 16 Hz and (d) 100 Hz, for decremental mode.

as illustrated in Figure 8(c) and (d) (solid lines). It is worth stressing that to obtain the pinched hysteresis loops shown in Figure 8(a) and (b) (solid lines) but at f = 100 Hz, the numeric value of C<sup>1</sup> must be adjusted. Therefore, one can insight that by scaling down C1, the hysteresis loop behaviour, for both topologies, can be pushed for operating at higher frequencies. On the other hand, Figure 7(a) was also simulated at HSPICE by using the numerical value of each element described in [31] and for both topologies. Simulation results are illustrated in Figure 8(a) and (b) (dash-dot lines), respectively; whereas the linear behaviours are depicted in Figure 8(c) and (d) (dash-dot lines).

To validate the results derived and demonstrate the real behaviour of the emulator circuit, Figure 7(a) was built and experimentally tested by using commercially available active devices. Therefore, Figure 8(a) and (b) (dot-square lines) show the experimental results for each topology and at each fundamental operating frequency; whereas Figure 8(c) and (d) (dotsquare lines) show that the hysteresis loops become dominated by R1, confirming the theory described above. A notable fingerprint of any memristor emulator circuit is the non-volatility of its memristance. This means that the memristance once programmed, its last value must be kept for a long time. In order to verify this property, the voltage across C<sup>1</sup> was first experimentally measured and next, by using Eq. (8), a post-processing was done for getting the memristance variation for each topology, as depicted in Figure 9 (top figure). The memristance variations were obtained when a pulse train of 5 V of amplitude and 0.5 ms of pulse width was applied to Figure 7(a), as illustrated in Figure 9 (lower figure).

As one can observe in Figure 9, the memristance range for both emulator circuits is 7 kΩ, and although the pulse train is applied indefinitely, the maximum memristance achieved is 19 kΩ; whereas the minimum memristance for the decremental case is 5 kΩ. On the other hand, if the pulse train with �5 V of amplitude and same pulse width is applied, then the memristive behaviour is inverted for each topology shown in the top of Figure 9 [31].

Figure 9. Experimental results of non-volatile memristance for incremental mode (black line) and decremental mode (red line). In the figure below, vm(t) as pulse train.

#### 3. Design guide

as illustrated in Figure 8(c) and (d) (solid lines). It is worth stressing that to obtain the pinched hysteresis loops shown in Figure 8(a) and (b) (solid lines) but at f = 100 Hz, the numeric value of C<sup>1</sup> must be adjusted. Therefore, one can insight that by scaling down C1, the hysteresis loop behaviour, for both topologies, can be pushed for operating at higher frequencies. On the other hand, Figure 7(a) was also simulated at HSPICE by using the numerical value of each element described in [31] and for both topologies. Simulation results are illustrated in Figure 8(a) and (b) (dash-dot lines), respectively; whereas the linear behaviours are depicted in Figure 8(c) and (d)

Figure 8. Numerical, HSPICE and experimental results of Figure 7(a) operating at: (a) 16 Hz and (c) 100 Hz, for

incremental mode; (b) 16 Hz and (d) 100 Hz, for decremental mode.

124 Memristor and Memristive Neural Networks

To validate the results derived and demonstrate the real behaviour of the emulator circuit, Figure 7(a) was built and experimentally tested by using commercially available active

(dash-dot lines).

According to Section 2, one can observe that Eqs. (1), (4) and (8) have the form

$$y\_n(t) = \mathbf{x}(t) \left( a\_n \pm b\_n \int\_0^t \mathbf{z}(\tau) d\tau \right) \tag{12}$$

where yn(t) is the current or voltage output signal, x(t) is the voltage or current input signal and z (t) is the voltage or current control signal; a<sup>n</sup> represents the linear time-invariant gain and b<sup>n</sup> represents the linear time-varying gain, which is associated with the time constant of the emulator circuit [28, 31, 32]. Assuming that z(t) = Amsin(ωt + θ), where θ is the phase in degrees, we obtain

$$\int\_0^t z(\tau)d\tau = -\frac{A\_\text{m}}{\omega}\cos\left(\omega t + \theta\right) = \mp \frac{1}{\omega} \sqrt{A\_\text{m}^2 - z^2(t)}\tag{13}$$

therefore, Eq. (12) becomes

$$y\_n(t) = x(t) \left( a\_n \mp \frac{b\_n}{\omega} \sqrt{A\_m^2 - z^2(t)} \right) \tag{14}$$

According to [28, 31, 32], the linear time-varying gain can be computed in function of ω and A<sup>m</sup> given by

$$b\_{\mathbf{n}} = \frac{a\_{\mathbf{n}} \omega k\_{\mathbf{n}}}{A\_{\mathbf{m}}} \tag{15}$$

hence, the emulator circuit does not only stop mimicking the behaviour of the memristor, but also reduces its application range. Note that below a certain critical frequency, the emulator circuit mimics well the behaviour of a memristor and beyond that of critical frequency, the

In order to overcome this shortcoming and achieve a pinched hysteresis loop operating at high frequency, an offset compensation technique must be applied. Such techniques have been reported in [33]. Basically, the technique involves adding two DC voltage sources in the analogue multiplier to vertically and horizontally control the offset of the hysteresis loop. However, as described in [33], this offset reduction technique is only applicable to floating and grounded memristor emulator circuits whose design is based on analogue multipliers. In this manner, let us consider the topologies shown in Figure 1(a) and 7(a), including the voltage sources, as depicted in Figure 10(a) and (b), respectively. According to Eq. (1), Figure 10(a) and [28, 33], the

circuit becomes a memristive device with an additional battery in series.

controlled incremental and decremental memristance is modified as

MðqmðtÞ, VH, VVÞ ¼ R<sup>1</sup> ∓

�

Similarly for Eq. (8), Figure 10(b) and [31, 33], the memristance becomes:

Figure 10. Offset compensated memristor emulator circuits: (a) Figure 1(a) and (b) Figure 7(a).

¼ R<sup>1</sup> �

R2 <sup>20</sup> <sup>V</sup><sup>V</sup> �

where V<sup>H</sup> is a DC voltage source to control the horizontally offset and V<sup>V</sup> is other DC voltage source to control the vertical offset of the frequency-dependent pinched hysteresis loop on the voltage-current plane. Note that if V<sup>H</sup> = V<sup>V</sup> = 0, then Eqs. (16) and (17) are reduced to Eqs. (1) and (8), respectively. For both topologies shown in Figure 10, two switches, S<sup>1</sup> and S2, are used to interchange the kind of memristor and to connect the V<sup>V</sup> voltage source in each case. To validate the offset reduction method, Figure 10(a) was configured at decremental mode and operating to 14 kHz. In a first step, V<sup>H</sup> = V<sup>V</sup> = 0 were considered and simulation results are depicted in Figure 11(a) (solid line). Note that the pinched hysteresis loop deviates of the origin. In a second step, the DC voltage sources were monotonically decreased until V<sup>H</sup> = �60.59 mV and V<sup>V</sup> = �160.3 mV, and as a consequence, the offset was reduced, as shown

R4ðR<sup>1</sup> � VVÞ 10R2R3C<sup>z</sup>

> R2 40C<sup>1</sup>

ðt 0

ðt 0 vmðτÞdτ � V<sup>H</sup> ð16Þ

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 127

imðτÞdτ � V<sup>H</sup> ð17Þ

φmðtÞ, VH, V<sup>V</sup>

M �

where k<sup>n</sup> ∈ (0, 1) is a parameter that is used to ensure the behaviour of the pinched hysteresis loop.

In order to design a memristor emulator circuit, the following four-step design procedure is proposed


If the above procedure is followed, it is most likely that a memristor emulator circuit with good features will result and with a frequency-dependent hysteresis loop with relatively symmetrical lobes.

#### 4. Offset compensation

Some properties that any emulator circuit must satisfy to be considered as memristor were described in Section 1. One of them is the frequency-dependent pinched hysteresis loop observed on the voltage-current plane, which must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions [1]. Thus, whether a periodic signal is applied to the memristor emulator circuit, both the voltage and current are zero when any of them is zero. Therefore, any device is a memristor or a memristive device when it has a current-voltage hysteresis curve with identical zero crossing. However, until today, all the memristor emulator circuits reported in the literature [19–32] are operating in low-frequency and some of them present a deviation of the crossing point on the origin. This behaviour is more evident when the operating frequency of the stimulus signal increases, and hence, the emulator circuit does not only stop mimicking the behaviour of the memristor, but also reduces its application range. Note that below a certain critical frequency, the emulator circuit mimics well the behaviour of a memristor and beyond that of critical frequency, the circuit becomes a memristive device with an additional battery in series.

In order to overcome this shortcoming and achieve a pinched hysteresis loop operating at high frequency, an offset compensation technique must be applied. Such techniques have been reported in [33]. Basically, the technique involves adding two DC voltage sources in the analogue multiplier to vertically and horizontally control the offset of the hysteresis loop. However, as described in [33], this offset reduction technique is only applicable to floating and grounded memristor emulator circuits whose design is based on analogue multipliers. In this manner, let us consider the topologies shown in Figure 1(a) and 7(a), including the voltage sources, as depicted in Figure 10(a) and (b), respectively. According to Eq. (1), Figure 10(a) and [28, 33], the controlled incremental and decremental memristance is modified as

$$M\left(\varphi\_{\rm m}(t), V\_{\rm H}, V\_{\rm V}\right) = R\_1 \pm \frac{R\_4(R\_1 - V\_{\rm V})}{10R\_2R\_3C\_x} \int\_0^t \upsilon\_{\rm m}(\tau)d\tau - V\_{\rm H} \tag{16}$$

Similarly for Eq. (8), Figure 10(b) and [31, 33], the memristance becomes:

ðt 0

pinched hysteresis loop, we choose k<sup>n</sup> = 0.5.

therefore, Eq. (12) becomes

126 Memristor and Memristive Neural Networks

A<sup>m</sup> given by

loop.

proposed

cal lobes.

4. Offset compensation

<sup>z</sup>ðτÞd<sup>τ</sup> ¼ � <sup>A</sup><sup>m</sup>

ω

ynðtÞ ¼ xðtÞ a<sup>n</sup> ∓

cos ðωt þ θÞ ¼ ∓

bn ω

According to [28, 31, 32], the linear time-varying gain can be computed in function of ω and

<sup>b</sup><sup>n</sup> <sup>¼</sup> <sup>a</sup>nωk<sup>n</sup> A<sup>m</sup>

where k<sup>n</sup> ∈ (0, 1) is a parameter that is used to ensure the behaviour of the pinched hysteresis

In order to design a memristor emulator circuit, the following four-step design procedure is

Step 1. For all memristor emulator circuit that has the form given by Eq. (12) and to ensure the

Step 2. Given an operating frequency and Am, use Eq. (15) to find the relation between b<sup>n</sup> and an. Step 3. Select the numeric value of an, which is associated to the linear time-invariant resistor/

Step 4. For each topology, b<sup>n</sup> is related with those parameters of the emulator circuit and τ.

If the above procedure is followed, it is most likely that a memristor emulator circuit with good features will result and with a frequency-dependent hysteresis loop with relatively symmetri-

Some properties that any emulator circuit must satisfy to be considered as memristor were described in Section 1. One of them is the frequency-dependent pinched hysteresis loop observed on the voltage-current plane, which must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions [1]. Thus, whether a periodic signal is applied to the memristor emulator circuit, both the voltage and current are zero when any of them is zero. Therefore, any device is a memristor or a memristive device when it has a current-voltage hysteresis curve with identical zero crossing. However, until today, all the memristor emulator circuits reported in the literature [19–32] are operating in low-frequency and some of them present a deviation of the crossing point on the origin. This behaviour is more evident when the operating frequency of the stimulus signal increases, and

conductor. As a consequence, the numeric value of b<sup>n</sup> is derived from Eq. (15).

Therefore, the numeric value of each resistor and capacitor can be deduced.

� � q

1 ω

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2

<sup>m</sup> � z<sup>2</sup>ðtÞ

q

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2

<sup>m</sup> � z<sup>2</sup>ðtÞ

ð13Þ

ð14Þ

ð15Þ

$$M(q\_{\rm m}(t), V\_{\rm H}, V\_{\rm V}) = R\_1 \mp \frac{R\_2}{20} V\_{\rm V} \pm \frac{R\_2}{40 \mathcal{C}\_1} \int\_0^t i\_{\rm m}(\tau) d\tau \pm V\_{\rm H} \tag{17}$$

where V<sup>H</sup> is a DC voltage source to control the horizontally offset and V<sup>V</sup> is other DC voltage source to control the vertical offset of the frequency-dependent pinched hysteresis loop on the voltage-current plane. Note that if V<sup>H</sup> = V<sup>V</sup> = 0, then Eqs. (16) and (17) are reduced to Eqs. (1) and (8), respectively. For both topologies shown in Figure 10, two switches, S<sup>1</sup> and S2, are used to interchange the kind of memristor and to connect the V<sup>V</sup> voltage source in each case. To validate the offset reduction method, Figure 10(a) was configured at decremental mode and operating to 14 kHz. In a first step, V<sup>H</sup> = V<sup>V</sup> = 0 were considered and simulation results are depicted in Figure 11(a) (solid line). Note that the pinched hysteresis loop deviates of the origin. In a second step, the DC voltage sources were monotonically decreased until V<sup>H</sup> = �60.59 mV and V<sup>V</sup> = �160.3 mV, and as a consequence, the offset was reduced, as shown

Figure 10. Offset compensated memristor emulator circuits: (a) Figure 1(a) and (b) Figure 7(a).

effect is because a normal non-linear resistor/conductor uses an integrator block and, in general, its behaviour can be modelled by Eq. (12). Since the inverse operation of an integral is the derivate, the hysteresis loop behaviour of a normal non-linear resistor can be inverted whether a differentiator block is used instead of an integrator block. Under this assumption

ðtÞ ¼ xðtÞ a<sup>i</sup> � b<sup>i</sup>

gain and b<sup>i</sup> is the linear time-varying gain. Assuming z(t) = A<sup>m</sup> sin (ωt + θ), we obtain

dt <sup>¼</sup> <sup>A</sup>m<sup>ω</sup> cos <sup>ð</sup>ω<sup>t</sup> <sup>þ</sup> <sup>θ</sup>޼�<sup>ω</sup>

� a<sup>i</sup> � biω

where yi(t) is the inverse current or voltage output signal, x(t) is the voltage or current input signal and z(t) is the voltage or current control signal; a<sup>i</sup> represents the linear time-invariant

Comparing Eqs. (14) and (20), one can observe that the sole difference is the position of ω. According to Section 3 [28, 31, 32], the linear time-varying gain can be computed in function of

> <sup>b</sup><sup>i</sup> <sup>¼</sup> <sup>a</sup>iωk<sup>i</sup> A<sup>m</sup>

where k<sup>i</sup> ∈ (0, 1). In Section 2, the behavioural model of normal flux- or charge-controlled resistors was derived and one can observe that each model has an integrative part. As first approximation and for obtaining an inverse flux- or charge-controlled resistor from a normal resistor, the integrator circuit of the latter must be replaced by a differentiator circuit in the former. This task can be done by simply interchanging C<sup>1</sup> by R<sup>2</sup> in Figure 1(a), as depicted in

> R1R3R4C<sup>z</sup> 10R<sup>2</sup>

Considering vm(t) = Amsin(ωt + ϕ), where ϕ is the phase in degrees and by using Eqs. (14) and

R1R<sup>4</sup> 10R2R3Czω

R1R3R4Czω 10R<sup>2</sup>

Comparing Eqs. (23) and (24) with Eqs. (14) and (20), respectively, one obtains

dvmðtÞ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � v<sup>2</sup> <sup>m</sup>ðtÞ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � v<sup>2</sup> <sup>m</sup>ðtÞ

q

q

dt <sup>ð</sup>22<sup>Þ</sup>

dzðtÞ

q

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � z<sup>2</sup>ðtÞ q �

dt � � <sup>ð</sup>18<sup>Þ</sup>

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291

ð19Þ

129

ð20Þ

ð21Þ

ð23Þ

ð24Þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � z<sup>2</sup>ðtÞ

and following the idea presented in Section 3, we have modified Eq. (12) as

yi

dzðτÞ

Figure 12(a), and analysing this figure we obtain

(20), Eqs. (1) and (22) are rewritten as

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

yi

ðtÞ ¼ xðtÞ

and Eq. (18) becomes

ω and A<sup>m</sup> given by

Figure 11. HSPICE results for: (a) decremental topology of Figure 10(a) and (b) incremental topology of Figure 10(b). For both figures: offset uncompensated (solid lines) and compensated (dashed lines).

in Figure 11(a) (dashed line). A similar analysis procedure was realized to the topology depicted in Figure 10(b) but operating to 160 kHz. In this manner, the grounded memristor emulator circuit was connected as incremental mode and considering V<sup>H</sup> = V<sup>V</sup> = 0. HSPICE simulations were obtained and shown in Figure 11(b) (solid line). In order to reduce the offset in Figure 11(b) (solid line), the DC voltage sources were updated to V<sup>H</sup> = 195.5 mV and V<sup>V</sup> = 1.568 V, and hence, the crossing point was pulled towards the origin, as shown in Figure 11(b) (dashed line). It is worth to stress that the value of each DC voltage source associated to each topology was derived to trial and error, and it should slightly be updated for each operating frequency. Hence, an open question is how to automatically compute the numeric value of each DC voltage source associated to each topology and operation mode. Moreover, in Figure 11(b) (solid lines), one can observe that each frequency-dependent pinched hysteresis loop becomes slightly deformed, resulting at an asymmetrical behaviour with regards to the origin, and hence, the hysteresis lobe area is not equal. Nonetheless, after of the offset compensation, the hysteresis lobe area for all frequency-dependent pinched hysteresis loops become relatively equal as depicted in Figure 11(b) (dashed lines). As a result, it is predicted that the frequency behaviour of the pinched hysteresis loops for both memristor emulator circuits can be pushed for operating in higher frequencies and holding a symmetrical behaviour, since the offset voltage glimpsed can again be reduced by updating the DC voltage sources.

#### 5. Transformation of normal non-linear resistors to inverse

A memristor/memductor is basically a resistor/conductor whose resistance/conductance can be changed by applying a voltage across its terminals or by applying a flow of current. The type of control signal depends on the type of memristor/memductor, i.e. flux- or chargecontrolled. In any case, the frequency-dependent pinched hysteresis loop of a normal nonlinear resistor/conductor will become a straight line if the operating frequency increases. This effect is because a normal non-linear resistor/conductor uses an integrator block and, in general, its behaviour can be modelled by Eq. (12). Since the inverse operation of an integral is the derivate, the hysteresis loop behaviour of a normal non-linear resistor can be inverted whether a differentiator block is used instead of an integrator block. Under this assumption and following the idea presented in Section 3, we have modified Eq. (12) as

$$y\_i(t) = \mathbf{x}(t) \left( a\_i \pm b\_i \frac{dz(t)}{dt} \right) \tag{18}$$

where yi(t) is the inverse current or voltage output signal, x(t) is the voltage or current input signal and z(t) is the voltage or current control signal; a<sup>i</sup> represents the linear time-invariant gain and b<sup>i</sup> is the linear time-varying gain. Assuming z(t) = A<sup>m</sup> sin (ωt + θ), we obtain

$$\frac{dz(\tau)}{dt} = A\_{\text{m}}\omega\cos\left(\omega t + \theta\right) = \pm\omega\sqrt{A\_{\text{m}}^2 - z^2(t)}\tag{19}$$

and Eq. (18) becomes

in Figure 11(a) (dashed line). A similar analysis procedure was realized to the topology depicted in Figure 10(b) but operating to 160 kHz. In this manner, the grounded memristor emulator circuit was connected as incremental mode and considering V<sup>H</sup> = V<sup>V</sup> = 0. HSPICE simulations were obtained and shown in Figure 11(b) (solid line). In order to reduce the offset in Figure 11(b) (solid line), the DC voltage sources were updated to V<sup>H</sup> = 195.5 mV and V<sup>V</sup> = 1.568 V, and hence, the crossing point was pulled towards the origin, as shown in Figure 11(b) (dashed line). It is worth to stress that the value of each DC voltage source associated to each topology was derived to trial and error, and it should slightly be updated for each operating frequency. Hence, an open question is how to automatically compute the numeric value of each DC voltage source associated to each topology and operation mode. Moreover, in Figure 11(b) (solid lines), one can observe that each frequency-dependent pinched hysteresis loop becomes slightly deformed, resulting at an asymmetrical behaviour with regards to the origin, and hence, the hysteresis lobe area is not equal. Nonetheless, after of the offset compensation, the hysteresis lobe area for all frequency-dependent pinched hysteresis loops become relatively equal as depicted in Figure 11(b) (dashed lines). As a result, it is predicted that the frequency behaviour of the pinched hysteresis loops for both memristor emulator circuits can be pushed for operating in higher frequencies and holding a symmetrical behaviour, since the offset voltage glimpsed can

Figure 11. HSPICE results for: (a) decremental topology of Figure 10(a) and (b) incremental topology of Figure 10(b). For

both figures: offset uncompensated (solid lines) and compensated (dashed lines).

128 Memristor and Memristive Neural Networks

again be reduced by updating the DC voltage sources.

5. Transformation of normal non-linear resistors to inverse

A memristor/memductor is basically a resistor/conductor whose resistance/conductance can be changed by applying a voltage across its terminals or by applying a flow of current. The type of control signal depends on the type of memristor/memductor, i.e. flux- or chargecontrolled. In any case, the frequency-dependent pinched hysteresis loop of a normal nonlinear resistor/conductor will become a straight line if the operating frequency increases. This

$$y\_i(t) = \mathbf{x}(t) \left( a\_i \pm b\_i \omega \sqrt{A\_m^2 - z^2(t)} \right) \tag{20}$$

Comparing Eqs. (14) and (20), one can observe that the sole difference is the position of ω. According to Section 3 [28, 31, 32], the linear time-varying gain can be computed in function of ω and A<sup>m</sup> given by

$$b\_{\rm i} = \frac{a\_{\rm i} a k\_{\rm i}}{A\_{\rm m}} \tag{21}$$

where k<sup>i</sup> ∈ (0, 1). In Section 2, the behavioural model of normal flux- or charge-controlled resistors was derived and one can observe that each model has an integrative part. As first approximation and for obtaining an inverse flux- or charge-controlled resistor from a normal resistor, the integrator circuit of the latter must be replaced by a differentiator circuit in the former. This task can be done by simply interchanging C<sup>1</sup> by R<sup>2</sup> in Figure 1(a), as depicted in Figure 12(a), and analysing this figure we obtain

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_1 R\_3 R\_4 C\_{\rm x}}{10 R\_2} \frac{dv\_{\rm m}(t)}{dt} \tag{22}$$

Considering vm(t) = Amsin(ωt + ϕ), where ϕ is the phase in degrees and by using Eqs. (14) and (20), Eqs. (1) and (22) are rewritten as

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_1 R\_4}{10 R\_2 R\_3 C\_{x^{\rm \alpha}}} \sqrt{A\_{\rm m}^2 - v\_{\rm m}^2(t)}\tag{23}$$

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_1 R\_3 R\_4 C\_x \omega}{10 R\_2} \sqrt{A\_{\rm m}^2 - v\_{\rm m}^2(t)}\tag{24}$$

Comparing Eqs. (23) and (24) with Eqs. (14) and (20), respectively, one obtains

$$a\_{\mathbf{n}} = a\_{\mathbf{i}} = R\_{1\prime} b\_{\mathbf{n}} = \frac{R\_1 R\_4}{10 R\_2 R\_3 C\_{\mathbf{z}}}, b\_{\mathbf{i}} = \frac{R\_1 R\_3 R\_4 C\_{\mathbf{z}}}{10 R\_2} \tag{25}$$

At this point, our results indicate that by selecting adequately the numerical values of each element of Eq. (25) for a particular operating frequency, the emulator circuits of Figures 1(a) and 12(a) are able to generate normal and inverse pinched hysteresis loops, respectively. It is worth to stress that the transformation methodology is only applicable for those topologies where the integrator circuit is clearly defined, and when it is replaced by a differentiator circuit, the behaviour of the resulting emulator circuit, in general, is not modified. However, floating and grounded non-linear resistor emulator circuits without this requirement have also been reported in the literature [27–33]. One example of them was shown in Figure 7(a). However, whether C<sup>1</sup> is replaced by an inductor L<sup>1</sup> as shown in Figure 12(b), we get

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_2 L\_1}{40} \frac{di\_{\rm m}(t)}{dt} \tag{26}$$

Afterwards assuming that im(t) = Amsin(ωt + ϕ) and by considering Eqs. (14) and (20), Eqs. (8) and (26) take the form

$$\frac{v\_m(t)}{i\_\mathrm{m}(t)} = R\_1 \pm \frac{R\_2}{40C\_1\omega} \sqrt{A\_\mathrm{m}^2 - i\_\mathrm{m}^2(t)}\tag{27}$$

$$\frac{v\_{\rm m}(t)}{i\_{\rm m}(t)} = R\_1 \pm \frac{R\_2 L\_1 \omega}{40} \sqrt{A\_{\rm m}^2 - i\_{\rm m}^2(t)}\tag{28}$$

Comparing Eqs. (27) and (28) again with Eqs. (14) and (20), respectively, one obtains

$$a\_{\mathbf{n}} = a\_{\mathbf{i}} = R\_1, b\_{\mathbf{n}} = \frac{R\_2}{40\mathcal{C}\_1}, b\_{\mathbf{i}} = \frac{R\_2 L\_1}{40} \tag{29}$$

Figure 13. Frequency-dependent hysteresis loop of Figure 1(a) (blue line) and Figure 12(a) (red line) operating to: 1 kHz for (a) incremental and (b) decremental mode; 2 kHz for (c) incremental and (d) decremental mode; 4 kHz for (e)

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 131

incremental and (f) decremental mode.

Note that although the behaviour of the inductor can be emulated by using gyrators, the resulting circuit becomes bulky and complex. Hence, this transformation technique does not

Figure 12. Inverse versions of: (a) Figure 1(a) and (b) Figure 7(a).

<sup>a</sup><sup>n</sup> <sup>¼</sup> <sup>a</sup><sup>i</sup> <sup>¼</sup> <sup>R</sup>1, bn <sup>¼</sup> <sup>R</sup>1R<sup>4</sup>

10R2R3C<sup>z</sup>

At this point, our results indicate that by selecting adequately the numerical values of each element of Eq. (25) for a particular operating frequency, the emulator circuits of Figures 1(a) and 12(a) are able to generate normal and inverse pinched hysteresis loops, respectively. It is worth to stress that the transformation methodology is only applicable for those topologies where the integrator circuit is clearly defined, and when it is replaced by a differentiator circuit, the behaviour of the resulting emulator circuit, in general, is not modified. However, floating and grounded non-linear resistor emulator circuits without this requirement have also been reported in the literature [27–33]. One example of them was shown in Figure 7(a).

However, whether C<sup>1</sup> is replaced by an inductor L<sup>1</sup> as shown in Figure 12(b), we get

R2L<sup>1</sup> 40

q

q

40C<sup>1</sup>

Afterwards assuming that im(t) = Amsin(ωt + ϕ) and by considering Eqs. (14) and (20), Eqs. (8)

R2 40C1ω

R2L1ω 40

Note that although the behaviour of the inductor can be emulated by using gyrators, the resulting circuit becomes bulky and complex. Hence, this transformation technique does not

Comparing Eqs. (27) and (28) again with Eqs. (14) and (20), respectively, one obtains

<sup>a</sup><sup>n</sup> <sup>¼</sup> <sup>a</sup><sup>i</sup> <sup>¼</sup> <sup>R</sup>1, b<sup>n</sup> <sup>¼</sup> <sup>R</sup><sup>2</sup>

dimðtÞ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � i 2 <sup>m</sup>ðtÞ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi A2 <sup>m</sup> � i 2 <sup>m</sup>ðtÞ

, b<sup>i</sup> <sup>¼</sup> <sup>R</sup>2L<sup>1</sup>

dt <sup>ð</sup>26<sup>Þ</sup>

<sup>40</sup> <sup>ð</sup>29<sup>Þ</sup>

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

vmðtÞ <sup>i</sup>mðt<sup>Þ</sup> <sup>¼</sup> <sup>R</sup><sup>1</sup> �

Figure 12. Inverse versions of: (a) Figure 1(a) and (b) Figure 7(a).

and (26) take the form

130 Memristor and Memristive Neural Networks

, bi <sup>¼</sup> <sup>R</sup>1R3R4C<sup>z</sup> 10R<sup>2</sup>

ð25Þ

ð27Þ

ð28Þ

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 131

Figure 13. Frequency-dependent hysteresis loop of Figure 1(a) (blue line) and Figure 12(a) (red line) operating to: 1 kHz for (a) incremental and (b) decremental mode; 2 kHz for (c) incremental and (d) decremental mode; 4 kHz for (e) incremental and (f) decremental mode.

show any advantage with respect to the methodology mentioned above. Without loss of generality, only HSPICE results of Figures 1(a) and 12(a) configured at incremental mode will be shown on the left side of Figure 13, whereas that for the decremental configuration will be shown on the right side. In a first step, both emulator circuits were configured to f = 2 kHz. HSPICE results are illustrated in Figure 13(c) and (d) and it is evident that these hysteresis loops are almost similar. Later, the operating frequency was decreased to f = 1 kHz, and as one can observe in Figure 13(a) and (b), the hysteresis loops present the behaviour forecasted. Finally, the operating frequency of vm(t) was increased to f = 4 kHz, and hence, the behaviour of the hysteresis loops was inverted, as depicted in Figure 13(e) and (f). From all these figures, we can observe that for inverse non-linear resistors, the hysteresis loop becomes a straight line when the operating frequency decreases, whereas for normal non-linear resistors, this behaviour is achieved when the operating frequency increases. Note that although the topology of an inverse non-linear resistor shows a frequency-dependent pinched hysteresis loop, this cannot be considered as memristor emulator circuit, since the property of non-volatility is not satisfied. Table 1 gives the numerical value for each passive element.

s 2 þ 1 C1

is: <sup>f</sup> <sup>0</sup> <sup>¼</sup> <sup>1</sup> 2π

ffiffiffiffiffiffiffiffiffiffiffi W<sup>2</sup> R3C1C<sup>2</sup> q

1 R1 � 1 R3 � �<sup>s</sup> <sup>þ</sup>

Figure 14. (a) FSK modulator based on SMCO by using Figure 4(a); and (b) SIMULINK model of Eq. (30).

From Eq. (30), the condition of oscillation (CO) is: R<sup>3</sup> = R<sup>1</sup> and the frequency of oscillation (FO)

respectively. By merging Figure 4(b) with Eq. (30), a SIMULINK model can be built. Such model is depicted in Figure 14(b) where the voltage and current gains are unitary (i.e. A<sup>v</sup> = A<sup>i</sup> = 1). Note that the SMCO along with an incremental memductor is depicted in the upper part of Figure 14(b), whereas the SMCO along with a decremental memductor is illustrated in the bottom. More detailed analysis of Eq. (30) is found in [36]. For this application, the SMCO was designed with an oscillation centre frequency of f<sup>0</sup> = 577 kHz and hence, R<sup>1</sup> =1kΩ, R<sup>3</sup> = 942 Ω, C<sup>1</sup> = C<sup>2</sup> = 140 pF and W<sup>2</sup> = 0.33 mS. In order to vary the incremental memductance, a pulse train with 2 V of amplitude and pulse width of 3 μs is used to increase W2; whereas for the decremental memductance, a pulse of 0.3 V of amplitude and with the same pulse width mentioned before is used to decrease W2. For both cases, when negative pulses with the same amplitudes mentioned before are applied, both memductances return to their last state [32]. By applying these control signals in Figure 14(b), one obtains an FSK signal, as shown in Figure 15 (a) and (b). On these last figures and into the interval [0, 2 ms], the operating frequency of the FSK modulator is the same as SMCO. Next, when a positive digital signal is applied to the incremental and decremental memductor, the memductance increases or decreases, respectively. As a consequence, the FO of the SMCO also increases or decreases, as shown in Figure 15(a) and (b) into the interval [2 ms, 4 ms], approximately. Afterwards, by applying a negative digital signal to the memductors, the FSK modulator returns to its original FO.

W<sup>2</sup> R3C1C<sup>2</sup>

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291

. It is seen that CO and FO can independently be controlled by R<sup>1</sup> and W2,

ð30Þ

133


Table 1. Numerical variables of Eq. (25) and component list of Figures 1(a) and 12(a).

## 6. Analogue applications based on memristor emulator circuits

This section discusses three examples at the behavioural level of abstraction on the use of memristor emulator circuits in real analogue applications.

#### 6.1. Frequency-shift keying (FSK) modulator

Modulator circuits are important blocks in digital communications since they are used to convert a unipolar bit sequence in an appropriate form for modulation and transmission [34]. Among the modulator circuits, frequency-shift keying (FSK) modulation is a frequency modulation scheme in which digital information is transmitted through discrete frequency changes of a carrier wave. Thus, the higher frequency of the modulator is assigned to signal 1 and the lower frequency is assigned to signal 0 [35]. This behaviour can be achieved by using a singlememductor controlled sinusoidal oscillator (SMCO), as shown in Figure 14(a). Through routine analysis, we get

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 133

$$\mathbf{s}^2 + \frac{1}{C\_1} \left(\frac{1}{R\_1} - \frac{1}{R\_3}\right) \mathbf{s} + \frac{W\_2}{R\_3 C\_1 C\_2} \tag{30}$$

From Eq. (30), the condition of oscillation (CO) is: R<sup>3</sup> = R<sup>1</sup> and the frequency of oscillation (FO) is: <sup>f</sup> <sup>0</sup> <sup>¼</sup> <sup>1</sup> 2π ffiffiffiffiffiffiffiffiffiffiffi W<sup>2</sup> R3C1C<sup>2</sup> q . It is seen that CO and FO can independently be controlled by R<sup>1</sup> and W2, respectively. By merging Figure 4(b) with Eq. (30), a SIMULINK model can be built. Such model is depicted in Figure 14(b) where the voltage and current gains are unitary (i.e. A<sup>v</sup> = A<sup>i</sup> = 1). Note that the SMCO along with an incremental memductor is depicted in the upper part of Figure 14(b), whereas the SMCO along with a decremental memductor is illustrated in the bottom. More detailed analysis of Eq. (30) is found in [36]. For this application, the SMCO was designed with an oscillation centre frequency of f<sup>0</sup> = 577 kHz and hence, R<sup>1</sup> =1kΩ, R<sup>3</sup> = 942 Ω, C<sup>1</sup> = C<sup>2</sup> = 140 pF and W<sup>2</sup> = 0.33 mS. In order to vary the incremental memductance, a pulse train with 2 V of amplitude and pulse width of 3 μs is used to increase W2; whereas for the decremental memductance, a pulse of 0.3 V of amplitude and with the same pulse width mentioned before is used to decrease W2. For both cases, when negative pulses with the same amplitudes mentioned before are applied, both memductances return to their last state [32]. By applying these control signals in Figure 14(b), one obtains an FSK signal, as shown in Figure 15 (a) and (b). On these last figures and into the interval [0, 2 ms], the operating frequency of the FSK modulator is the same as SMCO. Next, when a positive digital signal is applied to the incremental and decremental memductor, the memductance increases or decreases, respectively. As a consequence, the FO of the SMCO also increases or decreases, as shown in Figure 15(a) and (b) into the interval [2 ms, 4 ms], approximately. Afterwards, by applying a negative digital signal to the memductors, the FSK modulator returns to its original FO.

show any advantage with respect to the methodology mentioned above. Without loss of generality, only HSPICE results of Figures 1(a) and 12(a) configured at incremental mode will be shown on the left side of Figure 13, whereas that for the decremental configuration will be shown on the right side. In a first step, both emulator circuits were configured to f = 2 kHz. HSPICE results are illustrated in Figure 13(c) and (d) and it is evident that these hysteresis loops are almost similar. Later, the operating frequency was decreased to f = 1 kHz, and as one can observe in Figure 13(a) and (b), the hysteresis loops present the behaviour forecasted. Finally, the operating frequency of vm(t) was increased to f = 4 kHz, and hence, the behaviour of the hysteresis loops was inverted, as depicted in Figure 13(e) and (f). From all these figures, we can observe that for inverse non-linear resistors, the hysteresis loop becomes a straight line when the operating frequency decreases, whereas for normal non-linear resistors, this behaviour is achieved when the operating frequency increases. Note that although the topology of an inverse non-linear resistor shows a frequency-dependent pinched hysteresis loop, this cannot be considered as memristor emulator circuit, since the property of non-volatility is not satis-

fied. Table 1 gives the numerical value for each passive element.

6. Analogue applications based on memristor emulator circuits

Table 1. Numerical variables of Eq. (25) and component list of Figures 1(a) and 12(a).

memristor emulator circuits in real analogue applications.

6.1. Frequency-shift keying (FSK) modulator

Figure 12(a) 20 kΩ

132 Memristor and Memristive Neural Networks

tine analysis, we get

This section discusses three examples at the behavioural level of abstraction on the use of

Variable A<sup>m</sup> a<sup>n</sup> = a<sup>i</sup> b<sup>n</sup> b<sup>i</sup> k<sup>n</sup> k<sup>i</sup> F = 1 kHz 2 10e3 3.14e7 0.19 0.99 025 F = 2 kHz 0.5 0.5 F = 4 kHz 0.25 0.99 Element R<sup>1</sup> R<sup>3</sup> R<sup>2</sup> R<sup>4</sup> R<sup>5</sup> C<sup>z</sup> Figure 1(a) 10 kΩ 3.18 kΩ 100 kΩ 10 nF

Modulator circuits are important blocks in digital communications since they are used to convert a unipolar bit sequence in an appropriate form for modulation and transmission [34]. Among the modulator circuits, frequency-shift keying (FSK) modulation is a frequency modulation scheme in which digital information is transmitted through discrete frequency changes of a carrier wave. Thus, the higher frequency of the modulator is assigned to signal 1 and the lower frequency is assigned to signal 0 [35]. This behaviour can be achieved by using a singlememductor controlled sinusoidal oscillator (SMCO), as shown in Figure 14(a). Through rou-

Figure 14. (a) FSK modulator based on SMCO by using Figure 4(a); and (b) SIMULINK model of Eq. (30).

Since the integral and derivative parts of the continuous PID controller are, in practice, designed with R-C elements and active devices [27], one can obtain R<sup>i</sup> = R<sup>d</sup> =2kΩ, C<sup>i</sup> = 5 nF and C<sup>d</sup> = 1 μF. Under this assumption, Figure 4(b), the PID controller and Eq. (31) are merged to build a SIMULINK model. It is worth mentioning that the memductor shown in Figure 4(b) was configured to operate at 300 Hz. Thus, Figure 16 shows all feedback systems to be simulated [39]. In the upper part of Figure 16, the plant with feedback is illustrated. In the second block, the PID controller with fixed parameters along with the plant is depicted. The third block is the PID controller based on incremental memductor along with the plant; and finally, the fourth block depicts the PID controller based on decremental memductor along with the plant. For the last two cases, the memductance is varied by applying a pulse train, and a square signal with 5 V of amplitude and f = 200 Hz is applied to all feedback systems. Figure 17 shows all the transient responses of Figure 16. As a first step, the square signal (magenta line) is applied to the feedback plant, and its transient response is underdamped (green line), as shown in Figure 17(a). Hence, the plant needs to be controlled. In a second step, the transient response of the second block is obtained and shown in Figure 17(a) (black line). Here, the rise- and fall-time are symmetric and cannot be modified online. In order to get that effect, the incremental and decremental memductor is used [39]. For both memductances, the

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pulse train was adjusted to get the following cases:

Figure 16. PID controller based on memductors.

Figure 15. Time response of the FSK modulator using: (a) incremental memductor and (b) decremental memductor.

Therefore, we can observe that a memductor (or memristor) device is useful for controlling the FO of a SMCO and they can be used to design an FSK modulator.

#### 6.2. Proportional-integral-derivative (PID) controller

Proportional-integral-derivative (PID) control has been used successfully for regulating processes in industry for more than 60 years, due to its simple and easy design, low cost and wide range of applications. A PID controller involves three parts: proportional part, integral part and derivative part, and its target is to minimize the error between the set point and the measured output. It is worth mentioning that for a complex or non-linear process, sometimes it is very difficult to find the optimal parameters of the PID controller.

In this sense, the oldest and simplest method was proposed by Ziegler and Nichols [37]. However, this tuning method provides a large overshoot and settling time, and hence, the PID parameters must subsequently be refined. Other methods that can also be used for choosing the parameters of PID controller were reported in [38]. However, this method presents drawbacks when applied to certain types of plants. Furthermore, the PID parameters are always constant and almost without knowledge of the process to control. Therefore, an efficient and effective online tuning mechanism is widely demanded. This last task can be achieved by using a memristor/memductor, since its memristance/memductance can be kept even when the current flow in the memristor/memductor is stopped [1, 28–33, 35]. This property asserts that it is possible to update the parameters of a continuous PID controller online, i.e. the proportional gain (kp), integral gain1 (ki) and derivative gain (kd). In order to illustrate this idea, the transient response of a second-order low-pass filter is controlled by a PID controller [39]. The transfer function of the filter is given by

$$H(s) = \frac{\frac{1}{L\overline{C}}}{s^2 + \frac{s}{\overline{R}\overline{C}} + \frac{1}{LC}}\tag{31}$$

The numeric value of each element of Eq. (31) is R = 100 Ω, L = 0.475 mH, and C = 1 μF. At this point, the PID controller parameters, k<sup>p</sup> = 80, k<sup>i</sup> = 1e5 and k<sup>d</sup> = 2e-3, were obtained according to [37].

<sup>1</sup> This parameter should not be confused with k<sup>i</sup> parameter associated to the inverse nonlinear resistor.

Since the integral and derivative parts of the continuous PID controller are, in practice, designed with R-C elements and active devices [27], one can obtain R<sup>i</sup> = R<sup>d</sup> =2kΩ, C<sup>i</sup> = 5 nF and C<sup>d</sup> = 1 μF. Under this assumption, Figure 4(b), the PID controller and Eq. (31) are merged to build a SIMULINK model. It is worth mentioning that the memductor shown in Figure 4(b) was configured to operate at 300 Hz. Thus, Figure 16 shows all feedback systems to be simulated [39]. In the upper part of Figure 16, the plant with feedback is illustrated. In the second block, the PID controller with fixed parameters along with the plant is depicted. The third block is the PID controller based on incremental memductor along with the plant; and finally, the fourth block depicts the PID controller based on decremental memductor along with the plant. For the last two cases, the memductance is varied by applying a pulse train, and a square signal with 5 V of amplitude and f = 200 Hz is applied to all feedback systems. Figure 17 shows all the transient responses of Figure 16. As a first step, the square signal (magenta line) is applied to the feedback plant, and its transient response is underdamped (green line), as shown in Figure 17(a). Hence, the plant needs to be controlled. In a second step, the transient response of the second block is obtained and shown in Figure 17(a) (black line). Here, the rise- and fall-time are symmetric and cannot be modified online. In order to get that effect, the incremental and decremental memductor is used [39]. For both memductances, the pulse train was adjusted to get the following cases:

Figure 16. PID controller based on memductors.

Therefore, we can observe that a memductor (or memristor) device is useful for controlling the

Figure 15. Time response of the FSK modulator using: (a) incremental memductor and (b) decremental memductor.

Proportional-integral-derivative (PID) control has been used successfully for regulating processes in industry for more than 60 years, due to its simple and easy design, low cost and wide range of applications. A PID controller involves three parts: proportional part, integral part and derivative part, and its target is to minimize the error between the set point and the measured output. It is worth mentioning that for a complex or non-linear process, sometimes it is very

In this sense, the oldest and simplest method was proposed by Ziegler and Nichols [37]. However, this tuning method provides a large overshoot and settling time, and hence, the PID parameters must subsequently be refined. Other methods that can also be used for choosing the parameters of PID controller were reported in [38]. However, this method presents drawbacks when applied to certain types of plants. Furthermore, the PID parameters are always constant and almost without knowledge of the process to control. Therefore, an efficient and effective online tuning mechanism is widely demanded. This last task can be achieved by using a memristor/memductor, since its memristance/memductance can be kept even when the current flow in the memristor/memductor is stopped [1, 28–33, 35]. This property asserts that it is possible to update the parameters of a continuous PID controller online, i.e. the proportional gain (kp), integral gain1 (ki) and derivative gain (kd). In order to illustrate this idea, the transient response of a second-order low-pass filter is

controlled by a PID controller [39]. The transfer function of the filter is given by

HðsÞ ¼

This parameter should not be confused with k<sup>i</sup> parameter associated to the inverse nonlinear resistor.

1 LC <sup>s</sup><sup>2</sup> <sup>þ</sup> <sup>s</sup> RC <sup>þ</sup> <sup>1</sup> LC

The numeric value of each element of Eq. (31) is R = 100 Ω, L = 0.475 mH, and C = 1 μF. At this point, the PID controller parameters, k<sup>p</sup> = 80, k<sup>i</sup> = 1e5 and k<sup>d</sup> = 2e-3, were obtained according to [37].

ð31Þ

FO of a SMCO and they can be used to design an FSK modulator.

6.2. Proportional-integral-derivative (PID) controller

134 Memristor and Memristive Neural Networks

difficult to find the optimal parameters of the PID controller.

1

complex brain tasks and functions related to learning and memory. Emulation of biological synapses is the basis to build large-scale brain-inspired systems [40]. A key property of the brain is its ability to learn, this process lies in the plasticity of the synapses that allows the nervous system to adapt. Memristor is a candidate suitable to emulate a synapse, due to its non-volatility property and programmable device. But a single memristor cannot accomplish this task; in fact, there are several topologies that enable this behaviour, depending on the approach used for artificial neural network, i.e. cellular neural networks (CNN) [41], spiking neural networks (SNN) [42, 43], feed-forward neural networks (FFNN) [44] and recurrent neural networks (RNN) [45]. Few architectures based on memristors are focused on feed-forward artificial neural networks, which completely satisfies the requirements of an artificial synapse. On the other

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2. The synapse must be computed as an output, i.e. the product of the input signal with the

5. Each synapse must be capable of implementing a learning rule such as Hebbian or Back

Table 2 shows a comparison among the most recent memristive neural networks. Thus, the third column of the table shows whether design meets the five rules mentioned before, such that the synapse can be considered as learning synapse. Design of [41] does not meet rule 5, since to change a negative weight to positive not only additional circuitries is required, but on line training is not also possible; [43] meets some of the properties of [46], because it is implemented through an ideal memristor model whose applications are limited to simulations; [44] uses a high number of active components (i.e. 64) for building a synapse, considering the memristor emulator reported in [49]. The fourth column is the frequency of the spikes for SNN approach and for the case of MCNN and ANN the time for weight setting from its lowest to the highest value is described. If weight setting time is too long, then weight processing will take longer which affects its performance. Thus, only [44] simulates and fully implements a synapse based on a memristor emulator. Unlike [41, 42, 47], its hardware applications are not limited to HP memristor fabrication, but the number of elements and the operating frequency are parameters that restrict its performance. However, frequency is limited and the number of active components is high. On the other hand, the proposed synaptic memristive bridge circuit begins with the analysis of memristance of the flux-controlled memristor of Figure 1(a). First, memristance variation of Figure 1(a) is analysed,

The maximum value of memristance for an incremental memristor is: Minc ¼ R<sup>1</sup> þ R1k<sup>n</sup> and

MðφmðtÞÞ ¼ R<sup>1</sup> � R1αφmðtÞ ð32Þ

hand, there are several requirements that must be met for a synaptic learning [46]:

1. The weight must be stored always in the absence of learning.

synaptic weight also called synaptic weighting.

4. Each synapse must operate with low power dissipation.

the minimum is Minc ¼ R<sup>1</sup> � R1kn, as shown in Figure 18(a).

3. Each synapse must occupy a reduced area.

propagation [1, 40, 46].

where Eq. (1) can be rewritten as

Figure 17. (a) Transient response of the plant and PID controllers. (b) Pulse train for controlling the incremental and decremental memductance.


Therefore, we can observe that memristors/memductors are useful for controlling the rise- and fall-time of the transient response of a feedback system.

#### 6.3. Memristive synapses

As a last example, but not the least important, we describe the analysis and design of a synaptic circuit based on memristors. Basically, synapses are specialized sites where several neurons are connected, which receive and send information from other cells; this junction is the foundation of complex brain tasks and functions related to learning and memory. Emulation of biological synapses is the basis to build large-scale brain-inspired systems [40]. A key property of the brain is its ability to learn, this process lies in the plasticity of the synapses that allows the nervous system to adapt. Memristor is a candidate suitable to emulate a synapse, due to its non-volatility property and programmable device. But a single memristor cannot accomplish this task; in fact, there are several topologies that enable this behaviour, depending on the approach used for artificial neural network, i.e. cellular neural networks (CNN) [41], spiking neural networks (SNN) [42, 43], feed-forward neural networks (FFNN) [44] and recurrent neural networks (RNN) [45]. Few architectures based on memristors are focused on feed-forward artificial neural networks, which completely satisfies the requirements of an artificial synapse. On the other hand, there are several requirements that must be met for a synaptic learning [46]:


1. By using an incremental memductor, the rise-time (red line) of the system is largest than the rise-time gotten with fixed parameters (black line) and those obtained with the decremental memductor (blue line). In fact, the rise-time of the latter is the shortest, as depicted

Figure 17. (a) Transient response of the plant and PID controllers. (b) Pulse train for controlling the incremental and

2. By using a decremental memductor, the fall-time (blue line) of the system is largest than the fall-time gotten with fixed parameters (black line) and those obtained with the incremental memductor (red line). In fact, the fall-time of the latter is the shortest, as shown in

3. In order to get the same rise-time in all cases, both memductances were adjusted by using the pulse train shown in Figure 17(b), and the result can be observed in Figure 17(a) at

Therefore, we can observe that memristors/memductors are useful for controlling the rise- and

As a last example, but not the least important, we describe the analysis and design of a synaptic circuit based on memristors. Basically, synapses are specialized sites where several neurons are connected, which receive and send information from other cells; this junction is the foundation of

in Figure 17(a).

decremental memductance.

136 Memristor and Memristive Neural Networks

Figure 17(a).

5.5 ms, approximately.

6.3. Memristive synapses

fall-time of the transient response of a feedback system.


Table 2 shows a comparison among the most recent memristive neural networks. Thus, the third column of the table shows whether design meets the five rules mentioned before, such that the synapse can be considered as learning synapse. Design of [41] does not meet rule 5, since to change a negative weight to positive not only additional circuitries is required, but on line training is not also possible; [43] meets some of the properties of [46], because it is implemented through an ideal memristor model whose applications are limited to simulations; [44] uses a high number of active components (i.e. 64) for building a synapse, considering the memristor emulator reported in [49]. The fourth column is the frequency of the spikes for SNN approach and for the case of MCNN and ANN the time for weight setting from its lowest to the highest value is described. If weight setting time is too long, then weight processing will take longer which affects its performance. Thus, only [44] simulates and fully implements a synapse based on a memristor emulator. Unlike [41, 42, 47], its hardware applications are not limited to HP memristor fabrication, but the number of elements and the operating frequency are parameters that restrict its performance. However, frequency is limited and the number of active components is high. On the other hand, the proposed synaptic memristive bridge circuit begins with the analysis of memristance of the flux-controlled memristor of Figure 1(a). First, memristance variation of Figure 1(a) is analysed, where Eq. (1) can be rewritten as

$$M(\varphi\_{\mathfrak{m}}(t)) = R\_1 \pm R\_1 \alpha \varphi\_{\mathfrak{m}}(t) \tag{32}$$

The maximum value of memristance for an incremental memristor is: Minc ¼ R<sup>1</sup> þ R1k<sup>n</sup> and the minimum is Minc ¼ R<sup>1</sup> � R1kn, as shown in Figure 18(a).


Table 2. Comparison among memristive neural networks.

Figure 18. (a) Incremental and decremental memristance when v<sup>m</sup> = Amsin(ωt, ). (b) Simulation results of memristance for A<sup>m</sup> = 2 V, f = 8 kHz and k<sup>n</sup> = 0.8.

negative pulse is applied, an inverted behaviour is glimpsed. Whether the pulse width is wide enough, the output voltage vAB = v<sup>A</sup> � v<sup>B</sup> varies gradually from negative to positive voltages and vice versa. Therefore, the memristances M1(ϕm(t)) and M2(ϕm(t)) are varied within v<sup>m</sup> � v<sup>A</sup> and v<sup>m</sup> � v<sup>B</sup> voltages, respectively. For synapse design, first the voltage v<sup>2</sup> was considered and it is

> ðt 0

ðtÞ, ν<sup>A</sup> ¼ νmðtÞαφ<sup>M</sup><sup>1</sup>

ðt 0

vmðτÞdτ ð33Þ

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 139

ðtÞ ð34Þ

vmðτÞvðτÞBdτ ð35Þ

v<sup>2</sup> ¼ �v1α

Element R<sup>1</sup> R<sup>2</sup> = R<sup>4</sup> R<sup>3</sup> C<sup>z</sup> F = 8 kHz 10 kΩ 100 kΩ 1.97 kΩ 2.5 nF f = 10kHz 2 nF f = 5kHz 3 kΩ 2.652 nF

Table 3. Component list of Figure 1(a) configured in several operating frequencies.

vmðτÞ � vðτÞAdτ, ϕM2 ¼

v<sup>A</sup> ¼ �vmðtÞαφM2

Figure 19. (a) Synaptic memristive bridge and (b) SIMULINK model of Eqs. (34)–(38).

Hence, considering Eq. (33), v<sup>A</sup> and v<sup>B</sup> are redefined as

where the magnetic flux of each memristor is

Hence, vAB and ξ, the weight, are obtained as

ϕM1 ¼

ðt 0

described by

Considering that k<sup>n</sup> ∈ (0, 1), it is preferable to use k<sup>n</sup> ! 1 to assure more range of variation; however, it is necessary to recall that memristance value is limited. In this frame of reference, several tests varying k<sup>n</sup> were performed in HSPICE with incremental and decremental memristors tested separately and in different operating frequencies, as shown in Figure 18(b). Nevertheless, secondary effects are observed when varying k<sup>n</sup> ! 0.8, and therefore, the memristors have a different behaviour compared with Figure 18(a), since in this case, the incremental and decremental memristance vary within the same range of memristance. In order to obtain the same behaviour of memristance from Figure 1(a) and for several operating frequencies, each discrete element must be updated according to Table 3. Note that the proposed topology takes advantage of memristance behaviour and uses only two flux-controlled floating memristor emulators, M1(ϕm(t)), configured as decremental and M2(ϕm(t)) as an incremental memristor, along with two passive resistors R<sup>a</sup> = R<sup>b</sup> = 10 kΩ, as shown in Figure 19(a) [50]. The analysis of Figure 19(a) is as follows: when a positive pulse is applied, M1(φm(t)) decreases and M2(φm(t)) increases. As a consequence, v<sup>B</sup> decreases and v<sup>A</sup> increases. Moreover, when a


Table 3. Component list of Figure 1(a) configured in several operating frequencies.

Figure 19. (a) Synaptic memristive bridge and (b) SIMULINK model of Eqs. (34)–(38).

negative pulse is applied, an inverted behaviour is glimpsed. Whether the pulse width is wide enough, the output voltage vAB = v<sup>A</sup> � v<sup>B</sup> varies gradually from negative to positive voltages and vice versa. Therefore, the memristances M1(ϕm(t)) and M2(ϕm(t)) are varied within v<sup>m</sup> � v<sup>A</sup> and v<sup>m</sup> � v<sup>B</sup> voltages, respectively. For synapse design, first the voltage v<sup>2</sup> was considered and it is described by

$$
\sigma\_2 = \pm \upsilon\_1 \alpha \int\_0^t \upsilon\_m(\tau) d\tau \tag{33}
$$

Hence, considering Eq. (33), v<sup>A</sup> and v<sup>B</sup> are redefined as

$$
\upsilon\_{\mathcal{A}} = -\upsilon\_{\mathfrak{m}}(t)a\wp\_{\mathcal{M}\_2}(t), \ \upsilon\_{\mathcal{A}} = \upsilon\_{\mathfrak{m}}(t)a\wp\_{\mathcal{M}\_1}(t) \tag{34}
$$

where the magnetic flux of each memristor is

Considering that k<sup>n</sup> ∈ (0, 1), it is preferable to use k<sup>n</sup> ! 1 to assure more range of variation; however, it is necessary to recall that memristance value is limited. In this frame of reference, several tests varying k<sup>n</sup> were performed in HSPICE with incremental and decremental memristors tested separately and in different operating frequencies, as shown in Figure 18(b). Nevertheless, secondary effects are observed when varying k<sup>n</sup> ! 0.8, and therefore, the memristors have a different behaviour compared with Figure 18(a), since in this case, the incremental and decremental memristance vary within the same range of memristance. In order to obtain the same behaviour of memristance from Figure 1(a) and for several operating frequencies, each discrete element must be updated according to Table 3. Note that the proposed topology takes advantage of memristance behaviour and uses only two flux-controlled floating memristor emulators, M1(ϕm(t)), configured as decremental and M2(ϕm(t)) as an incremental memristor, along with two passive resistors R<sup>a</sup> = R<sup>b</sup> = 10 kΩ, as shown in Figure 19(a) [50]. The analysis of Figure 19(a) is as follows: when a positive pulse is applied, M1(φm(t)) decreases and M2(φm(t)) increases. As a consequence, v<sup>B</sup> decreases and v<sup>A</sup> increases. Moreover, when a

Figure 18. (a) Incremental and decremental memristance when v<sup>m</sup> = Amsin(ωt, ). (b) Simulation results of memristance for

Reference Approach Learning synapse Frequency (Hz) Memristor Active devices

[44] FFNN Yes 142 Emulator 69 5 [47] SNN 5 2 3 [43] 30 HP model 2 13 [42] 300 2 8 [48] 100 – – [41] MCNN No 0.71 1 1 [45] RNN Yes 1 – 1

Synapse Neuron

A<sup>m</sup> = 2 V, f = 8 kHz and k<sup>n</sup> = 0.8.

Table 2. Comparison among memristive neural networks.

138 Memristor and Memristive Neural Networks

$$\boldsymbol{\phi}\_{\mathbf{M}\_{1}} = \int\_{0}^{t} \boldsymbol{v}\_{\mathbf{m}}(\boldsymbol{\tau}) - \boldsymbol{v}(\boldsymbol{\tau})\_{\mathbf{A}} \, \mathrm{d}\boldsymbol{\tau}, \ \boldsymbol{\phi}\_{\mathbf{M}\_{2}} = \int\_{0}^{t} \boldsymbol{v}\_{\mathbf{m}}(\boldsymbol{\tau}) \boldsymbol{v}(\boldsymbol{\tau})\_{\mathbf{B}} \, \mathrm{d}\boldsymbol{\tau} \tag{35}$$

Hence, vAB and ξ, the weight, are obtained as

$$
\sigma\_{\rm AB} = a \upsilon\_{\rm m} \left( \phi\_{M\_1}(\mathbf{t}) + \phi\_{M\_2}(\mathbf{t}) \right), \ \xi = \frac{\upsilon\_{\rm AB}}{\upsilon\_{\rm m}} = a \left( \phi\_{M\_1}(\mathbf{t}) + \phi\_{M\_2}(\mathbf{t}) \right) \tag{36}
$$

Memristance variation for M2(ϕm(t)) is

$$M\_2\left(\phi\_{\mathcal{M}\_2}(\mathbf{t})\right) = R\_1 + R\_1 \mathfrak{a} \phi\_{\mathcal{M}\_2}(\mathbf{t})\tag{37}$$

Similarly, memristance variation for M1(ϕm(t)) is:

$$M\_1(\phi\_{\mathcal{M}\_1}(\mathbf{t})) = R\_1 + R\_1 \alpha \phi\_{\mathcal{M}\_1}(\mathbf{t}) \tag{38}$$

Figure 20. Memristance variations of Figure 19(a) when the bi-pulse signal <sup>v</sup><sup>m</sup> <sup>=</sup> 2 V at 8 kHz is applied: (a) MATLAB®

Memristor Emulator Circuit Design and Applications http://dx.doi.org/10.5772/intechopen.69291 141

Figure 21. <sup>ξ</sup> variations of Figure 19(a) when the bi-pulse signal <sup>v</sup><sup>m</sup> <sup>=</sup> 2 V at 8 kHz in (a) MATLAB® and (b) HSPICE®.

Figure 22. Synaptic multiplication when ξ = 0.8495 and a pulse signal v<sup>p</sup> = 1.5 V of amplitude with pulse width of 200 ns is

applied: (a) MATLAB results and (b) HSPICE simulations.

and (b) HSPICE®.

As observed in Eqs. (37) and (38), the memristances depend on Eq. (35) and each memristor in the synapse is designed with the same parameters, so their memristances vary at same rate. From Eqs. (34)–(38), a SIMULINK model is built and depicted in Figure 19(b). The synaptic memristive bridge was simulated in HSPICE and numerical simulations of Figure 19(b) were obtained at MATLAB. Thus, the memristance variation M1ðϕ<sup>M</sup><sup>1</sup> ðtÞÞ and M2ðϕ<sup>M</sup><sup>2</sup> ðtÞ are shown in Figure 20, respectively. The vAB voltage for k<sup>n</sup> = 0.8 behave as sawtooth wave, as seen in Figure 21, and ξ is approximated by

$$\xi = \begin{cases} 49077t - 1.5338 & 0 \ge t \ge \overline{\eta}\_2' \\ -48567 + 4.5373 & \overline{\eta}\_2' \ge t \ge T \end{cases} \tag{39}$$

whose confidence level is <sup>Q</sup><sup>2</sup> = 0.996. This value represents the linearity of <sup>ξ</sup>, if <sup>Q</sup><sup>2</sup> ! 1 means that there is a linear relation between input pulses and ξ. To verify the behaviour of the synaptic memristive bridge, three basic steps are performed [44, 46].


vAB ¼ αv<sup>m</sup>

Similarly, memristance variation for M1(ϕm(t)) is:

Memristance variation for M2(ϕm(t)) is

140 Memristor and Memristive Neural Networks

Figure 21, and ξ is approximated by

negative ξ is configured.

and st = 200 ns.

width is 2.5 μs which sets ξ = �0.8495.

� ϕ<sup>M</sup><sup>1</sup>

ðtÞ þ ϕ<sup>M</sup><sup>2</sup>

M<sup>2</sup> � ϕM2 ðtÞ �

M<sup>1</sup> � ϕM1 ðtÞ �

obtained at MATLAB. Thus, the memristance variation M1ðϕ<sup>M</sup><sup>1</sup>

(

synaptic memristive bridge, three basic steps are performed [44, 46].

ðtÞ �

, <sup>ξ</sup> <sup>¼</sup> <sup>v</sup>AB v<sup>m</sup>

¼ R<sup>1</sup> þ R1αϕ<sup>M</sup><sup>2</sup>

¼ R<sup>1</sup> þ R1αϕ<sup>M</sup><sup>1</sup>

As observed in Eqs. (37) and (38), the memristances depend on Eq. (35) and each memristor in the synapse is designed with the same parameters, so their memristances vary at same rate. From Eqs. (34)–(38), a SIMULINK model is built and depicted in Figure 19(b). The synaptic memristive bridge was simulated in HSPICE and numerical simulations of Figure 19(b) were

in Figure 20, respectively. The vAB voltage for k<sup>n</sup> = 0.8 behave as sawtooth wave, as seen in

<sup>ξ</sup> <sup>¼</sup> <sup>49077</sup><sup>t</sup> � <sup>1</sup>:5338 0 <sup>≥</sup> <sup>t</sup> <sup>≥</sup> <sup>T</sup>=<sup>2</sup> �48567 þ 4:5373 <sup>T</sup>=<sup>2</sup> ≥ t ≥ T

whose confidence level is <sup>Q</sup><sup>2</sup> = 0.996. This value represents the linearity of <sup>ξ</sup>, if <sup>Q</sup><sup>2</sup> ! 1 means that there is a linear relation between input pulses and ξ. To verify the behaviour of the

1. Sign setting. This stage refers to configure a positive sing or negative weight, and assures that ξ is within the desired range. Therefore, a bi-pulse signal with v<sup>m</sup> = �2 V of amplitude configured at several frequencies is applied, as depicted in Figure 22. To configure a positive sign, it is necessary to apply a falling edge pulse, when a rising edge pulse is applied, a

2. Weight setting. Once the sign is established, it is necessary to apply a pulse width to set weight of the synapse. For the case 8 kHz, the allowed maximum pulse width is 62.5 μs, in the general case it is T/2. Therefore, pulse signal v<sup>m</sup> with pulse width of range (0, T/2) is applied to set the weight to a desired ξ. In Figure 22 a pulse v<sup>m</sup> is shown whose pulse

3. Synaptic weight processing. This operation refers to perform vs = ξvp, which is the multiplication of a narrow input pulse vp and the pre-established ξ weight. The pulse width of v<sup>p</sup> is narrow due to an effect called memristance drifting which is drifting of flux accumulation φM1 and φ<sup>M</sup><sup>1</sup> caused by v<sup>p</sup> [1, 40]. However, the response to that narrow pulse is governed by the settling time (st) and slew rate (SR) of multiplier AD633 used in the memristor emulator circuit, whose st = 2 μs at output voltage V<sup>0</sup> = 20 V and SR of 20 V/μs. The AD633 can be replaced by AD734 multiplier whose SR = 450 V/μs at V<sup>0</sup> = 20 V

¼ α ϕ<sup>M</sup><sup>1</sup>

ðtÞ þ ϕ<sup>M</sup><sup>2</sup>

� �

ðtÞ

ðtÞ ð37Þ

ðtÞ ð38Þ

ðtÞÞ and M2ðϕ<sup>M</sup><sup>2</sup>

ð36Þ

ðtÞ are shown

ð39Þ

Figure 20. Memristance variations of Figure 19(a) when the bi-pulse signal <sup>v</sup><sup>m</sup> <sup>=</sup> 2 V at 8 kHz is applied: (a) MATLAB® and (b) HSPICE®.

Figure 21. <sup>ξ</sup> variations of Figure 19(a) when the bi-pulse signal <sup>v</sup><sup>m</sup> <sup>=</sup> 2 V at 8 kHz in (a) MATLAB® and (b) HSPICE®.

Figure 22. Synaptic multiplication when ξ = 0.8495 and a pulse signal v<sup>p</sup> = 1.5 V of amplitude with pulse width of 200 ns is applied: (a) MATLAB results and (b) HSPICE simulations.

Finally, Figure 22(a) presents a MATLAB simulation of a pulse v<sup>p</sup> = 2 V whose pulse width is 200 ns. This pulse is multiplied by ξ, obtaining v<sup>s</sup> = 1.699. On the other hand, the synaptic weight processing at HSPICE shown in Figure 22(b) is done following the same methodology [50].

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## 7. Conclusion

Memristor emulator circuits are useful for developing real memristor-based application circuits as well as for educational purposes. In this chapter, we have studied three memristor/ memductor emulator circuits whose behaviour can be configured as incremental or decremental. Two of them are grounded versions whereas the latter is floated. The behavioural model for each topology was derived and its SIMULINK model was also programmed. The design guide suggested in this chapter provides a systematic way for designing memristor/memductor emulator circuits with good features. Further, an offset compensation technique was also described in order to achieve the frequency-dependent pinched hysteresis loop that does not deviate of the origin when the operating frequency of the input signal increases. As a result, it is predicted that the frequency behaviour of the pinched hysteresis loops of memristor/memductor emulator circuits can be pushed for operating in higher frequencies and holding a symmetrical behaviour, since the offset voltage glimpsed can again be reduced by updating the DC voltage sources. Moreover, a transformation methodology for obtaining the behaviour of inverse non-linear resistors from normal non-linear resistors has also been described, and as it was observed in Section 5, the methodology consists in replacing the integrator circuit, clearly defined in the normal topologies by a differentiator circuit, so that not only an inverse behaviour is obtained, but also the resulting topology is not drastically modified with respect to the original topology. Finally, three real analogue applications based on memristors/memductors were addressed.

## Acknowledgements

This work was supported in part by the National Council for Science and Technology (CONACyT), Mexico, under Grant 222843 and in part by the Program to Strengthen Quality in Educational Institutions, under Grant C/PFCE-2016-29MSU0013Y-07-23.

## Author details

Carlos Sánchez-López<sup>1</sup> \*, Illiani Carro-Pérez<sup>2</sup> , Victor Hugo Carbajal-Gómez<sup>1</sup> , Miguel Angel Carrasco-Aguilar<sup>1</sup> and Francisco Epimenio Morales-López<sup>1</sup>

\*Address all correspondence to: carlsanmx@yahoo.com.mx


## References

Finally, Figure 22(a) presents a MATLAB simulation of a pulse v<sup>p</sup> = 2 V whose pulse width is 200 ns. This pulse is multiplied by ξ, obtaining v<sup>s</sup> = 1.699. On the other hand, the synaptic weight processing at HSPICE shown in Figure 22(b) is done following the same methodology [50].

Memristor emulator circuits are useful for developing real memristor-based application circuits as well as for educational purposes. In this chapter, we have studied three memristor/ memductor emulator circuits whose behaviour can be configured as incremental or decremental. Two of them are grounded versions whereas the latter is floated. The behavioural model for each topology was derived and its SIMULINK model was also programmed. The design guide suggested in this chapter provides a systematic way for designing memristor/memductor emulator circuits with good features. Further, an offset compensation technique was also described in order to achieve the frequency-dependent pinched hysteresis loop that does not deviate of the origin when the operating frequency of the input signal increases. As a result, it is predicted that the frequency behaviour of the pinched hysteresis loops of memristor/memductor emulator circuits can be pushed for operating in higher frequencies and holding a symmetrical behaviour, since the offset voltage glimpsed can again be reduced by updating the DC voltage sources. Moreover, a transformation methodology for obtaining the behaviour of inverse non-linear resistors from normal non-linear resistors has also been described, and as it was observed in Section 5, the methodology consists in replacing the integrator circuit, clearly defined in the normal topologies by a differentiator circuit, so that not only an inverse behaviour is obtained, but also the resulting topology is not drastically modified with respect to the original topology. Finally, three real analogue applications based on memristors/memductors were addressed.

This work was supported in part by the National Council for Science and Technology (CONACyT), Mexico, under Grant 222843 and in part by the Program to Strengthen Quality

, Victor Hugo Carbajal-Gómez<sup>1</sup>

,

in Educational Institutions, under Grant C/PFCE-2016-29MSU0013Y-07-23.

\*, Illiani Carro-Pérez<sup>2</sup>

\*Address all correspondence to: carlsanmx@yahoo.com.mx

Miguel Angel Carrasco-Aguilar<sup>1</sup> and Francisco Epimenio Morales-López<sup>1</sup>

1 Department of Electronics, Autonomous University of Tlaxcala, Tlaxcala, Mexico

2 Department of Mechatronics, Technological Institute of Monterrey, Puebla Campus, Mexico

7. Conclusion

142 Memristor and Memristive Neural Networks

Acknowledgements

Author details

Carlos Sánchez-López<sup>1</sup>


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[46] Hasler P, Diorio C, Minch BA, Mead C. Single transistor learning synapse with long term storage. Proceedings IEEE International Symposium on Circuits and Systems. 1995;1(1): 1660-1663

**Chapter 7**

**Provisional chapter**

**Simulating Memristive Networks in SystemC-AMS**

This chapter presents a solution for the simulation of large memristive networks with SystemC-AMS. SystemC-AMS allows simulating memristors both on analogue level and on digital level to link analogue memristive devices to digital circuits and system level specifications. We investigate the benefits and drawbacks of a SystemC-AMS simulation compared to a simulation in SPICE. We show for the example of a two-layer memristive network emulating an optical flow algorithm by the detection of moving edges that large memristive networks can be simulated with a free available SystemC-AMS simulation environment, whereas free available SPICE simulation environment fails. However, it is also shown that commercial SPICE simulators are superior against current SystemC-AMS implementations concerning the size of simulated memristive networks. However, SystemC-AMS simulations of memristive networks offer both still more flexibility and similar run times compared to commercial SPICE simulators for small-sized memristive networks. The flexibility and the powerfulness of a SystemC-AMS solution is demonstrated for a complex network that solves edge detection, filtering and detecting of moving objects. The possible run times of the memristive network are determined in the SystemC-AMS simulation environment and are compared with an optical flow algorithm

**Simulating Memristive Networks in SystemC-AMS**

DOI: 10.5772/intechopen.69662

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

One of the missing things in the research on modelling and simulation of large memristor networks is the availability of an adequate simulation system, which is both fast and flexible. Available SPICE models offer for commercial products, for example, Spectre Circuit Simulator,

**Keywords:** memristive networks, SystemC-AMS, memristor modelling, optical flow,

Dietmar Fey, Lukas Riedersberger and

Dietmar Fey, Lukas Riedersberger and

http://dx.doi.org/10.5772/intechopen.69662

Additional information is available at the end of the chapter

on classical hardware like a CPU and a GPU.

SPICE memristor simulation

**1. Introduction**

Additional information is available at the end of the chapter

Marc Reichenbach

**Abstract**

Marc Reichenbach


**Provisional chapter**

## **Simulating Memristive Networks in SystemC-AMS**

**Simulating Memristive Networks in SystemC-AMS**

DOI: 10.5772/intechopen.69662

Dietmar Fey, Lukas Riedersberger and Marc Reichenbach Marc Reichenbach Additional information is available at the end of the chapter

Dietmar Fey, Lukas Riedersberger and

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69662

#### **Abstract**

[46] Hasler P, Diorio C, Minch BA, Mead C. Single transistor learning synapse with long term storage. Proceedings IEEE International Symposium on Circuits and Systems. 1995;1(1):

[47] Pershin YV, Di Ventra M. Experimental demonstration of associative memory with

[48] Wang L, Li H, Duan S, Huang T, Wang H. Pavlov associative memory in a memristive neural network and its circuit implementation. Neurocomputing. 2016;171(1):23-29 [49] Kim H, Sah MP, Yang C, Cho S, Chua LO. Memristor emulator for memristor circuit applications. IEEE Transactions on Circuits and Systems I Regular Papers. 2012;59(10):

[50] Carro-Pérez I, González-Hernández HG, Sánchez-López C. High-frequency memristive synapses. Proceeding IEEE Latin American Symposium on Circuits & Systems. 2017;1

memristive neural networks. Neural Networks. 2010;23(7):881-886

1660-1663

146 Memristor and Memristive Neural Networks

2422-2431

(1):1-4

This chapter presents a solution for the simulation of large memristive networks with SystemC-AMS. SystemC-AMS allows simulating memristors both on analogue level and on digital level to link analogue memristive devices to digital circuits and system level specifications. We investigate the benefits and drawbacks of a SystemC-AMS simulation compared to a simulation in SPICE. We show for the example of a two-layer memristive network emulating an optical flow algorithm by the detection of moving edges that large memristive networks can be simulated with a free available SystemC-AMS simulation environment, whereas free available SPICE simulation environment fails. However, it is also shown that commercial SPICE simulators are superior against current SystemC-AMS implementations concerning the size of simulated memristive networks. However, SystemC-AMS simulations of memristive networks offer both still more flexibility and similar run times compared to commercial SPICE simulators for small-sized memristive networks. The flexibility and the powerfulness of a SystemC-AMS solution is demonstrated for a complex network that solves edge detection, filtering and detecting of moving objects. The possible run times of the memristive network are determined in the SystemC-AMS simulation environment and are compared with an optical flow algorithm on classical hardware like a CPU and a GPU.

**Keywords:** memristive networks, SystemC-AMS, memristor modelling, optical flow, SPICE memristor simulation

## **1. Introduction**

One of the missing things in the research on modelling and simulation of large memristor networks is the availability of an adequate simulation system, which is both fast and flexible. Available SPICE models offer for commercial products, for example, Spectre Circuit Simulator,

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

fast simulation times but don't offer flexibility. To establish links to higher abstraction levels, for example, to the system level, in order to combine memristive circuits with extensive digital circuits, or even the integration in processor architecture descriptions to execute software in virtual environments is very cumbersome.

software in one homogeneous environment but also the combination of discrete and continuous analogue systems. SystemC-AMS contains a solver for the Kirchhoff equations which are used for the computation of the behaviour of electrical networks. SystemC as well SystemC-AMS is not a new language but an extension of C++ about a corresponding library. Therefore, it allows the modelling of analogue and digital systems using a class-orientated structure. This feature is very beneficial for designing complex memristor networks using different models. Just by instantiating another memristor model in the SystemC-AMS program, a whole network can be simulated with another memristor model in a very convenient way. A modification of the electronic network is not

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 149

SystemC-AMS offers three main options for the modelling of discrete and continuous systems on different abstraction levels. Furthermore, these models can also be coupled via matched interfaces. An example scenario for such a coupling of components modelled in different domains consists of, for example, a binary module that is connected to a linear electronic circuit. In this case, the binary module could differ between two states which are used to control a voltage source. According to a state transfer of the binary output, the polarization of the continuous output voltage signal is reversed. For the work presented in this chapter, we used a proof-of-concept implementation of SystemC-AMS from Accellera and Coseda Technologies [5], which is freely available under an Apache 2.0 licence. Since this implementation was developed primarily with respect to its correct implementation of the IEEE standard 1666.1, the main focus was not laid on the simulation speed. Therefore, it is to investigate how other possible SystemC-AMS simulators could offer an alternative in future, resp. a re-evaluation has to be done when the current version of Coseda leaves its current

In the following, we briefly present the above-mentioned three modelling options offered

The *timed data flow* (TDF) model allows the modelling of discrete time steps. Each TDF module has a couple of inputs and outputs, which consume an event at discrete time steps. As result of this occurred event, the module can change its internal state. However, processing at discrete time steps does not help us to model the analogue behaviour of memristors. The *linear signal flow* (LSF) allows solving continuous equations. For that purpose, different basic blocks like adders, multipliers and integrators are offered, which can be connected and are processed by a built-in solver for differential equations. Also, this option does not meet our intention of memristor modelling since LSF is more orientated to model signal-processing algorithms based on pre-built blocks. The third main modelling method is thought to model analogue systems as *electrical linear networks* (ELNs). It allows the set-up and solving of electrical networks by applying the Kirchhoff circuit laws for electronic meshes and nodes. An electrical network consists of modules which are connected via nodes. Using these laws, increasing and decreasing currents and voltages can be determined for the devices. Since memristors are part of electronic circuits, we use this modelling technique primarily for the

by SystemC-AMS and evaluate them for their appropriateness to model memristors.

necessary.

proof-of-concept state.

memristor modelling.

**2.1. SystemC-AMS modelling options**

Therefore, we established a model for memristors in SystemC-AMS. A SystemC simulation can be carried as fast as SPICE simulations but allows a better linking to higher system levels as it is possible, for example, with Verilog-A, for which already memristor models exist [1]. SystemC-AMS allows also a detailed investigation of the analogue behaviour in the same way as one it is used it in SPICE.

For the modelling of single memristor behaviour in SystemC-AMS, we used the possibility to model variable resistors in SystemC-AMS with electrical linear networks (ELNs) as starting point. The resistance values of such elements can be controlled and modified by a discrete event input signal. We start to demonstrate this possibility with the well-known SPICE memristor model from Biolek et al. [2], which is based on an electronic equivalent circuit of the simple memristor behaviour description from Hewlett-Packard.

However, we do not mimic the electronic equivalent circuit in SystemC-AMS. The memristor model is realized in SystemC-AMS as an own object-orientated class. Using object-orientated programming principles allows simply exchanging the model for the memristive behaviour by another one. In principle, it is possible to use any other model as long as it is specified by a C/C++ code snippet. We have implemented in SystemC-AMS two memristor models, the HP model that is also used in Biolek's SPICE model [2] and a statistic description for a commercial memristor coming from Knowm Inc. [3].

We demonstrate the usefulness and the strength of a SystemC-AMS-based simulation system for a three-dimensional (3D) memristive circuit that implements a detection based on an optical flow. For this application, a memristive network was proposed in Ref. [4]. We adapt this solution and modelled the complete network in SystemC-AMS. We compare the achieved results with an implementation on a GPU to evaluate possibilities and limits of the compute capability of memristive circuits. The chapter is organized as follows. In Section 2, we present our solution for the modelling of memristors in SystemC-AMS. Section 3 gives a brief insight in the optical flow algorithm we used for an implementation on a GPU and a multi-core CPU serving as reference architecture for the simulated memristive network. The corresponding memristor network calculates optical flow gradients as moving edges with a memristive network. We selected exactly this network as a representative complex example for a SystemC-AMS specification of memristive networks. Section 4 specifies the achieved results for the simulation and compares it with a GPU/CPU implementation concerning the run time. Furthermore, the simulation time of a SystemC-AMS specification and a SPICE simulation of the specific memristive network are compared. Finally, the chapter ends with a conclusion.

## **2. Modelling memristors in systemC-AMS**

SystemC-AMS is an extension of the modelling language SystemC about analoguemixed signals. It allows not only the modelling of digital hardware and corresponding software in one homogeneous environment but also the combination of discrete and continuous analogue systems. SystemC-AMS contains a solver for the Kirchhoff equations which are used for the computation of the behaviour of electrical networks. SystemC as well SystemC-AMS is not a new language but an extension of C++ about a corresponding library. Therefore, it allows the modelling of analogue and digital systems using a class-orientated structure. This feature is very beneficial for designing complex memristor networks using different models. Just by instantiating another memristor model in the SystemC-AMS program, a whole network can be simulated with another memristor model in a very convenient way. A modification of the electronic network is not necessary.

SystemC-AMS offers three main options for the modelling of discrete and continuous systems on different abstraction levels. Furthermore, these models can also be coupled via matched interfaces. An example scenario for such a coupling of components modelled in different domains consists of, for example, a binary module that is connected to a linear electronic circuit. In this case, the binary module could differ between two states which are used to control a voltage source. According to a state transfer of the binary output, the polarization of the continuous output voltage signal is reversed. For the work presented in this chapter, we used a proof-of-concept implementation of SystemC-AMS from Accellera and Coseda Technologies [5], which is freely available under an Apache 2.0 licence. Since this implementation was developed primarily with respect to its correct implementation of the IEEE standard 1666.1, the main focus was not laid on the simulation speed. Therefore, it is to investigate how other possible SystemC-AMS simulators could offer an alternative in future, resp. a re-evaluation has to be done when the current version of Coseda leaves its current proof-of-concept state.

#### **2.1. SystemC-AMS modelling options**

fast simulation times but don't offer flexibility. To establish links to higher abstraction levels, for example, to the system level, in order to combine memristive circuits with extensive digital circuits, or even the integration in processor architecture descriptions to execute software

Therefore, we established a model for memristors in SystemC-AMS. A SystemC simulation can be carried as fast as SPICE simulations but allows a better linking to higher system levels as it is possible, for example, with Verilog-A, for which already memristor models exist [1]. SystemC-AMS allows also a detailed investigation of the analogue behaviour in the same way

For the modelling of single memristor behaviour in SystemC-AMS, we used the possibility to model variable resistors in SystemC-AMS with electrical linear networks (ELNs) as starting point. The resistance values of such elements can be controlled and modified by a discrete event input signal. We start to demonstrate this possibility with the well-known SPICE memristor model from Biolek et al. [2], which is based on an electronic equivalent circuit of the

However, we do not mimic the electronic equivalent circuit in SystemC-AMS. The memristor model is realized in SystemC-AMS as an own object-orientated class. Using object-orientated programming principles allows simply exchanging the model for the memristive behaviour by another one. In principle, it is possible to use any other model as long as it is specified by a C/C++ code snippet. We have implemented in SystemC-AMS two memristor models, the HP model that is also used in Biolek's SPICE model [2] and a statistic description for a commercial

We demonstrate the usefulness and the strength of a SystemC-AMS-based simulation system for a three-dimensional (3D) memristive circuit that implements a detection based on an optical flow. For this application, a memristive network was proposed in Ref. [4]. We adapt this solution and modelled the complete network in SystemC-AMS. We compare the achieved results with an implementation on a GPU to evaluate possibilities and limits of the compute capability of memristive circuits. The chapter is organized as follows. In Section 2, we present our solution for the modelling of memristors in SystemC-AMS. Section 3 gives a brief insight in the optical flow algorithm we used for an implementation on a GPU and a multi-core CPU serving as reference architecture for the simulated memristive network. The corresponding memristor network calculates optical flow gradients as moving edges with a memristive network. We selected exactly this network as a representative complex example for a SystemC-AMS specification of memristive networks. Section 4 specifies the achieved results for the simulation and compares it with a GPU/CPU implementation concerning the run time. Furthermore, the simulation time of a SystemC-AMS specification and a SPICE simulation of the specific memristive network are compared. Finally, the chapter ends with a conclusion.

SystemC-AMS is an extension of the modelling language SystemC about analoguemixed signals. It allows not only the modelling of digital hardware and corresponding

in virtual environments is very cumbersome.

memristor coming from Knowm Inc. [3].

**2. Modelling memristors in systemC-AMS**

simple memristor behaviour description from Hewlett-Packard.

as one it is used it in SPICE.

148 Memristor and Memristive Neural Networks

In the following, we briefly present the above-mentioned three modelling options offered by SystemC-AMS and evaluate them for their appropriateness to model memristors.

The *timed data flow* (TDF) model allows the modelling of discrete time steps. Each TDF module has a couple of inputs and outputs, which consume an event at discrete time steps. As result of this occurred event, the module can change its internal state. However, processing at discrete time steps does not help us to model the analogue behaviour of memristors. The *linear signal flow* (LSF) allows solving continuous equations. For that purpose, different basic blocks like adders, multipliers and integrators are offered, which can be connected and are processed by a built-in solver for differential equations. Also, this option does not meet our intention of memristor modelling since LSF is more orientated to model signal-processing algorithms based on pre-built blocks. The third main modelling method is thought to model analogue systems as *electrical linear networks* (ELNs). It allows the set-up and solving of electrical networks by applying the Kirchhoff circuit laws for electronic meshes and nodes. An electrical network consists of modules which are connected via nodes. Using these laws, increasing and decreasing currents and voltages can be determined for the devices. Since memristors are part of electronic circuits, we use this modelling technique primarily for the memristor modelling.

In the following, we describe in detail the SystemC-AMS specification we selected for the memristor modelling. **Figure 1** shows a block diagram of the corresponding model. The basic idea is to model the memristor with a SystemC-AMS built-in data type *variable resistor* which allows changing dynamically its resistance by a discrete value. For each memristor in the simulated network, the voltage, which drops down at its ports *p* and *n*, is read out via *get\_voltage*() in each simulation step. Depending on the used memristor model, the new memristor's memristance is calculated. Subsequently, the new value is assigned to the variable resistance via assigning a discrete signal by the method *set\_resistance*().

**6.** The functional behaviour of a memristor, defined by its specific model, is specified by a later instanced virtual function *solve*(), which can be implemented in C/C++ code for each

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 151

**//resistor controlled by discrete-event input signal, needs input**

A specific memristor is modelled by an inheritance from the *class Memristor*. This is shown in the following for the specification of a *class MemristorBiolek*, which is inherited by the generic *public class Memristor*. The functional behaviour of the inherited memristor is orientated to the SPICE equivalent model from Biolek given in Ref. [2]. Some physical features for the memristor are defined as constants at the beginning like the *DRIFT\_MOBILITY* of the ions and the *LENGTH* of the channel of the modelled memristor. Furthermore, variables for the maximum and the minimum resistance, *R\_ON* and *R\_OFF*, and the width of the doped region, *w*, are declared. Furthermore, the class constructor and some parameters

**//systemc ams interface to read voltage over the resistor**

specific memristor model:

**//ports of the memristor**

sca\_eln::sca\_terminal p,n;

**//converter and voltage meter** sca\_tdf::sca\_out<**double**> out;

sca\_eln::sca\_tdf::sca\_vsink vout;

**//control port of controlled resistor**

sc\_core::sc\_in<**double**> memristor\_control;

sc\_core::sc\_signal<**double**> memristor\_port;

**virtual void** solve(**const double** dt) = 0;

sca\_eln::sca\_de::sca\_r memristor\_resistor;

sca\_tdf::sca\_signal<**double**> memristor\_voltage;

**//systemc ams interface to set the new resistance**

**//solve must be implemented by the specific model**

**//Base class**

**public**:

};

**double** R;

**class** Memristor {

**Figure 1.** Block diagram for the selected SystemC-AMS model for a memristor.

The code fragment shown below is the corresponding SystemC-AMS specification:


**6.** The functional behaviour of a memristor, defined by its specific model, is specified by a later instanced virtual function *solve*(), which can be implemented in C/C++ code for each specific memristor model:

In the following, we describe in detail the SystemC-AMS specification we selected for the memristor modelling. **Figure 1** shows a block diagram of the corresponding model. The basic idea is to model the memristor with a SystemC-AMS built-in data type *variable resistor* which allows changing dynamically its resistance by a discrete value. For each memristor in the simulated network, the voltage, which drops down at its ports *p* and *n*, is read out via *get\_voltage*() in each simulation step. Depending on the used memristor model, the new memristor's memristance is calculated. Subsequently, the new value is assigned to the variable resistance

The code fragment shown below is the corresponding SystemC-AMS specification:

memristance is calculated and stored as discrete variable in *R*.

**Figure 1.** Block diagram for the selected SystemC-AMS model for a memristor.

responding voltage value is stored at *memristor\_voltage*.

**2.** The memristor has two ports *p* and *n*.

is connected to via the ports *p* and *n*.

**1.** The memristor is modelled as an object-orientated *class Memristor* in SystemC-AMS. The

**3.** The memristor device, denoted as *memristor\_resistor*, is modelled as variable resistor. It inherits its characteristics from the SystemC-AMS built-in type *sca\_eln::sca\_de::sca\_r*. This variable is used in the circuit to which an instanced memristor element of the *class Memristor*

**4.** The voltage drop at the memristor can be measured by a kind of display variable *out*, this is the readable voltage value, that is given out via the virtual voltage metre *vout*. The cor-

**5.** SystemC uses a discrete-event simulation, for that it is necessary to define a so-called control port parameter that checks if a signal change occurs at its input. This is the variable

*memristor\_control*. To this port, a signal has to be attached which is *memristor\_port*.

via assigning a discrete signal by the method *set\_resistance*().

150 Memristor and Memristive Neural Networks

```
//Base class
class Memristor {
public:
double R;
//ports of the memristor
sca_eln::sca_terminal p,n;
//resistor controlled by discrete-event input signal, needs input
sca_eln::sca_de::sca_r memristor_resistor;
//converter and voltage meter
sca_tdf::sca_out<double> out;
sca_eln::sca_tdf::sca_vsink vout;
//systemc ams interface to read voltage over the resistor
sca_tdf::sca_signal<double> memristor_voltage;
//control port of controlled resistor
sc_core::sc_in<double> memristor_control;
//systemc ams interface to set the new resistance
sc_core::sc_signal<double> memristor_port;
//solve must be implemented by the specific model
virtual void solve(const double dt) = 0;
};
```
A specific memristor is modelled by an inheritance from the *class Memristor*. This is shown in the following for the specification of a *class MemristorBiolek*, which is inherited by the generic *public class Memristor*. The functional behaviour of the inherited memristor is orientated to the SPICE equivalent model from Biolek given in Ref. [2]. Some physical features for the memristor are defined as constants at the beginning like the *DRIFT\_MOBILITY* of the ions and the *LENGTH* of the channel of the modelled memristor. Furthermore, variables for the maximum and the minimum resistance, *R\_ON* and *R\_OFF*, and the width of the doped region, *w*, are declared. Furthermore, the class constructor and some parameters (*R\_ON, R\_OFF, R\_INIT*) are defined, which can be passed to the class element when it is instanced to initialize these memristor parameters. The functionality of the memristor type is defined by the method *solve*. A discrete solution of a differential equation for the memristance change is used; the step width for the integration is defined by *dt*. The method *solve* is the central key of the flexibility in the simulation. It can be changed by another function to implement another model.

**if** (x < 0.0) x = 0.0;

**double const** P\_WINDOW) **const**

**return** 1 - pow(x − 1, 2 \* P\_WINDOW);

**double** U = memristor\_voltage.read(0);

I \* windowBiolek(w/LENGTH, I, 7.0);

} ;//end of definition of class Memristor

more or less straight line, that is, the non-linear behaviour disappears.

R = R\_ON \* (w/LENGTH) + R\_OFF \* (1 − w/LENGTH); **double** vD = ((DRIFT\_MOBILITY \* R\_ON)/LENGTH) \*

**return** 1 - pow(x, 2 \* P\_WINDOW);

**ble**)> voltage\_function) {

**double** I = U/R;

w += vD \* dt;

write\_resistance();

The next code sections show the implementation of the method *solve*() to calculate the memristance of the memristor. The nonlinear behaviour of the memristor is modelled by the window function *windowBiolek*() that was set up by Biolek in Ref. [2] in order to modify the

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 153

**void** MemristorBiolek::solve(**const double** dt, std::function<**double**(**dou**

**Figure 2** shows multiple overlaid hysteresis curves for the I-U relation at the memristor's poles. Throughout, the memristor was simulated with a minimum resistance *R*OFF = 200 Ω, a maximum resistance *R*ON = 28 Ω and an initial resistance *R*INIT = 100 Ω. A sinusoidal voltage source is attached serially to the memristor. The voltage source is oscillating with 1 kHz between −1 and 1 V. The simulated time was set to 1 s with a time resolution of 1 µs. It is to observe that with each oscillation, the hysteresis curve becomes more flat until it ends in a

changing of the width of the memristor's doped region *w* at the edges of the device

**inline long double** windowBiolek(**double** x, **double** I,

w = x \* LENGTH;

}

{

}

}

**if** (−I >= 0)

The following SystemC-AMS code sequence shows the specification of a class that models a memristor's behaviour specification according to the Biolek model

```
class MemristorBiolek: public Memristor {
private:
  const double DRIFT_MOBILITY = 440000.0 * pow(10.0, −18.0);
  const double LENGTH = 41.0 * pow(10.0, −9.0);
  double R_ON, R_OFF, w;
public:
MemristorBiolek(const double R_ON, const double R_OFF,
const double R_INIT);
void solve(const double dt, std::function<double(double)>
voltage_function = [](const double val) -> double
{
return val;
}
);
std::string name() const { return "Biolek"; }
};
```
The following code snippet specifies the constructor for the inherited class *MemristorBiolek*: Memristor::Memristor(**const double** R\_INIT): R(R\_INIT) {} ;

```
MemristorBiolek::MemristorBiolek(const double R_ON, const double R_
OFF, const double R_INIT): R_ON(R_ON), R_OFF(R_OFF), Memristor(R_INIT)
{
double x = (R_INIT − R_OFF)/(R_ON − R_OFF);
if (x > 1.0) x = 1.0;
```
**if** (x < 0.0) x = 0.0; w = x \* LENGTH; }

(*R\_ON, R\_OFF, R\_INIT*) are defined, which can be passed to the class element when it is instanced to initialize these memristor parameters. The functionality of the memristor type is defined by the method *solve*. A discrete solution of a differential equation for the memristance change is used; the step width for the integration is defined by *dt*. The method *solve* is the central key of the flexibility in the simulation. It can be changed by another function

The following SystemC-AMS code sequence shows the specification of a class that models a

**const double** DRIFT\_MOBILITY = 440000.0 \* pow(10.0, −18.0);

memristor's behaviour specification according to the Biolek model

**const double** LENGTH = 41.0 \* pow(10.0, −9.0);

**voltage\_function = [](const double** val**) -> double**

std::string name() **const** { **return** "Biolek"; }

**double** x = (R\_INIT − R\_OFF)/(R\_ON − R\_OFF);

MemristorBiolek(**const double** R\_ON**, const double** R\_OFF,

**void** solve**(const double** dt**, std::function<double(**double**)>**

The following code snippet specifies the constructor for the inherited class *MemristorBiolek*:

MemristorBiolek::MemristorBiolek(**const double** R\_ON, **const double** R\_ OFF, **const double** R\_INIT): R\_ON(R\_ON), R\_OFF(R\_OFF), Memristor(R\_INIT)

Memristor::Memristor(**const double** R\_INIT): R(R\_INIT) {} ;

**class** MemristorBiolek**: public** Memristor {

to implement another model.

152 Memristor and Memristive Neural Networks

**double** R\_ON, R\_OFF, w;

**const double** R\_INIT);

**if** (x > 1.0) x = 1.0;

**private:**

**public:**

{

} );

};

{

**return** val**;**

The next code sections show the implementation of the method *solve*() to calculate the memristance of the memristor. The nonlinear behaviour of the memristor is modelled by the window function *windowBiolek*() that was set up by Biolek in Ref. [2] in order to modify the changing of the width of the memristor's doped region *w* at the edges of the device

```
inline long double windowBiolek(double x, double I,
double const P_WINDOW) const
{
if (−I >= 0)
return 1 - pow(x − 1, 2 * P_WINDOW);
return 1 - pow(x, 2 * P_WINDOW);
}
void MemristorBiolek::solve(const double dt, std::function<double(dou
ble)> voltage_function) {
double U = memristor_voltage.read(0);
double I = U/R;
R = R_ON * (w/LENGTH) + R_OFF * (1 − w/LENGTH);
double vD = ((DRIFT_MOBILITY * R_ON)/LENGTH) *
I * windowBiolek(w/LENGTH, I, 7.0);
w += vD * dt;
write_resistance();
}
} ;//end of definition of class Memristor
```
**Figure 2** shows multiple overlaid hysteresis curves for the I-U relation at the memristor's poles. Throughout, the memristor was simulated with a minimum resistance *R*OFF = 200 Ω, a maximum resistance *R*ON = 28 Ω and an initial resistance *R*INIT = 100 Ω. A sinusoidal voltage source is attached serially to the memristor. The voltage source is oscillating with 1 kHz between −1 and 1 V. The simulated time was set to 1 s with a time resolution of 1 µs. It is to observe that with each oscillation, the hysteresis curve becomes more flat until it ends in a more or less straight line, that is, the non-linear behaviour disappears.

**3.1. Procedure of the optical flow**

*<sup>h</sup>* <sup>=</sup> (*u*, *<sup>v</sup>*) <sup>=</sup> (

modelling the dynamic of memristors with variable resistors

*x*

**3.2. Memristive network and SystemC-AMS specification**

(*x*, *y*) ⋅ *u* + *I*

mV, we get the following scaling of the input voltage for each pixel Eq. (4)

(*x* ) = *x* ⋅ (

This scaling has to be carried out for each pixel in the image. In our SystemC-AMS specification, this is done per instruction code, which calculates Eq. (4) and uses the result to

\_40

*y*

(*x*, *y*) ⋅ *v* + *I*

In the following, we exemplarily consider the details only for the derivatives in the space to *x* and *y* dimension for a corresponding 2D memristor network. The extension to the time domain would be an additional layer in the third direction between corresponding pixels in neighboured images. As mentioned, the algorithm works on grey-scaled images; therefore, the scales have to be inverted in corresponding voltages. For the simulation, it is enough to restrict to an 8-bit resolution. Since the voltage of a photo-sensitive cell is in the range of 0–40

*<sup>I</sup>*(*x*, *<sup>y</sup>*, *<sup>t</sup>*) <sup>=</sup> *<sup>I</sup>*(*x*, *<sup>y</sup>*, *<sup>t</sup>*) <sup>+</sup> *<sup>u</sup>* <sup>⋅</sup> *dt* \_\_\_ <sup>∂</sup>*<sup>I</sup>*

*I*

*Vp*

*I(x,y,t+dt)*, has to maintain its brightness

The procedure of Horn and Schunk was one of the first optical flow methods. It provides a dense and smooth global result. Global in this sense means that the whole image is considered and not only a local region around a pixel in order to solve the equation motion for pixels in two subsequent images. In an optical flow procedure, a vector field *h* is computed according to Eq. (1)

For the calculation of translating pixels, it is assumed that their intensities remain constant after the translation. That means, a pixel, which is moved between two images *I(x,y,t)* and

*I*(*x*, *y*, *t*) = *I*(*x* + *u* ⋅ *dt*, *y* + *v* ⋅ *dt*, *t* + *dt* ) (2)

As a consequence, each algorithm, which is based on this equation, has to calculate with scalar, that is, grey values, and not with colour values. This has to occur also later in the memristive network. Finally, after applying the chain rule, Eq. (2) can be transformed to the central Eq. (3) that is solved in a similar way by detecting moving edges by the corresponding memristive network presented in Ref. [3]. This network is simulated here with SystemC-AMS to demonstrate that complex memristive networks can be simulated with our approach of

> <sup>∂</sup>*<sup>x</sup>* <sup>+</sup> *<sup>v</sup>* <sup>⋅</sup> \_\_\_ <sup>∂</sup>*<sup>I</sup>* ∂*y*

> > *t*

+ *dt* \_\_*<sup>I</sup>*

<sup>∂</sup>*<sup>t</sup>* (3)

(*x*, *y*) = 0 (4)

<sup>255</sup>)mV (5)

\_*dx dt* , \_ *dy*

*dt* and *<sup>d</sup>y*\_\_\_ *dt* . 155

*dt*) (1)

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662

that describes the translation of pixel *(x,y)* in a two-dimensional (2D) image over time \_\_\_ *dx*

**Figure 2.** Result of SystemC-AMS simulation of a memristor excited by a sinusoidal voltage signal.

## **3. Simulation of an optical flow algorithm with a memristor network in SystemC-AMS**

In the last chapter, we have shown how to simulate the analogue behaviour of a single memristor element. The next step is to demonstrate the possibility to simulate a much more complex example, namely the simulation of optical flow as detection of moving edges in a grid of memristors. The network mimics the functional behaviour of an artificial retina with a network consisting of resistors and memristors. The network was presented in Ref. [4]. In the following, we describe the set-up of the memristive network and the necessary functions to realize the detection of moving edges. We compare in the following the solution with an optical flow implementation on classical hardware. The optical flow follows the procedure according to Horn and Schunk [6]. For reasons of completeness, we briefly describe this algorithm first and the corresponding memristive network later as well as its SystemC-AMS specification developed by us.

#### **3.1. Procedure of the optical flow**

The procedure of Horn and Schunk was one of the first optical flow methods. It provides a dense and smooth global result. Global in this sense means that the whole image is considered and not only a local region around a pixel in order to solve the equation motion for pixels in two subsequent images. In an optical flow procedure, a vector field *h* is computed according to Eq. (1) that describes the translation of pixel *(x,y)* in a two-dimensional (2D) image over time \_\_\_ *dx dt* and *<sup>d</sup>y*\_\_\_ *dt* .

$$h = \begin{pmatrix} u \ \upsilon \end{pmatrix} = \begin{pmatrix} \frac{dx}{dt} \ \frac{dy}{dt} \end{pmatrix} \tag{1}$$

For the calculation of translating pixels, it is assumed that their intensities remain constant after the translation. That means, a pixel, which is moved between two images *I(x,y,t)* and *I(x,y,t+dt)*, has to maintain its brightness

$$I(\mathbf{x}, y, t) = I(\mathbf{x} + \mathbf{u} \cdot dt, y + \mathbf{v} \cdot dt, t + dt \mid \tag{2})$$

As a consequence, each algorithm, which is based on this equation, has to calculate with scalar, that is, grey values, and not with colour values. This has to occur also later in the memristive network. Finally, after applying the chain rule, Eq. (2) can be transformed to the central Eq. (3) that is solved in a similar way by detecting moving edges by the corresponding memristive network presented in Ref. [3]. This network is simulated here with SystemC-AMS to demonstrate that complex memristive networks can be simulated with our approach of modelling the dynamic of memristors with variable resistors

$$I(\mathbf{x}, y, t) = I(\mathbf{x}, y, t) + \mathbf{u} \cdot dt \frac{\partial I}{\partial \mathbf{x}} + \mathbf{v} \cdot \frac{\partial I}{\partial y} + dt \frac{I}{\partial t} \tag{3}$$

$$I\_x(\mathbf{x}, y) \cdot \mathbf{u} + I\_y(\mathbf{x}, y) \cdot \mathbf{v} + I\_l(\mathbf{x}, y) = \mathbf{0} \tag{4}$$

#### **3.2. Memristive network and SystemC-AMS specification**

**3. Simulation of an optical flow algorithm with a memristor** 

**Figure 2.** Result of SystemC-AMS simulation of a memristor excited by a sinusoidal voltage signal.

In the last chapter, we have shown how to simulate the analogue behaviour of a single memristor element. The next step is to demonstrate the possibility to simulate a much more complex example, namely the simulation of optical flow as detection of moving edges in a grid of memristors. The network mimics the functional behaviour of an artificial retina with a network consisting of resistors and memristors. The network was presented in Ref. [4]. In the following, we describe the set-up of the memristive network and the necessary functions to realize the detection of moving edges. We compare in the following the solution with an optical flow implementation on classical hardware. The optical flow follows the procedure according to Horn and Schunk [6]. For reasons of completeness, we briefly describe this algorithm first and the corresponding memristive network later as well as its SystemC-AMS speci-

**network in SystemC-AMS**

154 Memristor and Memristive Neural Networks

fication developed by us.

In the following, we exemplarily consider the details only for the derivatives in the space to *x* and *y* dimension for a corresponding 2D memristor network. The extension to the time domain would be an additional layer in the third direction between corresponding pixels in neighboured images. As mentioned, the algorithm works on grey-scaled images; therefore, the scales have to be inverted in corresponding voltages. For the simulation, it is enough to restrict to an 8-bit resolution. Since the voltage of a photo-sensitive cell is in the range of 0–40 mV, we get the following scaling of the input voltage for each pixel Eq. (4)

$$V\_{\rho}(\mathbf{x}) = \mathbf{x} \cdot \left(\frac{40}{255}\right) \mathbf{mV} \tag{5}$$

This scaling has to be carried out for each pixel in the image. In our SystemC-AMS specification, this is done per instruction code, which calculates Eq. (4) and uses the result to instantiate a DC voltage source. **Figure 3** shows a scheme for a memristive circuit that handles each pixel in the image.

**PixelNode::PixelNode**(**const** size\_t image\_id, **const** size\_t idx,

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 157

**const double** R\_CONST, const double R\_ON, **const double** R\_OFF, const double R\_INIT, **const unsigned char** initial\_pixel\_value,

initial\_pixel\_value(initial\_pixel\_value),

eln\_pixel(("eln\_pixel\_"+std::to\_string(image\_id)+"\_"

eln\_pixel.memristor\_controll(A.get\_control\_port());

neighbours(("eln\_pixel\_neighbour\_node\_"+std::to\_string(image\_id)+"\_"

gnd(new sca\_eln::sca\_node\_ref(std::string("gnd"+std::to\_

If a low-resistance value is assigned to *RC*, the voltage drop at the resistance will occur slowly, and due to the higher voltage that is applied to the subsequently attached memristors, in this case, their memristances are changing faster. In opposite, a higher resistance produces a more time-lag reaction in the network since now the memristors need more time to adapt their internal states. This new generated voltage via *RC* is now the input for the main layer of the

+std::to\_string(idx)).c\_str(,vsource,R\_CONST),

**const double** vsource):

R\_CONST(R\_CONST),

vsource(vsource),

A(R\_ON,R\_OFF,R\_INIT),

string(image\_id)+"\_"

A.write\_resistance();

**return** mapped\_voltage;

}

}

+std::to\_string(idx).c\_str()),

+std::to\_string(idx).c\_str())) {

eln\_pixel.out(A.get\_voltage\_port());

**double** PixelNode::pixel\_value() **const** {

**double** mapped\_voltage = A.read\_voltage() \* ((R\_CONST+A.resistance())/A.resistance());

eln\_pixel.neighbours(neighbours);

The voltage *V*, representing a changed grey value, is attached to the network via a resistance *RC*, which influences the time behaviour of the network for solving the optical flow. Since the optical flow changes dynamically in the network, the flow is modelled by current flowing through dynamically adapting resistances for which memristors are required. A memristor *RM*, which stores the result of the optical flow, again as an encoded grey value, and two further memristors, denoted as outer plexiform layer (OPL) in **Figure 3**, complete the circuit handling a pixel.

A corresponding description of the header file for the pixel (without the OPL) in SystemC-AMS is shown below. Firstly, the parameters are specified for the constructor of a pixel class called *PixelNode*. Since an instance of *PixelNode* is one pixel within a 2D array, it receives two identifiers. The first one is *image\_id*. It identifies in which image the pixel is, remember the optical flow requires two subsequent layers connected with each other. The second identifier, *idx*, addresses uniquely the pixel within the image. Then, four resistance values are as follows: R\_CONST, the starting value for the top resistor *RC*, R\_ON, R\_OFF and R\_INIT for the initial setting of the memristor denoted as *A* in the class, which corresponds to the bottom memristor *R*M in **Figure 3**. The parameters *initial\_pixel* and *vsource* correspond to the input grey value of the pixel and the input voltage *V*, which has to be calculated elsewhere in the code according to Eq. (4). The further specifications *eln\_pixel* and *neighbours* refer to the virtual electronic network to make a connection to a virtual potentiometer to measure current running through the pixel and the voltage applied at that pixel, respectively, to the connection to the neighboured pixels via the OPL. Both specifications and the ground connection, *gnd*, also require unique identifiers which are passed as strings, *eln\_pixel* and *gnd*, in the parentheses to the instances of *A*. Finally, the instructions given within the brackets provide the connections to the memristor as variable resistor analogue to the example given in the previous chapter for a memristor of the class *MemristorBiolek*. The result voltage will adjust at *RC*. It is calculated in the method *PixelNode::pixel\_value*. This voltage can be used in order to calculate the resulting grey value

**Figure 3.** Electrical network for one pixel. The memristive fuse OPL realizes the connection to the neighbour pixel. All pixels correspond to the mid-layer. The resistance RC controls the speed of the adaption of the memristive network, the voltage over resistance RM corresponds to the result, that is, if a moving pixel was detected according to a detected optical flow.

```
PixelNode::PixelNode(const size_t image_id, const size_t idx,
const double R_CONST, const double R_ON,
const double R_OFF, const double R_INIT,
const unsigned char initial_pixel_value,
const double vsource):
R_CONST(R_CONST),
initial_pixel_value(initial_pixel_value),
vsource(vsource),
A(R_ON,R_OFF,R_INIT),
eln_pixel(("eln_pixel_"+std::to_string(image_id)+"_"
+std::to_string(idx)).c_str(,vsource,R_CONST),
neighbours(("eln_pixel_neighbour_node_"+std::to_string(image_id)+"_"
+std::to_string(idx).c_str()),
gnd(new sca_eln::sca_node_ref(std::string("gnd"+std::to_
string(image_id)+"_"
+std::to_string(idx).c_str())) {
eln_pixel.memristor_controll(A.get_control_port());
eln_pixel.out(A.get_voltage_port());
eln_pixel.neighbours(neighbours);
A.write_resistance();
}
double PixelNode::pixel_value() const {
double mapped_voltage = A.read_voltage() *
((R_CONST+A.resistance())/A.resistance());
return mapped_voltage;
}
```
instantiate a DC voltage source. **Figure 3** shows a scheme for a memristive circuit that handles

The voltage *V*, representing a changed grey value, is attached to the network via a resistance *RC*, which influences the time behaviour of the network for solving the optical flow. Since the optical flow changes dynamically in the network, the flow is modelled by current flowing through dynamically adapting resistances for which memristors are required. A memristor *RM*, which stores the result of the optical flow, again as an encoded grey value, and two further memristors, denoted as outer plexiform layer (OPL) in **Figure 3**, complete the circuit handling a pixel. A corresponding description of the header file for the pixel (without the OPL) in SystemC-AMS is shown below. Firstly, the parameters are specified for the constructor of a pixel class called *PixelNode*. Since an instance of *PixelNode* is one pixel within a 2D array, it receives two identifiers. The first one is *image\_id*. It identifies in which image the pixel is, remember the optical flow requires two subsequent layers connected with each other. The second identifier, *idx*, addresses uniquely the pixel within the image. Then, four resistance values are as follows: R\_CONST, the starting value for the top resistor *RC*, R\_ON, R\_OFF and R\_INIT for the initial setting of the memristor denoted as *A* in the class, which corresponds to the bottom memristor *R*M in **Figure 3**. The parameters *initial\_pixel* and *vsource* correspond to the input grey value of the pixel and the input voltage *V*, which has to be calculated elsewhere in the code according to Eq. (4). The further specifications *eln\_pixel* and *neighbours* refer to the virtual electronic network to make a connection to a virtual potentiometer to measure current running through the pixel and the voltage applied at that pixel, respectively, to the connection to the neighboured pixels via the OPL. Both specifications and the ground connection, *gnd*, also require unique identifiers which are passed as strings, *eln\_pixel* and *gnd*, in the parentheses to the instances of *A*. Finally, the instructions given within the brackets provide the connections to the memristor as variable resistor analogue to the example given in the previous chapter for a memristor of the class *MemristorBiolek*. The result voltage will adjust at *RC*. It is calculated in the method *PixelNode::pixel\_value*. This voltage can be used in order to calculate the resulting grey value

**Figure 3.** Electrical network for one pixel. The memristive fuse OPL realizes the connection to the neighbour pixel. All pixels correspond to the mid-layer. The resistance RC controls the speed of the adaption of the memristive network, the voltage over resistance RM corresponds to the result, that is, if a moving pixel was detected according to a detected

each pixel in the image.

156 Memristor and Memristive Neural Networks

optical flow.

If a low-resistance value is assigned to *RC*, the voltage drop at the resistance will occur slowly, and due to the higher voltage that is applied to the subsequently attached memristors, in this case, their memristances are changing faster. In opposite, a higher resistance produces a more time-lag reaction in the network since now the memristors need more time to adapt their internal states. This new generated voltage via *RC* is now the input for the main layer of the network. The function of this main layer is adapted to the outer plexiform layer of the retina. This main layer mimics horizontal cells in the retina. Therefore, a connection to the neighbour pixels has to be realized via the so-called *memristive fuses*. These fuses provide an automatic averaging of the voltages connected to neighboured pixels. If there is a high potential difference between two neighboured pixels, then the memristive fuse adjusts faster a higher memristance. This leads to an edge-preserving property of the filter since the influence of the pixel decreases by the time. However, this idea would not work with a single memristor because the potential difference on that memristor could be either positive or negative. In the case of a negative potential, the memristance would decrease. This is the reason why two memristors, which are connected with reversed poles, are seen as depicted in **Figure 3**. Doing this, it does not play a role if the applied voltages are either negative or positive. In case an edge is detected, one of the memristors behaves always different to the other one and we receive as output the voltage that can be detected at resistor *RC*.

sca\_eln::sca\_de::sca\_r memristor\_resistor\_two;

memristor\_resistor\_one("memristor\_resistor\_one",1.0), memristor\_resistor\_two("memristor\_resistor\_two",1.0),

memristor\_resistor\_voltage\_one("memristor\_resistor\_voltage\_one"), memristor\_resistor\_voltage\_two("memristor\_resistor\_voltage\_two"),

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 159

memristor\_resistor\_vout\_one("memristor\_resistor\_vout\_one") memristor\_resistor\_vout\_two("memristor\_resistor\_vout\_two")

memristor\_resistor\_one.inp(memristor\_control\_one);

memristor\_resistor\_two.inp(memristor\_control\_two);

//setup voltage measurements for memristor one and two

memristor\_resistor\_vout\_one.outp(memristor\_resistor\_voltage\_one);

memristor\_resistor\_vout\_two.outp(memristor\_resistor\_voltage\_two);

After the definition for a pixel and a memristive\_fuse, both these devices can be connected to construct the circuit shown in **Figure 3** by attaching one of the ports *p* or *n* of the memristive fuse to the port *neighbor* of a pixel node. The connection scheme for one pixel detecting the deriva-

in a 2D grid for a direct hexagonal neighbour connection is shown in **Figure 4**.

**SC\_CTOR**(memristive\_fuse) :

node("node"),

//setup memristors

memristor\_resistor\_one.n(node);

memristor\_resistor\_two.n(node);

memristor\_resistor\_vout\_one.p(n); memristor\_resistor\_vout\_one.n(p);

memristor\_resistor\_vout\_two.n(node);

memristor\_resistor\_vout\_two.p(p);

memristor\_resistor\_one.p(p);

memristor\_resistor\_two.p(p);

{

} };

tives *I x* and *I y*

The following specification in SystemC-AMS shows the code for a memristive fuse. Such a fuse has also a positive and a negative port like a single memristor. Therefore, it can be attached to an electrical network. Furthermore, as already shown in the example for a memristor, we need control signals, *memristor\_control\_one* and *memristor\_control\_two*, as discrete input signals to change the resistances of the variable resistors, *memristor\_resistor\_one* and *memristor\_resistor\_two*. These memristors are connected via an electrical node called *node*, which is defined in the constructor as well as the binding of their control signals *memristor\_control\_one/two* to their ports *memristor\_ resistor\_one/two.inp*. Furthermore, the virtual circuit points *memristor\_resistor\_vout\_one/two.n/p* are defined to measure the voltage at these memristors via the signals *memristor\_resistor\_vout\_ one/two.outp*. These signals allow displaying the voltages at both memristors

```
SC_MODULE(memristive_fuse)
```

```
{
```

```
//negative and positive terminal
```

```
sca_eln::sca_terminal n, p;
```

```
sc_core::sc_in<double> memristor_control_one, memristor_control_two;
sca_tdf::sca_out<double> memristor_resistor_voltage_one;
sca_tdf::sca_out<double> memristor_resistor_voltage_two;
```
## **private**:

```
sca_eln::sca_node node;
sca_eln::sca_tdf::sca_vsink memristor_resistor_vout_one;
sca_eln::sca_tdf::sca_vsink memristor_resistor_vout_two;
//two memristors
sca_eln::sca_de::sca_r memristor_resistor_one;
```

```
sca_eln::sca_de::sca_r memristor_resistor_two;
SC_CTOR(memristive_fuse) :
memristor_resistor_one("memristor_resistor_one",1.0),
memristor_resistor_two("memristor_resistor_two",1.0),
node("node"),
memristor_resistor_voltage_one("memristor_resistor_voltage_one"),
memristor_resistor_voltage_two("memristor_resistor_voltage_two"),
memristor_resistor_vout_one("memristor_resistor_vout_one")
memristor_resistor_vout_two("memristor_resistor_vout_two")
{
//setup memristors
memristor_resistor_one.n(node);
memristor_resistor_one.p(p);
memristor_resistor_one.inp(memristor_control_one);
memristor_resistor_two.n(node);
memristor_resistor_two.p(p);
memristor_resistor_two.inp(memristor_control_two);
//setup voltage measurements for memristor one and two
memristor_resistor_vout_one.p(n);
memristor_resistor_vout_one.n(p);
memristor_resistor_vout_one.outp(memristor_resistor_voltage_one);
memristor_resistor_vout_two.n(node);
memristor_resistor_vout_two.p(p);
memristor_resistor_vout_two.outp(memristor_resistor_voltage_two);
}
};
```
network. The function of this main layer is adapted to the outer plexiform layer of the retina. This main layer mimics horizontal cells in the retina. Therefore, a connection to the neighbour pixels has to be realized via the so-called *memristive fuses*. These fuses provide an automatic averaging of the voltages connected to neighboured pixels. If there is a high potential difference between two neighboured pixels, then the memristive fuse adjusts faster a higher memristance. This leads to an edge-preserving property of the filter since the influence of the pixel decreases by the time. However, this idea would not work with a single memristor because the potential difference on that memristor could be either positive or negative. In the case of a negative potential, the memristance would decrease. This is the reason why two memristors, which are connected with reversed poles, are seen as depicted in **Figure 3**. Doing this, it does not play a role if the applied voltages are either negative or positive. In case an edge is detected, one of the memristors behaves always different to the other one and we receive as

The following specification in SystemC-AMS shows the code for a memristive fuse. Such a fuse has also a positive and a negative port like a single memristor. Therefore, it can be attached to an electrical network. Furthermore, as already shown in the example for a memristor, we need control signals, *memristor\_control\_one* and *memristor\_control\_two*, as discrete input signals to change the resistances of the variable resistors, *memristor\_resistor\_one* and *memristor\_resistor\_two*. These memristors are connected via an electrical node called *node*, which is defined in the constructor as well as the binding of their control signals *memristor\_control\_one/two* to their ports *memristor\_ resistor\_one/two.inp*. Furthermore, the virtual circuit points *memristor\_resistor\_vout\_one/two.n/p* are defined to measure the voltage at these memristors via the signals *memristor\_resistor\_vout\_*

sc\_core::sc\_in<**double**> memristor\_control\_one, memristor\_control\_two;

*one/two.outp*. These signals allow displaying the voltages at both memristors

sca\_tdf::sca\_out<**double**> memristor\_resistor\_voltage\_one; sca\_tdf::sca\_out<**double**> memristor\_resistor\_voltage\_two;

sca\_eln::sca\_tdf::sca\_vsink memristor\_resistor\_vout\_one; sca\_eln::sca\_tdf::sca\_vsink memristor\_resistor\_vout\_two;

sca\_eln::sca\_de::sca\_r memristor\_resistor\_one;

output the voltage that can be detected at resistor *RC*.

**SC\_MODULE**(memristive\_fuse)

158 Memristor and Memristive Neural Networks

//negative and positive terminal

**sca\_eln::sca\_terminal** n, p;

sca\_eln::sca\_node node;

//two memristors

{

**private**:

After the definition for a pixel and a memristive\_fuse, both these devices can be connected to construct the circuit shown in **Figure 3** by attaching one of the ports *p* or *n* of the memristive fuse to the port *neighbor* of a pixel node. The connection scheme for one pixel detecting the derivatives *I x* and *I y* in a 2D grid for a direct hexagonal neighbour connection is shown in **Figure 4**.

memristance stays low and we can detect a corresponding voltage change at *RC* correspond-

The result voltage *UG* is given to, it can be converted to a grey value *x* according to Eq. (5):

*<sup>M</sup>* ⋅ (*RC* + *RM*) *x* = *U<sup>G</sup>* ⋅ (

Both things, initializing the memristors as described earlier and the grey scale conversion, are performed in our SystemC-AMS specification by appropriate instruction codes, for example, the calculation of the result voltage is carried out with the method *PixelNode::pixel\_value* shown above in the class description of *PixelNode*. Besides the automatic filtering of neighboured input voltages, the network as described above allows the detection of edges, too, because edges are nothing else than potential differences. **Figure 5** shows the scheme for a potential propagation if the input voltage is applied left and the ground is applied right. Since this happens also for small differences very fast due to the memristive fuses, a threshold has to be introduced in order to detect real edges. The detection assigns a pixel only then as edge pixel if at least three of the neighbour pixels are above the threshold. This is directly programmed in the SystemC-AMS code which is not shown here. We have not seen a possibility to carry out such thresholding directly in the original analogue network published in Ref. [4].

network and its SystemC-AMS equivalent. However, the optical flow requires the input and analysis of input data from two subsequent images in order to detect also the derivative *I*

Therefore, the network has to be extended in the third dimension and we have done that also in our SystemC-AMS specification. This is shown in **Figure 6** in a lateral view for two neighboured pixels located at the same coordinate in two subsequent layers which are connected in

That means we connected together in SystemC-AMS two grids of the size 16 × 12 as shown for one pixel in **Figure 4**. The first gird hosted an image *I(x,y,t*) and the second one the timely

**Figure 5.** SystemC-AMS network for a detection of a moving edge pixel. The edge pixel disappears on the left (two short

So far, we have described a solution for determining the derivatives *I*

the same way as the lateral connections by an additional memristive fuse.

\_255

<sup>40</sup> mV) (6)

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662

> *x* and *I<sup>y</sup>*

within the 2D

*t* . 161

ing to a given edge pixel.

*U<sup>G</sup>* = *I*

arrows) side and moves to the right (long arrow).

**Figure 4.** Scheme for the 2D memristive grid with X connection, that is, each pixel has eight connections to four neighbours in rectangular direction (left, right, top, bottom) and to the four diagonals.

This can also be specified in SystemC-AMS which we are unable to present in this paper due to reasons of clarity since the corresponding code is larger. Before we can move to the achieved simulation results, some things concerning the functionality of the network have to be explained before.

The electrical network constructed in this way fulfils several tasks. For example, before the optical flow processing takes place, a Gaussian filtering is carried out on the pixels, which is done by the OPL imitating memristive fuses, too.

An important thing that has to be avoided is that both memristors of a fuse have the same initial mid resistance <sup>=</sup> *<sup>R</sup>*ON \_\_\_\_\_\_\_\_ <sup>+</sup> *<sup>R</sup>*OFF <sup>2</sup> . In this case, the changes of memristances in both memristors countermand themselves. If the memristance of one memristors increases, the memristance of the other one decreases. A possible solution for this problem is that both memristors are initialized with a low resistance. In case of a given potential difference between two neighboured pixels, independent of its direction, only one memristor increases, whereas the other one's memristance stays low and we can detect a corresponding voltage change at *RC* corresponding to a given edge pixel.

The result voltage *UG* is given to, it can be converted to a grey value *x* according to Eq. (5):

The result voltage  $\mathcal{U}\_{\mathcal{C}}$  is given to, it can be converted to a grey value x according to Eq. (5):

$$\mathcal{U}\_{\mathcal{C}} = \mathcal{I}\_{\mathcal{M}} \cdot \left(\mathbb{R}\_{\mathcal{C}} + \mathbb{R}\_{\mathcal{M}}\right) \ge = \mathcal{U}\_{\mathcal{C}} \cdot \left(\frac{255}{40 \text{ mV}}\right) \tag{6}$$

Both things, initializing the memristors as described earlier and the grey scale conversion, are performed in our SystemC-AMS specification by appropriate instruction codes, for example, the calculation of the result voltage is carried out with the method *PixelNode::pixel\_value* shown above in the class description of *PixelNode*. Besides the automatic filtering of neighboured input voltages, the network as described above allows the detection of edges, too, because edges are nothing else than potential differences. **Figure 5** shows the scheme for a potential propagation if the input voltage is applied left and the ground is applied right. Since this happens also for small differences very fast due to the memristive fuses, a threshold has to be introduced in order to detect real edges. The detection assigns a pixel only then as edge pixel if at least three of the neighbour pixels are above the threshold. This is directly programmed in the SystemC-AMS code which is not shown here. We have not seen a possibility to carry out such thresholding directly in the original analogue network published in Ref. [4].

So far, we have described a solution for determining the derivatives *I x* and *I<sup>y</sup>* within the 2D network and its SystemC-AMS equivalent. However, the optical flow requires the input and analysis of input data from two subsequent images in order to detect also the derivative *I t* . Therefore, the network has to be extended in the third dimension and we have done that also in our SystemC-AMS specification. This is shown in **Figure 6** in a lateral view for two neighboured pixels located at the same coordinate in two subsequent layers which are connected in the same way as the lateral connections by an additional memristive fuse.

That means we connected together in SystemC-AMS two grids of the size 16 × 12 as shown for one pixel in **Figure 4**. The first gird hosted an image *I(x,y,t*) and the second one the timely

This can also be specified in SystemC-AMS which we are unable to present in this paper due to reasons of clarity since the corresponding code is larger. Before we can move to the achieved simulation results, some things concerning the functionality of the network have to

**Figure 4.** Scheme for the 2D memristive grid with X connection, that is, each pixel has eight connections to four

neighbours in rectangular direction (left, right, top, bottom) and to the four diagonals.

The electrical network constructed in this way fulfils several tasks. For example, before the optical flow processing takes place, a Gaussian filtering is carried out on the pixels, which is

An important thing that has to be avoided is that both memristors of a fuse have the same

countermand themselves. If the memristance of one memristors increases, the memristance of the other one decreases. A possible solution for this problem is that both memristors are initialized with a low resistance. In case of a given potential difference between two neighboured pixels, independent of its direction, only one memristor increases, whereas the other one's

<sup>2</sup> . In this case, the changes of memristances in both memristors

be explained before.

initial mid resistance <sup>=</sup> *<sup>R</sup>*ON \_\_\_\_\_\_\_\_ <sup>+</sup> *<sup>R</sup>*OFF

160 Memristor and Memristive Neural Networks

done by the OPL imitating memristive fuses, too.

**Figure 5.** SystemC-AMS network for a detection of a moving edge pixel. The edge pixel disappears on the left (two short arrows) side and moves to the right (long arrow).

between the two edges (see arrows in **Figure 7(d)**) can be identified and by this also the mov-

(a) (b) (c) (d)

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 163

**Figure 7.** Used test input images (top), the two scenes are slightly displaced. On the bottom left side, (a) solution based on Horn and Schunck procedure calculated on CPU with 32 × 24 image size; (b) solution for 16 × 24 image size. On the bottom right side, the solution for the same scenes determined with the simulated memristive network in SystemC-AMS.

The results of **Figure 7** demonstrate that it is possible to detect moving objects with the memristive network and its SystemC-AMS model. We are now interested on how fast the network and the SystemC-AMS simulation work. The simulation of the detected moving edges in **Figure 7(c)** shows simulation results for a simulated memristive network for a time interval of 3000 ms. In this case, Biolek model was not used for the memristors but the model from Knowm which produced a significantly higher contrast. At the beginning, only a wave can be observed. After a simulated real time of 3000 ms, a higher contrast is given with that model compared to the input image and the moving objects can be detected. As comparison with existing hardware, we have determined the run times of the detection with the optical flow based on Horn and Schunk on a CPU (corei5-6600 corresponds to Intel's Skylake microarchitecture) and a Jetson TX1-embedded GPU board from Nvidia. The CPU could compute in 3000-ms image sizes of 160×120. It is to expect that the memristive network works also on

Therefore, the memristive network lies in the same range as the CPU concerning the compute performance. The situation is different compared to the GPU. We measured a time of about 100 ms for an image size of 640 × 480. Hence, the GPU has clear advantages versus the mem-

However, the actual interesting point in this paper is the simulation time of the SystemC-AMS specification. In order to get significant values we have carried out a series of possible optimization measures concerning the network topology and the monitoring, resp., the virtual voltage measuring during the simulation. **Figure 8** shows the simulation time

ing of the cars shown in front and of the smaller one shown behind in the image.

Firstly, the detected edges (c), afterwards the detected directions of the moving edges (d).

higher resolution since it is a highly local parallel-processing scheme.

ristive network concerning the run time.

**Figure 6.** 3D connection of a pixel between two pixels neighboured in subsequent images.

displaced image *I(x,y,t+dt)*. A larger size could not be selected because the free SystemC-AMS version of Coseda did not allow generating more active elements. The SystemC-AMS code we tested extends more than 3000 memristors in all fuses and pixels for two images of size 16 × 12.

## **4. Results**

**Figure 7** shows the achieved functional results of the SystemC-AMS simulation for a traffic scene with the memristive network that works on the detection of moving edges with the memristive 2D network compared to a classical solution calculated according to Horn and Schunk on an Inteli5-6600 CPU. It is to recognize that the Horn and Schunk procedure algorithm works much better on a higher resolution, (a) versus (b), whereas the lower resolution is sufficient for the SystemC-AMS detection of moving edges (c). The low resolution was selected since this was the limit for the SystemC-AMS simulation with the proof-of-concept software solution. These moving edges are combined in one object. The grey edges are the disappearing edges, whereas the dark square corresponds to an appearing edge. The assignment

**Figure 7.** Used test input images (top), the two scenes are slightly displaced. On the bottom left side, (a) solution based on Horn and Schunck procedure calculated on CPU with 32 × 24 image size; (b) solution for 16 × 24 image size. On the bottom right side, the solution for the same scenes determined with the simulated memristive network in SystemC-AMS. Firstly, the detected edges (c), afterwards the detected directions of the moving edges (d).

between the two edges (see arrows in **Figure 7(d)**) can be identified and by this also the moving of the cars shown in front and of the smaller one shown behind in the image.

The results of **Figure 7** demonstrate that it is possible to detect moving objects with the memristive network and its SystemC-AMS model. We are now interested on how fast the network and the SystemC-AMS simulation work. The simulation of the detected moving edges in **Figure 7(c)** shows simulation results for a simulated memristive network for a time interval of 3000 ms. In this case, Biolek model was not used for the memristors but the model from Knowm which produced a significantly higher contrast. At the beginning, only a wave can be observed. After a simulated real time of 3000 ms, a higher contrast is given with that model compared to the input image and the moving objects can be detected. As comparison with existing hardware, we have determined the run times of the detection with the optical flow based on Horn and Schunk on a CPU (corei5-6600 corresponds to Intel's Skylake microarchitecture) and a Jetson TX1-embedded GPU board from Nvidia. The CPU could compute in 3000-ms image sizes of 160×120. It is to expect that the memristive network works also on higher resolution since it is a highly local parallel-processing scheme.

displaced image *I(x,y,t+dt)*. A larger size could not be selected because the free SystemC-AMS version of Coseda did not allow generating more active elements. The SystemC-AMS code we tested extends more than 3000 memristors in all fuses and pixels for two images of size

**Figure 6.** 3D connection of a pixel between two pixels neighboured in subsequent images.

**Figure 7** shows the achieved functional results of the SystemC-AMS simulation for a traffic scene with the memristive network that works on the detection of moving edges with the memristive 2D network compared to a classical solution calculated according to Horn and Schunk on an Inteli5-6600 CPU. It is to recognize that the Horn and Schunk procedure algorithm works much better on a higher resolution, (a) versus (b), whereas the lower resolution is sufficient for the SystemC-AMS detection of moving edges (c). The low resolution was selected since this was the limit for the SystemC-AMS simulation with the proof-of-concept software solution. These moving edges are combined in one object. The grey edges are the disappearing edges, whereas the dark square corresponds to an appearing edge. The assignment

16 × 12.

**4. Results**

162 Memristor and Memristive Neural Networks

Therefore, the memristive network lies in the same range as the CPU concerning the compute performance. The situation is different compared to the GPU. We measured a time of about 100 ms for an image size of 640 × 480. Hence, the GPU has clear advantages versus the memristive network concerning the run time.

However, the actual interesting point in this paper is the simulation time of the SystemC-AMS specification. In order to get significant values we have carried out a series of possible optimization measures concerning the network topology and the monitoring, resp., the virtual voltage measuring during the simulation. **Figure 8** shows the simulation time

done using Cadence Virtuoso. While Virtuoso was able to read the network and create a schematic view, it was not possible to start the Spectre simulation due to incompatibilities using

Simulating Memristive Networks in SystemC-AMS http://dx.doi.org/10.5772/intechopen.69662 165

In an older work [7], a similar 32 × 32 array of memristors was simulated in SPICE. Recently, Biolek et al. published a work [8] in which they used a parallel version of a commercial HSPICE simulator which allowed them to simulate extremely large memristor networks. They managed it to simulate a 100 × 100 memristive grid network containing 20,200 memristors in 5.5 s and a 1500 × 1500-sized memristive network containing 4.5 million memristors in 76 min by applying a modified version of the so-called S-model for memristors on a current

Exploiting the flexibility of a high-level language like SystemC-AMS, the presented simulation environment enables designers to carry out extensive investigations on large memristive circuits to estimate latency and energy consumption just by simple C++ code modifications. Furthermore, such a system allows the simulation of thousands of connected memristors at acceptable simulation times, which is shown by a direct comparison to an equivalent SPICE simulation. A SystemC-AMS description allows faster simulation, but currently the investigated SystemC-AMS implementations do not allow the simulation for networks concerning more than 10 k memristors. Therefore, there seems to be a need for action concerning an extension of SystemC-AMS environments in the future. On the other side, free available SPICE versions failed to simulate memristor networks in the size of 1000 s, whereas the presented SPICE-AMS implementation could handle it in acceptable simulation time of 4–5 s and around 1 s for an optimized version. However, compared to commercial HSPICE simulators only smaller-sized networks of memristors can be investigated. On the other side, a SystemC-AMS solution simplifies a coupling to digital system layers to realize mixed-signal simulations. We demonstrated this flexibility in principle in this paper for the optical flow

For the optical flow example, a comparison of a memristive network with real processor architecture like a GPU was carried out. It could be shown by simulations that using a GPU architecture is more efficient for the optical flow problem than a 2D grid memristive network solving the problem by detecting moving edges. The performance of a current CPU solution on the other side offers not more compute power than the memristive network which probably requires less energy consumption than the CPU. At all, we think that mixed-signal solutions are to favour, which combine analogue memristive circuits with digital processors, to unite computational flexibility and the benefits of energy-saving neuromorphic analogue memristor networks. A SystemC-AMS-based simulation environment is generally well suited for the design of such architectures and to estimate the required power and processing time. Our solution laid the foundation for such work in

the memristor Spice description.

Intel core i7 architecture.

**5. Conclusion**

algorithm.

the future.

**Figure 8.** Measuring the simulation time in SystemC-AMS for different options.

for filtering and edge detection in one image for the following different sizes 16 × 12, 32 × 24 and 35 × 26 for a not optimized version (most-left bars—non-optimized), a version, which uses only one memristor in the fuses which is sufficient for edge detection as we found out (second left bar—optimized memristive fuses), using a hexagonal grid instead a 3 × 3 grid as local neighbourhood for a pixel (second right bar—hexagonal grid), and removing the voltage potentiometers for each memristor in the SystemC-AMS code (most right bar—removed not required potentiometers). It is to detect that simulation time can be drastically reduced, for example, for a 35 × 26 image from 4500 ms down to about 750 ms for the largest resolution of 35 × 26 if all optimization steps are applied subsequently.

Our efforts to carry out an equivalent SPICE simulation with LT Spice have been in vain. The LT Spice simulator ended in an endless loop by the trial to simulate this large memristive network. With the PSpice A/D Lite version, the simulation aborted orderly with the message that the symbol table entry is out of bounds. May be the commercial version of Pspice allows to simulate such a large amount of devices. In all, in the 32 × 24-sized grid 768 voltage sources, 1536 resistors and 5461 memristor subcircuits have to be simulated. Further work has been done using Cadence Virtuoso. While Virtuoso was able to read the network and create a schematic view, it was not possible to start the Spectre simulation due to incompatibilities using the memristor Spice description.

In an older work [7], a similar 32 × 32 array of memristors was simulated in SPICE. Recently, Biolek et al. published a work [8] in which they used a parallel version of a commercial HSPICE simulator which allowed them to simulate extremely large memristor networks. They managed it to simulate a 100 × 100 memristive grid network containing 20,200 memristors in 5.5 s and a 1500 × 1500-sized memristive network containing 4.5 million memristors in 76 min by applying a modified version of the so-called S-model for memristors on a current Intel core i7 architecture.

## **5. Conclusion**

for filtering and edge detection in one image for the following different sizes 16 × 12, 32 × 24 and 35 × 26 for a not optimized version (most-left bars—non-optimized), a version, which uses only one memristor in the fuses which is sufficient for edge detection as we found out (second left bar—optimized memristive fuses), using a hexagonal grid instead a 3 × 3 grid as local neighbourhood for a pixel (second right bar—hexagonal grid), and removing the voltage potentiometers for each memristor in the SystemC-AMS code (most right bar—removed not required potentiometers). It is to detect that simulation time can be drastically reduced, for example, for a 35 × 26 image from 4500 ms down to about 750 ms for the largest resolu-

Our efforts to carry out an equivalent SPICE simulation with LT Spice have been in vain. The LT Spice simulator ended in an endless loop by the trial to simulate this large memristive network. With the PSpice A/D Lite version, the simulation aborted orderly with the message that the symbol table entry is out of bounds. May be the commercial version of Pspice allows to simulate such a large amount of devices. In all, in the 32 × 24-sized grid 768 voltage sources, 1536 resistors and 5461 memristor subcircuits have to be simulated. Further work has been

tion of 35 × 26 if all optimization steps are applied subsequently.

**Figure 8.** Measuring the simulation time in SystemC-AMS for different options.

164 Memristor and Memristive Neural Networks

Exploiting the flexibility of a high-level language like SystemC-AMS, the presented simulation environment enables designers to carry out extensive investigations on large memristive circuits to estimate latency and energy consumption just by simple C++ code modifications. Furthermore, such a system allows the simulation of thousands of connected memristors at acceptable simulation times, which is shown by a direct comparison to an equivalent SPICE simulation. A SystemC-AMS description allows faster simulation, but currently the investigated SystemC-AMS implementations do not allow the simulation for networks concerning more than 10 k memristors. Therefore, there seems to be a need for action concerning an extension of SystemC-AMS environments in the future. On the other side, free available SPICE versions failed to simulate memristor networks in the size of 1000 s, whereas the presented SPICE-AMS implementation could handle it in acceptable simulation time of 4–5 s and around 1 s for an optimized version. However, compared to commercial HSPICE simulators only smaller-sized networks of memristors can be investigated. On the other side, a SystemC-AMS solution simplifies a coupling to digital system layers to realize mixed-signal simulations. We demonstrated this flexibility in principle in this paper for the optical flow algorithm.

For the optical flow example, a comparison of a memristive network with real processor architecture like a GPU was carried out. It could be shown by simulations that using a GPU architecture is more efficient for the optical flow problem than a 2D grid memristive network solving the problem by detecting moving edges. The performance of a current CPU solution on the other side offers not more compute power than the memristive network which probably requires less energy consumption than the CPU. At all, we think that mixed-signal solutions are to favour, which combine analogue memristive circuits with digital processors, to unite computational flexibility and the benefits of energy-saving neuromorphic analogue memristor networks. A SystemC-AMS-based simulation environment is generally well suited for the design of such architectures and to estimate the required power and processing time. Our solution laid the foundation for such work in the future.

## **Author details**

Dietmar Fey\*, Lukas Riedersberger and Marc Reichenbach

\*Address all correspondence to: dietmar.fey@fau.de

Friedrich-Alexander-University Erlangen-Nürnberg (FAU), Computer Architecture, Department of Computer Science, Erlangen, Germany

## **References**

[1] Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: ThrEshold adaptive memristor model. IEEE Transactions on Circuits and Systems. 2013;**60-I**(1):211-221

**Chapter 8**

Provisional chapter

**Modeling of Coupled Memristive-Based Architectures**

DOI: 10.5772/intechopen.69327

Modeling of Coupled Memristive-Based Architectures

This chapter explores the dynamic behavior of dual flux coupled memristor circuits in order to explore the uncharted territory of the fundamental theory of memristor circuits. Neuromorphic computing anticipates highly dense systems of memristive networks, and with nanoscale devices within such close proximity to one another, it is anticipated that flux and charge coupling between adjacent memristors will have a bearing upon their operation. Using the constitutive relations of memristors, various cases of flux coupling are mathematically modeled. This involves analyzing two memristors connected in composite, both serially and in parallel in various polarity configurations. The new behavior of two coupled memristors is characterized based on memristive state equations, and memductance variation represented in terms of voltage, current, charge and flux. The rigorous mathematical analysis based on the fundamental circuit equations of ideal memristors affirms the memristor closure theorem, where coupled memristor

circuits behave as different types of memristors with higher complexity.

Keywords: memristor, memductance, coupling, flux, charge, series, parallel

In 1969, Leon Chua became the first person to publish non-linear circuit theory against a mathematical foundation [1]. In doing so, it became apparent that there was a hole in the circuit equations at the time. Shortly after, in 1971 he postulated that symmetry implies the existence of a fourth fundamental circuit element to link the missing relationship between charge and flux —that circuit element being the memristor [2]. This research resurfaced and was popularized in 2008, when Hewlett-Packard fabricated the first functional nanoscale memristor [3]. This particular brand of memristor was based on a bi-level titanium dioxide thin film containing dopants which migrate across the width of the memristor when a current is applied to it.

> © The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

**Applicable to Neural Network Models**

Applicable to Neural Network Models

Jason Kamran Jr Eshraghian, Herbert H.C. Iu and

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Jason Kamran Jr Eshraghian, Herbert H.C. Iu

http://dx.doi.org/10.5772/intechopen.69327

Kamran Eshraghian

Abstract

1. Introduction

and Kamran Eshraghian


#### **Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models** Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

DOI: 10.5772/intechopen.69327

Jason Kamran Jr Eshraghian, Herbert H.C. Iu and Kamran Eshraghian Jason Kamran Jr Eshraghian, Herbert H.C. Iu and Kamran Eshraghian

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69327

#### Abstract

**Author details**

166 Memristor and Memristive Neural Networks

**References**

20-March-2016]

Dietmar Fey\*, Lukas Riedersberger and Marc Reichenbach

Friedrich-Alexander-University Erlangen-Nürnberg (FAU), Computer Architecture,

[1] Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: ThrEshold adaptive memris-

[2] Biolek Z, Biolek D, Biolkov V. SPICE model of memristor with nonlinear dopant drift.

[3] Nugent MA, Molter TW. AHaH computing–From metastable switches to attractors to machine learning. PLoS ONE. 2014;**9**(2):e85175. DOI: doi:10.1371/journal.pone.0085175

[4] Lim CKK, Gelencser A, Prodromakis T. Computing image and motion with 3-D memristive grids. In: Adamatzky A, Chua L, editors. Memristor Networks. Cham: Springer

[5] Coseda Technologies GmbH. SystemC AMS Proof-of-Concept Download [Internet]. Available from: http://www.coseda-tech.com/systemc-ams-proof-of-concept [Accessed:

[7] Wang Y, Fei W, Yu H. SPICE simulator for hybrid CMOS memristor circuit and system. In: 13th International Workshop on Cellular Nanoscale Networks and their Applications

[8] Biolek D, Kolka Z, Biolkova V, Biolek Z. Memristor models for spice simulation of extremely large memristive networks. In: IEEE International Symposium on Circuits

and Systems (ISCAS); May 22-25, 2016, Montreal, QC: IEEE; 2016. pp. 389-392

[6] Horn BKP, Schunck BG. Determining optical flow. Artificial Intelligence. 1981;**17**

(CNNA 2012); August 29-31, 2012; Turin, Italy: IEEE; 2012. pp. 1-6

tor model. IEEE Transactions on Circuits and Systems. 2013;**60-I**(1):211-221

\*Address all correspondence to: dietmar.fey@fau.de

Department of Computer Science, Erlangen, Germany

Radioengineering. 2009;**18**(2):210-214

International Publishing; 2014. pp. 553-583

This chapter explores the dynamic behavior of dual flux coupled memristor circuits in order to explore the uncharted territory of the fundamental theory of memristor circuits. Neuromorphic computing anticipates highly dense systems of memristive networks, and with nanoscale devices within such close proximity to one another, it is anticipated that flux and charge coupling between adjacent memristors will have a bearing upon their operation. Using the constitutive relations of memristors, various cases of flux coupling are mathematically modeled. This involves analyzing two memristors connected in composite, both serially and in parallel in various polarity configurations. The new behavior of two coupled memristors is characterized based on memristive state equations, and memductance variation represented in terms of voltage, current, charge and flux. The rigorous mathematical analysis based on the fundamental circuit equations of ideal memristors affirms the memristor closure theorem, where coupled memristor circuits behave as different types of memristors with higher complexity.

Keywords: memristor, memductance, coupling, flux, charge, series, parallel

#### 1. Introduction

In 1969, Leon Chua became the first person to publish non-linear circuit theory against a mathematical foundation [1]. In doing so, it became apparent that there was a hole in the circuit equations at the time. Shortly after, in 1971 he postulated that symmetry implies the existence of a fourth fundamental circuit element to link the missing relationship between charge and flux —that circuit element being the memristor [2]. This research resurfaced and was popularized in 2008, when Hewlett-Packard fabricated the first functional nanoscale memristor [3]. This particular brand of memristor was based on a bi-level titanium dioxide thin film containing dopants which migrate across the width of the memristor when a current is applied to it.

© The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

Each fundamental circuit element holds a relationship between any two of either voltage, current, charge, or flux. The memristor thus becomes a fundamental circuit element as it fills the missing gap of the charge-flux relationship. It is important to note that even though q and ϕ are referred to as charge and flux, they do not have to be associated with a physical charge or real flux as is the case with classical conductors and inductors [4]. The integrating relationship between voltage and flux results in memristors being able to retain history, and exhibiting potentially different current values when the same voltage is applied to it. By definition, this enables the memristor to have different resistance values regardless of identical voltage excitation, stemming from memristance being a function of historical voltage. This gives rise to the nomenclature surrounding the memristor, a portmanteau of 'memory resistor'.

Therefore, coupling is to be expected between adjacent memristors, and must be taken into account when analyzing highly concentrated circuits. In addition to series and parallel connections, coupling has thus been established as a third unique relation in memristive systems [15]. The behavior of coupled memristors was rigorously analyzed in a systematic manner for the first time in Ref. [16] with consideration given to all polarity combinations. The theoretical analysis is confirmed in the same paper by use of a separately presented memristor emulator circuit from Ref. [17]. However, the results in the analysis is based on a memristor which exhibits a linear relationship between memductance and flux. This is obviously not the case for many memristors, such as the simplest case of a flux-controlled switching memristor presented in Ref. [18] where flux is controlled independent of memductance. As such, there is only a very narrow scope of memristors which the research in Ref. [16] applies to. The results in Ref. [18] served to broaden this assumption to ideal switching memristors which operate in two states, and obtain new results based on the same constitutive relation equations. This chapter dissects the results in Ref. [18] and presents them in a more comprehensive format, with the use of fundamental memristor theory to form the basis of the analysis to produce valid results. As such, the findings in this chapter can be applied more broadly and yet maintain the complex behavior which makes the memristor so attractive. The theoretical analysis and analytical solutions provide for novel memductance behavior in terms of flux, charge, voltage and current of ideal memristors. In the process, it is proven that the memristor closure theorem continues to stand for coupled memristors [19].

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

http://dx.doi.org/10.5772/intechopen.69327

169

The two types of ideal memristors considered are charge controlled or flux controlled [2]. The relationship between current and voltage of a charge controlled memristor is expressed by

where t is time, v(t) is voltage, q(t) is charge and M(q) is memristance. In its derivative form,

where ϕ(q) is flux (the time integral of voltage v(t)). Contrastingly, the current of a flux controlled

.

.

<sup>M</sup>ðqÞ ¼ <sup>d</sup>φðq<sup>Þ</sup>

<sup>W</sup>ðφÞ ¼ dqðφ<sup>Þ</sup>

The memductance W is the slope of the q-ϕ curve, which is a characteristic embedded into the

VðtÞ ¼ MðqÞiðtÞ, (1)

iðtÞ ¼ WðφÞvðtÞ, (3)

dq, (2)

dφ: (4)

2. Coupled memristors

memristance can be defined as

where W(ϕ) denotes the memductance and

memristor at the time of fabrication.

memristor is

The inherent characteristics of this revolutionary device have enabled its application in a diverse field of areas, including neuromorphic circuits [5] and non-volatile memory applications [6]. These applications often see arrays of memristors behaving compositely with one another. In addition to the functionality of single discrete memristors, the behaviors of multiple memristors in structures of connectivity have also been analyzed.

Memristors are polarity dependant—while this complicates circuit analysis, it allows for many more configuration permutations than the other fundamental circuits: the resistor, capacitor and inductor. The behavior of two memristor emulators in both serial and parallel connections are experimentally evaluated in Ref. [7], however, only identical polarity directions are considered. Two charge controlled memristors are connected in series and in parallel in Ref. [8], with their responses evaluated when polarity is varied. The composite behavior is analyzed by probing the relationships between flux, charge and memristance. The results show novel I-V characteristics which will prove to be useful applications in neural networks and logic circuits. The magnetic coupling of memristors are also considered in terms of mutual induction and capacitive connections in Ref. [9].

Many researchers have sought to use memristors to represent the synapses between neurons in artificial networks, and more recently, a memristive crossbar array has been successfully fabricated which implements a neural network, and is successfully capable of performing limited classifications and simple pattern recognition [10]. By training such networks on sets of known example patterns and tuning the weights of the 'synaptic' connections, unknown patterns and images can be recognized. Ultimately, researchers anticipate that networks with a density of 100 billion synapses per square centimeter in each layer should soon be possible by shrinking memristors down to 30 nm across. This indicates highly dense 3D structures with a very large number of memristors within very close proximity of one another will be the norm, and coupling memristor theory is of fundamental significance to this field. The use of memristive crossbar architectures has been gaining much traction in computing large sets of data [11–14], and the theory behind memristive coupling is absolutely essential in ensuring information is not lost due to undesirable coupling, or by manufacturing more efficient modes of information storage by utilizing coupling theory.

The coupling effects of capacitors and inductors via electric and magnetic fields are well known. The mutual capacitances and inductances of circuits comprised of multiple TiO2 memristors are dependent upon the physical features of each memristor cell [14], such as size and position. Therefore, coupling is to be expected between adjacent memristors, and must be taken into account when analyzing highly concentrated circuits. In addition to series and parallel connections, coupling has thus been established as a third unique relation in memristive systems [15].

The behavior of coupled memristors was rigorously analyzed in a systematic manner for the first time in Ref. [16] with consideration given to all polarity combinations. The theoretical analysis is confirmed in the same paper by use of a separately presented memristor emulator circuit from Ref. [17]. However, the results in the analysis is based on a memristor which exhibits a linear relationship between memductance and flux. This is obviously not the case for many memristors, such as the simplest case of a flux-controlled switching memristor presented in Ref. [18] where flux is controlled independent of memductance. As such, there is only a very narrow scope of memristors which the research in Ref. [16] applies to. The results in Ref. [18] served to broaden this assumption to ideal switching memristors which operate in two states, and obtain new results based on the same constitutive relation equations. This chapter dissects the results in Ref. [18] and presents them in a more comprehensive format, with the use of fundamental memristor theory to form the basis of the analysis to produce valid results. As such, the findings in this chapter can be applied more broadly and yet maintain the complex behavior which makes the memristor so attractive. The theoretical analysis and analytical solutions provide for novel memductance behavior in terms of flux, charge, voltage and current of ideal memristors. In the process, it is proven that the memristor closure theorem continues to stand for coupled memristors [19].

## 2. Coupled memristors

Each fundamental circuit element holds a relationship between any two of either voltage, current, charge, or flux. The memristor thus becomes a fundamental circuit element as it fills the missing gap of the charge-flux relationship. It is important to note that even though q and ϕ are referred to as charge and flux, they do not have to be associated with a physical charge or real flux as is the case with classical conductors and inductors [4]. The integrating relationship between voltage and flux results in memristors being able to retain history, and exhibiting potentially different current values when the same voltage is applied to it. By definition, this enables the memristor to have different resistance values regardless of identical voltage excitation, stemming from memristance being a function of historical voltage. This gives rise to the

The inherent characteristics of this revolutionary device have enabled its application in a diverse field of areas, including neuromorphic circuits [5] and non-volatile memory applications [6]. These applications often see arrays of memristors behaving compositely with one another. In addition to the functionality of single discrete memristors, the behaviors of multiple

Memristors are polarity dependant—while this complicates circuit analysis, it allows for many more configuration permutations than the other fundamental circuits: the resistor, capacitor and inductor. The behavior of two memristor emulators in both serial and parallel connections are experimentally evaluated in Ref. [7], however, only identical polarity directions are considered. Two charge controlled memristors are connected in series and in parallel in Ref. [8], with their responses evaluated when polarity is varied. The composite behavior is analyzed by probing the relationships between flux, charge and memristance. The results show novel I-V characteristics which will prove to be useful applications in neural networks and logic circuits. The magnetic coupling of memristors are also considered in terms of mutual induction and

Many researchers have sought to use memristors to represent the synapses between neurons in artificial networks, and more recently, a memristive crossbar array has been successfully fabricated which implements a neural network, and is successfully capable of performing limited classifications and simple pattern recognition [10]. By training such networks on sets of known example patterns and tuning the weights of the 'synaptic' connections, unknown patterns and images can be recognized. Ultimately, researchers anticipate that networks with a density of 100 billion synapses per square centimeter in each layer should soon be possible by shrinking memristors down to 30 nm across. This indicates highly dense 3D structures with a very large number of memristors within very close proximity of one another will be the norm, and coupling memristor theory is of fundamental significance to this field. The use of memristive crossbar architectures has been gaining much traction in computing large sets of data [11–14], and the theory behind memristive coupling is absolutely essential in ensuring information is not lost due to undesirable coupling, or by manufacturing more efficient modes

The coupling effects of capacitors and inductors via electric and magnetic fields are well known. The mutual capacitances and inductances of circuits comprised of multiple TiO2 memristors are dependent upon the physical features of each memristor cell [14], such as size and position.

nomenclature surrounding the memristor, a portmanteau of 'memory resistor'.

memristors in structures of connectivity have also been analyzed.

capacitive connections in Ref. [9].

168 Memristor and Memristive Neural Networks

of information storage by utilizing coupling theory.

The two types of ideal memristors considered are charge controlled or flux controlled [2]. The relationship between current and voltage of a charge controlled memristor is expressed by

$$V(t) = M(q)\dot{\imath}(t),\tag{1}$$

where t is time, v(t) is voltage, q(t) is charge and M(q) is memristance. In its derivative form, memristance can be defined as

$$M(q) = d\varphi(q) \Big/\_{d\eta'} \tag{2}$$

where ϕ(q) is flux (the time integral of voltage v(t)). Contrastingly, the current of a flux controlled memristor is

$$\dot{u}(t) = \mathcal{W}(\varphi)\upsilon(t),\tag{3}$$

where W(ϕ) denotes the memductance and

$$\mathcal{W}(\varphi) = d\mathfrak{q}(\varphi) \Big/\_{d\mathfrak{q}}.\tag{4}$$

The memductance W is the slope of the q-ϕ curve, which is a characteristic embedded into the memristor at the time of fabrication.

Flux ϕ and charge q are two intrinsic state variables which affect memductance. Two memristors can be coupled by either flux or charge as shown in Figures 1 and 2.

If two flux controlled memristors are considered, the ideal coupled memristive systems can be defined by the following set of equations,

$$
\dot{u}\_1(t) = W\_1(\varphi\_1, \varphi\_2) v\_1(t),\tag{5a}
$$

φðtÞ ¼ 0:8ð1 � cos tÞ � 0:4, (6a)

http://dx.doi.org/10.5772/intechopen.69327

171

qðtÞ ¼ 0:01φðtÞ þ 0:04 jφðtÞ þ 0:25j � 0:04 jφðtÞ � 0:25j: (6b)

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

Given Eqs. (6a) and (6b), the memductance value can be derived from Eq. (4) and is graphed

Figure 3. The q-ϕ relationship for an ideal switching memristor proposed in Ref. [4].

Figure 4. The memductance curve as a function of time derived from Eqs. (4), (6a), and (6b) displays how a memristor

with a three part piecewise linear relationship between flux can switch between high and low current states.

below in Figure 4.

$$
\dot{v}\_2(t) = W\_2(\varphi\_1, \varphi\_2) v\_2(t),
\tag{5b}
$$

$$d\!d\varphi\_1\Big/\_{\text{dt}} = \upsilon\_1(t), \!d\varphi\_2\Big/\_{\text{dt}} = \upsilon\_2(t). \tag{5c}$$

While a general rule cannot be ascertained which would be applicable for all ideal memristors, the most appropriate manner in approaching the task of modeling a pair of coupled memristors is to provide a procedural methodology instead. This is done by way of example with use of a particular type of switching memristor, complete with a known q-ϕ relationship.

Instead of assuming a linear relationship between memductance and flux as in Ref. [15], it is more appropriate to consider the ideal memristor proposed in Ref. [4], and derive the associated relationship between flux and memductance from a given q-ϕ relationship. An example of an ideal switching memristor is shown below in Figure 3, and the response of the memristor can be completely described by the q-ϕ curve displayed.

For the purposes of this paper, this example of an ideal switching memristor is completely characterized by the following equations:

Figure 1. Dual charge coupled memristors.

Figure 2. Dual flux coupled memristors.

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models http://dx.doi.org/10.5772/intechopen.69327 171

$$
\varphi(t) = 0.8(1 - \cos t) - 0.4,\tag{6a}
$$

$$q(t) = 0.01q(t) + 0.04\left|\varphi(t) + 0.25\right| - 0.04\left|\varphi(t) - 0.25\right|.\tag{6b}$$

Given Eqs. (6a) and (6b), the memductance value can be derived from Eq. (4) and is graphed below in Figure 4.

Figure 3. The q-ϕ relationship for an ideal switching memristor proposed in Ref. [4].

Flux ϕ and charge q are two intrinsic state variables which affect memductance. Two

If two flux controlled memristors are considered, the ideal coupled memristive systems can be

.

dt <sup>¼</sup> <sup>v</sup>1ðtÞ, <sup>d</sup>φ<sup>2</sup>

While a general rule cannot be ascertained which would be applicable for all ideal memristors, the most appropriate manner in approaching the task of modeling a pair of coupled memristors is to provide a procedural methodology instead. This is done by way of example with use of a particular type of switching memristor, complete with a known q-ϕ relationship. Instead of assuming a linear relationship between memductance and flux as in Ref. [15], it is more appropriate to consider the ideal memristor proposed in Ref. [4], and derive the associated relationship between flux and memductance from a given q-ϕ relationship. An example of an ideal switching memristor is shown below in Figure 3, and the response of the memristor

For the purposes of this paper, this example of an ideal switching memristor is completely

i1ðtÞ ¼ W1ðφ1,φ2Þv1ðtÞ, (5a)

i2ðtÞ ¼ W2ðφ1,φ2Þv2ðtÞ, (5b)

dt ¼ v2ðtÞ: (5c)

memristors can be coupled by either flux or charge as shown in Figures 1 and 2.

dφ<sup>1</sup> .

can be completely described by the q-ϕ curve displayed.

characterized by the following equations:

Figure 1. Dual charge coupled memristors.

Figure 2. Dual flux coupled memristors.

defined by the following set of equations,

170 Memristor and Memristive Neural Networks

Figure 4. The memductance curve as a function of time derived from Eqs. (4), (6a), and (6b) displays how a memristor with a three part piecewise linear relationship between flux can switch between high and low current states.

The memductance can be approximated by

$$\mathcal{W} = \begin{cases} \alpha, & |\varphi| < |\varphi\_t| \\ \beta, & |\varphi\_t| < |\varphi| < |\varphi\_{\max}| \end{cases} \tag{7}$$

slope values which correlate to two different states, whereas in the coupled case, there are

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173

Despite this being the result of a specific type of switching memristor, it is reasonable to conclude these two changes will occur in all cases of purely coupled switching memristors.

This result can be exploited in neural circuits where synaptic spikes have more complexity than mere 'ON-OFF states'. On the other hand, it may have an undesirable effect on memristive logic gates where having two states is essential for functionality. Necessary physical precautions must be taken in order to minimize the values of κ<sup>1</sup> and κ<sup>2</sup> for such processes, and to additionally account for excessive current passage through the memristor due to coupling. But if logic gates were to be extended beyond high and low states, then the multiple states of the memristor could

Two different configurations of serially connected memristors exist according to polarity combinations. The same approximation of the ideal memristors will apply to this section in

Connecting terminal B<sup>1</sup> to A<sup>2</sup> allows for a serial circuit structure for two memristors in identical

Applying Kirchhoff's voltage Law (KVL) and equating the current through both memristors,

v12ðtÞ ¼ v<sup>1</sup> þ v2, (9a)

iðtÞ ¼ W1ðφ1,φ2Þv1ðtÞ ¼ W2ðφ2,φ1Þv2ðtÞ: (9b)

be harnessed into a multi-level logic gate on a nanometer scale.

the voltage across and current through A<sup>1</sup> and B<sup>2</sup> can be written as

Figure 5. Memristors serially coupled with identical polarity configuration.

3. Coupled memristors in serial connections

3.1. Serial connection with identical polarities

the same form as in Eq. (7).

polarities as shown in Figure 5.

infinite states.

where α is a constant representing the high memductance state, β is the low memductance state, ϕmax is the maximum value of flux for a given sinusoidal voltage input (which in this particular case can be calculated by substituting t = π rads into Eq. (6a) where ϕmax = 1.2), and ϕ<sup>t</sup> is a certain threshold of flux where both current and memductance become discontinuous (in this case ϕ<sup>t</sup> = 0.4). Once again, it is reiterated that even though q and ϕ are referred to as charge and flux, they are not necessarily associated with real physical charge and flux in the way they are in classical conductors and inductors.

If this specific type of memristor is purely flux coupled with an identical memristor (without any other composite connections), and assuming the simple case of a first order mathematical model of coupling, the individual memductance of each device can be ascertained from Eqs. (5) and (7) as

$$\mathcal{W}\_1(\boldsymbol{\varphi}\_1, \boldsymbol{\varphi}\_2) = \begin{cases} \alpha\_1 + \kappa\_2 \boldsymbol{\varphi}\_{2'} & |\boldsymbol{\varphi}\_1| < |\boldsymbol{\varphi}\_t| \\ \boldsymbol{\beta}\_1 + \kappa\_2 \boldsymbol{\varphi}\_{2'} & |\boldsymbol{\varphi}\_t| < |\boldsymbol{\varphi}\_1| < |\boldsymbol{\varphi}\_{\text{max}}| \end{cases} \tag{8a}$$

$$\mathcal{W}\_2(\boldsymbol{\varphi}\_{2'}\boldsymbol{\varphi}\_1) = \begin{cases} \boldsymbol{\alpha}\_2 + \boldsymbol{\kappa}\_1 \boldsymbol{\varphi}\_{1'} & |\boldsymbol{\varphi}\_1| < |\boldsymbol{\varphi}\_t| \\ \boldsymbol{\beta}\_2 + \boldsymbol{\kappa}\_1 \boldsymbol{\varphi}\_{1'} & |\boldsymbol{\varphi}\_t| < |\boldsymbol{\varphi}\_1| < |\boldsymbol{\varphi}\_{\text{max}}| \end{cases} \tag{8b}$$

The coupling strength between these two memristors is reflected by the coupling coefficients κ<sup>1</sup> and κ<sup>2</sup> which can be tuned based on physical factors in fabrication. Therefore, the two memristors can be tightly or loosely coupled depending on the values of κ<sup>1</sup> and κ2.

A solvable equation with physical meaning requires assumptions about the physical behavior of the memristors. By considering the special case of identical excitations and voltage history (alternatively, the same initial conditions), and allowing for α<sup>1</sup> = α<sup>2</sup> = α, β<sup>1</sup> = β<sup>2</sup> = β, and κ<sup>1</sup> = κ<sup>2</sup> = 0.1 (which can be precisely achieved by fabrication) the constitutive relations are used to identify behavior unachievable by the lone memristor. Memductance after coupling effects in Eq. (8) can be attained by summing flux from Eq. (6a) with memductance from Eq. (7). Current is recalculated to take into account the effect from coupling due to the composite memristor. This can be done by taking the time derivative of Eq. (6a) which is the driving voltage source, and substituting it into Eq. (3).

The I-V characteristic plane can be mapped by considering the two purely coupled memristors (without any other connections) as a single device. This procedure is carried out with two identical ideal flux-coupled memristors represented by Figure 3 and configured as in Figure 2, to provide the I-V characteristics below.

When compared to the original hysteresis loop of just one of the two memristors, there are two notable differences: (i) the current spans a larger range of values due to the additive effect of ϕ<sup>2</sup> on i<sup>1</sup> (conversely, ϕ<sup>1</sup> has an identical effect on i2), and (ii) the single memristor has two different slope values which correlate to two different states, whereas in the coupled case, there are infinite states.

Despite this being the result of a specific type of switching memristor, it is reasonable to conclude these two changes will occur in all cases of purely coupled switching memristors.

This result can be exploited in neural circuits where synaptic spikes have more complexity than mere 'ON-OFF states'. On the other hand, it may have an undesirable effect on memristive logic gates where having two states is essential for functionality. Necessary physical precautions must be taken in order to minimize the values of κ<sup>1</sup> and κ<sup>2</sup> for such processes, and to additionally account for excessive current passage through the memristor due to coupling. But if logic gates were to be extended beyond high and low states, then the multiple states of the memristor could be harnessed into a multi-level logic gate on a nanometer scale.

## 3. Coupled memristors in serial connections

The memductance can be approximated by

172 Memristor and Memristive Neural Networks

way they are in classical conductors and inductors.

W1ðφ1,φ2Þ ¼

W2ðφ2,φ1Þ ¼

(

(

and (7) as

substituting it into Eq. (3).

to provide the I-V characteristics below.

<sup>W</sup> <sup>¼</sup> <sup>α</sup>, <sup>j</sup>φ<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>φ<sup>t</sup>

where α is a constant representing the high memductance state, β is the low memductance state, ϕmax is the maximum value of flux for a given sinusoidal voltage input (which in this particular case can be calculated by substituting t = π rads into Eq. (6a) where ϕmax = 1.2), and ϕ<sup>t</sup> is a certain threshold of flux where both current and memductance become discontinuous (in this case ϕ<sup>t</sup> = 0.4). Once again, it is reiterated that even though q and ϕ are referred to as charge and flux, they are not necessarily associated with real physical charge and flux in the

If this specific type of memristor is purely flux coupled with an identical memristor (without any other composite connections), and assuming the simple case of a first order mathematical model of coupling, the individual memductance of each device can be ascertained from Eqs. (5)

β<sup>1</sup> þ κ2φ2, jφ<sup>t</sup>

β<sup>2</sup> þ κ1φ1, jφ<sup>t</sup>

The coupling strength between these two memristors is reflected by the coupling coefficients κ<sup>1</sup> and κ<sup>2</sup> which can be tuned based on physical factors in fabrication. Therefore, the two

A solvable equation with physical meaning requires assumptions about the physical behavior of the memristors. By considering the special case of identical excitations and voltage history (alternatively, the same initial conditions), and allowing for α<sup>1</sup> = α<sup>2</sup> = α, β<sup>1</sup> = β<sup>2</sup> = β, and κ<sup>1</sup> = κ<sup>2</sup> = 0.1 (which can be precisely achieved by fabrication) the constitutive relations are used to identify behavior unachievable by the lone memristor. Memductance after coupling effects in Eq. (8) can be attained by summing flux from Eq. (6a) with memductance from Eq. (7). Current is recalculated to take into account the effect from coupling due to the composite memristor. This can be done by taking the time derivative of Eq. (6a) which is the driving voltage source, and

The I-V characteristic plane can be mapped by considering the two purely coupled memristors (without any other connections) as a single device. This procedure is carried out with two identical ideal flux-coupled memristors represented by Figure 3 and configured as in Figure 2,

When compared to the original hysteresis loop of just one of the two memristors, there are two notable differences: (i) the current spans a larger range of values due to the additive effect of ϕ<sup>2</sup> on i<sup>1</sup> (conversely, ϕ<sup>1</sup> has an identical effect on i2), and (ii) the single memristor has two different

memristors can be tightly or loosely coupled depending on the values of κ<sup>1</sup> and κ2.

α<sup>1</sup> þ κ2φ2, jφ1j < jφ<sup>t</sup>

α<sup>2</sup> þ κ1φ1, jφ1j < jφ<sup>t</sup>

j

j

j < jφ1j < jφmaxj

j < jφ1j < jφmaxj

β, jφ<sup>t</sup>

�

j

(7)

(8a)

(8b)

j < jφj < jφmaxj

Two different configurations of serially connected memristors exist according to polarity combinations. The same approximation of the ideal memristors will apply to this section in the same form as in Eq. (7).

#### 3.1. Serial connection with identical polarities

Connecting terminal B<sup>1</sup> to A<sup>2</sup> allows for a serial circuit structure for two memristors in identical polarities as shown in Figure 5.

Applying Kirchhoff's voltage Law (KVL) and equating the current through both memristors, the voltage across and current through A<sup>1</sup> and B<sup>2</sup> can be written as

$$
\upsilon\_{12}(t) = \upsilon\_1 + \upsilon\_2.\tag{9a}
$$

$$\dot{a}(t) = \mathcal{W}\_1(\varphi\_{1'}\varphi\_2)\upsilon\_1(t) = \mathcal{W}\_2(\varphi\_{2'}\varphi\_1)\upsilon\_2(t). \tag{9b}$$

Figure 5. Memristors serially coupled with identical polarity configuration.

Integrating both sides of Eq. (9a) leads to Eq. (10a), and substituting Eq. (8) into Eq. (9b) leads to Eq. (10b),

$$
\varphi\_{12}(t) = \varphi\_1 + \varphi\_2 \tag{10a}
$$

$$\begin{split} \dot{\mathbf{u}} &= \upsilon\_1 \left( \begin{cases} \alpha\_1 + \kappa\_2 \wp\_{2\prime} & |\wp\_1| < |\wp\_t| \\ \beta\_1 + \kappa\_2 \wp\_{2\prime} & |\wp\_t| < |\wp\_1| < |\wp\_{\max}| \end{cases} \right) \\ &= \upsilon\_2 \left( \begin{cases} -\alpha\_2 + \kappa\_1 \wp\_{1\prime} & |\wp\_1| < |\wp\_t| \\ -\beta\_2 + \kappa\_1 \wp\_{1\prime} & |\wp\_t| < |\wp\_1| < |\wp\_{\max}| \end{cases} \right) \end{split} \tag{10b}$$

From Eqs. (5), (9a) and (10), and by considering the special case of α<sup>1</sup> = α<sup>2</sup> = α, β<sup>1</sup> = β<sup>2</sup> = β, κ<sup>1</sup> = κ<sup>2</sup> = α, the following set of differential equations are obtained:

$$d\phi\_1 \Big/\_{dt} dt = v\_{12} (1 + \varphi\_1) \Big/\_{\left(2 + \varphi\_{12}\right)} \tag{11a}$$

$$d\boldsymbol{\varphi}\_{2} \Big/ \mathrm{d}\boldsymbol{t} = \boldsymbol{v}\_{12} (1 + \boldsymbol{\varphi}\_{2}) \Big/ (2 + \boldsymbol{\varphi}\_{12}) \tag{11b}$$

state of MR1 from Figure 5 is initially at ϕ<sup>1</sup> = 0 while the flux in MR2 ϕ<sup>2</sup> is varied, a general rule regarding the relationship between c<sup>1</sup> and c<sup>2</sup> with initial condition of MR2 ϕ2(ϕ<sup>1</sup> = 0) = u is

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175

Figure 6. As initial condition u changes, c<sup>1</sup> produces a reciprocal curve and c<sup>2</sup> displays linear behavior.

Substituting u = 0 into Eq. (13b) results in the simple solution of c<sup>1</sup> = c<sup>2</sup> = 1, or ϕ1(ϕ2) = ϕ<sup>2</sup> and ϕ2(ϕ1) = ϕ1. Substituting this into Eq. (10a) results in parity between the flux value of each memristor: ϕ<sup>1</sup> = ϕ<sup>2</sup> = ½ϕ12. Where u = �2, c<sup>1</sup> = c<sup>2</sup> = �1, ϕ1(ϕ2) = ϕ<sup>2</sup> � 2 and ϕ2(ϕ1) = ϕ<sup>1</sup> � 2.

As u increases from 0, c<sup>2</sup> linearly approaches ∞, and c<sup>1</sup> ! 1/∞. As an example, if u = 1, then the constants c<sup>1</sup> = ½, c<sup>2</sup> = 2, and ϕ1(ϕ2) = ½ϕ<sup>2</sup> � ½, ϕ2(ϕ1)=2ϕ<sup>1</sup> + 1. By assuming the excitation voltage is a sinusoidal input, the peak-to-peak amplitude of flux across ϕ<sup>1</sup> is half of that in Serial Case 1, whereas ϕ<sup>2</sup> has quadrupled. A tug-of-war of sorts occurs between ϕ<sup>1</sup> and ϕ2: as ϕ<sup>2</sup> increases, ϕ<sup>1</sup> decreases. Conversely, as u decreases from �2, c<sup>2</sup> ! �∞, and c<sup>1</sup> ! �1/∞.

This case behaves similarly to Case 2, but reversed. As u decreases from 0 towards �1, c1 ! ∞. As u increases from �2 towards �1, c<sup>1</sup> ! �∞. It is asymptotical at u = �1, while c<sup>2</sup> behaves

<sup>c</sup><sup>1</sup> <sup>¼</sup> <sup>1</sup>=ð<sup>1</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> (14a)

c<sup>2</sup> ¼ u þ 1 (14b)

developed and graphed in Figure 6:

3.1.1. Serial Case 1: parity at u = 0, u = �2

3.1.2. Serial Case 2: u = 0 ! ∞,u= �1 ! �∞

3.1.3. Serial Case 3: u = 0 ! �1, u = �2 ! �1

Eq. (11) reflects the complexity of memristive coupling: the derivatives of ϕ<sup>1</sup> and ϕ<sup>2</sup> are both functions of themselves and one another. If ϕ<sup>1</sup> changes due to an excitation voltage, a change in ϕ<sup>2</sup> is observed based on Eq. (11b). The change in ϕ<sup>2</sup> will affect ϕ<sup>1</sup> (independently of the initial excitation change), which goes back around to affect ϕ<sup>2</sup> and so on. The complex behaviors of memristive coupling are reflected in the way the flux variables are entangled in the solution of one another. Time dependence can therefore be eliminated in order to produce a solvable equation by substituting Eqs. (9a) and (10a) into Eq. (11), and dividing Eq. (11a) by Eq. (11b) (resp. Eq. (11b) by Eq. (11a)), which results in

$$d\boldsymbol{\varphi}\_1 \Big/\_{d\boldsymbol{\varphi}\_2} = (1 + \boldsymbol{\varphi}\_2) \Big/\_{(1 + \boldsymbol{\varphi}\_1)}.\tag{12}$$

This can be analytically solved to give

$$
\varphi\_1(\varphi\_2) = \mathfrak{c}\_1 \varphi\_2 + \mathfrak{c}\_1 - 1 \tag{13a}
$$

$$
\varphi\_2(\varphi\_1) = \mathfrak{c}\_2 \varphi\_1 + \mathfrak{c}\_2 - 1,\tag{13b}
$$

where c<sup>1</sup> and c<sup>2</sup> are both constants calculable based on pre-determined initial conditions of ϕ<sup>1</sup> and ϕ2. A number of cases are considered in order to ascertain a general rule for the values of c<sup>1</sup> and c<sup>2</sup> in terms of initial conditions. All of these cases can easily be created by simply biasing the relevant memristor with a rectangular voltage pulse over a given time in order to adjust the initial flux conditions. It is also worth noting that constants c<sup>1</sup> and c<sup>2</sup> can be changed at any time by switching off the driving voltage and re-biasing the memristor values. If it is assumed the flux

Figure 6. As initial condition u changes, c<sup>1</sup> produces a reciprocal curve and c<sup>2</sup> displays linear behavior.

state of MR1 from Figure 5 is initially at ϕ<sup>1</sup> = 0 while the flux in MR2 ϕ<sup>2</sup> is varied, a general rule regarding the relationship between c<sup>1</sup> and c<sup>2</sup> with initial condition of MR2 ϕ2(ϕ<sup>1</sup> = 0) = u is developed and graphed in Figure 6:

$$\mathcal{L}\_1 = \mathbf{1}/(\mathbf{1} + \boldsymbol{\mu})\tag{14a}$$

$$c\_2 = \mu + 1\tag{14b}$$

## 3.1.1. Serial Case 1: parity at u = 0, u = �2

Integrating both sides of Eq. (9a) leads to Eq. (10a), and substituting Eq. (8) into Eq. (9b) leads

α<sup>1</sup> þ κ2φ2, jφ1j < jφ<sup>t</sup>

( !

�α<sup>2</sup> þ κ1φ1, jφ1j < jφ<sup>t</sup>

From Eqs. (5), (9a) and (10), and by considering the special case of α<sup>1</sup> = α<sup>2</sup> = α, β<sup>1</sup> = β<sup>2</sup> = β,

( !

.

.

.

β<sup>1</sup> þ κ2φ2, jφ<sup>t</sup>

�β<sup>2</sup> þ κ1φ1, jφ<sup>t</sup>

dt <sup>¼</sup> <sup>v</sup>12ð<sup>1</sup> <sup>þ</sup> <sup>φ</sup>1<sup>Þ</sup>

dt <sup>¼</sup> <sup>v</sup>12ð<sup>1</sup> <sup>þ</sup> <sup>φ</sup>2<sup>Þ</sup>

<sup>d</sup>φ<sup>2</sup> <sup>¼</sup> <sup>ð</sup><sup>1</sup> <sup>þ</sup> <sup>φ</sup>2<sup>Þ</sup>

where c<sup>1</sup> and c<sup>2</sup> are both constants calculable based on pre-determined initial conditions of ϕ<sup>1</sup> and ϕ2. A number of cases are considered in order to ascertain a general rule for the values of c<sup>1</sup> and c<sup>2</sup> in terms of initial conditions. All of these cases can easily be created by simply biasing the relevant memristor with a rectangular voltage pulse over a given time in order to adjust the initial flux conditions. It is also worth noting that constants c<sup>1</sup> and c<sup>2</sup> can be changed at any time by switching off the driving voltage and re-biasing the memristor values. If it is assumed the flux

Eq. (11) reflects the complexity of memristive coupling: the derivatives of ϕ<sup>1</sup> and ϕ<sup>2</sup> are both functions of themselves and one another. If ϕ<sup>1</sup> changes due to an excitation voltage, a change in ϕ<sup>2</sup> is observed based on Eq. (11b). The change in ϕ<sup>2</sup> will affect ϕ<sup>1</sup> (independently of the initial excitation change), which goes back around to affect ϕ<sup>2</sup> and so on. The complex behaviors of memristive coupling are reflected in the way the flux variables are entangled in the solution of one another. Time dependence can therefore be eliminated in order to produce a solvable equation by substituting Eqs. (9a) and (10a) into Eq. (11), and dividing Eq. (11a) by Eq. (11b)

i ¼ v<sup>1</sup>

¼ v<sup>2</sup>

κ<sup>1</sup> = κ<sup>2</sup> = α, the following set of differential equations are obtained:

dφ<sup>1</sup> .

dφ<sup>2</sup> .

> dφ<sup>1</sup> .

(resp. Eq. (11b) by Eq. (11a)), which results in

This can be analytically solved to give

φ12ðtÞ ¼ φ<sup>1</sup> þ φ<sup>2</sup> (10a)

(10b)

j

j

<sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>φ</sup>12<sup>Þ</sup> (11a)

<sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>φ</sup>12<sup>Þ</sup> (11b)

<sup>ð</sup><sup>1</sup> <sup>þ</sup> <sup>φ</sup>1Þ: (12)

φ1ðφ2Þ ¼ c1φ<sup>2</sup> þ c<sup>1</sup> � 1 (13a)

φ2ðφ1Þ ¼ c2φ<sup>1</sup> þ c<sup>2</sup> � 1, (13b)

j < jφ1j < jφmaxj

j < jφ1j < jφmaxj

to Eq. (10b),

174 Memristor and Memristive Neural Networks

Substituting u = 0 into Eq. (13b) results in the simple solution of c<sup>1</sup> = c<sup>2</sup> = 1, or ϕ1(ϕ2) = ϕ<sup>2</sup> and ϕ2(ϕ1) = ϕ1. Substituting this into Eq. (10a) results in parity between the flux value of each memristor: ϕ<sup>1</sup> = ϕ<sup>2</sup> = ½ϕ12. Where u = �2, c<sup>1</sup> = c<sup>2</sup> = �1, ϕ1(ϕ2) = ϕ<sup>2</sup> � 2 and ϕ2(ϕ1) = ϕ<sup>1</sup> � 2.

## 3.1.2. Serial Case 2: u = 0 ! ∞,u= �1 ! �∞

As u increases from 0, c<sup>2</sup> linearly approaches ∞, and c<sup>1</sup> ! 1/∞. As an example, if u = 1, then the constants c<sup>1</sup> = ½, c<sup>2</sup> = 2, and ϕ1(ϕ2) = ½ϕ<sup>2</sup> � ½, ϕ2(ϕ1)=2ϕ<sup>1</sup> + 1. By assuming the excitation voltage is a sinusoidal input, the peak-to-peak amplitude of flux across ϕ<sup>1</sup> is half of that in Serial Case 1, whereas ϕ<sup>2</sup> has quadrupled. A tug-of-war of sorts occurs between ϕ<sup>1</sup> and ϕ2: as ϕ<sup>2</sup> increases, ϕ<sup>1</sup> decreases. Conversely, as u decreases from �2, c<sup>2</sup> ! �∞, and c<sup>1</sup> ! �1/∞.

## 3.1.3. Serial Case 3: u = 0 ! �1, u = �2 ! �1

This case behaves similarly to Case 2, but reversed. As u decreases from 0 towards �1, c1 ! ∞. As u increases from �2 towards �1, c<sup>1</sup> ! �∞. It is asymptotical at u = �1, while c<sup>2</sup> behaves linearly and passes through 0 at u = �1. The advantage of this case over Case 2 is that much less power is required to bias a memristor between these values in order to attain a flux value that approaches infinity. In other words, given a memristor without state boundary conditions, one can control it to behave like a regular resistor instead if so desired.

## 3.1.4. Serial Case 4: u = �1

Mathematically, there is no solution for c<sup>1</sup> as it approaches �∞ (depending on which side it approaches in accordance with Figure 6). Hence, in theory, MR1 is never in equilibrium when the two memristors are serially flux coupled with identical polarities, where the initial flux value of MR2 is �1 and MR1 is 0. Eq. (13a) shows that as c<sup>1</sup> ! ∞, ϕ<sup>1</sup> ! ∞. If this behavior is mapped against the given charge-flux relationship of the memristor characterized by Figure 3, the top segment of the memristor is a straight line. Therefore, after a sufficiently long time interval, ϕ<sup>1</sup> tends to the breakpoint and the memristor becomes equivalent to a resistor with a resistance of the inverse slope of the final segment (resp. where c<sup>1</sup> ! �∞, ϕ<sup>1</sup> ! �∞ and the memristor becomes equivalent to a resister with the value of the inverse slope of the first segment of the q–ϕ curve).

The effect seen here with flux approaching an infinite value is identical to an ideal memristor being connected to a DC source. A constant non-periodic voltage source will also result in flux tending indefinitely towards �∞, due to the integral relationship implied by Eq. (5c).

This result will not hold true for all ideal memristors [4]. If the memristor was defined by a polynomial <sup>q</sup> – <sup>ϕ</sup> curve, while <sup>ϕ</sup> ! �∞, dq dt ¼ iðtÞ!�∞. This implies that the memristor in question does not have a dc V-I curve, and in practice, the memristor would burn out long before the current became too large. This must also be considered in both Case 2 and Case 3, where current values can potentially go beyond the memristors capacity.

Given a sinusoidal voltage for v<sup>12</sup> from Eq. (9a) in the general form of

$$
\sigma\_{12} = A \sin(2\pi f t),
\tag{15}
$$

v<sup>12</sup> ¼ v<sup>1</sup> þ v<sup>2</sup> ¼ ðγ þ c1γÞ sin ðtÞ (17)

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

γ þ c1γ ¼ A (18)

cos ðtÞ (19a)

http://dx.doi.org/10.5772/intechopen.69327

j

(20a)

177

(20b)

j < jφ1j < jφmaxj

j

j < jφ1j < jφmaxj

<sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> cos <sup>ð</sup>tÞ þ <sup>u</sup> (19b)

Alternatively,

condition u.

W<sup>1</sup> ¼

W<sup>2</sup> ¼

8 ><

>:

8 ><

>:

give

And substituting Eqs. (14) and (18) into Eq. (16) gives

<sup>α</sup><sup>1</sup> � <sup>κ</sup><sup>1</sup> <sup>ð</sup>Að<sup>1</sup> <sup>þ</sup> <sup>u</sup>ÞÞ.

<sup>β</sup><sup>1</sup> � <sup>κ</sup><sup>1</sup> <sup>ð</sup>Að<sup>1</sup> <sup>þ</sup> <sup>u</sup>ÞÞ.

<sup>α</sup><sup>2</sup> � <sup>κ</sup><sup>2</sup> <sup>A</sup> <sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> .

<sup>β</sup><sup>2</sup> � <sup>κ</sup><sup>2</sup> <sup>A</sup> <sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> .

The same methodology applies for the other cases too.

high-low voltage states of the single memristor represented in Figure 4).

<sup>φ</sup>1ðt޼�<sup>A</sup> <sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> .

.

The assumption used in deriving Eq. (14) was that the initial condition of MR1 was ϕ<sup>1</sup> = 0, at which time ϕ<sup>2</sup> = u. Consider when t = π/2 s: ϕ<sup>1</sup> is indeed 0, and ϕ<sup>2</sup> is reduced to the initial

To find memductances W<sup>1</sup> and W<sup>2</sup> after serial coupling Eq. (19) is substituted into Eq. (8) to

<sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> cos <sup>ð</sup>tÞ þ <sup>u</sup> � �, <sup>j</sup>φ1<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>φ<sup>t</sup>

<sup>ð</sup><sup>2</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup> cos <sup>ð</sup>tÞ þ <sup>u</sup> � �, <sup>j</sup>φ<sup>t</sup>

cos ðtÞ � �, <sup>j</sup>φ1<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>φ<sup>t</sup>

cos ðtÞ � �, <sup>j</sup>φ<sup>t</sup>

The memductance (and by extension, current) can therefore be adjusted based on u. Biasing the initial state of MR2's flux for a desired value allows the two memristors to behave harmoniously like a pair of complementary variable switching resistors (while still maintaining the

When u = 0, and in the special case of α<sup>1</sup> = α2, β<sup>1</sup> = β2, and κ<sup>1</sup> = κ2, Eq. (20) shows that W<sup>1</sup> = W<sup>2</sup> and v<sup>1</sup> = v<sup>2</sup> = ½v12. As u increases from 0, W<sup>1</sup> increases and W<sup>2</sup> decreases. This is agreeable with Serial Case 2 of Figure 6: ϕ<sup>2</sup> increases and is the cause for coupling with MR1 which results in the increase of W<sup>1</sup> (resp. the decrease of ϕ<sup>1</sup> as u increases is the cause of the decrease in W2).

While a memristor has a variable resistance by its very definition, this variation is limited by the value of dϕ/dq according to the charge-flux curve. However, when two memristors have an additional parameter u which contributes to this variation, the two serially flux coupled

Figure 7 represents memductances derived from Eq. (18) at κ<sup>1</sup> = κ<sup>2</sup> = 0.02, α<sup>1</sup> = α<sup>2</sup> = 0.1, β<sup>1</sup> = β<sup>2</sup> = 0.01, and as shown in Serial Case 1, when u = 0 the two memristors operate with identical flux values which leads to identical memductance values W<sup>1</sup> = W<sup>2</sup> = W. When the

memristors behave as variable memristors which can be adjusted based on Eq. (20).

<sup>φ</sup>2ðt޼�Að<sup>1</sup> <sup>þ</sup> <sup>u</sup><sup>Þ</sup>

where A is the amplitude of v12, both ϕ<sup>1</sup> and ϕ<sup>2</sup> will take on a sinusoidal form as well, and functions for memductance, voltage and flux can be found in terms of time, initial conditions and amplitude A—all of which can easily be predetermined.

For the sake of both attaining a meaningful solution and demonstration, flux is first determined as a function of time where the term from Eq. (15) (2πf) is assumed to be 1 rad. This simplification yields

$$
\varphi\_2(t) = -\gamma \cos(t) + \mu,\tag{16a}
$$

where γ is the amplitude of ϕ2, and if Eq. (16a) is substituted into Eq. (13a) results in

$$
\varphi\_1(t) = -c\_1 \gamma \cos \left(t\right) + (c\_1 \mu + c\_1 - 1). \tag{16b}
$$

Substituting Eq. (16) into Eqs. (9a) and (5c) results in

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models http://dx.doi.org/10.5772/intechopen.69327 177

$$
\upsilon\_{12} = \upsilon\_1 + \upsilon\_2 = (\gamma + c\_1 \gamma) \sin \left( t \right) \tag{17}
$$

Alternatively,

linearly and passes through 0 at u = �1. The advantage of this case over Case 2 is that much less power is required to bias a memristor between these values in order to attain a flux value that approaches infinity. In other words, given a memristor without state boundary conditions,

Mathematically, there is no solution for c<sup>1</sup> as it approaches �∞ (depending on which side it approaches in accordance with Figure 6). Hence, in theory, MR1 is never in equilibrium when the two memristors are serially flux coupled with identical polarities, where the initial flux value of MR2 is �1 and MR1 is 0. Eq. (13a) shows that as c<sup>1</sup> ! ∞, ϕ<sup>1</sup> ! ∞. If this behavior is mapped against the given charge-flux relationship of the memristor characterized by Figure 3, the top segment of the memristor is a straight line. Therefore, after a sufficiently long time interval, ϕ<sup>1</sup> tends to the breakpoint and the memristor becomes equivalent to a resistor with a resistance of the inverse slope of the final segment (resp. where c<sup>1</sup> ! �∞, ϕ<sup>1</sup> ! �∞ and the memristor becomes equivalent to a resister with the value of the inverse slope of the first

The effect seen here with flux approaching an infinite value is identical to an ideal memristor being connected to a DC source. A constant non-periodic voltage source will also result in flux

This result will not hold true for all ideal memristors [4]. If the memristor was defined by a

question does not have a dc V-I curve, and in practice, the memristor would burn out long before the current became too large. This must also be considered in both Case 2 and Case 3,

where A is the amplitude of v12, both ϕ<sup>1</sup> and ϕ<sup>2</sup> will take on a sinusoidal form as well, and functions for memductance, voltage and flux can be found in terms of time, initial conditions

For the sake of both attaining a meaningful solution and demonstration, flux is first determined as a function of time where the term from Eq. (15) (2πf) is assumed to be 1 rad. This

where γ is the amplitude of ϕ2, and if Eq. (16a) is substituted into Eq. (13a) results in

dt ¼ iðtÞ!�∞. This implies that the memristor in

v<sup>12</sup> ¼ A sin ð2πf tÞ, (15)

φ2ðtÞ¼ �γ cos ðtÞ þ u, (16a)

φ1ðtÞ¼ �c1γ cos ðtÞþðc1u þ c<sup>1</sup> � 1Þ: (16b)

tending indefinitely towards �∞, due to the integral relationship implied by Eq. (5c).

where current values can potentially go beyond the memristors capacity.

Given a sinusoidal voltage for v<sup>12</sup> from Eq. (9a) in the general form of

and amplitude A—all of which can easily be predetermined.

Substituting Eq. (16) into Eqs. (9a) and (5c) results in

one can control it to behave like a regular resistor instead if so desired.

3.1.4. Serial Case 4: u = �1

176 Memristor and Memristive Neural Networks

segment of the q–ϕ curve).

simplification yields

polynomial <sup>q</sup> – <sup>ϕ</sup> curve, while <sup>ϕ</sup> ! �∞, dq

$$
\gamma + \mathfrak{c}\_1 \mathfrak{y} = A \tag{18}
$$

And substituting Eqs. (14) and (18) into Eq. (16) gives

$$\varphi\_1(t) = -A \Big/ (2+u) \cos \left(t \right) \tag{19a}$$

$$\varphi\_2(t) = -A(1+u)\Big/(2+u)\cos\left(t\right) + u \tag{19b}$$

The assumption used in deriving Eq. (14) was that the initial condition of MR1 was ϕ<sup>1</sup> = 0, at which time ϕ<sup>2</sup> = u. Consider when t = π/2 s: ϕ<sup>1</sup> is indeed 0, and ϕ<sup>2</sup> is reduced to the initial condition u.

To find memductances W<sup>1</sup> and W<sup>2</sup> after serial coupling Eq. (19) is substituted into Eq. (8) to give

$$\begin{aligned} W\_1 &= \begin{cases} a\_1 - \kappa\_1 \left( (A(1+u)) \Big/ (2+u) \cos \left( t \right) + u \right), & |\varphi\_1| < |\varphi\_t| \\ \beta\_1 - \kappa\_1 \left( (A(1+u)) \Big/ (2+u) \cos \left( t \right) + u \right), & |\varphi\_t| < |\varphi\_1| < |\varphi\_{\text{max}}| \end{cases} \end{aligned} \tag{20a}$$
 
$$W\_2 = \begin{cases} a\_2 - \kappa\_2 \left( A \Big/ (2+u) \cos \left( t \right) \right), & |\varphi\_1| < |\varphi\_t| \\ \beta\_2 - \kappa\_2 \left( A \Big/ (2+u) \cos \left( t \right) \right), & |\varphi\_t| < |\varphi\_1| < |\varphi\_{\text{max}}| \end{cases} \tag{20b}$$

The memductance (and by extension, current) can therefore be adjusted based on u. Biasing the initial state of MR2's flux for a desired value allows the two memristors to behave harmoniously like a pair of complementary variable switching resistors (while still maintaining the high-low voltage states of the single memristor represented in Figure 4).

When u = 0, and in the special case of α<sup>1</sup> = α2, β<sup>1</sup> = β2, and κ<sup>1</sup> = κ2, Eq. (20) shows that W<sup>1</sup> = W<sup>2</sup> and v<sup>1</sup> = v<sup>2</sup> = ½v12. As u increases from 0, W<sup>1</sup> increases and W<sup>2</sup> decreases. This is agreeable with Serial Case 2 of Figure 6: ϕ<sup>2</sup> increases and is the cause for coupling with MR1 which results in the increase of W<sup>1</sup> (resp. the decrease of ϕ<sup>1</sup> as u increases is the cause of the decrease in W2). The same methodology applies for the other cases too.

While a memristor has a variable resistance by its very definition, this variation is limited by the value of dϕ/dq according to the charge-flux curve. However, when two memristors have an additional parameter u which contributes to this variation, the two serially flux coupled memristors behave as variable memristors which can be adjusted based on Eq. (20).

Figure 7 represents memductances derived from Eq. (18) at κ<sup>1</sup> = κ<sup>2</sup> = 0.02, α<sup>1</sup> = α<sup>2</sup> = 0.1, β<sup>1</sup> = β<sup>2</sup> = 0.01, and as shown in Serial Case 1, when u = 0 the two memristors operate with identical flux values which leads to identical memductance values W<sup>1</sup> = W<sup>2</sup> = W. When the

Figure 7. The memductance curve of serially coupled memristors, u = 0 for W, and u = 0.02 for W<sup>1</sup> and W2.

initial condition of MR2 is changed to u = 0.02, the memductance of MR1 shifts upwards while the memductance of MR2 is approximately the same as W.

#### 3.2. Serial connection with opposite polarities

Following a similar procedure to above where one of two memristors in Figure 8 are flipped such that either terminals A<sup>1</sup> and A2, or B<sup>1</sup> and B<sup>2</sup> are connected, as shown in Figure 9, applying KVL to Eqs. (5) and (8) yields

$$\begin{split} \dot{\varrho}\_{t} &= \upsilon\_{1} \begin{cases} \alpha\_{1} - \kappa\_{2} \varrho\_{2^{\prime}} & |\varrho\_{1}| < |\varrho\_{t}| \\ \beta\_{1} - \kappa\_{2} \varrho\_{2^{\prime}} & |\varrho\_{t}| < |\varrho\_{1}| < |\varrho\_{\max}| \end{cases} \\ &= \upsilon\_{2} \begin{cases} -\alpha\_{2} + \kappa\_{1} \varrho\_{1^{\prime}} & |\varrho\_{1}| < |\varrho\_{t}| \\ -\beta\_{2} + \kappa\_{1} \varrho\_{1^{\prime}} & |\varrho\_{t}| < |\varrho\_{1}| < |\varrho\_{\max}| \end{cases} \end{split} \tag{21}$$

and substituting Eq. (5c) along with the same assumptions β<sup>1</sup> = β<sup>2</sup> = β, α<sup>1</sup> = α<sup>2</sup> = κ<sup>1</sup> = κ<sup>2</sup> = α into Eq. (21) results in the following differential equations

$$d\phi\_1 \Big/\_{dt} = -(1+\varphi\_1) \Big/\_{(1-\varphi\_2)}\tag{22a}$$

<sup>φ</sup><sup>1</sup> <sup>¼</sup> <sup>1</sup> 2

<sup>φ</sup><sup>2</sup> <sup>¼</sup> <sup>1</sup><sup>=</sup>

into Eq. (8), and assuming β<sup>1</sup> = β<sup>2</sup> = β, α<sup>1</sup> = α<sup>2</sup> = α, κ<sup>1</sup> = κ<sup>2</sup> = κ.

Figure 9. Memristors serially coupled with opposite polarity configuration.

I-V characteristic of just one memristor I-V1.

ð�1 þ e 2t

<sup>2</sup> � <sup>ð</sup><sup>e</sup> �2t

Figure 8. The I-V characteristic of two identical flux-coupled memristors shown in Figure 2 denoted I-V<sup>2</sup> compared to the

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

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179

Therefore, memductance of the individual memristor can be obtained by substituting Eq. (23)

Þ, (23a)

Þ=2 (23b)

$$d\phi\_2 \Big/\_{dt} = -(1 - \varphi\_2) \Big/\_{(1 + \varphi\_1)\_t} \tag{22b}$$

which solving simultaneously assuming initial conditions ϕ1(t) = ϕ2(t) = ϕ(0) results Eqs. (23a) and (23b), pictorially represented in Figure 10.

Figure 8. The I-V characteristic of two identical flux-coupled memristors shown in Figure 2 denoted I-V<sup>2</sup> compared to the I-V characteristic of just one memristor I-V1.

Figure 9. Memristors serially coupled with opposite polarity configuration.

initial condition of MR2 is changed to u = 0.02, the memductance of MR1 shifts upwards while

Figure 7. The memductance curve of serially coupled memristors, u = 0 for W, and u = 0.02 for W<sup>1</sup> and W2.

Following a similar procedure to above where one of two memristors in Figure 8 are flipped such that either terminals A<sup>1</sup> and A2, or B<sup>1</sup> and B<sup>2</sup> are connected, as shown in Figure 9,

α<sup>1</sup> � κ2φ2, jφ1j < jφ<sup>t</sup>

�α<sup>2</sup> þ κ1φ1, jφ1j < jφ<sup>t</sup>

.

.

and substituting Eq. (5c) along with the same assumptions β<sup>1</sup> = β<sup>2</sup> = β, α<sup>1</sup> = α<sup>2</sup> = κ<sup>1</sup> = κ<sup>2</sup> = α into

dt ¼ �ð<sup>1</sup> <sup>þ</sup> <sup>φ</sup>1<sup>Þ</sup>

dt ¼ �ð<sup>1</sup> � <sup>φ</sup>2<sup>Þ</sup>

which solving simultaneously assuming initial conditions ϕ1(t) = ϕ2(t) = ϕ(0) results Eqs. (23a)

β<sup>1</sup> � κ2φ2, jφ<sup>t</sup>

�β<sup>2</sup> þ κ1φ1, jφ<sup>t</sup>

j

j

<sup>ð</sup><sup>1</sup> � <sup>φ</sup>2<sup>Þ</sup> (22a)

<sup>ð</sup><sup>1</sup> <sup>þ</sup> <sup>φ</sup>1Þ, (22b)

( (21)

j < jφ1j < jφmaxj

j < jφ1j < jφmaxj

the memductance of MR2 is approximately the same as W.

i ¼ v<sup>1</sup>

¼ v<sup>2</sup>

Eq. (21) results in the following differential equations

and (23b), pictorially represented in Figure 10.

(

dφ<sup>1</sup> .

dφ<sup>2</sup> .

3.2. Serial connection with opposite polarities

applying KVL to Eqs. (5) and (8) yields

178 Memristor and Memristive Neural Networks

$$
\varphi\_1 = \frac{1}{2}(-1 + \varepsilon^{2t}),
\tag{23a}
$$

$$
\varphi\_2 = \mathbb{Y}\_2 - \left(\mathbb{e}^{-2t}\right)/2 \tag{23b}
$$

Therefore, memductance of the individual memristor can be obtained by substituting Eq. (23) into Eq. (8), and assuming β<sup>1</sup> = β<sup>2</sup> = β, α<sup>1</sup> = α<sup>2</sup> = α, κ<sup>1</sup> = κ<sup>2</sup> = κ.

Figure 10. Flux variation with time in anti-serial connection: figure on left displaying ϕ1(t) from Eq. (23a); figure on right figure showing ϕ2(t) from Eq. (23b).

$$W\_1(\boldsymbol{\wp}\_1, t) = \begin{cases} \alpha + \kappa \left( \frac{1}{2} - \frac{e^{-2t}}{2} \right), & |\boldsymbol{\wp}\_1| < |\boldsymbol{\wp}\_t| \\\\ \boldsymbol{\beta} + \kappa \left( \frac{1}{2} - \frac{e^{-2t}}{2} \right), & |\boldsymbol{\wp}\_t| < |\boldsymbol{\wp}\_1| < |\boldsymbol{\wp}\_{\max}| \end{cases} \tag{24a}$$
 
$$W\_2(\boldsymbol{\wp}\_{2^t}, t) = \begin{cases} \alpha + \frac{\kappa}{2} (-1 + e^{2t}), & |\boldsymbol{\wp}\_2| < |\boldsymbol{\wp}\_t| \\\\ \boldsymbol{\beta} + \frac{\kappa}{2} (-1 + e^{2t}), & |\boldsymbol{\wp}\_t| < |\boldsymbol{\wp}\_2| < |\boldsymbol{\wp}\_{\max}| \end{cases} \tag{24b}$$

these memristors will not display this behavior independently and so it is more practical to consider the two memristors as a single black box device. Equivalent memductance across A<sup>1</sup>

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

Two different configurations of parallel connected memristors exist according to polarity combinations, just as is the case with serially connected memristors. The same approximation of the ideal memristors will apply to this section in the same form as in Eq. (7). The first case to consider where memristors are configured with identical polarities is depicted in Figure 11.

The current passing through A<sup>1</sup> and B<sup>2</sup> as well as flux ϕ<sup>12</sup> can be derived from Kirchhoff's

<sup>i</sup> <sup>¼</sup> <sup>v</sup>1ðα<sup>1</sup> <sup>þ</sup> <sup>κ</sup>2φ2Þ þ <sup>v</sup>2ðα<sup>2</sup> <sup>þ</sup> <sup>κ</sup>1φ1Þ, <sup>j</sup>φ12<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>2φ<sup>t</sup>

1 2

<sup>ð</sup>κ<sup>1</sup> <sup>þ</sup> <sup>κ</sup>2Þφ<sup>2</sup>

<sup>ð</sup>κ<sup>1</sup> <sup>þ</sup> <sup>κ</sup>2Þφ<sup>2</sup>

<sup>12</sup>, j2φ<sup>t</sup>

v1ðβ<sup>1</sup> þ κ2φ2Þ þ v2ðβ<sup>2</sup> þ κ1φ1Þ, j2φ<sup>t</sup>

ðα<sup>1</sup> þ α2Þφ<sup>12</sup> þ

Figure 11. Coupled memristors connected in parallel with identical polarity configuration.

1 2

ðβ<sup>1</sup> þ β2Þφ<sup>12</sup> þ

i ¼ i<sup>1</sup> þ i2, φ<sup>12</sup> ¼ φ<sup>1</sup> þ φ2, (25)

<sup>12</sup>, jφ12j < j2φ<sup>t</sup>

j < jφ12j < j2φmaxj

j < jφ12j < j2φmaxj

j

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j

(26)

181

(27)

and A<sup>2</sup> can be numerically obtained as W1W2/(W1+W2) based on values of α, β and κ.

4. Coupled memristors in parallel connections

4.1. Parallel connection with identical polarities

(

8 >><

>>:

Memductance can accordingly be calculated,

Integration both sides of Eq. (24) yields

q ¼

Current Law (KCL) and Eq. (8),

In Figure 10, ϕ1(t) never stops, but increases to +∞. Hence, just as calculated in Serial Case 4 of 'Serial Connection with Identical Polarities', one of two ideal memristors can never be in equilibrium when coupled in anti-serial connection.

Once again, this behavior is mapped against the given charge-flux relationship of the switching memristor characterized by the shape of the curve in Figure 3. The first and final segments of the curve are theoretically non-ending straight lines, and thus, after a voltage pulse is applied for a sufficiently long time interval to increase flux far beyond the upper breakpoint ϕ<sup>1</sup> = 0.25 (resp. a negative voltage pulse to decrease flux beyond the lower breakpoint ϕ<sup>1</sup> = �0.25), the memristor becomes the equivalent of a resistor with the resistance value of the inverse slope of the final segment.

This behavior is considered comparatively against a single ideal memristor excited by a DC voltage. Suppose a battery with voltage E volts is connected across this memristor at t = 0. Where E > 0, ϕ(t) tends towards +∞. Just as in the case of MR1 of the two anti-serially fluxcoupled memristors, the DC-excited memristor is equivalent to a resistor with value of the inverse of the charge-flux slope.

Ignoring threshold switching effects, the memductance of MR1 reaches a steady state value while MR2 never achieves stability and instead tends towards a perfect conductor. However, these memristors will not display this behavior independently and so it is more practical to consider the two memristors as a single black box device. Equivalent memductance across A<sup>1</sup> and A<sup>2</sup> can be numerically obtained as W1W2/(W1+W2) based on values of α, β and κ.

#### 4. Coupled memristors in parallel connections

Two different configurations of parallel connected memristors exist according to polarity combinations, just as is the case with serially connected memristors. The same approximation of the ideal memristors will apply to this section in the same form as in Eq. (7). The first case to consider where memristors are configured with identical polarities is depicted in Figure 11.

#### 4.1. Parallel connection with identical polarities

The current passing through A<sup>1</sup> and B<sup>2</sup> as well as flux ϕ<sup>12</sup> can be derived from Kirchhoff's Current Law (KCL) and Eq. (8),

$$\mathbf{i} = \mathbf{i}\_1 + \mathbf{i}\_2 \cdot \boldsymbol{\varrho}\_{12} = \boldsymbol{\varrho}\_1 + \boldsymbol{\varrho}\_{2'} \tag{25}$$

$$\dot{q} = \begin{cases} \upsilon\_1(\alpha\_1 + \kappa\_2 \wp\_2) + \upsilon\_2(\alpha\_2 + \kappa\_1 \wp\_1), \ |\wp\_{12}| < |2\wp\_t| \\ \upsilon\_1(\beta\_1 + \kappa\_2 \wp\_2) + \upsilon\_2(\beta\_2 + \kappa\_1 \wp\_1), |2\wp\_t| < |\wp\_{12}| < |2\wp\_{\text{max}}| \end{cases} \tag{26}$$

Integration both sides of Eq. (24) yields

W1ðφ1, tÞ ¼

figure showing ϕ2(t) from Eq. (23b).

180 Memristor and Memristive Neural Networks

W2ðφ2, tÞ ¼

equilibrium when coupled in anti-serial connection.

value of the inverse slope of the final segment.

inverse of the charge-flux slope.

α þ κ

8 >>><

>>>:

8 ><

>:

β þ κ

α þ κ <sup>2</sup> ð�<sup>1</sup> <sup>þ</sup> <sup>e</sup>

β þ κ <sup>2</sup> ð�<sup>1</sup> <sup>þ</sup> <sup>e</sup>

1 <sup>2</sup> � <sup>e</sup>�2<sup>t</sup> 2 � �

Figure 10. Flux variation with time in anti-serial connection: figure on left displaying ϕ1(t) from Eq. (23a); figure on right

1 <sup>2</sup> � <sup>e</sup>�2<sup>t</sup> 2 � �

, jφ1j < jφ<sup>t</sup>

Þ, jφ2j < jφ<sup>t</sup>

, jφ<sup>t</sup>

2t

2t Þ, jφ<sup>t</sup>

In Figure 10, ϕ1(t) never stops, but increases to +∞. Hence, just as calculated in Serial Case 4 of 'Serial Connection with Identical Polarities', one of two ideal memristors can never be in

Once again, this behavior is mapped against the given charge-flux relationship of the switching memristor characterized by the shape of the curve in Figure 3. The first and final segments of the curve are theoretically non-ending straight lines, and thus, after a voltage pulse is applied for a sufficiently long time interval to increase flux far beyond the upper breakpoint ϕ<sup>1</sup> = 0.25 (resp. a negative voltage pulse to decrease flux beyond the lower breakpoint ϕ<sup>1</sup> = �0.25), the memristor becomes the equivalent of a resistor with the resistance

This behavior is considered comparatively against a single ideal memristor excited by a DC voltage. Suppose a battery with voltage E volts is connected across this memristor at t = 0. Where E > 0, ϕ(t) tends towards +∞. Just as in the case of MR1 of the two anti-serially fluxcoupled memristors, the DC-excited memristor is equivalent to a resistor with value of the

Ignoring threshold switching effects, the memductance of MR1 reaches a steady state value while MR2 never achieves stability and instead tends towards a perfect conductor. However,

j

j

(24a)

(24b)

j < jφ1j < jφmaxj

j < jφ2j < jφmaxj:

$$q = \begin{cases} \left. (\alpha\_1 + \alpha\_2) q \right|\_{12} + \frac{1}{2} (\kappa\_1 + \kappa\_2) q\_{12'}^2 \left| q\_{12} \right| < |2\varrho\_t| \\\\ (\beta\_1 + \beta\_2) q\_{12} + \frac{1}{2} (\kappa\_1 + \kappa\_2) q\_{12'}^2 \left| 2\varrho\_t \right| < |q\_{12}| < |2\varrho\_{\max}| \end{cases} \tag{27}$$

Memductance can accordingly be calculated,

Figure 11. Coupled memristors connected in parallel with identical polarity configuration.

$$W\_{12}(\boldsymbol{\varphi}\_{12}) = \frac{d\boldsymbol{q}(\boldsymbol{\varphi}\_{12})}{d\boldsymbol{\varphi}\_{12}} = \begin{cases} \left(\kappa\_1 + \kappa\_2\right)\boldsymbol{\varphi}\_{12} + \alpha\_1 + \alpha\_2 \ |\boldsymbol{\varphi}\_{12}| < |2\boldsymbol{\varphi}\_t|\\ \left(\kappa\_1 + \kappa\_2\right)\boldsymbol{\varphi}\_{12} + \boldsymbol{\beta}\_1 + \boldsymbol{\beta}\_{2'} \ |2\boldsymbol{\varphi}\_t| < |\boldsymbol{\varphi}\_{12}| < |2\boldsymbol{\varphi}\_{\text{max}}| \end{cases} \tag{28}$$

Finally, substituting Eq. (30) into Eq. (4) gives the total memductance of the coupled memristors

For the uncoupled case of κ<sup>1</sup> = κ<sup>2</sup> = 0, the parallel memristors operate as a new memristor where the memductance states (α1, α2, β1, β2) are additive, and all contribute towards the total coupled memductance. This particular aspect of the relationship is common to both parallel connection combinations when polarity is changed. The difference between the two cases is in

A comprehensive theoretical analysis of flux coupled memristors displays various kinds of new behaviour which are otherwise unattainable from a single memristor. The simplest case of coupling between two switching memristors is shown to have a diverse range of properties when memristors are acting in composite with each other. The results presented only consider bi-state memristors, and as such, we can expect different types of memristors with different charge-flux relationships to expand the types of dynamic behaviors exhibited, with the ability to modify the states attainable by tuning the variables associated with the coupling coefficient (such as physical proximity and device material just to name a couple

In summary, two serially connected memristors with identical polarities are shown to produce a pair of variable memristors determinable from initial conditions; two serially connected memristors with opposite polarities display behavior often displayed by memristors connected to DC sources, or otherwise resistive behavior. Parallel memristive systems are shown to produce a variation rate in terms of the coupling coefficients. This is a feature that can be

Further, what has been considered in this paper is the simplest case of identical memristors with identical initial conditions. The potential application of coupled memristors, in addition to the undoubtedly interesting characteristics of arrays of coupled memristors will serve to open up new avenues of applications, and also provide for guidelines on avoiding undesirable behaviors by having fabrication plants devise methods to reduce the coupling coefficient as low as practicable where design specifications see it fit. In particular, where neural networks will see densely populated circuits which depend on memristors behaving functionally, the effects of coupling must either be mitigated to avoid unexpected and fallible outcomes. The alternative view is that memristive coupling makes it possible to have more than two states between a pair of memristors which would otherwise only be capable of being switched either on or off, and as such, if these intermediary states are quantized, then a large system of many varying states can be produced out of a mere two memristors

<sup>¼</sup> <sup>ð</sup>κ<sup>1</sup> � <sup>κ</sup>2Þφ<sup>12</sup> <sup>þ</sup> <sup>α</sup><sup>1</sup> <sup>þ</sup> <sup>α</sup>2, <sup>j</sup>φ12<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>2φ<sup>t</sup>

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

ðκ<sup>1</sup> � κ2Þφ<sup>12</sup> þ β<sup>1</sup> þ β2, j2φ<sup>t</sup>

j

http://dx.doi.org/10.5772/intechopen.69327

(31)

183

j < jφ12j < j2φmaxj

in parallel connection:

5. Conclusion

of examples).

<sup>W</sup>12ðφ12Þ ¼ dqðφ12<sup>Þ</sup>

the effect of the coupling coefficient.

determined at the time of fabrication.

connected compositely.

dφ<sup>12</sup>

In this case the variation between the memductance and flux ϕ<sup>12</sup> is dependent on the total of the coupling coefficient values, κ<sup>1</sup> + κ2. While the total coupling coefficient is positive, memductance is in positive proportion to the excitation flux: a higher flux will result in higher memductance. Conversely, when the total coupling coefficient is negative, the memductance will linearly decrease with the increase of flux. It can be clearly observed from Eq. (28) that flux coupled memristors in parallel connection behave as a new flux controlled memristor, with the equivalent memductance equivalent to the sum of the individual memductances.

#### 4.2. Parallel connection with opposite polarities

A similar procedure can be used in order to ascertain the behavior of anti-parallel connected flux coupled memristors.

In the case shown in Figure 12, the current and flux across terminals A<sup>1</sup> and A<sup>2</sup> are also derived from KCL with the same relationship as in Eq. (25). When considered with respect to Eqs. (3) and (8), and using similar mathematical derivations to the previous sections the following result is obtained:

$$\dot{\mathbf{u}}(t) = \begin{cases} \boldsymbol{\upsilon}\_{1}(\boldsymbol{\alpha}\_{1} - \boldsymbol{\kappa}\_{2}\boldsymbol{\varrho}\_{2}) + \boldsymbol{\upsilon}\_{2}(\boldsymbol{\alpha}\_{2} + \boldsymbol{\kappa}\_{1}\boldsymbol{\varrho}\_{1}), \ |\boldsymbol{\varrho}\_{12}| < |2\boldsymbol{\varrho}\_{t}|\\ \boldsymbol{\upsilon}\_{1}(\boldsymbol{\beta}\_{1} - \boldsymbol{\kappa}\_{2}\boldsymbol{\varrho}\_{2}) + \boldsymbol{\upsilon}\_{2}(\boldsymbol{\beta}\_{2} + \boldsymbol{\kappa}\_{1}\boldsymbol{\varrho}\_{1}), |2\boldsymbol{\varrho}\_{t}| < |\boldsymbol{\varrho}\_{12}| < |2\boldsymbol{\varrho}\_{\max}| \end{cases} \tag{29}$$

Integrating both sides of Eq. (29) results in a coupled charge-flux relationship as shown below,

$$q = \begin{cases} & (\alpha\_1 + \alpha\_2)\wp\_{12} + \frac{1}{2}(\kappa\_1 - \kappa\_2)\wp\_{12'}^2 \ |\wp\_{12}| < |2\wp\_t|\\ & (\beta\_1 + \beta\_2)\wp\_{12} + \frac{1}{2}(\kappa\_1 - \kappa\_2)\wp\_{12'}^2 \ |2\wp\_t| < |\wp\_{12}| < |2\wp\_{\text{max}}| \end{cases} \tag{30}$$

Figure 12. Coupled memristors connected in parallel with opposite polarity configuration.

Finally, substituting Eq. (30) into Eq. (4) gives the total memductance of the coupled memristors in parallel connection:

$$W\_{12}(\boldsymbol{\wp}\_{12}) = \frac{d\boldsymbol{\eta}(\boldsymbol{\wp}\_{12})}{d\boldsymbol{\wp}\_{12}} = \begin{cases} (\kappa\_1 - \kappa\_2)\boldsymbol{\wp}\_{12} + \alpha\_1 + a\_{2\prime} \ |\boldsymbol{\wp}\_{12}| < |2\boldsymbol{\wp}\_t| \\\ (\kappa\_1 - \kappa\_2)\boldsymbol{\wp}\_{12} + \beta\_1 + \beta\_{2\prime} \ |2\boldsymbol{\wp}\_t| < |\boldsymbol{\wp}\_{12}| < |2\boldsymbol{\wp}\_{\text{max}}| \end{cases} \tag{31}$$

For the uncoupled case of κ<sup>1</sup> = κ<sup>2</sup> = 0, the parallel memristors operate as a new memristor where the memductance states (α1, α2, β1, β2) are additive, and all contribute towards the total coupled memductance. This particular aspect of the relationship is common to both parallel connection combinations when polarity is changed. The difference between the two cases is in the effect of the coupling coefficient.

## 5. Conclusion

<sup>W</sup>12ðφ12Þ ¼ dqðφ12<sup>Þ</sup>

182 Memristor and Memristive Neural Networks

dφ<sup>12</sup>

4.2. Parallel connection with opposite polarities

flux coupled memristors.

iðtÞ ¼

(

8 ><

>:

<sup>q</sup> <sup>¼</sup> <sup>ð</sup>α<sup>1</sup> <sup>þ</sup> <sup>α</sup>2Þφ<sup>12</sup> <sup>þ</sup>

ðβ<sup>1</sup> þ β2Þφ<sup>12</sup> þ

Figure 12. Coupled memristors connected in parallel with opposite polarity configuration.

result is obtained:

(

<sup>¼</sup> <sup>ð</sup>κ<sup>1</sup> <sup>þ</sup> <sup>κ</sup>2Þφ<sup>12</sup> <sup>þ</sup> <sup>α</sup><sup>1</sup> <sup>þ</sup> <sup>α</sup>2, <sup>j</sup>φ12<sup>j</sup> <sup>&</sup>lt; <sup>j</sup>2φ<sup>t</sup>

ðκ<sup>1</sup> þ κ2Þφ<sup>12</sup> þ β<sup>1</sup> þ β2, j2φ<sup>t</sup>

In this case the variation between the memductance and flux ϕ<sup>12</sup> is dependent on the total of the coupling coefficient values, κ<sup>1</sup> + κ2. While the total coupling coefficient is positive, memductance is in positive proportion to the excitation flux: a higher flux will result in higher memductance. Conversely, when the total coupling coefficient is negative, the memductance will linearly decrease with the increase of flux. It can be clearly observed from Eq. (28) that flux coupled memristors in parallel connection behave as a new flux controlled memristor, with the

A similar procedure can be used in order to ascertain the behavior of anti-parallel connected

In the case shown in Figure 12, the current and flux across terminals A<sup>1</sup> and A<sup>2</sup> are also derived from KCL with the same relationship as in Eq. (25). When considered with respect to Eqs. (3) and (8), and using similar mathematical derivations to the previous sections the following

Integrating both sides of Eq. (29) results in a coupled charge-flux relationship as shown below,

1 2

<sup>ð</sup>κ<sup>1</sup> � <sup>κ</sup>2Þφ<sup>2</sup>

v1ðβ<sup>1</sup> � κ2φ2Þ þ v2ðβ<sup>2</sup> þ κ1φ1Þ, j2φ<sup>t</sup>

1 2

v1ðα<sup>1</sup> � κ2φ2Þ þ v2ðα<sup>2</sup> þ κ1φ1Þ, jφ12j < j2φ<sup>t</sup>

<sup>ð</sup>κ<sup>1</sup> � <sup>κ</sup>2Þφ<sup>2</sup>

<sup>12</sup>, j2φ<sup>t</sup>

equivalent memductance equivalent to the sum of the individual memductances.

j

(28)

(29)

(30)

j < jφ12j < j2φmaxj

j

j

j < jφ12j < j2φmaxj

j < jφ12j < j2φmaxj

<sup>12</sup>, jφ12j < j2φ<sup>t</sup>

A comprehensive theoretical analysis of flux coupled memristors displays various kinds of new behaviour which are otherwise unattainable from a single memristor. The simplest case of coupling between two switching memristors is shown to have a diverse range of properties when memristors are acting in composite with each other. The results presented only consider bi-state memristors, and as such, we can expect different types of memristors with different charge-flux relationships to expand the types of dynamic behaviors exhibited, with the ability to modify the states attainable by tuning the variables associated with the coupling coefficient (such as physical proximity and device material just to name a couple of examples).

In summary, two serially connected memristors with identical polarities are shown to produce a pair of variable memristors determinable from initial conditions; two serially connected memristors with opposite polarities display behavior often displayed by memristors connected to DC sources, or otherwise resistive behavior. Parallel memristive systems are shown to produce a variation rate in terms of the coupling coefficients. This is a feature that can be determined at the time of fabrication.

Further, what has been considered in this paper is the simplest case of identical memristors with identical initial conditions. The potential application of coupled memristors, in addition to the undoubtedly interesting characteristics of arrays of coupled memristors will serve to open up new avenues of applications, and also provide for guidelines on avoiding undesirable behaviors by having fabrication plants devise methods to reduce the coupling coefficient as low as practicable where design specifications see it fit. In particular, where neural networks will see densely populated circuits which depend on memristors behaving functionally, the effects of coupling must either be mitigated to avoid unexpected and fallible outcomes. The alternative view is that memristive coupling makes it possible to have more than two states between a pair of memristors which would otherwise only be capable of being switched either on or off, and as such, if these intermediary states are quantized, then a large system of many varying states can be produced out of a mere two memristors connected compositely.

## Acknowledgements

This work was supported by the Australia-Korea Foundation—Department of Foreign Affairs and Trade under the AKF00640 grant.

[9] Mladenov V and Kirilov S. Analysis of the mutual inductive and capacitive connections and tolerances of memristors parameters of a memristor memory matrix. In: 2013 European Conference on Circuit Theory and Design (ECCTD); 8-12 Sept. 2013; 2013. pp. 1-4

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

http://dx.doi.org/10.5772/intechopen.69327

185

[10] Prezioso M, Merrikh-Bayat F, Hoskins BD, Adam GC, Likharev KK, Strukov DB. Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

[11] James AP, Fedorova I, Ibrayev T, Kudithipudi D. HTM spatial pooler with memristor crossbar circuits for sparse biometric recognition. IEEE Transactions on Biomedical Cir-

[12] Adam GC, Hoskins BD, Prezioso M, Merrikh-Bayat F, Charkrabarti B, Strukov DB. 3-D memristor crossbars for analog and neuromorphic computing applications. IEEE Trans-

[13] Truong SN, Pham KV, Yang W and Min KS. Sequential memristor crossbar for neuromorphic pattern recognition. IEEE Transactions on Nanotechnology. 2016;15(6):

[14] Yakopcic C, Alom MZ and Taha TM. Memristor crossbar deep network implementation based on a Convolutional neural network. In: 2016 International Joint Conference on Neural Networks (IJCNN); 24-29 July 2016; Vancouver, BC, Canada. IEEE; 2016. DOI:

[15] Cai W and Tetzlaff R. Beyond series and parallel: Coupling as a third relation in memristive systems. In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS);

[16] Yu DS, Iu HHC, Liang Y, Fernando T and Chua LO. Dynamic behavior of coupled memristor circuits. IEEE Transactions on Circuits and Systems I: Regular Papers. 2015;62

[17] Yu DS, Liang Y, Iu HHC, Chua LO. A universal mutator for transformations among memristor, memcapacitor and meminductor. IEEE Transactions on Circuits and Systems

[18] Eshraghian JK, Iu HHC, Fernando T, Yu DS, Li Z. Modelling and characterization of dynamic behavior of coupled memristor circuits. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS); 22-25 May 2016; 2016. pp. 690-693. DOI: 10.1109/

[19] Chua LO. Resistance switching memories are memristors. Applied Physics A. 2011;102

actions on Electron Devices. 2017;64(1):312-318. DOI: 10.1109/TED.2016.2630925

cuits and Systems. 2017;11(99):1-12. DOI: 10.1109/TBCAS.2016.2641983

Nature. 2015;521:61-64. DOI: 10.1038/nature14441

922-930. DOI: 10.1109/TNANO.2016.2611008

10.1109/IJCNN.2016.7727302

(6):1607-1616

ISCAS.2016.7527334

1-5 June 2014; 2014. pp. 1259-1262

II: Express Briefs. 2014;61(10):758-762

(4):765-783. DOI: 10.1007/s00339-011-6264-9

## Author details

Jason Kamran Jr Eshraghian<sup>1</sup> \*, Herbert H.C. Iu2 and Kamran Eshraghian<sup>3</sup>

\*Address all correspondence to: jeshraghian@gmail.com


## References


[9] Mladenov V and Kirilov S. Analysis of the mutual inductive and capacitive connections and tolerances of memristors parameters of a memristor memory matrix. In: 2013 European Conference on Circuit Theory and Design (ECCTD); 8-12 Sept. 2013; 2013. pp. 1-4

Acknowledgements

184 Memristor and Memristive Neural Networks

Author details

References

2896

Jason Kamran Jr Eshraghian<sup>1</sup>

1971;18(5):507-519

(10):104001-1040042

2013;60(10):2688-2700

and Trade under the AKF00640 grant.

\*Address all correspondence to: jeshraghian@gmail.com 1 Chungbuk National University, Cheongju, South Korea

2 University of Western Australia, Perth, Australia

3 iDataMap Corporation Pty Ltd, Adelaide, Australia

Nature. 2008;453:80-83. DOI: 10.1038/nature06932

Systems and Computers. 2010;19(2):407-424

2009; 2-5 Nov. 2009; 2009. pp. 485-490

This work was supported by the Australia-Korea Foundation—Department of Foreign Affairs

[1] Chua LO. Introduction to Nonlinear Network Theory. New York: McGraw-Hill; 1969

[2] Chua LO. Memristor: The missing circuit element. IEEE Transactions on Circuit Theory.

[3] Strukov DB, Snider GS, Stewart DR and Williams RS. The missing memristor found.

[4] Chua LO. If it's pinched it's a memristor. Semiconductor Science and Technology. 2014;29

[5] Sharifi MJ and Banadaki YM. General SPICE models for memristor and application to circuit simulation of memristor-based synapses and memory cells. Journal of Circuits,

[6] Ho Y, Huang GM and Li P. Nonvolatile memristor memory: Device characteristics and design implications. In: IEEE/ACM International Conference on Computer-Aided Design,

[7] Yu DS, Iu HHC, Fitch AL and Liang Y. A floating memristor emulator based relaxation oscillator. IEEE Transactions on Circuits and Systems I: Regular Papers. 2014;61(10):2888-

[8] Budhathoki RK, Sah MP, Adhikari SP, Kim H and Chua LO. Composite behavior of multiple memristor circuits. IEEE Transactions on Circuits and Systems I: Regular Papers.

\*, Herbert H.C. Iu2 and Kamran Eshraghian<sup>3</sup>


**Chapter 9**

Provisional chapter

**Mathematical Modeling of Memristors**

The memristor has quite a reputation as a missing circuit element. It is a powerful candidate for next-generation applications after being first implemented in HP's laboratories. At this point, mathematical models were needed for the analysis of the memristor, and a lot of studies were done on this subject. In this chapter, mathematical modeling and simulations of the memristor device have been emphasized. Firstly, linear drift and nonlinear drift models have been described on the basic HP model. The window functions used in the nonlinear drift model have been widely examined. Different from HP model, the Simmons tunnel barrier and the threshold adaptive memristor model (TEAM) have been also mentioned. As a result, the most widely used modeling techniques have been

DOI: 10.5772/intechopen.73921

Keywords: memristor modeling, HP model, linear drift model, nonlinear drift model, window functions, exponential model, Simmons tunnel barrier model, TEAM

In the circuit theory, it refers to the existence of three basic circuit elements that define connections between basic circuit parameters such as current (i), voltage (v), charge (q), and magnetic flux (φ). These are resistor, inductor, and capacitor. However, a circuit element that determines the relationship between the charge and the magnetic flux is not defined. The fourth fundamental circuit element representing this relation was firstly presented by Chua in mathematical terms in 1971 with the name of the memristor (memory + resistor) [1]. In 2008, a group of researcher from HP laboratories announced that they were physically producing memristor [2]. In Figure 1, the relationship between fundamental circuit elements and basic circuit

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

> © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Mathematical Modeling of Memristors

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.73921

Yasin Oğuz

Yasin Oğuz

Abstract

described in detail.

1. Introduction

parameters is shown.

#### **Mathematical Modeling of Memristors** Mathematical Modeling of Memristors

#### Yasin Oğuz Yasin Oğuz

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.73921

#### Abstract

The memristor has quite a reputation as a missing circuit element. It is a powerful candidate for next-generation applications after being first implemented in HP's laboratories. At this point, mathematical models were needed for the analysis of the memristor, and a lot of studies were done on this subject. In this chapter, mathematical modeling and simulations of the memristor device have been emphasized. Firstly, linear drift and nonlinear drift models have been described on the basic HP model. The window functions used in the nonlinear drift model have been widely examined. Different from HP model, the Simmons tunnel barrier and the threshold adaptive memristor model (TEAM) have been also mentioned. As a result, the most widely used modeling techniques have been described in detail.

DOI: 10.5772/intechopen.73921

Keywords: memristor modeling, HP model, linear drift model, nonlinear drift model, window functions, exponential model, Simmons tunnel barrier model, TEAM

## 1. Introduction

In the circuit theory, it refers to the existence of three basic circuit elements that define connections between basic circuit parameters such as current (i), voltage (v), charge (q), and magnetic flux (φ). These are resistor, inductor, and capacitor. However, a circuit element that determines the relationship between the charge and the magnetic flux is not defined. The fourth fundamental circuit element representing this relation was firstly presented by Chua in mathematical terms in 1971 with the name of the memristor (memory + resistor) [1]. In 2008, a group of researcher from HP laboratories announced that they were physically producing memristor [2]. In Figure 1, the relationship between fundamental circuit elements and basic circuit parameters is shown.

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Figure 1. Linkage between four fundamental circuit elements and basic circuit parameters such as current (i), voltage (v), charge (q), and magnetic flux (φ).

The relationship between current, voltage, charge, and flux for the memristor is given by:

$$\mathbf{v}(\mathbf{t}) = \mathbf{M}(\mathbf{q}(\mathbf{t})) \mathbf{i}(\mathbf{t}) \tag{1}$$

has a nonvolatile memory effect. On the other hand, memristor is not an element that stores

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 189

Memristor is similar to resistor with memory. It shows a nonlinear resistance characteristic that

Another distinguishing feature of the memristor is that the I-V change shows the pinched hysteresis loop characteristic. A memristor fed by a bipolar periodic signal always exhibits a pinched hysteresis I-V characteristic that passes through the origin. As the frequency of the excitation signal increases, the hysteresis lobe area decreases monotonically. When the frequency tends to infinity, the pinched hysteresis loop shrinks toward a single-valued function [6, 7].

The memristor, with being a passive circuit element, has a unique ability to remember the state of resistance that it possesses by maintaining the relationship between voltage and current time integrals. Due to these features, they are being nominated for many different applications

Different materials and techniques are used at the point of producing the memristor. The memristor structures produced from different materials can be given as example, such as titanium dioxide (TiO2) memristor [2], zinc oxide memristor [8, 9], silicon oxide memristor

Memristor-based applications require a suitable model for analysis and simulation of the system. When looking at the literature, the HP memristor model where the memristor mechanism based on the drift of oxygen vacancies is widely used. The memristor model developed by HP Lab is composed of Pt/TiO2/Pt structure as shown in Figure 2. Here, the TiO2 layer in which the one side doped with positive charged-rich oxygen vacancies (TiO2x) is placed between two platinum

The doped part of the TiO2 layer exhibits a low resistance behavior, while the undoped part exhibits a high resistance behavior. As a result of the appropriate excitation on this structure,

such as resistive memories, soft computing, neurocomputing, etc.

energy [3, 4].

the charge parameter is state variable [5].

[10], and GST (Ge2Sb2Te5) memristor [11].

Figure 2. Structure of memristor reported by HP Lab [2].

2. Modeling of memristor

2.1. HP memristor model

layers [2].

$$\mathbf{M(q)} = \mathbf{d}\boldsymbol{\varphi}(\mathbf{q})/\mathbf{dq} \tag{2}$$

$$\mathbf{i(t)} = \mathbf{W}(\boldsymbol{\varrho}(\mathbf{t})) \mathbf{v(t)} \tag{3}$$

$$\mathbf{W}(\mathbf{q}) = \mathbf{dq}(\mathbf{q}) / \mathbf{dq} \tag{4}$$

where M(q) has the unity of resistance and W(φ) has the unity of conductance [1].

Memristor has properties that are different from other fundamental circuit elements and can only be seen in a memristor such as nonvolatile memory effect, passivity, and pinched hysteresis loop.

When Eqs. (1) and (2) are opened, Eqs. (5) and (6) can be written as follows:

$$\mathbf{v}(\mathbf{t}) = \mathbf{M} \left( \int\_{-\infty}^{\mathbf{t}} \mathbf{i}(\mathbf{t}) d\mathbf{t} \right) \mathbf{i}(\mathbf{t}) \tag{5}$$

$$\mathbf{i}(\mathbf{t}) = \mathbf{W} \left( \int\_{-\infty}^{\mathbf{t}} \mathbf{v}(\mathbf{t}) d\mathbf{t} \right) \mathbf{v}(\mathbf{t}) \tag{6}$$

Eqs. (5) and (6) show that the memristance value is related to the history of the current passing through the memristor. That is, when the current passing through the memristor is cut off, it remains at the value of the memristance value. The memristance value starts to change from the last value when it provides the current again to memristor. In other words, the memristor has a nonvolatile memory effect. On the other hand, memristor is not an element that stores energy [3, 4].

Memristor is similar to resistor with memory. It shows a nonlinear resistance characteristic that the charge parameter is state variable [5].

Another distinguishing feature of the memristor is that the I-V change shows the pinched hysteresis loop characteristic. A memristor fed by a bipolar periodic signal always exhibits a pinched hysteresis I-V characteristic that passes through the origin. As the frequency of the excitation signal increases, the hysteresis lobe area decreases monotonically. When the frequency tends to infinity, the pinched hysteresis loop shrinks toward a single-valued function [6, 7].

The memristor, with being a passive circuit element, has a unique ability to remember the state of resistance that it possesses by maintaining the relationship between voltage and current time integrals. Due to these features, they are being nominated for many different applications such as resistive memories, soft computing, neurocomputing, etc.

Different materials and techniques are used at the point of producing the memristor. The memristor structures produced from different materials can be given as example, such as titanium dioxide (TiO2) memristor [2], zinc oxide memristor [8, 9], silicon oxide memristor [10], and GST (Ge2Sb2Te5) memristor [11].

## 2. Modeling of memristor

#### 2.1. HP memristor model

The relationship between current, voltage, charge, and flux for the memristor is given by:

charge (q), and magnetic flux (φ).

188 Memristor and Memristive Neural Networks

Figure 1. Linkage between four fundamental circuit elements and basic circuit parameters such as current (i), voltage (v),

M q� � <sup>¼</sup> <sup>d</sup><sup>φ</sup> <sup>q</sup>

Memristor has properties that are different from other fundamental circuit elements and can only be seen in a memristor such as nonvolatile memory effect, passivity, and pinched hysteresis loop.

ðt

0 @

i tð Þdt

v tð Þdt

1

1

�∞

ðt

0 @

�∞

Eqs. (5) and (6) show that the memristance value is related to the history of the current passing through the memristor. That is, when the current passing through the memristor is cut off, it remains at the value of the memristance value. The memristance value starts to change from the last value when it provides the current again to memristor. In other words, the memristor

where M(q) has the unity of resistance and W(φ) has the unity of conductance [1].

When Eqs. (1) and (2) are opened, Eqs. (5) and (6) can be written as follows:

v tðÞ¼ M

i tðÞ¼ W

v tðÞ¼ Mqtð Þ � � i tð Þ (1)

i tðÞ¼ Wð Þ φð Þt v tð Þ (3)

Wð Þ¼ φ dqð Þ φ =dφ (4)

� �=dq (2)

Ai tð Þ (5)

Av tð Þ (6)

Memristor-based applications require a suitable model for analysis and simulation of the system. When looking at the literature, the HP memristor model where the memristor mechanism based on the drift of oxygen vacancies is widely used. The memristor model developed by HP Lab is composed of Pt/TiO2/Pt structure as shown in Figure 2. Here, the TiO2 layer in which the one side doped with positive charged-rich oxygen vacancies (TiO2x) is placed between two platinum layers [2].

The doped part of the TiO2 layer exhibits a low resistance behavior, while the undoped part exhibits a high resistance behavior. As a result of the appropriate excitation on this structure,

Figure 2. Structure of memristor reported by HP Lab [2].

the ionic drift between the doped part and the undoped part results in a dynamic change in the width of the doped region. That is, the width of the doped region is taken as a state variable. As the width of the doped region approaches zero (w!0), the memristor goes to a high resistance state (HRS), and as the width of the doped region approaches D (w!D), the memristor goes to a low resistance state (LRS) as shown in Figure 3 [3].

Since the memristor's dimensions are very small (in few nm), it causes a change in the doped region even with a small stimulation applied. Thus the resistance of the memristor varies between HRS and LRS [3].

#### 2.2. Linear drift model

In the model known as the linear drift model, the relation between the current and the voltage of the memristor is defined by the following equation:

$$\mathbf{v}(\mathbf{t}) = \left[\mathbf{R}\_{\text{on}}\mathbf{x}(\mathbf{t}) + \mathbf{R}\_{\text{off}}(1 - \mathbf{x}(\mathbf{t}))\right] \mathbf{i}(\mathbf{t}) \tag{7}$$

$$\mathbf{x}(\mathbf{t}) = \frac{\mathbf{w}(\mathbf{t})}{\mathbf{D}} \qquad \qquad \in (0, 1) \tag{8}$$

x tðÞ¼ μ<sup>v</sup>

If Eq. (11) is put in its place in Eq. (9), the following memristance expression is achieved:

Ron

Mqtð Þ <sup>¼</sup> Roff <sup>1</sup> � <sup>μ</sup><sup>v</sup>

Through this model, the characteristics of the memristor can be observed by the simulations as shown in the ongoing part. The following values are used for the simulations performed in this

(ωt) where Vo = 1 V and f = 1 Hz (ω = 2πf), Ron = 100 Ω, and Roff = 160 kΩ. Figure 4 shows the change of the current and voltage of the memristor with time for the given parameter values. The pinched hysteresis loop in the I-V plane shown in Figure 5 is one of the fingerprint characteristics of the memristor. Figure 6 shows the relationship between state variable and memristance. This indicates that the memristance depends on the state variable x. This figure also shows that the state variable is limited between 0 and 1. In Figure 7, the change of memristance with applied

As shown in Figure 8, as the frequency increases, the I-V pinched hysteresis loops become narrower. As the frequency increases toward infinity, the I-V characteristic seems to be a linear resistance characteristic. Figure 9 shows the variation of the I-V characteristic for different

The linear drift model supposes that the state variable (x) of the memristor is proportional to the charge flowing through the memristor. This proportion is acceptable to the interface between the electrodes and the interface between the doped and undoped parts of the memristor. The position of the doped part changes with the applied input signal. Furthermore, the linear drift model assumes that the vacancies have the freedom to move along the all length of the memristor. These assumptions made in the HP model have been greatly simplified, neglecting some basic laws. The reported literature shows that the drift of vacancies is not linear in the region near the boundary interfaces. The reason is that even a small excitation signal can create a large electric field causing nonlinear drift of the vacancies near the boundary interfaces in the memristor. Another problematic situation related to the linear drift model is that the state variable (x) never reaches zero, indicating that oxygen vacancies are not

if the left side of the total expression is neglected because Ron <<Roff [2].

Mqtð Þ <sup>¼</sup> Ronμ<sup>v</sup>

This expression can be written as

s �<sup>1</sup> V�<sup>1</sup>

amplitude values of the excitation signal.

2.3. Nonlinear drift model and window functions

section. μ<sup>v</sup> = 10�<sup>14</sup> m2

voltage is seen.

Ron

<sup>D</sup><sup>2</sup> q tð Þþ Roff <sup>1</sup> � <sup>μ</sup><sup>v</sup>

Ron

<sup>D</sup><sup>2</sup> q tð Þ (11)

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 191

<sup>D</sup><sup>2</sup> q tð Þ (12)

<sup>D</sup><sup>2</sup> q tð Þ (13)

Ron

, D = 10 nm, initial value of w is 3 nm, input signal Vinput = Vo.sin

where Ron and Roff are the values of the resistance for w(t) = D and w(t) = 0, respectively [2, 8, 9]. From Eq. (7), the value of memristance can be expressed by

$$\mathbf{M(q(t))} = \frac{\mathbf{v(t)}}{\mathbf{i(t)}} = \mathbf{R\_{on}x(t)} + \mathbf{R\_{off}(1-x(t))}\tag{9}$$

As shown in Figure 3, the state of change of the memristor resistance is represented by x(t) value in Eq. (8). The speed of movement of the boundary between the doped layer and undoped layer is expressed as dx/dt with Eq. (10) [12, 13]:

$$\frac{d\mathbf{x}(\mathbf{t})}{d\mathbf{t}} = \mu\_{\mathbf{v}} \frac{\mathbf{R}\_{\text{on}}}{\mathbf{D}^2} \mathbf{i}(\mathbf{t}) \tag{10}$$

where μ<sup>v</sup> is the average drift mobility of the charges. If Eq. (10) is taken integral for time, the following expression is derived:

Figure 3. Representation of the HRS and LRS states of the memristor. (a) LRS and (b) HRS.

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 191

$$\mathbf{x}(\mathbf{t}) = \mu\_{\mathbf{v}} \frac{\mathbf{R}\_{\text{on}}}{\mathbf{D}^2} \mathbf{q}(\mathbf{t}) \tag{11}$$

If Eq. (11) is put in its place in Eq. (9), the following memristance expression is achieved:

$$\mathbf{M}(\mathbf{q}(\mathbf{t})) = \mathbf{R}\_{\rm on} \mu\_{\rm v} \frac{\mathbf{R}\_{\rm on}}{\mathbf{D}^2} \mathbf{q}(\mathbf{t}) + \mathbf{R}\_{\rm off} \left(1 - \mu\_{\rm v} \frac{\mathbf{R}\_{\rm on}}{\mathbf{D}^2} \mathbf{q}(\mathbf{t})\right) \tag{12}$$

This expression can be written as

the ionic drift between the doped part and the undoped part results in a dynamic change in the width of the doped region. That is, the width of the doped region is taken as a state variable. As the width of the doped region approaches zero (w!0), the memristor goes to a high resistance state (HRS), and as the width of the doped region approaches D (w!D), the

Since the memristor's dimensions are very small (in few nm), it causes a change in the doped region even with a small stimulation applied. Thus the resistance of the memristor varies

In the model known as the linear drift model, the relation between the current and the voltage

where Ron and Roff are the values of the resistance for w(t) = D and w(t) = 0, respectively [2, 8, 9].

As shown in Figure 3, the state of change of the memristor resistance is represented by x(t) value in Eq. (8). The speed of movement of the boundary between the doped layer and

where μ<sup>v</sup> is the average drift mobility of the charges. If Eq. (10) is taken integral for time, the

Ron

x tðÞ¼ w tð Þ

dx tð Þ dt <sup>¼</sup> <sup>μ</sup><sup>v</sup>

Figure 3. Representation of the HRS and LRS states of the memristor. (a) LRS and (b) HRS.

v tðÞ¼ ½ � Ronx tð Þþ Roffð Þ 1 � x tð Þ i tð Þ (7)

<sup>D</sup> <sup>∈</sup> ð Þ <sup>0</sup>; <sup>1</sup> (8)

i tð Þ <sup>¼</sup> Ronx tð Þþ Roffð Þ <sup>1</sup> � x tð Þ (9)

<sup>D</sup><sup>2</sup> i tð Þ (10)

memristor goes to a low resistance state (LRS) as shown in Figure 3 [3].

of the memristor is defined by the following equation:

From Eq. (7), the value of memristance can be expressed by

undoped layer is expressed as dx/dt with Eq. (10) [12, 13]:

following expression is derived:

Mqtð Þ <sup>¼</sup> v tð Þ

between HRS and LRS [3].

190 Memristor and Memristive Neural Networks

2.2. Linear drift model

$$\mathbf{M}(\mathbf{q}(\mathbf{t})) = \mathbf{R}\_{\text{off}} \left( 1 - \mu\_{\text{v}} \frac{\mathbf{R}\_{\text{on}}}{\mathbf{D}^2} \mathbf{q}(\mathbf{t}) \right) \tag{13}$$

if the left side of the total expression is neglected because Ron <<Roff [2].

Through this model, the characteristics of the memristor can be observed by the simulations as shown in the ongoing part. The following values are used for the simulations performed in this section. μ<sup>v</sup> = 10�<sup>14</sup> m2 s �<sup>1</sup> V�<sup>1</sup> , D = 10 nm, initial value of w is 3 nm, input signal Vinput = Vo.sin (ωt) where Vo = 1 V and f = 1 Hz (ω = 2πf), Ron = 100 Ω, and Roff = 160 kΩ. Figure 4 shows the change of the current and voltage of the memristor with time for the given parameter values. The pinched hysteresis loop in the I-V plane shown in Figure 5 is one of the fingerprint characteristics of the memristor. Figure 6 shows the relationship between state variable and memristance. This indicates that the memristance depends on the state variable x. This figure also shows that the state variable is limited between 0 and 1. In Figure 7, the change of memristance with applied voltage is seen.

As shown in Figure 8, as the frequency increases, the I-V pinched hysteresis loops become narrower. As the frequency increases toward infinity, the I-V characteristic seems to be a linear resistance characteristic. Figure 9 shows the variation of the I-V characteristic for different amplitude values of the excitation signal.

#### 2.3. Nonlinear drift model and window functions

The linear drift model supposes that the state variable (x) of the memristor is proportional to the charge flowing through the memristor. This proportion is acceptable to the interface between the electrodes and the interface between the doped and undoped parts of the memristor. The position of the doped part changes with the applied input signal. Furthermore, the linear drift model assumes that the vacancies have the freedom to move along the all length of the memristor. These assumptions made in the HP model have been greatly simplified, neglecting some basic laws. The reported literature shows that the drift of vacancies is not linear in the region near the boundary interfaces. The reason is that even a small excitation signal can create a large electric field causing nonlinear drift of the vacancies near the boundary interfaces in the memristor. Another problematic situation related to the linear drift model is that the state variable (x) never reaches zero, indicating that oxygen vacancies are not

Figure 4. Change of the current and voltage of the memristor with respect to time.

Figure 5. I-V pinched hysteresis loop of the memristor.

present in the memristor. Similarly, the doped region cannot cover the entire length of the memristor, because there will be no undoped part and the memristor will not work in this way [3, 14, 15].

In order to provide nonlinearity for the boundary problems mentioned above, functions called window function are introduced. This function is implemented by rearranging the expression

Figure 6. Change of the state variable and memristance of the memristor with respect to time.

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 193

Figure 7. Change of the memristance of the memristor with respect to voltage.

Eq. (10) as

Figure 6. Change of the state variable and memristance of the memristor with respect to time.

Figure 7. Change of the memristance of the memristor with respect to voltage.

present in the memristor. Similarly, the doped region cannot cover the entire length of the memristor, because there will be no undoped part and the memristor will not work in this way

Figure 4. Change of the current and voltage of the memristor with respect to time.

192 Memristor and Memristive Neural Networks

[3, 14, 15].

Figure 5. I-V pinched hysteresis loop of the memristor.

In order to provide nonlinearity for the boundary problems mentioned above, functions called window function are introduced. This function is implemented by rearranging the expression Eq. (10) as

• The function should take account of the boundary situation at the top and bottom elec-

• The function should provide nonlinear drift across the entire active area of the memristor.

• The function should be scalable in the interval of fmax(x) can be obtained such that

Many different window functions are proposed as a result of the studies carried out in order to

where p is the control parameter which changes the flatness of the f(x) curve around its

In Figure 10, the change of window function proposed by Joglekar for different p values is shown. The characteristic of this function is similar to the rectangular window function by increasing p value, and the nonlinear drift effect is reduced. The disadvantage of Joglekar's window function is the cling situation of the state variable at the boundaries, and it is difficult to change the window function due to the zero value at both boundaries. That is, the nonlinear drift problem is solved, but the boundary lock is not taken into account. When memristor arrives in Ron or Roff terminal condition, this state will be maintained forever due to zero value

Biolek has introduced a window function that provides a solution for model errors (the cling situation of the state variable at the boundaries) of Joglekar's window function. Biolek's window

Figure 11 shows the variation of the window function proposed by Biolek for different p values. The proposed window function by Biolek depends not only on the state variable but

1, i ≥ 0 0, i < 0

stp iðÞ¼

where p is positive integer and i is the memristor current [18].

f xð Þ¼ <sup>1</sup> � ð Þ 2x � <sup>1</sup> 2p (15)

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 195

f xð Þ¼ <sup>1</sup> � <sup>x</sup> � stpð Þ �<sup>i</sup> 2p (16)

(17)

• The function should ensure linkage between the linear and nonlinear drift models.

• The function should include the control parameter to set the model.

trodes of the memristor.

0 ≤ fmax(x) ≤ 1.

provide these criteria.

2.3.1. Joglekar's window function

Joglekar's window function can be given as

taken from the window function [13, 14].

2.3.2. Biolek's window function

function is expressed as follows:

maximum value at x = 0.5 and is a positive integer [17].

Figure 8. I-V pinched hysteresis loops of the memristor for Vo = 1 V and different frequency values.

Figure 9. I-V pinched hysteresis loops of the memristor for f = 1 Hz and different Vo values.

$$\frac{d\mathbf{x}(\mathbf{t})}{d\mathbf{t}} = \mu\_{\mathbf{v}} \frac{\mathbf{R}\_{\text{on}}}{\mathbf{D}^2} \mathbf{i}(\mathbf{t}) \,\mathbf{f}(\mathbf{x}(\mathbf{t})) \tag{14}$$

The function f(x) should have zero at the limits of the memristor (x = 0 and x = 1) and maximum value at the middle of the memristor (x = 0.5) [11]. An effective window function should satisfy the following conditions for modeling of nonlinearity [16]:


Many different window functions are proposed as a result of the studies carried out in order to provide these criteria.

#### 2.3.1. Joglekar's window function

Joglekar's window function can be given as

$$\mathbf{f}(\mathbf{x}) = \mathbf{1} - (2\mathbf{x} - \mathbf{1})^{2\mathbf{p}} \tag{15}$$

where p is the control parameter which changes the flatness of the f(x) curve around its maximum value at x = 0.5 and is a positive integer [17].

In Figure 10, the change of window function proposed by Joglekar for different p values is shown. The characteristic of this function is similar to the rectangular window function by increasing p value, and the nonlinear drift effect is reduced. The disadvantage of Joglekar's window function is the cling situation of the state variable at the boundaries, and it is difficult to change the window function due to the zero value at both boundaries. That is, the nonlinear drift problem is solved, but the boundary lock is not taken into account. When memristor arrives in Ron or Roff terminal condition, this state will be maintained forever due to zero value taken from the window function [13, 14].

#### 2.3.2. Biolek's window function

dx tð Þ dt <sup>¼</sup> <sup>μ</sup><sup>v</sup>

Figure 9. I-V pinched hysteresis loops of the memristor for f = 1 Hz and different Vo values.

Figure 8. I-V pinched hysteresis loops of the memristor for Vo = 1 V and different frequency values.

194 Memristor and Memristive Neural Networks

should satisfy the following conditions for modeling of nonlinearity [16]:

Ron

The function f(x) should have zero at the limits of the memristor (x = 0 and x = 1) and maximum value at the middle of the memristor (x = 0.5) [11]. An effective window function

<sup>D</sup><sup>2</sup> i tð Þfxt ð Þ ð Þ (14)

Biolek has introduced a window function that provides a solution for model errors (the cling situation of the state variable at the boundaries) of Joglekar's window function. Biolek's window function is expressed as follows:

$$\mathbf{f}(\mathbf{x}) = 1 - \left(\mathbf{x} - \text{stp}(-\mathbf{i})\right)^{2\mathbf{p}} \tag{16}$$

$$\text{stp}(\mathbf{i}) = \begin{cases} 1, & \mathbf{i} \ge \mathbf{0} \\ 0, & \mathbf{i} < \mathbf{0} \end{cases} \tag{17}$$

where p is positive integer and i is the memristor current [18].

Figure 11 shows the variation of the window function proposed by Biolek for different p values. The proposed window function by Biolek depends not only on the state variable but

Figure 10. Joglekar window function for different p values.

Figure 11. Biolek's window function for different p values.

also on the current flow through the memristor. Thus, the problem of boundary lock is resolved. However, this window function does not include the scalability factor, so the maximum value of the window function cannot be set to a lower or greater value [13].

2.3.3. Prodromakis' window function Prodromakis' window function is

Figure 12. Prodromakis' window function for j = 1 and different p values.

Figure 13. Prodromakis' window function for p = 10 and different j values.

f xð Þ¼ j 1 � ð Þ <sup>x</sup> � <sup>0</sup>:<sup>5</sup> <sup>2</sup> <sup>þ</sup> <sup>0</sup>:<sup>75</sup> h i � �<sup>p</sup>

(18)

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 197

Figure 12. Prodromakis' window function for j = 1 and different p values.

Figure 13. Prodromakis' window function for p = 10 and different j values.

#### 2.3.3. Prodromakis' window function

Prodromakis' window function is

also on the current flow through the memristor. Thus, the problem of boundary lock is resolved. However, this window function does not include the scalability factor, so the maxi-

mum value of the window function cannot be set to a lower or greater value [13].

Figure 10. Joglekar window function for different p values.

196 Memristor and Memristive Neural Networks

Figure 11. Biolek's window function for different p values.

$$\mathbf{f}(\mathbf{x}) = \mathbf{j}\left(\mathbf{1} - \left[\left(\mathbf{x} - \mathbf{0}.5\right)^2 + \mathbf{0}.75\right]^\mathbf{P}\right) \tag{18}$$

where p and j are a positive real number [16]. In Figure 12, the change of Prodromakis' window function for j = 1 and different p values is shown. Figure 13 shows the variation of the Prodromakis' window function for p = 10 and different j values.

Prodromakis proposes a solution for the scalability problem in the aforementioned by the presented window function. Prodromakis' window function provides a connection to the linear dopant drift model for sufficiently large values of p. However, the model built by Prodromakis still contains the problem of boundary lock [13].

#### 2.3.4. Zha's window function

This function has been introduced by Zha as a new window model so that boundary lock, scalability, and nonlinear effects can be met at the same time. Zha's window function is expressed as follows:

$$\mathbf{f}(\mathbf{x}) = \mathbf{j}\left(\mathbf{1} - \left[0.25\left(\mathbf{x} - \text{stp}(-\mathbf{i})\right)^2 + 0.75\right]^p\right) \tag{19}$$

functions according to state variable x for p = 10 and j = 1 values. In Figure 17, I-V characteristics have been plotted for the window functions in Figure 16. In Figure 18, the change of the memristance of the memristor with the applied voltage for the window functions of Figure 16

D = 10 nm, initial value of w is 3.145 nm, input signal Vinput = Vo.sin(ωt) where Vo = 1.2 V and

s <sup>1</sup> V<sup>1</sup> ,

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 199

has been presented. For simulations using these window functions, μ<sup>v</sup> = 10<sup>14</sup> m2

f = 1 Hz (ω = 2πf), Ron = 100 Ω, and Roff = 160 kΩ.

Figure 16. Different window functions for p = 10 and j = 1.

Figure 15. Zha's window function for p = 10 and different j values.

where stp(i) is given in Eq. (17) and p and j are positive real numbers [13]. Zha's window function for j = 1 and different p values in Figure 14 is shown. Figure 15 shows the Zha's window function for p = 10 and different j values.

#### 2.3.5. Comparison of window functions

In this section, the simulation results have been given over the nonlinear drift model of the window functions given in the previous sections. Figure 16 shows the change of window

Figure 14. Zha's window function for j = 1 and different p values.

Figure 15. Zha's window function for p = 10 and different j values.

where p and j are a positive real number [16]. In Figure 12, the change of Prodromakis' window function for j = 1 and different p values is shown. Figure 13 shows the variation of

Prodromakis proposes a solution for the scalability problem in the aforementioned by the presented window function. Prodromakis' window function provides a connection to the linear dopant drift model for sufficiently large values of p. However, the model built by Prodromakis

This function has been introduced by Zha as a new window model so that boundary lock, scalability, and nonlinear effects can be met at the same time. Zha's window function is

f xð Þ¼ j 1 � <sup>0</sup>:25 x � stpð Þ �<sup>i</sup> � �<sup>2</sup> <sup>þ</sup> <sup>0</sup>:<sup>75</sup>

where stp(i) is given in Eq. (17) and p and j are positive real numbers [13]. Zha's window function for j = 1 and different p values in Figure 14 is shown. Figure 15 shows the Zha's

In this section, the simulation results have been given over the nonlinear drift model of the window functions given in the previous sections. Figure 16 shows the change of window

h i � �<sup>p</sup>

(19)

the Prodromakis' window function for p = 10 and different j values.

still contains the problem of boundary lock [13].

window function for p = 10 and different j values.

Figure 14. Zha's window function for j = 1 and different p values.

2.3.5. Comparison of window functions

2.3.4. Zha's window function

198 Memristor and Memristive Neural Networks

expressed as follows:

Figure 16. Different window functions for p = 10 and j = 1.

functions according to state variable x for p = 10 and j = 1 values. In Figure 17, I-V characteristics have been plotted for the window functions in Figure 16. In Figure 18, the change of the memristance of the memristor with the applied voltage for the window functions of Figure 16 has been presented. For simulations using these window functions, μ<sup>v</sup> = 10<sup>14</sup> m2 s <sup>1</sup> V<sup>1</sup> , D = 10 nm, initial value of w is 3.145 nm, input signal Vinput = Vo.sin(ωt) where Vo = 1.2 V and f = 1 Hz (ω = 2πf), Ron = 100 Ω, and Roff = 160 kΩ.

been presented. In this model, the relation between the current of the memristor and the

where β, α, χ, and γ are experimental fitting parameters. How the state variable can influence the current is determined by the n parameter [12, 19]. According to Eq. (20), when the model is ON state, asymmetrical switching behavior is shown (sinh part). When the OFF state, the exponential part of the Eq. (20) has the dominant part of the current, which is similar to an

The models described so far were based on the HP model, which consisted of two regions, each of which was modeled as resistance. But Pickett presented another physical model of the memristor as an alternative to the HP model, consisting of a resistor and an electron tunnel

Figure 19 shows the memristor structure of the Simmons tunnel barrier model where w is the

w � aoff wc

w � aon wc

� �

� �

� j ji b

� �, <sup>i</sup> <sup>&</sup>gt; <sup>0</sup>

� j ji b

� �, <sup>i</sup> <sup>&</sup>lt; <sup>0</sup>

� w wc

(22)

� w wc

ioff � �exp �exp

ion � �exp �exp

<sup>β</sup>sinhð Þþ <sup>α</sup>v tð Þ <sup>χ</sup> expð Þ� <sup>γ</sup>v tð Þ <sup>1</sup> � � (20)

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 201

dt <sup>¼</sup> <sup>a</sup> � v tð Þmf xð Þ (21)

voltage is defined as follows:

ideal PN junction [12, 14].

2.5. Simmons tunnel barrier model

dw tð Þ dt ¼

tunneling barrier and Rs is the channel resistance.

8 >>><

>>>:

Figure 19. Memristor structure of Simmons tunnel barrier model.

w is the state variable of the model and can be written as

foffsinh <sup>i</sup>

fonsinh <sup>i</sup>

barrier in series [20].

<sup>i</sup> <sup>¼</sup> x tð Þ<sup>n</sup>

In this model, the differential equation of state variable is written as

dx tð Þ

where a and m are fitting parameters. f(x) can be any window function [14].

Figure 17. Change of I-V pinched hysteresis loops of the memristor for different window functions.

Figure 18. Change of the memristance of the memristor with respect to voltage for different window functions.

#### 2.4. Exponential model

Even in the models described so far, the nonlinearity of the large electric field in the memristor is still not taken into consideration. In [19], an exponential model that accounts the effect has been presented. In this model, the relation between the current of the memristor and the voltage is defined as follows:

$$\mathbf{i} = \mathbf{x}(\mathbf{t})^\mathbf{n} \| \mathbf{s} \| \mathbf{n}(\alpha \mathbf{v}(\mathbf{t})) + \chi \left( \exp(\gamma \mathbf{v}(\mathbf{t})) - 1 \right) \tag{20}$$

where β, α, χ, and γ are experimental fitting parameters. How the state variable can influence the current is determined by the n parameter [12, 19]. According to Eq. (20), when the model is ON state, asymmetrical switching behavior is shown (sinh part). When the OFF state, the exponential part of the Eq. (20) has the dominant part of the current, which is similar to an ideal PN junction [12, 14].

In this model, the differential equation of state variable is written as

$$\frac{d\mathbf{x}(\mathbf{t})}{d\mathbf{t}} = \mathbf{a} \cdot \mathbf{v}(\mathbf{t})^{\mathrm{m}} \mathbf{f}(\mathbf{x}) \tag{21}$$

where a and m are fitting parameters. f(x) can be any window function [14].

#### 2.5. Simmons tunnel barrier model

The models described so far were based on the HP model, which consisted of two regions, each of which was modeled as resistance. But Pickett presented another physical model of the memristor as an alternative to the HP model, consisting of a resistor and an electron tunnel barrier in series [20].

Figure 19 shows the memristor structure of the Simmons tunnel barrier model where w is the tunneling barrier and Rs is the channel resistance.

w is the state variable of the model and can be written as

$$\frac{\mathbf{dw}(\mathbf{t})}{\mathbf{dt}} = \begin{cases} \mathbf{f}\_{\text{off}} \sinh\left(\frac{\mathbf{i}}{\mathbf{i}\_{\text{off}}}\right) \exp\left[-\exp\left(\frac{\mathbf{w} - \mathbf{a}\_{\text{off}}}{\mathbf{w}\_{\text{c}}} - \frac{|\mathbf{i}|}{\mathbf{b}}\right) - \frac{\mathbf{w}}{\mathbf{w}\_{\text{c}}}\right], & \mathbf{i} > \mathbf{0} \\\\ \mathbf{f}\_{\text{on}} \sinh\left(\frac{\mathbf{i}}{\mathbf{i}\_{\text{on}}}\right) \exp\left[-\exp\left(\frac{\mathbf{w} - \mathbf{a}\_{\text{on}}}{\mathbf{w}\_{\text{c}}} - \frac{|\mathbf{i}|}{\mathbf{b}}\right) - \frac{\mathbf{w}}{\mathbf{w}\_{\text{c}}}\right], & \mathbf{i} < \mathbf{0} \end{cases} \tag{22}$$

Figure 19. Memristor structure of Simmons tunnel barrier model.

2.4. Exponential model

200 Memristor and Memristive Neural Networks

Even in the models described so far, the nonlinearity of the large electric field in the memristor is still not taken into consideration. In [19], an exponential model that accounts the effect has

Figure 18. Change of the memristance of the memristor with respect to voltage for different window functions.

Figure 17. Change of I-V pinched hysteresis loops of the memristor for different window functions.

where foff, fon, aoff, aon, ioff, ion, and b are fitting parameters [20]. The fon value has an amplitude order greater than foff. It is also effective in changing w in both parameters. The ion and ioff parameters effectively limit the current threshold. In this model, a window function is not required, because aoff and aon values force upper and lower bounds of x, respectively. Although this model is the most accurate model for a memristor, it is a nongeneric model that is defined for a particular type of memristor, which has a nonobvious relationship between current and voltage [14].

#### 2.6. ThrEshold Adaptive Memristor (TEAM) model

TEAM model is a memristor model with several assumptions for analysis simplification and computational efficiency. These assumptions are as follows:


Taking these assumptions into account, the derivation of the state variable is written as

$$\frac{\mathbf{dw}(\mathbf{t})}{\mathbf{dt}} = \begin{cases} \mathbf{k}\_{\text{off}} \cdot \left( \frac{\mathbf{i}(\mathbf{t})}{\mathbf{i}\_{\text{off}}} - \mathbf{1} \right)^{\alpha\_{\text{off}}} \cdot \mathbf{f}\_{\text{off}}(\mathbf{w}), & 0 < \mathbf{i}\_{\text{off}} < \mathbf{i} \\ 0 & \text{, } \mathbf{i}\_{\text{on}} < \mathbf{i} < \mathbf{i}\_{\text{off}} \\ \mathbf{k}\_{\text{on}} \cdot \left( \frac{\mathbf{i}(\mathbf{t})}{\mathbf{i}\_{\text{on}}} - \mathbf{1} \right)^{\alpha\_{\text{on}}} \cdot \mathbf{f}\_{\text{on}}(\mathbf{w}), & \mathbf{i} < \mathbf{i}\_{\text{on}} < \mathbf{0} \end{cases} \tag{23}$$

3. Conclusion

Author details

Yasin Oğuz

References

the HP memristor model has been given.

ing methods of the memristor have been emphasized.

Address all correspondence to: yasin.oguz@gumushane.edu.tr

18(5):507-519. DOI: 10.1109/TCT.1971.1083337

Letter. 2008;453:80-83. DOI: 10.1038/nature06932

Gümüşhane University, Gümüşhane, Turkey

This chapter describes the mathematical modeling and simulation of the memristor device. Firstly, brief information about the historical development of the memristor has been given. The emergence of the memristor idea and the formation of mathematical theory have been mentioned. Then, information about the realization of the memristor as a physical element and

Mathematical Modeling of Memristors http://dx.doi.org/10.5772/intechopen.73921 203

In the memristor applications, the memristor device must be mathematically modeled correctly for analysis and simulation studies. For this reason, mathematical modeling and model-

We mainly focus on five different models such as linear drift model, nonlinear drift model, exponential model, Simmons tunnel barrier model, and TEAM model. In addition, the different window functions proposed for the nonlinear drift model have been examined. We provided simulation results for some of the models reviewed. The effects on the I-V characteristics

[1] Chua LO. Memristor-the missing circuit element. IEEE Transaction Circuit Theory. 1971;

[2] Strukov DB, Snider GS, Stewart DR, Williams RS. The missing memristor found. Nature

[3] Dongale TD. Development of High Performance Memristor for Resistive Random Access Memory Application [Thesis]. Kolhapur Maharashtra, India: Shivaji University; 2015

[4] Georgiou PS. A Mathematical Framework for the Analysis and Modelling of Memristor

[5] Kavehei O. Memristive Devices and Circuits for Computing, Memory, and Neuromorphic

Nanodevices [Thesis]. London: Chemistry of Imperial College London; 2013

Applications [Thesis]. Australia: The University of Adelaide; 2011

of the window functions have been shown graphically with simulation results.

where koff (koff > 0,) kon (kon < 0),αoff, and αon are constants, ioff and ion are current thresholds, and w is the effective electric tunnel width. Dependency on state variable w by foff(w) and fon(w) functions is provided. These functions can be thought of as window functions to limit the state variable between won and woff. If we assume that the memristance changes linearly with w as in Eq. (7), the relationship between current and voltage can be written as

$$\mathbf{v}(\mathbf{t}) = \left[\mathbf{R}\_{\rm on} + \frac{\mathbf{R}\_{\rm off} - \mathbf{R}\_{\rm on}}{\mathbf{w}\_{\rm off} - \mathbf{w}\_{\rm on}}(\mathbf{w} - \mathbf{w}\_{\rm on})\right] \mathbf{i}(\mathbf{t}) \tag{24}$$

If we assume that the memristance changes exponentially with w, the relationship between current and voltage can be written as

$$\mathbf{v}(\mathbf{t}) = \mathcal{R}\_{\text{on}} \mathbf{e}^{\left(\frac{\lambda}{\mathbf{w}\_{\text{off}} - \mathbf{w}\_{\text{on}}} (\mathbf{w} - \mathbf{w}\_{\text{on}})\right)} \cdot \mathbf{i}(\mathbf{t}) \tag{25}$$

where λ is fitting parameter [21]:

$$\lambda = \ln \left( \frac{\mathbf{R}\_{\rm off}}{\mathbf{R}\_{\rm on}} \right) \tag{26}$$

## 3. Conclusion

where foff, fon, aoff, aon, ioff, ion, and b are fitting parameters [20]. The fon value has an amplitude order greater than foff. It is also effective in changing w in both parameters. The ion and ioff parameters effectively limit the current threshold. In this model, a window function is not required, because aoff and aon values force upper and lower bounds of x, respectively. Although this model is the most accurate model for a memristor, it is a nongeneric model that is defined for a particular type of memristor, which has a nonobvious relationship between

TEAM model is a memristor model with several assumptions for analysis simplification and

2. A polynomial relationship is established between the current of memristor and the internal

0 , ion < i < ioff

where koff (koff > 0,) kon (kon < 0),αoff, and αon are constants, ioff and ion are current thresholds, and w is the effective electric tunnel width. Dependency on state variable w by foff(w) and fon(w) functions is provided. These functions can be thought of as window functions to limit the state variable between won and woff. If we assume that the memristance changes linearly

> Roff � Ron woff � won

If we assume that the memristance changes exponentially with w, the relationship between

� �

v tðÞ¼ Rone <sup>λ</sup> woff�wonð Þ <sup>w</sup>�won

<sup>λ</sup> <sup>¼</sup> ln Roff Ron � �

� �

� foffð Þ w , 0 < ioff < i

(23)

(26)

i tð Þ (24)

� i tð Þ (25)

� fonð Þ w , i < ion < 0

ð Þ w � won

1. There is no change in the status variable for values below a certain threshold value.

Taking these assumptions into account, the derivation of the state variable is written as

ioff � 1 � �<sup>α</sup>off

ion � 1 � �<sup>α</sup>on

with w as in Eq. (7), the relationship between current and voltage can be written as

current and voltage [14].

202 Memristor and Memristive Neural Networks

2.6. ThrEshold Adaptive Memristor (TEAM) model

dw tð Þ dt ¼

current and voltage can be written as

where λ is fitting parameter [21]:

computational efficiency. These assumptions are as follows:

state drift derivative instead of the exponential dependence.

8 >>><

>>>:

v tðÞ¼ Ron þ

koff � i tð Þ

kon � i tð Þ

This chapter describes the mathematical modeling and simulation of the memristor device. Firstly, brief information about the historical development of the memristor has been given. The emergence of the memristor idea and the formation of mathematical theory have been mentioned. Then, information about the realization of the memristor as a physical element and the HP memristor model has been given.

In the memristor applications, the memristor device must be mathematically modeled correctly for analysis and simulation studies. For this reason, mathematical modeling and modeling methods of the memristor have been emphasized.

We mainly focus on five different models such as linear drift model, nonlinear drift model, exponential model, Simmons tunnel barrier model, and TEAM model. In addition, the different window functions proposed for the nonlinear drift model have been examined. We provided simulation results for some of the models reviewed. The effects on the I-V characteristics of the window functions have been shown graphically with simulation results.

## Author details

Yasin Oğuz

Address all correspondence to: yasin.oguz@gumushane.edu.tr

Gümüşhane University, Gümüşhane, Turkey

## References


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[19] Yang JJ, Pickett MD, Li X, Ohlberg DAA, Stewart DR, Williams RS. Memristive switching mechanism for metal/oxide/metal nanodevices. Nature Nanotechnology. 2008;3(7):429-433. DOI: 10.1038/nnano.2008.160

[6] Adhikari S, Sah M, Kim H, Chua L. Three fingerprints of memristor. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;60(11):3008-3021. DOI: 10.1109/TCSI.2013.

[7] Chua LO. Resistance switching memories are memristors. Applied Physics A. 2011;102:

[8] Gul F, Efeoglu H. ZnO and ZnO 1-x based thin film memristors: The effects of oxygen deficiency and thickness in resistive switching behavior. Ceramics International. 2017;

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[11] Wang Q, Sun HJ, Zhang JJ, Xu XH, And Miao XS. Electrode materials for Ge2Sb2Te5-based memristors. Journal of Electronic Materials. 2012;41(12):3417-3422. DOI: 10.1007/s11664-

[12] Elgabra H, Farhat IAH, Al Hosani AS, Homouz D, Mohammad B. Mathematical modeling of a memristor device. In: 2012 International Conference On Innovations in Information Technology (IIT); 18-20 mar 2012; Abu Dhabi, United Arab Emirates: IEEE; 2012. pp.

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**Section 3**

**Memristor Neuromorphic Applications**

**Memristor Neuromorphic Applications**

**Chapter 10**

**Provisional chapter**

**Introduction to Memristive HTM Circuits**

**Introduction to Memristive HTM Circuits**

DOI: 10.5772/intechopen.70123

Hierarchical temporal memory (HTM) is a cognitive learning algorithm intended to mimic the working principles of neocortex, part of the human brain said to be responsible for data classification, learning, and making predictions. Based on the combination of various concepts of neuroscience, it has already been shown that the software realization of HTM is effective on different recognition, detection, and prediction making tasks. However, its distinctive features, expressed in terms of hierarchy, modularity, and sparsity, suggest that hardware realization of HTM can be attractive in terms of providing faster processing speed as well as small memory requirements, on-chip area, and total power consumption. Despite there are few works done on hardware realization for HTM, there are promising results which illustrate effectiveness of incorporating an emerging memristor device technology to solve this open-research problem. Hence, this chapter reviews hardware designs for HTM with specific focus on memristive HTM circuits.

**Keywords:** hierarchical temporal memory, spatial pooler, temporal memory, memristor,

The ideas that created a basis for development of hierarchical temporal memory (HTM), a type of machine learning algorithm that emerged from the consideration of the Bayesian neural network (BNN) and spatial-temporal algorithm, was first introduced by Jeff Hawkins in 2004 in his book *On Intelligence* [1] written in collaboration with Sandra Blakeslee. One year later, in 2005, Hawkins launched Numenta company that worked on the implementation of HTM technology. The first version of the HTM algorithm implementation was developed in

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

Alex James, Timur Ibrayev, Olga Krestinskaya and

Alex James, Timur Ibrayev, Olga Krestinskaya

Additional information is available at the end of the chapter

non-volatile memory, memristive crossbars

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.70123

Irina Dolzhikova

**Abstract**

**1. Introduction**

and Irina Dolzhikova

**Provisional chapter**
