**3. Duty cycle division multiplexing (DCDM)**

Multiplexing process also can be realized using DCDM concept, and it has been proposed as an alternative technique to ETDM [3]. In order to implement DCDM concept, basic components can be used which are return-to-zero (RZ) convertor and electrical adder. Since, RZ convertor has the ability to adjust the duty cycle (DC) parameter, hence various DCs of binary signal can be obtained. In DCDM, each input tributary is applied to RZ convertor with the different predefined DC parameter. The outputs for all RZ convertors are combined by an electrical adder to generate the DCDM signal. This technique requires a synchronize bit and identical amplitude of non-return-to-zero (NRZ) format for all input tributary. **Figure 2** shows an example of DCDM signal generation for three tributaries. **Figure 2**a–c shows the 8 bits sequence (all possible combination) of input tributary 1, 2 and 3, respectively. **Figure 2d**–**f** shows the RZ format with 25% DC of tributary 1, 50% DC of tributary 2 and 75% DC of tributary 2, respectively, after NRZ to RZ conversion. Combination of signals in **Figure 2d**–**f** using electrical adder generates DCDM signal as shown in **Figure 2g**. Based on this multiplexing,

**Figure 2.** An example of DCDM signal.

a unique signal waveform or symbol can be obtained. There is a transition at the beginning of the DCDM symbol because RZ conversion turns the signal from high to low for bit 1 s.

## **4. Multi-slot amplitude coding (MSAC)**

MSAC technique is a latest multiplexing concept to enhance the utilization of signal level for generating waveform or symbol compared to DCDM and ETDM [4]. In this technique, the multiplexer converts all possible combination bits of each tributary as MSAC symbol based on predefine translation rule. MSAC symbols can be obtained based on two parameters, which are the number of slots, *S* and number of signal levels, *M* as depicted in **Figure 3**. Assuming an equal duration of slot, the slot duration of MSAC symbol, *Td* is given by

**Figure 3.** General format of symbol for MSAC.

$$Td = \frac{T\_s}{S} \tag{3}$$

where *T*<sup>S</sup> is the symbol duration. *T*<sup>S</sup> is similar to the bit duration of the input tributary, *T*<sup>b</sup> . Therefore,

$$T\_{\rm S} = T\_{\rm b} = \frac{1}{R} \tag{4}$$

where *R* is the input tributary bit rate.

For equal signal level spacing, the maximum amplitude of MSAC, *A* is

$$A = (M-1)\Delta\tag{5}$$

where ∆ is amplitude spacing. **Figure 4** displays an example of MSAC symbol for three users. There are nine symbols (*x*<sup>1</sup> (*t*) to *x*<sup>9</sup> (*t*)) for *S* = 3 and *M* = 3. Note that MSAC symbol allocates the first slot in symbol format as zero level.

**Figure 4.** Example of symbol waveform for *M* = 3 and *S* = 3.

**Figure 3.** General format of symbol for MSAC.

a unique signal waveform or symbol can be obtained. There is a transition at the beginning of the DCDM symbol because RZ conversion turns the signal from high to low for bit 1 s.

MSAC technique is a latest multiplexing concept to enhance the utilization of signal level for generating waveform or symbol compared to DCDM and ETDM [4]. In this technique, the multiplexer converts all possible combination bits of each tributary as MSAC symbol based on predefine translation rule. MSAC symbols can be obtained based on two parameters, which are the number of slots, *S* and number of signal levels, *M* as depicted in **Figure 3**. Assuming

an equal duration of slot, the slot duration of MSAC symbol, *Td* is given by

**4. Multi-slot amplitude coding (MSAC)**

70 Optical Fiber and Wireless Communications

## **5. Optical communication system simulation using MSAC**

**Figure 5** shows the simulation setup for *N* tributaries MSAC in optical communication system. This setup consists of transmitter section, transmission section and receiver section. The component for the transmitter section is *N* pulse pattern generators, MSAC multiplexer, external modulator and continuous wave laser. The number of pulse pattern generator will depend on number of tributary. Each tributary consists of a pulse pattern generator for generating pseudo random binary signal (PRBS). Note that *Tr*1, *Tr*2 and *TrN* represent tributary 1, tributary 2 and tributary *N*, respectively. Each pulse pattern generator has a common clock signal in order to obtain synchronize binary data stream as input signal to the MSAC multiplexer. MSAC multiplexer model implements a conversion process based on the rule. The signal from MSAC multiplexer then modulates the light from a continuous wave laser (CW LD) at 1550 nm, using an external modulator. The optical power of CW LD is fixed at 0 dBm. The external modulator is based on an amplitude modulator (AM) model. Transmission section consists of an optical attenuator and optical fibre. The modulated optical signal is fed into an optical attenuator. In optical attenuator, the signal input electrical field for both polarizations is attenuated. This optical attenuator is used to control the amount of launch optical power from the AM. For this simulation, optical fibre is based on a single mode fibre model, and it is placed after the optical attenuator. The propagation of modulated optical signal in single mode fibre model is based on the Schrödinger equation [5]. The receiver section consists of an optical amplifier, PIN photodiode, electrical low-pass filter and clock and data recovery. An optical amplifier that acts as a pre-amplifier is placed before PIN photodiode in order to boost the signal. Note that the optical amplifier also introduces ASE noise. The received optical signal is then converted to an electrical signal using a PIN photodiode. In this simulation, the signal is corrupted with typical noises in optical system such as shot noise and thermal noise. The PIN photodiode output signal is filtered with a Gaussian low-pass filter (LPF). In order to

**Figure 5.** MSAC system setup.

optimize the system performance, the cut-off frequency of filter is set at 0.75 *BW*, where BW is the first null bandwidth of baseband MSAC signal. The filtered electrical signal is fed into the clock and data recovery module to regenerate each tributary data stream. In clock and data recovery module, data recovery process is implemented using MATLAB programming based on the recovery rules of MSAC demultiplexer.
