**Carrier Mobility in Field-Effect Transistors**

Philippe Gaubert and Akinobu Teramoto

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/67885

#### Abstract

Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the <100> and <110> directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer.

Keywords: mobility, electron, hole, silicon, temperature, crystallographic orientation, channel direction, scattering mechanism, modeling, accumulation, extraction, (100), (110)

### 1. Introduction

The concept of employing an electric field to modulate the conductivity of a channel has been proposed first by Lilienfeld during the 1930s [1], long before its practical fabrication by Shockley et al. in 1947 [2]. Since, the field-effect transistor has taken several directions and is at the root of various devices such as the metal-oxide-semiconductor FET (MOSFET) [3], dual gate MOSFET [4], junction FET [5], high electron mobility transistor [6], four-gate transistor [7] and so on. Nevertheless, the most important parameter for all these devices is the mobility of

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the carrier flowing inside the channel. Their mobility, also known as their ability to move through the crystal, will define the electrical performances of the device. The mobility is consequently a paramount parameter, and its good knowledge is of prime importance to first understand the physics underlying the conduction mechanisms inside semiconductor devices and second to be able to model and simulate a single transistor and in turn more complex circuits. The mobility in field-effect transistors hinges on various physical and environmental parameters that we propose to investigate for MOSFETs fabricated on (100) and (110) siliconoriented wafers.

In Section 2, the method to measure the mobility is briefly reviewed for different structures, while Section 3 investigates several methods to extract the conduction parameters such as the low field mobility in Si(100) and Si(110) p-MOSFETs. Thus, its modeling is presented in Section 4 for the same devices. Results regarding the impact of the channel direction and wafer orientation on the mobility are investigated in Section 5 while the impact of the temperature is reported in Section 6 for Si(110) n-MOSFETs. Recently, devices based on the majority carriers rather than the minority ones to generate the current showed promising results. A methodology to extract their mobility is presented in Section 7 and is applied to accumulation-mode Si (100) p-MOSFETs. Finally, Section 8 concludes the chapter.

#### 2. Experimental measurement of the mobility

The knowledge of the experimental mobility of carriers that are flowing inside the channel of a FET is essential for the development of semiconductor devices and in turn electronic circuits. The direct measurement of the effective mobility μeff is not possible, but its calculation is enabled through the measurement of the drain current Id—gate voltage Vg characteristic and of the gatechannel capacitance C as a function of the gate voltage. Both characteristics can be measured at Vd = 100 mV on a large gate transistor with at least a gate length L and gate width W above 50 μm in order to allow an accurate measurement of the capacitance. The substrate, source and drain electrodes are grounded, and the measurement of the capacitance is carried out on the gate electrode side at relatively low frequencies f between 1 and 100 kHz to neglect the serie resistances. Thus, the inversion charge Qinv per unit area is calculated from the C – Vg characteristic

$$\mathbf{Q}\_{\rm inv}(\mathbf{V}\_{\rm g}) = \int\_{-\infty}^{\mathbf{V}\_{\rm g}} \mathbf{C}(\mathbf{V}\mathbf{g}) \mathbf{dV}\_{\rm g}.\tag{1}$$

The effective mobility μeff is finally calculated from

$$
\mu\_{\rm eff}(\mathbf{V}\_{\rm g}) = \frac{\mathbf{L}}{W} \frac{\mathbf{I}\_{\rm d}(\mathbf{V}\_{\rm g})}{\mathbf{V}\_{\rm d} \mathbf{Q}\_{\rm inv}(\mathbf{V}\_{\rm g})}.\tag{2}
$$

At this stage, the effective mobility can be plotted as a function of the carrier sheet density by dividing the inversion charge Qinv by the elementary charge q. It can also be plotted as a function of the transverse effective electric field Eeff that is calculated as follows:

Carrier Mobility in Field-Effect Transistors http://dx.doi.org/10.5772/67885 5

$$\mathbf{E}\_{\text{eff}}(\mathbf{V}\_{\text{g}}) = \frac{1}{\varepsilon\_{\text{Si}}\varepsilon\_{\text{0}}} [\mathbf{Q}\_{\text{dep}} + \eta \mathbf{Q}\_{\text{inv}}(\mathbf{V}\_{\text{g}})],\tag{3}$$

where Qdep is the depletion charge per unit area, εSi is the dielectric constant of the silicon, ε<sup>0</sup> is the permittivity of the vacuum, and η is a term referring to the averaging of the transverse electric field over the carrier distribution inside the conduction channel. In Eq. (3), the depletion charge Qdep is theoretically calculated from the doping concentration Nsub of the channel. It is expressed as follows:

$$\mathbf{Q\_{dep}} = \sqrt{\frac{4\varepsilon\_{\rm Si}\varepsilon\_{0}\phi\_{\rm B}\mathbf{N\_{sub}}}{\mathbf{q}}},\tag{4}$$

with

the carrier flowing inside the channel. Their mobility, also known as their ability to move through the crystal, will define the electrical performances of the device. The mobility is consequently a paramount parameter, and its good knowledge is of prime importance to first understand the physics underlying the conduction mechanisms inside semiconductor devices and second to be able to model and simulate a single transistor and in turn more complex circuits. The mobility in field-effect transistors hinges on various physical and environmental parameters that we propose to investigate for MOSFETs fabricated on (100) and (110) silicon-

In Section 2, the method to measure the mobility is briefly reviewed for different structures, while Section 3 investigates several methods to extract the conduction parameters such as the low field mobility in Si(100) and Si(110) p-MOSFETs. Thus, its modeling is presented in Section 4 for the same devices. Results regarding the impact of the channel direction and wafer orientation on the mobility are investigated in Section 5 while the impact of the temperature is reported in Section 6 for Si(110) n-MOSFETs. Recently, devices based on the majority carriers rather than the minority ones to generate the current showed promising results. A methodology to extract their mobility is presented in Section 7 and is applied to accumulation-mode Si

The knowledge of the experimental mobility of carriers that are flowing inside the channel of a FET is essential for the development of semiconductor devices and in turn electronic circuits. The direct measurement of the effective mobility μeff is not possible, but its calculation is enabled through the measurement of the drain current Id—gate voltage Vg characteristic and of the gatechannel capacitance C as a function of the gate voltage. Both characteristics can be measured at Vd = 100 mV on a large gate transistor with at least a gate length L and gate width W above 50 μm in order to allow an accurate measurement of the capacitance. The substrate, source and drain electrodes are grounded, and the measurement of the capacitance is carried out on the gate electrode side at relatively low frequencies f between 1 and 100 kHz to neglect the serie resistances. Thus, the inversion charge Qinv per unit area is calculated from the C – Vg characteristic

> ð Vg

CðVgÞdVg: ð1Þ

: ð2Þ

�∞

W

At this stage, the effective mobility can be plotted as a function of the carrier sheet density by dividing the inversion charge Qinv by the elementary charge q. It can also be plotted as a

IdðVgÞ VdQinvðVgÞ

QinvðVgÞ ¼

<sup>μ</sup>effðVgÞ ¼ <sup>L</sup>

function of the transverse effective electric field Eeff that is calculated as follows:

(100) p-MOSFETs. Finally, Section 8 concludes the chapter.

4 Different Types of Field-Effect Transistors - Theory and Applications

2. Experimental measurement of the mobility

The effective mobility μeff is finally calculated from

oriented wafers.

$$\phi\_{\rm B} = \frac{\mathbf{k}\_{\rm B} \mathbf{T}}{\mathbf{q}} \ln \left( \frac{\mathbf{N}\_{\rm sub}}{\mathbf{n}\_{\rm i}} \right), \tag{5}$$

being the bulk Fermi energy. In Eq. (5), kB is the Boltzmann constant, T is the temperature in Kelvin, and ni is the intrinsic carrier concentration. Takagi et al. [8] confirmed experimentally that in Eq. (3), η is equal to 1/3 for hole and to 1/2 for electron on Si(100) wafers [9]. Regarding Si (110) wafers, η is generally taken equal to 1/3 for both hole [3, 10] and electron [11].

Contrary to bulk transistors for which the methodology has been described previously, the substrate of transistors fabricated on silicon-on-insulator (SOI) wafers sometimes cannot be accessed and then cannot be grounded. The back-gate cannot be biased and can be floating as long as the applied gate voltage is large enough to neglect the impact of the back-gate [12]. The expression of the depletion charge Qdep given by Eq. (4) must be rearranged in Eq. (3) since the buried oxide is preventing the expansion of the depletion. If the depletion is expending deeper than the buried oxide, Qdep is given by qNsubtSOI where tSOI is the thickness of the SOI layer.

In the case of devices involving the majority carriers rather than the minority ones such as accumulation-mode transistors that will be studied in Section 7, the entire SOI layer is neutral when the accumulation layer is formed. The depletion charge Qdep in Eq. (3) must be removed, and the calculation is involving the sole accumulation charge Qacc [13, 14]. Eqs. (3) and (4) are rewritten as follows:

$$
\mu\_{\rm eff}(\mathbf{V\_g}) = \frac{\mathbf{L}}{\mathbf{W}} \frac{\mathbf{I\_d}(\mathbf{V\_g})}{\mathbf{V\_d} \mathbf{Q\_{acc}}(\mathbf{V\_g})} \tag{6}
$$

and

$$\mathbf{E}\_{\text{eff}}(\mathbf{V}\_{\text{g}}) = \frac{\eta \mathbf{Q}\_{\text{acc}}(\mathbf{V}\_{\text{g}})}{\varepsilon\_{\text{Si}} \varepsilon\_{\text{0}}}.\tag{7}$$

### 3. Mobility extraction methods

The knowledge of the conduction parameters is useful to model the drivability of a MOSFET and in turn simulate complex circuits. All extraction methods rely on the knowledge of the Id – Vg drain current-gate voltage characteristic measured for various gate lengths L and gate widths W.

The calculation procedures are based on the expression of the drain current in the linear region for a gate overdrive voltage Vg�Vth (Vth being the threshold voltage) greater than the drain voltage Vd (Vg�Vth>>Vd). In this range, the drain current Id is expressed as follows:

$$\mathbf{I}\_{\rm d} = \mu\_{\rm eff} \mathbf{C}\_{\rm ox} \frac{\mathbf{W} - \Delta \mathbf{W}}{\mathbf{L} - \Delta \mathbf{L}} (\mathbf{V}\_{\rm g} - \mathbf{V}\_{\rm th})(\mathbf{V}\_{\rm d} - \mathbf{I}\_{\rm d} \mathbf{R}\_{\rm acc}).\tag{8}$$

where Racc is the parasitic access resistances located at the source and drain contacts and Cox is the oxide capacitance. ΔW and ΔL are, respectively, the width and length gate channel reduction. In Eq. (8), the effective mobility μeff is generally replaced by the well known [15]:

$$
\mu\_{\rm eff} = \frac{\mu\_0}{1 + \Theta(\mathbf{V\_g} - \mathbf{V\_{th}})} \,\mathrm{}\tag{9}
$$

where μ<sup>0</sup> is the low field mobility and θ is the mobility attenuation factor.

Depending on the extraction method, it is possible to obtain the low field mobility μ0, the mobility attenuation factor θ, the parasitic access resistance Racc in series with the intrinsic resistance of the channel of the transistor, the channel width reduction ΔW and the channel length reduction ΔL.

#### 3.1. Silicon wafers with a (100) crystallographic orientation

Four different extraction methods have been used to extract the conduction parameters in p-MOSFETs fabricated on (100) silicon-oriented wafers. These methods are the Schreutelkamp method [16, 17], the interpolation method explained in Tsividis book [18], the Ghibaudo method [19] and finally the Ciofi method [20].

The Schreutelkamp method is based on Eqs. (8) and (9) and requires the calculation of intermediate parameters around a given gate overdrive voltage Vg�Vth that has been measured on several transistors featuring various gate length L for a given gate width W. A representation of this method is shown in Figure 1 for Vg�Vth = 1 V. Id �<sup>1</sup> is plotted as a function of the gate length L, and the intersection with the vertical and horizontal axis is collected as shown in the inset of Figure 1. The low field mobility μ<sup>0</sup> is extracted from the slope of the linear plot (1/Id)int/Lint versus (Vg – Vth) �1 , while the mobility attenuation factor θ is obtained from the intersection with the vertical axis. On the other hand, the intersection of the plot Lint versus Lint/(1/Id)int with the vertical axis gives the channel length reduction ΔL, and the intersection with the horizontal axis gives the parasitic access resistance Racc. The extracted data according to the Schreutelkamp method on Si(100) p-MOSFETs are reported in Table 1. Note that the Schreutelkamp method does not allow the obtaining of the gate width reduction ΔW. The

3. Mobility extraction methods

6 Different Types of Field-Effect Transistors - Theory and Applications

widths W.

length reduction ΔL.

The knowledge of the conduction parameters is useful to model the drivability of a MOSFET and in turn simulate complex circuits. All extraction methods rely on the knowledge of the Id – Vg drain current-gate voltage characteristic measured for various gate lengths L and gate

The calculation procedures are based on the expression of the drain current in the linear region for a gate overdrive voltage Vg�Vth (Vth being the threshold voltage) greater than the drain

where Racc is the parasitic access resistances located at the source and drain contacts and Cox is the oxide capacitance. ΔW and ΔL are, respectively, the width and length gate channel reduc-

1 þ θðVg � VthÞ

Depending on the extraction method, it is possible to obtain the low field mobility μ0, the mobility attenuation factor θ, the parasitic access resistance Racc in series with the intrinsic resistance of the channel of the transistor, the channel width reduction ΔW and the channel

Four different extraction methods have been used to extract the conduction parameters in p-MOSFETs fabricated on (100) silicon-oriented wafers. These methods are the Schreutelkamp method [16, 17], the interpolation method explained in Tsividis book [18], the Ghibaudo

The Schreutelkamp method is based on Eqs. (8) and (9) and requires the calculation of intermediate parameters around a given gate overdrive voltage Vg�Vth that has been measured on several transistors featuring various gate length L for a given gate width W. A representation

length L, and the intersection with the vertical and horizontal axis is collected as shown in the inset of Figure 1. The low field mobility μ<sup>0</sup> is extracted from the slope of the linear plot

intersection with the vertical axis. On the other hand, the intersection of the plot Lint versus Lint/(1/Id)int with the vertical axis gives the channel length reduction ΔL, and the intersection with the horizontal axis gives the parasitic access resistance Racc. The extracted data according to the Schreutelkamp method on Si(100) p-MOSFETs are reported in Table 1. Note that the Schreutelkamp method does not allow the obtaining of the gate width reduction ΔW. The

<sup>L</sup> � <sup>Δ</sup><sup>L</sup> <sup>ð</sup>Vg � VthÞðVd � IdRaccÞ: <sup>ð</sup>8<sup>Þ</sup>

, ð9Þ

�<sup>1</sup> is plotted as a function of the gate

, while the mobility attenuation factor θ is obtained from the

voltage Vd (Vg�Vth>>Vd). In this range, the drain current Id is expressed as follows:

W � ΔW

tion. In Eq. (8), the effective mobility μeff is generally replaced by the well known [15]:

<sup>μ</sup>eff <sup>¼</sup> <sup>μ</sup><sup>0</sup>

where μ<sup>0</sup> is the low field mobility and θ is the mobility attenuation factor.

Id ¼ μeffCox

3.1. Silicon wafers with a (100) crystallographic orientation

of this method is shown in Figure 1 for Vg�Vth = 1 V. Id

�1

method [19] and finally the Ciofi method [20].

(1/Id)int/Lint versus (Vg – Vth)

Figure 1. Example of the procedure to obtain Lint and (1/Id)int for the centered Vg–Vth = 1 V in the frame of the Schreutlkamp method.


Table 1. Conduction parameters extracted using several methods for Si(100) p-MOSFETs at Vd = 50 mV [21].

impact of the centered gate overdrive voltage Vg – Vth on the conduction parameters has been conducted. The results on the low field mobility μ<sup>0</sup> and channel length reduction ΔL are shown in Figure 2. Both values are strongly decreasing when the gate overdrive voltage is increased until Vg – Vth = 0.8 V and are reaching a more stable behavior afterwards. For Vg – Vth < 0.8 V, the transistor is not working in the linear regime, and Eq. (8) is inaccurate, thus the fast drop. Additionally, the mobility model does not fit accurately the effective mobility, making the calculation even more inaccurate. For Vg – Vth > 0.8 V, the low field mobility μ<sup>0</sup> is slightly increasing, while the channel length reduction ΔL is slightly decreasing. The reason is that even if Eq. (8) can be applied, Eq. (9) does not perfectly model the effective mobility. For each centered Vg – Vth, the parameters that are modeling the mobility are slightly changing in order to accurately fit the effective mobility according to the centered Vg – Vth. In turns, the channel length reduction ΔL and the low field mobility μ<sup>0</sup> are not constant. An equivalent behavior has been also acknowledged when the mobility attenuation factor θ and the parasitic access resistance Racc have been plotted as a function of the centered gate overdrive voltage Vg – Vth.

Like the previous method, the one developed by Ghibaudo is also based on the same equations; however, the calculation requires the derivative of the Id – Vg curves for different gate

Figure 2. Evolution of the extracted low field mobility μ<sup>0</sup> and channel length reduction ΔL as a function of the centered gate overdrive voltage Vg–Vth in the frame of the Schreutlkamp method.

length L and gate width W, that is the transconductance gm. Data measured around the threshold voltage are used. The plots Id/gm 0.5 and gm �0.5 as a function of Vg – Vth allow the extraction of the intermediate parameters Gm and θ\* , respectively, since Id/gm 0.5 = (GmVd) 0.5(Vg – Vth) and gm �0.5=(GmVd) �0.5[1 + θ\* (Vg – Vth)]. Note that, the linear fittings are realized in the range Vg>Vth. The slope of the former fitting gives Gm, while the latter one allows the extraction of θ\* . Thus, the intersection of the plot Gm versus W with the horizontal axis gives the gate width reduction ΔW, and the intersection of the plot Gm �<sup>1</sup> versus L gives the gate length reduction ΔL. Finally, the mobility attenuation factor θ and the parasitic access resistances Racc are obtained from the plot θ\* versus Gm since θ\* =θ + GmRacc. θ\* is the extrinsic mobility attenuation factor. The extracted parameters for Si(100) p-MOSFETs using the Ghibaudo method are reported in Table 1.

While the Ghibaudo method is making use of the derivative, the extraction method developed by Ciofi is based on the numerical analysis of the discretization of the Id – Vg characteristics and requires here as well the calculation of two intermediate parameters, K and H. They are extracted from the plot Vd/Id versus Vg – Vth for several gate lengths L and gate widths W since Vd/Id=K�<sup>1</sup> ((Vg – Vth) �<sup>1</sup> + H). H and K are related together by H=θ + KRacc, and the plot H versus K allows the obtaining of the mobility attenuation factor θ and the parasitic access resistances Racc. Plotting K�<sup>1</sup> versus L and K versus W, respectively, gives the gate length reduction ΔL and the gate width reduction ΔW at the intersection with the horizontal axis. Data measured at relatively high gate overdrive voltage for Si(100) p-MOSFETs have been used, and the results of the Ciofi method are reported in Table 1. θ\* versus Gm for the Ghibaudo method and H versus K for the Ciofi method have been plotted on the same Figure 3. The results in Figure 3 are almost identical for both methods, so are the units. In fact, K and Gm are the transconductance parameter and equals to μ0CoxW/L. Moreover, the similarity between both methods is obvious since θ + KRacc=H=θ\* =θ + GmRacc. Note that, for both the Ghibaudo and the Ciofi methods, the knowledge of the threshold voltage Vth prior their implementation is not mandatory since the threshold voltage Vth can be extracted during the procedures described above.

Figure 3. Fitting of θ\* = fg(Gm) for the Ghibaudo method and H = fc(K) for the Ciofi method to obtain the access the parasitic access resistance Racc and the mobility attenuation factor θ [21].

Even if the method is quite limited since the low field mobility μ<sup>0</sup> and the mobility attenuation factor θ cannot be evaluated, the interpolation method proposed in the book by Tsividis has been still implemented for Si(100) p-MOSFETs and the results are reported in Table 1.

The four methods have been successfully employed to extract the conduction parameters although a disagreement is visible in regards to the parasitic access resistances Racc. The similarity between the Ciofi method and the Ghibaudo method leads to very similar data and in turn an undervaluation of the parasitic access resistances Racc when compared with the values obtained using the two other methods.

#### 3.2. Silicon wafers with a (110) crystallographic orientation

length L and gate width W, that is the transconductance gm. Data measured around the thresh-

Figure 2. Evolution of the extracted low field mobility μ<sup>0</sup> and channel length reduction ΔL as a function of the centered

intersection of the plot Gm versus W with the horizontal axis gives the gate width reduction ΔW,

mobility attenuation factor θ and the parasitic access resistances Racc are obtained from the plot

While the Ghibaudo method is making use of the derivative, the extraction method developed by Ciofi is based on the numerical analysis of the discretization of the Id – Vg characteristics and requires here as well the calculation of two intermediate parameters, K and H. They are extracted from the plot Vd/Id versus Vg – Vth for several gate lengths L and gate widths W since

versus K allows the obtaining of the mobility attenuation factor θ and the parasitic access resistances Racc. Plotting K�<sup>1</sup> versus L and K versus W, respectively, gives the gate length reduction ΔL and the gate width reduction ΔW at the intersection with the horizontal axis. Data measured at relatively high gate overdrive voltage for Si(100) p-MOSFETs have been used, and the results of the Ciofi method are reported in Table 1. θ\* versus Gm for the Ghibaudo method and H versus K for the Ciofi method have been plotted on the same Figure 3. The results in Figure 3 are almost identical for both methods, so are the units. In fact, K and Gm are the transconductance parameter and equals to μ0CoxW/L. Moreover, the simi-

the Ghibaudo and the Ciofi methods, the knowledge of the threshold voltage Vth prior their implementation is not mandatory since the threshold voltage Vth can be extracted during the

, respectively, since Id/gm

(Vg – Vth)]. Note that, the linear fittings are realized in the range Vg>Vth.

=θ + GmRacc. θ\* is the extrinsic mobility attenuation factor. The extracted

�<sup>1</sup> + H). H and K are related together by H=θ + KRacc, and the plot H

�0.5 as a function of Vg – Vth allow the extraction of

�<sup>1</sup> versus L gives the gate length reduction ΔL. Finally, the

0.5 = (GmVd)

=θ + GmRacc. Note that, for both

0.5(Vg – Vth) and

. Thus, the

0.5 and gm

The slope of the former fitting gives Gm, while the latter one allows the extraction of θ\*

parameters for Si(100) p-MOSFETs using the Ghibaudo method are reported in Table 1.

old voltage are used. The plots Id/gm

�0.5[1 + θ\*

and the intersection of the plot Gm

((Vg – Vth)

procedures described above.

larity between both methods is obvious since θ + KRacc=H=θ\*

gm

�0.5=(GmVd)

Vd/Id=K�<sup>1</sup>

θ\* versus Gm since θ\*

the intermediate parameters Gm and θ\*

gate overdrive voltage Vg–Vth in the frame of the Schreutlkamp method.

8 Different Types of Field-Effect Transistors - Theory and Applications

The extraction methods previously described have been implemented for p-MOSFETs fabricated on (110) silicon-oriented wafers in order to extract the conduction parameters. The results are reported in Table 2, and the extraction methods are consistent. Compared to Si (100) p-MOSFETs, the low field mobility μ<sup>0</sup> for Si(110) p-MOSFETs is almost three times higher, confirming the superiority of the hole mobility on (110) silicon surface [22].

At the same time, the mobility attenuation factor θ is 10 times weaker for Si(110) p-MOSFETs, indicating that the degradation of the effective mobility might be much more pronounced for Si


Table 2. Conduction parameters extracted using several methods for Si(110) p-MOSFETs at Vd = 100 mV [21].

Figure 4. Plot of gm �0.5 as a function of the gate overdrive voltage Vg–Vth for transistors fabricated on Si(100) and Si(110) wafers. The linear fitting of the curve allows the extraction of the intermediate parameter Gm in the frame of the Ghibaudo method. L = 10 μm, Vd = 50 mV for Si(100) and Vd = 100 mV for Si(110) transistors.

(100) p-MOSFETs. However, the main result is the impossibility to extract the parasitic access resistances Racc and the mobility attenuation factor θ with the Ghibaudo method, whereas the method has been successfully employed for Si(100) p-MOSFETs [23]. Indeed, as shown in Figure 4, whereas the extraction of Gm from Id/gm 0.5 has been possible, and in turn the extraction of the low field mobility μ0, the gate length reduction ΔL and the gate width reduction ΔW, the linear fitting of gm �0.5 versus the gate voltage could not be done. Concerning the Schreutelkamp method, the same procedure as previously described has been carried out and a behavior similar to the one noticed for Si(100) p-MOSFETs has been acknowledged.
