5. Relation between the mobility, the channel direction and the wafer orientation

Inversion-mode fully depleted p- and n-channel silicon-on insulator (SOI) MOSFETs have been fabricated on bonded SOI (100) and (110) crystallographic silicon-oriented wafers. For each wafer, transistors with different channel directions were manufactured. The process flow has been entirely conducted in the clean room of the Fluctuation Free Facility at Tohoku University. 33-mm-diameter wafers have been used after cutting them from 8 inches wafers. The doping concentration has been adjusted to 1016 cm�<sup>3</sup> by ion implantation. The thickness of the SOI layer was 50 nm, and the thickness of the buried oxide was 100 nm. Prior the formation of the 7.5-nm-thick gate oxide by radical oxidation [29] an alkali-free process [22, 30] able to keep the silicon surface flat was used. The roughness of the Si/SiO2 interface was further reduced by repeating several times the procedure radical oxidation–etching [31]. The procedure has been repeated two times for the Si(100) wafers and four times for the Si(110) ones and led to the same microroughness measured to 0.08 nm. The effective mobility has been measured according to the methodology presented in Section 2 at Vd = 50 mV. Measurements have been carried out on MOSFETs with a gate dimension of W = 100 μm and L = 100 μm.

#### 5.1. Silicon wafers with a (100) crystallographic orientation

The low field mobility μ0, the mobility attenuation factor θ, the gate length reduction ΔL, the gate width reduction ΔW and the parasitic access resistances Racc have been extracted for Si (100) n- and p-MOSFETs and are available in a previous paper by Gaubert et al. [32]. The Ghibaudo and Ciofi methods have been used. Figure 9 shows the effective mobility for hole and electron on Si(100) wafers. It is clear that n-MOSFETs own greater performances than p-MOSFETs since the mobility of the former ones is five times higher than the mobility of the latter ones. It is also clear that the channel direction has no impact on the mobility of the n-MOSFETs. However, a slight difference can be noticed for the hole, the highest mobility being measured for a channel along the <100> direction. The direction of choice for the

Figure 9. Electron and hole effective mobility μeff as a function of the effective electric field Eeff for Si(100) MOSFETs featuring a channel along the <110> (full lines) and <100> (dashed lines) directions.

electronic manufacturers is the <110> direction and an easy and costless way to slightly enhance performances of electronic devices would be to manufacture p-MOSFETs on Si(100) wafers with a channel following the <100> direction. The shift from the <110> direction for the <100> direction can give rise to a maximum enhancement of 10% of the drivability [12].

#### 5.2. Silicon wafers with a (110) crystallographic orientation

5. Relation between the mobility, the channel direction and the wafer

carried out on MOSFETs with a gate dimension of W = 100 μm and L = 100 μm.

The low field mobility μ0, the mobility attenuation factor θ, the gate length reduction ΔL, the gate width reduction ΔW and the parasitic access resistances Racc have been extracted for Si (100) n- and p-MOSFETs and are available in a previous paper by Gaubert et al. [32]. The Ghibaudo and Ciofi methods have been used. Figure 9 shows the effective mobility for hole and electron on Si(100) wafers. It is clear that n-MOSFETs own greater performances than p-MOSFETs since the mobility of the former ones is five times higher than the mobility of the latter ones. It is also clear that the channel direction has no impact on the mobility of the n-MOSFETs. However, a slight difference can be noticed for the hole, the highest mobility being measured for a channel along the <100> direction. The direction of choice for the

Figure 9. Electron and hole effective mobility μeff as a function of the effective electric field Eeff for Si(100) MOSFETs

featuring a channel along the <110> (full lines) and <100> (dashed lines) directions.

5.1. Silicon wafers with a (100) crystallographic orientation

14 Different Types of Field-Effect Transistors - Theory and Applications

Inversion-mode fully depleted p- and n-channel silicon-on insulator (SOI) MOSFETs have been fabricated on bonded SOI (100) and (110) crystallographic silicon-oriented wafers. For each wafer, transistors with different channel directions were manufactured. The process flow has been entirely conducted in the clean room of the Fluctuation Free Facility at Tohoku University. 33-mm-diameter wafers have been used after cutting them from 8 inches wafers. The doping concentration has been adjusted to 1016 cm�<sup>3</sup> by ion implantation. The thickness of the SOI layer was 50 nm, and the thickness of the buried oxide was 100 nm. Prior the formation of the 7.5-nm-thick gate oxide by radical oxidation [29] an alkali-free process [22, 30] able to keep the silicon surface flat was used. The roughness of the Si/SiO2 interface was further reduced by repeating several times the procedure radical oxidation–etching [31]. The procedure has been repeated two times for the Si(100) wafers and four times for the Si(110) ones and led to the same microroughness measured to 0.08 nm. The effective mobility has been measured according to the methodology presented in Section 2 at Vd = 50 mV. Measurements have been

orientation

It has been demonstrated in Section 3 that the extraction methods are difficult to set up for p-MOSFETs on Si(110) wafers. Nevertheless, the method proposed by Tsividis has been used for the Si(110) p-MOSFETs while the Ciofi and Ghibaudo method helped extract the conduction parameters for the Si(110) n-MOSFETs. The results are reported in a previous paper by Gaubert et al. [32]. The mobility in Si(110) p-MOSFETs is shown in Figure 10. The dependence with the channel is clearly visible. The highest mobility is obtained for a channel following the <110> direction, while the lowest one is obtained for a channel along the <100> direction. Furthermore, an increase in the mobility with the effective electric field can be noticed, especially for the <110> direction, where an increasing limitation by the phonon scatterings was expected. This behavior is caused by the inter-subband phonon scatterings as noticed in Section 4.2. The clear role played by the inter-subband phonon scatterings on limiting the mobility spans on a more visible way in Figure 10 than in Figure 5. The reason is the lower doping concentration of the devices studied in this section that consequently shifts the Coulomb scattering limited mobility to lower effective electric fields. The inter-subband phonon scatterings are explained by the small energetic separation between the two lowest heavy-holelike subbands, which is favoring the inter-subband transitions assisted by the absorption of optical phonon. This behavior reaches its maximum for a channel along the <110> direction since the holes in this direction have the lowest mass [12].

The Id – Vg curves for Si(110) n-MOSFETs have been measured, and the results are presented in Figure 11 along with the corresponding tranconductances gm. The larger drivability is ascribed to the <100> direction. From Ref. [32], the value of the attenuation factor θ for the Si(100)

Figure 10. Effective mobility μeff as a function of the effective electric field Eeff for Si(110) p-MOSFETs featuring a channel along several directions.

Figure 11. Drain current Id (right) and transconductance gm (left) as a function of the gate overdrive voltage Vg–Vth for Si (110) n-MOSFETs featuring a channel along the <110> (full lines) and <100> (dashed lines) directions.

n-MOSFETs is 0.175 V�<sup>1</sup> , while the one obtained for the Si(110) n-MOSFETs is 0.6 V�<sup>1</sup> . The larger value for Si(110) wafers reflects an unusual degradation of the mobility that makes the drain current Id saturate and drop at high gate overdrive voltage Vg – Vth, as shown in Figure 11. The saturation and decrease in the drain current Id are more pronounced for the <100> direction and find its origin in the balance of the linear product (current is proportional to nμ) between the increase in the number of carriers n and the decrease in the mobility μ. As shown in Figure 11, the unusual consequence is a negative transconductance gm at high voltage. The mobility is shown in Figure 12. Like for the Si(110) p-MOSFETs and contrary to the Si(100) n-MOSFETs, there is a dependence between the mobility and the channel direction. The highest mobility is obtained for the <100> direction, and the lowest is obtained for the <110> direction, the opposite trend revealed for Si(110) p-MOSFETs. The surface roughness is limiting in more proportion the mobility of the transistors along the <100> direction and explains the more pronounced drop of the drain current Id shown in Figure 11.

Figure 12. Effective mobility μeff as a function of the effective electric field Eeff for Si(110) n-MOSFETs featuring a channel along several directions.

#### 6. Relation between the mobility and the temperature

n-MOSFETs is 0.175 V�<sup>1</sup>

16 Different Types of Field-Effect Transistors - Theory and Applications

along several directions.

, while the one obtained for the Si(110) n-MOSFETs is 0.6 V�<sup>1</sup>

larger value for Si(110) wafers reflects an unusual degradation of the mobility that makes the drain current Id saturate and drop at high gate overdrive voltage Vg – Vth, as shown in Figure 11. The saturation and decrease in the drain current Id are more pronounced for the <100> direction and find its origin in the balance of the linear product (current is proportional to nμ) between the increase in the number of carriers n and the decrease in the mobility μ. As shown in Figure 11, the unusual consequence is a negative transconductance gm at high voltage. The mobility is shown in Figure 12. Like for the Si(110) p-MOSFETs and contrary to the Si(100) n-MOSFETs, there is a dependence between the mobility and the channel direction. The highest mobility is obtained for the <100> direction, and the lowest is obtained for the <110> direction, the opposite trend revealed for Si(110) p-MOSFETs. The surface roughness is limiting in more proportion the mobility of the transistors along the <100> direction and

Figure 12. Effective mobility μeff as a function of the effective electric field Eeff for Si(110) n-MOSFETs featuring a channel

Figure 11. Drain current Id (right) and transconductance gm (left) as a function of the gate overdrive voltage Vg–Vth for Si

(110) n-MOSFETs featuring a channel along the <110> (full lines) and <100> (dashed lines) directions.

explains the more pronounced drop of the drain current Id shown in Figure 11.

. The

It is well known that temperature has a major impact on the performances of MOSFETs. Every scattering mechanisms that are limiting the mobility have a specific response toward the change in temperature as Gaubert et al. demonstrated for Si(110) n-MOSFETs [33]. Contrary to p-MOSFETs fabricated on Si(110) wafers, the mobility of n-MOSFETs on this orientation is limited by the Coulomb scattering in the low range effective electric field, the phonon scattering in the middle range and finally the surface roughness scattering at high effective electric field. With the intention to understand the response of each scattering mechanisms taken individually to the temperature, a study has been conducted on Si(110) n-MOSFETs investigated in the precedent section. Transistors with a channel along the <100> direction have been studied for different temperatures from 213 to 473�K. Figure 13 reports the drain current Id and the associated transconductance gm for three different temperatures. Increasing the temperature degrades the drivability and the transconductance even though a slight improvement in the latter quantity can be acknowledged at high gate voltage. In addition, the peculiar behavior acknowledged in the previous section for Si(110) n-MOSFETs, that is a saturation followed by a drop of the drivability with an increase of the gate voltage, is amplified with a decrease of the temperature and leads to even more negative transconductance in the high bias range. This suggests that the drop of temperature increases the degradation ratio generated by the surface roughness scattering mechanisms. The mobility for different temperatures is shown in Figure 14. As expected, the mobility is enhanced when the temperature is reduced. The scattering mechanisms have been studied separately by the means of the modeling. The mobilities shown in Figure 14 have been modeled according the Matthiessen rule with the three main scattering mechanisms:

$$\frac{1}{\mu\_{\rm eff}} = \frac{1}{\mu\_{\rm Coul}} + \frac{1}{\mu\_{\rm Ph}} + \frac{1}{\mu\_{\rm SR}} = \frac{1}{\mathbf{A}\_{\rm Coul}\mathbf{E}\_{\rm eff}^{\beta}} + \frac{1}{\mathbf{A}\_{\rm Ph}\mathbf{E}\_{\rm eff}^{-0.3}} + \frac{1}{\mathbf{A}\_{\rm SR}\mathbf{E}\_{\rm eff}^{\gamma}}.\tag{11}$$

μCoul is the Coulomb-limited mobility, proportional to Eeff <sup>β</sup> where β is a fitting parameter [34]. μPh is the phonon-limited mobility, generally proportional to Eeff �0.3 [11]. Finally, μSR is the surface

Figure 13. Drain current Id (right) and transconductance gm (left) as a function of the gate voltage Vg for Si(110) n-MOSFETs measured at three different temperatures.

Figure 14. Effective mobility μeff as a function of the effective electric field Eeff for Si(110) n-MOSFETs measured at different temperatures. The several scattering mechanisms limiting the mobility have been also reported.

roughness-limited mobility. It is proportional to Eeff <sup>γ</sup> [35] where γ is a fitting parameter generally found between �1 and �3. Quantities ACoul, APh and ASR are fitting parameters associated, respectively, with the Coulomb, Phonon and Surface roughness scattering mechanisms.

The results for the Coulomb scattering mechanisms μCoul are shown in Figure 15. The Coulomb-limited mobility μCoul is temperature dependant, and β is varying between 0.8 and 1.2. A point independent of the temperature is visible for an effective electric field around 3 · 10<sup>3</sup> V/cm. It corresponds to the crossing point visible on the Id – Vg curves of Figure 13 for Vg around 100 mV. Below that, point the temperature increases the energy of electron that are scattering less since the Coulomb interaction is weakening. Finally, results shown in Figure 15 and those reported by Gaubert et al. [33] showing an attenuation of the variation of ACoul with a decrease in the temperature suggests that the Coulomb-limited mobility μCoul might become independent of the temperature at low temperature. The results regarding the phonon-limited mobility μPh are shown in Figure 16. The phonon-limited mobility μPh is temperature

Figure 15. Extracted Coulomb mobility μCoul as a function of the effective electric field Eeff for Si(110) n-MOSFETs measured at different temperatures.

Figure 16. Extracted phonon mobility μPh as a function of the effective electric field Eeff for Si(110) n-MOSFETs measured at different temperatures.

roughness-limited mobility. It is proportional to Eeff

18 Different Types of Field-Effect Transistors - Theory and Applications

measured at different temperatures.

found between �1 and �3. Quantities ACoul, APh and ASR are fitting parameters associated,

Figure 14. Effective mobility μeff as a function of the effective electric field Eeff for Si(110) n-MOSFETs measured at

The results for the Coulomb scattering mechanisms μCoul are shown in Figure 15. The Coulomb-limited mobility μCoul is temperature dependant, and β is varying between 0.8 and 1.2. A point independent of the temperature is visible for an effective electric field around 3 · 10<sup>3</sup> V/cm. It corresponds to the crossing point visible on the Id – Vg curves of Figure 13 for Vg around 100 mV. Below that, point the temperature increases the energy of electron that are scattering less since the Coulomb interaction is weakening. Finally, results shown in Figure 15 and those reported by Gaubert et al. [33] showing an attenuation of the variation of ACoul with a decrease in the temperature suggests that the Coulomb-limited mobility μCoul might become independent of the temperature at low temperature. The results regarding the phonon-limited mobility μPh are shown in Figure 16. The phonon-limited mobility μPh is temperature

Figure 15. Extracted Coulomb mobility μCoul as a function of the effective electric field Eeff for Si(110) n-MOSFETs

respectively, with the Coulomb, Phonon and Surface roughness scattering mechanisms.

different temperatures. The several scattering mechanisms limiting the mobility have been also reported.

<sup>γ</sup> [35] where γ is a fitting parameter generally

dependant according to a T1.3 law. Nevertheless, their ratio with the effective electric field remains unchanged with a change in temperature. The results regarding the surfaceroughness-limited mobility μSR are shown in Figure 17. The surface-roughness-limited mobility μSR is temperature dependant. However, like for the Coulomb-limited mobility μCoul, the results at low temperature strongly suggest that the surface-roughness-limited mobility μSR becomes independent when the temperature is lowered down. Gaubert et al. [33] showed that ASR is converging towards a constant value for temperature lower than 200K, with γ reaching a value of 2. The surface-roughness-limited mobility μSR features a crossing point for effective electric field around 2 MV/cm, roughly corresponding to the breakdown of the gate oxide. Above this point, the increase in temperature is reducing the collision with the interface. The study of this peculiar behavior is made extremely difficult owing the impossibility to carry measurements on.

Figure 17. Extracted surface roughness mobility μSR as a function of the effective electric field Eeff for Si(110) n-MOSFETs measured at different temperatures.

To finish, the shift from the Si(100) wafers to the Si(110) wafers degrades the electron mobility as testified by results shown in Figures 9 and 12. The study of the mobility in Si(100) n-MOSFETs has been conducted in a similar way for 303� K exclusively, and the calculation of each scattering mechanisms showed that this degradation is actually the result of a strong limitation arising from the Coulomb and surface roughness scattering rather than the phonon mechanisms, results that has been demonstrated by Gaubert et al. [33].

#### 7. Mobility in an accumulation layer

Even though making use of the majority carriers to generate the current [36, 37] is already known and has been investigated more than 40 years ago, this approach has recently gained interest, and recent studies have positioned the accumulation-mode MOSFETs as serious competitors [13, 14, 38–41] to take over the conventional transistors for future CMOS technologies. Scarce data have been published so far regarding the carrier mobility flowing inside an accumulation layer [14, 36], and a method to extract it from the conventional mobility measurement is proposed here since in accumulation-mode MOSFETs the conduction, and thus, the measured mobility involves the conduction inside the accumulation layer and the conduction occurring inside the SOI layer. Planar mode fully depleted silicon-on-insulator p-type MOSFETs on three different unibond p-type SOI (100) silicon oriented wafers have been fabricated in order to assess the mobility in an accumulation layer. The doping concentration of the SOI layer has been adjusted to 1015, 1016 and 2 · 1017 cm�<sup>3</sup> . A 7.5-nm-thick gate oxide has been formed by plasma oxidation after etching the SOI layer until reaching 50 nm. The mobility measurement method proposed in Section 2 has been followed with Qdep = 0. The results are shown in Figure 18. The mobility for the conventional inversion-mode p-MOSFETs has been reported for comparison and accurately follows the universal curve by Takagi et al. [8] at high effective electric field Eeff. While the results suggest that the mobility for the accumulation-mode devices possessing a doping concentration of 1015 and 1016 cm�<sup>3</sup> is following the universal curve, it is clear that the one with a doping concentration of 2 · 1017 cm�<sup>3</sup>

Figure 18. Experimental effective mobility μeff as a function of the effective electric field Eeff for accumulation- and inversion-mode Si(100) p-MOSFETs featuring different doping concentrations.

does not. As expressed previously, the SOI layer is contributing to the total measured current, and in turn, it is included in the calculation of the mobility as presented in Eq. (2). It is also clear from Figure 19 that the calculation of Qacc is false in the case of accumulation-mode MOSFETs. Indeed, the impact of the SOI layer is clearly visible and must be removed to obtain C – Vg characteristics such as the one reported for an inversion-mode MOSFETs in Figure 19.

To finish, the shift from the Si(100) wafers to the Si(110) wafers degrades the electron mobility as testified by results shown in Figures 9 and 12. The study of the mobility in Si(100) n-MOSFETs has been conducted in a similar way for 303� K exclusively, and the calculation of each scattering mechanisms showed that this degradation is actually the result of a strong limitation arising from the Coulomb and surface roughness scattering rather than the phonon mechanisms, results

Even though making use of the majority carriers to generate the current [36, 37] is already known and has been investigated more than 40 years ago, this approach has recently gained interest, and recent studies have positioned the accumulation-mode MOSFETs as serious competitors [13, 14, 38–41] to take over the conventional transistors for future CMOS technologies. Scarce data have been published so far regarding the carrier mobility flowing inside an accumulation layer [14, 36], and a method to extract it from the conventional mobility measurement is proposed here since in accumulation-mode MOSFETs the conduction, and thus, the measured mobility involves the conduction inside the accumulation layer and the conduction occurring inside the SOI layer. Planar mode fully depleted silicon-on-insulator p-type MOSFETs on three different unibond p-type SOI (100) silicon oriented wafers have been fabricated in order to assess the mobility in an accumulation layer. The doping concentration

has been formed by plasma oxidation after etching the SOI layer until reaching 50 nm. The mobility measurement method proposed in Section 2 has been followed with Qdep = 0. The results are shown in Figure 18. The mobility for the conventional inversion-mode p-MOSFETs has been reported for comparison and accurately follows the universal curve by Takagi et al. [8] at high effective electric field Eeff. While the results suggest that the mobility for the accumulation-mode devices possessing a doping concentration of 1015 and 1016 cm�<sup>3</sup> is following the universal curve, it is clear that the one with a doping concentration of 2 · 1017 cm�<sup>3</sup>

Figure 18. Experimental effective mobility μeff as a function of the effective electric field Eeff for accumulation- and

inversion-mode Si(100) p-MOSFETs featuring different doping concentrations.

. A 7.5-nm-thick gate oxide

that has been demonstrated by Gaubert et al. [33].

20 Different Types of Field-Effect Transistors - Theory and Applications

7. Mobility in an accumulation layer

of the SOI layer has been adjusted to 1015, 1016 and 2 · 1017 cm�<sup>3</sup>

The appropriate evaluation of the mobility must be conducted from the relevant data, the accumulation charge and the current generated exclusively by the accumulation layer. At the flat-band voltage Vfb, the SOI current reaches its maximum value and its subtraction from the Id – Vg curves give the current generated by the accumulation layer. Vbf is evaluated from the knowledge of the flat-band capacitance Cfb obtained from

$$\frac{1}{\mathbf{C}\_{\text{fb}}} = \frac{1}{\mathbf{C}\_{\text{ox}}} + \frac{1}{\mathbf{C}\_{\text{deb}}},\tag{12}$$

where Cdeb is the Debye capacitance and can be easily calculated like Cox. Vfb is obtained with the help of the C – Vg curves shown in Figure 19. By turn, the maximum SOI current and SOI charge are evaluated, respectively, from the Id – Vg and Qacc – Vg curves and subtracted afterwards. The calculation of the effective mobility μeff and of the effective electric field Eeff has been conducted again for the three doping concentration, and the results are shown in Figure 20. All curves are now reaching the universal curve indicating that an accumulation layer has a universal behavior identical to the one seen for an inversion layer. The universal curve by Takagi et al. [8] is appropriate for both the inversion and accumulation layers. It is also confirming the rightfulness of η = 1/3 for the calculation of the effective electric field Eeff in Eq. (7) indicating again that the carriers in an accumulation layer are behaving in a similar way than the ones in an inversion layer with regard to the phonon and surface roughness scattering mechanisms as previously described by Chindalore et al. [42]. To finish contrary to the inversion layer, an early screening of the Coulomb scattering is occurring in the case of an accumulation layer, allowing the mobility in an accumulation layer to reach at first the bulk mobility

Figure 19. Experimental capacitance C as a function of the gate voltage Vg for accumulation- and inversion-mode Si(100) p-MOSFETs with a doping concentration Nd(a) = 2 · 10<sup>17</sup> cm�<sup>3</sup> . The capacitance has been measured at Vd = 100 mV and a frequency f = 100 kHz.

Figure 20. Calculated effective mobility μeff inside the accumulation layer of accumulation-mode Si(100) p-MOSFETs featuring different doping concentrations as a function of the effective electric field Eeff.

before the phonon scatterings dominate [14, 43], thus the monotonically decrease in the mobility seen at low effective electric field Eeff in Figure 20.

These last results indicate that even if the mobility shown in Figure 18 for accumulation-mode MOSFETs with a doping concentration 1015 and 1016 cm�<sup>3</sup> could have been interpreted as correct, are actually false owing to the contribution of the SOI layer.

#### 8. Conclusion

In this chapter, we reviewed some of the main aspects of the mobility in field-effect transistors and especially for the (110) crystallographic silicon-oriented wafers. The mobility in p-MOSFETs on Si(110) wafers is limited by inter-subband scattering mechanism making its extraction by the means of the Ghibaudo method inappropriate and in turn its modeling inaccurate. A more adapted model relying on a physical approach has been developed. This new expression is incorporating the Coulomb, phonon and surface roughness scattering mechanism and is allowing a precise modeling of the drivability and transconductance in Si(110) p-MOSFETs. In addition, the study showed a clear dependency between the mobility and the channel direction for transistors fabricated on Si(110) wafers, while no impact has been noticed for conventional Si(100) wafers. The highest mobility has been revealed for a channel along the <100> direction for electron and along the <110> direction for hole. The study in temperature in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms are actually temperature dependent. More, the degradation of the electron mobility in Si(110) wafers has been explained by a substantial increase in the Coulomb and surface roughness scatterings than the phonon ones when compared with the Si(100) wafers. To finish, a methodology has been proposed and successfully employed to calculate the carrier mobility in the accumulation layer of newly developed accumulation-mode MOSFETs. The result showed afterwards that accumulation and inversion layers are behaving in a similar way in regard to the phonon and surface roughness scattering mechanism. Nevertheless, the mobility in an accumulation layer is monotonically decreasing from the bulk mobility when the electric field is increased, owing to an earlier screening of the carrier by the Coulomb scatterings.
