**4. Influence of metal-semiconductor interface on electrical stability of TFTs**

Despite the high potential of TFTs to enable low-cost electronics, these devices have the disadvantage of threshold voltage shift after a prolonged application of gate bias stress. In a-Si TFTs, the threshold voltage shift mechanisms have been studied to estimate the long-term behaviour of TFT circuits. Because of the continuous growing application of novel materialbased TFTs in electronics, an updated research for threshold voltage shift mechanisms is needed. The defect state creation in active layer and charge trapping in the gate dielectric is presumably the mechanisms responsible for the threshold voltage shift in TFTs. During the application of gate bias stress (or during normal operation), the charge trapping and defect state creation mechanisms occur simultaneously; therefore, the experimental results of threshold voltage shift do not provide any information about the quantitative effect of each of these mechanisms on the threshold voltage shift of the TFT. In addition, it has been proposed the relaxation of the threshold voltage after the annealing of the defect states in the active layer and the charge back tunnelling of trapped electrons inside the gate insulator [24–26]. However, the experimental published results for the relaxation of threshold voltage do not support the defect state annealing mechanism. While the estimations of charge trapping and de-trapping from gate insulator traps show a good agreement with the experimental threshold voltage relaxation. Therefore, from the threshold voltage shift mechanisms, charge trapping in the gate insulator is reversible [26–30].

On the other hand, the proposed mechanisms responsible for threshold voltage shift are directly related to the insulator-semiconductor interface. However, it has been also reported that quality of the metal-semiconductor interface strongly influences the kinetics of threshold voltage shift and relaxation of TFTs [31]. Based on the results reported for the charge trapping and defect state creation mechanisms of threshold voltage shift, a general conclusion cannot be drawn. The kinetics of the mechanisms strongly depends on the fabrication process of the TFTs. It is important to consider that deposition conditions of the active layer also affect the rate of the creation of the extra defect states in the active layer.

In this section, a comparison of the threshold voltage shift in TFTs with the same insulator-semiconductor interface but different metal-semiconductor interface is presented. The threshold voltage shift is calculated as a function of the stress time at gate bias stress of 20 V and *V*ds = 0 V. These are the typical conditions for electrical stress in TFTs [32–36]. The complete fabrication procedure of the TFTs can be found elsewhere [14]. The gate insulator was deposited in two sets of devices using the same deposition conditions. After that the fabrication of the metal-semiconductor interface was different. In one set of devices, it was employed the over-etching and plasma processes described in Section 2.2. As passivation layer a silicon nitride film was used. On the other set of devices, the active layer and n+ contact region films were continuously deposited with no vacuum break in the chamber. As passivation layer a silicon oxide film was used. The schematic cross-section of the fabricated devices is shown in **Figure 16**.

**Table 1** summarises the parameters extracted in both TFTs. Since both TFTs have identical insulator-semiconductor interface, the slight difference in values of subthreshold slope is

**Figure 16.** Schematic cross-section of the fabricated devices.

**4. Influence of metal-semiconductor interface on electrical stability of** 

trapping in the gate insulator is reversible [26–30].

116 Different Types of Field-Effect Transistors - Theory and Applications

rate of the creation of the extra defect states in the active layer.

cross-section of the fabricated devices is shown in **Figure 16**.

Despite the high potential of TFTs to enable low-cost electronics, these devices have the disadvantage of threshold voltage shift after a prolonged application of gate bias stress. In a-Si TFTs, the threshold voltage shift mechanisms have been studied to estimate the long-term behaviour of TFT circuits. Because of the continuous growing application of novel materialbased TFTs in electronics, an updated research for threshold voltage shift mechanisms is needed. The defect state creation in active layer and charge trapping in the gate dielectric is presumably the mechanisms responsible for the threshold voltage shift in TFTs. During the application of gate bias stress (or during normal operation), the charge trapping and defect state creation mechanisms occur simultaneously; therefore, the experimental results of threshold voltage shift do not provide any information about the quantitative effect of each of these mechanisms on the threshold voltage shift of the TFT. In addition, it has been proposed the relaxation of the threshold voltage after the annealing of the defect states in the active layer and the charge back tunnelling of trapped electrons inside the gate insulator [24–26]. However, the experimental published results for the relaxation of threshold voltage do not support the defect state annealing mechanism. While the estimations of charge trapping and de-trapping from gate insulator traps show a good agreement with the experimental threshold voltage relaxation. Therefore, from the threshold voltage shift mechanisms, charge

On the other hand, the proposed mechanisms responsible for threshold voltage shift are directly related to the insulator-semiconductor interface. However, it has been also reported that quality of the metal-semiconductor interface strongly influences the kinetics of threshold voltage shift and relaxation of TFTs [31]. Based on the results reported for the charge trapping and defect state creation mechanisms of threshold voltage shift, a general conclusion cannot be drawn. The kinetics of the mechanisms strongly depends on the fabrication process of the TFTs. It is important to consider that deposition conditions of the active layer also affect the

In this section, a comparison of the threshold voltage shift in TFTs with the same insulator-semiconductor interface but different metal-semiconductor interface is presented. The threshold voltage shift is calculated as a function of the stress time at gate bias stress of 20 V and *V*ds = 0 V. These are the typical conditions for electrical stress in TFTs [32–36]. The complete fabrication procedure of the TFTs can be found elsewhere [14]. The gate insulator was deposited in two sets of devices using the same deposition conditions. After that the fabrication of the metal-semiconductor interface was different. In one set of devices, it was employed the over-etching and plasma processes described in Section 2.2. As passivation layer a silicon nitride film was used. On the other set of devices, the active layer and n+ contact region films were continuously deposited with no vacuum break in the chamber. As passivation layer a silicon oxide film was used. The schematic

**Table 1** summarises the parameters extracted in both TFTs. Since both TFTs have identical insulator-semiconductor interface, the slight difference in values of subthreshold slope is

**TFTs**


**Table 1.** Comparison of the parameters of the TFTs.

considered just statistical fluctuation. The values of off-current are of the same order of magnitude. The on/off-current ratio is very similar for both TFTs. However, an important difference in field-effect mobility is found. The mobility for TFTs using SiNx as a passivation layer (hydrogen plasma) was 0.85 cm<sup>2</sup> /Vs, higher than the 0.68 cm<sup>2</sup> /Vs for TFTs using SiO<sup>2</sup> passivation. This result is related to the metal-semiconductor interface, the higher value of mobility may indicate a lower contact resistance.

**Figure 17** shows the threshold voltage shift ∆*V*T as a function of the stress time. The figure shows a higher shift for TFTs using SiN*x* passivation. It is important to mention that the observed threshold voltage shift for both TFTs could not be recovered after a rest period of 48 hours and under the application of negative gate bias, suggesting that the shift is irreversible. Since the charge trapping in the gate insulator is reversible, therefore, under the applied gate bias conditions, the shift in the threshold voltage seems to be due to creation of defect states in the active layer.

The higher value of mobility results of a lower contact resistance, however, the higher instability of this TFT related to defect state creation suggests a dependency with the fabrication of the metal-semiconductor interface. Probably due to defects induced by the over-etching process. Also, the SiN*x* passivation layer may has influence on the electrical instability of the TFT. Further research is necessary to address these assumptions. Although both TFTs

**Figure 17.** Threshold voltage shift ∆*V*T as function of the stress time.

have the same insulator-semiconductor interface, the metal-semiconductor interface plays an important role in the electrical stability of these devices. The research of the kinetics of the mechanisms responsible for the instability on TFTs needs to be extensively explored for emergent TFT technologies.
