**3. Alternatives for metal-semiconductor interface improvement**

The requirements for getting a high-quality metal-semiconductor interface are complex. Typically, in field-effect transistors, a heavily doped interlayer or contact region film is used between the semiconductor and source/drain electrodes in order to improve the metal-semiconductor interface. However, in amorphous semiconductors, the doping efficiency drops at high doping levels. Moreover, in some TFT technologies, there are no doped interlayer films to improve the metal-semiconductor interface. These make even more complex to obtain a high-quality interface.

#### **3.1. Doped regions for source/drain contacts**

In the case of hydrogenated amorphous silicon (a-Si:H), Le Comber and Spear [13] reported that amorphous silicon prepared by plasma-enhanced chemical vapor deposition (PECVD) can effectively be doped by adding small amounts of phosphine (PH<sup>3</sup> ) or diborane (B<sup>2</sup> H6 ) to the silane (SiH<sup>4</sup> ) in the discharge gas. As expected, the conductivity increases at low doping levels. However, at higher doping levels, the conductivity decreases presumably due to the generation of defect states.

**Figure 2** shows the contact resistance of a-Ge:H films at 200°C as function of the PH<sup>3</sup> flow. At low flow of PH<sup>3</sup> the contact resistance decreases, but at higher flow it increases. This behaviour agrees with the reported by Le Comber and Spear. Similarly, **Figure 3** shows the contact resistance of the p-type a-Ge:H film as a function of the B<sup>2</sup> H6 flow. At low flow of B<sup>2</sup> H6 , the contact resistance increases but at higher flow it decreases and finally increases again. This behaviour also agrees with the reported by Le Comber and Spear. These interlayer films enhance the tunnelling of carriers through the metal-semiconductor interface, reducing the contact resistance and improving the interface. The n-type a-Ge:H film was successfully used as a contact region film in ambipolar a-SiGe:H TFTs [14].

#### **3.2. Plasma processes to improve the contact resistance**

In this section, the improvement of carrier mobility, on/off-current ratio and threshold voltage using hydrogen plasma at the active layer prior to define the source/drain contacts is presented. Firstly, an over-etching in the active layer before forming the source/drain contacts is performed. This over-etching closes the source/drain contacts to the induced channel layer, as indicate in **Figure 4**.

**Figure 4a** shows the structure of the TFT after the deposition of the gate electrode, gate insulator, active layer and passivation layer. Typically, after this step, the passivation layer is etched to form the source/drain contacts (**Figure 4b**). In this case, added to the etching of the passivation layer, an over-etching in the active layer is performed, as indicate in **Figure 4c**. Moreover,

**Figure 2.** Contact resistance of the n-type a-Ge:H films as a function of the PH<sup>3</sup> flow.

**Figure 3.** Contact resistance of the p-type a-Ge:H films as a function of the B<sup>2</sup> H6 flow.

**Figure 2** shows the contact resistance of a-Ge:H films at 200°C as function of the PH<sup>3</sup>

tact resistance of the p-type a-Ge:H film as a function of the B<sup>2</sup>

as a contact region film in ambipolar a-SiGe:H TFTs [14].

106 Different Types of Field-Effect Transistors - Theory and Applications

**3.2. Plasma processes to improve the contact resistance**

**Figure 2.** Contact resistance of the n-type a-Ge:H films as a function of the PH<sup>3</sup>

iour agrees with the reported by Le Comber and Spear. Similarly, **Figure 3** shows the con-

the contact resistance increases but at higher flow it decreases and finally increases again. This behaviour also agrees with the reported by Le Comber and Spear. These interlayer films enhance the tunnelling of carriers through the metal-semiconductor interface, reducing the contact resistance and improving the interface. The n-type a-Ge:H film was successfully used

In this section, the improvement of carrier mobility, on/off-current ratio and threshold voltage using hydrogen plasma at the active layer prior to define the source/drain contacts is presented. Firstly, an over-etching in the active layer before forming the source/drain contacts is performed. This over-etching closes the source/drain contacts to the induced channel layer,

**Figure 4a** shows the structure of the TFT after the deposition of the gate electrode, gate insulator, active layer and passivation layer. Typically, after this step, the passivation layer is etched to form the source/drain contacts (**Figure 4b**). In this case, added to the etching of the passivation layer, an over-etching in the active layer is performed, as indicate in **Figure 4c**. Moreover,

the contact resistance decreases, but at higher flow it increases. This behav-

H6

flow.

low flow of PH<sup>3</sup>

as indicate in **Figure 4**.

flow. At

H6 ,

flow. At low flow of B<sup>2</sup>

a hydrogen plasma is applied [15]. For comparison, a set of devices without hydrogen plasma was fabricated. Finally, the source/drain contacts are formed (**Figure 4d**).

**Figure 5** shows the transfer characteristics of the TFTs with and without hydrogen plasma. The TFTs with applied hydrogen plasma exhibit an on/off-current ratio approximately of 10<sup>6</sup> and an off-current approximately of 300 fA at 0 *V*gs. While the TFTs without hydrogen plasma exhibit an on/off-current ratio of 10<sup>3</sup> and off-current of 20 pA. The subthreshold slopes values for both TFTs with and without hydrogen plasma were 0.56 and 0.61 V/DEC, respectively. The slopes are very similar. Typically, in TFTs, the subthreshold slope is largely decided by the quality of gate insulator-active layer interface. The subthreshold slope is dependent on the trap density in the active layer (*N*T) and at the interface (*D*it). The subthreshold slope can be approximated as the following equation [15]:

$$S = qK\_\text{\tiny{}^\circ C} \text{T} \{ N\_\text{\tiny{}^\circ C} \text{ts} + D\_\text{\tiny{}^\circ} \} / C\_\text{\tiny{}^\circ C} \text{log}(e) \tag{1}$$

where *q* is the electron charge, *K*B is the Boltzmann constant, *T* is the absolute temperature, *t*s is the active layer thickness and *C*ox is the gate insulator capacitance per unit area. If *N*T or *D*it is separately set to zero, the respective maximum values of *N*T and *D*it are obtained. The *N*<sup>T</sup> and *D*it values were of 2.65 × 10<sup>17</sup> cm−3/eV and 2.65 × 1012 cm−2/eV, respectively, for TFTs with applied hydrogen plasma. For TFTs without hydrogen plasma, the values were of 2.88 × 1017 cm−3/eV and 2.88 × 1012 cm−2/eV, respectively. Since both TFTs have identical insulator-semiconductor interface and the over-etching process only affects the source/drain regions, we do not expect any difference in the quality of the insulator-semiconductor interface of the devices.

**Figure 4.** Process flow and cross-section of the TFT with over-etching at source/drain regions. (See text for description).

**Figure 5.** Transfer characteristics of the TFTs with and without hydrogen plasma.

**Figure 4.** Process flow and cross-section of the TFT with over-etching at source/drain regions. (See text for description).

108 Different Types of Field-Effect Transistors - Theory and Applications

On the other hand, **Figure 6** shows the square root of *I* ds vs. *V*gs of the TFT at a saturation regime. The threshold voltage and field-effect mobility can be extracted from the intercept with *V*gs axis and slope, using Eq. (2).

$$I\_{ds} = \mu\_{\rm FE} C\_{\rm ox} (\mathcal{W}/2L)(V\_{gs} - V\_{\rm \tau})^2 \tag{2}$$

where *μ*FE is the field-effect mobility, *C*ox is the capacitance per unit area of the gate insulator, *W* and *L* are the channel width and the length, respectively, and *V*T is the threshold voltage. The extracted threshold voltage and field-effect mobility were of 0.8 and 0.85 cm<sup>2</sup> /Vs, respectively, for TFTs with hydrogen plasma. While 1.86 and 0.52 cm<sup>2</sup> /Vs were extracted for TFTs without hydrogen plasma.

It is well known that hydrogen saturates dangling bonds in amorphous films [16]. Thus, the hydrogen plasma reduces the plasma-induced damage in the source/drain regions of the active layer, and as result the contact resistance of the TFT is improved. This can be corroborated with the higher values of carrier mobility and on-current.

**Figures 7** and **8** show the output characteristics of the TFTs with and without hydrogen plasma. The output characteristics of TFTs without hydrogen plasma exhibit a high contact resistance that appears in the form of current crowding, in the bias range of 0–1V of *V*ds. Also, the driving current capability is higher for TFTs with hydrogen plasma, as indicated by their values of *I* ds. These results confirm the hydrogen plasma reduces the plasma-induced damage and improve the metal-semiconductor interface. These processes in the source/drain regions lead to form good ohmic contacts.

**Figure 6.** Square root of *I*ds vs. *V*gs of the TFT at saturation regime.

**Figure 7.** Output characteristics of TFTs with over-etching and hydrogen plasma.

**Figure 8.** Output characteristics of TFTs with over-etching but without hydrogen plasma.

#### **3.3. Planarization of the gate electrode in bottom-gate TFTs**

**Figure 6.** Square root of *I*ds vs. *V*gs of the TFT at saturation regime.

110 Different Types of Field-Effect Transistors - Theory and Applications

**Figure 7.** Output characteristics of TFTs with over-etching and hydrogen plasma.

Thin-film transistors are successfully employed in active-matrix displays [17]. In this application, the inverted staggered structure is the most used [17]. In an inverted structure, the gate electrode is placed at the bottom of the structure (bottom-gate structure). The advantage of using this inverted structure is that the gate electrode protects the active layer from backplane light. The problem is when the active-matrix displays become larger, the number of address lines must increase and the gate lines must be narrower and longer. To avoid an increase in the resistance of the gate line, which results in delay on the display performance, the gate line must be thicker. Then, the problem with this thicker gate is that the gate insulator tends to be thinner around the corners of the gate, increasing the leakage current and electric stress due to the high electric field at the corner [18]. In order to reduce these effects, the planarization of the gate electrode was proposed by other groups [19, 20].

As far as we know, the only work related to the study of the planarization of the gate electrode is conducted by Chen et al. [18]. They reported a reduction in the contact resistance attributed to the planarization process. However, this improvement in the contact resistance is difficult to understand, since the planarization of the gate electrode improves the insulatorsemiconductor interface but not the metal-semiconductor interface. Firstly, the experimental characteristics of planarized and unplanarized TFTs are presented. After that using a physically based simulator (SILVACO), the main interfaces are analysed to understand the origin of this improvement.

The experimental transfer characteristics of unplanarized and planarized TFTs are shown in **Figure 9**. The planarized TFT shows a subthreshold slope ~0.45 V/DEC and ~0.49 V/DEC, for n-type and p-type regions, respectively, while on/off-current ratios around 10<sup>5</sup> were obtained for n-type and p-type regions. On the other hand, the unplanarized TFT shows a subthreshold slope ~1 V/DEC for an n-type region and 1.3 V/DEC for a p-type region, on/off-current ratios ~10<sup>4</sup> and 103 for n-type and p-type regions, respectively.

The threshold voltage and field-effect mobility were extracted from the transfer characteristics operating in the saturation regime (*V*ds = *V*gs), using Eq. (2). For planarized TFTs, the threshold voltage was 1.11 and −2.18 V for n-type and p-type regions, respectively. The extracted fieldeffect mobilities were 0.68 and 0.15 cm<sup>2</sup> /Vs for n-type and p-type regions, respectively. For unplanarized TFTs, the threshold voltage was 2.4 and −3.35 V for n-type and p-type regions, respectively. The extracted field-effect mobilities were 0.11 cm<sup>2</sup> /Vs for an n-type region and 0.02 cm2 /Vs for a p-type region.

**Figure 10** shows the output characteristics for planarized and unplanarized TFTs. It is important to mention that the output characteristics show an ambipolar behaviour. A detailed discussion and modelling can be found in Ref. [14]. In the output characteristics of unplanarized TFTs, current crowding appears in the bias range from 0 to 1 V of *V*ds. This high contact resistance effect slightly appears in planarized TFTs. To corroborate this effect, the contact resistance was extracted from the n-type region of both planarized and unplanarized TFTs. The contact resistance was extracted by the extrapolation of the width-normalized contact resistance as indicated in **Figure 1**. The contact resistance was approximately 1413 Ωcm for

**Figure 9.** Transfer characteristics of unplanarized and planarized TFTs.

The experimental transfer characteristics of unplanarized and planarized TFTs are shown in **Figure 9**. The planarized TFT shows a subthreshold slope ~0.45 V/DEC and ~0.49 V/DEC, for

for n-type and p-type regions. On the other hand, the unplanarized TFT shows a subthreshold slope ~1 V/DEC for an n-type region and 1.3 V/DEC for a p-type region, on/off-current ratios

The threshold voltage and field-effect mobility were extracted from the transfer characteristics operating in the saturation regime (*V*ds = *V*gs), using Eq. (2). For planarized TFTs, the threshold voltage was 1.11 and −2.18 V for n-type and p-type regions, respectively. The extracted field-

unplanarized TFTs, the threshold voltage was 2.4 and −3.35 V for n-type and p-type regions,

**Figure 10** shows the output characteristics for planarized and unplanarized TFTs. It is important to mention that the output characteristics show an ambipolar behaviour. A detailed discussion and modelling can be found in Ref. [14]. In the output characteristics of unplanarized TFTs, current crowding appears in the bias range from 0 to 1 V of *V*ds. This high contact resistance effect slightly appears in planarized TFTs. To corroborate this effect, the contact resistance was extracted from the n-type region of both planarized and unplanarized TFTs. The contact resistance was extracted by the extrapolation of the width-normalized contact resistance as indicated in **Figure 1**. The contact resistance was approximately 1413 Ωcm for

/Vs for n-type and p-type regions, respectively. For

were obtained

/Vs for an n-type region and

n-type and p-type regions, respectively, while on/off-current ratios around 10<sup>5</sup>

for n-type and p-type regions, respectively.

respectively. The extracted field-effect mobilities were 0.11 cm<sup>2</sup>

**Figure 9.** Transfer characteristics of unplanarized and planarized TFTs.

~10<sup>4</sup>

0.02 cm2

and 103

effect mobilities were 0.68 and 0.15 cm<sup>2</sup>

112 Different Types of Field-Effect Transistors - Theory and Applications

/Vs for a p-type region.

**Figure 10.** Output characteristics for planarized and unplanarized TFTs. a) Planarized and b) Unplanarized.

unplanarized TFTs and 589 Ωcm for planarized TFTs. This agrees with the higher values of drain current in planarized TFTs. It is important to note that subthreshold slope is improved in planarized TFTs. Some authors suggest a better injection of carriers from the source electrode into the active layer [21]. Also, other authors have reported a better subthreshold slope after improving the contact resistance [22, 23].

The experimental results agree with the reported previously by Chen et al. However, the improvement in contact resistance by the planarization process is unexplained. Using ATHENA, both planarized and unplanarized structures were simulated. Then, using ATLAS, electrical measurements were simulated. The cutline tool within the ATLAS simulator generates one-dimensional profiles from the insulator-semiconductor and metal-semiconductor interfaces. Ideal contacts were considered for source/drain contacts in both unplanarized and planarized simulated TFTs (ohmic contacts without contact resistance).

**Figure 11** shows a comparison of the cross-section of planarized and unplanarized TFTs simulated by ATHENA. Applying a positive gate bias of 5 V, the electric field of the planarized and unplanarized gate electrodes was extracted by ATLAS (**Figure 12**). As expected, for the planarized TFT, the electric field is uniform through the insulator-semiconductor interface. However, for the unplanarized TFT, the electric field is not uniform through the insulatorsemiconductor interface. There is an increase of the electric field due to the thinner gate insulator. This increase in the electric field causes an accumulation of electrons in the channel close to the corners of the gate, as shows **Figure 13**.

The difference of the electron concentration in the channel works as a scattering mechanism, limiting the mobility of the carriers. This can explain the lower extracted field-effect mobility in the unplanarized TFTs. Also, the variations of the electron concentration reflect an increase in the conduction band energy of the active layer close to the source/drain contacts, as show in **Figure 14**. This increase in energy acts as a barrier for the electrons, where only electrons with higher energy can pass the barrier. As result, the device contact resistance apparently

**Figure 11.** Cross-section of planarized and unplanarized TFTs simulated by ATHENA. a) Planarized and b) Unplanarized.

**Figure 12.** Electric field of the planarized and unplanarized TFTs simulated by ATLAS. a) Planarized and b) Unplanarized.

**Figure 13.** Accumulation of electrons in the channel close to the corners of the gate simulated by ATLAS. a) Planarized and b) Unplanarized.

**Figure 14.** Conduction band energy of the active layer close to the source/drain contacts. a) Planarized and b) Unplanarized.

increases. To corroborate these assumptions, **Figure 15** shows the simulated output characteristics of both planarized and unplanarized TFTs. The simulation agrees with the behaviour exhibited in the experimental and simulated results.

**Figure 15.** Simulated output characteristics of planarized and unplanarized TFTs.

**Figure 13.** Accumulation of electrons in the channel close to the corners of the gate simulated by ATLAS. a) Planarized

**Figure 11.** Cross-section of planarized and unplanarized TFTs simulated by ATHENA. a) Planarized and b) Unplanarized.

114 Different Types of Field-Effect Transistors - Theory and Applications

**Figure 12.** Electric field of the planarized and unplanarized TFTs simulated by ATLAS. a) Planarized and b) Unplanarized.

and b) Unplanarized.
