4. Electrical characterization of semiconductor interfaces: semiconductor doping, interfacial and oxide charges

#### 4.1. Steady-state capacitance

An overview of charge carrier profiling, steady-state and transient capacitance, deep-level transient spectroscopy methods can be found in Ref. [82]. CV methods are most frequently used to extract parameters critical for operation of semiconductor devices. The interface trap densities, the fixed oxide charge, the carrier concentration in a semiconductor, and the permittivity of an insulator can be obtained from CV measurements. Here, more emphasis is given to basic limitations of CV methods, possible errors, and examples of using CV techniques.

The measure of charge responses in MOS devices as a function of electric field is the differential capacitance. To account for the interface trap effects, the Berglund method that establishes the relation between applied voltage across the MOS structure and the band-bending in equilibrium can be used [83]. Figure 6 exemplifies the energy distributions of the interface states at the (100)Si/SiO2 and (100)Si/HfO2 interfaces in panels (a) and (b), respectively. The Dit distributions in panel (a) are obtained using the Berglund procedure. The results of Dit distributions extracted from a low-frequency CV curve and ac admittance data are compared in panel (b) indicating a perfect match in the energy range where the fast interface states contribute to the emission of charge carriers. The Si/SiO2 interface trap distributions derived from the 100 Hz CV curves reveal two peaks centered at 0.25 and 0.85 eV above the Si valence-band edge, Figure 6(a). The peaks are superimposed on the U-shaped background corresponding to a continuous distribution of the surface states in energy and ascribed to the existence of weak SiSi and SiO bonds at the Si/SiO2interface [84]. The observed peak energy positions correspond to the (+/0) and (0/) transitions of the amphoteric Pb0 defect. No measurable contribution of the Pb1 center to the Dit could be detected in the central part of the Si bandgap, in agreement with the previous studies [74], which compare the total interface trap density Nit and the Pb0 and Pb1 densities inferred from the ESR data. The estimation of the total interface trap density Nit in work [74] was done according to Gray and Brown as described in work [85]. This procedure is advantageous over the low-frequency Berglund method in the following: (i) It allows detection of the interface states close (20 meV) to the Si band gap edges, inaccessible for room-temperature

proton can be trapped by the oxide network and form a donor-like surface state. When hydrogen is available in gate oxides as it can be upon an irradiation process, the neutral E´

Charge trapping in gate oxides is one of the major obstacles in integration of high-k gate dielectrics in CMOS technology. Among the issues is the enhanced migration of dopant impurities originating from ion implantation steps. As such, ESR studies are indispensable to unravel point defects, which may appear detrimental for MOSFET performance. For example, ESR studies of phosphorous implanted high-k dielectrics reveal that P incorporating in the metal oxide network forms point defects by substituting for Hf or Zr in HfO2 or ZrO2, respectively [76]. Such defects formed due to enhanced migration of dopant impurities during dopant activation thermal steps may potentially trap charge.ESR studies have been applied to diverse ion-implanted systems. In SiO2,

ultrasound treatment was applied during implantation of Si+ ions into thermal SiO2 on (100)Si [77]; ESR found a radical mechanism of degradation of the ion-implanted photoresist [78]. Applications of the ESR techniques to study ion-beam-induced implantation damage in carbon-based materials

ESR techniques have been explored in studies of spintronic materials fabricated by ion implantation. To probe the spin relaxation, the technique of choice is the pulse-electron spin resonance spectroscopy. ESR studies have been undertaken to measure spin relaxation times of dopants in Si. Shallow donors in Si are known for their long relaxation time suggesting a possible application of spins as qubits. The transverse relaxation time measured for isolated spins is associated with the decoherence time. ESR studies have been used to determine spin relaxation times in Sb-implanted isotopically enriched 28Si [80]. It has been shown that annealing of ultralow dose antimony implants leads to high degrees of electrical dopant activation with minimal diffusion. Spin relaxation times were increased when paramagnetic defects at the Si/ SiO2 interface were passivated by hydrogen. Except for the Si/SiO2 system, pulsed ESR experiments have been used to characterize the coherent spin dynamics of nanofabricated nitrogen

4. Electrical characterization of semiconductor interfaces: semiconductor

An overview of charge carrier profiling, steady-state and transient capacitance, deep-level transient spectroscopy methods can be found in Ref. [82]. CV methods are most frequently used to extract parameters critical for operation of semiconductor devices. The interface trap densities, the fixed oxide charge, the carrier concentration in a semiconductor, and the permittivity of an insulator can be obtained from CV measurements. Here, more emphasis is given to basic limitations of CV methods, possible errors, and examples of using CV techniques.

The measure of charge responses in MOS devices as a function of electric field is the differential capacitance. To account for the interface trap effects, the Berglund method that establishes

<sup>γ</sup> centers (Si enrichment in the oxide) was found when in situ

center may be again passivated serving as a hole-trapping site.

vacancy centers in nitrogen implanted high-purity diamond [81].

doping, interfacial and oxide charges

4.1. Steady-state capacitance

a substantial reduction in S and E<sup>0</sup>

78 Ion Implantation - Research and Application

have been described in Ref. [79].

Figure 6. The interface trap distributions inferred from the capacitance-voltage measurements following the Berglund method and compared with these determined from ac conductance data as denoted by (•) symbols in panel (b).

CV analysis. (ii) It is decoupled from the uncertainty of Si surface potential determination near the band edges when the interface trap density is high.

A strong capacitance dispersion and dc leakage current may hamper application of CV methods based on low-high frequency CV measurements. As such, the Terman procedure based on comparison of the calculated ideal and experimental high-frequency CV curves may have limited applications in determining the interface trap densities in the case of interfaces of high-k dielectrics with semiconductors. Also, the interface trap contribution to the CV curve shift in voltage due to the interface traps becomes less prominent when equivalent electrical thickness of an insulator decreases [86, 87].

CV techniques can be used to extract the charge carrier profile in a semiconductor, the important characteristic of ion-implanted devices. The dopant profile is obtained from the high-frequency CV curve to minimize possible uncertainties stemming from the interface trap charge contribution to the depletion layer capacitance. The principle behind the dopant profiling is that as the semiconductor becomes depleted by the majority carriers, the capacitance decreases. A rapid decrease of the capacitance indicates a low dopant concentration, whereas a slow reduction indicates a high doping level. The capacitance as a function of voltage is related to the majority carrier density and can be obtained from the slope of the Mott-Schottky curve [88].

A variant of CV carrier profiling, which employs an electrochemical contact to a semiconductor, is an electrochemical capacitance-voltage (ECV) technique. ECV may appear as advantageous compared to the conventional CV methods due to its capability to measure spatial-ionized impurity distribution to practically unlimited depth, not being hindered by the breakdown at a high doping level [89]. ECV profiling can be applied to materials, which cannot be studied by the Hall measurements, for example, to conductive ferromagnetic semiconductors [90]. Despite its utility, ECV applicability is limited by the sample thickness when it is comparable with the Debye length, or, if a sample consists of several thin layers, which are either of different chemical composition or doping. The charge transfer at the interface is an important difference between a semiconductor/electrolyte (SE) interface and a Schottky contact. In the former case, it is supported by an electrochemical process. Parameters of the SE interface are determined by the electronic structure of the interface. The potential distribution in the SE interface and the effects of the semiconductor surface states on the potential redistribution between the semiconductor and the Helmholtz layer have been considered in review articles [91, 92]. When the surface states are not present at the semiconductor electrode the reverse bias drops across the semiconductor space charge region. It is than possible to determine the carrier concentration in the semiconductor. Except for the charge trapped in the surface states, there can be other charges, which result in the flat band voltage shift (Vfb) and modify the capacitive-frequency responses. An interfacial electric dipole layer can also result in a Vfb shift when the latter coincides with the change in electron affinity indicating that the dipoles attached to the semiconductor surface contribute to the Vfb shift, not surface charges.

Analysis of CMOS devices with nanometer thin insulators requires taking into account quantummechanical effects in the accumulation capacitance [93, 94] and the inversion capacitance [95] in order to extract the equivalent oxide thickness or the semiconductor doping density, respectively. The doping density can be extracted from the inversion layer capacitance by relating the depletion layer width WD and the carrier concentration NA,D

$$\mathcal{W}\_D = \sqrt{\frac{4\varepsilon\_s \, kT \ln(N\_{A,D}/n\_i)}{q \cdot (N\_{A,D})}} \tag{3}$$

where ni is the intrinsic concentration in a semiconductor at a given temperature T and q is the elemental charge [96].

Alternatively, the doping density can be known from the band bending at the onset of strong inversion Ψs inv ≈ <sup>2</sup>kT q ln NA,D ni � �: The surface potential is obtained by using the Berglund integral. For the scaled MOS devices, one has to take into account the contribution of the finite density of states and the finite inversion layer thickness to the inversion layer capacitance or utilize the capacitance in the weak inversion to extract the substrate doping (cf. Figure 2 in Ref. [95]). The inference of the semiconductor substrate doping from the inversion capacitance may appear to be superior over other experimental approaches, because it is decoupled from the possible contribution of the interface states to the depletion layer capacitance. This technique has been applied to trace boron concentration in silicon as a probe for the presence of radiolytic hydrogen in SiO2 when analyzing the impact of vacuum ultraviolet irradiation and ion implantation of fluorine and argon on charge built-up in Si/SiO2 MOS systems [97, 98]. Local characteristics of dopants can be obtained on semiconductor devices by using the scanning capacitance microscopy, a technique based on local capacitance-voltage analysis with submicron spatial resolution [99].

#### 4.2. Steady-state ac conductance

CV analysis. (ii) It is decoupled from the uncertainty of Si surface potential determination near

A strong capacitance dispersion and dc leakage current may hamper application of CV methods based on low-high frequency CV measurements. As such, the Terman procedure based on comparison of the calculated ideal and experimental high-frequency CV curves may have limited applications in determining the interface trap densities in the case of interfaces of high-k dielectrics with semiconductors. Also, the interface trap contribution to the CV curve shift in voltage due to the interface traps becomes less prominent when equivalent electrical

CV techniques can be used to extract the charge carrier profile in a semiconductor, the important characteristic of ion-implanted devices. The dopant profile is obtained from the high-frequency CV curve to minimize possible uncertainties stemming from the interface trap charge contribution to the depletion layer capacitance. The principle behind the dopant profiling is that as the semiconductor becomes depleted by the majority carriers, the capacitance decreases. A rapid decrease of the capacitance indicates a low dopant concentration, whereas a slow reduction indicates a high doping level. The capacitance as a function of voltage is related to the majority carrier density and can be obtained from the slope of the

A variant of CV carrier profiling, which employs an electrochemical contact to a semiconductor, is an electrochemical capacitance-voltage (ECV) technique. ECV may appear as advantageous compared to the conventional CV methods due to its capability to measure spatial-ionized impurity distribution to practically unlimited depth, not being hindered by the breakdown at a high doping level [89]. ECV profiling can be applied to materials, which cannot be studied by the Hall measurements, for example, to conductive ferromagnetic semiconductors [90]. Despite its utility, ECV applicability is limited by the sample thickness when it is comparable with the Debye length, or, if a sample consists of several thin layers, which are either of different chemical composition or doping. The charge transfer at the interface is an important difference between a semiconductor/electrolyte (SE) interface and a Schottky contact. In the former case, it is supported by an electrochemical process. Parameters of the SE interface are determined by the electronic structure of the interface. The potential distribution in the SE interface and the effects of the semiconductor surface states on the potential redistribution between the semiconductor and the Helmholtz layer have been considered in review articles [91, 92]. When the surface states are not present at the semiconductor electrode the reverse bias drops across the semiconductor space charge region. It is than possible to determine the carrier concentration in the semiconductor. Except for the charge trapped in the surface states, there can be other charges, which result in the flat band voltage shift (Vfb) and modify the capacitive-frequency responses. An interfacial electric dipole layer can also result in a Vfb shift when the latter coincides with the change in electron affinity indicating that the dipoles attached to the semiconductor surface contribute to

Analysis of CMOS devices with nanometer thin insulators requires taking into account quantummechanical effects in the accumulation capacitance [93, 94] and the inversion capacitance [95] in order to extract the equivalent oxide thickness or the semiconductor doping density, respectively.

the band edges when the interface trap density is high.

thickness of an insulator decreases [86, 87].

80 Ion Implantation - Research and Application

Mott-Schottky curve [88].

the Vfb shift, not surface charges.

The dynamic electrical responses of junction space-charge layers can be probed by using ac admittance spectroscopy or transient spectroscopy methods. These methods are applicable to both the deep bulk trap [100, 101] and interface trap [102, 103] studies in MOS devices. The ac admittance method is a classical approach to characterize the interface states in MOS structures [104]. The method better accentuates fast interface states, which are spatially located at the SI interface plane. The method considers the imaginary part of the measured admittance, which is directly linked to the charge trapped and emitted from the interface states as a consequence of the applied ac electric field. The localized states exchanging charge with the majority carrier band of a semiconductor respond to ac signal with both the capacitive and conductive components. At a particular frequency ω which is ωτ = 1, where τ is the characteristic time constant for the charge exchange with the localized state. The ratio Gp/ω reaches a maximum value directly proportional to the density of the surfaces states Dit. The trap occupancy is modulated by the semiconductor surface potential Ψs. The capture cross sections sp,<sup>n</sup> and the trap densities Nt(p,n) can be inferred from the frequency dependences of conductance exemplified in Figure 7. The interface trap resonances can be analyzed by using different models. Initially, it was suggested that there exists a quasicontinuous distribution of the interface states localized at the SI interface and that the surface charge and potential are uniform all over the interface. The broadening of the experimental normalized conductance curves was explained by Nicollian and Goetzberger as related to a random oxide charge and charge of the interface

states distributed in the interface plane [105]. The tunnel recharging of the traps has been considered in Ref. [106]. To account for asymmetric conductance peaks, another model suggested that the interface traps at a particular energy have a range of cross sections spanning over orders of magnitude [107].

In nanoscale CMOS devices, the excessive leakage current impacts characterization of the interface traps by application of ac admittance spectroscopy. It has been demonstrated that errors in series resistance are critical when Dit values are determined at the accumulation band bending, while high tunnel currents hamper characterization of the midgap interface states [108]. The practical solution of the problem associated with the interface trap characterization in tunnel MOS-devices is the use of the charge pumping method [109, 110]. When the leakage current does not impede the interface trap analysis, the interface states in the (100)Si/SiO2 and (100)Si/HfO2 entities can be reliably inferred from the capacitance frequency dispersion [111, 112] or ac admittance spectroscopy combined with the CV methods [113]. In the latter work, it has been observed that the Dit density measured on Hf-containing samples subjected to a high-temperature anneal in oxygen and a subsequent passivation in hydrogen is still higher than that inferred for the equally treated (100)Si/SiO2 interface. After passivation in molecular hydrogen, both the HfO2 and SiO2 interfaces with Si exhibited the Dit peak positioned at 0.4 eV above the silicon valence band top. When Pb0 centers are passivated by molecular hydrogen the ac conductance responses are dominated by the contribution of the slow states, which are usually ascribed to the oxide-related imperfections. The slow states giving rise to the feature observed at 0.4 eV are likely to originate from the near interfacial oxide interlayer and could exist due to a lattice distortion in strained interfaces.

Figure 7. Equivalent parallel conductance as a function of frequency. The points are experimental values taken on a MOScapacitor at different surface potentials ψs. The silicon substrate is of p-type conductivity.

#### 4.3. Transient capacitance

states distributed in the interface plane [105]. The tunnel recharging of the traps has been considered in Ref. [106]. To account for asymmetric conductance peaks, another model suggested that the interface traps at a particular energy have a range of cross sections spanning

In nanoscale CMOS devices, the excessive leakage current impacts characterization of the interface traps by application of ac admittance spectroscopy. It has been demonstrated that errors in series resistance are critical when Dit values are determined at the accumulation band bending, while high tunnel currents hamper characterization of the midgap interface states [108]. The practical solution of the problem associated with the interface trap characterization in tunnel MOS-devices is the use of the charge pumping method [109, 110]. When the leakage current does not impede the interface trap analysis, the interface states in the (100)Si/SiO2 and (100)Si/HfO2 entities can be reliably inferred from the capacitance frequency dispersion [111, 112] or ac admittance spectroscopy combined with the CV methods [113]. In the latter work, it has been observed that the Dit density measured on Hf-containing samples subjected to a high-temperature anneal in oxygen and a subsequent passivation in hydrogen is still higher than that inferred for the equally treated (100)Si/SiO2 interface. After passivation in molecular hydrogen, both the HfO2 and SiO2 interfaces with Si exhibited the Dit peak positioned at 0.4 eV above the silicon valence band top. When Pb0 centers are passivated by molecular hydrogen the ac conductance responses are dominated by the contribution of the slow states, which are usually ascribed to the oxide-related imperfections. The slow states giving rise to the feature observed at 0.4 eV are likely to originate from the near interfacial

oxide interlayer and could exist due to a lattice distortion in strained interfaces.

Figure 7. Equivalent parallel conductance as a function of frequency. The points are experimental values taken on a MOS-

capacitor at different surface potentials ψs. The silicon substrate is of p-type conductivity.

over orders of magnitude [107].

82 Ion Implantation - Research and Application

Transient-capacitance spectroscopy has been initially developed to study deep bulk trap levels in semiconductors and termed by Lang as deep-level transient spectroscopy (DLTS). The capacitance DLTS is a preferred variant of the transient measurements, because it allows to separate minority and majority carrier emissions [114]. The technique is based on recording fast capacitance transients and passing the transient signal through a rate window circuit using a boxcar integrator and predefining the width of the gate pulse, the integrator response time, and the rate-window time constant. A lock-in amplifier used instead of a boxcar integrator requires settings for the rate-window, the initial gate-off period and the phase. When the traps are continuously distributed in energy (such as the interface traps) the measurement yields an emission time-constant spectrum, which depends on both the trap distribution and capture cross sections. A conventional DLTS procedure uses biases in depletion and pulsed voltage to populate interface traps with majority carriers. The responses of the device capacitance are recorded as the interface trap occupancy tends to equilibrium distribution. The energy of the traps can be determined independently of the emission rate by using two charging pulses of slightly different amplitude to selectively populate the interface traps [115]. A new method to determine capture cross sections independently of temperature and energy has been proposed in the work [116]. The method exploits the use of small trap-filling pulses to narrow the energy range within which the surface states become populated with majority carriers. Schematic diagrams representing (a) energy bands at the SI interface and (b) the pulsing sequence are shown in Figure 8.

When a voltage pulse sequence ΔV is superimposed on a constant voltage biasing a MOS structure to the surface depletion by the majority carriers, the capacitance difference recorded between times t1 and t2 is expressed as

Figure 8. Schematic diagrams representing (a) energy bands at the SI interface and (b) the capacitance and the surface potential at the SI interface.

$$
\Delta \mathcal{C} = A \int\_{E\_v}^{E\_c} N\_s(E) \left[ e^{-\frac{\ell\_1}{\tau\_n}} - e^{-\frac{\ell\_2}{\tau\_n}} \right] [f\_0(E) - f\_1(E)] dE,\tag{4}
$$

where NS(E) is the surface state density at energy E, τ<sup>n</sup> is the emission time constant for electrons when considering n-type semiconductor. A constant A= С<sup>3</sup> <sup>0</sup>=εsCoxND, where C<sup>0</sup> is a capacitance at reverse bias, ε<sup>s</sup> is the Si permittivity, and Cox is the insulator capacitance, ND is the substrate doping. The integration limits span from the valence band edge Ev to the conductance band edge Ec, and Ef is the Fermi level.The electron occupation of the surface states at the surface potential values Ψ<sup>s</sup> and Ψ<sup>s</sup> � ΔE=q is described by the Fermi functions f <sup>o</sup>ðEÞ and f <sup>1</sup>ðEÞ. As the pulse amplitude is small, the occupancy of the surface states can be approximated by the δ function, and Eq. (4) can be written as the capacitance of a discrete level.

$$
\Delta \mathbf{C} = A N\_s(E\_t) \left[ \mathbf{e}^{\left(-\frac{t\_1}{\tau\_\mathbf{n}(\vec{t}\_t)}\right)} - \mathbf{e}^{\left(-\frac{t\_2}{\tau\_\mathbf{n}(\vec{t}\_t)}\right)} \right] \tag{5}
$$

For a discrete level, DLTS spectrum peaks at

$$
\tau\_n = \frac{t\_2 - t\_1}{\ln(\tau/t\_1)}\tag{6}
$$

The emission time constant is expressed as

$$\pi\_n = \left[\sigma\_{\rm flt} \cdot \mathbf{N}\_c \cdot \sigma\_n \mathbf{e}^{(-\Delta \mathbf{E}\_l/kT)}\right]^{-1} \text{.} \tag{7}$$

where vth is the thermal velocity of electrons, Nc <sup>¼</sup> NDeðqVf <sup>=</sup>kT<sup>Þ</sup> is the effective density of states in the conduction band, σ<sup>s</sup> is the capture cross section for electrons, and ΔEt is the activation energy.

Assuming a capture cross section is exponentially dependent on energy

$$
\sigma\_n = \sigma\_0 e^{-\Delta \mathbb{E}\_v/kT} \,\prime \,\tag{8}
$$

with σ<sup>0</sup> and ΔE<sup>σ</sup> being the preexponential factor and the activation energy, respectively, a set of the capture cross sections at different energies can be expressed as

$$
\sigma\_n(E\_{t\prime}\mid T) = \sigma\_0(E\_t) e^{\left(-\Delta E\_\sigma(E\_t)/kT\right)}.\tag{9}
$$

The apparent activation energy and the energy-dependent term σ0ðEtÞ can be determined from the Arrhenius plot. Repeating the DLTS measurements at different gate voltages (i.e., different surface potentials), one obtains σ0ðEtÞ. The surface potential values can be determined from CV curves. The doping density and the oxide capacitance are estimated from the CV curves under the inversion and the accumulation, respectively.

In DLTS measurements, the bias dependence of the peak is a distinct signature of the charge carrier emission from the interface states [117]. Being characterized by DLTS and CV measurements, the oxide charge, the interface state densities, and capture cross sections in the energy gap can be utilized to obtain surface recombination velocities [118]. Applying DLTS pulses of opposite polarity (from accumulation to inversion) allows estimating the thermal generation times of bulk and surface centers [119]. DLTS techniques are capable in determining the trap properties in terms of relaxation mechanism and the defect profiling, the information valuable to study defects introduced by ion beams and ionizing radiation [100]. Naturally, characterization approaches are purpose-specific and can be based on several experimental techniques to identify a particular defect or study its energetics and kinetics. For example, commonly used techniques for studying the electrical- and optical characteristics of point defects such as DLTS and photoluminescence are sensitive to the defect states within the bandgap but have to be complemented by ESR studies to obtain information on the atomic structure of a defect or a defect complex.

### 4.4. Photoinjection

ΔC ¼ A

84 Ion Implantation - Research and Application

For a discrete level, DLTS spectrum peaks at

The emission time constant is expressed as

energy.

ðEc Ev

electrons when considering n-type semiconductor. A constant A= С<sup>3</sup>

NsðEÞ e

by the δ function, and Eq. (4) can be written as the capacitance of a discrete level.

<sup>Δ</sup><sup>C</sup> <sup>¼</sup> ANsðEt<sup>Þ</sup> <sup>e</sup> � <sup>t</sup>

τ<sup>n</sup> ¼ ½vth � Nc � σne

σ<sup>n</sup> ¼ σ0e

σnðEt, TÞ ¼ σ0ðEtÞe

Assuming a capture cross section is exponentially dependent on energy

the capture cross sections at different energies can be expressed as

the inversion and the accumulation, respectively.

�t 1 <sup>τ</sup><sup>n</sup> � e �t 2 τn h i

where NS(E) is the surface state density at energy E, τ<sup>n</sup> is the emission time constant for

capacitance at reverse bias, ε<sup>s</sup> is the Si permittivity, and Cox is the insulator capacitance, ND is the substrate doping. The integration limits span from the valence band edge Ev to the conductance band edge Ec, and Ef is the Fermi level.The electron occupation of the surface states at the surface potential values Ψ<sup>s</sup> and Ψ<sup>s</sup> � ΔE=q is described by the Fermi functions f <sup>o</sup>ðEÞ and f <sup>1</sup>ðEÞ. As the pulse amplitude is small, the occupancy of the surface states can be approximated

> 1 τnðEtÞ � �

<sup>τ</sup><sup>n</sup> <sup>¼</sup> <sup>t</sup><sup>2</sup> � <sup>t</sup><sup>1</sup>

where vth is the thermal velocity of electrons, Nc <sup>¼</sup> NDeðqVf <sup>=</sup>kT<sup>Þ</sup> is the effective density of states in the conduction band, σ<sup>s</sup> is the capture cross section for electrons, and ΔEt is the activation

with σ<sup>0</sup> and ΔE<sup>σ</sup> being the preexponential factor and the activation energy, respectively, a set of

The apparent activation energy and the energy-dependent term σ0ðEtÞ can be determined from the Arrhenius plot. Repeating the DLTS measurements at different gate voltages (i.e., different surface potentials), one obtains σ0ðEtÞ. The surface potential values can be determined from CV curves. The doping density and the oxide capacitance are estimated from the CV curves under

�

�ΔEσðEtÞ=kT

�

� <sup>e</sup> � <sup>t</sup> 2 τnðEtÞ

" # � �

ð�ΔEt=kTÞ � �1

½f <sup>0</sup>ðEÞ � f <sup>1</sup>ðEÞ�dE, ð4Þ

ln <sup>t</sup>2=<sup>t</sup><sup>1</sup> ð Þ <sup>ð</sup>6<sup>Þ</sup>

�ΔEσ<sup>=</sup>kT, <sup>ð</sup>8<sup>Þ</sup>

, ð7Þ

: ð9Þ

<sup>0</sup>=εsCoxND, where C<sup>0</sup> is a

ð5Þ

The methods based on photoinjection of charge carriers in metal-semiconductor barrier structures are sensitive to local nonuniformities in semiconductor interfaces because charge in a semiconductor induces an equal charge in the electrodes giving rise to electric fields at the interfaces, with a consequent field-effect modulation of the barrier heights (for the all-encompassing review on the subject of internal photoemission spectroscopy (IPE) methods one can refer to the book [120]). The early application of scanning internal photoemission to map sodium contamination at the Si/SiO2 interface has been reported in work [121]. The IPE and trap photodepopulation methods were applied to reveal electron traps in Na+ and Al+ implanted SiO2 [122]. At present, this technique has been revived to study ion beam induced charge nonuniformities in GaN and SiC [123].

Experimentally, the charge injected into an oxide, i.e., the current over the time of injection should remain unchanged by the method used for the charge detection. The trapped charge density is determined sensing the electric field created by the trapped charge. The electric field created by the charge of trapped carriers can be also observed in variations of the surface band bending of a semiconductor, i.e., a semiconductor space-charge layer serves as the field-sensing element. The band bending as a function of electric field can be extracted from capacitancevoltage measurements and the additional contribution of trapped charge to the field can be determined as a voltage shift of a CV curve. In MOSFETs, the trapped charge can be monitored as a function of the threshold voltage. This technique senses the charge carrier density in the inversion channel to monitor the electric field at the SI interface. Alternatively, the electric field induced by the trapped charge can be monitored by the Kelvin probe or photovoltage. In the latter case, the light intensity should be sufficient to set the flat band conditions at the semiconductor surface.

The experimental studies of the trapped charge in ion-implanted insulators are numerous with several examples represented in Refs. [124–131]. The interfacial defect densities modified by ion implantation have been studied combining IPE and ac conductance spectroscopy methods on nitrogen implanted SiC/SiO2interfaces [132]. IPE reveals that nitrogen incorporates in carbon clusters at the SiC/SiO2 interface that causes a shift of the electron levels to higher binding energies. Inferring the Schottky barrier height from the IPE spectra, it has been shown that ion implantation of sulfur in the NiSi/Si barrier does not induce changes in the barrier height, but increases doping in silicon [133]. The silicide/Si barrier modification by intentional dopant segregation has been verified in work [134].

#### 4.5. Slow interface states as a special case of study

Defects generated by ionizing radiation and/or electric field, as well as the defects in undamaged devices, are considered to be spatially distributed across the SI interface and can be classified accordingly to the spatial location as the oxide-related traps and the interface traps. In respect to the latter, it is generally accepted that the interface traps are rapidly communicating with the silicon conduction or valence bands. The defects within the oxide interlayer also can exchange charge with silicon as has been revealed by the noise measurements [135]. Combining ac admittance spectroscopy and the noise measurements, it has been established that the fast interface states at the Si/SiO2 interface, likely associated with the dangling bond defects, contribute to the loss peak in conductance measurements [136]. The defect states residing in an oxide layer are responsible for 1/f noise and random telegraph noise. These trapping centers in the oxide contribute to the conductance plateau at low frequency in ac conductance spectra (cf. Figure 2 of Ref. [137]). A separable contribution of the oxide-related traps has been revealed employing measurements of subthreshold current [138] and the charge-pumping technique [139] to MOSFETs and CV measurements taken on the gate-controlled diode [140]. The latter technique is applicable for characterization of the interface traps in MOS devices composed on wide band gap semiconductors, because it allows supplying minority carriers in an amount sufficient to compensate for the low thermal generation rates of the minority carriers. An alternative method of providing minority carriers to invert a semiconductor surface is a controlled deposition of surface charges onto an insulator surface from corona discharging in air as it has been proposed in Ref. [141]. In this work, a surface charge has been deposited on SiO2 and high-k dielectrics to overcompensate the carrier leakage current in silicon MOS capacitors and enable extraction of Dit(E) profiles following the Berglund formalism. There are several advantages of the inverting semiconductor surfaces by employing noninvasive electrostatic charging of an insulator surface in a MOS structure: (i) The method does not involve fabrication of a transistor or a gate-controlled diode. (ii) The Berglund analysis can be used to reliably estimate Dit(E) over the major part of a semiconductor band gap (for Si, from 0.2 to 0.9 eV above the valence band edge) using just MOS capacitors of one type of semiconductor conductivity. (iii) The method may employ CV measurements at mid-kHz frequency range allowing investigation of samples, which experience relatively high leakage current.

The sub-division of the interface trap responses into slow and fast on the basis of their characteristic time constants is important in research on the irradiation-induced damage in MOS devices. The interface state generation under irradiation or high electric field stress can involve electron-

hole recombination in a gate insulator as proposed by Lai [142], the hole trapping according to the "hydrogen model" by Griscom [60], or generation of dangling bond defects in the oxide. Experimentally, it has been shown that both the fast and slow interface states can be generated upon oxide damage by high electric field or irradiation [143]. The mechanisms operative in the interface trap built-up upon irradiation or electric field stress are governed by hydrogen impurity, interfacial strain preexisting in thin insulating films on semiconductors, and experimental conditions used to impose damage on MOS devices.
