**Applications**

**Chapter 5**

Provisional chapter

**Operational Amplifier Design in CMOS at Low-Voltage**

DOI: 10.5772/intechopen.68815

Operational Amplifier Design in CMOS at Low-Voltage

Today, digital circuit cores provide the main circuit implementation approach for integrated circuit (IC) functions in very-large-scale integration (VLSI) circuits and systems. Typical functions include sensor signal input, data storage, digital signal processing (DSP) operations, system control and communications. Despite the fact that a large portion of the circuitry may be developed and implemented using digital logic techniques, there is still a need for high performance analogue circuits such as amplifiers and filters that provide signal conditioning functionality prior to sampling into the digital domain using an analogue-to-digital converter (ADC) for analogue sensor signals. The demands on the design require a multitude of requirements to be taken into account. In this chapter, the design of the operational amplifier (op-amp) is discussed as an important circuit within the front-end circuitry of a mixed-signal IC. The discussion will focus on the design of the op-amp using different compensation schemes incorporating negative Miller compensation and designed to operate at lower power supply voltage levels. A design case study is included which utilises the gm/ID ratio design approach to determine the transistor sizes. The simulation approach is focussed on the open-loop

Keywords: op-amp, design, stability, gm/ID, Miller compensation, negative Miller

In this chapter, the focus of the discussion is on the design of the op-amp, which will act as an integral part of the on-chip analogue signal conditioning circuitry for the front-end section of a

> © The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

**for Sensor Input Front-End Circuits in VLSI Devices**

for Sensor Input Front-End Circuits in VLSI Devices

Muhaned Zaidi, Ian Grout and Abu Khari A'ain

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

frequency response performance of the op-amp.

http://dx.doi.org/10.5772/intechopen.68815

Muhaned Zaidi, Ian Grout and

Abu Khari A'ain

Abstract

compensation

1. Introduction

#### **Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices** Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

DOI: 10.5772/intechopen.68815

Muhaned Zaidi, Ian Grout and Abu Khari A'ain Muhaned Zaidi, Ian Grout and

Additional information is available at the end of the chapter Abu Khari A'ain

http://dx.doi.org/10.5772/intechopen.68815 Additional information is available at the end of the chapter

#### Abstract

Today, digital circuit cores provide the main circuit implementation approach for integrated circuit (IC) functions in very-large-scale integration (VLSI) circuits and systems. Typical functions include sensor signal input, data storage, digital signal processing (DSP) operations, system control and communications. Despite the fact that a large portion of the circuitry may be developed and implemented using digital logic techniques, there is still a need for high performance analogue circuits such as amplifiers and filters that provide signal conditioning functionality prior to sampling into the digital domain using an analogue-to-digital converter (ADC) for analogue sensor signals. The demands on the design require a multitude of requirements to be taken into account. In this chapter, the design of the operational amplifier (op-amp) is discussed as an important circuit within the front-end circuitry of a mixed-signal IC. The discussion will focus on the design of the op-amp using different compensation schemes incorporating negative Miller compensation and designed to operate at lower power supply voltage levels. A design case study is included which utilises the gm/ID ratio design approach to determine the transistor sizes. The simulation approach is focussed on the open-loop frequency response performance of the op-amp.

Keywords: op-amp, design, stability, gm/ID, Miller compensation, negative Miller compensation

### 1. Introduction

In this chapter, the focus of the discussion is on the design of the op-amp, which will act as an integral part of the on-chip analogue signal conditioning circuitry for the front-end section of a

Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

mixed-signal IC. The performance requirements and design issues for circuit operation on a single-rail power supply and operating at 3.3 V or lower will be considered. The op-amp architecture will be discussed, and the focus will be on the design of the compensation circuitry that will be required for amplifier stability purposes. In particular, the use of Miller and negative Miller compensation techniques, and the effects of different compensation techniques on amplifier operation, will be identified. The discussion will be supported using suitable simulation study results. The chapter will initially consider the analogue circuit requirements before discussing op-amp design and compensation techniques. The concepts introduced and analysed will be accompanied by analogue circuit simulation results using Cadence Spectre simulator and the circuit design will be implemented using a 0.35 µm n-well complementary metal oxide semiconductor (CMOS) fabrication process. In order to provide a better understanding, the discussion will include the use of MATLAB for mathematical modelling the frequency response of the op-amp in open loop.

hardware and software operations. The choice of the electronics in the digital processing module in many cases is based on using either software programmable devices such as the microcontroller (µC), microprocessor (µP) and digital signal processor (DSP), or hardware configurable devices such as the field programmable gate array (FPGA) and complex programmable logic device (CPLD). However, the alternative that involves the design of a custom integrated circuit would be based on application specific integrated circuit (ASIC) design techniques. Designing such ASICs would enable a custom design to be created and higher levels of integration that result in physically smaller electronics and the integration of digital, analogue and mixed-signal circuits within a single packaged device. Considering the analogue sensor part of the system, the signal output from the sensor would normally need to be modified (conditioned) in order to provide signal levels that can be sampled by the digital signal-processing module via a suitable

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Such signal conditioning operations include signal amplification, DC level shifting and antialiasing filtering (low-pass filtering to remove any high frequency signal components that would be aliased to lower frequencies). In general, these signal conditioning circuits are based on the use of the op-amp with negative feedback using external resistors and capacitors. However, the operating conditions of the op-amp such as the power supply voltage level would need to be taken into account when either selecting an existing op-amp to use or when designing the op-amp itself. The performance of the op-amp in these types of signal conditioning circuits would be a key factor in what performance could be achieved with the circuits used. In the past, the power supply voltage would not have been a major factor in determining the op-amp performance. The power supply voltage would have been at levels that enabled the op-amp circuitry to operate without encountering power supply voltage limitation issues. With the move towards lower power supply voltage levels at, and below 3.3 V operation, and moving towards 1 V system operation, the power supply conditions must now be accounted for. The op-amp circuit architectures along with circuit design approaches must be reconsidered in order to enable these op-amps to be designed with appropriate characteristics for low-voltage operation.

The op-amp is a high-gain DC differential amplifier that is the core building block for many analogue circuits. In general, it consists of two or more amplification stages using transistors, integrated capacitors and in some designs, integrated resistors. Figure 2 identifies the basic symbol for the voltage input/voltage output op-amp, which has two inputs (the inverting (IN) and non-inverting (IN+) inputs), a DC power supply (V + and V) and either one output (a single-ended output (a)) or two outputs (a differential output (b)). The op-amp is designed to have certain characteristics that include a high open-loop differential gain (AOL), a high gainbandwidth product, a high input resistance, a low output resistance, a low output offset voltage, a high dynamic range (minimum to maximum signal range) and a high common-mode rejection ratio (CMRR) [1]. The op-amps shown in Figure 2 identify the circuits in open loop without any

ADC, which converts the analogue signal to a digital representation.

3. Conventional op-amp design approach

3.1. Introduction

### 2. Analogue front end circuits in mixed-signal IC designs

Today, electronic systems are embedded in everyday items such as smart phones, mobile computing, biomedical monitoring (bioinstrumentation) systems, entertainment systems and environmental monitoring systems. In many cases, these systems are based on capturing sensor signals, processing and converting them to a suitable digital representation, undertaking digital signal processing (DSP) operations, storing values in local memory, interfacing to a user and finally providing wired or wireless communications to another electronic system. The basic idea is shown in Figure 1. The sensors can provide either analogue outputs (such as voltage, current, frequency and impedance) or digital outputs (logic 0 and 1 levels with associated voltage values). In general, the sensor output signals would require signal conditioning in order to create signal values that are in a suitable form to be captured by a digital processing module. This digital processing module would provide the necessary functions in hardware only or as a mixture of

Figure 1. Sensor signal sampling and digital signal processing.

hardware and software operations. The choice of the electronics in the digital processing module in many cases is based on using either software programmable devices such as the microcontroller (µC), microprocessor (µP) and digital signal processor (DSP), or hardware configurable devices such as the field programmable gate array (FPGA) and complex programmable logic device (CPLD). However, the alternative that involves the design of a custom integrated circuit would be based on application specific integrated circuit (ASIC) design techniques. Designing such ASICs would enable a custom design to be created and higher levels of integration that result in physically smaller electronics and the integration of digital, analogue and mixed-signal circuits within a single packaged device. Considering the analogue sensor part of the system, the signal output from the sensor would normally need to be modified (conditioned) in order to provide signal levels that can be sampled by the digital signal-processing module via a suitable ADC, which converts the analogue signal to a digital representation.

Such signal conditioning operations include signal amplification, DC level shifting and antialiasing filtering (low-pass filtering to remove any high frequency signal components that would be aliased to lower frequencies). In general, these signal conditioning circuits are based on the use of the op-amp with negative feedback using external resistors and capacitors. However, the operating conditions of the op-amp such as the power supply voltage level would need to be taken into account when either selecting an existing op-amp to use or when designing the op-amp itself. The performance of the op-amp in these types of signal conditioning circuits would be a key factor in what performance could be achieved with the circuits used. In the past, the power supply voltage would not have been a major factor in determining the op-amp performance. The power supply voltage would have been at levels that enabled the op-amp circuitry to operate without encountering power supply voltage limitation issues. With the move towards lower power supply voltage levels at, and below 3.3 V operation, and moving towards 1 V system operation, the power supply conditions must now be accounted for. The op-amp circuit architectures along with circuit design approaches must be reconsidered in order to enable these op-amps to be designed with appropriate characteristics for low-voltage operation.

### 3. Conventional op-amp design approach

### 3.1. Introduction

mixed-signal IC. The performance requirements and design issues for circuit operation on a single-rail power supply and operating at 3.3 V or lower will be considered. The op-amp architecture will be discussed, and the focus will be on the design of the compensation circuitry that will be required for amplifier stability purposes. In particular, the use of Miller and negative Miller compensation techniques, and the effects of different compensation techniques on amplifier operation, will be identified. The discussion will be supported using suitable simulation study results. The chapter will initially consider the analogue circuit requirements before discussing op-amp design and compensation techniques. The concepts introduced and analysed will be accompanied by analogue circuit simulation results using Cadence Spectre simulator and the circuit design will be implemented using a 0.35 µm n-well complementary metal oxide semiconductor (CMOS) fabrication process. In order to provide a better understanding, the discussion will include the use of MATLAB for mathematical modelling the frequency response of the op-amp in

Today, electronic systems are embedded in everyday items such as smart phones, mobile computing, biomedical monitoring (bioinstrumentation) systems, entertainment systems and environmental monitoring systems. In many cases, these systems are based on capturing sensor signals, processing and converting them to a suitable digital representation, undertaking digital signal processing (DSP) operations, storing values in local memory, interfacing to a user and finally providing wired or wireless communications to another electronic system. The basic idea is shown in Figure 1. The sensors can provide either analogue outputs (such as voltage, current, frequency and impedance) or digital outputs (logic 0 and 1 levels with associated voltage values). In general, the sensor output signals would require signal conditioning in order to create signal values that are in a suitable form to be captured by a digital processing module. This digital processing module would provide the necessary functions in hardware only or as a mixture of

2. Analogue front end circuits in mixed-signal IC designs

Figure 1. Sensor signal sampling and digital signal processing.

open loop.

114 Very-Large-Scale Integration

The op-amp is a high-gain DC differential amplifier that is the core building block for many analogue circuits. In general, it consists of two or more amplification stages using transistors, integrated capacitors and in some designs, integrated resistors. Figure 2 identifies the basic symbol for the voltage input/voltage output op-amp, which has two inputs (the inverting (IN) and non-inverting (IN+) inputs), a DC power supply (V + and V) and either one output (a single-ended output (a)) or two outputs (a differential output (b)). The op-amp is designed to have certain characteristics that include a high open-loop differential gain (AOL), a high gainbandwidth product, a high input resistance, a low output resistance, a low output offset voltage, a high dynamic range (minimum to maximum signal range) and a high common-mode rejection ratio (CMRR) [1]. The op-amps shown in Figure 2 identify the circuits in open loop without any

Figure 2. Single-ended output and differential output op-amps.

external feedback components from the output signal back to the input signal. The op-amp, therefore, would have a set of open-loop characteristics. In general, the op-amp would be designed to operate in closed loop where feedback components, primarily resistors and capacitors are used to provide either negative (linear operations) or positive (non-linear operations) feedback.

The three defined regions of operation are cut-off, linear and saturation where:

the transistor threshold voltage (VT) in this region.

Figure 3. Large-signal IV characteristic of the MOSFET.

linearly with increasing drain-source voltage.

with the drain-source channel in strong inversion.

signal equivalent circuit model for the MOSFET is shown in Figure 4.

3.4. Small-signal model

Cut-off region: Cut-off is a region in which the transistor will be OFF, and there will be no current flow from the drain to the source (iD (cut-off) = 0). The gate-source voltage is less than

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Linear or ohmic or non-saturation region: In this region, the gate-source voltage is larger than, or equal to, VT and the drain-source voltage larger than zero but less than the saturation (pinch-off) voltage (vDSsat = (vGS–VT)). A channel is created between the drain and source terminals, and there is current flow from drain to source. The drain current will increase

Saturation region: In this region, the gate-source voltage is larger or equal to, the transistor threshold voltage, and drain-source voltage has reached or exceeds, vDSsat. This occurs when the channel charge becomes pinched off at the drain-channel interface, and the transistor operation is now in the saturation region. In the simplest (first order) transistor model, increases in vDS do not cause an increase in iD and so iD becomes independent of vDS. However, a more representative model includes an iD dependence on the value of vDS. Moreover, the transistor operation depends on the gate overdrive voltage (veff = (vGS–VT))

Although the transistor is a non-linear device, for circuit analysis purposes when developing linear circuits, a linear model for the transistor operating in the saturation region at a specified DC operating (bias) point is initially created. This then describes the behaviour of the transistor to small-signal changes around the bias point, and the small-signal model is then used to determine AC gain values. The signal changes are considered to be small so enabling the approximation that the transistor operation is linear around this DC operating point to be valid. Moreover, defining the small-signal behaviour of the transistor as a transfer function, the transconductance (gm), and output conductance (go) is required model parameters. The small-

In the discussion within this chapter, CMOS fabrication process is considered as it is the most widely used fabrication process to realise VLSI ICs. The work presented here will focus on CMOS op-amp circuit design considerations, particularly the AC (frequency) response and stability. The standard topology for the single-ended output two-stage op-amp is considered, and the behaviour of an example case study design will be presented.

### 3.2. Metal oxide semiconductor field effect transistor

The metal oxide semiconductor field effect transistor (MOSFET) is the most widely used semiconductor device. It is a non-linear device that has four terminals: the drain, source, gate and bulk (or body, substrate). Two forms of MOSFET can be created: the n-channel (nMOS) and p-channel (pMOS) [2]. With these transistors, a voltage between the gate and the source (vgs) controls the flow of drain current (id). To design circuits using these devices, it is necessary to know their current-voltage (IV) characteristics. In conventional circuit design, the transistor is usually modelled using two discrete models to mathematically describe the IV characteristics: a large-signal and a small-signal model. Each model would be used for different design and analysis purposes.

### 3.3. Large-signal model

A curve that describes the large-signal IV characteristic is shown in Figure 3. The operation of the transistor is modelled using three different regions according to the values of the gatesource voltage (vGS) and the drain-source voltage (vDS). This models the MOSFET drain current (iD) against vDS with different values of vGS.

Figure 3. Large-signal IV characteristic of the MOSFET.

external feedback components from the output signal back to the input signal. The op-amp, therefore, would have a set of open-loop characteristics. In general, the op-amp would be designed to operate in closed loop where feedback components, primarily resistors and capacitors are used to provide either negative (linear operations) or positive (non-linear operations)

In the discussion within this chapter, CMOS fabrication process is considered as it is the most widely used fabrication process to realise VLSI ICs. The work presented here will focus on CMOS op-amp circuit design considerations, particularly the AC (frequency) response and stability. The standard topology for the single-ended output two-stage op-amp is considered,

The metal oxide semiconductor field effect transistor (MOSFET) is the most widely used semiconductor device. It is a non-linear device that has four terminals: the drain, source, gate and bulk (or body, substrate). Two forms of MOSFET can be created: the n-channel (nMOS) and p-channel (pMOS) [2]. With these transistors, a voltage between the gate and the source (vgs) controls the flow of drain current (id). To design circuits using these devices, it is necessary to know their current-voltage (IV) characteristics. In conventional circuit design, the transistor is usually modelled using two discrete models to mathematically describe the IV characteristics: a large-signal and a small-signal model. Each model would be used for different design

A curve that describes the large-signal IV characteristic is shown in Figure 3. The operation of the transistor is modelled using three different regions according to the values of the gatesource voltage (vGS) and the drain-source voltage (vDS). This models the MOSFET drain current

and the behaviour of an example case study design will be presented.

3.2. Metal oxide semiconductor field effect transistor

Figure 2. Single-ended output and differential output op-amps.

feedback.

116 Very-Large-Scale Integration

and analysis purposes.

3.3. Large-signal model

(iD) against vDS with different values of vGS.

The three defined regions of operation are cut-off, linear and saturation where:

Cut-off region: Cut-off is a region in which the transistor will be OFF, and there will be no current flow from the drain to the source (iD (cut-off) = 0). The gate-source voltage is less than the transistor threshold voltage (VT) in this region.

Linear or ohmic or non-saturation region: In this region, the gate-source voltage is larger than, or equal to, VT and the drain-source voltage larger than zero but less than the saturation (pinch-off) voltage (vDSsat = (vGS–VT)). A channel is created between the drain and source terminals, and there is current flow from drain to source. The drain current will increase linearly with increasing drain-source voltage.

Saturation region: In this region, the gate-source voltage is larger or equal to, the transistor threshold voltage, and drain-source voltage has reached or exceeds, vDSsat. This occurs when the channel charge becomes pinched off at the drain-channel interface, and the transistor operation is now in the saturation region. In the simplest (first order) transistor model, increases in vDS do not cause an increase in iD and so iD becomes independent of vDS. However, a more representative model includes an iD dependence on the value of vDS. Moreover, the transistor operation depends on the gate overdrive voltage (veff = (vGS–VT)) with the drain-source channel in strong inversion.

#### 3.4. Small-signal model

Although the transistor is a non-linear device, for circuit analysis purposes when developing linear circuits, a linear model for the transistor operating in the saturation region at a specified DC operating (bias) point is initially created. This then describes the behaviour of the transistor to small-signal changes around the bias point, and the small-signal model is then used to determine AC gain values. The signal changes are considered to be small so enabling the approximation that the transistor operation is linear around this DC operating point to be valid. Moreover, defining the small-signal behaviour of the transistor as a transfer function, the transconductance (gm), and output conductance (go) is required model parameters. The smallsignal equivalent circuit model for the MOSFET is shown in Figure 4.

Figure 4. MOSFET small-signal equivalent circuit model.

However, if the signal level is increased, the transistor operation becomes non-linear and will represent by the large-signal model. The conventional analogue design method for the op-amp considers the use of the transistor operating in the saturation region and the drain-source channel to be in strong inversion. This requires the circuit voltage levels (and hence the power supply voltage) to be of suitably high levels to ensure that the transistor remains in saturation and strong inversion for linear circuit operation. Analogue CMOS integrated circuit design needs to use a suitable technology to determine MOSFET dimensions and create the required circuit performance. However, today, when developing circuit designs based on using MOSFETs at low-power and low-voltage, the small-signal and large-signal models are no longer suitable to define transistor operation.

#### 3.5. Example two-stage CMOS op-amp design

The op-amp circuit can be based on different architectures, and each architecture provides advantages in operation when compared to other architectures. In the design considered in this chapter, the two-stage CMOS operational amplifier is used with a simplified architecture as shown in Figure 5. Two amplification stages are used, the first stage providing high voltage gain and the second stage providing additional voltage gain and a large output signal swing. In addition, each stage uses negative feedback frequency compensation to improve stability and bandwidth. Negative Miller compensation is applied around the first stage using two identical capacitors (CNM), and Miller compensation is applied around the second stage using two identical capacitors (CM). The circuit schematic of the selected op-amp architecture is shown in Figure 6. Note how the signals between the first stage and the second stage are connected and how the actual circuit connections differ from the simplified architecture (Figure 5). The first stage consists of a transconductance stage with differential input transistors PM1 and PM2 followed by folded cascode (FC) stage. The mirror connected transistors NM5 and NM6 in the folded cascode sum the input transistors differential current. The current sources PM8 and PM9 on the upper side must provide a current larger than the bias current for each input transistor.

The second stage is a class AB amplifier, and the single-ended output comes from transistors PM17 and NM14. The second stage is primarily used to provide a large output voltage swing (rail-to-rail output) with high DC voltage gain. NM10 and PM13 perform the feed-forward class-AB control. These transistors are biased by two in-phase signal currents using the two cascode transistors NM8 and PM11. The gate voltages for these two transistors are kept at a constant value using the stacked diode-connected transistors (PM14, PM15 and NM11, NM12). The floating current source (PM12 and PM13) has the same structure as the feed-forward

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Figure 5. Two-stage op-amp case study design simplified architecture.

Figure 6. Two-stage op-amp design case study design schematic.

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices http://dx.doi.org/10.5772/intechopen.68815 119

Figure 5. Two-stage op-amp case study design simplified architecture.

However, if the signal level is increased, the transistor operation becomes non-linear and will represent by the large-signal model. The conventional analogue design method for the op-amp considers the use of the transistor operating in the saturation region and the drain-source channel to be in strong inversion. This requires the circuit voltage levels (and hence the power supply voltage) to be of suitably high levels to ensure that the transistor remains in saturation and strong inversion for linear circuit operation. Analogue CMOS integrated circuit design needs to use a suitable technology to determine MOSFET dimensions and create the required circuit performance. However, today, when developing circuit designs based on using MOSFETs at low-power and low-voltage, the small-signal and large-signal models are no longer suitable to

The op-amp circuit can be based on different architectures, and each architecture provides advantages in operation when compared to other architectures. In the design considered in this chapter, the two-stage CMOS operational amplifier is used with a simplified architecture as shown in Figure 5. Two amplification stages are used, the first stage providing high voltage gain and the second stage providing additional voltage gain and a large output signal swing. In addition, each stage uses negative feedback frequency compensation to improve stability and bandwidth. Negative Miller compensation is applied around the first stage using two identical capacitors (CNM), and Miller compensation is applied around the second stage using two identical capacitors (CM). The circuit schematic of the selected op-amp architecture is shown in Figure 6. Note how the signals between the first stage and the second stage are connected and how the actual circuit connections differ from the simplified architecture (Figure 5). The first stage consists of a transconductance stage with differential input transistors PM1 and PM2 followed by folded cascode (FC) stage. The mirror connected transistors NM5 and NM6 in the folded cascode sum the input transistors differential current. The current sources PM8 and PM9 on the upper side must provide a

The second stage is a class AB amplifier, and the single-ended output comes from transistors PM17 and NM14. The second stage is primarily used to provide a large output voltage swing

define transistor operation.

118 Very-Large-Scale Integration

3.5. Example two-stage CMOS op-amp design

Figure 4. MOSFET small-signal equivalent circuit model.

current larger than the bias current for each input transistor.

Figure 6. Two-stage op-amp design case study design schematic.

(rail-to-rail output) with high DC voltage gain. NM10 and PM13 perform the feed-forward class-AB control. These transistors are biased by two in-phase signal currents using the two cascode transistors NM8 and PM11. The gate voltages for these two transistors are kept at a constant value using the stacked diode-connected transistors (PM14, PM15 and NM11, NM12). The floating current source (PM12 and PM13) has the same structure as the feed-forward

class-AB control. The compensation circuitry is split into two parts. Miller compensation around the second stage provides op-amp stability. The op-amp has two Miller capacitors around the class-AB amplifier. Negative Miller compensation around the first stage is provided the extended the bandwidth (increases the unity gain frequency) and also uses two capacitors.

layout, along with external components, will contribute to the potential for instability when the op-amp is used in a closed-loop configuration, for example, when the op-amp is used in a unity gain buffer configuration. One common way to predict the closed-loop stability of an amplifier is by determining the PM of the open-loop gain response. The PM must be greater than 0� to prevent negative feedback becoming positive feedback thus creating signal oscillation rather than signal amplification. To determine PM at the unity gain frequency, the differ-

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

where θ is the phase shift of the output signal in degrees (referenced to 0�) when the gain magnitude is unity (0 dB). It is commonly considered that an op-amp in open-loop will require a phase margin of 45� or higher. The GM (in dB) is the difference between the gain magnitude

Given the complexity of the input-output relationship of the op-amp, it is common to model the op-amp input-output behaviour in terms of a transfer function for analysis purposes. Typically, a Laplace transfer function is created to model the frequency response and the response is viewed using a Bode plot. The transfer function provides a form for determining important system response characteristics (without solving the complete set of differential

The roots of the numerator N(s) (zx) are called the zeros of the transfer function, and the roots of the denominator D(s) (py) are called as the poles of the transfer function. S is a complex frequency. It is often suitable to factor the polynomials in the numerator and denominator so

This form of equation directly identifies the system poles and zeros. Using the transfer function characteristics, the Bode plot is a particularly useful tool to visualise the frequency response for analysis purposes. However, with the complexity of the networks formed by the circuit (i.e. the connection of the transistors) and the compensation structures, any system transfer functions that can be derived from the frequency response of the actual circuit to mathematically model the op-amp behaviour rapidly becomes complex. The result is a transfer function with multiple poles and zeros to consider with a complexity that cannot be easy investigated using hand calculations. Hand calculations usually utilise a simplified transfer function, using a form with the most dominant two or three poles, and a full analysis would require the use of a suitable analogue circuit simulator (typically SPICE based) and

<sup>P</sup>ðs<sup>Þ</sup> <sup>¼</sup> <sup>K</sup>: <sup>ð</sup><sup>s</sup> � <sup>z</sup>1Þ:ð<sup>s</sup> � <sup>z</sup>2Þ…ð<sup>s</sup> � zm<sup>Þ</sup>

<sup>ð</sup><sup>s</sup> � <sup>p</sup>1Þð<sup>s</sup> � <sup>p</sup>2Þ…ð<sup>s</sup> � pn<sup>Þ</sup> <sup>ð</sup>5<sup>Þ</sup>

PM ¼ ð1800 � jθjÞ at the unity gain f requency <sup>ð</sup>2<sup>Þ</sup>

http://dx.doi.org/10.5772/intechopen.68815

GM ¼ ð<sup>0</sup> dB � Gain magnitude <sup>ð</sup>in dBÞÞ at <sup>180</sup><sup>o</sup> phase shif t <sup>ð</sup>3<sup>Þ</sup>

<sup>¼</sup> ams<sup>m</sup> <sup>þ</sup> am�<sup>1</sup>sðm�1<sup>Þ</sup> <sup>þ</sup> … <sup>þ</sup> <sup>a</sup>2<sup>s</sup> <sup>þ</sup> … <sup>þ</sup> ao bnsn þ bn�<sup>1</sup>sðn�1<sup>Þ</sup> þ … þ b2s þ … þ bo

ð4Þ

121

ence between the amount of signal phase shift and 180� is determined:

at 180� phase shift and the unity gain magnitude (i.e. 0 dB):

<sup>H</sup>ðsÞ ¼ <sup>N</sup>ðs<sup>Þ</sup> DðsÞ

<sup>H</sup>ðsÞ ¼ <sup>Z</sup>ðs<sup>Þ</sup>

that the transfer function then becomes:

equations) in the form:

### 4. Op-amp stability and compensation techniques

### 4.1. Introduction

The reason for considering stability in a circuit design is to ensure that the circuit remains stable under the required operating conditions. Instability occurs when the op-amp is configured with negative feedback, and under certain conditions, the negative feedback becomes positive. In the unstable case, the circuit output then oscillates. Stability under any input condition is referred to as unconditionally stable, or absolutely stable [3]. However, if a system is not unconditionally stable, a margin of stability must be built-in to ensure stable operation under the required operating conditions. To achieve stable op-amp operation in closed-loop, the designer can add a capacitance between specific nodes within the op-amp that deliberately reduces the open-loop gain magnitude at higher signal frequencies. This technique, referred to as compensation, is implemented by typically bypassing one of the internal op-amp gain stages with a high-pass filter. In the simplest sense, a capacitor is connected between the output and input nodes of a gain stage. The purpose is to decrease the gain magnitude to less than unity at frequencies where instability could occur. A single compensation capacitor implementation is widely used in two-stage op-amp designs. However, there are several other techniques used for the op-amp compensation. Improvements to the op-amp performance using the single capacitor compensation approach include the inclusion of a series resistor, buffer or buffer and series resistor. Other techniques, for example, use multiple feedback capacitors connected to different stages within the circuit. These techniques can be used with the two-stage op-amp. Additional techniques require the inclusion of more than two gain stages and, with decreases in integrated circuit process geometries, op-amps with more than two gain stages have become more common to achieve a sufficiently high open-loop gain. There are two common assumptions in the design of compensation topologies. First, the gain magnitude of the stage is larger than one. Second, the compensation and output load capacitance values are larger than the combined output transistor capacitances for each stage. In addition to the DC gain of the op-amp, there are four parameters of particular interest pertaining to its frequency response. These are the unity-gain bandwidth (UGB), gain-bandwidth product (GBWP), phase margin (PM) and gain margin (GM). UGB specifies the frequency at which the op-amp open-loop differential gain magnitude (|AOL|) is unity (i.e. 0 dB). GBWP defines the gain-bandwidth product of the op-amp gain magnitude and frequency (f):

$$GBWP = |A\_{OL}| \ast f\tag{1}$$

A potential problem, however, of using a multiple-stage op-amp is for unstable circuit behaviour resulting in an oscillatory output signal due to the capacitances within the op-amp circuit and signal feedback paths that exist. The transistor capacitances and parasitic effects due to layout, along with external components, will contribute to the potential for instability when the op-amp is used in a closed-loop configuration, for example, when the op-amp is used in a unity gain buffer configuration. One common way to predict the closed-loop stability of an amplifier is by determining the PM of the open-loop gain response. The PM must be greater than 0� to prevent negative feedback becoming positive feedback thus creating signal oscillation rather than signal amplification. To determine PM at the unity gain frequency, the difference between the amount of signal phase shift and 180� is determined:

class-AB control. The compensation circuitry is split into two parts. Miller compensation around the second stage provides op-amp stability. The op-amp has two Miller capacitors around the class-AB amplifier. Negative Miller compensation around the first stage is provided the extended

The reason for considering stability in a circuit design is to ensure that the circuit remains stable under the required operating conditions. Instability occurs when the op-amp is configured with negative feedback, and under certain conditions, the negative feedback becomes positive. In the unstable case, the circuit output then oscillates. Stability under any input condition is referred to as unconditionally stable, or absolutely stable [3]. However, if a system is not unconditionally stable, a margin of stability must be built-in to ensure stable operation under the required operating conditions. To achieve stable op-amp operation in closed-loop, the designer can add a capacitance between specific nodes within the op-amp that deliberately reduces the open-loop gain magnitude at higher signal frequencies. This technique, referred to as compensation, is implemented by typically bypassing one of the internal op-amp gain stages with a high-pass filter. In the simplest sense, a capacitor is connected between the output and input nodes of a gain stage. The purpose is to decrease the gain magnitude to less than unity at frequencies where instability could occur. A single compensation capacitor implementation is widely used in two-stage op-amp designs. However, there are several other techniques used for the op-amp compensation. Improvements to the op-amp performance using the single capacitor compensation approach include the inclusion of a series resistor, buffer or buffer and series resistor. Other techniques, for example, use multiple feedback capacitors connected to different stages within the circuit. These techniques can be used with the two-stage op-amp. Additional techniques require the inclusion of more than two gain stages and, with decreases in integrated circuit process geometries, op-amps with more than two gain stages have become more common to achieve a sufficiently high open-loop gain. There are two common assumptions in the design of compensation topologies. First, the gain magnitude of the stage is larger than one. Second, the compensation and output load capacitance values are larger than the combined output transistor capacitances for each stage. In addition to the DC gain of the op-amp, there are four parameters of particular interest pertaining to its frequency response. These are the unity-gain bandwidth (UGB), gain-bandwidth product (GBWP), phase margin (PM) and gain margin (GM). UGB specifies the frequency at which the op-amp open-loop differential gain magnitude (|AOL|) is unity (i.e. 0 dB). GBWP defines the gain-bandwidth

A potential problem, however, of using a multiple-stage op-amp is for unstable circuit behaviour resulting in an oscillatory output signal due to the capacitances within the op-amp circuit and signal feedback paths that exist. The transistor capacitances and parasitic effects due to

GBWP ¼ jAOLj � f ð1Þ

the bandwidth (increases the unity gain frequency) and also uses two capacitors.

4. Op-amp stability and compensation techniques

product of the op-amp gain magnitude and frequency (f):

4.1. Introduction

120 Very-Large-Scale Integration

$$PM = \begin{pmatrix} 180^0 - \ |\theta| \end{pmatrix} \text{ at the unity gain frequency} \tag{2}$$

where θ is the phase shift of the output signal in degrees (referenced to 0�) when the gain magnitude is unity (0 dB). It is commonly considered that an op-amp in open-loop will require a phase margin of 45� or higher. The GM (in dB) is the difference between the gain magnitude at 180� phase shift and the unity gain magnitude (i.e. 0 dB):

$$\text{G} \text{ } \text{GM} = \begin{pmatrix} \text{0 dB} - \text{ Gain magnitude (in dB)} \end{pmatrix} \text{ at } 180^{\circ} \text{ phase shift} \tag{3}$$

Given the complexity of the input-output relationship of the op-amp, it is common to model the op-amp input-output behaviour in terms of a transfer function for analysis purposes. Typically, a Laplace transfer function is created to model the frequency response and the response is viewed using a Bode plot. The transfer function provides a form for determining important system response characteristics (without solving the complete set of differential equations) in the form:

$$H(\mathbf{s}) = \frac{N(\mathbf{s})}{D(\mathbf{s})} = \frac{a\_m \mathbf{s}^m + a\_{m-1} \mathbf{s}^{(m-1)} + \dots + a\_2 \mathbf{s} + \dots + a\_0}{b\_n \mathbf{s}^n + b\_{n-1} \mathbf{s}^{(n-1)} + \dots + b\_2 \mathbf{s} + \dots + b\_o} \tag{4}$$

The roots of the numerator N(s) (zx) are called the zeros of the transfer function, and the roots of the denominator D(s) (py) are called as the poles of the transfer function. S is a complex frequency. It is often suitable to factor the polynomials in the numerator and denominator so that the transfer function then becomes:

$$H(\mathbf{s}) = \frac{Z(\mathbf{s})}{P(\mathbf{s})} = \text{K. } \frac{(\mathbf{s} - \mathbf{z}\_1).(\mathbf{s} - \mathbf{z}\_2)...(\mathbf{s} - \mathbf{z}\_m)}{(\mathbf{s} - p\_1)(\mathbf{s} - p\_2)...(\mathbf{s} - p\_n)}\tag{5}$$

This form of equation directly identifies the system poles and zeros. Using the transfer function characteristics, the Bode plot is a particularly useful tool to visualise the frequency response for analysis purposes. However, with the complexity of the networks formed by the circuit (i.e. the connection of the transistors) and the compensation structures, any system transfer functions that can be derived from the frequency response of the actual circuit to mathematically model the op-amp behaviour rapidly becomes complex. The result is a transfer function with multiple poles and zeros to consider with a complexity that cannot be easy investigated using hand calculations. Hand calculations usually utilise a simplified transfer function, using a form with the most dominant two or three poles, and a full analysis would require the use of a suitable analogue circuit simulator (typically SPICE based) and mathematical modelling tools such as MATLAB. However, deriving simplified transfer function models of the complex circuit can result in loss of detail with some of the critical frequency response parameters. Assumptions are therefore required to simplify the transfer functions without losing important information and any results must be treated with caution, particularly as the relevance of the results obtained must be determined.

#### 4.2. Miller compensation

Miller compensation is achieved by using a capacitor (CM) between the input and output nodes [4] of the second inverting stage of the two-stage op amp as shown in Figure 7a. The dominant (lower frequency) pole in the circuit transfer function is shifted to a lower frequency due to the Miller effect, and the non-dominant (higher frequency) pole is shifted to a higher frequency. The capacitor does not influence the DC response of the amplifier but retains a high gain at mid-band frequencies and reduces the high frequency gain. In this way, the two poles are split and this stabilises the amplifier, but this results in a reduction in signal bandwidth. In addition, the right-hand plane (RHP) zero causes a negative phase shift. The zero comes from the direct feedthrough of the input to the output through the Miller capacitor. If A is the voltage gain of the amplifier, and CM is a feedback capacitance across the amplifier, Miller theory identifies that CM effectively shows as a capacitance from the input and output nodes to ground as shown in Figure 7b. For a twostage CMOS op-amp design, considering it to be modelled as a transfer function with two poles only, Miller compensation is used for pole splitting. To establish the frequency dependent gain of this circuit, the small-signal equivalent circuit, as shown in Figure 8, can also be created.

The Bode plot for the equivalent circuit in Figure 8 is shown in Figure 9 and can be used to identify the positions of the poles and zeros in the transfer function. The first pole (f10) is shifted to a lower frequency (f1) and the second pole (f20) is shifted to a higher frequency (f2), although creating the zero (fz). In addition, the phase is shifted to a higher frequency.

4.3. Negative Miller compensation

the partial cancellation of these capacitances.

The effect of circuit capacitances, in particular, considering the transistor capacitances, must be considered at higher frequencies as they can cause undesirable phase shifts at higher frequencies that would not be present at lower frequencies. For example, transistor input capacitances can cause problems in circuit operation at higher frequencies and are difficult to eliminate, resulting in reduced op-amp performance. However, as improvement in the fabrication processes leads to reduced transistor geometries, a decrease in transistor capacitance values can be obtained. Negative Miller compensation can, however, be used to improve the frequency response of an op-amp [5]. The idea is shown in Figure 10. Negative Miller compensation is based on Miller effect, which defines the effect of the feedback capacitance CNM on the input capacitance CI. In Figure 10, a capacitance (CNM) is connected between the output and input nodes of a non-inverting amplifier. This creates the effect of a negative capacitance. Negative capacitance provides a method for reducing the effects of the transistor input capacitances by

Figure 9. Bode plot showing the pole movement in frequency due to the Miller capacitor.

Figure 8. Small-signal equivalent circuit for a two-stage CMOS op-amp including Miller compensation.

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Figure 7. Inverting amplifier with (a) Miller capacitance and (b) equivalent model.

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Figure 8. Small-signal equivalent circuit for a two-stage CMOS op-amp including Miller compensation.

Figure 9. Bode plot showing the pole movement in frequency due to the Miller capacitor.

#### 4.3. Negative Miller compensation

mathematical modelling tools such as MATLAB. However, deriving simplified transfer function models of the complex circuit can result in loss of detail with some of the critical frequency response parameters. Assumptions are therefore required to simplify the transfer functions without losing important information and any results must be treated with cau-

Miller compensation is achieved by using a capacitor (CM) between the input and output nodes [4] of the second inverting stage of the two-stage op amp as shown in Figure 7a. The dominant (lower frequency) pole in the circuit transfer function is shifted to a lower frequency due to the Miller effect, and the non-dominant (higher frequency) pole is shifted to a higher frequency. The capacitor does not influence the DC response of the amplifier but retains a high gain at mid-band frequencies and reduces the high frequency gain. In this way, the two poles are split and this stabilises the amplifier, but this results in a reduction in signal bandwidth. In addition, the right-hand plane (RHP) zero causes a negative phase shift. The zero comes from the direct feedthrough of the input to the output through the Miller capacitor. If A is the voltage gain of the amplifier, and CM is a feedback capacitance across the amplifier, Miller theory identifies that CM effectively shows as a capacitance from the input and output nodes to ground as shown in Figure 7b. For a twostage CMOS op-amp design, considering it to be modelled as a transfer function with two poles only, Miller compensation is used for pole splitting. To establish the frequency dependent gain of this circuit, the small-signal equivalent circuit, as shown in Figure 8,

The Bode plot for the equivalent circuit in Figure 8 is shown in Figure 9 and can be used to identify the positions of the poles and zeros in the transfer function. The first pole (f10) is shifted to a lower frequency (f1) and the second pole (f20) is shifted to a higher frequency (f2), although

creating the zero (fz). In addition, the phase is shifted to a higher frequency.

Figure 7. Inverting amplifier with (a) Miller capacitance and (b) equivalent model.

tion, particularly as the relevance of the results obtained must be determined.

4.2. Miller compensation

122 Very-Large-Scale Integration

can also be created.

The effect of circuit capacitances, in particular, considering the transistor capacitances, must be considered at higher frequencies as they can cause undesirable phase shifts at higher frequencies that would not be present at lower frequencies. For example, transistor input capacitances can cause problems in circuit operation at higher frequencies and are difficult to eliminate, resulting in reduced op-amp performance. However, as improvement in the fabrication processes leads to reduced transistor geometries, a decrease in transistor capacitance values can be obtained. Negative Miller compensation can, however, be used to improve the frequency response of an op-amp [5]. The idea is shown in Figure 10. Negative Miller compensation is based on Miller effect, which defines the effect of the feedback capacitance CNM on the input capacitance CI. In Figure 10, a capacitance (CNM) is connected between the output and input nodes of a non-inverting amplifier. This creates the effect of a negative capacitance. Negative capacitance provides a method for reducing the effects of the transistor input capacitances by the partial cancellation of these capacitances.

Figure 10. Concept for negative Miller compensation.

The amplifier has a gain magnitude greater than unity. The equivalent input capacitance (CI') is given by:

$$\mathbf{C}'\_{I} = \mathbf{C}\_{I} + (1 - |A|)\mathbf{C}\_{NM} \tag{6}$$

analogue design in CMOS technologies. It considers the relationship between the ratio of the transconductance gm over DC drain current ID. In addition, the normalised drain current is also a basic design parameter. The gm/ID characteristic provides a useful way to describe the MOSFET operation and provides a straightforward way to estimate transistor dimensions and support circuit design at low-voltage operation. The gm/ID ratio is expressed as follows:

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

Figure 11 identifies two key graphs used. Figure 11a on the left shows the gm/ID versus VGS characteristic, and Figure 11b on the right shows the gm/ID versus ID characteristic. The greater the slope of the curve, the greater the gm/ID ratio. This condition occurs when the transistor is operating in weak inversion. As the slope of the curve reduces, the transistor moves into strong inversion. Between weak and strong inversion, moderate inversion occurs. It is to be noted, however, that the region of the moderate inversion is not clearly defined. Weak and moderate inversion are more satisfactory for low-power designs [7]. Moreover, the overdrive voltage (veff) is low, which is suitable for low supply voltage operation. Figure 12a on the left shows the relationship between the gm/ID with normalised current ID.(W/L), and Figure 12b on the right shows the transistor transit frequency (fT) versus gm/ID. These curves act as aids to design and hence determining the transistor dimensions. In addition, its analytical form covers all transistor channel inversion conditions, from weak through moderate to strong inversion. The gm/ID ratio design approach allows the designer to evaluate design trade-offs for different circuit

As previously identified, the gm/ID ratio is a MOSFET characteristic directly related to all channel inversion conditions [8] of the transistor when the transistor is operating in saturation.

Figure 11. The gm/ID ratio of the MOSFET versus: (a) gate-source voltage (VGS) and (b) drain current (ID).

<sup>¼</sup> <sup>∂</sup>logðID<sup>Þ</sup> ∂Vgs

ð7Þ

125

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gm ID

5.2. MOSFET circuit design from weak to strong inversion

design operation scenarios.

<sup>¼</sup> <sup>∂</sup>ID=∂Vgs ID

The value of C<sup>0</sup> <sup>I</sup> can be controlled by varying CNM and if CNM is large, there will be a net negative capacitance, or an equivalent inductive effect, over a narrow frequency band [6]. Within the op-amp, a gain stage is usually created using an inverting amplifier with a singleended output. However, with a single-ended output amplifier, in order to incorporate negative Miller compensation then two cascaded gain stages would need to be used. One gain stage would be a non-inverting amplifier, and the feedback capacitor connection is then possible. The second would be an inverting amplifier to provide the overall inverting amplifier arrangement. For a fully differential gain stage, the negative Miller technique can be applied directly. A negative capacitance property can be utilised to improve bandwidth and phase margin. The negative capacitance design moves the non-dominant pole to a higher frequency whilst keeping the location of the dominant pole approximately the same.

### 5. gm/ID ratio design approach

#### 5.1. Introduction

When designing a CMOS op-amp using available transistor models, there can be a substantial difference between the hand calculation results using simple first-order models and simulation results using more complex models (typically BSIM3 transistor simulation models are available for a fabrication process). This would be due to both the complexities of the models used and the accuracy of the models taking into account the boundaries of operation at which the models are designed to operate in. The transistors are, however, operating in the saturation region and in the conventional op-amp design approach, the transistors are considered to also operate in strong inversion where the gate-source voltage is high as discussed in Section 3. At low-voltage operation that is appropriate also for low-power designs, the transistor gatesource voltage is lower and the transistor may be operating in moderate or weak inversion. The transconductance-DC drain current ratio (gm/ID) design approach provides separate analytical formulas for strong, moderate and weak inversion, so as to provide simple formulas that are useable in all channel inversion conditions. The approach is particularly suitable for analogue design in CMOS technologies. It considers the relationship between the ratio of the transconductance gm over DC drain current ID. In addition, the normalised drain current is also a basic design parameter. The gm/ID characteristic provides a useful way to describe the MOSFET operation and provides a straightforward way to estimate transistor dimensions and support circuit design at low-voltage operation. The gm/ID ratio is expressed as follows:

$$\frac{\mathcal{g}\_m}{I\_D} = \frac{\partial I\_D / \partial V\_{\mathcal{g}^s}}{I\_D} = \frac{\partial \log(I\_D)}{\partial V\_{\mathcal{g}^s}} \tag{7}$$

Figure 11 identifies two key graphs used. Figure 11a on the left shows the gm/ID versus VGS characteristic, and Figure 11b on the right shows the gm/ID versus ID characteristic. The greater the slope of the curve, the greater the gm/ID ratio. This condition occurs when the transistor is operating in weak inversion. As the slope of the curve reduces, the transistor moves into strong inversion. Between weak and strong inversion, moderate inversion occurs. It is to be noted, however, that the region of the moderate inversion is not clearly defined. Weak and moderate inversion are more satisfactory for low-power designs [7]. Moreover, the overdrive voltage (veff) is low, which is suitable for low supply voltage operation. Figure 12a on the left shows the relationship between the gm/ID with normalised current ID.(W/L), and Figure 12b on the right shows the transistor transit frequency (fT) versus gm/ID. These curves act as aids to design and hence determining the transistor dimensions. In addition, its analytical form covers all transistor channel inversion conditions, from weak through moderate to strong inversion. The gm/ID ratio design approach allows the designer to evaluate design trade-offs for different circuit design operation scenarios.

#### 5.2. MOSFET circuit design from weak to strong inversion

The amplifier has a gain magnitude greater than unity. The equivalent input capacitance (CI') is

negative capacitance, or an equivalent inductive effect, over a narrow frequency band [6]. Within the op-amp, a gain stage is usually created using an inverting amplifier with a singleended output. However, with a single-ended output amplifier, in order to incorporate negative Miller compensation then two cascaded gain stages would need to be used. One gain stage would be a non-inverting amplifier, and the feedback capacitor connection is then possible. The second would be an inverting amplifier to provide the overall inverting amplifier arrangement. For a fully differential gain stage, the negative Miller technique can be applied directly. A negative capacitance property can be utilised to improve bandwidth and phase margin. The negative capacitance design moves the non-dominant pole to a higher frequency whilst keep-

When designing a CMOS op-amp using available transistor models, there can be a substantial difference between the hand calculation results using simple first-order models and simulation results using more complex models (typically BSIM3 transistor simulation models are available for a fabrication process). This would be due to both the complexities of the models used and the accuracy of the models taking into account the boundaries of operation at which the models are designed to operate in. The transistors are, however, operating in the saturation region and in the conventional op-amp design approach, the transistors are considered to also operate in strong inversion where the gate-source voltage is high as discussed in Section 3. At low-voltage operation that is appropriate also for low-power designs, the transistor gatesource voltage is lower and the transistor may be operating in moderate or weak inversion. The transconductance-DC drain current ratio (gm/ID) design approach provides separate analytical formulas for strong, moderate and weak inversion, so as to provide simple formulas that are useable in all channel inversion conditions. The approach is particularly suitable for

<sup>I</sup> can be controlled by varying CNM and if CNM is large, there will be a net

<sup>I</sup> ¼ CI þ ð1 � jAjÞCNM ð6Þ

C0

ing the location of the dominant pole approximately the same.

5. gm/ID ratio design approach

Figure 10. Concept for negative Miller compensation.

given by:

The value of C<sup>0</sup>

124 Very-Large-Scale Integration

5.1. Introduction

As previously identified, the gm/ID ratio is a MOSFET characteristic directly related to all channel inversion conditions [8] of the transistor when the transistor is operating in saturation.

Figure 11. The gm/ID ratio of the MOSFET versus: (a) gate-source voltage (VGS) and (b) drain current (ID).

Figure 12. MOSFET characteristics: (a) gm/ID ratio versus normalised current (ID.(W/L)) and (b) transit frequency (fT) versus gm/ID ratio.

#### 5.2.1. Strong inversion

When vGS is higher than the threshold voltage VT, the inversion channel is strongly created, and the drift current is dominant. The classical quadratic iD-vGS MOSFET equation is based on this condition. The value for gm in strong inversion is independent of MOSFET sizing and process parameters, and it depends only on the DC bias conditions, ID and veff. Similarly, gm/ID depends only on veff and the transistor has a small gm/ID, a high gate-source voltage, a high drain current, a high fT, low noise and small dimensions (width and length).

### 5.2.2. Moderate inversion

The transition between weak inversion and strong inversion is called moderate inversion. Moderate inversion is important for modern analogue CMOS circuit design where designs are created to operate the MOSFET in this condition. Moderate inversion presents a higher gm/ID ratio and a lower gate-source voltage in relation to strong inversion combined with smaller gate area and capacitance, and a higher bandwidth compared to weak inversion.

6. Case study op-amp design

Is valid in all channel operating conditions (weak, moderate

There are different curves for gm/ID depending on the

Used for circuits operating on lower power supply voltage

A simplified technique suitable for new evolving fabrication

A fast design technique as the equations that model the electrical behaviour of circuits can be signified by gm/ID.

In this design approach, VGS should be kept as small as possible and transistor gate-source capacitance should be

The gm/ID ratio is used directly as a central design variable to

Links the variables such as gm, fT, ID and Veff to specifications

The gm/ID ratio associates small-signal and a large-signal

Not necessary to create the condition VGS > VT. Valid only if VGS > VT.

and strong) of the MOSFET.

inversion region.

process technologies.

small as possible.

determine circuit performance.

such as bandwidth and power.

levels.

The op-amp is an important differential amplifier circuit that has formed the basis of many analogue and mixed-signal IC designs. In this design case study, a two-stage op-amp has been designed and internally compensated by using negative Miller capacitance in the first stage and Miller capacitance in the second stage as shown in Figure 5. The idea behind this approach was to develop circuit stability using Miller compensation and increase the bandwidth using negative Miller compensation. The op-amp was designed using the gm/ID ratio design approach in order to consider low-voltage operation and is based on the architecture shown in Figure 5, with the circuit as shown in Figure 6. When operated on a 3.3 V power supply voltage, the MOSFETs operate in moderate inversion to optimise DC gain, unity gain frequency, PM and GM. The op-amp operation was simulated using Cadence Spectre simulator, the MOSFET models were based on a 0.35 µm CMOS fabrication process, and the AC performance both without and with an output load capacitance was assessed in simulation. A differential input voltage was applied

Uses charts and simple equations. Depends on complex equations and sometimes based on

Table 1. Differences between the gm/ID ratio design approach and the conventional design approach.

gm/ID design approach Conventional design approach using VT, KP and λ

voltage levels.

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

technologies.

and voltage relationships.

performance of the circuit.

poorly defined parameters.

modulation (λ).

Is valid only in strong inversion of the MOSFET.

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Uses the ID versus VGS and ID versus VDS curves.

Used for circuits operating on higher power supply

Not suitable for new evolving fabrication process

Not appropriate as a fast design technique. It does not have compact electrical models capable of simple current

If (VGS –VT) is small, a large geometry device is required and thus large transistor gate-source capacitance.

Parameters such as µCox, VT and vDS(sat) are considered as

assumptions such as ignoring the effect of channel length

Small- and a large-signal models are not associated.

The gm/ID ratio is not directly used to determine the

to the op-amp in open loop and a single-ended output voltage monitored.

6.1. Introduction

(gm ! ID) parameters.

#### 5.2.3. Weak inversion

In weak inversion, the drain current can be determined using an exponential expression. The transistor has a large gm/ID, a low gate-source voltage, a low drain current, a low fT, high noise and large dimensions (width and length).

Each channel inversion condition has different performance characteristics and a circuit design would then be optimised to account for these characteristics. Given that a design can be created by either using the conventional design approach or the gm/ID ratio design approach, Table 1 provides a summary comparison between the approaches.


Table 1. Differences between the gm/ID ratio design approach and the conventional design approach.

### 6. Case study op-amp design

#### 6.1. Introduction

5.2.1. Strong inversion

versus gm/ID ratio.

126 Very-Large-Scale Integration

5.2.2. Moderate inversion

5.2.3. Weak inversion

and large dimensions (width and length).

Table 1 provides a summary comparison between the approaches.

When vGS is higher than the threshold voltage VT, the inversion channel is strongly created, and the drift current is dominant. The classical quadratic iD-vGS MOSFET equation is based on this condition. The value for gm in strong inversion is independent of MOSFET sizing and process parameters, and it depends only on the DC bias conditions, ID and veff. Similarly, gm/ID depends only on veff and the transistor has a small gm/ID, a high gate-source voltage, a high

Figure 12. MOSFET characteristics: (a) gm/ID ratio versus normalised current (ID.(W/L)) and (b) transit frequency (fT)

The transition between weak inversion and strong inversion is called moderate inversion. Moderate inversion is important for modern analogue CMOS circuit design where designs are created to operate the MOSFET in this condition. Moderate inversion presents a higher gm/ID ratio and a lower gate-source voltage in relation to strong inversion combined with smaller gate area and capacitance, and a higher bandwidth compared to weak inversion.

In weak inversion, the drain current can be determined using an exponential expression. The transistor has a large gm/ID, a low gate-source voltage, a low drain current, a low fT, high noise

Each channel inversion condition has different performance characteristics and a circuit design would then be optimised to account for these characteristics. Given that a design can be created by either using the conventional design approach or the gm/ID ratio design approach,

drain current, a high fT, low noise and small dimensions (width and length).

The op-amp is an important differential amplifier circuit that has formed the basis of many analogue and mixed-signal IC designs. In this design case study, a two-stage op-amp has been designed and internally compensated by using negative Miller capacitance in the first stage and Miller capacitance in the second stage as shown in Figure 5. The idea behind this approach was to develop circuit stability using Miller compensation and increase the bandwidth using negative Miller compensation. The op-amp was designed using the gm/ID ratio design approach in order to consider low-voltage operation and is based on the architecture shown in Figure 5, with the circuit as shown in Figure 6. When operated on a 3.3 V power supply voltage, the MOSFETs operate in moderate inversion to optimise DC gain, unity gain frequency, PM and GM. The op-amp operation was simulated using Cadence Spectre simulator, the MOSFET models were based on a 0.35 µm CMOS fabrication process, and the AC performance both without and with an output load capacitance was assessed in simulation. A differential input voltage was applied to the op-amp in open loop and a single-ended output voltage monitored.

### 6.2. Op-amp simulation and results

The op-amp simulation study was performed with two conditions: first, no output load capacitance and second, with a variable output load capacitance. An AC analysis was performed on the op-amp design using typical transistor models with the transistors biased for a 3.3 V singlerail power supply voltage operation.

compensation techniques and that the choice of compensation technique would determine

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In this study, the simulation approach and results obtained concentrated on the frequency response by using the op-amp with different internal compensation techniques and an output load capacitance with values of 0.1, 0.5 and 1.0 pF. Table 3 shows the results of the simulation

An additional form of analysis undertaken with this design was to consider the transfer function for the op-amp input-output relationship. The transfer function is a useful form for evaluating the op-amp frequency response. For a typical op-amp, then the transfer function would contain a large number of poles and zeros. This form would be too complex for initial design development, and so it is common to approximate the transfer function to a simple form that contains typically only two or three poles. These can be estimated from the smallsignal equivalent circuit. In addition, once the op-amp design has been created, it is possible to extract the poles and zeros using the circuit simulator and to minimise the initial transfer function of the circuit model having large number of poles and zeros into a simpler transfer

Characteristic No output load capacitance 0.1 pF 0.5 pF 1.0 pF DC gain (dB) 82.5 82.5 82.5 82.5 Phase margin (degree) 63.03 61.39 55.99 50.96 Unity gain frequency (MHz) 205.54 203.83 195.54 183.38 Gain margin (dB) 9.93 9.80 9.44 9.23

Table 3. Open-loop op-amp performance with different output load capacitance values (with combined Miller and

Figure 14. Frequency response of the open-loop op-amp design with different load capacitances: (a) gain and (b) phase

whether the op-amp is stable or not in closed loop.

study that are shown in Bode plot format in Figure 14.

6.2.2. Study 2: with output load capacitance

6.3. Transfer function analysis

negative Miller compensation).

(Spectre simulation on the transistor circuit model).

### 6.2.1. Study 1: without output load capacitance

In this study, the simulation approach and results obtained concentrated on the frequency response by using the op-amp with different internal compensation techniques and no output load capacitance. First, no internal compensation was incorporated and then compensation using Miller, negative Miller and a combination of Miller and negative Miller arrangements were considered. Table 2 shows the results of the simulation study that are shown in Bode plot format in Figure 13.

For the op-amp with no compensation and negative Miller compensation only, the GM was a positive number (based on the simulator output value), and hence, the op-amp would be unstable in closed loop. In addition, with these two scenarios, the PM was negative (simulator output value) and this also indicated that the op-amp would be unstable in closed-loop. The results show that the gain magnitude and phase shift are controllable with the different


Table 2. Open-loop op-amp performance with different compensation techniques.

Figure 13. Bode plot of the open-loop op-amp performance with different compensation techniques: (a) gain and (b) phase (Spectre simulation on the transistor circuit model).

compensation techniques and that the choice of compensation technique would determine whether the op-amp is stable or not in closed loop.

### 6.2.2. Study 2: with output load capacitance

In this study, the simulation approach and results obtained concentrated on the frequency response by using the op-amp with different internal compensation techniques and an output load capacitance with values of 0.1, 0.5 and 1.0 pF. Table 3 shows the results of the simulation study that are shown in Bode plot format in Figure 14.

### 6.3. Transfer function analysis

6.2. Op-amp simulation and results

128 Very-Large-Scale Integration

rail power supply voltage operation.

format in Figure 13.

6.2.1. Study 1: without output load capacitance

The op-amp simulation study was performed with two conditions: first, no output load capacitance and second, with a variable output load capacitance. An AC analysis was performed on the op-amp design using typical transistor models with the transistors biased for a 3.3 V single-

In this study, the simulation approach and results obtained concentrated on the frequency response by using the op-amp with different internal compensation techniques and no output load capacitance. First, no internal compensation was incorporated and then compensation using Miller, negative Miller and a combination of Miller and negative Miller arrangements were considered. Table 2 shows the results of the simulation study that are shown in Bode plot

For the op-amp with no compensation and negative Miller compensation only, the GM was a positive number (based on the simulator output value), and hence, the op-amp would be unstable in closed loop. In addition, with these two scenarios, the PM was negative (simulator output value) and this also indicated that the op-amp would be unstable in closed-loop. The results show that the gain magnitude and phase shift are controllable with the different

CNM and CM = 0.31 pF No compensation Negative Miller only Miller only Miller and negative Miller

Figure 13. Bode plot of the open-loop op-amp performance with different compensation techniques: (a) gain and (b)

DC gain (dB) 82.5 82.5 82.5 82.5 Phase margin (degrees) 65.19 52.56 57.47 63.03 Unity gain frequency (MHz) 1073 1177 177.33 205.54 Gain margin (dB) 14.27 11.08 10.61 9.93

Table 2. Open-loop op-amp performance with different compensation techniques.

phase (Spectre simulation on the transistor circuit model).

An additional form of analysis undertaken with this design was to consider the transfer function for the op-amp input-output relationship. The transfer function is a useful form for evaluating the op-amp frequency response. For a typical op-amp, then the transfer function would contain a large number of poles and zeros. This form would be too complex for initial design development, and so it is common to approximate the transfer function to a simple form that contains typically only two or three poles. These can be estimated from the smallsignal equivalent circuit. In addition, once the op-amp design has been created, it is possible to extract the poles and zeros using the circuit simulator and to minimise the initial transfer function of the circuit model having large number of poles and zeros into a simpler transfer


Table 3. Open-loop op-amp performance with different output load capacitance values (with combined Miller and negative Miller compensation).

Figure 14. Frequency response of the open-loop op-amp design with different load capacitances: (a) gain and (b) phase (Spectre simulation on the transistor circuit model).

function having a reduced number of poles and zeros. The process for investigating the circuit operation and simplifying the transfer function considered was to:

transfer functions model a biproper system with a finite high frequency gain rather than a

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

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131

Designing and operating analogue circuits at low power supply voltages are challenging tasks. In the past, the circuits typically encountered were designed to operate at higher voltage levels, and so circuit performance limitations due to a limited voltage range was not an issue for many designs. Today, the operation of electronic circuits with low-voltage power supplies is now a requirement for use in electronic systems where size, weight, and power consumption are especially important. For example, in battery-operated portable equipment, a reduction in the battery requirements such as size, weight and energy capacity can provide cost reduction benefits in equipment production, purchase and use as well as making the equipment more portable. The move towards low-voltage operation can be considered from three different

1. The increasing use of battery-operated portable systems requires low-power dissipation in

2. Reduced feature sizes in modern VLSI fabrication processes results in larger electric fields that, unless the power supply voltages are reduced, result in reliability problems.

3. Reduced feature sizes in modern VLSI fabrication processes results in a higher density of the electronics that increases the power dissipation per unit area. The low-voltage opera-

As device geometries in CMOS are reduced, the benefits include reduced size, higher operating speeds and reduced power consumption (due to the ability to operate the designs on lower power supply voltage levels), which are mostly exploited in the digital parts of a design. However, this move comes at a cost of introducing device characteristics not seen with larger device geometries. Reducing the power supply voltage has been exploited effectively in digital circuits, but analogue circuits exploiting reduced geometry and voltage operation need to account for a range of circuit performance limiting issues not a concern in digital. In analogue circuits, reducing device geometries and power supply voltage levels have an enormous impact on the analogue circuit capability. For example, as the device geometries become smaller and circuit densities increase, currents in the circuit may need to be reduced in order to prevent excessive temperature increments due to the power consumption per unit area. In addition, reliability problems would exist at higher voltage levels (voltage levels which were commonly used in the past, such as 5 V, but now would be too high for reliable circuit operation) due to excessively high electric fields that would exist. Process variations as CMOS technology move to the lower (deep) sub-micron levels and their effects on low geometry devices, such as transistor width and length dimensions, means that analogue circuit performance can vary widely between devices of the same type and this is accompanied in reduced device geometries by an increase in transistor leakage currents. Whilst the geometries reduce, the transistor threshold voltage (VT) is, however, remaining relatively constant, and as the power supply voltage is reduced, this causes as

order to prolong circuit operation time with a battery energy source.

tion can be used to reduce the power dissipation per unit area.

7. Op-amp design and operation at lower power supply voltages

realistic strictly proper transfer function.

perspectives:


From the analysis of the open-loop op-amp pole and zero locations as extracted from the circuit, the initial transfer function consisted of 23 poles and 23 zeros. Although it would be expected that the number of poles should be greater than the number of zeros in the transfer function for a strictly proper system, the original 23 pole and zero transfer function extracted is used in the following discussion, and hence, the results are used with a certain level of caution. These were the raw results obtained from the pole-zero analysis in Spectre. It should be noted that the transfer function has the same number of poles and zeros and hence would be referred to as a biproper system. When the transfer function is biproper, it is not reflective of a realisable system at high frequencies as it would have a finite gain at the higher signal frequencies. A strictly proper system where the gain reduces to zero at higher frequencies, as would be expected in a real op-amp, the number of poles must be greater than the number of zeros. This effect can be seen when simulating the transfer function for this design at the higher signal frequencies that would not actually be encountered. To simplify this transfer function from original number of poles and zeros, MATLAB was used to reduce the transfer function to one with just three poles and zeros. Table 4 shows the resulting performance of the different simulation models, noting that the response of the three models would be valid only up to a certain frequency as the


Table 4. Simulated op-amp performance comparison (Spectre (transistor level model), MATLAB (transfer function) and Verilog-A (transfer function)).

transfer functions model a biproper system with a finite high frequency gain rather than a realistic strictly proper transfer function.

### 7. Op-amp design and operation at lower power supply voltages

function having a reduced number of poles and zeros. The process for investigating the circuit

3. Use MATLAB to reduce the number of poles and zeros in the transfer function and simulate the transfer function behaviour to ensure that the reduced transfer function Bode

4. Translate the new transfer function to high-level Verilog-A model and compare the Verilog-A model to the original analogue circuit simulation results and the MATLAB

From the analysis of the open-loop op-amp pole and zero locations as extracted from the circuit, the initial transfer function consisted of 23 poles and 23 zeros. Although it would be expected that the number of poles should be greater than the number of zeros in the transfer function for a strictly proper system, the original 23 pole and zero transfer function extracted is used in the following discussion, and hence, the results are used with a certain level of caution. These were the raw results obtained from the pole-zero analysis in Spectre. It should be noted that the transfer function has the same number of poles and zeros and hence would be referred to as a biproper system. When the transfer function is biproper, it is not reflective of a realisable system at high frequencies as it would have a finite gain at the higher signal frequencies. A strictly proper system where the gain reduces to zero at higher frequencies, as would be expected in a real op-amp, the number of poles must be greater than the number of zeros. This effect can be seen when simulating the transfer function for this design at the higher signal frequencies that would not actually be encountered. To simplify this transfer function from original number of poles and zeros, MATLAB was used to reduce the transfer function to one with just three poles and zeros. Table 4 shows the resulting performance of the different simulation models, noting that the response of the three models would be valid only up to a certain frequency as the

Number of poles/zeros Performance Spectre MATLAB Verilog-A

Table 4. Simulated op-amp performance comparison (Spectre (transistor level model), MATLAB (transfer function) and

Gain margin (dB) 9.938 9.95 9.938

Unity gain frequency (MHz) 205.5 198 205.5 Phase margin (degrees) 63 63 63 DC gain (dB) 82.47 82.5 82.47

Gain margin (dB) – 10.7 10.64

Unity gain frequency (MHz) – 192 200.8 Phase margin (degrees) – 54.4 54.61 DC gain (dB) – 83.9 83.88

1. Extract the poles and zeros from the circuit model using Cadence Spectre simulator.

2. Transfer the pole and zero values to MATLAB and create the transfer function.

plot and key characteristics are comparable to the original transfer function.

operation and simplifying the transfer function considered was to:

simulation study results.

130 Very-Large-Scale Integration

23/23 (MATLAB and Verilog-A transfer function models only)

3/3 (MATLAB and Verilog-A transfer function models only)

Verilog-A (transfer function)).

Designing and operating analogue circuits at low power supply voltages are challenging tasks. In the past, the circuits typically encountered were designed to operate at higher voltage levels, and so circuit performance limitations due to a limited voltage range was not an issue for many designs. Today, the operation of electronic circuits with low-voltage power supplies is now a requirement for use in electronic systems where size, weight, and power consumption are especially important. For example, in battery-operated portable equipment, a reduction in the battery requirements such as size, weight and energy capacity can provide cost reduction benefits in equipment production, purchase and use as well as making the equipment more portable. The move towards low-voltage operation can be considered from three different perspectives:


As device geometries in CMOS are reduced, the benefits include reduced size, higher operating speeds and reduced power consumption (due to the ability to operate the designs on lower power supply voltage levels), which are mostly exploited in the digital parts of a design. However, this move comes at a cost of introducing device characteristics not seen with larger device geometries. Reducing the power supply voltage has been exploited effectively in digital circuits, but analogue circuits exploiting reduced geometry and voltage operation need to account for a range of circuit performance limiting issues not a concern in digital. In analogue circuits, reducing device geometries and power supply voltage levels have an enormous impact on the analogue circuit capability. For example, as the device geometries become smaller and circuit densities increase, currents in the circuit may need to be reduced in order to prevent excessive temperature increments due to the power consumption per unit area. In addition, reliability problems would exist at higher voltage levels (voltage levels which were commonly used in the past, such as 5 V, but now would be too high for reliable circuit operation) due to excessively high electric fields that would exist. Process variations as CMOS technology move to the lower (deep) sub-micron levels and their effects on low geometry devices, such as transistor width and length dimensions, means that analogue circuit performance can vary widely between devices of the same type and this is accompanied in reduced device geometries by an increase in transistor leakage currents. Whilst the geometries reduce, the transistor threshold voltage (VT) is, however, remaining relatively constant, and as the power supply voltage is reduced, this causes as reduction in the available voltage range for circuit operation (a reduction in the (VDD –VT) value). Analogue circuits would typically require the creation of bias currents for circuits such as current mirrors which are created using transistors. The need to account for the transistor to be operating in either the weak, moderate or strong inversion regions of operation and the resulting transistor performance differences due to the region of operation would need to be accounted for. The use of fully differential structures is considered given their superior performance with circuit parameters such as CMRR and PSRR (power-supply rejection-ratio), lower signal distortion and wider signal swing range. Finally, the need to maximise dynamic signal range which often requires a rail-to-rail output voltage range and for op-amps operated in unity-gain configuration, the input stage should also have a rail-torail common mode input voltage range [9].

References

Hall, Inc.; 1987

[1] Haskard Malcolm R. Analog VLSI design: nMOS and CMOS. Hoboken, NJ, USA: Prentice-

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

http://dx.doi.org/10.5772/intechopen.68815

133

[2] Baker R Jacob. CMOS: Circuit Design, Layout, and Simulation. 3rd ed. Hoboken, NJ, USA:

[3] Laker K, Sansen W. Design of Analog Integrated Circuits and Systems. 1st ed. New York,

[4] Eduard Säckinger. Broadband Circuits for Optical Fiber Communication. 1st ed. Hoboken,

[5] Boaz S-T, Mücahit K, Friedman EG. A high-speed CMOS op-amp design technique using negative Miller capacitance. In: 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004); 15 Dec. 2004; IEEE; 2004. pp. 623-626. DOI: 10.1109/ICECS.2004.1399758

[6] Wu H-M. A 3.125-GHz limiting amplifier for optical receiver system. In: 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006); 4–7 Dec. 2006; IEEE; 2007.

[7] Silveira F, Flandre D, Jespers PGA. A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE Journal of Solid-State Circuits. 1996;31(9):1314-1319. DOI: 10.1109/4.535416 [8] Jespers P. The gm/ID methodology, a sizing tool for low-voltage analog CMOS circuits.

[9] Wassenaar RF, Gierkink SLJ, Botma JH. Low-voltage CMOS operational amplifiers. In: Edgar S-S, Andreou AG, editors. Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits (IEEE Press Series on Microelectronic Systems). 1st ed.

John Wiley & Sons; 2011. DOI: 10.1002/9780470891179

USA: McGraw-Hill Companies; 1994. p. 898

pp. 210-213. DOI: 10.1109/APCCAS.2006.342369

Piscataway, NJ, USA: Wiley-IEEE Press; 1999

New York, USA: Springer Science & Business Media; 2010. p. 188

NJ, USA: Wiley; 2005. p. 456

### 8. Conclusions

The op-amp is an integral part of the on-chip analogue signal conditioning circuitry for the front-end section of mixed-signal ICs. In this chapter, the design of the two-stage op-amp was considered, which was designed using a 0.35 µm CMOS fabrication process and working on a single rail 3.3 V power supply. Considerations were given to low-voltage design (operating at and below 3.3 V) by using the gm/ID ratio design approach and the use of both Miller and negative Miller compensation as an internal compensation scheme for op-amp stability and signal bandwidth reasons. The discussion was accompanied by an op-amp case study design and simulation study results that focused on AC performance.

### Acknowledgements

The authors would like to acknowledge the support for this work from the Iraqi Ministry of Higher Education and Scientific Research (MOHESR).

### Author details

Muhaned Zaidi1,2, Ian Grout1 \* and Abu Khari A'ain<sup>3</sup>

\*Address all correspondence to: ian.grout@ul.ie

1 Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland

2 Wasit University, Wasit, Iraq

3 Department of Electronic and Computer Engineering, Universiti Teknologi Malaysia, Skudai, Malaysia

### References

reduction in the available voltage range for circuit operation (a reduction in the (VDD –VT) value). Analogue circuits would typically require the creation of bias currents for circuits such as current mirrors which are created using transistors. The need to account for the transistor to be operating in either the weak, moderate or strong inversion regions of operation and the resulting transistor performance differences due to the region of operation would need to be accounted for. The use of fully differential structures is considered given their superior performance with circuit parameters such as CMRR and PSRR (power-supply rejection-ratio), lower signal distortion and wider signal swing range. Finally, the need to maximise dynamic signal range which often requires a rail-to-rail output voltage range and for op-amps operated in unity-gain configuration, the input stage should also have a rail-to-

The op-amp is an integral part of the on-chip analogue signal conditioning circuitry for the front-end section of mixed-signal ICs. In this chapter, the design of the two-stage op-amp was considered, which was designed using a 0.35 µm CMOS fabrication process and working on a single rail 3.3 V power supply. Considerations were given to low-voltage design (operating at and below 3.3 V) by using the gm/ID ratio design approach and the use of both Miller and negative Miller compensation as an internal compensation scheme for op-amp stability and signal bandwidth reasons. The discussion was accompanied by an op-amp case study design

The authors would like to acknowledge the support for this work from the Iraqi Ministry of

\* and Abu Khari A'ain<sup>3</sup>

1 Department of Electronic and Computer Engineering, University of Limerick, Limerick,

3 Department of Electronic and Computer Engineering, Universiti Teknologi Malaysia,

rail common mode input voltage range [9].

and simulation study results that focused on AC performance.

Higher Education and Scientific Research (MOHESR).

\*Address all correspondence to: ian.grout@ul.ie

8. Conclusions

132 Very-Large-Scale Integration

Acknowledgements

Author details

Skudai, Malaysia

Ireland

Muhaned Zaidi1,2, Ian Grout1

2 Wasit University, Wasit, Iraq


**Chapter 6**

Provisional chapter

**Design of High-Order CMOS Analog Notch Filter with**

DOI: 10.5772/intechopen.73157

Analog notch filters schematics are very rare. Two circuit diagrams are reviewed with symbolic equations. The first schematic is analog notch filter based on twin-T circuit diagram. The second schematic is analog notch filter based on the Friend biquad circuit.

Keywords: analog notch filter, high-order filter, LCR prototype, interference rejection

Notch filters or band stop filters have many types of applications. The first application is interference mitigation in GNSS receiver [1]. The second application is the removal of powerline noise from biomedical signals which have operating frequency range from 50 to 60 Hz, while biomedical signal such as EEG has magnitude response in the range of 1–40 Hz [2]. The third application is for a radio frequency image rejection [3]. The fourth application is for an interference rejection in UWB systems. In this application, the filter can notch the

A second-order notch can be constructed using an LCR passive prototype. The advent of the very large-scale integration allows tens of thousands of transistors to be fabricated in an integrated circuit. CMOS analog notch filters can be easily designed and built in an IC chip. There are many types of techniques to design analog filter at the architecture or block diagram level such as active RC filter, Gm-C filter, switched Capacitor filter, etc. In this chapter, we will

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

> © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

magnitude more than 35 db at operating frequency of 900 MHz [4].

design analog notch filter based on Gm-C filter block diagram.

Design of High-Order CMOS Analog Notch Filter with

**0.18 μm CMOS Technology**

0.18 μm CMOS Technology

http://dx.doi.org/10.5772/intechopen.73157

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

Kittipong Tripetch

Abstract

1. Introduction

Kittipong Tripetch

#### **Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology** Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

DOI: 10.5772/intechopen.73157

#### Kittipong Tripetch Kittipong Tripetch

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.73157

Abstract

Analog notch filters schematics are very rare. Two circuit diagrams are reviewed with symbolic equations. The first schematic is analog notch filter based on twin-T circuit diagram. The second schematic is analog notch filter based on the Friend biquad circuit.

Keywords: analog notch filter, high-order filter, LCR prototype, interference rejection

### 1. Introduction

Notch filters or band stop filters have many types of applications. The first application is interference mitigation in GNSS receiver [1]. The second application is the removal of powerline noise from biomedical signals which have operating frequency range from 50 to 60 Hz, while biomedical signal such as EEG has magnitude response in the range of 1–40 Hz [2]. The third application is for a radio frequency image rejection [3]. The fourth application is for an interference rejection in UWB systems. In this application, the filter can notch the magnitude more than 35 db at operating frequency of 900 MHz [4].

A second-order notch can be constructed using an LCR passive prototype. The advent of the very large-scale integration allows tens of thousands of transistors to be fabricated in an integrated circuit. CMOS analog notch filters can be easily designed and built in an IC chip. There are many types of techniques to design analog filter at the architecture or block diagram level such as active RC filter, Gm-C filter, switched Capacitor filter, etc. In this chapter, we will design analog notch filter based on Gm-C filter block diagram.

### 2. Transconductor capacitor filter based on floating active inductors

There are many choices of transconductor in the literatures. The first transconductor was published by Nedungadi [5]. It is proposed since 1984. This transconductor is very linear; its linear range can be extended by design and simulation. The circuit diagram is shown in Figure 1. Its typical linear range, which is output current versus input voltage, can be plotted by level 1 transistor model as follows.

Drain current of an NMOS and a PMOS transistor can be expressed as follows [6]:

$$I\_D = \frac{\mu\_n \mathbb{C}\_{ox}}{2} \left(\frac{W}{L}\right) (V\_{GS} - V\_{TH})^2 (1 + \lambda V\_{DS}) \tag{1}$$

ID <sup>¼</sup> <sup>W</sup> L

IDS ¼ WvsatCox

prototype.

(5) below [7]:

Figures 2 and 3.

3. Second-order notch filter

μeCox

1

CCA

ð Þ VGS � VTH

ECL ≫ VGS � VTH for long channel device

ECL ≪ VGS � VTH for short channel device

VGS � VTH � VDS

ð Þþ VGS � VTH ECL <sup>≈</sup> WvsatCoxð Þ VGS � VTH

<sup>θ</sup>tox � �<sup>η</sup> , <sup>η</sup> <sup>¼</sup> <sup>1</sup>:<sup>85</sup> for 0:<sup>13</sup> <sup>μ</sup><sup>m</sup>

2

In order for someone to plot linear range by using multiple transistors, output current can be written as a function input voltage by writing KVL around the loop. Another way of representation is to derive small signal transconductance gain in frequency domain which is a ratio of output current which flows out from the output node divided by input voltage. Small-signal equivalent circuit concept can make the circuit analysis difficult because of parasitic capacitance. Transconductor circuit diagram which has too many transistors may not work if it is believed in small-signal circuit concept because the circuit has too many poles and zeros which make the element substitution of transconductor to deviate from ideal transfer function of LCR

Circuit idea of notch filter is very rare. This is because the theory of an ideal second-order transfer function is well defined. The notch filter or band reject filer is found to be expressed as

H sð Þ¼ <sup>s</sup><sup>2</sup> <sup>þ</sup> <sup>ω</sup><sup>2</sup>

where ω<sup>z</sup> is the notch frequency, ω<sup>p</sup> is a pole frequency and ω<sup>z</sup> ¼ ωp.

<sup>s</sup><sup>2</sup> <sup>þ</sup> <sup>ω</sup><sup>p</sup> Qp � �<sup>s</sup> <sup>þ</sup> <sup>ω</sup><sup>2</sup>

Numerator polynomial can be designed to have any value so that the roots of the numerator

The circuit which implements this function is called twin-T RC network which can be drawn in

polynomial have roots of it equal with complex zero after equating them with zero.

z

p

� �VDS

2

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

http://dx.doi.org/10.5772/intechopen.73157

(3)

137

(4)

(5)

1 þ VDS ECL

<sup>1</sup> <sup>þ</sup> VGS�VTH

0

BB@

<sup>μ</sup><sup>e</sup> <sup>¼</sup> <sup>μ</sup><sup>0</sup>

$$-I\_D = \frac{\mu\_p \mathcal{C}\_{ox}}{2} \left(\frac{\mathcal{W}}{L}\right) (V\_{GS} - V\_{TH})^2 (1 - \lambda V\_{DS}) \tag{2}$$

where ID is the drain current, μ<sup>n</sup> is the electron mobility, μ<sup>p</sup> is the hole mobility, Cox is oxide thickness and λ is the channel length modulation.

For submicron CMOS, drain current of NMOS and PMOS transistor can be shown in the formulas (3) and (4). As a consequence of high electric field, both x and y dimensions are a derivative of electric filed by distance along x- and y-axes:

Figure 1. (a) Differential amplifier with cross couple concept, (b) replacement of ideal voltage source with transistor in (a), and (c) cross couple circuit diagram with cascade active load.

$$\begin{aligned} I\_D &= \frac{W}{L} \left( \frac{\mu\_e \mathbf{C\_{ox}}}{1 + \frac{V\_{DS}}{E\_c L}} \right) \left( V\_{GS} - V\_{TH} - \frac{V\_{DS}}{2} \right) V\_{DS} \\\\ \mu\_e &= \frac{\mu\_0}{1 + \left( \frac{V\_{GS} - V\_{TH}}{\partial t\_{ox}} \right)^{\eta^\*}}, \eta = 1.85 \quad \text{for } \mathbf{0.13} \text{ }\mu\text{m} \end{aligned} \tag{3}$$

$$I\_{DS} = W \mathbf{\hat{v}\_{sat}} \mathbf{C\_{ox}} \frac{\left( V\_{GS} - V\_{TH} \right)^2}{\left( V\_{GS} - V\_{TH} \right) + E\_C L} \approx W \mathbf{\hat{v}\_{sat}} \mathbf{C\_{ox}} (V\_{GS} - V\_{TH})$$

$$E\_C L \gg V\_{GS} - V\_{TH} \quad \text{for } \mathbf{long{chamel}} \text{ }\text{device} \tag{4}$$

$$E\_C L \ll V\_{GS} - V\_{TH} \quad \text{for } \mathbf{short} \text{ channel device}$$

In order for someone to plot linear range by using multiple transistors, output current can be written as a function input voltage by writing KVL around the loop. Another way of representation is to derive small signal transconductance gain in frequency domain which is a ratio of output current which flows out from the output node divided by input voltage. Small-signal equivalent circuit concept can make the circuit analysis difficult because of parasitic capacitance. Transconductor circuit diagram which has too many transistors may not work if it is believed in small-signal circuit concept because the circuit has too many poles and zeros which make the element substitution of transconductor to deviate from ideal transfer function of LCR prototype.

### 3. Second-order notch filter

2. Transconductor capacitor filter based on floating active inductors

Drain current of an NMOS and a PMOS transistor can be expressed as follows [6]:

W L 

> W L

ID <sup>¼</sup> <sup>μ</sup>nCox 2

�ID <sup>¼</sup> <sup>μ</sup>pCox 2

thickness and λ is the channel length modulation.

and (c) cross couple circuit diagram with cascade active load.

derivative of electric filed by distance along x- and y-axes:

by level 1 transistor model as follows.

136 Very-Large-Scale Integration

There are many choices of transconductor in the literatures. The first transconductor was published by Nedungadi [5]. It is proposed since 1984. This transconductor is very linear; its linear range can be extended by design and simulation. The circuit diagram is shown in Figure 1. Its typical linear range, which is output current versus input voltage, can be plotted

ð Þ VGS � VTH

ð Þ VGS � VTH

where ID is the drain current, μ<sup>n</sup> is the electron mobility, μ<sup>p</sup> is the hole mobility, Cox is oxide

For submicron CMOS, drain current of NMOS and PMOS transistor can be shown in the formulas (3) and (4). As a consequence of high electric field, both x and y dimensions are a

Figure 1. (a) Differential amplifier with cross couple concept, (b) replacement of ideal voltage source with transistor in (a),

2

2

ð Þ 1 þ λVDS (1)

ð Þ 1 � λVDS (2)

Circuit idea of notch filter is very rare. This is because the theory of an ideal second-order transfer function is well defined. The notch filter or band reject filer is found to be expressed as (5) below [7]:

$$H(\mathbf{s}) = \frac{\mathbf{s}^2 + \omega\_z^2}{\mathbf{s}^2 + \left(\frac{\omega\_r}{Q\_r}\right)\mathbf{s} + \omega\_p^2} \tag{5}$$

where ω<sup>z</sup> is the notch frequency, ω<sup>p</sup> is a pole frequency and ω<sup>z</sup> ¼ ωp.

Numerator polynomial can be designed to have any value so that the roots of the numerator polynomial have roots of it equal with complex zero after equating them with zero.

The circuit which implements this function is called twin-T RC network which can be drawn in Figures 2 and 3.

V<sup>1</sup> � Vout sC<sup>1</sup>

Vin � V<sup>1</sup> R1 

> <sup>¼</sup> <sup>V</sup><sup>2</sup> sC<sup>3</sup> þ

Vin � V<sup>2</sup> sC<sup>2</sup>

V<sup>1</sup> � Vout sC<sup>1</sup>

Substitute Eq. (11) into an Eq. (9):

<sup>¼</sup> <sup>V</sup><sup>1</sup> R3 þ

Substitute an Eq. (10) into an Eq. (12):

Vin � V<sup>1</sup> R1 

Vinð Þ¼ sC1R<sup>3</sup>

þ

þ

V<sup>2</sup> � Vout R2

Vinð Þ¼ sC3R<sup>2</sup> <sup>V</sup><sup>2</sup> sC3R<sup>2</sup> <sup>þ</sup> sC2R<sup>2</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>C2C<sup>3</sup>

sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s ð Þ <sup>2</sup>C2C<sup>3</sup>

¼ Vout

<sup>V</sup><sup>1</sup> <sup>¼</sup> Vout <sup>s</sup><sup>2</sup>C4R4C1R<sup>2</sup> <sup>þ</sup> s C<sup>ð</sup> <sup>1</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>1R4Þ þ <sup>R</sup>2R<sup>4</sup>

<sup>¼</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � <sup>V</sup>2ð Þ sC1R<sup>4</sup> ð Þ R2R<sup>4</sup> 

Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � <sup>V</sup>2ð Þ sC1R<sup>4</sup> ð Þ R2R<sup>4</sup> 

VinðsC1R3ð Þ <sup>R</sup>2R<sup>4</sup> Þ ¼ Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � <sup>V</sup>2ð Þ sC1R<sup>4</sup>

�Voutð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup>

�V2ð Þ sC1R<sup>4</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C1R3Þ þ R1R<sup>3</sup>

Vinð Þ¼ sa<sup>12</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> <sup>ð</sup>s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup>

<sup>V</sup><sup>2</sup> <sup>¼</sup> Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup>

V<sup>2</sup> � Vout R2

V<sup>1</sup> � Vout sC<sup>1</sup> ð Þ Vin � V<sup>1</sup> ð Þ¼ sC1R<sup>3</sup> V1ð Þþ sC1R<sup>1</sup> ð Þ V<sup>1</sup> � Vout R1R<sup>3</sup> Vinð Þ¼ sC1R<sup>3</sup> V1ðsC1R<sup>1</sup> þ sC1R<sup>3</sup> þ R1R3Þ � Voutð Þ R1R<sup>3</sup>

ð Þ Vin � <sup>V</sup><sup>2</sup> sC3R<sup>2</sup> <sup>¼</sup> <sup>V</sup>2ð Þþ sC2R<sup>2</sup> ð Þ <sup>V</sup><sup>2</sup> � Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup>

1 R4 þ sC<sup>4</sup> 

ð Þ V<sup>1</sup> � Vout R2R<sup>4</sup> þ ð Þ V<sup>2</sup> � Vout sC1R<sup>4</sup> ¼ Voutð Þ 1 þ sC4R<sup>4</sup> ð Þ sC1R<sup>2</sup> <sup>V</sup>1ð Þþ <sup>R</sup>2R<sup>4</sup> <sup>V</sup>2ð Þ¼ sC1R<sup>4</sup> Vout sC1R<sup>2</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>C4R4C1R<sup>2</sup> <sup>þ</sup> <sup>R</sup>2R<sup>4</sup> <sup>þ</sup> sC1R<sup>4</sup>

<sup>¼</sup> <sup>V</sup><sup>1</sup> R3 þ

V<sup>2</sup> � Vout R2

V<sup>1</sup> � Vout sC<sup>1</sup> ð Þ Vin � V<sup>1</sup> ð Þ¼ sC1R<sup>3</sup> V1ð Þþ sC1R<sup>1</sup> ð Þ V<sup>1</sup> � Vout R1R<sup>3</sup>

Vinð Þ¼ sC1R<sup>3</sup> V1ðsC1R<sup>1</sup> þ sC1R<sup>3</sup> þ R1R3Þ � Voutð Þ R1R<sup>3</sup>

¼ Vout

� Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup>

¼ Vout

 � <sup>V</sup>2ð Þ sC1R<sup>4</sup> ð Þ R2R<sup>4</sup> 

ð Þ sC1R<sup>1</sup> <sup>þ</sup> sC1R<sup>3</sup> <sup>þ</sup> <sup>R</sup>1R<sup>3</sup>

1 R4 þ sC<sup>4</sup>

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

(8)

http://dx.doi.org/10.5772/intechopen.73157

ðsC1R<sup>1</sup> þ sC1R<sup>3</sup> þ R1R3Þ � Voutð Þ R1R<sup>3</sup>

ð Þ 1 þ sC4R<sup>4</sup> R4

(9)

139

(10)

(11)

(12)

Figure 2. (a) Twin T network and (b) twin T network with buffered op-amp.

Figure 3. The Friend Biquad circuit.

### A. Appendix

The notch filter block diagram is analyzed with Kirchoff current law to prove that it is notch filter transfer function. There are two notch circuits in this appendix. The passive element has its own name without any duplication of names. The current is assumed to flow from left to right and flow from positive potential to ground. Also assume that all nodes in the circuit have positive potential except ground node.

$$\left(\frac{V\_{in} - V\_1}{R\_1}\right) = \frac{V\_1}{R\_3} + \frac{V\_1 - V\_{out}}{sC\_1} \tag{6}$$

$$\frac{V\_{in} - V\_2}{s\mathcal{C}\_2} = \frac{V\_2}{s\mathcal{C}\_3} + \frac{V\_2 - V\_{out}}{R\_2} \tag{7}$$

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology http://dx.doi.org/10.5772/intechopen.73157 139

$$\frac{V\_1 - V\_{out}}{s\mathbb{C}\_1} + \frac{V\_2 - V\_{out}}{R\_2} = V\_{out} \left(\frac{1}{R\_4} + s\mathbb{C}\_4\right) \tag{8}$$

$$\begin{aligned} \left(\frac{V\_{in} - V\_1}{R\_1}\right) &= \frac{V\_1}{R\_3} + \frac{V\_1 - V\_{out}}{s\mathbb{C}\_1} \\ (V\_{in} - V\_1)(s\mathbb{C}\_1 R\_3) &= V\_1(s\mathbb{C}\_1 R\_1) + (V\_1 - V\_{out})R\_1 R\_3 \\ V\_{in}(s\mathbb{C}\_1 R\_3) &= V\_1(s\mathbb{C}\_1 R\_1 + s\mathbb{C}\_1 R\_3 + R\_1 R\_3) - V\_{out}(R\_1 R\_3) \end{aligned} \tag{9}$$

Vin � V<sup>2</sup> sC<sup>2</sup> <sup>¼</sup> <sup>V</sup><sup>2</sup> sC<sup>3</sup> þ V<sup>2</sup> � Vout R2 ð Þ Vin � <sup>V</sup><sup>2</sup> sC3R<sup>2</sup> <sup>¼</sup> <sup>V</sup>2ð Þþ sC2R<sup>2</sup> ð Þ <sup>V</sup><sup>2</sup> � Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup> Vinð Þ¼ sC3R<sup>2</sup> <sup>V</sup><sup>2</sup> sC3R<sup>2</sup> <sup>þ</sup> sC2R<sup>2</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup> <sup>V</sup><sup>2</sup> <sup>¼</sup> Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup> sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s ð Þ <sup>2</sup>C2C<sup>3</sup> (10) V<sup>1</sup> � Vout sC<sup>1</sup> þ V<sup>2</sup> � Vout R2 ¼ Vout 1 R4 þ sC<sup>4</sup> ¼ Vout ð Þ 1 þ sC4R<sup>4</sup> R4 ð Þ V<sup>1</sup> � Vout R2R<sup>4</sup> þ ð Þ V<sup>2</sup> � Vout sC1R<sup>4</sup> ¼ Voutð Þ 1 þ sC4R<sup>4</sup> ð Þ sC1R<sup>2</sup> <sup>V</sup>1ð Þþ <sup>R</sup>2R<sup>4</sup> <sup>V</sup>2ð Þ¼ sC1R<sup>4</sup> Vout sC1R<sup>2</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>C4R4C1R<sup>2</sup> <sup>þ</sup> <sup>R</sup>2R<sup>4</sup> <sup>þ</sup> sC1R<sup>4</sup> <sup>V</sup><sup>1</sup> <sup>¼</sup> Vout <sup>s</sup><sup>2</sup>C4R4C1R<sup>2</sup> <sup>þ</sup> s C<sup>ð</sup> <sup>1</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>1R4Þ þ <sup>R</sup>2R<sup>4</sup> � <sup>V</sup>2ð Þ sC1R<sup>4</sup> ð Þ R2R<sup>4</sup> <sup>¼</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � <sup>V</sup>2ð Þ sC1R<sup>4</sup> ð Þ R2R<sup>4</sup> (11)

Substitute Eq. (11) into an Eq. (9):

A. Appendix

138 Very-Large-Scale Integration

Figure 3. The Friend Biquad circuit.

positive potential except ground node.

The notch filter block diagram is analyzed with Kirchoff current law to prove that it is notch filter transfer function. There are two notch circuits in this appendix. The passive element has its own name without any duplication of names. The current is assumed to flow from left to right and flow from positive potential to ground. Also assume that all nodes in the circuit have

> <sup>¼</sup> <sup>V</sup><sup>1</sup> R3 þ

<sup>¼</sup> <sup>V</sup><sup>2</sup> sC<sup>3</sup> þ V<sup>1</sup> � Vout sC<sup>1</sup>

V<sup>2</sup> � Vout R2

(6)

(7)

Vin � V<sup>1</sup> R1 

Figure 2. (a) Twin T network and (b) twin T network with buffered op-amp.

Vin � V<sup>2</sup> sC<sup>2</sup>

$$\begin{aligned} \left(\frac{V\_{in} - V\_1}{R\_1}\right) &= \frac{V\_1}{R\_3} + \frac{V\_1 - V\_{out}}{s\mathbf{C}\_1} \\ (V\_{in} - V\_1)(s\mathbf{C}\_1 R\_3) &= V\_1(s\mathbf{C}\_1 R\_1) + (V\_1 - V\_{out})R\_1 R\_3 \\ V\_{in}(s\mathbf{C}\_1 R\_3) &= V\_1(s\mathbf{C}\_1 R\_1 + s\mathbf{C}\_1 R\_3 + R\_1 R\_3) - V\_{out}(R\_1 R\_3) \\ V\_{in}(s\mathbf{C}\_1 R\_3) &= \begin{bmatrix} V\_{out}(s^2 a\_{21} + s a\_{11} + a\_{01}) - V\_2(s\mathbf{C}\_1 R\_4) \\ (R\_2 R\_4) \end{bmatrix} (s\mathbf{C}\_1 R\_1 + s\mathbf{C}\_1 R\_4) \\ V\_{in}(s\mathbf{C}\_1 R\_3)(s\mathbf{C}\_2 R\_4) &= \begin{bmatrix} V\_{out}(s^2 a\_{21} + s a\_{11} + a\_{01}) - V\_2(s\mathbf{C}\_1 R\_4) \end{bmatrix} (s\mathbf{C}\_1 R\_1 + s\mathbf{C}\_1 R\_3 + R\_1 R\_3) \\ -V\_{out}(R\_1 R\_3)(s\mathbf{R}\_2 R\_4) \\ V\_{in}(s\mathbf{a}\_{12}) &= V\_{out} \left[ (s^2 a\_{21} + s a\_{11} + a\_{01})(s(\mathbf{C}\_1 R\_1 + s\mathbf{C}\_1 R\_3) + R\_1 R\_3) - (R\_1 R\_3)(R\_2 R\_4) \right] \\ -V\_2(s\mathbf{C}\_1 R\_4)(s(\mathbf{C}\_1 R\_1 + \mathbf{C}\_1 R\_3) + R\_1 R\_3) \end{aligned} (12)$$

Substitute an Eq. (10) into an Eq. (12):

Vinð Þ¼ sa<sup>12</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � � �V2ð Þ sC1R<sup>4</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C1R3Þ þ R1R<sup>3</sup> Vinð Þ¼ sa<sup>12</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � � � Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup> � � sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s ð Þ <sup>2</sup>C2C<sup>3</sup> � �ð Þ sC1R<sup>4</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C1R3Þ þ R1R<sup>3</sup> Vinð Þ sa<sup>12</sup> s Cð Þ <sup>3</sup>R<sup>2</sup> þ C2R<sup>2</sup> <sup>þ</sup>s<sup>2</sup>C2C<sup>3</sup> ! <sup>¼</sup> Vout<sup>½</sup> <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ� <sup>R</sup>2R<sup>4</sup> sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s <sup>2</sup>C2C<sup>3</sup> � � � Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup> 2 ð Þ C2C<sup>3</sup> � � � � ð Þ sC1R<sup>4</sup> ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R<sup>3</sup> (13)

Vin <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � � <sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup> � � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup>

a<sup>35</sup> ¼ C2C3C1R4ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>25</sup> ¼ C2C3R1R<sup>3</sup>

Vout Vin

s

Vin � V<sup>1</sup> R1 � �

x<sup>2</sup> ¼ ð Þ sC2R<sup>1</sup>

x<sup>3</sup> ¼ ð Þ sC1R<sup>1</sup>

Vin <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � � <sup>¼</sup> Vout

KCL at V1:

a<sup>34</sup> ¼ ð Þ a12C2C<sup>3</sup> þ ð Þ C3R2C1R<sup>4</sup> ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>24</sup> ¼ a12ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> , a<sup>14</sup> ¼ C3R2R1R<sup>3</sup>

sa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup>

sa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup>

þa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup>

Vin � V1x<sup>1</sup> þ V2x<sup>2</sup> þ V4x<sup>3</sup> ¼ 0

x<sup>1</sup> ¼ ð Þ sC1R<sup>1</sup> þ sC2R<sup>1</sup> þ 1

<sup>¼</sup> <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � �

<sup>¼</sup> s s<sup>2</sup>a<sup>34</sup> <sup>þ</sup> sa<sup>24</sup> <sup>þ</sup> <sup>a</sup><sup>14</sup> � �

<sup>s</sup><sup>5</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>4</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup>

<sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>03C2C<sup>3</sup> � <sup>a</sup><sup>25</sup>

<sup>s</sup><sup>5</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>4</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup>

<sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>03C2C<sup>3</sup> � <sup>a</sup><sup>25</sup>

<sup>s</sup><sup>4</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>3</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup>

þs að Þ <sup>13</sup>ðC3R<sup>2</sup> þ C2R2Þ þ a03C2C<sup>3</sup> � a<sup>25</sup>

¼ ð Þ V<sup>1</sup> � V<sup>4</sup> sC<sup>1</sup> þ ð Þ V<sup>1</sup> � V<sup>2</sup> sC<sup>2</sup>

Vin � V<sup>1</sup> ¼ V1ðsC1R<sup>1</sup> þ sC2R1Þ � V2ð Þ� sC2R<sup>1</sup> V4ð Þ sC1R<sup>1</sup>

Vin ¼ V1ðsC1R<sup>1</sup> þ sC2R<sup>1</sup> þ 1Þ � V2ð Þ� sC2R<sup>1</sup> V4ð Þ sC1R<sup>1</sup>

<sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup>

<sup>þ</sup>s<sup>3</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup>

<sup>þ</sup>s<sup>3</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup>

� � � Vout <sup>s</sup><sup>3</sup>a<sup>35</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>25</sup> � �

http://dx.doi.org/10.5772/intechopen.73157

141

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

> > (16)

(17)

Vinð Þ sa<sup>12</sup> s Cð Þ <sup>3</sup>R<sup>2</sup> þ C2R<sup>2</sup> <sup>þ</sup>s<sup>2</sup>C2C<sup>3</sup> ! <sup>¼</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup> � �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � � � Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup> � � � � ð Þ sC1R<sup>4</sup> ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R<sup>3</sup> Vin <sup>s</sup><sup>3</sup>ð Þþ <sup>a</sup>12C2C<sup>3</sup> <sup>s</sup><sup>2</sup>a12ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> � � ¼ Vout <sup>s</sup><sup>3</sup>a21ðC1R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>s</sup><sup>2</sup> a21ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> þa11ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> 0 @ 1 A þs a ½ � ð Þ <sup>11</sup> ðR1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> Þ þ a01ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> þa01ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> 2 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 5 s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � � (14)

�Vin <sup>s</sup><sup>3</sup>ð Þ <sup>C</sup>3R2C1R<sup>4</sup> <sup>ð</sup>C1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ sC3R2R1R<sup>3</sup> � � � Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup> � � Vin <sup>s</sup><sup>3</sup>ð Þþ <sup>a</sup>12C2C<sup>3</sup> <sup>s</sup><sup>2</sup>a12ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> � � <sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup> � � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � � �Vin <sup>s</sup><sup>3</sup>ð Þ <sup>C</sup>3R2C1R<sup>4</sup> <sup>ð</sup>C1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ sC3R2R1R<sup>3</sup> � � � Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup> � �

a<sup>33</sup> ¼ a21ð Þ C1R<sup>1</sup> þ sC1R<sup>3</sup> , a<sup>23</sup> ¼ a21ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> þa11ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> 0 @ 1 A, a<sup>13</sup> ¼ ½ � ð Þ a<sup>11</sup> ðR1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> Þ þ a01ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> a<sup>03</sup> ¼ a01ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> Vin <sup>s</sup><sup>3</sup>ða12C2C<sup>3</sup> <sup>þ</sup> ð Þ <sup>C</sup>3R2C1R<sup>4</sup> ð Þ <sup>C</sup>1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R<sup>3</sup> Þ þ <sup>s</sup><sup>2</sup>a12ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ sC3R2R1R<sup>3</sup> � � <sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup> � � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � � �Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup> � � a<sup>34</sup> ¼ ð Þ a12C2C<sup>3</sup> þ ð Þ C3R2C1R<sup>4</sup> ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>24</sup> ¼ a12ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> , a<sup>14</sup> ¼ C3R2R1R<sup>3</sup> (15)

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology http://dx.doi.org/10.5772/intechopen.73157 141

Vin <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � � <sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup> � � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � � � Vout <sup>s</sup><sup>3</sup>a<sup>35</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>25</sup> � � a<sup>34</sup> ¼ ð Þ a12C2C<sup>3</sup> þ ð Þ C3R2C1R<sup>4</sup> ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>24</sup> ¼ a12ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> , a<sup>14</sup> ¼ C3R2R1R<sup>3</sup> a<sup>35</sup> ¼ C2C3C1R4ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>25</sup> ¼ C2C3R1R<sup>3</sup> Vin <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � � <sup>¼</sup> Vout <sup>s</sup><sup>5</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>4</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> <sup>þ</sup>s<sup>3</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup> <sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>03C2C<sup>3</sup> � <sup>a</sup><sup>25</sup> sa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> 2 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 5 Vout Vin <sup>¼</sup> <sup>s</sup><sup>3</sup>a<sup>34</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>24</sup> <sup>þ</sup> sa<sup>14</sup> � � <sup>s</sup><sup>5</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>4</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> <sup>þ</sup>s<sup>3</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup> <sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>03C2C<sup>3</sup> � <sup>a</sup><sup>25</sup> sa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> 2 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 5 <sup>¼</sup> s s<sup>2</sup>a<sup>34</sup> <sup>þ</sup> sa<sup>24</sup> <sup>þ</sup> <sup>a</sup><sup>14</sup> � � s <sup>s</sup><sup>4</sup>a33C2C<sup>3</sup> <sup>þ</sup> <sup>s</sup><sup>3</sup>ð Þ <sup>a</sup>23C2C<sup>3</sup> <sup>þ</sup> <sup>a</sup>33ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> <sup>þ</sup>s<sup>2</sup>ð Þ <sup>a</sup>23ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>a</sup>13ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ � <sup>a</sup><sup>35</sup> þs að Þ <sup>13</sup>ðC3R<sup>2</sup> þ C2R2Þ þ a03C2C<sup>3</sup> � a<sup>25</sup> þa03ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> 2 6 6 6 6 6 6 6 6 6 4 3 7 7 7 7 7 7 7 7 7 5 (16)

KCL at V1:

Vinð Þ¼ sa<sup>12</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup>

Vinð Þ¼ sa<sup>12</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup>

s Cð Þ <sup>3</sup>R<sup>2</sup> þ C2R<sup>2</sup>

s Cð Þ <sup>3</sup>R<sup>2</sup> þ C2R<sup>2</sup>

<sup>s</sup><sup>3</sup>a21ðC1R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>s</sup><sup>2</sup>

þa01ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup>

Vin <sup>s</sup><sup>3</sup>ð Þþ <sup>a</sup>12C2C<sup>3</sup> <sup>s</sup><sup>2</sup>a12ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup>

�Vin <sup>s</sup><sup>3</sup>ð Þ <sup>C</sup>3R2C1R<sup>4</sup> <sup>ð</sup>C1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ sC3R2R1R<sup>3</sup>

�Vin <sup>s</sup><sup>3</sup>ð Þ <sup>C</sup>3R2C1R<sup>4</sup> <sup>ð</sup>C1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ sC3R2R1R<sup>3</sup>

<sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup>

!

<sup>þ</sup>s<sup>2</sup>C2C<sup>3</sup>

s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup>

<sup>2</sup>C2C<sup>3</sup> � � � Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup>

!

<sup>þ</sup>s<sup>2</sup>C2C<sup>3</sup>

sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s

140 Very-Large-Scale Integration

Vinð Þ sa<sup>12</sup>

Vinð Þ sa<sup>12</sup>

¼ Vout

�V2ð Þ sC1R<sup>4</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C1R3Þ þ R1R<sup>3</sup>

� �

<sup>¼</sup> Vout<sup>½</sup> <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup>

<sup>¼</sup> Vout <sup>s</sup><sup>2</sup>a<sup>21</sup> <sup>þ</sup> sa<sup>11</sup> <sup>þ</sup> <sup>a</sup><sup>01</sup>

Vin <sup>s</sup><sup>3</sup>ð Þþ <sup>a</sup>12C2C<sup>3</sup> <sup>s</sup><sup>2</sup>a12ð Þ <sup>C</sup>3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R<sup>2</sup> � �

a21ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup>

� � � Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup>

� � � Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup>

0 @

a<sup>13</sup> ¼ ½ � ð Þ a<sup>11</sup> ðR1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> Þ þ a01ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup>

� � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup>

a<sup>34</sup> ¼ ð Þ a12C2C<sup>3</sup> þ ð Þ C3R2C1R<sup>4</sup> ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup> , a<sup>24</sup> ¼ a12ð Þ C3R<sup>2</sup> þ C2R<sup>2</sup> , a<sup>14</sup> ¼ C3R2R1R<sup>3</sup>

Vin <sup>s</sup><sup>3</sup>ða12C2C<sup>3</sup> <sup>þ</sup> ð Þ <sup>C</sup>3R2C1R<sup>4</sup> ð Þ <sup>C</sup>1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R<sup>3</sup> Þ þ <sup>s</sup><sup>2</sup>a12ðC3R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ sC3R2R1R<sup>3</sup> � �

� �

þa11ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup>

� Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup>

� � � Vinð Þþ sC3R<sup>2</sup> Vout <sup>s</sup><sup>2</sup>ð Þ <sup>C</sup>2C<sup>3</sup>

0 @

þs a ½ � ð Þ <sup>11</sup> ðR1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup> Þ þ a01ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup>

a<sup>33</sup> ¼ a21ð Þ C1R<sup>1</sup> þ sC1R<sup>3</sup> , a<sup>23</sup> ¼

a<sup>03</sup> ¼ a01ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup>

�Vout <sup>s</sup><sup>3</sup>C2C3C1R4ðC1R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>s</sup><sup>2</sup>C2C3R1R<sup>3</sup> � �

� � <sup>¼</sup> Vout <sup>s</sup><sup>3</sup>a<sup>33</sup> <sup>þ</sup> <sup>s</sup><sup>2</sup>a<sup>23</sup> <sup>þ</sup> sa<sup>13</sup> <sup>þ</sup> <sup>a</sup><sup>03</sup>

sC3R<sup>2</sup> þ sC2R<sup>2</sup> þ s ð Þ <sup>2</sup>C2C<sup>3</sup> � �

� �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � �

� �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � �

> 2 ð Þ C2C<sup>3</sup>

ð Þ sC1R<sup>4</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C1R3Þ þ R1R<sup>3</sup>

� � � � ð Þ sC1R<sup>4</sup> ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R<sup>3</sup>

� �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ <sup>R</sup>2R<sup>4</sup> � �

� � � � ð Þ sC1R<sup>4</sup> ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>1R3Þ þ <sup>R</sup>1R<sup>3</sup>

1 A

s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup> � �

� �

� �

1 A,

� �

� � s C<sup>ð</sup> <sup>3</sup>R<sup>2</sup> <sup>þ</sup> <sup>C</sup>2R2Þ þ <sup>s</sup><sup>2</sup>C2C<sup>3</sup>

a21ð Þ R1R<sup>3</sup> � ð Þ R1R<sup>3</sup> ð Þ R2R<sup>4</sup>

þa11ð Þ C1R<sup>1</sup> þ C1R<sup>3</sup>

� �ðs C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> sC1R3Þ þ <sup>R</sup>1R3Þ � ð Þ <sup>R</sup>1R<sup>3</sup> ð Þ� <sup>R</sup>2R<sup>4</sup>

(13)

(14)

(15)

$$\begin{aligned} \left(\frac{V\_{in} - V\_1}{R\_1}\right) &= (V\_1 - V\_4) \mathbf{s} \mathbf{C}\_1 + (V\_1 - V\_2) \mathbf{s} \mathbf{C}\_2 \\\\ V\_{in} - V\_1 &= V\_1 (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1 + \mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1) - V\_2 (\mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1) - V\_4 (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1) \\\\ V\_{in} &= V\_1 (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1 + \mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1 + 1) - V\_2 (\mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1) - V\_4 (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1) \\\\ V\_{in} - V\_1 \mathbf{x}\_1 + V\_2 \mathbf{x}\_2 + V\_4 \mathbf{x}\_3 &= 0 \\\\ \mathbf{x}\_1 &= (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1 + \mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1 + 1) \\\\ \mathbf{x}\_2 &= (\mathbf{s} \mathbf{C}\_2 \mathbf{R}\_1) \\\\ \mathbf{x}\_3 &= (\mathbf{s} \mathbf{C}\_1 \mathbf{R}\_1) \end{aligned} \tag{17}$$

KCL at V2:

$$\begin{aligned} V(V\_1 - V\_2) & \mathbf{s} \mathbf{C}\_2 = \left(\frac{V\_2 - V\_4}{R\_3}\right) + \frac{V\_2}{R\_4} \\ V\_1(\mathbf{s} \mathbf{C}\_2) &= V\_2 \left(\mathbf{s} \mathbf{C}\_2 + \frac{1}{R\_3} + \frac{1}{R\_4}\right) - V\_4 \left(\frac{1}{R\_3}\right) \\ V\_1(\mathbf{s} \mathbf{C}\_2) - V\_2 \mathbf{x}\_4 + V\_4 \mathbf{x}\_5 &= 0 \\ \mathbf{x}\_4 &= \left(s \mathbf{C}\_2 + \frac{1}{R\_3} + \frac{1}{R\_4}\right) \\ \mathbf{x}\_5 &= \left(\frac{1}{R\_3}\right) \end{aligned} \tag{18}$$

KCL at Vout:

Avð Þ¼ V<sup>3</sup> � V<sup>2</sup>

�V2Av þ V3Av þ

1 �x<sup>1</sup> x<sup>2</sup> 0 x<sup>3</sup> 0 0 sC<sup>2</sup> �x<sup>4</sup> 0 x<sup>5</sup> 0 x<sup>6</sup> 0 0 �x<sup>7</sup> x<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup>

<sup>x</sup><sup>12</sup> <sup>¼</sup> <sup>1</sup> R7

All of these equations can be written in matrix form as follows:

Substitute Eq. (23) into Eq. (19); we will get the following equation:

Vin ¼ V1x<sup>1</sup> � V2x<sup>2</sup> � V4x<sup>3</sup> Vinx<sup>6</sup> � V3x<sup>7</sup> þ V4x<sup>8</sup> ¼ 0

From Eq. (17), it can be rewritten as follows:

V<sup>1</sup> y<sup>1</sup>

� � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup>

y<sup>1</sup> ¼ ð Þ¼ x1x<sup>6</sup>

y<sup>2</sup> ¼ ð Þ¼ x2x<sup>6</sup>

y<sup>3</sup> ¼ ð Þ¼ x<sup>8</sup> � x3x<sup>6</sup>

All of these equations can be written in matrix form as follows:

Vout � V<sup>4</sup> R7

> V4 R7

�V2Av þ V3Av þ x12V<sup>4</sup> � x12Vout ¼ 0

Vin � V1x<sup>1</sup> þ V2x<sup>2</sup> þ V4x<sup>3</sup> ¼ 0 Vin ¼ V1x<sup>1</sup> � V2x<sup>2</sup> � V4x<sup>3</sup>

ð Þ V1x<sup>1</sup> � V2x<sup>2</sup> � V4x<sup>3</sup> x<sup>6</sup> � V3x<sup>7</sup> þ V4x<sup>8</sup> ¼ 0

� � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup>

ð Þ sC2R<sup>1</sup> R2

> 1 R6

V1ð Þ� x1x<sup>6</sup> V2ð Þ� x2x<sup>6</sup> V3x<sup>7</sup> þ V4ð Þ¼ x<sup>8</sup> � x3x<sup>6</sup> 0

½ � s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 R2

> � ð Þ sC1R<sup>1</sup> R2

� � <sup>¼</sup> <sup>0</sup>

<sup>¼</sup> <sup>R</sup><sup>2</sup> � ð Þ sC1R1R<sup>6</sup> R6R<sup>2</sup>

� Vout R7 ¼ 0

Vin V1 V2 V<sup>3</sup> V4 Vout

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

¼

http://dx.doi.org/10.5772/intechopen.73157

(21)

143

(22)

(23)

(24)

KCL at V3:

$$\begin{aligned} \left(\frac{V\_{in} - V\_3}{R\_2}\right) &= \frac{V\_3}{R\_5} + \left(\frac{V\_3 - V\_4}{R\_6}\right) \\ \frac{V\_{in}}{R\_2} &= V\_3 \left(\frac{1}{R\_2} + \frac{1}{R\_5} + \frac{1}{R\_6}\right) - V\_4 \left(\frac{1}{R\_6}\right) \\ V\_{in} \mathbf{x}\_6 - V\_3 \mathbf{x}\_7 + V\_4 \mathbf{x}\_8 &= \mathbf{0} \\ \mathbf{x}\_6 &= \frac{1}{R\_2} \\ \mathbf{x}\_7 &= \left(\frac{1}{R\_2} + \frac{1}{R\_5} + \frac{1}{R\_6}\right) \\ \mathbf{x}\_8 &= \left(\frac{1}{R\_6}\right) \end{aligned} \tag{19}$$

KCL at V4:

$$\begin{aligned} \frac{V\_3 - V\_4}{R\_6} + \left(\frac{V\_{out} - V\_4}{R\_7}\right) &= \frac{V\_4}{R\_8} \\ \frac{V\_3}{R\_6} - V\_4 \left(\frac{1}{R\_6} + \frac{1}{R\_7} + \frac{1}{R\_8}\right) + \frac{V\_{out}}{R\_7} &= 0 \\ V\_3 x\_9 - V\_4 x\_{10} + V\_{out} x\_{11} &= 0 \\ x\_9 &= \frac{1}{R\_6} \\ x\_{10} &= \left(\frac{1}{R\_6} + \frac{1}{R\_7} + \frac{1}{R\_8}\right) \\ x\_{11} &= \frac{1}{R\_7} \end{aligned} \tag{20}$$

KCL at Vout:

KCL at V2:

142 Very-Large-Scale Integration

KCL at V3:

KCL at V4:

ð Þ <sup>V</sup><sup>1</sup> � <sup>V</sup><sup>2</sup> sC<sup>2</sup> <sup>¼</sup> <sup>V</sup><sup>2</sup> � <sup>V</sup><sup>4</sup>

V1ð Þ� sC<sup>2</sup> V2x<sup>4</sup> þ V4x<sup>5</sup> ¼ 0

1 R3 þ 1 R4

> <sup>¼</sup> <sup>V</sup><sup>3</sup> R5 þ

1 R2 þ 1 R5 þ 1 R6

Vinx<sup>6</sup> � V3x<sup>7</sup> þ V4x<sup>8</sup> ¼ 0

V1ð Þ¼ sC<sup>2</sup> V<sup>2</sup> sC<sup>2</sup> þ

x<sup>4</sup> ¼ sC<sup>2</sup> þ

Vin � V<sup>3</sup> R2 

¼ V<sup>3</sup>

<sup>x</sup><sup>5</sup> <sup>¼</sup> <sup>1</sup> R3 

> Vin R2

<sup>x</sup><sup>6</sup> <sup>¼</sup> <sup>1</sup> R2

<sup>x</sup><sup>7</sup> <sup>¼</sup> <sup>1</sup> R2 þ 1 R5 þ 1 R6

<sup>x</sup><sup>8</sup> <sup>¼</sup> <sup>1</sup> R6 

V<sup>3</sup> � V<sup>4</sup> R6

<sup>x</sup><sup>9</sup> <sup>¼</sup> <sup>1</sup> R6

<sup>x</sup><sup>10</sup> <sup>¼</sup> <sup>1</sup> R6 þ 1 R7 þ 1 R8

<sup>x</sup><sup>11</sup> <sup>¼</sup> <sup>1</sup> R7

V3 R6 � V<sup>4</sup> þ

1 R6 þ 1 R7 þ 1 R8

V3x<sup>9</sup> � V4x<sup>10</sup> þ Voutx<sup>11</sup> ¼ 0

Vout � V<sup>4</sup> R7 

R3 

> 1 R3 þ 1 R4

þ V2 R4

V<sup>3</sup> � V<sup>4</sup> R6 

� V<sup>4</sup>

<sup>¼</sup> <sup>V</sup><sup>4</sup> R8

> þ Vout R7 ¼ 0

1 R6 

� V<sup>4</sup>

1 R3 

(18)

(19)

(20)

$$\begin{aligned} A\_v(V\_3 - V\_2) &= \frac{V\_{out} - V\_4}{R\_7} \\ -V\_2 A\_v + V\_3 A\_v + \frac{V\_4}{R\_7} - \frac{V\_{out}}{R\_7} &= 0 \\ -V\_2 A\_v + V\_3 A\_v + \mathbf{x}\_{12} V\_4 - \mathbf{x}\_{12} V\_{out} &= 0 \\ \mathbf{x}\_{12} &= \frac{1}{R\_7} \end{aligned} \tag{21}$$

All of these equations can be written in matrix form as follows:

$$
\begin{bmatrix}
1 & -x\_1 & x\_2 & 0 & x\_3 & 0 \\
0 & s\mathbb{C}\_2 & -x\_4 & 0 & x\_5 & 0 \\
x\_6 & 0 & 0 & -x\_7 & x\_8 & 0 \\
0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\
0 & 0 & -A\_v & A\_v & x\_{12} & x\_{12} \\
& & & & & \\
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_4 \\
V\_{out} \\
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix} \tag{22}
$$

From Eq. (17), it can be rewritten as follows:

$$\begin{aligned} V\_{in} - V\_1 \mathbf{x}\_1 + V\_2 \mathbf{x}\_2 + V\_4 \mathbf{x}\_3 &= \mathbf{0} \\ V\_{in} &= V\_1 \mathbf{x}\_1 - V\_2 \mathbf{x}\_2 - V\_4 \mathbf{x}\_3 \end{aligned} \tag{23}$$

Substitute Eq. (23) into Eq. (19); we will get the following equation:

$$\begin{aligned} V\_{in} &= V\_1 \mathbf{x}\_1 - V\_2 \mathbf{x}\_2 - V\_4 \mathbf{x}\_3 \\ V\_{in} \mathbf{x}\_6 - V\_3 \mathbf{x}\_7 + V\_4 \mathbf{x}\_8 = \mathbf{0} \\ (V\_1 \mathbf{x}\_1 - V\_2 \mathbf{x}\_2 - V\_4 \mathbf{x}\_3) \mathbf{x}\_6 - V\_3 \mathbf{x}\_7 + V\_4 \mathbf{x}\_8 = \mathbf{0} \\ V\_1 (\mathbf{x}\_1 \mathbf{x}\_6) - V\_2 (\mathbf{x}\_2 \mathbf{x}\_6) - V\_3 \mathbf{x}\_7 + V\_4 (\mathbf{x}\_8 - \mathbf{x}\_3 \mathbf{x}\_6) &= \mathbf{0} \\ V\_1 (\mathbf{y}\_1) - V\_2 (\mathbf{y}\_2) - V\_3 \mathbf{x}\_7 + V\_4 (\mathbf{y}\_3) &= \mathbf{0} \\ y\_1 = (\mathbf{x}\_1 \mathbf{x}\_6) &= \frac{[s(\mathbf{C}\_1 \mathbf{R}\_1 + \mathbf{C}\_2 \mathbf{R}\_1) + 1]}{R\_2} \\ y\_2 = (\mathbf{x}\_2 \mathbf{x}\_6) &= \frac{(s \mathbf{C}\_2 \mathbf{R}\_1)}{R\_2} \\ y\_3 = (\mathbf{x}\_8 - \mathbf{x}\_3 \mathbf{x}\_6) &= \frac{1}{R\_6} - \frac{(s \mathbf{C}\_1 \mathbf{R}\_1)}{R\_2} = \frac{R\_2 - (s \mathbf{C}\_1 \mathbf{R}\_1 \mathbf{R}\_6)}{R\_6 R\_2} \end{aligned} \tag{24}$$

All of these equations can be written in matrix form as follows:

$$
\begin{bmatrix}
1 & -\mathbf{x}\_1 & \mathbf{x}\_2 & \mathbf{0} & \mathbf{x}\_3 & \mathbf{0} \\
\mathbf{0} & s\mathbf{C}\_2 & -\mathbf{x}\_4 & \mathbf{0} & \mathbf{x}\_5 & \mathbf{0} \\
\mathbf{0} & y\_1 & -y\_2 & -\mathbf{x}\_7 & y\_3 & \mathbf{0} \\
\mathbf{0} & \mathbf{0} & \mathbf{0} & \mathbf{x}\_9 & -\mathbf{x}\_{10} & \mathbf{x}\_{11} \\
\mathbf{0} & \mathbf{0} & -A\_v & A\_v & \mathbf{x}\_{12} & \mathbf{x}\_{12} \\
\mathbf{0} & \mathbf{0} & \mathbf{0} & \mathbf{0} & \mathbf{0} & \mathbf{0}
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_{out}
\end{bmatrix} = \begin{bmatrix}
\mathbf{0} \\
\mathbf{0} \\
\mathbf{0} \\
\mathbf{0} \\
\mathbf{0} \\
\mathbf{0}
\end{bmatrix} \tag{25}
$$

From Eq. (18), it can be rewritten as follows:

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2x<sup>4</sup> � <sup>V</sup>4x<sup>5</sup> sC<sup>2</sup> � �

� � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup>

� y<sup>2</sup> � �

V2y<sup>7</sup> � V3x<sup>7</sup> þ V4y<sup>8</sup> ¼ 0

sC<sup>2</sup> þ

<sup>y</sup><sup>8</sup> <sup>¼</sup> <sup>y</sup><sup>3</sup> � <sup>x</sup>5y<sup>1</sup>

� y<sup>2</sup> � �

> 1 R3 þ 1 R4

� �

<sup>s</sup><sup>2</sup>C2ð Þþ <sup>C</sup>1R<sup>1</sup> s C<sup>2</sup> <sup>þ</sup>

sC<sup>2</sup> � �

All of these equations can be written in matrix form as follows:

V2x<sup>4</sup> � V4x<sup>5</sup> sC<sup>2</sup> � � <sup>y</sup><sup>1</sup>

> x4y<sup>1</sup> sC<sup>2</sup>

<sup>y</sup><sup>7</sup> <sup>¼</sup> <sup>x</sup>4y<sup>1</sup> sC<sup>2</sup>

V<sup>1</sup> y<sup>1</sup>

V2

y<sup>7</sup> ¼

¼

V1ð Þ� sC<sup>2</sup> V2x<sup>4</sup> þ V4x<sup>5</sup> ¼ 0

� � (29)

http://dx.doi.org/10.5772/intechopen.73157

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2x<sup>4</sup> � <sup>V</sup>4x<sup>5</sup> sC<sup>2</sup>

� � <sup>¼</sup> <sup>0</sup>

� � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup>

sC<sup>2</sup> � �

� � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup>

ðs Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1Þ � ð Þ sC2R<sup>1</sup> sC<sup>2</sup>

ð Þ C1R<sup>1</sup> þ C2R<sup>1</sup>

� <sup>1</sup> sC2R<sup>3</sup>

Vin V1 V2 V3 V4 Vout

¼

� � <sup>¼</sup> <sup>0</sup>

sC2R<sup>2</sup> � �

þ

1 R3 þ 1 R4 � �

½ � s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 R2 � �

� sC2R<sup>1</sup> R2 � �

(30)

145

(31)

¼ 0

Substitute Eq. (29) into Eq. (24); we will get the following equation:

� � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup>

� � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup>

¼ sC<sup>2</sup> þ

� <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup> � <sup>x</sup>5y<sup>1</sup>

1 R3 þ 1 R4

sC2R<sup>2</sup>

� �

sC2R<sup>2</sup>

1 R3 þ 1 R4 � �

<sup>¼</sup> <sup>R</sup><sup>2</sup> � ð Þ sC1R1R<sup>6</sup> R6R<sup>2</sup>

<sup>¼</sup> ð Þ <sup>R</sup><sup>2</sup> � ð Þ sC1R1R<sup>6</sup> sC2R<sup>3</sup> � <sup>R</sup>6ð Þ ½ � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> sC2R2R3R<sup>6</sup>

<sup>y</sup><sup>8</sup> <sup>¼</sup> �s<sup>2</sup>ðC1R1R6C2R3Þ þ s R<sup>ð</sup> <sup>2</sup>C2R<sup>3</sup> � <sup>R</sup>6C1R<sup>1</sup> � <sup>R</sup>6C2R1Þ � <sup>R</sup><sup>6</sup> sC2R2R3R<sup>6</sup>

> 1 0 y<sup>4</sup> �y<sup>5</sup> y<sup>6</sup> 0 0 sC<sup>2</sup> �x<sup>4</sup> 0 x<sup>5</sup> 0 0 0 y<sup>7</sup> �x<sup>7</sup> y<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup> 00 0 0 0 0

From Eq. (24), it can be rewritten as follows:

$$\begin{aligned} V\_1(y\_1) - V\_2(y\_2) - V\_3 \mathbf{x}\_7 + V\_4(y\_3) &= 0\\ V\_1 &= \left(\frac{V\_2 y\_2 + V\_3 \mathbf{x}\_7 - V\_4 y\_3}{y\_1}\right) \end{aligned} \tag{26}$$

Substitute Eq. (26) into Eq. (17); we will get the following equation:

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2y<sup>2</sup> <sup>þ</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>3</sup> y1 � � Vin � V1x<sup>1</sup> þ V2x<sup>2</sup> þ V4x<sup>3</sup> ¼ 0 Vin � <sup>V</sup>2y<sup>2</sup> <sup>þ</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>3</sup> y1 � �x<sup>1</sup> <sup>þ</sup> <sup>V</sup>2x<sup>2</sup> <sup>þ</sup> <sup>V</sup>4x<sup>3</sup> <sup>¼</sup> <sup>0</sup> Vin <sup>þ</sup> <sup>V</sup><sup>2</sup> <sup>x</sup><sup>2</sup> � <sup>y</sup>2x<sup>1</sup> y1 � � � V<sup>3</sup> x7x<sup>1</sup> y1 � � <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>x</sup><sup>3</sup> � <sup>y</sup>3x<sup>1</sup> y1 � � ¼ 0 Vin þ V2y<sup>4</sup> � V3y<sup>5</sup> þ V4y<sup>6</sup> ¼ 0 <sup>y</sup><sup>4</sup> <sup>¼</sup> <sup>x</sup><sup>2</sup> � <sup>y</sup>2x<sup>1</sup> y1 � � <sup>¼</sup> sC2R<sup>1</sup> � sC2R<sup>1</sup> R2 � � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � �ð Þ¼ R<sup>2</sup> 0 <sup>y</sup><sup>5</sup> <sup>¼</sup> <sup>x</sup>7x<sup>1</sup> y1 � � <sup>¼</sup> <sup>1</sup> R2 þ 1 R5 þ 1 R6 � � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � �R<sup>2</sup> <sup>¼</sup> <sup>R</sup><sup>2</sup> R2 þ R2 R5 þ R2 R6 � � <sup>y</sup><sup>6</sup> <sup>¼</sup> <sup>x</sup><sup>3</sup> � <sup>y</sup>3x<sup>1</sup> y1 � � <sup>¼</sup> sC1R<sup>1</sup> � <sup>R</sup><sup>2</sup> � sC1R1R<sup>6</sup> R6R<sup>2</sup> � � ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> <sup>R</sup><sup>2</sup> ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � � <sup>¼</sup> sC1R<sup>1</sup> � <sup>R</sup><sup>2</sup> � sC1R1R<sup>6</sup> R6 � � ¼ sð Þ� 2C1R<sup>1</sup> R2 R6 � � (27)

All of these equations can be written in matrix form as follows:

$$
\begin{bmatrix}
1 & 0 & y\_4 & -y\_5 & y\_6 & 0 \\
0 & s\mathbf{C}\_2 & -\mathbf{x}\_4 & 0 & \mathbf{x}\_5 & 0 \\
0 & y\_1 & -y\_2 & -\mathbf{x}\_7 & y\_3 & 0 \\
0 & 0 & 0 & \mathbf{x}\_9 & -\mathbf{x}\_{10} & \mathbf{x}\_{11} \\
0 & 0 & -A\_v & A\_v & \mathbf{x}\_{12} & \mathbf{x}\_{12} \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_{out}
\end{bmatrix} = 
\begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix}
\tag{28}
$$

From Eq. (18), it can be rewritten as follows:

1 �x<sup>1</sup> x<sup>2</sup> 0 x<sup>3</sup> 0 0 sC<sup>2</sup> �x<sup>4</sup> 0 x<sup>5</sup> 0 0 y<sup>1</sup> �y<sup>2</sup> �x<sup>7</sup> y<sup>3</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup> 00 0 0 0 0

� � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup>

x<sup>1</sup> þ V2x<sup>2</sup> þ V4x<sup>3</sup> ¼ 0

<sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>x</sup><sup>3</sup> � <sup>y</sup>3x<sup>1</sup>

� � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup>

s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � �

R6R<sup>2</sup>

¼ sð Þ� 2C1R<sup>1</sup>

y1 � �

s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � �

� � ð Þ s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> <sup>R</sup><sup>2</sup>

R2 R6 � �

> Vin V1 V2 V3 V4 Vout

¼

¼ 0

<sup>R</sup><sup>2</sup> <sup>¼</sup> <sup>R</sup><sup>2</sup> R2 þ R2 R5 þ R2 R6

ð Þ s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 � �

ð Þ¼ R<sup>2</sup> 0

� �

Vin V1 V2 V<sup>3</sup> V<sup>4</sup> Vout

� � <sup>¼</sup> <sup>0</sup>

� � (26)

¼

(25)

(27)

(28)

144 Very-Large-Scale Integration

From Eq. (24), it can be rewritten as follows:

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2y<sup>2</sup> <sup>þ</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>3</sup> y1 � �

Vin <sup>þ</sup> <sup>V</sup><sup>2</sup> <sup>x</sup><sup>2</sup> � <sup>y</sup>2x<sup>1</sup>

<sup>y</sup><sup>4</sup> <sup>¼</sup> <sup>x</sup><sup>2</sup> � <sup>y</sup>2x<sup>1</sup>

<sup>y</sup><sup>6</sup> <sup>¼</sup> <sup>x</sup><sup>3</sup> � <sup>y</sup>3x<sup>1</sup>

<sup>y</sup><sup>5</sup> <sup>¼</sup> <sup>x</sup>7x<sup>1</sup> y1 � �

Vin � V1x<sup>1</sup> þ V2x<sup>2</sup> þ V4x<sup>3</sup> ¼ 0 Vin � <sup>V</sup>2y<sup>2</sup> <sup>þ</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>3</sup> y1 � �

> y1 � �

Vin þ V2y<sup>4</sup> � V3y<sup>5</sup> þ V4y<sup>6</sup> ¼ 0

y1 � �

> <sup>¼</sup> <sup>1</sup> R2 þ 1 R5 þ 1 R6

y1 � �

<sup>¼</sup> sC1R<sup>1</sup> � <sup>R</sup><sup>2</sup> � sC1R1R<sup>6</sup>

All of these equations can be written in matrix form as follows:

V<sup>1</sup> y<sup>1</sup>

Substitute Eq. (26) into Eq. (17); we will get the following equation:

� V<sup>3</sup>

x7x<sup>1</sup> y1 � �

R2

� � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup>

<sup>¼</sup> sC1R<sup>1</sup> � <sup>R</sup><sup>2</sup> � sC1R1R<sup>6</sup>

<sup>¼</sup> sC2R<sup>1</sup> � sC2R<sup>1</sup>

R6 � �

1 0 y<sup>4</sup> �y<sup>5</sup> y<sup>6</sup> 0 0 sC<sup>2</sup> �x<sup>4</sup> 0 x<sup>5</sup> 0 0 y<sup>1</sup> �y<sup>2</sup> �x<sup>7</sup> y<sup>3</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup> 00 0 0 0 0

� � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup>

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2y<sup>2</sup> <sup>þ</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>3</sup> y1

$$\begin{aligned} V\_1(\mathbf{sC\_2}) - V\_2 \mathbf{x\_4} + V\_4 \mathbf{x\_5} &= \mathbf{0} \\ V\_1 &= \left( \frac{V\_2 \mathbf{x\_4} - V\_4 \mathbf{x\_5}}{s \mathbf{C\_2}} \right) \end{aligned} \tag{29}$$

Substitute Eq. (29) into Eq. (24); we will get the following equation:

<sup>V</sup><sup>1</sup> <sup>¼</sup> <sup>V</sup>2x<sup>4</sup> � <sup>V</sup>4x<sup>5</sup> sC<sup>2</sup> � � V<sup>1</sup> y<sup>1</sup> � � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup> � � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup> � � <sup>¼</sup> <sup>0</sup> V2x<sup>4</sup> � V4x<sup>5</sup> sC<sup>2</sup> � � <sup>y</sup><sup>1</sup> � � � <sup>V</sup><sup>2</sup> <sup>y</sup><sup>2</sup> � � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup> � � <sup>¼</sup> <sup>0</sup> V2 x4y<sup>1</sup> sC<sup>2</sup> � y<sup>2</sup> � � � <sup>V</sup>3x<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>3</sup> � <sup>x</sup>5y<sup>1</sup> sC<sup>2</sup> � � ¼ 0 V2y<sup>7</sup> � V3x<sup>7</sup> þ V4y<sup>8</sup> ¼ 0 <sup>y</sup><sup>7</sup> <sup>¼</sup> <sup>x</sup>4y<sup>1</sup> sC<sup>2</sup> � y<sup>2</sup> � � ¼ sC<sup>2</sup> þ 1 R3 þ 1 R4 � � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> sC2R<sup>2</sup> � � � sC2R<sup>1</sup> R2 � � y<sup>7</sup> ¼ sC<sup>2</sup> þ 1 R3 þ 1 R4 � �ðs Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1Þ � ð Þ sC2R<sup>1</sup> sC<sup>2</sup> sC2R<sup>2</sup> ¼ <sup>s</sup><sup>2</sup>C2ð Þþ <sup>C</sup>1R<sup>1</sup> s C<sup>2</sup> <sup>þ</sup> 1 R3 þ 1 R4 � �ð Þ C1R<sup>1</sup> þ C2R<sup>1</sup> � � þ 1 R3 þ 1 R4 � � sC2R<sup>2</sup> <sup>y</sup><sup>8</sup> <sup>¼</sup> <sup>y</sup><sup>3</sup> � <sup>x</sup>5y<sup>1</sup> sC<sup>2</sup> � � <sup>¼</sup> <sup>R</sup><sup>2</sup> � ð Þ sC1R1R<sup>6</sup> R6R<sup>2</sup> � <sup>1</sup> sC2R<sup>3</sup> ½ � s Cð <sup>1</sup>R<sup>1</sup> þ C2R1Þ þ 1 R2 � � <sup>¼</sup> ð Þ <sup>R</sup><sup>2</sup> � ð Þ sC1R1R<sup>6</sup> sC2R<sup>3</sup> � <sup>R</sup>6ð Þ ½ � s C<sup>ð</sup> <sup>1</sup>R<sup>1</sup> <sup>þ</sup> <sup>C</sup>2R1Þ þ <sup>1</sup> sC2R2R3R<sup>6</sup> <sup>y</sup><sup>8</sup> <sup>¼</sup> �s<sup>2</sup>ðC1R1R6C2R3Þ þ s R<sup>ð</sup> <sup>2</sup>C2R<sup>3</sup> � <sup>R</sup>6C1R<sup>1</sup> � <sup>R</sup>6C2R1Þ � <sup>R</sup><sup>6</sup> sC2R2R3R<sup>6</sup> (30)

All of these equations can be written in matrix form as follows:

$$
\begin{bmatrix}
1 & 0 & y\_4 & -y\_5 & y\_6 & 0 \\
0 & s\mathbf{C}\_2 & -\mathbf{x}\_4 & 0 & \mathbf{x}\_5 & 0 \\
0 & 0 & y\_7 & -\mathbf{x}\_7 & y\_8 & 0 \\
0 & 0 & 0 & \mathbf{x}\_9 & -\mathbf{x}\_{10} & \mathbf{x}\_{11} \\
0 & 0 & -A\_v & A\_v & \mathbf{x}\_{12} & \mathbf{x}\_{12} \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_4 \\
V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix}
\tag{31}
$$

From Eq. (30), it can be rewritten as follows:

$$\begin{aligned} V\_2 y\_7 - V\_3 x\_7 + V\_4 y\_8 &= 0\\ V\_2 &= \left(\frac{V\_3 x\_7 - V\_4 y\_8}{y\_7}\right) \end{aligned} \tag{32}$$

Update matrix in Eq. (34) by substituting Eq. (35) into as follows:

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (21):

�V2Av þ V3Av þ x12V<sup>4</sup> � x12Vout ¼ 0

� �Av <sup>þ</sup> <sup>V</sup>3Av <sup>þ</sup> <sup>x</sup>12V<sup>4</sup> � <sup>x</sup>12Vout <sup>¼</sup> <sup>0</sup>

<sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>x</sup><sup>12</sup> <sup>þ</sup> <sup>y</sup>8Av

V3x<sup>9</sup> � V4x<sup>10</sup> þ Voutx<sup>11</sup> ¼ 0

<sup>V</sup><sup>3</sup> <sup>¼</sup> <sup>V</sup>4x<sup>10</sup> � Voutx<sup>11</sup> x9

y7 � �

Vin V<sup>1</sup> V2 V3 V<sup>4</sup> Vout

� � (39)

� Voutx<sup>12</sup> ¼ 0

<sup>V</sup><sup>2</sup> <sup>¼</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>8</sup> y7 � �

� <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>8</sup> y7

<sup>V</sup><sup>3</sup> Av � <sup>x</sup>7Av

From Eq. (20), it can be rewritten as follows:

y7 � �

V3z<sup>1</sup> þ V4z<sup>2</sup> � Voutx<sup>12</sup> ¼ 0

1 0 0 y<sup>9</sup> y<sup>10</sup> 0 sC<sup>2</sup> 0 �y<sup>11</sup> y<sup>12</sup> 0 0 y<sup>7</sup> �x<sup>7</sup> y<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 0 z<sup>1</sup> z<sup>2</sup> �x<sup>12</sup> 00 0 0 0 0

Update matrix in Eq. (34) by substituting Eq. (37) into as follows:

1 0 0 y<sup>9</sup> y<sup>10</sup> 0 sC<sup>2</sup> 0 �y<sup>11</sup> y<sup>12</sup> 0 0 y<sup>7</sup> �x<sup>7</sup> y<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup>

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

Vin V1 V<sup>2</sup> V3 V4 Vout

http://dx.doi.org/10.5772/intechopen.73157

(36)

(37)

(38)

ð Þ 1:4 ð Þ 2:3 ð Þ 3:3

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (27):

$$\begin{aligned} V\_2 &= \left(\frac{V\_3 \mathbf{x}\_7 - V\_4 \mathbf{y}\_8}{y\_7}\right) \\ V\_{in} + V\_2 y\_4 - V\_3 y\_5 + V\_4 y\_6 &= 0 \\ V\_{in} + \left(\frac{V\_3 \mathbf{x}\_7 - V\_4 y\_8}{y\_7}\right) y\_4 - V\_3 y\_5 + V\_4 y\_6 &= 0 \\ V\_{in} + V\_3 \left(\frac{\mathbf{x}\_7 y\_4}{y\_7} - y\_5\right) + V\_4 \left(y\_6 - \frac{y\_8 y\_4}{y\_7}\right) &= 0 \\ V\_{in} + V\_3 y\_9 + V\_4 y\_{10} &= 0 \\ y\_9 &= \left(\frac{\mathbf{x}\_7 y\_4}{y\_7} - y\_5\right) \\ y\_{10} &= \left(y\_6 - \frac{y\_8 y\_4}{y\_7}\right) \end{aligned} \tag{33}$$

Update matrix in Eq. (31) by substituting Eq. (33) into as follows:

$$
\begin{bmatrix}
1 & 0 & 0 & y\_9 & y\_{10} & 0 \\
0 & s\mathbf{C}\_2 & -\mathbf{x}\_4 & 0 & \mathbf{x}\_5 & 0 \\
0 & 0 & y\_7 & -\mathbf{x}\_7 & y\_8 & 0 \\
0 & 0 & 0 & \mathbf{x}\_9 & -\mathbf{x}\_{10} & \mathbf{x}\_{11} \\
0 & 0 & -A\_v & A\_v & \mathbf{x}\_{12} & \mathbf{x}\_{12} \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_4 \\
V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix}
\tag{34}
$$

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (29):

$$\begin{aligned} V\_2 &= \left(\frac{V\_3 \mathbf{x}\_7 - V\_4 \mathbf{y}\_8}{y\_7}\right) \\ V\_1 (\mathbf{s} \mathbf{C}\_2) - V\_2 \mathbf{x}\_4 + V\_4 \mathbf{x}\_5 &= 0 \\ V\_1 (\mathbf{s} \mathbf{C}\_2) - \left(\frac{V\_3 \mathbf{x}\_7 - V\_4 \mathbf{y}\_8}{y\_7}\right) \mathbf{x}\_4 + V\_4 \mathbf{x}\_5 &= 0 \\ V\_1 (\mathbf{s} \mathbf{C}\_2) - V\_3 \left(\frac{\mathbf{x}\_7 \mathbf{x}\_4}{y\_7}\right) + V\_4 \left(\mathbf{x}\_5 + \frac{y\_5 \mathbf{x}\_4}{y\_7}\right) &= 0 \\ V\_1 (\mathbf{s} \mathbf{C}\_2) - V\_3 y\_{11} + V\_4 y\_{12} &= 0 \end{aligned} \tag{35}$$

Update matrix in Eq. (34) by substituting Eq. (35) into as follows:

From Eq. (30), it can be rewritten as follows:

Very-Large-Scale Integration

V2y<sup>7</sup> � V3x<sup>7</sup> þ V4y<sup>8</sup> ¼ 0 <sup>V</sup><sup>2</sup> <sup>¼</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>8</sup> y7

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (27):

<sup>V</sup><sup>2</sup> <sup>¼</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>8</sup> y7 � �

Vin þ

Vin þ V<sup>3</sup>

<sup>y</sup><sup>9</sup> <sup>¼</sup> <sup>x</sup>7y<sup>4</sup> y7

<sup>y</sup><sup>10</sup> <sup>¼</sup> <sup>y</sup><sup>6</sup> � <sup>y</sup>8y<sup>4</sup>

Update matrix in Eq. (31) by substituting Eq. (33) into as follows:

Vin þ V2y<sup>4</sup> � V3y<sup>5</sup> þ V4y<sup>6</sup> ¼ 0

� y<sup>5</sup> � �

V3x<sup>7</sup> � V4y<sup>8</sup> y7 � �

> x7y<sup>4</sup> y7

Vin þ V3y<sup>9</sup> þ V4y<sup>10</sup> ¼ 0

� y<sup>5</sup> � �

y7 � �

1 0 0 y<sup>9</sup> y<sup>10</sup> 0 sC<sup>2</sup> �x<sup>4</sup> 0 x<sup>5</sup> 0 0 y<sup>7</sup> �x<sup>7</sup> y<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 �Av Av x<sup>12</sup> x<sup>12</sup> 00 0 0 0 0

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (29):

<sup>V</sup><sup>2</sup> <sup>¼</sup> <sup>V</sup>3x<sup>7</sup> � <sup>V</sup>4y<sup>8</sup> y7 � �

V1ð Þ� sC<sup>2</sup>

V1ð Þ� sC<sup>2</sup> V<sup>3</sup>

V1ð Þ� sC<sup>2</sup> V2x<sup>4</sup> þ V4x<sup>5</sup> ¼ 0

V3x<sup>7</sup> � V4y<sup>8</sup> y7 � �

> x7x<sup>4</sup> y7 � �

V1ð Þ� sC<sup>2</sup> V3y<sup>11</sup> þ V4y<sup>12</sup> ¼ 0

� � (32)

y<sup>4</sup> � V3y<sup>5</sup> þ V4y<sup>6</sup> ¼ 0

y7 � �

0

(33)

(34)

(35)

<sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>6</sup> � <sup>y</sup>8y<sup>4</sup>

x<sup>4</sup> þ V4x<sup>5</sup> ¼ 0

y7 � �

0

<sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>x</sup><sup>5</sup> <sup>þ</sup> <sup>y</sup>8x<sup>4</sup>

Vin V1 V2 V3 V4 Vout

$$
\begin{bmatrix} (1.4) \\ (2.3) \\ (3.3) \\ (3.3) \\ \\ \\ \\ \\ \\ \end{bmatrix} \begin{bmatrix} 1 & 0 & 0 & y\_9 & y\_{10} & 0 \\ 0 & s\mathcal{C}\_2 & 0 & -y\_{11} & y\_{12} & 0 \\ 0 & 0 & y\_7 & -x\_7 & y\_8 & 0 \\ 0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\ 0 & 0 & -A\_v & A\_v & x\_{12} & x\_{12} \\ \\ \\ \end{bmatrix} \begin{bmatrix} V\_{in} \\ V\_1 \\ V\_2 \\ V\_3 \\ V\_4 \\ V\_5 \\ V\_6 \\ \end{bmatrix} = \begin{bmatrix} 0 \\ 0 \\ 0 \\ 0 \\ 0 \\ 0 \\ 0 \\ \end{bmatrix} \tag{36}
$$

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (21):

$$\begin{aligned} V\_2 &= \left(\frac{V\_{3\Upsilon\tau} - V\_4 y\_8}{y\_7}\right) \\ &- V\_2 A\_v + V\_3 A\_v + \mathbf{x}\_{12} V\_4 - \mathbf{x}\_{12} V\_{out} = 0 \\ &- \left(\frac{V\_3 \mathbf{x}\_7 - V\_4 y\_8}{y\_7}\right) A\_v + V\_3 A\_v + \mathbf{x}\_{12} V\_4 - \mathbf{x}\_{12} V\_{out} = 0 \\ &\\ V\_3 \left(A\_v - \frac{\mathbf{x}\_7 A\_v}{y\_7}\right) + V\_4 \left(\mathbf{x}\_{12} + \frac{y\_8 A\_v}{y\_7}\right) - V\_{out} \mathbf{x}\_{12} = 0 \end{aligned} \tag{37}$$
  $V\_3 \mathbf{z}\_1 + V\_4 \mathbf{z}\_2 - V\_{out} \mathbf{x}\_{12} = 0$ 

Update matrix in Eq. (34) by substituting Eq. (37) into as follows:

$$
\begin{bmatrix}
1 & 0 & 0 & y\_9 & y\_{10} & 0 \\
0 & s\mathbf{C}\_2 & 0 & -y\_{11} & y\_{12} & 0 \\
0 & 0 & y\_7 & -x\_7 & y\_8 & 0 \\
0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\
0 & 0 & 0 & z\_1 & z\_2 & -x\_{12} \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_4 \\
V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix}
\tag{38}
$$

From Eq. (20), it can be rewritten as follows:

$$\begin{aligned} V\_3 \mathbf{x}\_9 - V\_4 \mathbf{x}\_{10} + V\_{out} \mathbf{x}\_{11} &= 0\\ V\_3 = \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) \end{aligned} \tag{39}$$

Substitute Eq. (39) into Eq. (37); we will get the following equation:

$$\begin{aligned} V\_3 &= \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) \\ V\_3 z\_1 &+ V\_4 z\_2 - V\_{out} \mathbf{x}\_{12} = 0 \\ &\left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) z\_1 + V\_4 z\_2 - V\_{out} \mathbf{x}\_{12} = 0 \\ V\_4 \left(\frac{\mathbf{x}\_{10} z\_1}{\mathbf{x}\_9} + z\_2\right) - V\_{out} \left(\frac{\mathbf{x}\_{11} z\_1}{\mathbf{x}\_9} + \mathbf{x}\_{12}\right) &= 0 \\ V\_4 z\_3 - V\_{out} z\_4 &= 0 \end{aligned} \tag{40}$$

Substitute Eq. (39) into Eq. (33); we will get the following equation:

Vin þ

Vin þ V<sup>4</sup>

Update matrix in Eq. (43) by substituting Eq. (44) into as follows:

Substitute Eq. (37) into Eq. (44); we will get the following equation:

Author details

Kittipong Tripetch

Address all correspondence to: kan1972@a2.keio.jp

Rajamangala University of Technology Suvarnabhumi, Japan

<sup>V</sup><sup>3</sup> <sup>¼</sup> <sup>V</sup>4x<sup>10</sup> � Voutx<sup>11</sup> x9 � �

Vin þ V3y<sup>9</sup> þ V4y<sup>10</sup> ¼ 0

x10y<sup>9</sup> x9

Vin þ V4z<sup>7</sup> � Voutz<sup>8</sup> ¼ 0

1 0 0 0 z<sup>7</sup> �z<sup>8</sup> sC<sup>2</sup> 0 �y<sup>11</sup> y<sup>12</sup> 0 0 y<sup>7</sup> 0 z<sup>5</sup> z<sup>6</sup> 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 0 0 z<sup>3</sup> �z<sup>4</sup> 00 0 0 0 0

V4z<sup>3</sup> � Voutz<sup>4</sup> ¼ 0

z4 z3 � �

Vin þ V4z<sup>7</sup> � Voutz<sup>8</sup> ¼ 0

z4 z3

z4z<sup>7</sup> z3 � z<sup>8</sup> � �

Vin <sup>þ</sup> Voutz<sup>9</sup> <sup>¼</sup> <sup>0</sup> ! Vout

� �z<sup>7</sup> � Voutz<sup>8</sup> <sup>¼</sup> <sup>0</sup>

0

¼ � <sup>1</sup> z9

Vin

V<sup>4</sup> ¼ Vout

Vin þ Vout

Vin þ Vout

V4x<sup>10</sup> � Voutx<sup>11</sup> x9

� �y<sup>9</sup> <sup>þ</sup> <sup>V</sup>4y<sup>10</sup> <sup>¼</sup> <sup>0</sup>

x11y<sup>9</sup> x9 � �

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

Vin V1 V2 V3 V4 Vout

http://dx.doi.org/10.5772/intechopen.73157

0

(44)

(45)

(46)

<sup>þ</sup> <sup>y</sup><sup>10</sup> � � � Vout

Update matrix in Eq. (36) by substituting Eq. (40) into as follows:

$$
\begin{bmatrix}
1 & 0 & 0 & y\_9 & y\_{10} & 0 \\
0 & s\mathbf{C}\_2 & 0 & -y\_{11} & y\_{12} & 0 \\
0 & 0 & y\_7 & -x\_7 & y\_8 & 0 \\
0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\
0 & 0 & 0 & 0 & z\_3 & -z\_4 \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\
V\_1 \\
V\_2 \\
V\_3 \\
V\_4 \\
V\_4 \\
V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0 \\
0 \\
0 \\
0 \\
0
\end{bmatrix} \tag{41}
$$

Substitute Eq. (39) into Eq. (30); we will get the following equation:

$$\begin{aligned} V\_3 &= \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) \\ V\_2 y\_7 &- V\_3 \mathbf{x}\_7 + V\_4 y\_8 = 0 \\ V\_2 y\_7 &- \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) \mathbf{x}\_7 + V\_4 y\_8 = 0 \\ V\_2 y\_7 &+ V\_4 \left(y\_8 - \frac{\mathbf{x}\_{10} \mathbf{x}\_7}{\mathbf{x}\_9}\right) + V\_{out} \left(\frac{\mathbf{x}\_{11} \mathbf{x}\_7}{\mathbf{x}\_9}\right) = 0 \\ V\_2 y\_7 + V\_4 z\_5 + V\_{out} z\_6 &= 0 \end{aligned} \tag{42}$$

Update matrix in Eq. (41) by substituting Eq. (40) into as follows:

$$
\begin{bmatrix}
1 & 0 & 0 & y\_9 & y\_{10} & 0 \\
0 & s\mathbb{C}\_2 & 0 & -y\_{11} & y\_{12} & 0 \\
0 & 0 & y\_7 & 0 & z\_5 & z\_6 \\
0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\
0 & 0 & 0 & 0 & z\_3 & -z\_4 \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\ V\_1 \\ V\_2 \\ V\_3 \\ V\_4 \\ V\_4 \\ V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\ 0 \\ 0 \\ 0 \\ 0 \\ 0 \\ 0
\end{bmatrix} \tag{43}
$$

Substitute Eq. (39) into Eq. (33); we will get the following equation:

$$\begin{aligned} V\_3 &= \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) \\ V\_{in} + V\_3 y\_9 + V\_4 y\_{10} &= 0 \\ V\_{in} + \left(\frac{V\_4 \mathbf{x}\_{10} - V\_{out} \mathbf{x}\_{11}}{\mathbf{x}\_9}\right) y\_9 + V\_4 y\_{10} &= 0 \\ V\_{in} + V\_4 \left(\frac{\mathbf{x}\_{10} y\_9}{\mathbf{x}\_9} + y\_{10}\right) - V\_{out} \left(\frac{\mathbf{x}\_{11} y\_9}{\mathbf{x}\_9}\right) &= 0 \\ V\_{in} + V\_4 z\_7 - V\_{out} z\_8 &= 0 \end{aligned} \tag{44}$$

Update matrix in Eq. (43) by substituting Eq. (44) into as follows:

$$
\begin{bmatrix}
1 & 0 & 0 & 0 & z\_7 & -z\_8 \\
0 & s\mathbf{C}\_2 & 0 & -y\_{11} & y\_{12} & 0 \\
0 & 0 & y\_7 & 0 & z\_5 & z\_6 \\
0 & 0 & 0 & x\_9 & -x\_{10} & x\_{11} \\
0 & 0 & 0 & 0 & z\_3 & -z\_4 \\
0 & 0 & 0 & 0 & 0 & 0
\end{bmatrix}
\begin{bmatrix}
V\_{in} \\ V\_1 \\ V\_2 \\ V\_3 \\ V\_4 \\ V\_{out}
\end{bmatrix} = \begin{bmatrix}
0 \\ 0 \\ 0 \\ 0 \\ 0 \\ 0
\end{bmatrix}
\tag{45}
$$

Substitute Eq. (37) into Eq. (44); we will get the following equation:

$$\begin{aligned} V\_4z\_3 - V\_{out}z\_4 &= 0\\ V\_4 &= V\_{out} \left(\frac{z\_4}{z\_3}\right) \\ V\_{in} + V\_4z\_7 - V\_{out}z\_8 &= 0\\ V\_{in} + V\_{out} \left(\frac{z\_4}{z\_3}\right)z\_7 - V\_{out}z\_8 &= 0\\ V\_{in} + V\_{out} \left(\frac{z\_4z\_7}{z\_3} - z\_8\right) &= 0\\ V\_{in} + V\_{out}z\_9 &= 0 \rightarrow \frac{V\_{out}}{V\_{in}} = -\frac{1}{z\_9} \end{aligned} \tag{46}$$

### Author details

Substitute Eq. (39) into Eq. (37); we will get the following equation:

<sup>V</sup><sup>3</sup> <sup>¼</sup> <sup>V</sup>4x<sup>10</sup> � Voutx<sup>11</sup> x9 � �

V4x<sup>10</sup> � Voutx<sup>11</sup> x9 � �

V4z<sup>3</sup> � Voutz<sup>4</sup> ¼ 0

x10z<sup>1</sup> x9

Update matrix in Eq. (36) by substituting Eq. (40) into as follows:

Substitute Eq. (39) into Eq. (30); we will get the following equation:

<sup>V</sup><sup>3</sup> <sup>¼</sup> <sup>V</sup>4x<sup>10</sup> � Voutx<sup>11</sup> x9 � �

V2y<sup>7</sup> � V3x<sup>7</sup> þ V4y<sup>8</sup> ¼ 0 <sup>V</sup>2y<sup>7</sup> � <sup>V</sup>4x<sup>10</sup> � Voutx<sup>11</sup>

<sup>V</sup>2y<sup>7</sup> <sup>þ</sup> <sup>V</sup><sup>4</sup> <sup>y</sup><sup>8</sup> � <sup>x</sup>10x<sup>7</sup>

Update matrix in Eq. (41) by substituting Eq. (40) into as follows:

V2y<sup>7</sup> þ V4z<sup>5</sup> þ Voutz<sup>6</sup> ¼ 0

1 0 0 y<sup>9</sup> y<sup>10</sup> 0 sC<sup>2</sup> 0 �y<sup>11</sup> y<sup>12</sup> 0 0 y<sup>7</sup> 0 z<sup>5</sup> z<sup>6</sup> 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 0 0 z<sup>3</sup> �z<sup>4</sup> 00 0 0 0 0

x9 � �

> x9 � �

V4

Very-Large-Scale Integration

V3z<sup>1</sup> þ V4z<sup>2</sup> � Voutx<sup>12</sup> ¼ 0

þ z<sup>2</sup> � �

1 0 0 y<sup>9</sup> y<sup>10</sup> 0 sC<sup>2</sup> 0 �y<sup>11</sup> y<sup>12</sup> 0 0 y<sup>7</sup> �x<sup>7</sup> y<sup>8</sup> 0 00 0 x<sup>9</sup> �x<sup>10</sup> x<sup>11</sup> 0 0 0 0 z<sup>3</sup> �z<sup>4</sup> 00 0 0 0 0

� Vout

z<sup>1</sup> þ V4z<sup>2</sup> � Voutx<sup>12</sup> ¼ 0

x<sup>7</sup> þ V4y<sup>8</sup> ¼ 0

x11x<sup>7</sup> x9 � �

> Vin V1 V2 V3 V4 Vout

0

þ Vout

Vin V1 V2 V3 V4 Vout

þ x<sup>12</sup> � �

0

(40)

(41)

(42)

(43)

x11z<sup>1</sup> x9

Kittipong Tripetch

Address all correspondence to: kan1972@a2.keio.jp

Rajamangala University of Technology Suvarnabhumi, Japan

### References


References

150 Very-Large-Scale Integration

2008;2(1):38-47

Image Rejection. I-473-476

States: Mcgraw-Hill; 2004

adaptive filter and notch filter. In: ICEEICT. 2014

Journal of Solid-State Circuits. February 2009;44(2):331-343

transconductance adjustment. In: ISCAS89. pp. 663-666

[1] Borio D, Camoriano L, Presti LL. Two-pole and multi pole notch filters: A computationally effective solution for GNSS interference detection and mitigation. IEEE Systems Journal.

[2] Biswas U, Maniruzzaman Md. Removing power line interference from ECG signal using

[3] Parthasarathy J, Harjani R. Novel Integratable Notch Filter Implementation for 100 dB

[4] Valeese A, Bevilacqua A, Sandner C, Tiebout M, Gerosa A, Neviani A. Analysis and Design of an Integrated Notch Filter for the rejection of interference in UWB systems. IEEE

[5] Adams WJ, Nedungadi A, Geiger RL. Design of a programmable OTA with multi decade

[6] Hodges DA, Jackson HG. Analysis and Design of Digital Integrated Circuit. 3rd ed. United

[7] Daryanani G. Principle of Active Network Synthesis and Design. Singapore: Wiley; 1976

*Edited by Kim Ho Yeap and Humaira Nisar*

In this book, a variety of topics related to Very-Large-Scale Integration (VLSI) is extensively discussed. The topics encompass the physics of VLSI transistors, the process of integrated chip design and fabrication and the applications of VLSI devices. It is intended to provide information on the latest advancement of VLSI technology to researchers, physicists as well as engineers working in the field of semiconductor manufacturing and VLSI design.

Very-Large-Scale Integration

Very-Large-Scale Integration

*Edited by Kim Ho Yeap and Humaira Nisar*

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