**IC Design and Fabrication**

**Chapter 3**

Provisional chapter

**Low Power Design Methodology**

Low Power Design Methodology

Nagarajan Pandian and Vinoth Gopi Savithri

Nagarajan Pandian and Vinoth Gopi Savithri

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.73729

low power dissipation, VLSI

Abstract

1. Introduction

Vithyalakshmi Natarajan, Ashok Kumar Nagarajan,

Due to widespread application of portable electronic devices and the evaluation of microelectronic technology, power dissipation has become a critical parameter in low power VLSI circuit designs. In emerging VLSI technology, the circuit complexity and high speed imply significant increase in the power consumption. In low power CMOS VLSI circuits, the energy dissipation is caused by charging and discharging of internal node capacitances due to transition activity, which is one of the major factors that also affect the dynamic power dissipation. The reduction in power, area and the improvement of speed require optimization at all levels of design procedures. Here various design methodolo-

DOI: 10.5772/intechopen.73729

gies are discussed to achieve our required low power design concepts.

increase the area and power consumption of the circuit (Figure 1).

Keywords: power modeling, switching activity, self-transition, coupling transition,

As VLSI technology advances, the complexity and speed circuit increase, resulting in high power consumption. In VLSI design, small area and high performance are two conflicting constraints. The integrated circuit (IC) designer's activities have been involved in trading of these constraints. There are many possible design considerations, due to which the power efficiency has become important. The most portable systems used in recent era, which are powered by batteries, are performing tasks requiring lots of computations. The most important aspect of Moore's Law is that it has become a universal predictor for the growth of the entire semiconductor industry. From Moore's law, it is understood that the number of devices in a chip doubles every 18 months. This will increase the number of transistors used and hence

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited.

> © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Vithyalakshmi Natarajan, Ashok Kumar Nagarajan,

#### **Low Power Design Methodology** Low Power Design Methodology

Vithyalakshmi Natarajan, Ashok Kumar Nagarajan, Nagarajan Pandian and Vinoth Gopi Savithri Vithyalakshmi Natarajan, Ashok Kumar Nagarajan, Nagarajan Pandian and Vinoth Gopi Savithri

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.73729

#### Abstract

Due to widespread application of portable electronic devices and the evaluation of microelectronic technology, power dissipation has become a critical parameter in low power VLSI circuit designs. In emerging VLSI technology, the circuit complexity and high speed imply significant increase in the power consumption. In low power CMOS VLSI circuits, the energy dissipation is caused by charging and discharging of internal node capacitances due to transition activity, which is one of the major factors that also affect the dynamic power dissipation. The reduction in power, area and the improvement of speed require optimization at all levels of design procedures. Here various design methodologies are discussed to achieve our required low power design concepts.

DOI: 10.5772/intechopen.73729

Keywords: power modeling, switching activity, self-transition, coupling transition, low power dissipation, VLSI

### 1. Introduction

As VLSI technology advances, the complexity and speed circuit increase, resulting in high power consumption. In VLSI design, small area and high performance are two conflicting constraints. The integrated circuit (IC) designer's activities have been involved in trading of these constraints. There are many possible design considerations, due to which the power efficiency has become important. The most portable systems used in recent era, which are powered by batteries, are performing tasks requiring lots of computations. The most important aspect of Moore's Law is that it has become a universal predictor for the growth of the entire semiconductor industry. From Moore's law, it is understood that the number of devices in a chip doubles every 18 months. This will increase the number of transistors used and hence increase the area and power consumption of the circuit (Figure 1).

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and eproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Figure 1. Graphical representation of Moore's law.

#### 1.1. Need for low power design

Power dissipation is the main constraint when it comes to portability. Hence, it is necessary to take care of the system's total power consumption. Minimizing the overall power consumption in such devices is essential because it is advantageous to exploit the run time with least possible requirements on weight, battery life and size owed to batteries. Therefore, in portable devices, 'the low power design is the most decisive factor to think while designing system on chip. Normally, mobile users demand additional features and prolonged battery life at a lower cost. Almost 70% of users look for longer talk time and standby time as key feature for mobile phones. One of the top operator requirements in 4G is Power efficiency. Customers always look for smaller, trim and graceful mobile devices. This is the need of high levels of silicon integration in modern processes, but sophisticated processes have intrinsically higher power indulgence. So, design is very important in low power consumption devices.

#### 1.2. Impact of power dissipation

Whenever there is power dissipation, it unvaryingly leads to an increase in chip temperature. This temperature rise affects devices when it is switched on and off. With device in OFF condition, power dissipation increases the number of intrinsic carriers ni provided by the below relation:

$$\mathbf{a}\_{\mathrm{i}} \; \mathbf{a} \; \mathbf{e} \; \mathrm{e}^{-\mathrm{E}} \; \mathrm{G}^{\mathrm{V}} \; \mathrm{T} \tag{1}$$

minority carrier, but will be affected by the threshold voltage (VT) and mobility (μ). These parameters decrease with increase in temperature and this leads to change in drain current (ID). Hence the device performance might not meet the required specifications. Also, power dissipation is more critical in battery-powered applications as the greater power dissipated,

Heat sinks are used to dissipate heat generated by power dissipation. The thermal resistance of heat sink is lower than that of the package. So heat sink draws the heat. To eliminate heat efficiently, the rate of heat transferred to the environment should be greater than heat generated. This heat transfer rate depends on thermal resistance θ, as provided by the below relation:

From the above relation, it can be seen that large σc implies smaller θ. θ is also given by the relation

Θ ≤ Tj–Ta

Historically, VLSI designers have used circuit speed as the performance metric. In fact, power considerations have been the ultimate design criteria in special portable applications. The main aim of these applications was maximum battery life time, with minimum power. Low power design is also required to reduce the power in high-end systems with huge integration density

To optimize power dissipation specifically with low power methodology in digital systems, the method should be applied all over the design from system to process level. It is very important to have knowledge about the power distribution. So the blocks or parts consuming fraction of power could be clearly optimized for saving power. Different design levels specif-

Minimizing the supply voltage of a device is one of the best solutions to reduce power dissipation. The trade-off of this approach is that delay may increase significantly, when VDD

l is the length, A is the area and σc is the thermal conductivity of the heat sink.

Using this relation, we can see that for a given power dissipation, PD

where Tj is the junction temperature and Ta is the ambient temperature. Heat sink materials are generally coated black to radiate more energy.

Θ ¼ l=σ<sup>C</sup> A (2)

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Θ ¼ δ T=δ P (3)

=PD (4)

the battery life will be less.

where:

1.3. Reduction of temperature

1.4. Low power design methodology

and thus improve the speed of operation.

ically of power reduction are shown in Figure 2.

1.4.1. Power reduction through process technology

From the above equation, it is very clear that when temperature increases, intrinsic carriers also increase. With temperature increase, the less affected ones are the majority carriers which are contributed by impurity atoms. As the temperature increases further, the leakage current that depends on the concentration of the minority carrier, increases which leads to further increase in temperature. Ultimately, the device might break down, if the dissipated heat is not removed properly. An ON device will not be affected much by the increase of minority carrier, but will be affected by the threshold voltage (VT) and mobility (μ). These parameters decrease with increase in temperature and this leads to change in drain current (ID). Hence the device performance might not meet the required specifications. Also, power dissipation is more critical in battery-powered applications as the greater power dissipated, the battery life will be less.

### 1.3. Reduction of temperature

Heat sinks are used to dissipate heat generated by power dissipation. The thermal resistance of heat sink is lower than that of the package. So heat sink draws the heat. To eliminate heat efficiently, the rate of heat transferred to the environment should be greater than heat generated. This heat transfer rate depends on thermal resistance θ, as provided by the below relation:

$$
\Theta = \text{l/} \sigma\_{\mathbb{C}} \text{ A} \tag{2}
$$

where:

1.1. Need for low power design

48 Very-Large-Scale Integration

Figure 1. Graphical representation of Moore's law.

1.2. Impact of power dissipation

below relation:

Power dissipation is the main constraint when it comes to portability. Hence, it is necessary to take care of the system's total power consumption. Minimizing the overall power consumption in such devices is essential because it is advantageous to exploit the run time with least possible requirements on weight, battery life and size owed to batteries. Therefore, in portable devices, 'the low power design is the most decisive factor to think while designing system on chip. Normally, mobile users demand additional features and prolonged battery life at a lower cost. Almost 70% of users look for longer talk time and standby time as key feature for mobile phones. One of the top operator requirements in 4G is Power efficiency. Customers always look for smaller, trim and graceful mobile devices. This is the need of high levels of silicon integration in modern processes, but sophisticated processes have intrinsically higher power

Whenever there is power dissipation, it unvaryingly leads to an increase in chip temperature. This temperature rise affects devices when it is switched on and off. With device in OFF condition, power dissipation increases the number of intrinsic carriers ni provided by the

> ni α e –<sup>E</sup> G =V

From the above equation, it is very clear that when temperature increases, intrinsic carriers also increase. With temperature increase, the less affected ones are the majority carriers which are contributed by impurity atoms. As the temperature increases further, the leakage current that depends on the concentration of the minority carrier, increases which leads to further increase in temperature. Ultimately, the device might break down, if the dissipated heat is not removed properly. An ON device will not be affected much by the increase of

<sup>T</sup> (1)

indulgence. So, design is very important in low power consumption devices.

l is the length, A is the area and σc is the thermal conductivity of the heat sink.

From the above relation, it can be seen that large σc implies smaller θ. θ is also given by the relation

$$
\Theta = \clubsuit \,\mathrm{T}/\mathsf{\eth}\,\mathrm{P} \tag{3}
$$

Using this relation, we can see that for a given power dissipation, PD

$$\Theta \le \left( \mathbf{T\_j} - \mathbf{T\_a} \right) / \mathbf{P\_D} \tag{4}$$

where Tj is the junction temperature and Ta is the ambient temperature.

Heat sink materials are generally coated black to radiate more energy.

### 1.4. Low power design methodology

Historically, VLSI designers have used circuit speed as the performance metric. In fact, power considerations have been the ultimate design criteria in special portable applications. The main aim of these applications was maximum battery life time, with minimum power. Low power design is also required to reduce the power in high-end systems with huge integration density and thus improve the speed of operation.

To optimize power dissipation specifically with low power methodology in digital systems, the method should be applied all over the design from system to process level. It is very important to have knowledge about the power distribution. So the blocks or parts consuming fraction of power could be clearly optimized for saving power. Different design levels specifically of power reduction are shown in Figure 2.

### 1.4.1. Power reduction through process technology

Minimizing the supply voltage of a device is one of the best solutions to reduce power dissipation. The trade-off of this approach is that delay may increase significantly, when VDD

1.4.4. Power reduction by algorithm level

• Utilize low system clocks

1.5. Power modelling

• Use high level of integration

dissipation components are [1]

during the switching transient

Thus the total power dissipation PT is

• Short circuit power dissipation

1.5.1. Static power dissipation

model.

the input voltage

• Data coding for reduce the switching activity.

1.4.5. Power reduction through system integration

• Minimizing the number of operation and hence reduce the number of hardware resources

Numerous power components and their outcome must be identified to reduce power consumption of certain circuit. Out of two power dissipation types, the maximum power dissipation relates to peak instantaneous current and the second type is average power dissipation. Due to power line resistance, peak current affects the noise in supply voltage. This causes heating of device and hence results in performance degradation. With a view on battery life time, this average power dissipation becomes more important. The three important power

• Static power due to leakage current ILeak and other static component ISt due to the value of

• Dynamic power caused by the total output capacitance CL and short circuit current ISC,

PT ¼ PS þ PD þ PSC

Static power dissipation is the power consumed during the standby mode of a design. CMOS gates typically have some amount of sub-threshold leakage current even when gates are not turned on. The drain to source leakage current is the main component of static power consumption. The leakage power is a very small part of the overall power consumption. In a typical chip 10% of the power consumed is leakage and 90% is dynamic power. So, clearly the major concern is dynamic power dissipation. Figure 3 shows static power calculation

Energy E ¼

ð T

0

Instantaneous power P tðÞ¼ iDDð Þt VDD (5)

p tð Þdt (6)

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Figure 2. Power reduction design aspects.

approaches the threshold voltage. So devices must be properly scaled to overcome this problem. The advantages of scaling are:


#### 1.4.2. Power reduction through circuit/logic design


#### 1.4.3. Power reduction through architectural model


### 1.4.4. Power reduction by algorithm level


### 1.4.5. Power reduction through system integration


### 1.5. Power modelling

approaches the threshold voltage. So devices must be properly scaled to overcome this prob-

lem. The advantages of scaling are: • Improve the device characteristics

Figure 2. Power reduction design aspects.

50 Very-Large-Scale Integration

• Enhanced interconnect technology

• High density of integration

• Reduce the geometric and junction capacitances

1.4.2. Power reduction through circuit/logic design

• Reduce switching activity by optimized algorithm

• Smart circuit techniques which minimizes no of devices used in the circuit

• Reduces VDD in non-critical paths and proper transistor sizing

• Techniques for power management like shut down of unused blocks

• Instruction set minimization for easier decoding and execution

• Use of more static than dynamic circuits

• Custom design may improve the power

1.4.3. Power reduction through architectural model

• Reduction in the numbers of global busses

• Architectures based on pipelining, parallelism etc., • Memory partitioning by enabling selective blocks

• Optimize clock and bus loading

• Re-encoding of sequential circuits

• Use of multi-VT circuits

Numerous power components and their outcome must be identified to reduce power consumption of certain circuit. Out of two power dissipation types, the maximum power dissipation relates to peak instantaneous current and the second type is average power dissipation. Due to power line resistance, peak current affects the noise in supply voltage. This causes heating of device and hence results in performance degradation. With a view on battery life time, this average power dissipation becomes more important. The three important power dissipation components are [1]


Thus the total power dissipation PT is

$$\text{PT} = \text{PS} + \text{PD} + \text{PSC}$$

### 1.5.1. Static power dissipation

Static power dissipation is the power consumed during the standby mode of a design. CMOS gates typically have some amount of sub-threshold leakage current even when gates are not turned on. The drain to source leakage current is the main component of static power consumption. The leakage power is a very small part of the overall power consumption. In a typical chip 10% of the power consumed is leakage and 90% is dynamic power. So, clearly the major concern is dynamic power dissipation. Figure 3 shows static power calculation model.

$$\text{Instantaneous power} \,\mathbf{P}(\mathbf{t}) = \mathbf{i}\_{\text{DD}}(\mathbf{t}) \mathbf{V}\_{\text{DD}} \tag{5}$$

$$\text{Energy} \to \prod\_{0}^{\text{T}} p(t)dt\tag{6}$$

Figure 3. Static power calculation model.

$$\mathbf{E} = \int\_0^\mathbf{T} i D D(t) V D D \, dt \tag{7}$$

During charging cycle

Figure 4. Equivalent circuits for dynamic power calculation.

During the discharge cycle

suppose the system clock frequency is f.

Most gates do not switch every clock cycle,

ip ¼ CL:

in ¼ �CL:

CLVodVo �

0

V2 DD 2 þ

PD ¼ fsw CL VDD

Assuming a logic gate goes through one complete charge/discharge cycle for every clock cycle,

PD ¼ E CL:VDD

A clock has E = 1 because it rises and fall every cycle, but most data have a maximum energy

The dynamic component of power consumption arises when the capacitive load CL of a CMOS circuit is charged through PMOS transitions to make a voltage transition from 0 to 1, half of which is stored in the output capacitor and half is dissipated in the PMOS device [2]. No

2

Vo<sup>2</sup> 2 � �VDD

VDD ð

2 4

0

PD ¼ fsw CL

transition activity factor E = 0.5 because they transit only once every cycle.

PD ¼ fsw

Let fsw = Ef, where E is the energy transition activity factor.

PD ¼ fsw CL

dVo

dVo tð Þ

ð 0

CLVodVo

3

VDD " # " # (14)

� � � � (15)

<sup>2</sup> (16)

:f (17)

VDD

� Vo<sup>2</sup> 2 � �<sup>0</sup>

> V2 DD 2

dt (11)

dt (12)

5 (13)

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$$\text{Static power } P\_S = \text{E/T} \tag{8}$$

$$\text{P}\_{\text{S}} = 1/\text{T} \left[ iDD(t)VDD \, dt \right] \tag{9}$$

#### 1.5.2. Dynamic power dissipation

A dynamic power vector describes an event in which power is dissipated due to a signal switching at the cell input during charging and discharging of load capacitance. Dynamic power is further divided into switching power and internal power.

• Switching power

Switching power is dissipated when the load capacitance at the output of the cell is being charged or discharged. The load capacitance is composed of interconnect capacitance and gate capacitances. Switching activity of cells depend on the quantity of switching power. On the cell output, if there are huge logic transitions, then switching power surges.

• Internal power

Within a cell, internal power is specifically consumed for charging and discharging cell capacitances. When logical transitions occur, Pmos and Nmos transistors are ON at the same time for a short period. This causes a connection between Vdd and ground rails.

The power dissipation can be estimated by the load capacitance CL. This power loss is due to the charging and discharging of load capacitance CL [1]. The average dynamic power PD is required to charge and discharge a capacitance CL at a switching frequency fsw and equivalent dynamic power calculation model is shown in Figure 4.

$$\mathbf{P\_D} = f\_{sw} \int\_0^\mathbf{T} \dot{\mathbf{o}}(t) V \mathbf{\dot{o}}(t) dt \tag{10}$$

Figure 4. Equivalent circuits for dynamic power calculation.

During charging cycle

E ¼ ð T

PS ¼ 1=T

power is further divided into switching power and internal power.

output, if there are huge logic transitions, then switching power surges.

for a short period. This causes a connection between Vdd and ground rails.

PD ¼ f sw

dynamic power calculation model is shown in Figure 4.

1.5.2. Dynamic power dissipation

Figure 3. Static power calculation model.

52 Very-Large-Scale Integration

• Switching power

• Internal power

0

ð T

0

A dynamic power vector describes an event in which power is dissipated due to a signal switching at the cell input during charging and discharging of load capacitance. Dynamic

Switching power is dissipated when the load capacitance at the output of the cell is being charged or discharged. The load capacitance is composed of interconnect capacitance and gate capacitances. Switching activity of cells depend on the quantity of switching power. On the cell

Within a cell, internal power is specifically consumed for charging and discharging cell capacitances. When logical transitions occur, Pmos and Nmos transistors are ON at the same time

The power dissipation can be estimated by the load capacitance CL. This power loss is due to the charging and discharging of load capacitance CL [1]. The average dynamic power PD is required to charge and discharge a capacitance CL at a switching frequency fsw and equivalent

> ð T

> > 0

iDD tð ÞVDD dt (7)

iDD tð ÞVDD dt (9)

io tð ÞVo tð Þdt (10)

Static power PS ¼ E=T (8)

$$\dot{\mathbf{u}}\_p = \mathbf{C}\_L \frac{d\mathbf{V}\mathbf{o}}{dt} \tag{11}$$

During the discharge cycle

$$\dot{q}\_n = -\mathcal{C}\_L \frac{dVo(t)}{dt} \tag{12}$$

$$\mathbf{P}\_{\rm D} = \text{fsw} \left[ \int\_{0}^{\text{VDD}} \mathbb{C}\_{L} V\_{o} dVol - \int\_{\rm{VDD}}^{0} \mathbb{C}\_{L} V\_{o} dVol} \right] \tag{13}$$

$$\mathbf{P}\_{\rm D} = \text{fsw} \left[ \mathbf{C}\_{\rm L} \left[ \left[ \frac{V \sigma^2}{2} \right]\_{0}^{VDD} - \left[ \frac{V \sigma^2}{2} \right]\_{VDD}^{0} \right] \right] \tag{14}$$

$$\mathbf{P\_D} = \text{fsw} \left[ \text{Ch} \left[ \frac{V\_{DD}^2}{2} + \frac{V\_{DD}^2}{2} \right] \right] \tag{15}$$

$$\mathbf{P\_D = fsw \ C\_L \ V\_{DD}}^2 \tag{16}$$

Assuming a logic gate goes through one complete charge/discharge cycle for every clock cycle, suppose the system clock frequency is f.

Let fsw = Ef, where E is the energy transition activity factor.

Most gates do not switch every clock cycle,

$$\text{PD} = \text{E} \, \text{Cl} \, \text{V} \text{DD}^2 \, \text{f} \tag{17}$$

A clock has E = 1 because it rises and fall every cycle, but most data have a maximum energy transition activity factor E = 0.5 because they transit only once every cycle.

The dynamic component of power consumption arises when the capacitive load CL of a CMOS circuit is charged through PMOS transitions to make a voltage transition from 0 to 1, half of which is stored in the output capacitor and half is dissipated in the PMOS device [2]. No

ð19Þ

55

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http://dx.doi.org/10.5772/intechopen.73729

ð20Þ

ð21Þ

ð22Þ

ð23Þ

ð24Þ

ð25Þ

assuming that Vtn = � Vtp and β<sup>n</sup> = β<sup>p</sup> and that the behaviour is symmetrical around t2.

The equation suggests that, depending on the input rise and fall times and β, the short circuit current varies. For load inverters, on nodes, slow rise times significantly reduces (20%) SC power dissipation. If power dissipation is a concern, then it is good if all the edges are kept fast. Further increase in load capacitance significantly reduces the short circuit dissipation by

The internal power and the capacitive load power are the two key components for dynamic power dissipation in a complex design, like the internal node. The power in an internal node is determined by the amount of the power dissipated by the internal capacitive nodes [3]. Sometimes, internal node short circuit power is also included in the node to calculate the dynamic power at the internal node. So the dynamic power cannot be calculated by the simple

transition activity determines how often this transition occurs on a power. Considering capacitive node for N periods of time 0 ! 1 and 1 ! 0 transitions will occur. The transition activity E determines how many low to high and high to low transitions occur at the output [4]. In other words, the activity E represents the probability that a transition 0 ! 1 will occur during the period T = 1/f. The average dynamic power of a complex design due to the output load

f because MOS devices might not switch when the clock is switching. The

With

Assuming an inverter without load,

where tp is the period of the waveform.

reduced capacitive dissipation PD.

1.7. Transition activity

equation CLVDD<sup>2</sup>

capacitance is given by

Figure 6. Power analysis chart, IRTS-2011.

charge is drawn from the VDD during the 1 to 0 transition at the output. But the energy stored in the capacitor is dissipated in the pull-down NMOS device shown in Figure 5. The main cause of energy dissipation in CMOS circuits is due to charging and discharging of the node capacitances. The power analysis chart is also shown in Figure 6.

#### 1.6. Short circuit power dissipation

Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND. Also called crowbar current, the total power dissipation is more than 20% of total power. As clock frequency increases, transitions increases and consequently short circuit power dissipation increases. It can be reduced by

• faster input and slower output

• Vdd < = Vtn + |Vtp|

So both NMOS and PMOS are not ON at the same time.

The short-circuit power dissipation is given by

$$\mathbf{I}\_{\rm D} = \mathbf{I}\_{\rm mean} \, ^\*\mathbf{V}\_{\rm DD} \tag{18}$$

For the input waveform shown in Figure 8, which depicts the short circuit in an unloaded inverter,

#### Low Power Design Methodology http://dx.doi.org/10.5772/intechopen.73729 55

$$I\_{\text{mean}} = 2 \times \frac{2}{T} \int\_{t\_l}^{t\_f} \frac{\rho}{2} (V \cdot l\_{bl}(t) - V \cdot l\_l)^{\frac{1}{2}} dt \tag{19}$$

assuming that Vtn = � Vtp and β<sup>n</sup> = β<sup>p</sup> and that the behaviour is symmetrical around t2.

$$I\_{\text{new}} = 2 \times \frac{2}{T} \int\_{t\_1}^{t\_2} \frac{\rho}{2} (V\_{\text{-}h}(t) - V\_{\text{-}l})^{\text{'}\_{\text{int}}} dt \tag{20}$$

With

charge is drawn from the VDD during the 1 to 0 transition at the output. But the energy stored in the capacitor is dissipated in the pull-down NMOS device shown in Figure 5. The main cause of energy dissipation in CMOS circuits is due to charging and discharging of the node

Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND. Also called crowbar current, the total power dissipation is more than 20% of total power. As clock frequency increases, transitions increases

For the input waveform shown in Figure 8, which depicts the short circuit in an unloaded inverter,

PD <sup>¼</sup> Imean<sup>∗</sup> VDD (18)

and consequently short circuit power dissipation increases. It can be reduced by

capacitances. The power analysis chart is also shown in Figure 6.

So both NMOS and PMOS are not ON at the same time.

The short-circuit power dissipation is given by

1.6. Short circuit power dissipation

Figure 6. Power analysis chart, IRTS-2011.

• faster input and slower output

• Vdd < = Vtn + |Vtp|

Figure 5. Energy per transition.

54 Very-Large-Scale Integration

$$\mathcal{V}\_{\text{v}}(t) = \frac{\mathcal{V}\_{\text{eff}}}{t} \, \_{4} \tag{21}$$

$$
\mathbf{t}\_1 = \frac{V\_\star}{V\_\infty} \mathbf{t},\tag{22}
$$

$$t\_1 = \frac{t\_r}{2} \tag{23}$$

$$\mathbf{t}\_r = \mathbf{t}\_f = (\mathbf{t}\_{r'}) \tag{24}$$

Assuming an inverter without load,

$$\left(\boldsymbol{\nu}\_{\*} - \,\_{2}^{\mathsf{f}} (\boldsymbol{\nu}\_{\partial\mathsf{M}} - \boldsymbol{\mathfrak{z}} \,\mathsf{V}) \, \right)^{\mathsf{f}\_{\mathsf{f}\_{\mathsf{c}}}}\_{\mathsf{f}\_{\mathsf{c}}} \tag{25}$$

where tp is the period of the waveform.

The equation suggests that, depending on the input rise and fall times and β, the short circuit current varies. For load inverters, on nodes, slow rise times significantly reduces (20%) SC power dissipation. If power dissipation is a concern, then it is good if all the edges are kept fast. Further increase in load capacitance significantly reduces the short circuit dissipation by reduced capacitive dissipation PD.

#### 1.7. Transition activity

The internal power and the capacitive load power are the two key components for dynamic power dissipation in a complex design, like the internal node. The power in an internal node is determined by the amount of the power dissipated by the internal capacitive nodes [3]. Sometimes, internal node short circuit power is also included in the node to calculate the dynamic power at the internal node. So the dynamic power cannot be calculated by the simple equation CLVDD<sup>2</sup> f because MOS devices might not switch when the clock is switching. The transition activity determines how often this transition occurs on a power. Considering capacitive node for N periods of time 0 ! 1 and 1 ! 0 transitions will occur. The transition activity E determines how many low to high and high to low transitions occur at the output [4]. In other words, the activity E represents the probability that a transition 0 ! 1 will occur during the period T = 1/f. The average dynamic power of a complex design due to the output load capacitance is given by

$$\mathbf{P\_D = E\_L C\_{DD}}^2 \mathbf{f\_{DD}}^2 \mathbf{f\_{CD}} \tag{26}$$

The internal power dissipation, due to internal nodes, the internal dynamic power of a cell is given by

$$P\_{\text{int}-\text{dyn}} = \sum\_{i=1}^{\infty} E\_i \mathbb{C}\_i V\_i \, V\_{DD} \, f \tag{27}$$

design consideration. Several factors contribute to this trend like the growth of personal computing devices such as portable desktops, audio and video-based multimedia products and wireless communication systems which demand high-speed computation and complex functionality with low power consumption [6]. So there is a strong requirement for power consumption reduction so as to reduce packaging and cooling cost and improve product reliability. When the target is a low power application, a power analyser/estimator ranks the various design aspects, thus helps in selecting the one that is potentially more effective from the power standpoint.

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Table 2. Energy transition analysis for coupling capacitance, Yan Zhang et al. 2002.

A top-down two-dimensional ordinary VLSI design approach is illustrated in Figure 7. The figure summarizes the flow of steps that are required to follow from a system-level specification to the physical design. The approach is aimed to estimate the design parameters such as

the performance optimization and area minimization, as shown in Figures 8–10.

1.8.1. Two-dimensional design flow

Figure 7. Short circuit power calculation model.

Due to charging and discharging the data changed from 1 to 0 or from 0 to 1 vice versa between adjacent bus wires or on the same bus wire. This is classified into two types:


#### 1.7.1. Self-transition

A Self-transition (ST) is defined as a transition from 0 ! 1 or 1 ! 0 on bus with reference to the previous data on it [5]. Energy transition analysis is shown in Table 1.

#### 1.7.2. Coupling transition

A coupling transition (CT) is defined as a transition from 0 ! 1 or 1 ! 0, between two adjacent bus wires [5]. The corresponding energy transition analysis is shown in Table 2.

#### 1.8. Design parameter

The low power design work mainly focuses on estimating the dynamic power dissipation. In the past, the major concern of the designer was about area, speed and cost. The secondary importance was provided for power considerations. In recent years, power has become as the primary


Table 1. Energy transition analysis for self-capacitance, Yan Zhang et al. 2002.


Table 2. Energy transition analysis for coupling capacitance, Yan Zhang et al. 2002.

design consideration. Several factors contribute to this trend like the growth of personal computing devices such as portable desktops, audio and video-based multimedia products and wireless communication systems which demand high-speed computation and complex functionality with low power consumption [6]. So there is a strong requirement for power consumption reduction so as to reduce packaging and cooling cost and improve product reliability. When the target is a low power application, a power analyser/estimator ranks the various design aspects, thus helps in selecting the one that is potentially more effective from the power standpoint.

### 1.8.1. Two-dimensional design flow

PD ¼ E CL VDD

The internal power dissipation, due to internal nodes, the internal dynamic power of a cell is

i¼1

between adjacent bus wires or on the same bus wire. This is classified into two types:

Due to charging and discharging the data changed from 1 to 0 or from 0 to 1 vice versa

A Self-transition (ST) is defined as a transition from 0 ! 1 or 1 ! 0 on bus with reference to the

A coupling transition (CT) is defined as a transition from 0 ! 1 or 1 ! 0, between two adjacent

The low power design work mainly focuses on estimating the dynamic power dissipation. In the past, the major concern of the designer was about area, speed and cost. The secondary importance was provided for power considerations. In recent years, power has become as the primary

bus wires [5]. The corresponding energy transition analysis is shown in Table 2.

Pint�dyn <sup>¼</sup> <sup>X</sup><sup>∝</sup>

previous data on it [5]. Energy transition analysis is shown in Table 1.

Table 1. Energy transition analysis for self-capacitance, Yan Zhang et al. 2002.

given by

56 Very-Large-Scale Integration

• Self-transition

1.7.1. Self-transition

• Coupling transition

1.7.2. Coupling transition

1.8. Design parameter

2

f (26)

EiCiVi VDD f (27)

A top-down two-dimensional ordinary VLSI design approach is illustrated in Figure 7. The figure summarizes the flow of steps that are required to follow from a system-level specification to the physical design. The approach is aimed to estimate the design parameters such as the performance optimization and area minimization, as shown in Figures 8–10.

Figure 7. Short circuit power calculation model.

1.8.2. Three-dimensional design flow

Figure 11. Three-dimensional (3D) VLSI design flow.

A three-dimensional top-down VLSI design approach is illustrated in Figure 11. The figure summarizes the flow of steps that are required to follow from a system-level specification to the physical design. The approach is aimed to estimate the design parameters at performance optimization, area minimization and power optimization shown in Figure 12. In each of the design levels, there are two important power factors, namely, power optimization and power estimation. Power optimization is the process of obtaining the best design knowing the design constraints and without violating design specifications. Power estimation is determined as the process of computing power and energy dissipated with a definite percentage of precision and at different stages of design process. This technique also estimates the outcome of several optimization and design alterations on power at different levels of abstraction, as shown in Figure 12. Design attains power optimization first and then does power estimation. But for certain design, there is no specific design procedure. Each design might include a lot of low power techniques and thus significantly reduce power dissipation. But certain combination of low power designs can provide better result than certain other combination techniques. Usually

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Figure 8. Short circuit behaviour of CMOS inverter without load.

Figure 9. Two-dimensional (2D) VLSI design flow.

Figure 10. Two-dimensional (2D) design parameter.

### 1.8.2. Three-dimensional design flow

Figure 8. Short circuit behaviour of CMOS inverter without load.

58 Very-Large-Scale Integration

Figure 9. Two-dimensional (2D) VLSI design flow.

Figure 10. Two-dimensional (2D) design parameter.

A three-dimensional top-down VLSI design approach is illustrated in Figure 11. The figure summarizes the flow of steps that are required to follow from a system-level specification to the physical design. The approach is aimed to estimate the design parameters at performance optimization, area minimization and power optimization shown in Figure 12. In each of the design levels, there are two important power factors, namely, power optimization and power estimation. Power optimization is the process of obtaining the best design knowing the design constraints and without violating design specifications. Power estimation is determined as the process of computing power and energy dissipated with a definite percentage of precision and at different stages of design process. This technique also estimates the outcome of several optimization and design alterations on power at different levels of abstraction, as shown in Figure 12. Design attains power optimization first and then does power estimation. But for certain design, there is no specific design procedure. Each design might include a lot of low power techniques and thus significantly reduce power dissipation. But certain combination of low power designs can provide better result than certain other combination techniques. Usually

Figure 11. Three-dimensional (3D) VLSI design flow.

1.9.1. Non-power tool

waveform viewers.

power at these levels.

• XPower analysis tool

Figure 14. Power analysis flow chart.

a. Tanner EDA, Microwind: Transistor level

b. RTL Power Estimator: RTL level

c. Power Compiler: Gate level.

1.9.2. Power tool

Non-power tools include simulation tools, synthesis tools, layout tools, extraction tools and

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Varieties of power analysis tools are available to estimate the power of a design. Among them are Xilinx, Tanner, Microwind, etc. These EDA power tools are very familiar and user-friendly. The power products are tools that comprise a complete methodology for low power design. Xilinx power tool XPower offers power analysis and optimization throughout the design cycle (from RTL to the gate level). Tanner and Microwind are used for transistor-level analysis. Analysing power early in the design cycle can significantly affect design quality. Design modifications done at RTL level can get good results. Power tools used to calculate power quickly as well as do measurements accurately. The following tools are used to calculate the

Power analysis and estimation is available throughout the design process, as shown in Figure 14.

Activity rates are the basis of Xilinx Power tool. They are defined by the rate at which a logic element or net capacitance switches. Activity rates for dynamic calculations are expressed in

Figure 12. Three-dimensional (3D) design parameter.

Figure 13. Relationship between different abstraction level and power estimation techniques.

power will be consumed due to transition activities as the capacitors gets charged and discharged. So for higher level systems, power dissipation is preserved by shutdown of system portions when not required and thus the transition activities are reduced (Figure 13).

#### 1.9. Power estimation tool

Recently, complexity levels of device size and programmable devices have grown to amazing complexity levels. Years ago, an average design had nearly twelve thousand gates. Presently, there are hundreds of thousands and sometimes multimillion gates. So when size of design increases, power consumption also increases. In the meantime, there is huge demand for battery-powered systems, specifically, handheld devices which are constantly sensitive and smaller to power usage. So it is clearly understood that in programmable logic devices design power consumption cannot be ignored. This chapter deals more on power calculations using Macros and is experimented using power tools. Prior to the power tools, other tools have been used to provide the necessary input to the power tools. More importance is provided to the tools specifically involved in low power estimation, which has been classified as power tools and non-power tools.

### 1.9.1. Non-power tool

Non-power tools include simulation tools, synthesis tools, layout tools, extraction tools and waveform viewers.

### 1.9.2. Power tool

Varieties of power analysis tools are available to estimate the power of a design. Among them are Xilinx, Tanner, Microwind, etc. These EDA power tools are very familiar and user-friendly. The power products are tools that comprise a complete methodology for low power design. Xilinx power tool XPower offers power analysis and optimization throughout the design cycle (from RTL to the gate level). Tanner and Microwind are used for transistor-level analysis. Analysing power early in the design cycle can significantly affect design quality. Design modifications done at RTL level can get good results. Power tools used to calculate power quickly as well as do measurements accurately. The following tools are used to calculate the power at these levels.


Power analysis and estimation is available throughout the design process, as shown in Figure 14.

• XPower analysis tool

power will be consumed due to transition activities as the capacitors gets charged and discharged. So for higher level systems, power dissipation is preserved by shutdown of system

Recently, complexity levels of device size and programmable devices have grown to amazing complexity levels. Years ago, an average design had nearly twelve thousand gates. Presently, there are hundreds of thousands and sometimes multimillion gates. So when size of design increases, power consumption also increases. In the meantime, there is huge demand for battery-powered systems, specifically, handheld devices which are constantly sensitive and smaller to power usage. So it is clearly understood that in programmable logic devices design power consumption cannot be ignored. This chapter deals more on power calculations using Macros and is experimented using power tools. Prior to the power tools, other tools have been used to provide the necessary input to the power tools. More importance is provided to the tools specifically involved in low power estimation, which has been classified as power tools

portions when not required and thus the transition activities are reduced (Figure 13).

Figure 13. Relationship between different abstraction level and power estimation techniques.

1.9. Power estimation tool

Figure 12. Three-dimensional (3D) design parameter.

60 Very-Large-Scale Integration

and non-power tools.

Activity rates are the basis of Xilinx Power tool. They are defined by the rate at which a logic element or net capacitance switches. Activity rates for dynamic calculations are expressed in

Figure 14. Power analysis flow chart.

frequency. The activity rate might be relative to clock and hence net or logic element might switch at any fraction of the clock frequency. Thus the main use of activity rate is in the recalculation of power and could be easily achieved by varying system clock frequency. So simulation data could be used, and this saves time. Also Xilinx Power supports several numbers of input clocks. Expressed in percentage scale, 100% activity rate means that standard signal state changes once every clock cycle. Switching rate will be the activity rate if net and logic are not clock sync (Figures 15–22).

• Microwind

This software tool is dedicated to microelectronics and nanotechnology. The microwind software allows the designer to simulate and design an integrated circuit at physical description level. It provides innovative EDA solutions to the analog, digital and mixed-signal IC market. With MOS characteristic viewer, mix signal simulator, in-built layout editing tools, it is easier to complete design process. Microwind unifies netlist extraction, pattern-based simulator, layout compilation, SPICE extraction of schematic, Verilog extractor, schematic entry on layout


mix-signal circuit simulation, sign-off correlation, BSIM4 tutorial on MOS devices, crosssectional and 3D viewer to deliver matchless architecture productivity and performance.

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Tanner tool is a suite of tools to perform spice analysis for analog integrated circuits. Following

• Tanner EDA Tool

are the Tanner tool engine machines:

Figure 17. Power calculation of digital CMOS circuits.

Figure 16. Simulation of digital CMOS circuits.

1. Schematic Edit (S-EDIT) 2. Simulation Edit (T-EDIT) 3. Waveforms Edit (W-EDIT)

4. Layout Edit (L-EDIT)

Figure 15. Power output calculation using XPower.

Figure 16. Simulation of digital CMOS circuits.

frequency. The activity rate might be relative to clock and hence net or logic element might switch at any fraction of the clock frequency. Thus the main use of activity rate is in the recalculation of power and could be easily achieved by varying system clock frequency. So simulation data could be used, and this saves time. Also Xilinx Power supports several numbers of input clocks. Expressed in percentage scale, 100% activity rate means that standard signal state changes once every clock cycle. Switching rate will be the activity rate if net and

This software tool is dedicated to microelectronics and nanotechnology. The microwind software allows the designer to simulate and design an integrated circuit at physical description level. It provides innovative EDA solutions to the analog, digital and mixed-signal IC market. With MOS characteristic viewer, mix signal simulator, in-built layout editing tools, it is easier to complete design process. Microwind unifies netlist extraction, pattern-based simulator, layout compilation, SPICE extraction of schematic, Verilog extractor, schematic entry on layout

logic are not clock sync (Figures 15–22).

Figure 15. Power output calculation using XPower.

• Microwind

62 Very-Large-Scale Integration

Figure 17. Power calculation of digital CMOS circuits.

mix-signal circuit simulation, sign-off correlation, BSIM4 tutorial on MOS devices, crosssectional and 3D viewer to deliver matchless architecture productivity and performance.

• Tanner EDA Tool

Tanner tool is a suite of tools to perform spice analysis for analog integrated circuits. Following are the Tanner tool engine machines:


Figure 18. Layout of digital CMOS circuits.


Figure 21. Tanner waveform viewer.

Figure 22. L-Edit IC layout.

Figure 20. T-spice simulation.

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Figure 19. Tanner S-Edit schematic capture.

The Tanner engine tools are used to design and simulate new ideas in analog-integrated circuits; this saves time and cost of chip fabrication.

### 1.10. Conclusion

In CMOS circuits, most of the power dissipates through dynamic power dissipation than static power dissipation. In CMOS circuits, static power dissipation is in the range of nano watts. The most significant source of dynamic power dissipation is caused by transition activities of the circuits. A higher operating frequency leads to more transition activities in the circuits and results in increased power dissipation. Using proper encoding techniques may reduce switching activity in the circuit. This will reduce the overall transition activity. Hence, the dynamic power dissipation can be reduced in VLSI circuits effectively.

Figure 20. T-spice simulation.

Figure 21. Tanner waveform viewer.

Figure 22. L-Edit IC layout.

The Tanner engine tools are used to design and simulate new ideas in analog-integrated circuits;

In CMOS circuits, most of the power dissipates through dynamic power dissipation than static power dissipation. In CMOS circuits, static power dissipation is in the range of nano watts. The most significant source of dynamic power dissipation is caused by transition activities of the circuits. A higher operating frequency leads to more transition activities in the circuits and results in increased power dissipation. Using proper encoding techniques may reduce switching activity in the circuit. This will reduce the overall transition activity. Hence, the dynamic power

this saves time and cost of chip fabrication.

Figure 19. Tanner S-Edit schematic capture.

Figure 18. Layout of digital CMOS circuits.

64 Very-Large-Scale Integration

dissipation can be reduced in VLSI circuits effectively.

1.10. Conclusion

### Author details

Vithyalakshmi Natarajan<sup>1</sup> \*, Ashok Kumar Nagarajan<sup>1</sup> , Nagarajan Pandian<sup>1</sup> and Vinoth Gopi Savithri<sup>2</sup>


### References

[1] Weste N, Eshraghian K. Principle of CMOS VLSI Design: A System Perspective. 2nd ed. New York: Addison–Wesley; 1993

**Chapter 4**

**Provisional chapter**

**High-purity Refractory Metals for Thin Film**

**High-purity Refractory Metals for Thin Film** 

DOI: 10.5772/intechopen.69126

It is shown that cast targets of highly pure refractory metals like W, Mo, Ti, Ta, Co, etc. and their compounds can be produced by means of a set of vacuum-metallurgical techniques—by vacuum high-frequency levitation, EB floating zone melting, EB melting, and electric arc vacuum melting as well as chemical purifying by ion exchange and halides. The cast refractory metal targets are extremely pure and chemically homogeneous. For magnetron sputtering and laser ablation, the cast silicide targets are also produced. The study reveals the possibilities and conditions of depositing the silicides and titaniumtungsten barrier layers by both the laser evaporation and magnetron sputtering. The physical and structural parameters as well as a trace impurity composition of sputtered metals and deposited thin films are studied by grazing-beam incidence X-ray diffraction, Auger electron spectroscopy, Rutherford backscattering of helium ions, mass spectrom-

**Keywords:** EB vacuum melting, target, magnetron sputtering, laser ablation, thin films,

The application of thin films of pure Al and Al doped with Si (1 at.% Si) seems to be useful for the production of thin films for integrated circuits with dimensions of about 2 μm. A further reduction of dimensions to less than 1 μm and decreasing the *p-n* transition to 0.3 μm increase demands for parameters/operation conditions and necessitate a search for more reliable constructive and technological designs of the metallization including the contact units. Hence, ultra-purity is a term increasingly being applied to refractory metals [1–3]. Not only applications in the electronic industry but also their use as superconducting materials

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

**Metallization of VLSI**

**Metallization of VLSI**

Additional information is available at the end of the chapter

etry with inductively coupled plasma, etc.

resistivity, refractory metals

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69126

Vadim Glebovsky

**Abstract**

**1. Introduction**

Vadim Glebovsky


**Provisional chapter**

### **High-purity Refractory Metals for Thin Film Metallization of VLSI Metallization of VLSI**

**High-purity Refractory Metals for Thin Film** 

DOI: 10.5772/intechopen.69126

Vadim Glebovsky Additional information is available at the end of the chapter

Vadim Glebovsky

Author details

66 Very-Large-Scale Integration

Vithyalakshmi Natarajan<sup>1</sup>

Vinoth Gopi Savithri<sup>2</sup>

References

\*, Ashok Kumar Nagarajan<sup>1</sup>

1 Sree Vidyanikethan Engineering College, Chittoor, Andhra Pradesh, India

[1] Weste N, Eshraghian K. Principle of CMOS VLSI Design: A System Perspective. 2nd ed.

[2] Stan MR, Burleson WP. Bus-invert coding for low power I/O. IEEE Youngsoo Shin, Soo-Ik Chae & Kiyoung Choi 2001. Partial Bus-Invert Coding for Power Optimization of Application-Specific Systems. IEEE Transactions On Very Large Scale Integration Systems. 1995, vol. 9,

[3] Young Chul Kim, Young Jin Lee. Power effective bus encoding scheme with no crosstalk and minimized bus Transition. International Journal of Control and Automation. 2013;6(4):1-10

[4] Verma SK, Kaushik BK. Encoding schemes for reduction of power dissipation, crosstalk and delay in VLSI interconnects: A Review. International Journal of Recent Trends in

[5] Sainarayanan KS, Ravindra JVR, Kiran T Nath, Srinivas MB. Coding for minimizing energy in VLSI interconnects. The 18th International Conference on Microelectronics. 2006 pp. 166-169

[6] Abhijeet Dhanotiya, Vishal Sharma. Power reduction in digital VLSI circuits. International

Journal of Research in IT, Management and Engineering. 2014;4(6):13-23

\*Address all correspondence to: vidhyavinoth@gmail.com

2 QuEST, Global, Technopark, Trivandrum, Kerala, India

no. 2, pp. 377-383. Trans. On VLSI, vol. 3, pp. 49-58

Engineering and Technology. 2010;3(4):74-76

New York: Addison–Wesley; 1993

, Nagarajan Pandian<sup>1</sup> and

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69126

### **Abstract**

It is shown that cast targets of highly pure refractory metals like W, Mo, Ti, Ta, Co, etc. and their compounds can be produced by means of a set of vacuum-metallurgical techniques—by vacuum high-frequency levitation, EB floating zone melting, EB melting, and electric arc vacuum melting as well as chemical purifying by ion exchange and halides. The cast refractory metal targets are extremely pure and chemically homogeneous. For magnetron sputtering and laser ablation, the cast silicide targets are also produced. The study reveals the possibilities and conditions of depositing the silicides and titaniumtungsten barrier layers by both the laser evaporation and magnetron sputtering. The physical and structural parameters as well as a trace impurity composition of sputtered metals and deposited thin films are studied by grazing-beam incidence X-ray diffraction, Auger electron spectroscopy, Rutherford backscattering of helium ions, mass spectrometry with inductively coupled plasma, etc.

**Keywords:** EB vacuum melting, target, magnetron sputtering, laser ablation, thin films, resistivity, refractory metals

### **1. Introduction**

The application of thin films of pure Al and Al doped with Si (1 at.% Si) seems to be useful for the production of thin films for integrated circuits with dimensions of about 2 μm. A further reduction of dimensions to less than 1 μm and decreasing the *p-n* transition to 0.3 μm increase demands for parameters/operation conditions and necessitate a search for more reliable constructive and technological designs of the metallization including the contact units. Hence, ultra-purity is a term increasingly being applied to refractory metals [1–3]. Not only applications in the electronic industry but also their use as superconducting materials

or applications in the nuclear industry call for refractory metals and their alloys of utmost purity. The most intensive impact on ultra-purity of refractory metals is presently exerted by the electronic industry for VLSI applications [4–6]. In a word, VLSI means miniaturization. The goal of VLSI development is to find ways to pack as many tiny electronic components as possible into the smallest possible space. Often, smaller circuits also operate faster and, ultimately, drastically cut the overall cost of computation, opening up new possibilities for applications. Continued evolution of ever smaller devices has aroused a renewed interest in the development of new metallization processes for low resistivity gates, interconnections, and ohmic contacts. Al, W, and Mo are notable among the metals proposed for gate and interconnection metallization. The use of Al, however, requires all postgate processing of devices to be limited to very low temperatures, preferably below 500°C. The use of refractory metals, such as W and Mo, requires a complete passivation of these metals against oxidizing environments, a deposition by means that will not lead to unwanted traps in the gate oxide, and reliable etching of metals for pattern generation. Uncertainties associated with the stability of these metal films have led to a search for alternatives. As a rule, the different components deposited onto the Si substrate by different sputtering/evaporation methods must be ultrapure, especially with respect to trace contaminants listed in **Table 1** where the impurity compositions are represented for refractory metals studied in this chapter. The wide variety of applications of ultrahigh purity refractory metals as sputter targets in microelectronics is really impressive. A great number of companies compete to offer ultrapure refractory metal materials for sputter targets. Materials presently in the microelectronics use are W/Ti, Mo, MoSi2 , WSi2 , TaSi2 , TiSi2 , etc. As a rule, different components must be ultrapure, especially with respect to "mobile ions" (Li<sup>+</sup> , Na+ , K+ , Ca+ , and Mg+ ). With increasing miniaturization, an intrinsic radioactivity also exerts harmful effects; therefore, various components must be "free" of U and Th contamination. Nonmetals (O, N, H, and C) are detrimental too, as are impurities of Fe, Co, and Ni, for certain applications. However, information on analytical methods used for a chemical characterization of such materials as well as on metallurgical techniques used for a preparation of materials is extremely scarce or sometimes also misleading. It is known that a metal gate cannot withstand to the oxidizing annealing ambient and a source-drain formation by ion implantation is difficult because of the channeling of doping ions through the gate metal during ion implantation. In the process developed for MOS VLSI fabrication, W is used as the gate metal because a degradation of SiO2 by annealing a Me/SiO2 /Si structure at about 1000°C can be minimized. An oxidation of W is prevented by a moist hydrogen atmosphere during annealing. Si is also oxidized in the similar ambient. The most effective solution for VLSI is by applying barrier layers, such as Ti/W thin layers, nitrides, or silicides of refractory metals. The use of barrier layers requires a rational technique for their deposition as well as the materials of an optimal chemical composition. Even using Ti/W thin films as both barrier and conducting layers, the most suitable and advanced deposition technique is the magnetron sputtering, which is widely employed in commercial microelectronics. Thin films of Ti/W quasi-alloys as diffusion barriers for metal contacts on Si are used very intensively in the last decades. The W in this composition is supposed to serve as an interlayer diffusion barrier and the Ti as both a deoxidizer and a stopper of the grain boundary diffusion. The well-known channeling is stopped by forming a thin

**Impurity Mo Ti Ta W Nb V Zr Hf Co Ni** C 0.1 30.0 30.0 4.0 40.0 20/0 50.0 50.0 10.0 0.5 O 0.5 400.0 5.0 1.0 5.0 200.0 100.0 10.0 20.0 – H 0.2 – 2.0 0.1 1.0 – – – 1.0 – N 0.05 5.0 5.0 5.0 5.0 5.0 5.0 5.0 7.0 – Fe 0.5 10.0 0.5 1.0 0.5 8.0 300.0 3 50.0 0.1 Al 0.03 5.0 2.0 0.04 2.0 20.0 10.0 0.05 10.0 0.1 Cu 0.6 0.4 0.6 0.3 0.5 0.08 300.0 4 10.0 0.1 Ni 0.2 10.0 3.0 1.0 5.0 0.3 100.0 0.3 370.0 Matrix Ti 0.2 Matrix 3.0 – 3.0 0.3 – 2.0 10.0 0.2 Si 0.3 0.6 1.0 0.04 5.0 2.0 1.0 0.5 15.0 1.0 S 0.3 0.2 0.2 0.1 5.0 2.0 – – 10.0 – P 1.0 1.0 1.0 0.5 1.0 0.5 – – 5.0 – Nb 2.0 2.0 30.0 1.0 Matrix 0.2 – – 4.0 1.0 W 20.0 100.0 2.0 Matrix 30.0 0.3 – 0.3 10.0 1.0 Co – – 0.2 – 2.0 0.3 – – Matrix 0.1 Mo Matrix – 0.2 0.5 4.0 – 0.3 0.5 10.0 1.0 Ta 2.0 – Matrix 1.0 50.0 30.0 – – 5.0 1.0 Cr – 0.3 0.3 – 0.5 0.3 5.0 1.0 10.0 0.1 Cd 1.0 0.7 0.3 0.1 0.3 0.2 – – 0.1 0.2 Mg – 0.5 0.2 0.1 1.0 2.0 10.0 0.1 10.0 0.1 K 0.4 8.0 1.0 0.02 1.0 1.0 1.0 – 1.0 0.3 Na 0.2 – – 0.01 – – 10.0 – 1.0 – Li – – – – – – 10.0 – 1.0 – Ca 1.0 1.0 0.3 1.0 1.0 1.0 1.0 1.0 10.0 0.1 Sb 1.0 0.7 0.3 1.0 0.3 0.5 1.0 – 1.0 – Mn 0.2 0.3 0.3 0.03 0.3 0.1 1.0 0.1 10.0 0.1 Zr 0.3 0.3 0.3 – 0.3 0.3 Matrix 5.0 10.0 – As 0.2 0.5 0.3 0.3 0.3 0.2 0.3 – 1.0 0.1 Pb 2.0 4.0 1.0 1.0 1.0 1.0 1.0 1.0 10.0 – Zn 0.7 0.4 0.3 0.3 0.3 0.3 0.3 0.1 1.0 – Sn 1.0 – 0.3 1.0 0.3 – 0.3 1.0 1.0 – Bi – – 0.3 1.0 0.3 – – – 10.0 –

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or applications in the nuclear industry call for refractory metals and their alloys of utmost purity. The most intensive impact on ultra-purity of refractory metals is presently exerted by the electronic industry for VLSI applications [4–6]. In a word, VLSI means miniaturization. The goal of VLSI development is to find ways to pack as many tiny electronic components as possible into the smallest possible space. Often, smaller circuits also operate faster and, ultimately, drastically cut the overall cost of computation, opening up new possibilities for applications. Continued evolution of ever smaller devices has aroused a renewed interest in the development of new metallization processes for low resistivity gates, interconnections, and ohmic contacts. Al, W, and Mo are notable among the metals proposed for gate and interconnection metallization. The use of Al, however, requires all postgate processing of devices to be limited to very low temperatures, preferably below 500°C. The use of refractory metals, such as W and Mo, requires a complete passivation of these metals against oxidizing environments, a deposition by means that will not lead to unwanted traps in the gate oxide, and reliable etching of metals for pattern generation. Uncertainties associated with the stability of these metal films have led to a search for alternatives. As a rule, the different components deposited onto the Si substrate by different sputtering/evaporation methods must be ultrapure, especially with respect to trace contaminants listed in **Table 1** where the impurity compositions are represented for refractory metals studied in this chapter. The wide variety of applications of ultrahigh purity refractory metals as sputter targets in microelectronics is really impressive. A great number of companies compete to offer ultrapure refractory metal materials for sputter targets. Materials presently in the microelectronics use are W/Ti, Mo,

, etc. As a rule, different components must be ultrapure, especially

). With increasing miniaturization,

by annealing a

, and Mg+

/Si structure at about 1000°C can be minimized. An oxidation of W is prevented by

a moist hydrogen atmosphere during annealing. Si is also oxidized in the similar ambient. The most effective solution for VLSI is by applying barrier layers, such as Ti/W thin layers, nitrides, or silicides of refractory metals. The use of barrier layers requires a rational technique for their deposition as well as the materials of an optimal chemical composition. Even using Ti/W thin films as both barrier and conducting layers, the most suitable and advanced deposition technique is the magnetron sputtering, which is widely employed in commercial microelectronics. Thin films of Ti/W quasi-alloys as diffusion barriers for metal contacts on Si are used very intensively in the last decades. The W in this composition is supposed to serve as an interlayer diffusion barrier and the Ti as both a deoxidizer and a stopper of the grain boundary diffusion. The well-known channeling is stopped by forming a thin

an intrinsic radioactivity also exerts harmful effects; therefore, various components must be "free" of U and Th contamination. Nonmetals (O, N, H, and C) are detrimental too, as are impurities of Fe, Co, and Ni, for certain applications. However, information on analytical methods used for a chemical characterization of such materials as well as on metallurgical techniques used for a preparation of materials is extremely scarce or sometimes also misleading. It is known that a metal gate cannot withstand to the oxidizing annealing ambient and a source-drain formation by ion implantation is difficult because of the channeling of doping ions through the gate metal during ion implantation. In the process developed for MOS

MoSi2

Me/SiO2

, WSi2

68 Very-Large-Scale Integration

, TaSi2

with respect to "mobile ions" (Li<sup>+</sup>

, TiSi2

, Na+ , K+ , Ca+

VLSI fabrication, W is used as the gate metal because a degradation of SiO2

69


**2. Production of highly pure refractory targets and thin films**

Naturally, in order to prepare highly pure sputter targets, the purest initial refractory metals are selected. For example, to produce the purest Ti sponge, the last versions of the Kroll process are included. Then a Ti sponge is elaborated with effective vacuum metallurgy techniques resulting highly pure metal Ti. In general, the basic way of a controlled purification of refractory metals from gas-forming interstitials and metal impurities is high-temperature vacuum melting or annealing. During this process the dissolved atoms of these impurities diffuse to the metal surface and desorb from it. According to modern representations [9, 10], the process of evolution of dissolved gas-forming atoms from the bulk of liquid metals to a vacuum consists of three successive stages: (*a*) a diffusion to the surface of the melt, (*b*) a transition through the interface to an adsorbed state, and (*c*) a surface recombination of adsorbed atoms with a formation and further desorption of diatomic molecules. Stage (*c*) in this chain is essentially nonlinear. Mechanisms of the O evolution depend on the metal nature and consist of the direct desorption of adsorbed O atoms in the atomic state and of the formation and further desorption of metal oxides of different stoichiometries. On the basis of principles of an evaporation deoxidation, the high-temperature behavior of O in refractory metals in vacuum can be roughly divided into three types. Ti, V, and Cr are characterized by a practically complete absence of the evaporation of O and metal oxides, because O in these metals is strongly bound with a metal matrix and has a very high thermal stability. The vapor pressure of the matrix metal (Ti, V, Cr) is much higher than other oxides of these metals. Mo and W are characterized by a high excess of the metal oxide vapor pressure above the metal vapor pressure; therefore dissolved and then chemosorbed O desorbs either independently or as metal oxides. Nb, Ta, Zr, and Hf behave intermediately. It seems that one has an opportunity for a preliminary estimate of the O behavior at the high-temperature vacuum treatment of both solid and liquid metals. A very different situation exists for C atoms which are strongly bound with metal and do not desorb independently. The basis of C evolution to vacuum is an interaction of O and C on the metal surface and further desorption in the form of gaseous CO. Naturally, it is very important to collect theoretical and experimental data on the behavior of such nonmetal impurities as O and C, because this information is a basis for the development of the commercial metallurgical technologies of the production of the high-purity refractory metals for microelectronics. A complex study has been fulfilled which allows one to establish the kinetic connection between the behavior of the mean concentrations of O and C. The dependence of this connection was studied on initial contents of gas-forming interstitials in liquid metals, as well as on the temperature, gaseous phase, and "diffusional transparency" of liquid metals. It has been shown that critical concentrations exist which are typical of each refractory metal. Below this critical concentration, O does not react with C, and the concentration of the latter during vacuum treatment remains constant. Experiments are also made, which demonstrated a high possibility of producing high-purity refractory metals. It has been shown that the "diffusional transparency," when diffusion does not influence chemical processes in liquid metals, can be realized in both vacuum levitation crucible-less melting and electron beam floating

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**2.1. Purification of refractory metals**

**Table 1.** Trace impurities in refractory metals participating in these studies.

layer of BPSG or WO<sup>x</sup> on the W [4]. Because barrier layers in integrated circuits simultaneously serve as conducting layers, it is very important to have all possible information on their physical characteristics. However, electric characteristics of Ti/W contacts to Si, which have naturally to be dependent on the film stoichiometry, structure, and purity of Ti/W thin films, are not studied in a whole concentration range in the Ti/W system. The only experimental data available are results for Ti/W alloys with a mean content of 10–30 at.% W because these quasi-alloys are supposed to be optimal ones for microelectronics. Other problems aroused are connected with the preparation of sputter targets of a known chemical composition and required purity. A preparation of targets by the powder metallurgy (PM) techniques when compacted targets are manufactured using procedures such as powder mixing, hot pressing, hot rolling, and annealing is fraught with the contamination by a considerable amount of impurities, especially gas-forming ones. Thus, it can be said that the impurity content in targets prepared by PM techniques is predetermined by the preparation technique itself. As a result, there exists a possibility of a strong instability of the sputtering process due to an intensive gas release from the compacted powder target and even unpredictable fracture of sputtering components because of the explosive-like gas release at higher temperatures. It seems that a solution of this problem is in the combination of high-pressure techniques and in situ high-temperature annealing of PM compacted targets in a high vacuum [7]. Such a complex procedure allows one to produce PM compacted targets with a density which is nearly equal to the tabulated one of the material. An alternative to PM techniques is the use of cast targets produced from high-purity cast refractory metals without contaminating procedures like open-air hot pressing or hot rolling [8]. When it is necessary to prepare thin films of alloys, targets composed of cast metal blocks or co-sputtering of several cast metal targets can be used. It is known that TiW alloys cannot be produced by conventional melting procedures because of the great difference of their melting temperatures of both components. The sputtering or co-sputtering of cast metal targets seems to be the most promising ones owing to their flexibility and reliability, i.e., it is possible to obtain any necessary chemical composition of films due to the wide choice of compositions of "mosaic" targets, as well as deposition rates of each metal component during co-sputtering. One of the sections in the chapter will be discussing the experimental results of studies of the deposition of Ti/W thin films with different Ti/W ratios, made by magnetron sputtering of two cast metal targets, as well as of the dependence of the electrical resistivity on the Ti/W ratio. In other sections results of a deposition of thin films of other high-purity refractory elemental metals like Mo, W, Ti, and Co will be presented as well as the preparation of cast disilicide targets and deposition of thin films of disilicides for diffusion barriers of a high physical quality.

### **2. Production of highly pure refractory targets and thin films**

### **2.1. Purification of refractory metals**

layer of BPSG or WO<sup>x</sup>

70 Very-Large-Scale Integration

on the W [4]. Because barrier layers in integrated circuits simultane-

ously serve as conducting layers, it is very important to have all possible information on their physical characteristics. However, electric characteristics of Ti/W contacts to Si, which have naturally to be dependent on the film stoichiometry, structure, and purity of Ti/W thin films, are not studied in a whole concentration range in the Ti/W system. The only experimental data available are results for Ti/W alloys with a mean content of 10–30 at.% W because these quasi-alloys are supposed to be optimal ones for microelectronics. Other problems aroused are connected with the preparation of sputter targets of a known chemical composition and required purity. A preparation of targets by the powder metallurgy (PM) techniques when compacted targets are manufactured using procedures such as powder mixing, hot pressing, hot rolling, and annealing is fraught with the contamination by a considerable amount of impurities, especially gas-forming ones. Thus, it can be said that the impurity content in targets prepared by PM techniques is predetermined by the preparation technique itself. As a result, there exists a possibility of a strong instability of the sputtering process due to an intensive gas release from the compacted powder target and even unpredictable fracture of sputtering components because of the explosive-like gas release at higher temperatures. It seems that a solution of this problem is in the combination of high-pressure techniques and in situ high-temperature annealing of PM compacted targets in a high vacuum [7]. Such a complex procedure allows one to produce PM compacted targets with a density which is nearly equal to the tabulated one of the material. An alternative to PM techniques is the use of cast targets produced from high-purity cast refractory metals without contaminating procedures like open-air hot pressing or hot rolling [8]. When it is necessary to prepare thin films of alloys, targets composed of cast metal blocks or co-sputtering of several cast metal targets can be used. It is known that TiW alloys cannot be produced by conventional melting procedures because of the great difference of their melting temperatures of both components. The sputtering or co-sputtering of cast metal targets seems to be the most promising ones owing to their flexibility and reliability, i.e., it is possible to obtain any necessary chemical composition of films due to the wide choice of compositions of "mosaic" targets, as well as deposition rates of each metal component during co-sputtering. One of the sections in the chapter will be discussing the experimental results of studies of the deposition of Ti/W thin films with different Ti/W ratios, made by magnetron sputtering of two cast metal targets, as well as of the dependence of the electrical resistivity on the Ti/W ratio. In other sections results of a deposition of thin films of other high-purity refractory elemental metals like Mo, W, Ti, and Co will be presented as well as the preparation of cast disilicide targets and deposition of thin films

**Impurity Mo Ti Ta W Nb V Zr Hf Co Ni** V 0.5 1.0 1.0 0.4 1.0 Matrix 1.0 1.0 10.0 – U 0.005 0.006 – 0.005 – – – – 0.005 0.05 Th 0.005 0.006 – 0.005 – – – – 0.005 0.05

**Table 1.** Trace impurities in refractory metals participating in these studies.

of disilicides for diffusion barriers of a high physical quality.

Naturally, in order to prepare highly pure sputter targets, the purest initial refractory metals are selected. For example, to produce the purest Ti sponge, the last versions of the Kroll process are included. Then a Ti sponge is elaborated with effective vacuum metallurgy techniques resulting highly pure metal Ti. In general, the basic way of a controlled purification of refractory metals from gas-forming interstitials and metal impurities is high-temperature vacuum melting or annealing. During this process the dissolved atoms of these impurities diffuse to the metal surface and desorb from it. According to modern representations [9, 10], the process of evolution of dissolved gas-forming atoms from the bulk of liquid metals to a vacuum consists of three successive stages: (*a*) a diffusion to the surface of the melt, (*b*) a transition through the interface to an adsorbed state, and (*c*) a surface recombination of adsorbed atoms with a formation and further desorption of diatomic molecules. Stage (*c*) in this chain is essentially nonlinear. Mechanisms of the O evolution depend on the metal nature and consist of the direct desorption of adsorbed O atoms in the atomic state and of the formation and further desorption of metal oxides of different stoichiometries. On the basis of principles of an evaporation deoxidation, the high-temperature behavior of O in refractory metals in vacuum can be roughly divided into three types. Ti, V, and Cr are characterized by a practically complete absence of the evaporation of O and metal oxides, because O in these metals is strongly bound with a metal matrix and has a very high thermal stability. The vapor pressure of the matrix metal (Ti, V, Cr) is much higher than other oxides of these metals. Mo and W are characterized by a high excess of the metal oxide vapor pressure above the metal vapor pressure; therefore dissolved and then chemosorbed O desorbs either independently or as metal oxides. Nb, Ta, Zr, and Hf behave intermediately. It seems that one has an opportunity for a preliminary estimate of the O behavior at the high-temperature vacuum treatment of both solid and liquid metals. A very different situation exists for C atoms which are strongly bound with metal and do not desorb independently. The basis of C evolution to vacuum is an interaction of O and C on the metal surface and further desorption in the form of gaseous CO. Naturally, it is very important to collect theoretical and experimental data on the behavior of such nonmetal impurities as O and C, because this information is a basis for the development of the commercial metallurgical technologies of the production of the high-purity refractory metals for microelectronics. A complex study has been fulfilled which allows one to establish the kinetic connection between the behavior of the mean concentrations of O and C. The dependence of this connection was studied on initial contents of gas-forming interstitials in liquid metals, as well as on the temperature, gaseous phase, and "diffusional transparency" of liquid metals. It has been shown that critical concentrations exist which are typical of each refractory metal. Below this critical concentration, O does not react with C, and the concentration of the latter during vacuum treatment remains constant. Experiments are also made, which demonstrated a high possibility of producing high-purity refractory metals. It has been shown that the "diffusional transparency," when diffusion does not influence chemical processes in liquid metals, can be realized in both vacuum levitation crucible-less melting and electron beam floating zone melting because transport limitations can be removed by the constant renewal of the reaction surface. As for purifying refractory metals from metal impurities, it is important to emphasize that melting temperatures of refractory metals are high enough comparing with ones of many dissolved metal impurities in refractory matrixes. During high-temperature vacuum melting or annealing of refractory metals, dissolved atoms of gas-forming and metallic impurities diffuse to the metal surface and desorb from it. It means that there are optimal conditions for vacuum evaporation of metal impurities because their vapor pressure becomes very high at *T*m of refractory metals. Optimal conditions of a vacuum refining have been identified and demonstrated a possibility of the production of Mo, W, Ti, Co, and other refractory metals having low contents of O and C (about 10−6 at.%) [11–16]. The opportunity has been demonstrated of the preparation of high-purity refractory metals, when contents of both C and O are at the determination level of the analytical techniques, such as deuteron activation, fast neutron activation, and mass spectrometry with inductively coupled plasma. The relationship between the purity of refractory metals and physical quality of deposited thin films was studied depending on the magnetron and laser sputtering conditions. This is not surprising since only gradually is it realized by scientific community dealing with these materials that the preparation of ultrapure refractory metals might be less difficult than a suitable and thorough trace chemical characterization. It is obvious that the analytic data at the ppb level are difficult to obtain and that interlaboratory comparisons exhibit a scatter of values, which is inversely proportional to the concentration level. This is a natural phenomenon symbolizing the state of the art of the analytical characterization of materials and should not be interpreted as an incompetency of analytical laboratories involved. **Figure 1** gives a rough estimate of the situation experienced by participants in many round robins analyses. However, a scatter of analytical round robin results, especially, on the ppb level of analysis is very hard—discrepancies between results of same samples but at different labs could achieve 100% and more. This is not too surprising that a scientific community has to understand gradually and to realize when dealing with these metals that the preparation of ultrapure refractory metals might be less problematic than its elemental characterization [2, 3]. Analytic measurements at the ppm and ppb levels are difficult to obtain, and that interlaboratory comparisons exhibit a scatter of values, which is inversely proportional to a concentration level. This is a natural phenomenon symbolizing the state of the art of the analytical characterization of materials

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Three main metallurgical procedures are developed to produce cast refractory metals of high purity for magnetron targets. Procedure #1 is the complex technology for producing elemental metal ingots/targets and bimetallic targets (e.g., Mo/Cu). It consisted of multiple electron beam (EB) vacuum melting of PM compacted blanks of refractory metals, hot pressing, hot rolling, electrochemical etching, electrochemical plating, high-pressure vacuum diffusion welding at high temperatures, machining, etc. Then the bimetallic Mo/Cu targets can be made of the Mo sheet and copper base joined together by vacuum diffusion welding. The upper high-purity Mo sheet of bimetallic Mo/Cu targets serves as a sputter material, whereas the Cu base serves as a heat-conducting material. Similar experiments are successfully done on other metal pairs such as Mo/Cu, W/Cu, Nb/Cu, NiV/Cu, etc. However, the most reliable results are obtained at the production of Mo/Cu. In spite of the lack of a reliable experience of using such targets in commercial sputter setups before, with this technology, hundreds of bimetallic targets are produced for several commercial microelectronics companies in Russia. Procedure #2 consists of multiple EB melting of PM compacted blanks in a vacuum of 1 ×10−6 Torr. Sometimes, the poly- and single-crystalline rods of EB floating zone melting can be used because they are much purer than PM sintered blanks. Two types of water-cooled copper molds, vertical and horizontal, are used for melting and solidification of round ingots of 80–150 mm in diameter and 1.300 mm length and flat ingots of sizes 35×100×1300 mm. Then ingots are carefully deformed and/or machined to get sputter targets. The rectangular and cylindrical molds are used to produce disks or plates of different sizes and diameters (80–210 mm). Procedure #3 is a duplex process, e.g., it consists of multiple EB vacuum melting and/or electric arc vacuum melting [16]. The liquid metal in the mold of the electric arc vacuum setup is intensively stirred by the electromagnetic field of the powerful electromagnetic solenoid. Thus, in this combination, EB vacuum melting is used mainly for a vacuum purification of liquid metals from gas-forming interstitials and metallic impurities, while electric arc vacuum melting is used mainly to produce ingots with a fine-grained macrostructure (this combination of tech-

and should not be interpreted as an incompetency of analytical laboratories involved.

**2.2. Technologies for production of refractory metals**

niques was used mainly for producing W or Mo).

10–20 Ω cm with/without a thin film (about 0.3 μm) of SiO2

**2.3. Sputter of targets and deposition of thin films of refractory metals**

Micro-metallurgy aspects imply a study of the magnetron sputtering and deposition of thin films and to study an influence of some parameters of the thin-film metallization on physical properties of deposited metal films. Refractory metal films are deposited on Si(100) wafers of

strates are cleaned chemically prior to be loaded into the magnetron sputter apparatus. For

at room temperature. The Si sub-

**Figure 1.** Scatter of round robin results at the trace and ultra-trace levels as a function of concentration levels of trace components.

realize when dealing with these metals that the preparation of ultrapure refractory metals might be less problematic than its elemental characterization [2, 3]. Analytic measurements at the ppm and ppb levels are difficult to obtain, and that interlaboratory comparisons exhibit a scatter of values, which is inversely proportional to a concentration level. This is a natural phenomenon symbolizing the state of the art of the analytical characterization of materials and should not be interpreted as an incompetency of analytical laboratories involved.

### **2.2. Technologies for production of refractory metals**

zone melting because transport limitations can be removed by the constant renewal of the reaction surface. As for purifying refractory metals from metal impurities, it is important to emphasize that melting temperatures of refractory metals are high enough comparing with ones of many dissolved metal impurities in refractory matrixes. During high-temperature vacuum melting or annealing of refractory metals, dissolved atoms of gas-forming and metallic impurities diffuse to the metal surface and desorb from it. It means that there are optimal conditions for vacuum evaporation of metal impurities because their vapor pressure becomes very high at *T*m of refractory metals. Optimal conditions of a vacuum refining have been identified and demonstrated a possibility of the production of Mo, W, Ti, Co, and other refractory metals having low contents of O and C (about 10−6 at.%) [11–16]. The opportunity has been demonstrated of the preparation of high-purity refractory metals, when contents of both C and O are at the determination level of the analytical techniques, such as deuteron activation, fast neutron activation, and mass spectrometry with inductively coupled plasma. The relationship between the purity of refractory metals and physical quality of deposited thin films was studied depending on the magnetron and laser sputtering conditions. This is not surprising since only gradually is it realized by scientific community dealing with these materials that the preparation of ultrapure refractory metals might be less difficult than a suitable and thorough trace chemical characterization. It is obvious that the analytic data at the ppb level are difficult to obtain and that interlaboratory comparisons exhibit a scatter of values, which is inversely proportional to the concentration level. This is a natural phenomenon symbolizing the state of the art of the analytical characterization of materials and should not be interpreted as an incompetency of analytical laboratories involved. **Figure 1** gives a rough estimate of the situation experienced by participants in many round robins analyses. However, a scatter of analytical round robin results, especially, on the ppb level of analysis is very hard—discrepancies between results of same samples but at different labs could achieve 100% and more. This is not too surprising that a scientific community has to understand gradually and to

**Figure 1.** Scatter of round robin results at the trace and ultra-trace levels as a function of concentration levels of trace

components.

72 Very-Large-Scale Integration

Three main metallurgical procedures are developed to produce cast refractory metals of high purity for magnetron targets. Procedure #1 is the complex technology for producing elemental metal ingots/targets and bimetallic targets (e.g., Mo/Cu). It consisted of multiple electron beam (EB) vacuum melting of PM compacted blanks of refractory metals, hot pressing, hot rolling, electrochemical etching, electrochemical plating, high-pressure vacuum diffusion welding at high temperatures, machining, etc. Then the bimetallic Mo/Cu targets can be made of the Mo sheet and copper base joined together by vacuum diffusion welding. The upper high-purity Mo sheet of bimetallic Mo/Cu targets serves as a sputter material, whereas the Cu base serves as a heat-conducting material. Similar experiments are successfully done on other metal pairs such as Mo/Cu, W/Cu, Nb/Cu, NiV/Cu, etc. However, the most reliable results are obtained at the production of Mo/Cu. In spite of the lack of a reliable experience of using such targets in commercial sputter setups before, with this technology, hundreds of bimetallic targets are produced for several commercial microelectronics companies in Russia. Procedure #2 consists of multiple EB melting of PM compacted blanks in a vacuum of 1 ×10−6 Torr. Sometimes, the poly- and single-crystalline rods of EB floating zone melting can be used because they are much purer than PM sintered blanks. Two types of water-cooled copper molds, vertical and horizontal, are used for melting and solidification of round ingots of 80–150 mm in diameter and 1.300 mm length and flat ingots of sizes 35×100×1300 mm. Then ingots are carefully deformed and/or machined to get sputter targets. The rectangular and cylindrical molds are used to produce disks or plates of different sizes and diameters (80–210 mm). Procedure #3 is a duplex process, e.g., it consists of multiple EB vacuum melting and/or electric arc vacuum melting [16]. The liquid metal in the mold of the electric arc vacuum setup is intensively stirred by the electromagnetic field of the powerful electromagnetic solenoid. Thus, in this combination, EB vacuum melting is used mainly for a vacuum purification of liquid metals from gas-forming interstitials and metallic impurities, while electric arc vacuum melting is used mainly to produce ingots with a fine-grained macrostructure (this combination of techniques was used mainly for producing W or Mo).

#### **2.3. Sputter of targets and deposition of thin films of refractory metals**

Micro-metallurgy aspects imply a study of the magnetron sputtering and deposition of thin films and to study an influence of some parameters of the thin-film metallization on physical properties of deposited metal films. Refractory metal films are deposited on Si(100) wafers of 10–20 Ω cm with/without a thin film (about 0.3 μm) of SiO2 at room temperature. The Si substrates are cleaned chemically prior to be loaded into the magnetron sputter apparatus. For depositing thin films of metals, magnetron sputter apparatuses of two kinds are used: (*a*) the magnetron sputter system with the planetary arrangement of Si substrates for thin film depositing and (*b*) the conveyer system when Si substrates are deposited during traveling through different chambers of the apparatus. A special care is taken to exclude such contaminants as O, C, and alkaline metals from the apparatus environment. A vacuum at the sputter vessel is about 10−6 Torr prior to sputtering. Magnetron targets are cleaned preliminary for 40 min in vacuum. During sputtering, the vessel is filled with Ar of high purity to a pressure of about 10−3 Pa. The relative atomic impurity concentration of Ar is less than 3×10−6 %. Before sputtering, a heating of Si wafers to 250–300°C is carried out. It has been found that such a procedure is sufficient to produce a clean surface. The deposition rate is practically proportional to the sputtering power for high-purity refractory metals at a constant pressure in a sputtering vessel (**Figure 2**).

used for a production of targets, on the specific resistivity of thin refractory metal films, there are sputtered targets produced both by the standard PM procedure and EB vacuum melting. The content of gas-forming elements (C, O, N) in PM Mo targets is at least 100 times higher than in EBM Mo targets. It should be also mentioned that after prolong vacuum annealing of both targets and thin films, the content of gas-forming interstitials is still very high. The specific resistivity of Mo films of 0.15–1.0 μm thick deposited by sputtering the PM and EBM

These results show that an initial purity of the target metal has a very strong influence on the specific resistivity of thin Mo films. After long sputtering, magnetron targets have an erosion path of about 10 mm depth and 20 mm width, and the further sputtering process is characterized by a little bit higher instability. The quantity of sputtered material is about 15–20% of the mass of the target depending on the target design and intensity of a sputtering process. This also shows that the design of targets and magnetrons should be optimal. An effect of a substrate heating on the specific resistivity is studied. When films are deposited on unheated substrates, their electric resistivity is increased by 50–150%, and the scatter of the specific resistivity is greater by 30–40%. This can be accounted for an influence of gas-forming impurities adsorbed on the surface of substrates. A confirmation of this fact is found in the lowering of the specific resistivity of Mo films deposited on unheated substrates with sublayers of Ti or V. These metals are sputtered from targets in the same sputtering vessel and probably react with gases adsorbed on a substrate surface. It is supposed that additional thin layers should not have a strong effect on resistivity measurements. To elucidate the influence of gas-forming impurities on the specific resistivity of refractory metal films, the sputtering power (or deposition rate) is varied and an air is introduced

that the specific resistivity of high-purity films of Mo, Ti, and Zr depends strongly on the deposition rate and on the presence of reactive gases in the deposition area (**Figure 3**). The ratio of the

higher the ratio, the less clean is the procedure. In other words, the specific resistivity of the films depends on the ratio of quantities of sputtered (deposited) atoms and interstitials dissolved in the metal films. The dependence of the specific resistivity on interstitials dissolved in the deposited

= (1 + γ*mS*/γ*<sup>g</sup>*

the metal deposition and condensation of molecules of *n-*atomic reactive gases in the refractory metal film, respectively, and *S* is a deposition area. The rate of dissolution of reactive gasses in the deposited metal film is much higher than the rate of a gas exchange in the deposition area of

that the rate of dissolution of reactive gases in the film is constant. Because the quantity of metal atoms, γ*mS*, which is sputtered in a unit time is nearly proportional to the sputtering power *W*, we had γ*mS* = *kW*, where *k* is the coefficient of proportionality. This coefficient changes slowly with sputter parameters and is determined by dependence of the sputtering coefficient of refractory metals on the energy of sputtering ions and the geometry of the sputtering setup. Considering

)

interstitial content in the film on the ratio of the sputtering power to the reactive gas flow into the deposition area. The dependence allows us to present curves in **Figure 3** as the dependence of the specific resistivity on the atomic concentration of interstitials in films (**Figure 4**). The air leakage

film is studied (**Figure 4**). To analyze this dependence, the atomic concentration *C*<sup>i</sup>

= (1 + *kW*/*nQ*<sup>i</sup>

to the target resistivity ρm is a characteristic of the procedure as a whole: the

*S*)

s−1) during sputtering. Experiments have confirmed

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−1, where γ*m* and γ*<sup>g</sup>*

, we had *Q*<sup>i</sup>

= γ*<sup>g</sup>*

−l. This equation describes the dependence of

of interstitials

are specific rates of

*S*. Here, it is assumed

targets under the same sputtering conditions are 20–35 and 5.17 μΩ cm, respectively.

(1 ×10−5, 4 ×10−3, 1.3 ×10−4, and 4 ×10−4 Pa m3

from reactive gases can be written as *C*<sup>i</sup>

these equations, we can receive *C*<sup>i</sup>

the magnetron sputtering setup, e.g., for the air leakage *Q*<sup>i</sup>

film resistivity ρ<sup>v</sup>

As-deposited films are annealed in vacuum. The sputter rate and layer thickness are controlled with the microprocessor and profilometer, respectively. The electrical resistivity of films is measured using a standard four-point probe. Generally speaking, film properties are affected not only by a deposition process as a whole but also by an initial quality of sputter targets. The specific resistivity of cast metal targets and thin films of highly pure refractory metals are shown in **Table 2**. It is well known that the specific resistivity of refractory metals is an integral characteristic of their purity. To study the influence of macro-metallurgical procedures,

**Figure 2.** Dependence of a sputter rate for refractory metals on a sputter power at *P*Ar=1 Pa.


**Table 2.** Specific resistivity of films and cast metal targets produced of highly pure refractory metals.

used for a production of targets, on the specific resistivity of thin refractory metal films, there are sputtered targets produced both by the standard PM procedure and EB vacuum melting. The content of gas-forming elements (C, O, N) in PM Mo targets is at least 100 times higher than in EBM Mo targets. It should be also mentioned that after prolong vacuum annealing of both targets and thin films, the content of gas-forming interstitials is still very high. The specific resistivity of Mo films of 0.15–1.0 μm thick deposited by sputtering the PM and EBM targets under the same sputtering conditions are 20–35 and 5.17 μΩ cm, respectively.

depositing thin films of metals, magnetron sputter apparatuses of two kinds are used: (*a*) the magnetron sputter system with the planetary arrangement of Si substrates for thin film depositing and (*b*) the conveyer system when Si substrates are deposited during traveling through different chambers of the apparatus. A special care is taken to exclude such contaminants as O, C, and alkaline metals from the apparatus environment. A vacuum at the sputter vessel is about 10−6 Torr prior to sputtering. Magnetron targets are cleaned preliminary for 40 min in vacuum. During sputtering, the vessel is filled with Ar of high purity to a pressure of about 10−3 Pa. The relative atomic impurity concentration of Ar is less than 3×10−6 %. Before sputtering, a heating of Si wafers to 250–300°C is carried out. It has been found that such a procedure is sufficient to produce a clean surface. The deposition rate is practically proportional to the sputtering power

for high-purity refractory metals at a constant pressure in a sputtering vessel (**Figure 2**).

**Condition Metal**

74 Very-Large-Scale Integration

As-deposited films are annealed in vacuum. The sputter rate and layer thickness are controlled with the microprocessor and profilometer, respectively. The electrical resistivity of films is measured using a standard four-point probe. Generally speaking, film properties are affected not only by a deposition process as a whole but also by an initial quality of sputter targets. The specific resistivity of cast metal targets and thin films of highly pure refractory metals are shown in **Table 2**. It is well known that the specific resistivity of refractory metals is an integral characteristic of their purity. To study the influence of macro-metallurgical procedures,

**Mo W V Nb Ta Ti Zr Hf**

Film 5.17 15.0 27.1 17.4 16.8 49.2 41.8 48.3 Target 5.2 5.5 25.0 – 12.7 41.7 – –

**Table 2.** Specific resistivity of films and cast metal targets produced of highly pure refractory metals.

**Figure 2.** Dependence of a sputter rate for refractory metals on a sputter power at *P*Ar=1 Pa.

These results show that an initial purity of the target metal has a very strong influence on the specific resistivity of thin Mo films. After long sputtering, magnetron targets have an erosion path of about 10 mm depth and 20 mm width, and the further sputtering process is characterized by a little bit higher instability. The quantity of sputtered material is about 15–20% of the mass of the target depending on the target design and intensity of a sputtering process. This also shows that the design of targets and magnetrons should be optimal. An effect of a substrate heating on the specific resistivity is studied. When films are deposited on unheated substrates, their electric resistivity is increased by 50–150%, and the scatter of the specific resistivity is greater by 30–40%. This can be accounted for an influence of gas-forming impurities adsorbed on the surface of substrates. A confirmation of this fact is found in the lowering of the specific resistivity of Mo films deposited on unheated substrates with sublayers of Ti or V. These metals are sputtered from targets in the same sputtering vessel and probably react with gases adsorbed on a substrate surface. It is supposed that additional thin layers should not have a strong effect on resistivity measurements. To elucidate the influence of gas-forming impurities on the specific resistivity of refractory metal films, the sputtering power (or deposition rate) is varied and an air is introduced (1 ×10−5, 4 ×10−3, 1.3 ×10−4, and 4 ×10−4 Pa m3 s−1) during sputtering. Experiments have confirmed that the specific resistivity of high-purity films of Mo, Ti, and Zr depends strongly on the deposition rate and on the presence of reactive gases in the deposition area (**Figure 3**). The ratio of the film resistivity ρ<sup>v</sup> to the target resistivity ρm is a characteristic of the procedure as a whole: the higher the ratio, the less clean is the procedure. In other words, the specific resistivity of the films depends on the ratio of quantities of sputtered (deposited) atoms and interstitials dissolved in the metal films. The dependence of the specific resistivity on interstitials dissolved in the deposited film is studied (**Figure 4**). To analyze this dependence, the atomic concentration *C*<sup>i</sup> of interstitials from reactive gases can be written as *C*<sup>i</sup> = (1 + γ*mS*/γ*<sup>g</sup> S*) −1, where γ*m* and γ*<sup>g</sup>* are specific rates of the metal deposition and condensation of molecules of *n-*atomic reactive gases in the refractory metal film, respectively, and *S* is a deposition area. The rate of dissolution of reactive gasses in the deposited metal film is much higher than the rate of a gas exchange in the deposition area of the magnetron sputtering setup, e.g., for the air leakage *Q*<sup>i</sup> , we had *Q*<sup>i</sup> = γ*<sup>g</sup> S*. Here, it is assumed that the rate of dissolution of reactive gases in the film is constant. Because the quantity of metal atoms, γ*mS*, which is sputtered in a unit time is nearly proportional to the sputtering power *W*, we had γ*mS* = *kW*, where *k* is the coefficient of proportionality. This coefficient changes slowly with sputter parameters and is determined by dependence of the sputtering coefficient of refractory metals on the energy of sputtering ions and the geometry of the sputtering setup. Considering these equations, we can receive *C*<sup>i</sup> = (1 + *kW*/*nQ*<sup>i</sup> ) −l. This equation describes the dependence of interstitial content in the film on the ratio of the sputtering power to the reactive gas flow into the deposition area. The dependence allows us to present curves in **Figure 3** as the dependence of the specific resistivity on the atomic concentration of interstitials in films (**Figure 4**). The air leakage

performance of IC necessitates the search for materials and the development of a technology for the deposition of films in addition to or replacing the traditionally used Al (due to the appearance of high-temperature processes) and poly-Si having a high surface resistance. The renewed interest in the use in the IC of refractory metals, e.g., Mo [17, 18], nevertheless, is complicated by difficulties in obtaining films with properties of massive samples. Mo has a rather low specific resistivity and the closest to Si value of the coefficient of thermal expansion.

a sufficiently high resistance to a mechanical damage. In addition, Mo forms ohmic contacts

ment is done by comparing a high-purity Mo target with a conventional one. It is shown that alkaline metals move easily in gate insulation films and deteriorate properties of MOS interface. The high-purity target which contains no more than 0.01–0.03 ppm Na and K and the conventional one with about 10 ppm of these metals are used in this experiment. The mobile ion quantity in the Mo gate MOS diodes which are produced with either the high-purity target or conventional one are compared before and after the annealing. Results show that no mobile ions are observed in the diode made with the high-purity target. The experiments conducted using W targets show similar results as well. By using several W targets which contained different amounts of Na, it is reported that there is a strong correlation between Na content and the amount of mobile ions in gate electrodes. In [7, 17], it is suggested that α-rays, directly radiated from electrode and interconnecting materials, are the worst factor in the operational reliability of the highly integrated VLSI. The amounts of α-rays radiated from Mo thin films formed by low or high U content targets are <1 and 700 ppb in the high pure targets and conventional targets, respectively; <1 and 280 ppb in the high pure Mo thin films and conventional Mo thin films, respectively; and <4.2 ×10−5 α cm−2 h−1 and 1.2 ×10−2 α cm−2 h−1 from the high pure and conventional Mo thin films, respectively. As can be seen from these results, there is a remarkable difference in amounts of α-rays which causes errors. Some decades ago, sputter targets contained several tens ppb and even ppm of U, while now in production scale, targets can often contain less than 1 ppb. EB evaporation makes it possible to obtain films with the

= 15 μΩ cm only when the substrates are heated during the deposition

O, etc.) in the area of the discharge led to a relatively high

V cm−1 are applied. This imposes additional con-

to 400°C and higher. Cathode sputtering due to the high reactivity of Mo, low deposition rate (<0.5 nm s−1), and difficulties in providing sufficiently small partial pressures of contaminating

level of the resistivity (higher than 30 μΩ cm). Magnetron sputtering systems that provide deposition rates at the level of 1–2 nm s−1 and above make the study of the feasibility of using this method of depositing refractory metal films for the fabrication of IC, in particular with MOS structures. It should be noted that such structures, *ceteris paribus*, are particularly sensitive to impurities such as alkali metals, which diffuse rapidly in the ionized state through

ditions on the parameters of the target material and, of course, on film deposition conditions

In our study [19] of Mo films, the procedure #1 is mainly used for purification and production of high-purity Mo targets. It is consisted of multiple EB melting of commercial PM bars/

—the most widely used dielectric in the IC—and has

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77

). In [17], an interesting experi-

It practically does not interact with SiO2

specific resistivity ρ<sup>v</sup>

dielectric SiO2

gas-forming impurities (O, N, H2

*2.4.2. Depositing molybdenum films*

films when voltage fields 10<sup>5</sup>

with Si with a comparatively low resistance (10−5 to 10−4 Ω cm2

**Figure 3.** Dependence of film resistivity on sputtering power *W* and current leakage *Q*.

**Figure 4.** Resistivity ratio as function of interstitial content in the deposited films.

influence becomes very strong as the atomic concentration of interstitials in the film becomes higher than about 10−3 at.% (about 10 ppm).

#### **2.4. Depositing molybdenum layers**

#### *2.4.1. Short background*

Materials and technology of the deposition of thin metal films largely determine a level of performance and reliability of integrated circuits. Increasing the degree of integration and performance of IC necessitates the search for materials and the development of a technology for the deposition of films in addition to or replacing the traditionally used Al (due to the appearance of high-temperature processes) and poly-Si having a high surface resistance. The renewed interest in the use in the IC of refractory metals, e.g., Mo [17, 18], nevertheless, is complicated by difficulties in obtaining films with properties of massive samples. Mo has a rather low specific resistivity and the closest to Si value of the coefficient of thermal expansion. It practically does not interact with SiO2 —the most widely used dielectric in the IC—and has a sufficiently high resistance to a mechanical damage. In addition, Mo forms ohmic contacts with Si with a comparatively low resistance (10−5 to 10−4 Ω cm2 ). In [17], an interesting experiment is done by comparing a high-purity Mo target with a conventional one. It is shown that alkaline metals move easily in gate insulation films and deteriorate properties of MOS interface. The high-purity target which contains no more than 0.01–0.03 ppm Na and K and the conventional one with about 10 ppm of these metals are used in this experiment. The mobile ion quantity in the Mo gate MOS diodes which are produced with either the high-purity target or conventional one are compared before and after the annealing. Results show that no mobile ions are observed in the diode made with the high-purity target. The experiments conducted using W targets show similar results as well. By using several W targets which contained different amounts of Na, it is reported that there is a strong correlation between Na content and the amount of mobile ions in gate electrodes. In [7, 17], it is suggested that α-rays, directly radiated from electrode and interconnecting materials, are the worst factor in the operational reliability of the highly integrated VLSI. The amounts of α-rays radiated from Mo thin films formed by low or high U content targets are <1 and 700 ppb in the high pure targets and conventional targets, respectively; <1 and 280 ppb in the high pure Mo thin films and conventional Mo thin films, respectively; and <4.2 ×10−5 α cm−2 h−1 and 1.2 ×10−2 α cm−2 h−1 from the high pure and conventional Mo thin films, respectively. As can be seen from these results, there is a remarkable difference in amounts of α-rays which causes errors. Some decades ago, sputter targets contained several tens ppb and even ppm of U, while now in production scale, targets can often contain less than 1 ppb. EB evaporation makes it possible to obtain films with the specific resistivity ρ<sup>v</sup> = 15 μΩ cm only when the substrates are heated during the deposition to 400°C and higher. Cathode sputtering due to the high reactivity of Mo, low deposition rate (<0.5 nm s−1), and difficulties in providing sufficiently small partial pressures of contaminating gas-forming impurities (O, N, H2 O, etc.) in the area of the discharge led to a relatively high level of the resistivity (higher than 30 μΩ cm). Magnetron sputtering systems that provide deposition rates at the level of 1–2 nm s−1 and above make the study of the feasibility of using this method of depositing refractory metal films for the fabrication of IC, in particular with MOS structures. It should be noted that such structures, *ceteris paribus*, are particularly sensitive to impurities such as alkali metals, which diffuse rapidly in the ionized state through dielectric SiO2 films when voltage fields 10<sup>5</sup> V cm−1 are applied. This imposes additional conditions on the parameters of the target material and, of course, on film deposition conditions

#### *2.4.2. Depositing molybdenum films*

influence becomes very strong as the atomic concentration of interstitials in the film becomes

Materials and technology of the deposition of thin metal films largely determine a level of performance and reliability of integrated circuits. Increasing the degree of integration and

higher than about 10−3 at.% (about 10 ppm).

**Figure 4.** Resistivity ratio as function of interstitial content in the deposited films.

**Figure 3.** Dependence of film resistivity on sputtering power *W* and current leakage *Q*.

**2.4. Depositing molybdenum layers**

*2.4.1. Short background*

76 Very-Large-Scale Integration

In our study [19] of Mo films, the procedure #1 is mainly used for purification and production of high-purity Mo targets. It is consisted of multiple EB melting of commercial PM bars/ rods at a melting rate of about 0.5 kg min−1 in a vacuum of 1×10−6 Torr. The power is 250 kW at an accelerating voltage of 25 kV and an emission current of 4 A. Two types of water-cooled copper crystallizers (molds) are used: cylindrical and rectangular. Analysis of the impurity content in Mo targets before sputtering is carried out by means of highly sensitive analytical methods: fast neutron activation, deuteron activation, mass spectrometry with inductively coupled ions, etc. The trace element composition of Mo targets is represented in **Table 1**. Mo films are deposited on Si(100) wafers (10–20 Ω cm) with/without a thin film (about 0.3 μm) of SiO2 at room temperature. Substrates are cleaned chemically prior to load into a magnetron sputter apparatus. The sputtering chamber pressure is 10−6 Torr prior to sputtering; magnetron targets are trained for 40 min in vacuum. During sputtering, the chamber is filled with Ar of high purity to 10−3 Torr. Before sputtering, a heating of Si wafers at 250–300°C is carried out. It has been found that such a procedure is sufficient to produce a clean surface. The deposition rate is practically proportional to the sputtering power at a constant pressure in the sputtering chamber. The resistivity of samples of EB-melted Mo is 5.2–5.6 μΩ cm. The specific resistivity of Mo films 0.15–1.0 μm thick deposited from PM targets under same sputtering conditions is 20–35 μΩ cm. These experiments show that an initial purity of target has a very strong influence on the resistivity of thin Mo films. An effect of a substrate heating on the specific resistivity is also studied. An increased scatter of the resistivity is accounted for by the influence of gaseous impurities adsorbed on the substrate surface. To elucidate the influence of gaseous impurities in the specific resistivity of the Mo films, a sputtering power (a deposition rate) is varied, and an air leakage is introduced during sputtering. The experiments have confirmed that the specific resistivity of the films depends strongly on the deposition rate and reactive gases in the deposition area (**Figure 3**). The ratio of the film-specific resistivity (ρ<sup>v</sup> ) to the target-specific resistivity (ρvm) is a characteristic of the procedure quality: the higher the ratio, the less clean is the procedure. In other words, the specific resistivity of the film depends on the ratio of the quantities of the Mo sputtered (deposited) atoms and interstitials dissolved in the film (**Figure 4**). To obtain ingots free of pores and having a uniform distribution of impurities, a double run is sufficient with a melting rate 0.9–1.0 kg min−1. As a starting material, the rods of commercial purity are used. The samples for the elemental analyses and metallographic studies are cut from the Mo ingot. A composition of trace impurities in the cast Mo under study can be seen in **Table 1**. The macrostructure of cast Mo ingots consists of grains with a length of 40–60 mm and an average diameter of 0.2–3 mm. As substrates for deposition, Si wafers of 76–100 mm in diameter are used, covered with a thermally grown SiO2 of 0.05–0.3 μm thick. Mo films are deposited in a planar-parallel setup with the magnetron sputtering system. Relative to the target in a plane parallel to the target and situated at a fixed distance from it, substrates are linearly moved on which a metal film is deposited. The setup is continuously moving and equipped with gateways for loading and unloading substrates, providing the setup working without breaking a vacuum. In the setup used, the principle of a vacuum lock of the discharge area is used. As the working gas, a purified Ar is used, which is fed through a leak valve into a discharge area connected to a suction volume of diffusion slots for the passage of conveyor substrates. The pressure in the volume to feed airless Ar is less than 5×10−5 Pa and, in the process, less than 2.5×10−2 Pa; a discharge current is up to 15 A at a discharge voltage up to 600 V. The unit has an ability to preheat substrates by infrared lamps. Sputtering target composed of four elements is set out in a cooled holder. On

each element of the target, O-shaped sputter area (erosion) forms, whose length exceeds the width of the deposition area, thus ensuring the reproducibility of the thickness of the deposited layer on substrates with an accuracy of 2% (**Figure 5**). Ar flow during the deposition is

the concentration of impurities introduced in the film less than 10−4 m.%. When depositing the films, it is revealed that the rate of Mo deposition, depending on the process conditions (Ar pressure, voltage, and discharge current) with accuracy of 10%, is a subject obtained by an analysis of the process. The length of the cathode dark space is determined experimentally by measuring a probe potential distribution in the discharge. In the field of real mode dispersion, it is not more than 0.1 cm, which corresponds to estimates by the formula of Child-Langmuir. Furthermore, the parameter *t* = *L/l* ≤ 0.2 is defined, which greatly facilitates the integration of the equation. Dependence *F* for Mo is determined for voltages in the range of 300–500 V. The calculated dependence of the deposition rate in a normalized form concerning the conditions, under which there is no scattering of the sputtered Mo atoms on the Ar atoms, is shown in **Figure 6**. Experimental data are obtained by measuring a thickness of the layers deposited

rounding atmosphere in the discharge area is less than 1×10−5 Pa m3

**Figure 5.** Two magnetron targets: new (a) and (b) after 200 cycles of sputtering.

**Figure 6.** Dependence of deposition rate on Ar pressure: points, experimental data, and curve, calculated data.

s−1. According to approximate estimates, a leakage of gas from the sur-

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

s−1, which corresponds to

79

1 ×10−3 to 2 ×10−2 Pa m<sup>2</sup>

each element of the target, O-shaped sputter area (erosion) forms, whose length exceeds the width of the deposition area, thus ensuring the reproducibility of the thickness of the deposited layer on substrates with an accuracy of 2% (**Figure 5**). Ar flow during the deposition is 1 ×10−3 to 2 ×10−2 Pa m<sup>2</sup> s−1. According to approximate estimates, a leakage of gas from the surrounding atmosphere in the discharge area is less than 1×10−5 Pa m3 s−1, which corresponds to the concentration of impurities introduced in the film less than 10−4 m.%. When depositing the films, it is revealed that the rate of Mo deposition, depending on the process conditions (Ar pressure, voltage, and discharge current) with accuracy of 10%, is a subject obtained by an analysis of the process. The length of the cathode dark space is determined experimentally by measuring a probe potential distribution in the discharge. In the field of real mode dispersion, it is not more than 0.1 cm, which corresponds to estimates by the formula of Child-Langmuir. Furthermore, the parameter *t* = *L/l* ≤ 0.2 is defined, which greatly facilitates the integration of the equation. Dependence *F* for Mo is determined for voltages in the range of 300–500 V. The calculated dependence of the deposition rate in a normalized form concerning the conditions, under which there is no scattering of the sputtered Mo atoms on the Ar atoms, is shown in **Figure 6**. Experimental data are obtained by measuring a thickness of the layers deposited

**Figure 5.** Two magnetron targets: new (a) and (b) after 200 cycles of sputtering.

rods at a melting rate of about 0.5 kg min−1 in a vacuum of 1×10−6 Torr. The power is 250 kW at an accelerating voltage of 25 kV and an emission current of 4 A. Two types of water-cooled copper crystallizers (molds) are used: cylindrical and rectangular. Analysis of the impurity content in Mo targets before sputtering is carried out by means of highly sensitive analytical methods: fast neutron activation, deuteron activation, mass spectrometry with inductively coupled ions, etc. The trace element composition of Mo targets is represented in **Table 1**. Mo films are deposited on Si(100) wafers (10–20 Ω cm) with/without a thin film (about 0.3 μm) of

 at room temperature. Substrates are cleaned chemically prior to load into a magnetron sputter apparatus. The sputtering chamber pressure is 10−6 Torr prior to sputtering; magnetron targets are trained for 40 min in vacuum. During sputtering, the chamber is filled with Ar of high purity to 10−3 Torr. Before sputtering, a heating of Si wafers at 250–300°C is carried out. It has been found that such a procedure is sufficient to produce a clean surface. The deposition rate is practically proportional to the sputtering power at a constant pressure in the sputtering chamber. The resistivity of samples of EB-melted Mo is 5.2–5.6 μΩ cm. The specific resistivity of Mo films 0.15–1.0 μm thick deposited from PM targets under same sputtering conditions is 20–35 μΩ cm. These experiments show that an initial purity of target has a very strong influence on the resistivity of thin Mo films. An effect of a substrate heating on the specific resistivity is also studied. An increased scatter of the resistivity is accounted for by the influence of gaseous impurities adsorbed on the substrate surface. To elucidate the influence of gaseous impurities in the specific resistivity of the Mo films, a sputtering power (a deposition rate) is varied, and an air leakage is introduced during sputtering. The experiments have confirmed that the specific resistivity of the films depends strongly on the deposition rate and reactive gases in the deposition area (**Figure 3**). The ratio of the film-specific resistivity (ρ<sup>v</sup>

to the target-specific resistivity (ρvm) is a characteristic of the procedure quality: the higher the ratio, the less clean is the procedure. In other words, the specific resistivity of the film depends on the ratio of the quantities of the Mo sputtered (deposited) atoms and interstitials dissolved in the film (**Figure 4**). To obtain ingots free of pores and having a uniform distribution of impurities, a double run is sufficient with a melting rate 0.9–1.0 kg min−1. As a starting material, the rods of commercial purity are used. The samples for the elemental analyses and metallographic studies are cut from the Mo ingot. A composition of trace impurities in the cast Mo under study can be seen in **Table 1**. The macrostructure of cast Mo ingots consists of grains with a length of 40–60 mm and an average diameter of 0.2–3 mm. As substrates for deposition, Si wafers of 76–100 mm in diameter are used, covered with a thermally grown

 of 0.05–0.3 μm thick. Mo films are deposited in a planar-parallel setup with the magnetron sputtering system. Relative to the target in a plane parallel to the target and situated at a fixed distance from it, substrates are linearly moved on which a metal film is deposited. The setup is continuously moving and equipped with gateways for loading and unloading substrates, providing the setup working without breaking a vacuum. In the setup used, the principle of a vacuum lock of the discharge area is used. As the working gas, a purified Ar is used, which is fed through a leak valve into a discharge area connected to a suction volume of diffusion slots for the passage of conveyor substrates. The pressure in the volume to feed airless Ar is less than 5×10−5 Pa and, in the process, less than 2.5×10−2 Pa; a discharge current is up to 15 A at a discharge voltage up to 600 V. The unit has an ability to preheat substrates by infrared lamps. Sputtering target composed of four elements is set out in a cooled holder. On

)

SiO2

78 Very-Large-Scale Integration

SiO2

**Figure 6.** Dependence of deposition rate on Ar pressure: points, experimental data, and curve, calculated data.

under different conditions for specified periods of time. The thickness is measured with a precision micro-interferometer with accuracy of 300 Å. To correctly determine the deposition rate, the layers of 1 mm thickness are used.

made with an effective channel of a length *L*ef = 1.2 μm at the channel length *L* = 2.0 μm on the gate. To eliminate the effects of shortening the channel, ion implantation of the channel

High-purity Refractory Metals for Thin Film Metallization of VLSI

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at the voltage of "source-drain" *U*sd = −2 V and the "source-substrate" *U*ss = −2 V are reached on the transistors with gates made of poly-Si and Mo, respectively, at doses of 0.12 and 0.06 a.e. Comparing the current-voltage characteristics shown in **Figure 8** for the transistor of the same geometry, it is revealed that the design efficiency of a poly-Si gate is lower than the structure having a gate made of Mo. This is due to the fact that with increasing doping with B, there is a more severe degradation of mobility in the short channel as well as reducing the slope. Finally, along with the achievement of the resistivity of ~10 μΩ cm of Mo film, which is a very significant for use in IC as an element of their design, the ability has appeared to implement ohmic contacts with Si having a low resistance level, especially in the case of shallow (less than 0.5 μm) transitions. To clarify this possibility and evaluate the stability of the contact, the dependence of the contact resistance on heat treatment conditions is necessary for rapid annealing of surface states. The results (**Figure 9**) show that it remains at 2×10−6 Ω.cm. It is found that the specific resistivity of the contacts depends on

level of ~10−8 A cm−2 is constant at various temperatures and duration of the heat treatment.

ary of Mo-Si. It should be noted that due to the fine-grained structure of Mo film (grain size of about 700 Å), a photoengraving provided receiving patterns of paths and the size of gaps between paths of about 3 μm and besides the restriction is limiting the possibility of obtaining the necessary quality patterns on a photoresist. The uniformity of the structure and the reproducibility of Mo film properties provided highly reproducible results in a large number of plates are confirmed as well. Thus, the studies show real possibilities and

**Figure 8.** Current-voltage characteristics of transistors with the same geometry of gates produced of Mo (1, 3) and of

= 1.0 V

81


at the bound-

by B is made. Measurements show that the magnitudes of the threshold voltage *U*<sup>t</sup>

the temperature of the heat treatment as well as the leakage current of *n*<sup>+</sup>

advantages of using highly pure Mo for obtaining VLSI.

: (1, 2) 4 V, (3, 4) 2 V; ΔSiO2=400 Å; *L*ef=1.2 μm.

poly-Si (2, 4); *U*<sup>g</sup>

Additional studies have confirmed that this is due to the formation of MoSi2

To assess the quality of the deposited Mo films, the dependence of the resistivity is determined based on the Mo films on both the deposition conditions and the current-voltage characteristics of the MOS structure. The resistivity is calculated from the results of surface resistance measurements by four-point probe method and a Mo layer thickness with pre-coating a thin layer of Al (0.01 μm) to eliminate a phase distortion. Furthermore, after obtaining the deposition rate depending on the processing mode (the discharge voltage, current, and Ar pressure), the resistivity is determined from the measured surface resistance and the layer thickness calculated from the processing mode. It is found that the resistivity of Mo films in the thickness range of 0.15–1.0 μm with the deposition rate of higher than 1 nm s−1 changed a little, and its average value is 10 μΩ cm. Preheating the substrate reduces the resistivity to 8.5 μΩ cm, and it begins to depend on a layer thickness. Apparently, this is due to the influence of residual gases adsorbed on a wafer surface. It is interesting to note that when using PM Mo of a commercial purity (grade M−1) as an initial material for the target, a resistivity of the Mo films with a thickness of 0.5 μm cannot drop below 15–20 μΩ cm. To assess the specific applicability of the Mo films, test structures are fabricated on Si wafers with a resistivity of 7.5 Ω cm with orientation. The cross sections of a MOS test structure including the capacitor, element for determining the contact resistance of Mo-Si, and transistor are prepared. One of them (transistor) is shown in **Figure 7**. The fixed charge density in the oxide and fast surface states near Fermi level are determined on the high-frequency and quasi-static capacitance-voltage characteristics of the capacitor, which are, respectively, 5×1010 and 9×1010 cm−2. Shifting the flat-band potential after a thermal treatment at 200°C and the field voltage ±2×10<sup>6</sup> V cm−1 does not exceed 50 mV for 5 min, which indicates the high stability of the obtained structures.

Measurements of the flat-band voltage on structures are made with a change in the dielectric thickness, depending on the allowed, to determine the difference between the work function of the metal semiconductor, Δ*φ*ms, which prove to equal to −0.285±0.015 V. In the case of poly-Si gate, the work function difference is −0.9 V. It is known that a more positive value should significantly improve the current-voltage characteristics of the transistor with a short channel. In order to confirm the feasibility of this assumption, the transistors are

**Figure 7.** Test MOS structure (transistor); 1, SiO2 ; 2, PS glass; 3, Mo; and 4, Mo+Al.

made with an effective channel of a length *L*ef = 1.2 μm at the channel length *L* = 2.0 μm on the gate. To eliminate the effects of shortening the channel, ion implantation of the channel by B is made. Measurements show that the magnitudes of the threshold voltage *U*<sup>t</sup> = 1.0 V at the voltage of "source-drain" *U*sd = −2 V and the "source-substrate" *U*ss = −2 V are reached on the transistors with gates made of poly-Si and Mo, respectively, at doses of 0.12 and 0.06 a.e. Comparing the current-voltage characteristics shown in **Figure 8** for the transistor of the same geometry, it is revealed that the design efficiency of a poly-Si gate is lower than the structure having a gate made of Mo. This is due to the fact that with increasing doping with B, there is a more severe degradation of mobility in the short channel as well as reducing the slope. Finally, along with the achievement of the resistivity of ~10 μΩ cm of Mo film, which is a very significant for use in IC as an element of their design, the ability has appeared to implement ohmic contacts with Si having a low resistance level, especially in the case of shallow (less than 0.5 μm) transitions. To clarify this possibility and evaluate the stability of the contact, the dependence of the contact resistance on heat treatment conditions is necessary for rapid annealing of surface states. The results (**Figure 9**) show that it remains at 2×10−6 Ω.cm. It is found that the specific resistivity of the contacts depends on the temperature of the heat treatment as well as the leakage current of *n*<sup>+</sup> -*p*-transition on the level of ~10−8 A cm−2 is constant at various temperatures and duration of the heat treatment. Additional studies have confirmed that this is due to the formation of MoSi2 at the boundary of Mo-Si. It should be noted that due to the fine-grained structure of Mo film (grain size of about 700 Å), a photoengraving provided receiving patterns of paths and the size of gaps between paths of about 3 μm and besides the restriction is limiting the possibility of obtaining the necessary quality patterns on a photoresist. The uniformity of the structure and the reproducibility of Mo film properties provided highly reproducible results in a large number of plates are confirmed as well. Thus, the studies show real possibilities and advantages of using highly pure Mo for obtaining VLSI.

under different conditions for specified periods of time. The thickness is measured with a precision micro-interferometer with accuracy of 300 Å. To correctly determine the deposition

To assess the quality of the deposited Mo films, the dependence of the resistivity is determined based on the Mo films on both the deposition conditions and the current-voltage characteristics of the MOS structure. The resistivity is calculated from the results of surface resistance measurements by four-point probe method and a Mo layer thickness with pre-coating a thin layer of Al (0.01 μm) to eliminate a phase distortion. Furthermore, after obtaining the deposition rate depending on the processing mode (the discharge voltage, current, and Ar pressure), the resistivity is determined from the measured surface resistance and the layer thickness calculated from the processing mode. It is found that the resistivity of Mo films in the thickness range of 0.15–1.0 μm with the deposition rate of higher than 1 nm s−1 changed a little, and its average value is 10 μΩ cm. Preheating the substrate reduces the resistivity to 8.5 μΩ cm, and it begins to depend on a layer thickness. Apparently, this is due to the influence of residual gases adsorbed on a wafer surface. It is interesting to note that when using PM Mo of a commercial purity (grade M−1) as an initial material for the target, a resistivity of the Mo films with a thickness of 0.5 μm cannot drop below 15–20 μΩ cm. To assess the specific applicability of the Mo films, test structures are fabricated on Si wafers with a resistivity of 7.5 Ω cm with orientation. The cross sections of a MOS test structure including the capacitor, element for determining the contact resistance of Mo-Si, and transistor are prepared. One of them (transistor) is shown in **Figure 7**. The fixed charge density in the oxide and fast surface states near Fermi level are determined on the high-frequency and quasi-static capacitance-voltage characteristics of the capacitor, which are, respectively, 5×1010 and 9×1010 cm−2. Shifting the flat-band poten-

tial after a thermal treatment at 200°C and the field voltage ±2×10<sup>6</sup>

**Figure 7.** Test MOS structure (transistor); 1, SiO2

50 mV for 5 min, which indicates the high stability of the obtained structures.

Measurements of the flat-band voltage on structures are made with a change in the dielectric thickness, depending on the allowed, to determine the difference between the work function of the metal semiconductor, Δ*φ*ms, which prove to equal to −0.285±0.015 V. In the case of poly-Si gate, the work function difference is −0.9 V. It is known that a more positive value should significantly improve the current-voltage characteristics of the transistor with a short channel. In order to confirm the feasibility of this assumption, the transistors are

; 2, PS glass; 3, Mo; and 4, Mo+Al.

V cm−1 does not exceed

rate, the layers of 1 mm thickness are used.

80 Very-Large-Scale Integration

**Figure 8.** Current-voltage characteristics of transistors with the same geometry of gates produced of Mo (1, 3) and of poly-Si (2, 4); *U*<sup>g</sup> : (1, 2) 4 V, (3, 4) 2 V; ΔSiO2=400 Å; *L*ef=1.2 μm.

many different parameters, such as sputtering conditions, a chemical purity of metal components, a design of the sputter setup, and technologies used for the preparation of targets. To the best of our knowledge, no studies have been reported on using of Ti/W composite cast targets for the deposition of TiW barrier layers. In this chapter, scientific and technological results are presented on both the production of high-purity metals by the vacuum-melting technique and deposition of thin TiW layers by sputtering of composite targets [6, 7, 20–22]. When it is necessary to prepare thin films of alloys, targets composed of the cast metal blocks or co-sputtering of several cast metal targets can be used. As a rule all metallic components should be ultrapure, especially with respect to "mobile ions." With increasing miniaturization, the intrinsic radioactivity also exerts harmful effects; therefore, various components should be "free" of U and Th contamination. Gas-forming interstitials (O, N, H, C) are detrimental too. Because of strict requirements to the purity of refractory metals for microelectronics, all undesired impurities should be removed to less than the level of ppm level in order to be able to prepare extremely pure refractory metals or binary alloys based on such pure metals. Hence, considerable effort is necessary in the purification and doping processes. All process steps should be monitored by very sensitive and, generally, very expensive instrumental analytical methods down to a level even of 1 ppb with a special reference to the gas-forming elements which are extremely

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83

*2.5.2. Depositing titanium-tungsten layers by co-sputtering titanium and tungsten targets*

The targets of 78 mm diameter and 6 mm thick are used for magnetron co-sputtering [20, 23]. They are machined from polycrystalline ingots of high-purity W and Ti (the metallurgical procedure #2). W and Ti disks for co-sputtering have the same sizes. The films are deposited by magnetron co-sputtering high-purity Ti and W disks which are fixed in water-cooled copper holders of the magnetron sputter setup. The Ar pressure is maintained automatically. Substrates of Si (10–20 Ω cm, 100 mm diameter) placed on a planar substrate holder are spun freely on their axis with 15 rotations per minute and moving in the circular zone which passes above the sputtering targets at a frequency of 30 rotations per minute. The distance between targets and substrates is 60 mm. A shield between them enables the preliminary training of targets and realization of necessary sputtering conditions. The substrates are cleaned chemically prior to load into the magnetron sputtering apparatus. Prior to the deposition, the apparatus is evacuated to 10−6 Torr; a leakage of gasses into the deposition area is no higher than 10−2 Pa s−1. Before the deposition, the substrates are in situ heated to 250–300°C. A discharge power on each target is up to 2 kW; Ar pressure during a co-sputtering procedure is 10−3 Torr. Based on an assumption that the deposited layer density does not differ from that of a bulk metal, in order to obtain a necessary Ti/W ratio in the film, deposition rates of both metals are determined as a function of the discharge power at Ar pressure of 1 Pa. For that purpose metal films are deposited on thermally oxidized Si substrates at various discharge powers, the energy consumption during these processes being 400–600 kJ. This ensures the layer thickness of 0.5 μm and the possibility of their measurement with sufficient accuracy. Experiments show that the deposition rate of each metal depends linearly on the discharge power. **Figure 10** depicts dependences of mean and instant rates with respect to the thickness

, nm s−1) and dependences of mean and instant deposition rates (γ1

and γ2

, atoms

difficult to determine in metal materials.

(γ1

and γ2

**Figure 9.** Dependence of contact resistivity on the temperature and duration of heat treatment which were necessary for rapid annealing of the surface states; temperature, (1) 450°C, (2) 475°C.

#### **2.5. Depositing titanium-tungsten layers**

#### *2.5.1. Short background*

Multilayer structures have become widely used in silicon VLSI technology to produce thin-film current-conducting systems. Normally, they contain contact layers, barrier layers, and base current-conducting layers. In some cases, barrier layers are simultaneously contact-to-Si layers. The reproducibility of the current-conducting system of silicon VLSI as a whole depends to the high extent on physical and chemical properties of diffusion barrier layers between the Si and Al. Naturally, properties of barrier layers connect with the purity of materials, the solubility of other chemical elements in the multilayer structure during thermal processing, interfaces between layers, and manufacturing techniques used. Chemical impurities dissolved in films should not cause any strong radiation damage during the process of film deposition. Currentconducting systems with Ti barrier layers are characterized by the formation of a TiAl<sup>3</sup> phase at annealing temperatures above 485°C, which leads to consumption of a barrier material. The solubility of Si in TiAl is several times higher than in Al. Therefore, if barrier layers are not sufficiently thick or contain defects, a degradation rate of the Si/Ti/Al or Si/PtSi/Ti/Al contacts may turn out to be unacceptably high. Films of TiW alloy exhibit a better combination of strength and plasticity than Ti, which considerably reduce a probability that vacancies and point puncture-type defects would be formed in films when residual mechanical stresses are high. It is interesting to study, simultaneously with general conditions of a formation of current-conducting systems, a variety of factors affecting properties of the layered current-conducting systems in VLSI structures. It is found that the content of Ti in TiW barrier layers can be varied in the range 12–43 at.% Ti. At the same time, Ti/W targets, sputtered or evaporated for the deposition of TiW barrier layers, contain no less than 30–40 at.% Ti. The correlation between the Ti content in sputter targets and in deposited thin layers is necessary to develop a controllable deposition process. However, such correlation is very difficult to find and achieve because it depends on many different parameters, such as sputtering conditions, a chemical purity of metal components, a design of the sputter setup, and technologies used for the preparation of targets. To the best of our knowledge, no studies have been reported on using of Ti/W composite cast targets for the deposition of TiW barrier layers. In this chapter, scientific and technological results are presented on both the production of high-purity metals by the vacuum-melting technique and deposition of thin TiW layers by sputtering of composite targets [6, 7, 20–22]. When it is necessary to prepare thin films of alloys, targets composed of the cast metal blocks or co-sputtering of several cast metal targets can be used. As a rule all metallic components should be ultrapure, especially with respect to "mobile ions." With increasing miniaturization, the intrinsic radioactivity also exerts harmful effects; therefore, various components should be "free" of U and Th contamination. Gas-forming interstitials (O, N, H, C) are detrimental too. Because of strict requirements to the purity of refractory metals for microelectronics, all undesired impurities should be removed to less than the level of ppm level in order to be able to prepare extremely pure refractory metals or binary alloys based on such pure metals. Hence, considerable effort is necessary in the purification and doping processes. All process steps should be monitored by very sensitive and, generally, very expensive instrumental analytical methods down to a level even of 1 ppb with a special reference to the gas-forming elements which are extremely difficult to determine in metal materials.

#### *2.5.2. Depositing titanium-tungsten layers by co-sputtering titanium and tungsten targets*

**2.5. Depositing titanium-tungsten layers**

rapid annealing of the surface states; temperature, (1) 450°C, (2) 475°C.

Multilayer structures have become widely used in silicon VLSI technology to produce thin-film current-conducting systems. Normally, they contain contact layers, barrier layers, and base current-conducting layers. In some cases, barrier layers are simultaneously contact-to-Si layers. The reproducibility of the current-conducting system of silicon VLSI as a whole depends to the high extent on physical and chemical properties of diffusion barrier layers between the Si and Al. Naturally, properties of barrier layers connect with the purity of materials, the solubility of other chemical elements in the multilayer structure during thermal processing, interfaces between layers, and manufacturing techniques used. Chemical impurities dissolved in films should not cause any strong radiation damage during the process of film deposition. Currentconducting systems with Ti barrier layers are characterized by the formation of a TiAl<sup>3</sup>

**Figure 9.** Dependence of contact resistivity on the temperature and duration of heat treatment which were necessary for

at annealing temperatures above 485°C, which leads to consumption of a barrier material. The solubility of Si in TiAl is several times higher than in Al. Therefore, if barrier layers are not sufficiently thick or contain defects, a degradation rate of the Si/Ti/Al or Si/PtSi/Ti/Al contacts may turn out to be unacceptably high. Films of TiW alloy exhibit a better combination of strength and plasticity than Ti, which considerably reduce a probability that vacancies and point puncture-type defects would be formed in films when residual mechanical stresses are high. It is interesting to study, simultaneously with general conditions of a formation of current-conducting systems, a variety of factors affecting properties of the layered current-conducting systems in VLSI structures. It is found that the content of Ti in TiW barrier layers can be varied in the range 12–43 at.% Ti. At the same time, Ti/W targets, sputtered or evaporated for the deposition of TiW barrier layers, contain no less than 30–40 at.% Ti. The correlation between the Ti content in sputter targets and in deposited thin layers is necessary to develop a controllable deposition process. However, such correlation is very difficult to find and achieve because it depends on

phase

*2.5.1. Short background*

82 Very-Large-Scale Integration

The targets of 78 mm diameter and 6 mm thick are used for magnetron co-sputtering [20, 23]. They are machined from polycrystalline ingots of high-purity W and Ti (the metallurgical procedure #2). W and Ti disks for co-sputtering have the same sizes. The films are deposited by magnetron co-sputtering high-purity Ti and W disks which are fixed in water-cooled copper holders of the magnetron sputter setup. The Ar pressure is maintained automatically. Substrates of Si (10–20 Ω cm, 100 mm diameter) placed on a planar substrate holder are spun freely on their axis with 15 rotations per minute and moving in the circular zone which passes above the sputtering targets at a frequency of 30 rotations per minute. The distance between targets and substrates is 60 mm. A shield between them enables the preliminary training of targets and realization of necessary sputtering conditions. The substrates are cleaned chemically prior to load into the magnetron sputtering apparatus. Prior to the deposition, the apparatus is evacuated to 10−6 Torr; a leakage of gasses into the deposition area is no higher than 10−2 Pa s−1. Before the deposition, the substrates are in situ heated to 250–300°C. A discharge power on each target is up to 2 kW; Ar pressure during a co-sputtering procedure is 10−3 Torr. Based on an assumption that the deposited layer density does not differ from that of a bulk metal, in order to obtain a necessary Ti/W ratio in the film, deposition rates of both metals are determined as a function of the discharge power at Ar pressure of 1 Pa. For that purpose metal films are deposited on thermally oxidized Si substrates at various discharge powers, the energy consumption during these processes being 400–600 kJ. This ensures the layer thickness of 0.5 μm and the possibility of their measurement with sufficient accuracy. Experiments show that the deposition rate of each metal depends linearly on the discharge power. **Figure 10** depicts dependences of mean and instant rates with respect to the thickness (γ1 and γ2 , nm s−1) and dependences of mean and instant deposition rates (γ1 and γ2 , atoms cm<sup>2</sup> ) on the discharge power. Six groups of film samples are prepared which differ from each other by quantities of monoatomic layers of Ti and W and by Ti/W ratios. Quantities of monoatomic layers of each metal in these six film specimens are shown in **Table 3**. Bearing in mind that the 1-mm-thick film area of 1 cm2 contains 5.67×1015 Ti atoms and using experimental data of **Figure 11**, the sputtering discharge power for each target can be determined which is necessary to prepare homogeneous TiW films with definite but different Ti/W ratios. Because Ti layers alternated with W layers in the film structure, some lamination or layering of the film is possible. To escape this, vacuum annealing is done to make the structure of as-deposited films more homogeneous, which is confirmed by X-ray diffraction. The mean grain size of films with different chemical compositions measured by transmission electron microscopy is in the range 10–20 nm. The structure of samples 2 to 4 revealed by X-ray diffraction (**Table 3** and **Figure 11**) is found to be a solid solution of Ti in *bcc* α-W with a lattice parameter from 0.318 to 0.323 nm (by 0.5–2% larger than that for pure W films—*bcc* β-W has a lattice parameter *a* = 0.317 nm). The structure of pure Ti films is *hcp* α-Ti with *a* = 0.295 nm and *c* = 0.447 nm. Such a surprising result is supposed to be a consequence of intermixing of Ti and W atoms with high energies (1–3 eV), the mutual interdiffusion and an overlapping deposition zones during magnetron co-sputtering although the thickness of deposited layers is about 4 nm.

The specific resistivity of TiW thin films depending on the Ti/W ratio is studied using values of the surface resistivity and the film thickness (**Figure 11**). The resistivity of thin films of

pure W and Ti is very near to the tabulated ones for bulk metals. They are shown in **Figure 11** as points *A* for W and *B* for Ti. The coincidence of the resistivity for films and bulk samples can be a characteristic of the quality of the co-sputtering procedure. The resistivity of films is increased gradually as the Ti/W ratio is changed from those for pure W to pure Ti. However, it is worth to mention that the resistivities of quasi-alloy films are always higher than those of pure metals. Such behavior of the resistivity of both pure metals and alloys is well known in physical metallurgy and can be explained by using physical models for a conduction of electrons in solids. From the physical point of view, the Ti/W quasi-alloy consists of two very different metals which have very different physical properties (densities, melting points, etc.) and phase structures (*hcp* and *bcc*). Thus, it is very difficult to make a reliable prediction of the resistivity curve behavior of these films depending on their chemical compositions. Experimental studies of physical characteristics of these quasi-alloys are of a great interest because of the necessity of getting the physical description of the composition, structure, etc. Another experimental fact which is also very surprising is the resistivity of TiW films with a small addition of W, as a dopant (1–4 at.%): the resistivity of a doped Ti became higher than the specific resistivity of pure Ti films. Contrary to this fact, the difference between the resistivities of both pure W films and TiW films with a small addition of Ti as a doping element increases gradually. At the moment there is no a reliable explanation of this interesting fact. Comparing our data with those of Babcock and Tu [22], values of the specific resistivity of thin films deposited by co-sputtering of high-purity cast metal targets are much lower than those of [22]. The discrepancies between the results of these two studies are evidently the consequence of using cast metal targets of higher purity in our study [20] as well as a more advanced deposition procedure. Another result, which is also of some interest, is the

**Figure 11.** Dependence of resistivity of Ti/W films on Ti/W ratio. Points 1–6 [20], points of curve *D* [22]; point *C* for film

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85

deposited from PM target.

**Figure 10.** Mean and instant deposition rates as function of the film thickness.


**Table 3.** Quantities of monoatomic layers of Ti and W in six film samples.

cm<sup>2</sup>

84 Very-Large-Scale Integration

is about 4 nm.

in mind that the 1-mm-thick film area of 1 cm2

**Sample Monoatomic layers**

**Figure 10.** Mean and instant deposition rates as function of the film thickness.

**Table 3.** Quantities of monoatomic layers of Ti and W in six film samples.

) on the discharge power. Six groups of film samples are prepared which differ from each other by quantities of monoatomic layers of Ti and W and by Ti/W ratios. Quantities of monoatomic layers of each metal in these six film specimens are shown in **Table 3**. Bearing

mental data of **Figure 11**, the sputtering discharge power for each target can be determined which is necessary to prepare homogeneous TiW films with definite but different Ti/W ratios. Because Ti layers alternated with W layers in the film structure, some lamination or layering of the film is possible. To escape this, vacuum annealing is done to make the structure of as-deposited films more homogeneous, which is confirmed by X-ray diffraction. The mean grain size of films with different chemical compositions measured by transmission electron microscopy is in the range 10–20 nm. The structure of samples 2 to 4 revealed by X-ray diffraction (**Table 3** and **Figure 11**) is found to be a solid solution of Ti in *bcc* α-W with a lattice parameter from 0.318 to 0.323 nm (by 0.5–2% larger than that for pure W films—*bcc* β-W has a lattice parameter *a* = 0.317 nm). The structure of pure Ti films is *hcp* α-Ti with *a* = 0.295 nm and *c* = 0.447 nm. Such a surprising result is supposed to be a consequence of intermixing of Ti and W atoms with high energies (1–3 eV), the mutual interdiffusion and an overlapping deposition zones during magnetron co-sputtering although the thickness of deposited layers

The specific resistivity of TiW thin films depending on the Ti/W ratio is studied using values of the surface resistivity and the film thickness (**Figure 11**). The resistivity of thin films of

1 1.4 13.8 2 5.0 13.8 3 12.0 14.0 4 11.0 5.5 5 11.0 3.0 6 14.4 1.0

contains 5.67×1015 Ti atoms and using experi-

**Ti W**

**Figure 11.** Dependence of resistivity of Ti/W films on Ti/W ratio. Points 1–6 [20], points of curve *D* [22]; point *C* for film deposited from PM target.

pure W and Ti is very near to the tabulated ones for bulk metals. They are shown in **Figure 11** as points *A* for W and *B* for Ti. The coincidence of the resistivity for films and bulk samples can be a characteristic of the quality of the co-sputtering procedure. The resistivity of films is increased gradually as the Ti/W ratio is changed from those for pure W to pure Ti. However, it is worth to mention that the resistivities of quasi-alloy films are always higher than those of pure metals. Such behavior of the resistivity of both pure metals and alloys is well known in physical metallurgy and can be explained by using physical models for a conduction of electrons in solids. From the physical point of view, the Ti/W quasi-alloy consists of two very different metals which have very different physical properties (densities, melting points, etc.) and phase structures (*hcp* and *bcc*). Thus, it is very difficult to make a reliable prediction of the resistivity curve behavior of these films depending on their chemical compositions. Experimental studies of physical characteristics of these quasi-alloys are of a great interest because of the necessity of getting the physical description of the composition, structure, etc. Another experimental fact which is also very surprising is the resistivity of TiW films with a small addition of W, as a dopant (1–4 at.%): the resistivity of a doped Ti became higher than the specific resistivity of pure Ti films. Contrary to this fact, the difference between the resistivities of both pure W films and TiW films with a small addition of Ti as a doping element increases gradually. At the moment there is no a reliable explanation of this interesting fact. Comparing our data with those of Babcock and Tu [22], values of the specific resistivity of thin films deposited by co-sputtering of high-purity cast metal targets are much lower than those of [22]. The discrepancies between the results of these two studies are evidently the consequence of using cast metal targets of higher purity in our study [20] as well as a more advanced deposition procedure. Another result, which is also of some interest, is the difference between the resistivity of films deposited from two kinds of sputtering targets: cast metal targets and PM Ti/W powder targets. By sputtering of targets compacted from highpurity Ti and W powders with W content of 25 at.% by PM techniques, vacuum-annealed films have the specific resistivity of 130 μΩ cm (Point *C*, **Figure 11**). Auger spectrometry of films which are obtained by magnetron sputtering of PM targets shows the presence of high contents of C and O, 5 and 4 at.%, respectively. In layers obtained by co-sputtering of cast metal targets, C and O contents are lower than 1 at.%.

or thermal painting. During measurements of mechanical stresses, the heating of all samples is carried out in the same way. The thickness of TiW films is 0.18 μm with accuracy of 0.02 μm. The sheet resistance is 3.5–4.5 Ω/□; the specific resistivity of TiW films is 65–72 μΩ cm. The samples are analyzed by four-point probe sheet resistance measurements, scanning electron microscopy, Auger electron spectroscopy, X-ray diffraction, X-ray electron probe spectroscopy, and laser ellipsometry, enabling an evaluation of residual mechanical stresses in films to be made with error of 2%. The leakage currents and Schottky barrier heights are registered with accuracy of 0.5 and 0.1% over the measurement range, respectively. XRD data show that TiW films are solid solutions of Ti in a W matrix with increased W lattice parameters. A relative increase in the W lattice parameter depends on a quality of surface conditions (polished or unpolished) of Si substrates on which films are deposited (**Figure 13**). The relative increase in the W lattice parameter for a polished surface was δ*d*/*d*0 = 7×10−3, while for an unpolished surface, it is δ*d*/*d*0 = 2×10−3. Here *d*0 is the lattice parameter of W (from ASTM tables). This difference is mainly due to the action of residual mechanical stresses in films. Measurements

of a curvature of Si substrates with WTi films show that bending radii were *R*l*<sup>b</sup>*

sublayer. Mechanical stresses of specimens with/without SiO2

of TiW films on the polished Si substrate with (*b*) and without (*a*) the thermal SiO2

with a microstructure of TiW films. Mean grain sizes of TiW films are 35 and 45 nm for sam-

The bending displacement is reciprocally related to the bending radius of the substrates, and so it can be supposed that mechanical stresses in films deposited on unpolished substrates are lower than those in films deposited on polished substrates. This correlates with values of relative deviations of the lattice parameter for unpolished and polished substrates (δ*d*/*d*0 = 2×10−3 and 7×10−3, respectively). The absolute value of the bending displacement can be used to estimate resulting mechanical stresses in the sample. Values of bending radii for samples with-

polished Si substrates. These results confirm the observations of the dependence of mechanical stresses in thin layers on properties of the material and its crystallographic microstructure.

TiW films. As a result, there is a more spontaneous formation of nuclei, faster unity, and higher resulting stresses localized on grain boundaries. The influence of sublayers on the layer

**Figure 13.** Scanning electron micrographs of the surface morphology of samples with structure Si/TiW (polished Si

= 64.5 m for polished Si substrates with/without a thermal SiO2

sublayers are higher than for samples with SiO2

/TiW (b) (×100,000).

' = 69.0 m and *R*2*<sup>b</sup>*

*R*2*b*

Bending radii are *R*1*<sup>b</sup>*

ples with/without SiO2

It can also be supposed that SiO2

substrate) (a) and Si/SiO2

thermal SiO2

out SiO2

= 47.0 m and

87

sublayer.

sublayer correlate

sublayer on the Si surface.

sublayers on both unpolished and

' = 103.0 m for unpolished Si substrates with/without

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sublayers change conditions of nucleation and growth of

sublayer, respectively. **Figure 13** shows microstructures of surfaces

### *2.5.3. Composite titanium-tungsten targets for deposing barrier layers*

Metallurgical technologies to produce of Ti/W targets are selected according to procedure #1 [24]. Multiple EB vacuum melting of compacted Ti blanks is used, as well as cold/warm/hot rolling, cutting, drilling, pressing, etching, polishing, etc. By this procedure, cast Ti polycrystalline disks of 190 mm in diameter and 23 mm thick are prepared. For this purpose, Ti rods produced by iodide process are preliminary carefully purified by EB floating zone vacuum melting and then remelted by EB vacuum melting in specially designed water-cooled copper molds. At the same time, highly pure W single-crystalline rods of 11 mm in diameter and 350 mm length are purified by EB floating zone vacuum melting. Composite cast Ti/W targets consisted of Ti disks with W cylindrical attachments, arranged in such way that the ratio between the areas of Ti and W sections on sputtered targets surface corresponds to the necessary Ti/W ratio in deposited films (**Figure 12**). TiW films are deposited by sputtering composite Ti/W, contained 40 at% of Ti, in a sputter deposition system with d.c. power of 2.4–3.2 kW. Leakage currents are measured at a reverse bias voltage of 15 V. The current density during sputtering is about 0.1 A cm−2. The sputtering yields of Ti and W are the same; however, they are chosen to obtain the necessary Ti/W ratio during the whole sputtering procedure. The deposition rate is about 1.8 nm s−1. Films are deposited on *n*-Si(111) substrates (100 mm in diameter) preheated in vacuum by IR lamps to 250°C with accuracy of 5°C. Test Schottky diodes with both *n*-Si/PtSi/TiW/Al and *n*-Si/PtSi/Mo/Al structures are formed by standard techniques. These techniques consist of (*a*) deposition of thin Pt layers by cathode sputtering on Si substrates through contact windows of 10 μm × 15 μm which are formed in a surface thermal SiO2 layer, (*b*) annealing of the PtSi structure and removal of the unreacted Pt, (*c*) magnetron sputtering of TiW or Mo, and (*d*) deposition of the upper Al layer by d.c. magnetron sputtering of A1-1 at.% Si target. Photolithography and etching are used to obtain contact windows. The structures are annealed in a nitrogen atmosphere at 450°C for different times, but not more than 3 h. The temperature of Si substrates is measured indirectly by a calibration

**Figure 12.** Composite sputter Ti/W targets (left, new; right, after 150 cycles).

or thermal painting. During measurements of mechanical stresses, the heating of all samples is carried out in the same way. The thickness of TiW films is 0.18 μm with accuracy of 0.02 μm. The sheet resistance is 3.5–4.5 Ω/□; the specific resistivity of TiW films is 65–72 μΩ cm. The samples are analyzed by four-point probe sheet resistance measurements, scanning electron microscopy, Auger electron spectroscopy, X-ray diffraction, X-ray electron probe spectroscopy, and laser ellipsometry, enabling an evaluation of residual mechanical stresses in films to be made with error of 2%. The leakage currents and Schottky barrier heights are registered with accuracy of 0.5 and 0.1% over the measurement range, respectively. XRD data show that TiW films are solid solutions of Ti in a W matrix with increased W lattice parameters. A relative increase in the W lattice parameter depends on a quality of surface conditions (polished or unpolished) of Si substrates on which films are deposited (**Figure 13**). The relative increase in the W lattice parameter for a polished surface was δ*d*/*d*0 = 7×10−3, while for an unpolished surface, it is δ*d*/*d*0 = 2×10−3. Here *d*0 is the lattice parameter of W (from ASTM tables). This difference is mainly due to the action of residual mechanical stresses in films. Measurements of a curvature of Si substrates with WTi films show that bending radii were *R*l*<sup>b</sup>* = 47.0 m and *R*2*b* = 64.5 m for polished Si substrates with/without a thermal SiO2 sublayer on the Si surface. Bending radii are *R*1*<sup>b</sup>* ' = 69.0 m and *R*2*<sup>b</sup>* ' = 103.0 m for unpolished Si substrates with/without thermal SiO2 sublayer. Mechanical stresses of specimens with/without SiO2 sublayer correlate with a microstructure of TiW films. Mean grain sizes of TiW films are 35 and 45 nm for samples with/without SiO2 sublayer, respectively. **Figure 13** shows microstructures of surfaces of TiW films on the polished Si substrate with (*b*) and without (*a*) the thermal SiO2 sublayer.

difference between the resistivity of films deposited from two kinds of sputtering targets: cast metal targets and PM Ti/W powder targets. By sputtering of targets compacted from highpurity Ti and W powders with W content of 25 at.% by PM techniques, vacuum-annealed films have the specific resistivity of 130 μΩ cm (Point *C*, **Figure 11**). Auger spectrometry of films which are obtained by magnetron sputtering of PM targets shows the presence of high contents of C and O, 5 and 4 at.%, respectively. In layers obtained by co-sputtering of cast

Metallurgical technologies to produce of Ti/W targets are selected according to procedure #1 [24]. Multiple EB vacuum melting of compacted Ti blanks is used, as well as cold/warm/hot rolling, cutting, drilling, pressing, etching, polishing, etc. By this procedure, cast Ti polycrystalline disks of 190 mm in diameter and 23 mm thick are prepared. For this purpose, Ti rods produced by iodide process are preliminary carefully purified by EB floating zone vacuum melting and then remelted by EB vacuum melting in specially designed water-cooled copper molds. At the same time, highly pure W single-crystalline rods of 11 mm in diameter and 350 mm length are purified by EB floating zone vacuum melting. Composite cast Ti/W targets consisted of Ti disks with W cylindrical attachments, arranged in such way that the ratio between the areas of Ti and W sections on sputtered targets surface corresponds to the necessary Ti/W ratio in deposited films (**Figure 12**). TiW films are deposited by sputtering composite Ti/W, contained 40 at% of Ti, in a sputter deposition system with d.c. power of 2.4–3.2 kW. Leakage currents are measured at a reverse bias voltage of 15 V. The current density during sputtering is about 0.1 A cm−2. The sputtering yields of Ti and W are the same; however, they are chosen to obtain the necessary Ti/W ratio during the whole sputtering procedure. The deposition rate is about 1.8 nm s−1. Films are deposited on *n*-Si(111) substrates (100 mm in diameter) preheated in vacuum by IR lamps to 250°C with accuracy of 5°C. Test Schottky diodes with both *n*-Si/PtSi/TiW/Al and *n*-Si/PtSi/Mo/Al structures are formed by standard techniques. These techniques consist of (*a*) deposition of thin Pt layers by cathode sputtering on Si substrates through contact windows of 10 μm × 15 μm which are formed in a surface

layer, (*b*) annealing of the PtSi structure and removal of the unreacted Pt, (*c*)

magnetron sputtering of TiW or Mo, and (*d*) deposition of the upper Al layer by d.c. magnetron sputtering of A1-1 at.% Si target. Photolithography and etching are used to obtain contact windows. The structures are annealed in a nitrogen atmosphere at 450°C for different times, but not more than 3 h. The temperature of Si substrates is measured indirectly by a calibration

metal targets, C and O contents are lower than 1 at.%.

thermal SiO2

86 Very-Large-Scale Integration

*2.5.3. Composite titanium-tungsten targets for deposing barrier layers*

**Figure 12.** Composite sputter Ti/W targets (left, new; right, after 150 cycles).

The bending displacement is reciprocally related to the bending radius of the substrates, and so it can be supposed that mechanical stresses in films deposited on unpolished substrates are lower than those in films deposited on polished substrates. This correlates with values of relative deviations of the lattice parameter for unpolished and polished substrates (δ*d*/*d*0 = 2×10−3 and 7×10−3, respectively). The absolute value of the bending displacement can be used to estimate resulting mechanical stresses in the sample. Values of bending radii for samples without SiO2 sublayers are higher than for samples with SiO2 sublayers on both unpolished and polished Si substrates. These results confirm the observations of the dependence of mechanical stresses in thin layers on properties of the material and its crystallographic microstructure. It can also be supposed that SiO2 sublayers change conditions of nucleation and growth of TiW films. As a result, there is a more spontaneous formation of nuclei, faster unity, and higher resulting stresses localized on grain boundaries. The influence of sublayers on the layer

**Figure 13.** Scanning electron micrographs of the surface morphology of samples with structure Si/TiW (polished Si substrate) (a) and Si/SiO2 /TiW (b) (×100,000).

microstructure is confirmed by experiments in which Al layers are deposited onto both Si substrates and Si substrates with TiW film. The influence of a sublayer material on the film microstructure is studied on Al layers, prepared by magnetron sputtering of Al targets doped with Si (1 at.%), onto Si substrates with/without TiW sublayer. **Figure 14** shows a microrelief of Al films deposited on Si substrates without (*a*) and with (*b*) the TiW sublayer. The microstructure of the Al film in the Si/Al structure is rather smooth, and the Al film consists of coarse grains with a mean grain size of 1.1–1.3 μm. The mean grain size of Al films in the Si/TiW/Al structure is lower (about 0.3 μm) than in the Si/Al structure. TiW films, deposited by magnetron sputtering of composite cast TiW targets, contained approximately 40 at.% Ti, with a remainder W. Because TiW films serve simultaneously as current-conducting and barrier layers, sputtering targets should have a relatively high W content, together with the necessary Ti/W ratio for both optimal barrier properties and lower electric resistivity of TiW films. For effective barrier properties, it is preferable to have the Ti content in a range 30–40 at.% Ti in TiW thin films.

of thin films, although it is well known that interstitials, even at low concentrations, form very stable fine chemical compounds like refractory metal carbides, oxides, nitrides, etc., which precipitate on boundaries in thin metal films and can serve as boundary diffusion stoppers. On the other hand, the lack of discontinuities on the curve for C at an etching time of 50 min, e.g., near the Si/TiW interface, confirms both the effectiveness of the preparation of Si substrate surfaces before deposition and the sufficient cleanliness of sputter and deposition processes, at least at initial stages. A slight monotonic decrease in the Ti content near the Si/TiW interface is probably connected with an increase in the W content near the interface. It may also be a result of the nucleation of TiW films, which is preferable for W atoms because TiW films are based on the W lattice. It may also be associated with the fact that the coefficient of a W self-diffusion is much higher than the coefficient of a Ti self-diffusion

**Figure 15.** Auger electron spectra of samples with structure Si/TiW: (a) Auger electron spectra of samples with structure

Si/TiW before (a) and after (b) isothermal annealing at 510°C for 1 h.

on a nucleation front during the film growth, as well as more frequent collisions of W atoms with a nuclei, and hence a higher probability of their accumulation on the nuclei. As can be seen from **Figure 15(a)**, W and Ti are homogeneously distributed throughout the film depth, which is probably a consequence of their interdiffusion. Near Si/TiW interface, there is a rather extended silicide layer, as can be seen from a monotonic change in the Si curve. Some localization of C near Si/TiW interface can be related to the differences in a C limited solubility and a C diffusion coefficient between the initial TiW film and the transition silicide layer

on the fast O diffusion, compared with the self-diffusion of components of TiW alloy, and

solution, it is possible that Ti may display deoxidizing abilities and react with the Si recov-

This supposition is in agreement with a monotonic change in the Si curve which correlates with a similar O curve. A temperature effect results in the depth redistribution of chemical components and impurities of TiW film. **Figure 15(b)** shows the Auger profiles for the depth distribution of elements in TiW films, isothermally annealed at 510°C in vacuum for 1 h. The W and Ti are homogeneously distributed throughout the film depth which is probably a consequence of the interdiffusion. At the Si/TiW interface, there is a rather extended silicide layer as can be seen from a monotonic change of the curve for Si. An increase in the C content

the high O solubility in W and Ti as well as in their silicides. If no Tix

s−1, respectively). This may promote an easier motion of W atoms

High-purity Refractory Metals for Thin Film Metallization of VLSI

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89

/TiW interface. The considerable O content in TiW layer is dependent

. In this case, a nonstoichiometric Ti silicide phase should be formed, because

Wy

phase is not observed at such low temperatures.

is present in a solid

(1.88×10−8 and 6.4×10−8 cm<sup>2</sup>

detected near the SiO2

the formation of the stoichiometric TiSi2

ered from SiO2

As shown earlier, the specific resistivity of TiW films increases with decreasing the W content to 98 at.%: the specific resistivity for this alloy is approximately 2.5 times higher than that for pure Ti films. The difference in the specific resistivity in the range of 30–40 at.% Ti is not large: 60–70 μΩ cm. To meet the requirements of the composite target design, the Ti content of 40 at.% is chosen. An excellent correlation between Ti/W ratios of targets and of films during the whole lifetime of sputtering targets is found, despite the fact that sizes of the erosion area changed significantly. The contents of the Ti and W components in the films vary slightly after 130–150 sputtering cycles. The relative deviation of the Ti content from the standard one during the target lifetime does not exceed 2 rel.%. Our AES studies of TiW films have revealed low concentrations of interstitials, such as O, C, and P. Auger profiling data of unannealed specimens are shown in **Figure 15(a)**. A typical result for these films is a sharp decrease of O and C contents during the etching process and a deepening of the analyzing zone. The behavior of O and C is very similar, and their curves partially overlap. Mechanical properties and microstructure of TiW layers also depend on the content of gasforming interstitials, e.g., O, C, and H, even when they are present in very small quantities. It is unclear how strong the influence of a low content of interstitials is on physical properties

**Figure 14.** Scanning micrographs of the structure morphology of samples with structures Si/Al (a) and Si/TiW/Al (b) ×100,000.

microstructure is confirmed by experiments in which Al layers are deposited onto both Si substrates and Si substrates with TiW film. The influence of a sublayer material on the film microstructure is studied on Al layers, prepared by magnetron sputtering of Al targets doped with Si (1 at.%), onto Si substrates with/without TiW sublayer. **Figure 14** shows a microrelief of Al films deposited on Si substrates without (*a*) and with (*b*) the TiW sublayer. The microstructure of the Al film in the Si/Al structure is rather smooth, and the Al film consists of coarse grains with a mean grain size of 1.1–1.3 μm. The mean grain size of Al films in the Si/TiW/Al structure is lower (about 0.3 μm) than in the Si/Al structure. TiW films, deposited by magnetron sputtering of composite cast TiW targets, contained approximately 40 at.% Ti, with a remainder W. Because TiW films serve simultaneously as current-conducting and barrier layers, sputtering targets should have a relatively high W content, together with the necessary Ti/W ratio for both optimal barrier properties and lower electric resistivity of TiW films. For effective barrier properties, it is preferable to have the Ti content in a range 30–40 at.% Ti in TiW thin films.

As shown earlier, the specific resistivity of TiW films increases with decreasing the W content to 98 at.%: the specific resistivity for this alloy is approximately 2.5 times higher than that for pure Ti films. The difference in the specific resistivity in the range of 30–40 at.% Ti is not large: 60–70 μΩ cm. To meet the requirements of the composite target design, the Ti content of 40 at.% is chosen. An excellent correlation between Ti/W ratios of targets and of films during the whole lifetime of sputtering targets is found, despite the fact that sizes of the erosion area changed significantly. The contents of the Ti and W components in the films vary slightly after 130–150 sputtering cycles. The relative deviation of the Ti content from the standard one during the target lifetime does not exceed 2 rel.%. Our AES studies of TiW films have revealed low concentrations of interstitials, such as O, C, and P. Auger profiling data of unannealed specimens are shown in **Figure 15(a)**. A typical result for these films is a sharp decrease of O and C contents during the etching process and a deepening of the analyzing zone. The behavior of O and C is very similar, and their curves partially overlap. Mechanical properties and microstructure of TiW layers also depend on the content of gasforming interstitials, e.g., O, C, and H, even when they are present in very small quantities. It is unclear how strong the influence of a low content of interstitials is on physical properties

**Figure 14.** Scanning micrographs of the structure morphology of samples with structures Si/Al (a) and Si/TiW/Al

(b) ×100,000.

88 Very-Large-Scale Integration

**Figure 15.** Auger electron spectra of samples with structure Si/TiW: (a) Auger electron spectra of samples with structure Si/TiW before (a) and after (b) isothermal annealing at 510°C for 1 h.

of thin films, although it is well known that interstitials, even at low concentrations, form very stable fine chemical compounds like refractory metal carbides, oxides, nitrides, etc., which precipitate on boundaries in thin metal films and can serve as boundary diffusion stoppers. On the other hand, the lack of discontinuities on the curve for C at an etching time of 50 min, e.g., near the Si/TiW interface, confirms both the effectiveness of the preparation of Si substrate surfaces before deposition and the sufficient cleanliness of sputter and deposition processes, at least at initial stages. A slight monotonic decrease in the Ti content near the Si/TiW interface is probably connected with an increase in the W content near the interface. It may also be a result of the nucleation of TiW films, which is preferable for W atoms because TiW films are based on the W lattice. It may also be associated with the fact that the coefficient of a W self-diffusion is much higher than the coefficient of a Ti self-diffusion (1.88×10−8 and 6.4×10−8 cm<sup>2</sup> s−1, respectively). This may promote an easier motion of W atoms on a nucleation front during the film growth, as well as more frequent collisions of W atoms with a nuclei, and hence a higher probability of their accumulation on the nuclei. As can be seen from **Figure 15(a)**, W and Ti are homogeneously distributed throughout the film depth, which is probably a consequence of their interdiffusion. Near Si/TiW interface, there is a rather extended silicide layer, as can be seen from a monotonic change in the Si curve. Some localization of C near Si/TiW interface can be related to the differences in a C limited solubility and a C diffusion coefficient between the initial TiW film and the transition silicide layer detected near the SiO2 /TiW interface. The considerable O content in TiW layer is dependent on the fast O diffusion, compared with the self-diffusion of components of TiW alloy, and the high O solubility in W and Ti as well as in their silicides. If no Tix Wy is present in a solid solution, it is possible that Ti may display deoxidizing abilities and react with the Si recovered from SiO2 . In this case, a nonstoichiometric Ti silicide phase should be formed, because the formation of the stoichiometric TiSi2 phase is not observed at such low temperatures. This supposition is in agreement with a monotonic change in the Si curve which correlates with a similar O curve. A temperature effect results in the depth redistribution of chemical components and impurities of TiW film. **Figure 15(b)** shows the Auger profiles for the depth distribution of elements in TiW films, isothermally annealed at 510°C in vacuum for 1 h. The W and Ti are homogeneously distributed throughout the film depth which is probably a consequence of the interdiffusion. At the Si/TiW interface, there is a rather extended silicide layer as can be seen from a monotonic change of the curve for Si. An increase in the C content at Si/TiW interface can be related to differences in the C limited solubility and the C diffusion coefficient between initial TiW film and the transition silicide layer.

layers, obtained at an increased sputtering power, is partly due to a higher dispersion of the microstructure. Schottky diodes with TiW films exhibit a higher level of leakage currents than diodes with Mo films, although in both cases leakage currents are not an obstacle to the commercial use of these highly pure refractory metals as Schottky diode barrier layers. On the other hand, a great advantage of Schottky diodes with the Si/PtSi/TiW/Al structure is a rather

the mean value for structures with TiW layers is no higher than 0.1 V during thermal testing at 450°C for 3 h in nitrogen (**Figure 17**, curves 1 and 2). At the same time, the maximum deviation

Refractory metal silicides have a large potential as materials for the low-resistance contacts, gate electrodes, and interconnections in microelectronic devices [24, 25]. One of the wellknown techniques for preparation of silicide layers involves a laser co-evaporation and magnetron co-sputtering of pure metal films onto a surface of a Si substrate with a subsequent high-temperature annealing. Another is magnetron sputtering or laser evaporation of silicide targets produced by PM or vacuum melting/casting. Casting of silicide ingots of commercial sizes is a well-known metallurgical problem because all refractory metal silicides are very brittle and hard in mechanical working. The optimal method is production of composite cast refractory metal silicide targets (cast silicide pieces are attached to copper bases by ultrasonic soldering). Vacuum melting and casting refractory metal silicides for targets solve the two main problems of thin-film deposition, i.e., desired chemical composition and high purity of

magnetron sputter because it is necessary to use two vacuum techniques—vacuum HF levita-

composite, cast silicide targets of 152 mm in diameter are produced. Our study has revealed

Other refractory metal silicides are produced in a similar way. Three experimental series are conducted to obtain silicide films: (1) laser evaporation of cast silicide targets, (2) magnetron sputtering cast silicide targets, and (3) magnetron co-sputtering of metal and Si targets. Initial materials for silicide sintering are 5N-purity Si and high-purity refractory metals (**Table 1**). Homogeneous mixtures of high-purity Si and refractory metal are prepared and isostatically pressed. Then mixture samples are sintered in a vacuum at 1100°C for 3 h. PM sintered samples are melted by vacuum HF levitation and cast in copper molds. The levitation melting consists of suspending a solid sample in HF electromagnetic field and melting it by the induced electrical currents. The resulting 25 g liquid drops have a form of the sphere. To solidify a liquid drop, it is enough to switch off an electric power. During laser ablation, the 10×15×5

 cast targets are evaporated with a solid-state Nd-laser of 1.06 μm wavelength, 0.8 J pulse energy, and 10–20 Hz pulse frequency [26]. The laser beam spot is 2–3 mm in diameter.

from the mean value for structures with Mo layers is twice as high after a thermal testing

). A maximum deviation of *U*<sup>0</sup>

http://dx.doi.org/10.5772/intechopen.69126

High-purity Refractory Metals for Thin Film Metallization of VLSI

targets for the laser ablation or

targets used in this study [26] for laser

and are chemically homogeneous. For magnetron sputtering

films by both the laser evaporation and magnetron sputtering.

from

91

high thermal stability of a direct breakdown potential *U*<sup>0</sup>

**2.6. Depositing films of refractory metal silicides for barrier layers**

thin films. The most problematic is a production of cast WSi2

tion and EB float zone melting. Rectangular cast WSi2

ablation have a volume of 1.5 cm<sup>3</sup>

possibilities of depositing WSi2

mm3

at 450°C for 1 h in nitrogen (**Figure 17**, curve 3).

*2.6.1. Depositing films of refractory metal disilicides*

of *U*<sup>0</sup>

TiW films with a junction depth of 0.18 μm are tested as barrier layers on diodes with a square shape (10 μm × 15 μm). Schottky barrier heights on *n*-Si are determined from the current *vs*. applied voltage measurements. TiW layers form a relatively low Schottky barrier contacts to *n*-type Si (no higher than 0.5–0.6 eV). Curves 1 and 2 in **Figure 16** show the dependence of leakage currents on the testing time at 450°C in nitrogen. For comparison, barrier layers of Mo are also tested (**Figure 16**, curve 3). The measurements of the direct breakdown potential (*U*<sup>0</sup> ) for structures with TiW layers have revealed their high thermal stability after testing at 450°C for 3 h in nitrogen. A similar testing of structures with Mo layers shows that they are of a lower stability than structures with TiW layers (**Figure 16**, curve 3). Our experimental data on the testing of TiW barrier layers are associated with both the microstructure and morphology of Si-Me interface in contact with barrier layers of TiW or Mo. It is worth noting that leakage currents can be lowered by optimizing the technological procedures, for example, by a choice of a sputtering power (**Figure 17**). A higher quality of contacts with TiW barrier

**Figure 16.** Leakage currents of samples with Schottky barrier diode structures *n*-Si/PtSi/TiW/AI and *n*-Si/PtSi/Mo/Al tested at 450°C in nitrogen: (1, 2) TiW films deposited at sputter deposition powers of 2.4 and 3.2 kW, respectively; (3) Mo film.

**Figure 17.** Direct breakdown voltages of samples with Schottky barrier diode structures at a current of 300 pA: (1, 2) structure *n*-Si/PtSi/TiW/Al (sputter deposition powers of 2.4 and 3.2 kW, respectively); (3) structure *n*-Si/PtSi/Mo/Al.

layers, obtained at an increased sputtering power, is partly due to a higher dispersion of the microstructure. Schottky diodes with TiW films exhibit a higher level of leakage currents than diodes with Mo films, although in both cases leakage currents are not an obstacle to the commercial use of these highly pure refractory metals as Schottky diode barrier layers. On the other hand, a great advantage of Schottky diodes with the Si/PtSi/TiW/Al structure is a rather high thermal stability of a direct breakdown potential *U*<sup>0</sup> ). A maximum deviation of *U*<sup>0</sup> from the mean value for structures with TiW layers is no higher than 0.1 V during thermal testing at 450°C for 3 h in nitrogen (**Figure 17**, curves 1 and 2). At the same time, the maximum deviation of *U*<sup>0</sup> from the mean value for structures with Mo layers is twice as high after a thermal testing at 450°C for 1 h in nitrogen (**Figure 17**, curve 3).

#### **2.6. Depositing films of refractory metal silicides for barrier layers**

#### *2.6.1. Depositing films of refractory metal disilicides*

at Si/TiW interface can be related to differences in the C limited solubility and the C diffusion

TiW films with a junction depth of 0.18 μm are tested as barrier layers on diodes with a square shape (10 μm × 15 μm). Schottky barrier heights on *n*-Si are determined from the current *vs*. applied voltage measurements. TiW layers form a relatively low Schottky barrier contacts to *n*-type Si (no higher than 0.5–0.6 eV). Curves 1 and 2 in **Figure 16** show the dependence of leakage currents on the testing time at 450°C in nitrogen. For comparison, barrier layers of Mo are also tested (**Figure 16**, curve 3). The measurements of the direct breakdown potential

) for structures with TiW layers have revealed their high thermal stability after testing at 450°C for 3 h in nitrogen. A similar testing of structures with Mo layers shows that they are of a lower stability than structures with TiW layers (**Figure 16**, curve 3). Our experimental data on the testing of TiW barrier layers are associated with both the microstructure and morphology of Si-Me interface in contact with barrier layers of TiW or Mo. It is worth noting that leakage currents can be lowered by optimizing the technological procedures, for example, by a choice of a sputtering power (**Figure 17**). A higher quality of contacts with TiW barrier

**Figure 17.** Direct breakdown voltages of samples with Schottky barrier diode structures at a current of 300 pA: (1, 2) structure *n*-Si/PtSi/TiW/Al (sputter deposition powers of 2.4 and 3.2 kW, respectively); (3) structure *n*-Si/PtSi/Mo/Al.

**Figure 16.** Leakage currents of samples with Schottky barrier diode structures *n*-Si/PtSi/TiW/AI and *n*-Si/PtSi/Mo/Al tested at 450°C in nitrogen: (1, 2) TiW films deposited at sputter deposition powers of 2.4 and 3.2 kW, respectively; (3)

coefficient between initial TiW film and the transition silicide layer.

(*U*<sup>0</sup>

90 Very-Large-Scale Integration

Mo film.

Refractory metal silicides have a large potential as materials for the low-resistance contacts, gate electrodes, and interconnections in microelectronic devices [24, 25]. One of the wellknown techniques for preparation of silicide layers involves a laser co-evaporation and magnetron co-sputtering of pure metal films onto a surface of a Si substrate with a subsequent high-temperature annealing. Another is magnetron sputtering or laser evaporation of silicide targets produced by PM or vacuum melting/casting. Casting of silicide ingots of commercial sizes is a well-known metallurgical problem because all refractory metal silicides are very brittle and hard in mechanical working. The optimal method is production of composite cast refractory metal silicide targets (cast silicide pieces are attached to copper bases by ultrasonic soldering). Vacuum melting and casting refractory metal silicides for targets solve the two main problems of thin-film deposition, i.e., desired chemical composition and high purity of thin films. The most problematic is a production of cast WSi2 targets for the laser ablation or magnetron sputter because it is necessary to use two vacuum techniques—vacuum HF levitation and EB float zone melting. Rectangular cast WSi2 targets used in this study [26] for laser ablation have a volume of 1.5 cm<sup>3</sup> and are chemically homogeneous. For magnetron sputtering composite, cast silicide targets of 152 mm in diameter are produced. Our study has revealed possibilities of depositing WSi2 films by both the laser evaporation and magnetron sputtering. Other refractory metal silicides are produced in a similar way. Three experimental series are conducted to obtain silicide films: (1) laser evaporation of cast silicide targets, (2) magnetron sputtering cast silicide targets, and (3) magnetron co-sputtering of metal and Si targets. Initial materials for silicide sintering are 5N-purity Si and high-purity refractory metals (**Table 1**). Homogeneous mixtures of high-purity Si and refractory metal are prepared and isostatically pressed. Then mixture samples are sintered in a vacuum at 1100°C for 3 h. PM sintered samples are melted by vacuum HF levitation and cast in copper molds. The levitation melting consists of suspending a solid sample in HF electromagnetic field and melting it by the induced electrical currents. The resulting 25 g liquid drops have a form of the sphere. To solidify a liquid drop, it is enough to switch off an electric power. During laser ablation, the 10×15×5 mm3 cast targets are evaporated with a solid-state Nd-laser of 1.06 μm wavelength, 0.8 J pulse energy, and 10–20 Hz pulse frequency [26]. The laser beam spot is 2–3 mm in diameter. The substrates are Si(100), Si(111), MgO, ZrO2 , and Al<sup>2</sup> O3 . The substrate temperature is varied within the range of 100–750°C. The deposition time is 5–20 min and a film thickness 15–200 nm. Magnetron sputtering involves the sputter cleaning of cast targets and sputtering films in Ar. Magnetron co-sputtering is as well used to produce many other refractory metal silicides (Ti-Si, Zr-Si, Hf-Si, V-Si, Nb-Si, Ta-Si, Mo-Si, WSi2 , CoSi2 , etc.). The sputtering system is first evacuated down to a vacuum of 2×10−6 Torr prior to the deposition of thin silicide films. Si wafers are cleaned chemically prior to load into a magnetron sputter apparatus. A special care is taken to exclude such contaminants as O, C, and alkaline metals from an apparatus environment. The sputtering procedure involves sputter cleaning cast silicide targets in Ar for 5–10 min, while the shutter is closed and sputters depositing silicide films in Ar. The relative atomic impurity content in Ar is less than 3×10−6. The resistivity of thin disilicide films as well as cast disilicide targets is shown in **Table 4**.

cast blocks of 20×15×5 mm<sup>3</sup>

phospho-silicate-glass (BPSG) layer and annealed in N2

with WSi2

WSi2

with N<sup>2</sup>

at 950°C in N<sup>2</sup>

of cast specimens and of conducting WSi2

The specific resistivity of cast WSi2

evaporation (ablation) of cast WSi2

amorphous WSi2

contacts of WSi2

are machined and soldered ultrasonically to copper bases of 152 mm

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

gas. The annealing chamber is purged

before

93

diameter (**Figure 18**). Considering that our purpose is to replace a standard Al metallization

used. Following sputtering, the wafers are cleaned in a dilute HF solution for 4 min and rinsed in deionized water before loading into the deposition chamber. The wafers are treated in a buffer etchant for 10 s. A poly-Si layer 0.11 μm thick is deposited onto two wafers. The 0.25 μm thick

 layer together with a satellite is deposited, and the Al commutation is formed. The WSi2 layer is reactively ion etched. For removal of the photoresist, a plasma-chemical treatment is employed with additional chemical treatment. Then the wafers are covered with a 0.7 μm boro-

for 10 min before each anneal, and the annealed wafers are allowed to cool in N2

removing from the chamber. The BPSG layer is etched off with different chemical procedures. Various chemical treatments of etching are used on different parts of wafers. Treatment #1 consisted of stripping of the BPSG layer in a buffer etchant for 2 min. In treatment #2, the BPSG layer is stripped off in a similar buffer etchant; however, the layer is etched for 4 min. Treatment #3 involves reactive ion etching of contacts. Treatment #4 includes all three treatments listed above. The input power to sputter composite mosaic targets is as much as 260 W for 30 min for each cycle. Before sputtering, Si wafers are heated to 250–300°C. It has been found that such a procedure is sufficient to produce a clean Si surface. The deposition rate is proportional to the sputtering power at a constant pressure in the sputtering chamber. The sputtering rate and the layer thickness are monitored during deposition with the microprocessor and profilometer, respectively. The deposited silicide films are annealed in vacuum. Some samples are annealed

as well as to form the next metallization level, it is not our aim to study a resistivity of

to the *p*-type conductivity layers. Thus, the simplified technological method is

for 30 min. The film thickness is found to be 200–250 nm. The specific resistivity

sured by the four-point probe sheet resistance method. X-ray phase analysis of cast samples is performed on a Siemens D-500 diffractometer (ψ = 25°, Fe-07), and a JXA-5 apparatus is used for local X-ray spectral analysis. Chemical reactions between the film and wafer as well as the distribution of elements are studied by Auger electron spectroscopy together with ion sputtering with a JAMP-10S Auger electron spectrometer. The energy of the primary ion beam is 10 keV, and the current was 5×10−6 A. The spot is increased up to 100 μm diameter to prevent a decomposition of the material studied and to lower an electron current density. 1 keV Ar ions are used for sputtering. Instability of an ion gun is no more than 10%. The ion beam diameter is 10 mm. A scanning electron microscope study is performed with a JSM-35S and a Stereoscan 240. Both the elemental composition and elemental depth distribution of 100 nm thick WSi2 films are analyzed by means of Rutherford backscattering of 1.5 MeV He ions. After annealing of thin refractory metal films deposited in vacuum by magnetron co-sputtering of cast highpurity refractory metals on Si or Si-on-sapphire substrates at 650–700°C, stoichiometric thin

disilicide films are produced, which are confirmed by Auger electron spectrometry.

(70 μΩ cm). Local X-ray spectral analyses of cast targets show that samples are homogeneous. An analysis of the phase composition of laser-deposited films obtained by

paths as well as contacts to poly-Si layers is mea-

targets is 50 μΩ cm. It is lower than that of PM targets

targets on (100) and (111) Si substrates shows that

forms at substrate temperatures up to 400°C. Above this temperature

### *2.6.2. Depositing films of WSi<sup>2</sup>*

During magnetron sputtering, the WSi2 films are deposited onto Si(100) wafers (10–20 Ω cm) with/without a thin film (about 0.3 μm) of SiO2 at room temperature. The WSi2 films are deposited by magnetron sputtering cast targets in a sputter deposition system with a constant vacuum of 2×10−2 Torr and d.c. power of 0.26 kW [27]. To produce targets for magnetron sputtering, the WSi2


**Table 4.** Specific resistivity of thin disilicide films of refractory metals.

**Figure 18.** Composite WSi2 targets for magnetron sputtering: left, new; right, after 150 cycles.

cast blocks of 20×15×5 mm<sup>3</sup> are machined and soldered ultrasonically to copper bases of 152 mm diameter (**Figure 18**). Considering that our purpose is to replace a standard Al metallization with WSi2 as well as to form the next metallization level, it is not our aim to study a resistivity of contacts of WSi2 to the *p*-type conductivity layers. Thus, the simplified technological method is used. Following sputtering, the wafers are cleaned in a dilute HF solution for 4 min and rinsed in deionized water before loading into the deposition chamber. The wafers are treated in a buffer etchant for 10 s. A poly-Si layer 0.11 μm thick is deposited onto two wafers. The 0.25 μm thick WSi2 layer together with a satellite is deposited, and the Al commutation is formed. The WSi2 layer is reactively ion etched. For removal of the photoresist, a plasma-chemical treatment is employed with additional chemical treatment. Then the wafers are covered with a 0.7 μm borophospho-silicate-glass (BPSG) layer and annealed in N2 gas. The annealing chamber is purged with N<sup>2</sup> for 10 min before each anneal, and the annealed wafers are allowed to cool in N2 before removing from the chamber. The BPSG layer is etched off with different chemical procedures.

The substrates are Si(100), Si(111), MgO, ZrO2

Si, Zr-Si, Hf-Si, V-Si, Nb-Si, Ta-Si, Mo-Si, WSi2

targets is shown in **Table 4**.

92 Very-Large-Scale Integration

*2.6.2. Depositing films of WSi<sup>2</sup>*

During magnetron sputtering, the WSi2

with/without a thin film (about 0.3 μm) of SiO2

**Disilicide Electrical resistivity (μΩ cm)**

**Table 4.** Specific resistivity of thin disilicide films of refractory metals.

**Figure 18.** Composite WSi2

, and Al<sup>2</sup>

within the range of 100–750°C. The deposition time is 5–20 min and a film thickness 15–200 nm. Magnetron sputtering involves the sputter cleaning of cast targets and sputtering films in Ar. Magnetron co-sputtering is as well used to produce many other refractory metal silicides (Ti-

, CoSi2

ated down to a vacuum of 2×10−6 Torr prior to the deposition of thin silicide films. Si wafers are cleaned chemically prior to load into a magnetron sputter apparatus. A special care is taken to exclude such contaminants as O, C, and alkaline metals from an apparatus environment. The sputtering procedure involves sputter cleaning cast silicide targets in Ar for 5–10 min, while the shutter is closed and sputters depositing silicide films in Ar. The relative atomic impurity content in Ar is less than 3×10−6. The resistivity of thin disilicide films as well as cast disilicide

by magnetron sputtering cast targets in a sputter deposition system with a constant vacuum of 2×10−2 Torr and d.c. power of 0.26 kW [27]. To produce targets for magnetron sputtering, the WSi2

TiSi2 16.9 13–17 ZrSi2 75.8 40–43 HfSi2 62.0 150–260 VSi2 66.5 67–80 NbSi2 50.4 55–63 TaSi2 46.1 60 MoSi2 21.6 67–80 WSi2 80.1 50–70 CoSi2 16.0 30.0

targets for magnetron sputtering: left, new; right, after 150 cycles.

O3

. The substrate temperature is varied

, etc.). The sputtering system is first evacu-

films are deposited onto Si(100) wafers (10–20 Ω cm)

films are deposited

at room temperature. The WSi2

**Target Film**

Various chemical treatments of etching are used on different parts of wafers. Treatment #1 consisted of stripping of the BPSG layer in a buffer etchant for 2 min. In treatment #2, the BPSG layer is stripped off in a similar buffer etchant; however, the layer is etched for 4 min. Treatment #3 involves reactive ion etching of contacts. Treatment #4 includes all three treatments listed above. The input power to sputter composite mosaic targets is as much as 260 W for 30 min for each cycle. Before sputtering, Si wafers are heated to 250–300°C. It has been found that such a procedure is sufficient to produce a clean Si surface. The deposition rate is proportional to the sputtering power at a constant pressure in the sputtering chamber. The sputtering rate and the layer thickness are monitored during deposition with the microprocessor and profilometer, respectively. The deposited silicide films are annealed in vacuum. Some samples are annealed at 950°C in N<sup>2</sup> for 30 min. The film thickness is found to be 200–250 nm. The specific resistivity of cast specimens and of conducting WSi2 paths as well as contacts to poly-Si layers is measured by the four-point probe sheet resistance method. X-ray phase analysis of cast samples is performed on a Siemens D-500 diffractometer (ψ = 25°, Fe-07), and a JXA-5 apparatus is used for local X-ray spectral analysis. Chemical reactions between the film and wafer as well as the distribution of elements are studied by Auger electron spectroscopy together with ion sputtering with a JAMP-10S Auger electron spectrometer. The energy of the primary ion beam is 10 keV, and the current was 5×10−6 A. The spot is increased up to 100 μm diameter to prevent a decomposition of the material studied and to lower an electron current density. 1 keV Ar ions are used for sputtering. Instability of an ion gun is no more than 10%. The ion beam diameter is 10 mm. A scanning electron microscope study is performed with a JSM-35S and a Stereoscan 240. Both the elemental composition and elemental depth distribution of 100 nm thick WSi2 films are analyzed by means of Rutherford backscattering of 1.5 MeV He ions. After annealing of thin refractory metal films deposited in vacuum by magnetron co-sputtering of cast highpurity refractory metals on Si or Si-on-sapphire substrates at 650–700°C, stoichiometric thin disilicide films are produced, which are confirmed by Auger electron spectrometry.

The specific resistivity of cast WSi2 targets is 50 μΩ cm. It is lower than that of PM targets (70 μΩ cm). Local X-ray spectral analyses of cast targets show that samples are homogeneous. An analysis of the phase composition of laser-deposited films obtained by evaporation (ablation) of cast WSi2 targets on (100) and (111) Si substrates shows that amorphous WSi2 forms at substrate temperatures up to 400°C. Above this temperature it crystallizes and exhibits a mixture of the tetragonal phase and a small amount of the semiconducting hexagonal phase. As the substrate temperature is increased, the amount of the hexagonal phase decreases. At 700°C the film is single-phase tetragonal having a metallic type of conduction. At 750°C, a small amount of a second phase (W<sup>5</sup> Si3 ) reappears. The experimental results show that, as the pulse frequency is lowered, WSi2 films become multiphase. In this case the main tetragonal phase of WSi2 is observed together with a small amount of the hexagonal phase and W5 Si3 . The occurrence of a phase deficient in Si with respect to the disilicide composition might be attributed to the evaporation of the latter. The phase compositions of films obtained after annealing and those deposited immediately onto a hot substrate are similar. Interplanar distances for lines on diffraction patterns of sintered and cast WSi2 targets and of WSi2 films deposited from cast targets at 700°C are given in **Table 5**. Phase compositions of films are seen to correspond to those of targets. A small deviation of intensities of measured lines from tabulated ones indicates the presence of texture in samples. Rutherford backscattering data indicate that 100 nm WSi2 films (the Si/W ratio being approximately 2) are obtained on Si substrates (**Figure 19**). An analysis of the elemental depth distribution shows that this ratio remains constant throughout the film depth. No transitional layer between the film and the substrate (Si or neutral) is observed.

In every case, the tetragonal WSi2 , which coexisted with a small amount of W5 Si3 , is the dominant phase. The microstructural studies of the films deposited on Si(111) at 700°C in a vacuum show that they are homogeneous without ruptures. Being rather thin (30 nm), the films probably copy a substrate surface relief. The SEM studies of the cross sections of the films show that a boundary between WSi2

**Figure 19.** Rutherford backscattering spectra (*E*<sup>0</sup>

remains at the same level as in WSi2

etching, there is a light erosion of the WSi2

is greater on the samples annealed at 1000°C.

samples without poly-Si sublayers under WSi2

The mean electrical resistance of WSi2

electric resistivities of WSi2

WSi2

experimental results are obtained when WSi2

corresponding to occurrence of W and Si atoms on the surface.

analyzing zone. The behavior of O and C at WSi2

solubility of C and C diffusion coefficient in initial WSi2

layer is partially melted during annealing at 1000°C, so the WSi2

of cast composite targets. Auger electron spectrometry studies of WSi2

a sharp decrease in O and C contents during ion etching of specimens and deepening an

neously distributed in the film, which is probably a consequence of interdiffusion. Near SiO2

layer. There are no visible changes of these layers after chemical etching as well as no changes of them after etching off the BPSG layers. However, after chemical etching and reactive ion

is etched off and the etched surface has a light roughness. The BPSG layer under the WSi2

uneven (curved); however, there are no fractures or cracks. The samples annealed at 900°C have no changes at all. The most visible changes in contacts to the poly-Si and wafers of the samples annealed at 900°C show the appearance of clear distortions in contact sites of wafers without the poly-Si sublayers. The wafers with poly-Si sublayers have no changes. This effect

after annealing at 900 and 1000°C, respectively. The mean electric resistivities of WSi2

ducting paths without poly-Si sublayers are 6.65 and 5.6 Ω/□ after annealing at 900 and 1000°C, respectively. Electrical contacts to *p*-type layers are absent, because the layers in the vicinity of contacts can be heavily doped with P from the BPSG layer through the silicide layer or poly-Si. The electrical resistance of contacts to *n*-type conductivity layers on

tered with values up to 20 μΩ cm for 50 contacts. The samples with poly-Si sublayers exhibit

 interface, there is a rather narrow layer where O is sharply increased and W is sharply decreased; however, Si content after a short decrease remains at a former level. C content

=1.5 MeV) for film structure WSi2

film of 100 nm thick and Si substrate is rather distinct. Similar

layer and at the interface. This can be related to the limited

films are deposited by magnetron sputtering

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

layer is similar. W and Si are homoge-

film, transition layer, and SiO2

conducting paths are slightly

surface. It is found that about 15% of the layer

conducting paths before annealing is 33 kΩ. The mean

layers is not reproducible and is very scat-

conducting paths with poly-Si sublayers are 6.32 and 4.7 Ω/□

films have revealed

/Si. Arrows indicate energy positions

/

95

sub-

con-


**Table 5.** Interplanar distances *dhkl* of WSi2 for PM target, cast target, and thin film deposited on Si(100) substrate by laser ablation and magnetron sputtering of cast target.

it crystallizes and exhibits a mixture of the tetragonal phase and a small amount of the semiconducting hexagonal phase. As the substrate temperature is increased, the amount of the hexagonal phase decreases. At 700°C the film is single-phase tetragonal having a

cient in Si with respect to the disilicide composition might be attributed to the evaporation of the latter. The phase compositions of films obtained after annealing and those deposited immediately onto a hot substrate are similar. Interplanar distances for lines on

cast targets at 700°C are given in **Table 5**. Phase compositions of films are seen to correspond to those of targets. A small deviation of intensities of measured lines from tabulated ones indicates the presence of texture in samples. Rutherford backscattering data

Si substrates (**Figure 19**). An analysis of the elemental depth distribution shows that this ratio remains constant throughout the film depth. No transitional layer between the film

nant phase. The microstructural studies of the films deposited on Si(111) at 700°C in a vacuum show that they are homogeneous without ruptures. Being rather thin (30 nm), the films probably copy a substrate surface relief. The SEM studies of the cross sections of the films show

 3.908 3.911 3.907 3.928 3.927 2.970 2.970 2.970 2.962 2.970 2.270 2.270 2.268 2.263 2.269 2.020 2.025 2.026 2.025 2.025 1.961 1.963 1.964 1.965 – 1.961 1.963 1.964 1.965 1.964 1.603 1.606 1.606 1.601 1.608 1.485 1.485 1.484 1.483 1.484 1.412 1.412 1.413 – 1.410 1.407 1/407 1.407 1.409 – 1.304 1.305 1.304 1.308 – 1.258 1.258 1.258 1.255 1.257 1.241 1.241 1.240 – –

**File data PM powder target Cast target Film (laser) Film (magnetron)**

Si3

targets and of WSi2

films (the Si/W ratio being approximately 2) are obtained on

for PM target, cast target, and thin film deposited on Si(100) substrate by laser

, which coexisted with a small amount of W5

Si3

is observed together

films deposited from

Si3

, is the domi-

. The occurrence of a phase defi-

) reap-

films

metallic type of conduction. At 750°C, a small amount of a second phase (W<sup>5</sup>

become multiphase. In this case the main tetragonal phase of WSi2

with a small amount of the hexagonal phase and W5

diffraction patterns of sintered and cast WSi2

and the substrate (Si or neutral) is observed.

indicate that 100 nm WSi2

94 Very-Large-Scale Integration

*hkl d*

In every case, the tetragonal WSi2

**Table 5.** Interplanar distances *dhkl* of WSi2

ablation and magnetron sputtering of cast target.

pears. The experimental results show that, as the pulse frequency is lowered, WSi2

**Figure 19.** Rutherford backscattering spectra (*E*<sup>0</sup> =1.5 MeV) for film structure WSi2 /Si. Arrows indicate energy positions corresponding to occurrence of W and Si atoms on the surface.

that a boundary between WSi2 film of 100 nm thick and Si substrate is rather distinct. Similar experimental results are obtained when WSi2 films are deposited by magnetron sputtering of cast composite targets. Auger electron spectrometry studies of WSi2 films have revealed a sharp decrease in O and C contents during ion etching of specimens and deepening an analyzing zone. The behavior of O and C at WSi2 layer is similar. W and Si are homogeneously distributed in the film, which is probably a consequence of interdiffusion. Near SiO2 / WSi2 interface, there is a rather narrow layer where O is sharply increased and W is sharply decreased; however, Si content after a short decrease remains at a former level. C content remains at the same level as in WSi2 layer and at the interface. This can be related to the limited solubility of C and C diffusion coefficient in initial WSi2 film, transition layer, and SiO2 sublayer. There are no visible changes of these layers after chemical etching as well as no changes of them after etching off the BPSG layers. However, after chemical etching and reactive ion etching, there is a light erosion of the WSi2 surface. It is found that about 15% of the layer is etched off and the etched surface has a light roughness. The BPSG layer under the WSi2 layer is partially melted during annealing at 1000°C, so the WSi2 conducting paths are slightly uneven (curved); however, there are no fractures or cracks. The samples annealed at 900°C have no changes at all. The most visible changes in contacts to the poly-Si and wafers of the samples annealed at 900°C show the appearance of clear distortions in contact sites of wafers without the poly-Si sublayers. The wafers with poly-Si sublayers have no changes. This effect is greater on the samples annealed at 1000°C.

The mean electrical resistance of WSi2 conducting paths before annealing is 33 kΩ. The mean electric resistivities of WSi2 conducting paths with poly-Si sublayers are 6.32 and 4.7 Ω/□ after annealing at 900 and 1000°C, respectively. The mean electric resistivities of WSi2 conducting paths without poly-Si sublayers are 6.65 and 5.6 Ω/□ after annealing at 900 and 1000°C, respectively. Electrical contacts to *p*-type layers are absent, because the layers in the vicinity of contacts can be heavily doped with P from the BPSG layer through the silicide layer or poly-Si. The electrical resistance of contacts to *n*-type conductivity layers on samples without poly-Si sublayers under WSi2 layers is not reproducible and is very scattered with values up to 20 μΩ cm for 50 contacts. The samples with poly-Si sublayers exhibit much less scatter in a specific resistance. Thus, *R*Al-n+ = 360–400 kΩ for 50 contacts on a sample annealed at 900°C; however, the resistance for 50 contacts on a sample annealed at 1000°C is 1.4–1.8 kΩ. *R*Al-polySi = 600–700 kΩ for 100 contacts on samples annealed at 900°C; however, the analogous value for 100 contacts on samples annealed at 1000°C is 3.3–3.5 kΩ. All *n+ -p*-junctions on the large perimeter area of about 16,000 μm2 and 2120 contacts have leakage currents lower than 0.04 nA at a bias voltage of 15 V. With an increase of the bias voltage, leakage currents increase monotonically up to 0.1 nA at 20 V; however, at 21–22 V junctions have breakdowns.

the film obtained under nitrogen with O content of 10−4%. The heat treatment is conducted in a diffusion furnace. To reduce the amount of O in the as-deposited Ti films, an annealing is used together with getters. Getters are Si wafers; the front and rear sides of which are coated with Ti films of a thickness 0.1 μm. Plates are positioned before and after experimental samples relative to Ar flow. As substrates, single-crystalline wafers of *n*-Si(100) of 100 mm in diameter, doped with P to the resistance of 4.5 Ω cm, are used. In the case of Ti silicides on the polycrystalline Si, Ti films are deposited on the oxidized beforehand poly-Si of 0.45 μm thick obtained by a silane ammonolysis under a reduced pressure. The thickness of Ti films is measured by the interference method with accuracy of 0.005 μm. A silicide film thickness is calculated from known ratios, knowing the thickness of the metal film, and is measured in

temperature during depositing Ti films does not exceed 423°C. Plates are subjected to the standard chemical treatment, and immediately prior to Ti deposition, Si surface is purified by plasma etching. To investigate the degree of influence of both the alloying and impurity-type doping, Si substrates (or a poly-Si film) are subjected to ion doping with B or P at ion energies

furnace in two steps: at 898K in a nitrogen atmosphere for 30 min and, then, after removing the TiN layer, at 1123K and 30–60 min in a vacuum or Ar atmosphere. A need to anneal in nitrogen causes by the fact that the resulting surface layer consisting essentially of TiN prevented the lateral Ti diffusion which in the real VLSI structures can cause short circuits. The crystal structure of the elemental and phase composition of as-deposited films and silicide films are studied by electron diffraction, scanning and electron microscopy, Rutherford backscattering, as well as X-ray methods, in particular by "moving beam," which allows determining the change of the phase composition across the film thickness. A study is performed on the profiles of the element distribution across the film thickness by Rutherford backscattering with an initial energy of 1 MeV He ions. The scattering angle is 170°. The energy resolution of the detector system is 17 keV. To improve the depth resolution, a sliding experimental geometry is used, in which angles of incidence and scattered ions have a value of 60°. This improvement allows reaching a resolution of 10 nm for Ti and 15 nm for Si, while at normal resolution geometry, they are 20 and 30 nm, respectively. **Figure 20** shows energy spectra of Rutherford backscattering for as-deposited and annealed at 898 K samples. It can be seen (**Figure 20**, spectrum 1) that in the original Ti film, some O is present, as evidenced by the spectrum peak in 350–368 keV energy. The profiles of an element distribution, calculated from the spectrum, allow the thickness of the film to be determined, which is found to be

for the sample. Provided that the volume Ti content is 5.68×1022 at./cm3

not exceed 25%. An annealing under nitrogen at 898 K and 30 min leads to a redistribution of elements in the surface layer (**Figure 20**, spectrum 2). A layer near the surface is enriched with

sion to the unit of length in this case is not correct due to a lack of accurate data on the volume concentration of atoms in the silicide film), the relative concentration of elements corresponds

phase. After chemical or plasma-chemical removal of the fluorine-containing plasma,

N atoms and with a small amount of O. At a range of depths (3.5–5.5)×1017 at./cm<sup>2</sup>

the surface layer of the film has a phase composition of the TiSi2

), Ti film thickness is found to be ~53 μm. O mainly localized in the

(15–20 nm), and its concentration does

/Si structure. The Si substrate

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

97

is carried out in a diffusion

and

(a conver-

with some excess of Si. In

a scanning electron microscope of the vertical cleavage of TiSi2

of 40 and 60 keV, respectively. An annealing Ti film to form TiSi2

~3×1017 at./cm<sup>2</sup>

)/*N*\* (at./cm<sup>3</sup>

surface layer of the film of a thickness 1×1017 at./cm<sup>2</sup>

*d* = *x* (at./cm2

to TiSi2

Analysis of experimental results suggests that WSi2 deposited during laser evaporation do not form due to Si diffusion from the substrate. This view is supported by experiments on a film deposition on neutral substrates (MgO, Al2 O3 , ZrO<sup>2</sup> ) where the dominant phase is WSi2 . An important advantage of laser evaporation and magnetron sputtering for depositing films, compared to the annealing technology, is that single-phase films are deposited at a substrate temperature of 700°C, which is 300°C lower than in the case of annealing. Noteworthy is the fact that the tetragonal phase of WSi2 is obtained at a substrate temperature of 600°C, which is in disagreement with data, which state that this phase nucleates and grows at temperatures above 620°C. The results on room-temperature deposition of thin (30 nm) films on Si substrates (and subsequently annealing at 750°C for 1 min) are also of interest. Their phase composition is analogous to that of films deposited directly on hot substrates. This is very promising technologically. Data on Rutherford backscattering and layer-by-layer X-ray phase analysis suggest that no transition layer exists between the film and the substrate. This is also an advantage compared to the annealing technology. Tetragonal disilicide films deposited by laser evaporation have the resistivity of 50–70 μΩ cm, which conform to values for films deposited by annealing, but it is much lower than for films deposited by magnetron sputtering of PM targets (120 μΩ cm). W and Si are homogeneously distributed across the film, which is probably a consequence of their interdiffusion. Near WSi2 /SiO2 interface, there is a rather narrow transitional layer, where O and W replace each other. In SiO2 layer, following the interface, mainly Si and O are found, with low amounts of W and C. Both of these elements are distributed homogeneously in SiO2 layer by diffusion. O content in WSi2 layer is a consequence of the fast O diffusion, compared with a self-diffusion of other components of the system, and the high O solubility in W as well as in its silicides.

#### **2.7. Depositing titanium films**

Of particular interest are thin films of TiSi2 which due to their low electrical resistivity are the most promising for the inter-element wiring and silicidation areas of the emitters, collectors, and injectors of the bipolar IC, as well the sources, drains, and gates in VLSI. In this connection it is necessary to determine the conditions of formation of TiSi2 films on substrates of single- and polycrystalline Si varying degrees of doping. Here, studies are done of thin films of the TiSi2 formed by a solid-phase reaction of Ti films with the mono- and polycrystalline Si substrate. Thin films of TiSi2 are obtained by magnetron sputtering targets of highly pure Ti, produced by multiple EB vacuum-melting Ti rods and followed by a heat treatment of the film obtained under nitrogen with O content of 10−4%. The heat treatment is conducted in a diffusion furnace. To reduce the amount of O in the as-deposited Ti films, an annealing is used together with getters. Getters are Si wafers; the front and rear sides of which are coated with Ti films of a thickness 0.1 μm. Plates are positioned before and after experimental samples relative to Ar flow. As substrates, single-crystalline wafers of *n*-Si(100) of 100 mm in diameter, doped with P to the resistance of 4.5 Ω cm, are used. In the case of Ti silicides on the polycrystalline Si, Ti films are deposited on the oxidized beforehand poly-Si of 0.45 μm thick obtained by a silane ammonolysis under a reduced pressure. The thickness of Ti films is measured by the interference method with accuracy of 0.005 μm. A silicide film thickness is calculated from known ratios, knowing the thickness of the metal film, and is measured in a scanning electron microscope of the vertical cleavage of TiSi2 /Si structure. The Si substrate temperature during depositing Ti films does not exceed 423°C. Plates are subjected to the standard chemical treatment, and immediately prior to Ti deposition, Si surface is purified by plasma etching. To investigate the degree of influence of both the alloying and impurity-type doping, Si substrates (or a poly-Si film) are subjected to ion doping with B or P at ion energies of 40 and 60 keV, respectively. An annealing Ti film to form TiSi2 is carried out in a diffusion furnace in two steps: at 898K in a nitrogen atmosphere for 30 min and, then, after removing the TiN layer, at 1123K and 30–60 min in a vacuum or Ar atmosphere. A need to anneal in nitrogen causes by the fact that the resulting surface layer consisting essentially of TiN prevented the lateral Ti diffusion which in the real VLSI structures can cause short circuits. The crystal structure of the elemental and phase composition of as-deposited films and silicide films are studied by electron diffraction, scanning and electron microscopy, Rutherford backscattering, as well as X-ray methods, in particular by "moving beam," which allows determining the change of the phase composition across the film thickness. A study is performed on the profiles of the element distribution across the film thickness by Rutherford backscattering with an initial energy of 1 MeV He ions. The scattering angle is 170°. The energy resolution of the detector system is 17 keV. To improve the depth resolution, a sliding experimental geometry is used, in which angles of incidence and scattered ions have a value of 60°. This improvement allows reaching a resolution of 10 nm for Ti and 15 nm for Si, while at normal resolution geometry, they are 20 and 30 nm, respectively. **Figure 20** shows energy spectra of Rutherford backscattering for as-deposited and annealed at 898 K samples. It can be seen (**Figure 20**, spectrum 1) that in the original Ti film, some O is present, as evidenced by the spectrum peak in 350–368 keV energy. The profiles of an element distribution, calculated from the spectrum, allow the thickness of the film to be determined, which is found to be ~3×1017 at./cm<sup>2</sup> for the sample. Provided that the volume Ti content is 5.68×1022 at./cm3 and *d* = *x* (at./cm2 )/*N*\* (at./cm<sup>3</sup> ), Ti film thickness is found to be ~53 μm. O mainly localized in the surface layer of the film of a thickness 1×1017 at./cm<sup>2</sup> (15–20 nm), and its concentration does not exceed 25%. An annealing under nitrogen at 898 K and 30 min leads to a redistribution of elements in the surface layer (**Figure 20**, spectrum 2). A layer near the surface is enriched with N atoms and with a small amount of O. At a range of depths (3.5–5.5)×1017 at./cm<sup>2</sup> (a conversion to the unit of length in this case is not correct due to a lack of accurate data on the volume concentration of atoms in the silicide film), the relative concentration of elements corresponds to TiSi2 phase. After chemical or plasma-chemical removal of the fluorine-containing plasma, the surface layer of the film has a phase composition of the TiSi2 with some excess of Si. In

much less scatter in a specific resistance. Thus, *R*Al-n+ = 360–400 kΩ for 50 contacts on a sample annealed at 900°C; however, the resistance for 50 contacts on a sample annealed at 1000°C is 1.4–1.8 kΩ. *R*Al-polySi = 600–700 kΩ for 100 contacts on samples annealed at 900°C; however, the analogous value for 100 contacts on samples annealed at 1000°C is 3.3–3.5 kΩ.

leakage currents lower than 0.04 nA at a bias voltage of 15 V. With an increase of the bias voltage, leakage currents increase monotonically up to 0.1 nA at 20 V; however, at 21–22 V

not form due to Si diffusion from the substrate. This view is supported by experiments on

ture of 600°C, which is in disagreement with data, which state that this phase nucleates and grows at temperatures above 620°C. The results on room-temperature deposition of thin (30 nm) films on Si substrates (and subsequently annealing at 750°C for 1 min) are also of interest. Their phase composition is analogous to that of films deposited directly on hot substrates. This is very promising technologically. Data on Rutherford backscattering and layer-by-layer X-ray phase analysis suggest that no transition layer exists between the film and the substrate. This is also an advantage compared to the annealing technology. Tetragonal disilicide films deposited by laser evaporation have the resistivity of 50–70 μΩ cm, which conform to values for films deposited by annealing, but it is much lower than for films deposited by magnetron sputtering of PM targets (120 μΩ cm). W and Si are homogeneously distributed across the film, which is probably a consequence of their interdiffu-

low amounts of W and C. Both of these elements are distributed homogeneously in SiO2

pared with a self-diffusion of other components of the system, and the high O solubility in

most promising for the inter-element wiring and silicidation areas of the emitters, collectors, and injectors of the bipolar IC, as well the sources, drains, and gates in VLSI. In this connec-

single- and polycrystalline Si varying degrees of doping. Here, studies are done of thin films

Ti, produced by multiple EB vacuum-melting Ti rods and followed by a heat treatment of

formed by a solid-phase reaction of Ti films with the mono- and polycrystalline

tion it is necessary to determine the conditions of formation of TiSi2

. An important advantage of laser evaporation and magnetron sputtering for depositing films, compared to the annealing technology, is that single-phase films are deposited at a substrate temperature of 700°C, which is 300°C lower than in the case of annealing.

O3 , ZrO<sup>2</sup>

interface, there is a rather narrow transitional layer, where O and W

layer, following the interface, mainly Si and O are found, with

layer is a consequence of the fast O diffusion, com-

which due to their low electrical resistivity are the

are obtained by magnetron sputtering targets of highly pure

films on substrates of

and 2120 contacts have

deposited during laser evaporation do

) where the dominant phase is

is obtained at a substrate tempera-

*-p*-junctions on the large perimeter area of about 16,000 μm2

All *n+*

96 Very-Large-Scale Integration

WSi2

sion. Near WSi2

of the TiSi2

/SiO2

layer by diffusion. O content in WSi2

Of particular interest are thin films of TiSi2

replace each other. In SiO2

W as well as in its silicides.

**2.7. Depositing titanium films**

Si substrate. Thin films of TiSi2

junctions have breakdowns.

Analysis of experimental results suggests that WSi2

a film deposition on neutral substrates (MgO, Al2

Noteworthy is the fact that the tetragonal phase of WSi2

**2.8. Studying TiSi2**

700°C, only TiSi2

formation of TiO<sup>2</sup>

TiSi without TiSi2

to TiSi2

*2.8.2. TiSi2*

to prepare TiSi2

surface SiO2

acted Ti, TiO<sup>2</sup>

thickness of TiSi2

*/Si interfaces*

of Ti films is 40–80 nm. TiSi2

annealing is carried out at 600–700°C under a N<sup>2</sup>

methods, such as fast neutron activation, deuteron activation, He3

*2.8.1. Short background*

**/Si interfaces**

single-crystalline Si substrate, the growth rate of TiSi2

and TiSi2

A study on the interaction of Ti atoms with a Si surface as chemical reactions at the interface between thin films of Ti and Si is of great interest. It is known that at Ti-Si interface at above

growth rate is proportional to the square root of the annealing time (so-called *t*0.5 rule). On a

are uneven in a thickness if Ti-Si interface contaminated with impurities. Annealing Ti films on the single-crystalline Si in oxygen or in a mixture of oxygen + nitrogen at 600°C leads to a

mate analytic possibilities of EELS in a study of chemical transformations at Ti-Si interface.

Single-crystal Si(100) wafers doped with P and Ti rods after EB floating zone melting are used

with the electrical resistance of 1 Ω cm are previously chemically cleaned from organic impurities and then immersed in HF, followed by washing in a deionized water to remove a natural

subsequent silicide formation is done by the two-stage high-temperature annealing. The first

homogenization are completed at a second annealing at 800°C under Ar atmosphere. The

four-point probe. The typical resistivity of the Ti layers is 50 μΩ cm; the resistivity of the TiSi2 layers is 13 μΩ cm. An analysis of trace impurities is performed by high sensitive physical

trometry with inductively coupled plasma, etc. When registering electron spectra in the analog mode, the relative energy resolution is 0.6%; in a retarding mode, the absolute resolution

films by a standard self-aligned silicide method in Ti-Si(100) system. Si wafers

. A Si substrate temperature during Ti deposition is about 180°C. The thickness

, and TiN are removed using an etchant selective to silicide. Silicidation and

layers is about 100 nm. The sheet resistance of the films is measured by a

films are deposited by magnetron sputtering of Ti targets. A

atmosphere for 35–40 min. An excess unre-

ion activation, mass spec-

. It is also interesting that at room temperature, Ti and Si do not interact at Ti-Si(100) interface. From electron spectroscopy, similar data for Ti-Si(111) system are also known. However, by RBS experiments a diffuseness of Ti-Si(111) interface at room temperature has been discussed. The main reason of this obstacle for solving the problem is a lack of suitable instruments to identify the reaction products in a Ti-Si system. These instruments should be similar in their capabilities, especially in the depth of the layer to be analyzed. They should be based on a study of Si(L2.3VV) Auger line shape of, e.g., PtSi system. Thus, it seems that the most distinguished technique which can help us in eliminating the problem is an electron energy-loss spectroscopy (EELS) which is known by its high sensitivity to electronic restructuring of solid surfaces and by possibilities to vary a depth of the layer under analysis [28].

; however, a heating in N2

. Whereas if to anneal a mixture of Ti5

The goal of this study is to obtain electron energy-loss spectra of TiSi2

can be formed. It is also proved that on an amorphous Si substrate, the

Si3

is much slower, and grown TiSi2

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

leads to the formation of TiN, Ti5

and TiSi at >800°C, it transforms

, Ti, and Si and to esti-

films

99

Si3 , and

**Figure 20.** Energy-loss RBS spectra for as-deposited and annealed at 898 K samples. Ti (1) and TiSi2 (2, 3), 2, 3—898K; 2—15 min; 3—15 min after etching off upper layer.

this case, the films do not contain N and O in amounts sufficient for detection by RBS. As a result of X-ray studies, it is established that the formed TiSi2 phase has an orthorhombic C54 structure with lattice constants *a* = 0.825 nm, *b* = 0.4783 nm, and *c* = 0.854 nm, wherein Ti5 O9 phase is detected on the surface of the film (α = 0.5, 1 deg). The phase composition of films is enough uniform in thickness.

There is no significant difference for TiSi2 films formed on *n*- and *p*-type substrates. After the plasma-chemical removal of the surface layer, TiSi2 film is amorphous, and after re-annealing at 1123K, is polycrystalline with an average grain size 0.1–0.3 μm. After the removal of TiSi2 film, precipitates are found on the substrate surface which can be easily removed mechanically. An analysis of these precipitates by electron diffraction has revealed that it is TiN, resulting in the surface film due to its annealing in a nitrogen environment. These results are consistent with RBS (**Figure 20**, spectrum 2). Studies, as well as microreliefs of the substrate surface after the removal TiSi2 film, lead to the conclusion about a fairly clear boundary between TiSi2 film and Si substrate. It can be explained by the mechanism of an interaction of Ti with Si, at which a diffusing dopant is predominantly Si. A second stage of annealing the film at 1023K during 30 and 60 min, after the removal of TiN surface layer, leads to a stabilization of C54 TiSi2 phase. Under these conditions, TiSi2 films have a homogeneous phase composition across their thickness and did not contain the phase of Ti5 O9 . Seemingly it had been removed together with the surface layer. The resistivity of the films of C54 TiSi2 is 13–15 μΩ cm, which is in agreement with known data. With increasing of the substrate doping with P or B, any changes in the phase composition of films are not established: only forming the low-impedance phase C54 TiSi2 . It is shown that the low-impedance phase C54 is formed at 963 K during 10–30 min, and its formation is dependent on O content in as-deposited Ti films. Reducing the temperature of the formation of the phase C54 in TiSi2 to 898 K, in this case, may be linked with a sufficiently low O content in as-deposited Ti films. This in turn is determined by the method of producing Ti targets and characteristics of the heat treatment of films associated with additional getters.

#### **2.8. Studying TiSi2 /Si interfaces**

### *2.8.1. Short background*

A study on the interaction of Ti atoms with a Si surface as chemical reactions at the interface between thin films of Ti and Si is of great interest. It is known that at Ti-Si interface at above 700°C, only TiSi2 can be formed. It is also proved that on an amorphous Si substrate, the growth rate is proportional to the square root of the annealing time (so-called *t*0.5 rule). On a single-crystalline Si substrate, the growth rate of TiSi2 is much slower, and grown TiSi2 films are uneven in a thickness if Ti-Si interface contaminated with impurities. Annealing Ti films on the single-crystalline Si in oxygen or in a mixture of oxygen + nitrogen at 600°C leads to a formation of TiO<sup>2</sup> and TiSi2 ; however, a heating in N2 leads to the formation of TiN, Ti5 Si3 , and TiSi without TiSi2 . Whereas if to anneal a mixture of Ti5 Si3 and TiSi at >800°C, it transforms to TiSi2 . It is also interesting that at room temperature, Ti and Si do not interact at Ti-Si(100) interface. From electron spectroscopy, similar data for Ti-Si(111) system are also known. However, by RBS experiments a diffuseness of Ti-Si(111) interface at room temperature has been discussed. The main reason of this obstacle for solving the problem is a lack of suitable instruments to identify the reaction products in a Ti-Si system. These instruments should be similar in their capabilities, especially in the depth of the layer to be analyzed. They should be based on a study of Si(L2.3VV) Auger line shape of, e.g., PtSi system. Thus, it seems that the most distinguished technique which can help us in eliminating the problem is an electron energy-loss spectroscopy (EELS) which is known by its high sensitivity to electronic restructuring of solid surfaces and by possibilities to vary a depth of the layer under analysis [28]. The goal of this study is to obtain electron energy-loss spectra of TiSi2 , Ti, and Si and to estimate analytic possibilities of EELS in a study of chemical transformations at Ti-Si interface.

#### *2.8.2. TiSi2 /Si interfaces*

this case, the films do not contain N and O in amounts sufficient for detection by RBS. As a

phase is detected on the surface of the film (α = 0.5, 1 deg). The phase composition of films is

at 1123K, is polycrystalline with an average grain size 0.1–0.3 μm. After the removal of TiSi2 film, precipitates are found on the substrate surface which can be easily removed mechanically. An analysis of these precipitates by electron diffraction has revealed that it is TiN, resulting in the surface film due to its annealing in a nitrogen environment. These results are consistent with RBS (**Figure 20**, spectrum 2). Studies, as well as microreliefs of the substrate

of Ti with Si, at which a diffusing dopant is predominantly Si. A second stage of annealing the film at 1023K during 30 and 60 min, after the removal of TiN surface layer, leads to a sta-

μΩ cm, which is in agreement with known data. With increasing of the substrate doping with P or B, any changes in the phase composition of films are not established: only forming

at 963 K during 10–30 min, and its formation is dependent on O content in as-deposited Ti

case, may be linked with a sufficiently low O content in as-deposited Ti films. This in turn is determined by the method of producing Ti targets and characteristics of the heat treatment

phase. Under these conditions, TiSi2

been removed together with the surface layer. The resistivity of the films of C54 TiSi2

composition across their thickness and did not contain the phase of Ti5

films. Reducing the temperature of the formation of the phase C54 in TiSi2

structure with lattice constants *a* = 0.825 nm, *b* = 0.4783 nm, and *c* = 0.854 nm, wherein Ti5

**Figure 20.** Energy-loss RBS spectra for as-deposited and annealed at 898 K samples. Ti (1) and TiSi2

phase has an orthorhombic C54

films formed on *n*- and *p*-type substrates. After the

film, lead to the conclusion about a fairly clear boundary

. It is shown that the low-impedance phase C54 is formed

film and Si substrate. It can be explained by the mechanism of an interaction

film is amorphous, and after re-annealing

films have a homogeneous phase

. Seemingly it had

to 898 K, in this

is 13–15

O9

O9

(2, 3), 2, 3—898K;

result of X-ray studies, it is established that the formed TiSi2

enough uniform in thickness.

98 Very-Large-Scale Integration

surface after the removal TiSi2

the low-impedance phase C54 TiSi2

of films associated with additional getters.

between TiSi2

bilization of C54 TiSi2

There is no significant difference for TiSi2

2—15 min; 3—15 min after etching off upper layer.

plasma-chemical removal of the surface layer, TiSi2

Single-crystal Si(100) wafers doped with P and Ti rods after EB floating zone melting are used to prepare TiSi2 films by a standard self-aligned silicide method in Ti-Si(100) system. Si wafers with the electrical resistance of 1 Ω cm are previously chemically cleaned from organic impurities and then immersed in HF, followed by washing in a deionized water to remove a natural surface SiO2 . A Si substrate temperature during Ti deposition is about 180°C. The thickness of Ti films is 40–80 nm. TiSi2 films are deposited by magnetron sputtering of Ti targets. A subsequent silicide formation is done by the two-stage high-temperature annealing. The first annealing is carried out at 600–700°C under a N<sup>2</sup> atmosphere for 35–40 min. An excess unreacted Ti, TiO<sup>2</sup> , and TiN are removed using an etchant selective to silicide. Silicidation and homogenization are completed at a second annealing at 800°C under Ar atmosphere. The thickness of TiSi2 layers is about 100 nm. The sheet resistance of the films is measured by a four-point probe. The typical resistivity of the Ti layers is 50 μΩ cm; the resistivity of the TiSi2 layers is 13 μΩ cm. An analysis of trace impurities is performed by high sensitive physical methods, such as fast neutron activation, deuteron activation, He3 ion activation, mass spectrometry with inductively coupled plasma, etc. When registering electron spectra in the analog mode, the relative energy resolution is 0.6%; in a retarding mode, the absolute resolution does not depend on the energy and is of 0.7 eV. Electron spectra are measured in a spectrometer with a double-pass cylindrical mirror analyzer. To get Auger electron spectra, a monoenergetic (half width, 0.5 eV) electron beam is used with an energy of *E*p = 3 keV. For electron energy-loss spectra (EELS), electron beams with energies 100, 400, and 2000 eV are used. The removal of surface contaminations and analysis of the depth distribution of elements are conducted in combination with sputtering of the sample surface by 2 keV Ar ions with 9 μA cm2 . A residual gas pressure in the test chamber of the spectrometer is 5×10−8 Pa, and Ar pressure during sputtering was 3×10−3 Pa. An elemental analysis is performed by Auger spectroscopy using factors of an elemental sensitivity.

the thin Si layer on the surface of Ti or TiSi<sup>x</sup>

tron approximation: ωp = (4π*ne*<sup>2</sup>

*N* (*E*)/d*E*<sup>2</sup>

known values of specific densities ρTi = 4.51 g/cm<sup>3</sup>

the main peak in EEL spectrum with *E*p = 100 eV of TiSi2

the most analytic spectra are spectra with narrow peaks.

**Sample** *M* **ћω<sup>s</sup>**

**Table 6.** The maximum positions *M* of the EEL spectra and plasmon energies ћωp (in eV).

ωs

4.043 g/cm3

derivative d<sup>2</sup>

energy ћω<sup>s</sup>

films differ from those in a bulk Si. The changes

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

/*m*)1/2, where *n* a density of valence electrons per volume unit,

. For TiSi2

is very close to the surface plasmon

and ρsi = 2.33 g/cm<sup>3</sup>

for *E*p = 153 eV [31]. A comparison of energy shows that a location of

at various

101

a density of

for different

,

**/***m)***1/2**

observed in the low-energy part of the Auger spectrum are due to changes in Auger energylosses spectra. Therefore, EEL spectra are studied using a monochromatic electron beam as an excitation source. EEL spectra, which are obtained in reflection geometry, provided data on excitations in layers of 0.3–2 nm thick. Thus, a contribution of surface excitations, as a rule, is of a great importance for these spectra. The value of this contribution depends on both the mean-free path of electrons in analysis and the experimental geometry. In addition to a quantitative interpretation of reflection, EEL spectra should be taken into account not only

For analytical purposes, some of the parameters of the measured spectra are often possible to use without further mathematical processing. For example, energy positions of major peaks in EEL spectra are slightly depended on a shape of multiple scattering histories. It is of inter-

energies of primary electron energies of bulk and surface plasmons, estimated in a free-elec-

= ωp/√2 (see **Table 6**). An estimation of the valence electron density is carried out using

energy values differ from maxima locations in EEL spectra recorded in a form of the second

contributions of both the bulk and surface plasmons in EEL spectrum at *E*p = 400 eV are comparable in a magnitude. As the energy of primary electrons increases, spectral peaks become narrower. A total width at a half height of the mean peak, Δ1/2, received by this method, is decreased from 19 eV at *E*p = 100 eV to 10 eV at *E*p = 2 keV. This parameter is influenced by the background of electron inelastic scattering. Thus, a peak width at 3/4 height, Δ3/4, seems more

energies of primary electrons is done. The spectra differences can be observed for all *E*p, but

Considering spectra at *E*p = 100 eV, when a mean-free electron path is minimal—0.4 nm, the locations of the main maxima in the spectra are different, but due to a complicated shape of spectra, the energy locations cannot be the main analytical functions. It seems that more characteristics are widths Δ3/4 that are equal to 16.3, 13.7, and 10.5 eV for spectra of Ti, TiSi2

Si 15.2 16.8 17.0 16.8 16.6 Ti 8.4 14.6 17.4 19.2 17.7 TiSi2 13.2 18.0 19.0 17.2 19.8

**100 400 2000 Ref. [31] (4π***ne***<sup>2</sup>**

analytical. A comparison of EEL spectra of Ti and Si with the spectrum of TiSi2

measured by X-ray analysis is used [25]. It should be emphasized that tabulated

= 13.9 eV and with *E*p = 2 keV, which is close to the bulk plasmon energy. The

multiple small-angle electron scattering but large-angle scattering as well.

est to compare measured energy locations of intense peaks in EEL spectra of TiSi2

The electrical properties of metal and silicide layers in Ti-Si system depend strongly on impurities. Thus, it is very important to use Ti targets with the highest purity for the sputter. This means a low content of gas-forming interstitials and metal impurities. After a complex of vacuum procedures, Ti designed for magnetron sputtering contains trace impurities according with **Table 1**. In **Figure 21** a distribution of elements in TiSi2 films is shown. A subsurface area, after sputter over 9 min, contains, besides TiSi2 , certain amounts of TiN and SiO2 . These data can be drawn from an analysis of the form Si (L2.3VV) lines and an intensity ratio of Ti (LMV) (418 eV) to Ti (LMM) (387 eV). A composition of the interior of films, sputtered for 30 min (from 10th min etching up to the 40th min), is close to TiSi2 . A total content of gas-forming interstitials (C, O) in this area of films is not greater than 1–2 at.%. Note that the ratio of peak intensities of Ti (418 eV)/Ti (387 eV) lines in TiSi2 , measured at a modulation voltage of 3 V, is equal to 1.13. This value is very close to 1.2. For metal Ti this value is 1.6; thus, an intensity ratio of Ti (418 eV)/Ti(387 eV) may be used for analytical purposes when estimating a number of Ti atoms in reaction with Si. Si(L2.3VV) Auger line shape in the transition region from TiSi2 to Si varies insignificantly at layer-to-layer sputtering. Such behavior is known as a characteristic of refractory metals silicides [29, 30]. It is noted that in the range of kinetic energies from 75 to 85 eV, however, variations of electron spectra nevertheless happened. It seems that this fact is difficult to use for analytical purposes because of a low relative intensity of this spectral region. Thus, a shift of Si (L2.3VV) line by 1.3 eV, observed in the initial stage of the formation of TiSi2 , seems to be due to the fact that relaxation conditions during the Auger process in

**Figure 21.** Profile element distribution in TiSi2 /Si(100) structure, obtained by AES during etching with argon ions.

the thin Si layer on the surface of Ti or TiSi<sup>x</sup> films differ from those in a bulk Si. The changes observed in the low-energy part of the Auger spectrum are due to changes in Auger energylosses spectra. Therefore, EEL spectra are studied using a monochromatic electron beam as an excitation source. EEL spectra, which are obtained in reflection geometry, provided data on excitations in layers of 0.3–2 nm thick. Thus, a contribution of surface excitations, as a rule, is of a great importance for these spectra. The value of this contribution depends on both the mean-free path of electrons in analysis and the experimental geometry. In addition to a quantitative interpretation of reflection, EEL spectra should be taken into account not only multiple small-angle electron scattering but large-angle scattering as well.

For analytical purposes, some of the parameters of the measured spectra are often possible to use without further mathematical processing. For example, energy positions of major peaks in EEL spectra are slightly depended on a shape of multiple scattering histories. It is of interest to compare measured energy locations of intense peaks in EEL spectra of TiSi2 at various energies of primary electron energies of bulk and surface plasmons, estimated in a free-electron approximation: ωp = (4π*ne*<sup>2</sup> /*m*)1/2, where *n* a density of valence electrons per volume unit, ωs = ωp/√2 (see **Table 6**). An estimation of the valence electron density is carried out using known values of specific densities ρTi = 4.51 g/cm<sup>3</sup> and ρsi = 2.33 g/cm<sup>3</sup> . For TiSi2 a density of 4.043 g/cm3 measured by X-ray analysis is used [25]. It should be emphasized that tabulated energy values differ from maxima locations in EEL spectra recorded in a form of the second derivative d<sup>2</sup> *N* (*E*)/d*E*<sup>2</sup> for *E*p = 153 eV [31]. A comparison of energy shows that a location of the main peak in EEL spectrum with *E*p = 100 eV of TiSi2 is very close to the surface plasmon energy ћω<sup>s</sup> = 13.9 eV and with *E*p = 2 keV, which is close to the bulk plasmon energy. The contributions of both the bulk and surface plasmons in EEL spectrum at *E*p = 400 eV are comparable in a magnitude. As the energy of primary electrons increases, spectral peaks become narrower. A total width at a half height of the mean peak, Δ1/2, received by this method, is decreased from 19 eV at *E*p = 100 eV to 10 eV at *E*p = 2 keV. This parameter is influenced by the background of electron inelastic scattering. Thus, a peak width at 3/4 height, Δ3/4, seems more analytical. A comparison of EEL spectra of Ti and Si with the spectrum of TiSi2 for different energies of primary electrons is done. The spectra differences can be observed for all *E*p, but the most analytic spectra are spectra with narrow peaks.

Considering spectra at *E*p = 100 eV, when a mean-free electron path is minimal—0.4 nm, the locations of the main maxima in the spectra are different, but due to a complicated shape of spectra, the energy locations cannot be the main analytical functions. It seems that more characteristics are widths Δ3/4 that are equal to 16.3, 13.7, and 10.5 eV for spectra of Ti, TiSi2 ,


**Table 6.** The maximum positions *M* of the EEL spectra and plasmon energies ћωp (in eV).

**Figure 21.** Profile element distribution in TiSi2

of TiSi2

using factors of an elemental sensitivity.

100 Very-Large-Scale Integration

ing with **Table 1**. In **Figure 21** a distribution of elements in TiSi2

min (from 10th min etching up to the 40th min), is close to TiSi2

area, after sputter over 9 min, contains, besides TiSi2

intensities of Ti (418 eV)/Ti (387 eV) lines in TiSi2

/Si(100) structure, obtained by AES during etching with argon ions.

does not depend on the energy and is of 0.7 eV. Electron spectra are measured in a spectrometer with a double-pass cylindrical mirror analyzer. To get Auger electron spectra, a monoenergetic (half width, 0.5 eV) electron beam is used with an energy of *E*p = 3 keV. For electron energy-loss spectra (EELS), electron beams with energies 100, 400, and 2000 eV are used. The removal of surface contaminations and analysis of the depth distribution of elements are conducted in combination with sputtering of the sample surface by 2 keV Ar ions with 9 μA cm2

A residual gas pressure in the test chamber of the spectrometer is 5×10−8 Pa, and Ar pressure during sputtering was 3×10−3 Pa. An elemental analysis is performed by Auger spectroscopy

The electrical properties of metal and silicide layers in Ti-Si system depend strongly on impurities. Thus, it is very important to use Ti targets with the highest purity for the sputter. This means a low content of gas-forming interstitials and metal impurities. After a complex of vacuum procedures, Ti designed for magnetron sputtering contains trace impurities accord-

data can be drawn from an analysis of the form Si (L2.3VV) lines and an intensity ratio of Ti (LMV) (418 eV) to Ti (LMM) (387 eV). A composition of the interior of films, sputtered for 30

interstitials (C, O) in this area of films is not greater than 1–2 at.%. Note that the ratio of peak

is equal to 1.13. This value is very close to 1.2. For metal Ti this value is 1.6; thus, an intensity ratio of Ti (418 eV)/Ti(387 eV) may be used for analytical purposes when estimating a number of Ti atoms in reaction with Si. Si(L2.3VV) Auger line shape in the transition region from TiSi2 to Si varies insignificantly at layer-to-layer sputtering. Such behavior is known as a characteristic of refractory metals silicides [29, 30]. It is noted that in the range of kinetic energies from 75 to 85 eV, however, variations of electron spectra nevertheless happened. It seems that this fact is difficult to use for analytical purposes because of a low relative intensity of this spectral region. Thus, a shift of Si (L2.3VV) line by 1.3 eV, observed in the initial stage of the formation

, seems to be due to the fact that relaxation conditions during the Auger process in

.

. These

films is shown. A subsurface

. A total content of gas-forming

, certain amounts of TiN and SiO2

, measured at a modulation voltage of 3 V,

and Si, respectively, at *E*p=100 eV. By measuring values for thin Ti-Si films, their presence can be found in the layer of 0.4 nm thick. Of course, there is a problem of distinguishing a simple mixture of Ti+Si and TiSi2 with EEL spectra. The artificial spectrum of a simple unreacted Ti+Si mixture is produced by a superposition of EEL spectra normalized to the elastic peak intensity and taken with corresponding weights. It can be shown that at low primary electron energy (*E*p=100 eV), when a peak width is greater, a value of Δ3/4 close to that for TiSi2 may be received at a certain mixture composition. In this case, the simple unreacted Ti+Si mixture and a composition of TiSi2 layer after a chemical reaction may be distinguished, because (*a*) the location of the maximum in the spectrum of the mixture is close either to the location of the maximum in Ti spectrum (8.4 eV) or Si spectrum (15.2 eV), excluding a small transition region of compositions near Ti-Si=1; (*b*) with coincident maxima in spectra, the *a* location on the energy-loss scale corresponds to 29.9 eV for TiSi2 and 24.6 eV for the mixture of Ti+Si spectrum. With *E*p = 2 keV, it is not difficult to distinguish EEL spectrum of TiSi2 from those of the mechanical Ti+Si mixture, because for mixture spectra the location of the main maximum are within 17–17.4 eV, whereas for TiSi2 this value is 18.8 eV (**Figure 22**). Besides, the EEL spectrum of TiSi2 exhibits also a second maximum at energy of ≈38 eV that is missing in spectra of Ti-Si mixture. Thus, EELS enables one to carry out an analysis of an interaction of components in Ti-Si system with a high depth resolution.

diffraction patterns in the sliding beam incidence and Rutherford backscattering of He ions, the phase and elemental composition of the films are investigated. Currently in microelectronics two methods are used for producing silicide thin films. The first of them is a deposition of metal films on a Si surface, followed by high-temperature annealing. The second is composed of sputtering targets made of a silicide powder. Unfortunately, the manufacture of targets using PM technologies usually leads to instabilities of sputtering and contamination of targets, which increase the specific resistivity of deposited films. Thus, vacuum-melting procedures, seemingly, become an optimal and logic decision for the production of targets. In recent years, interesting results have been obtained by the method of sputtering metal and semiconductor films by a laser radiation which has several advantages over other methods of depositing films. It is compatible with high vacuum setups and does not require using a working gas. When the laser radiation flux density in the affected area exceeds 10−9 W s−2, the evaporation of the target material takes place without a formation of a liquid phase (laser ablation), so that the stoichiometry of the film corresponds to the composition of the target. This is an excellent opportunity of using laser deposition films for substances with a complex stoichiometry. A high efficient sputter rate (10−6 A s−1) supports reducing the contamination of the film by the residual gasses of the vacuum system. Due to the

temperatures than for other methods. Here, experimental results of our studies are presented of

purity and a commercial Co. To further increase the purity of Co, a double EB vacuum refining is performed [15]. A typical content of impurities after chemical and EB floating zone

tion, the mixture of high-purity Co and Si is melted in a vacuum induction furnace in high purity Ar. The melt is poured into molds receiving rods of 10 mm in diameter and 150 mm

are of 20×15×5 mm. They are evaporated by laser in a vacuum setup. A solid-state Nd-glass laser is used with wavelength of 1.06 μm, pulse repetition rate of 10 Hz, and pulse energy of 0.8 J. The vacuum chamber is evacuated to a vacuum of 1×10−6 Torr using a turbo pump. The laser beam is focused by a lens; the focal spot size is 2–3 mm. A distance between the target and substrate is 70 mm. For heating the substrate, an infrared heater with halogen lamps is

, and ZrO<sup>2</sup>

subjected to chemical cleaning and then immediately prior to depositing are heated at 850° for 10 min in vacuum. The temperature of substrates is varied in the range of 100–800°; the deposition time is varied from 5 to 20 min. A film thickness is measured using a profilometer and is from 300 to 1500 Å. The specific resistivity of bulk samples and thin films is measured

ingots does not lead to a significant change in its phase composition. The specific resistiv-

in length. The resulting bars are subjected to double floating EB zone melting. CoSi2

O3

films by laser ablation of cast high-purity targets.

K), it is possible to obtain epitaxial films at lower substrate

High-purity Refractory Metals for Thin Film Metallization of VLSI

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103

targets are used a polycrystalline Si of 99.999%

of a stoichiometric composi-

are used as substrates. Substrates are

samples show that they are a single phase

samples. Double EB melting of CoSi2

. A local X-ray analysis of cross sections has revealed

is 16–20 μΩ cm, which is close to the data, obtained for single

targets

high energy of condensed atoms (10<sup>5</sup>

*2.9.2. Depositing cobalt disilicide films*

As the initial materials for preparing CoSi2

used. The Si(100) wafers, mica, MgO, Al2

and composed of stoichiometric CoSi2

ity of bulk samples of CoSi2

by the four-point probe method. XRD data of CoSi2

the homogeneity of the chemical composition of CoSi2

purifying is shown in **Table 1**. For the preparation of CoSi2

obtaining the CoSi2

### **2.9. Depositing cobalt disilicide films by laser ablation**

### *2.9.1. Short background*

An interest in silicides of refractory metals has increased significantly due to their great potential as a material of low resistance contacts, gates, and interconnects of the thin-film metallization of Si integrated circuits. The principal possibility of obtaining pure CoSi2 targets by vacuummetallurgical methods is developed [15, 32]. The optimal conditions of sputter targets have been revealed, providing a deposition of CoSi2 films with the specific resistivity of 30 μΩ cm. By X-ray

**Figure 22.** Electron energy-loss spectra of Ti (1) and Si (2); a linear combination of these spectra with different weight fractions.

diffraction patterns in the sliding beam incidence and Rutherford backscattering of He ions, the phase and elemental composition of the films are investigated. Currently in microelectronics two methods are used for producing silicide thin films. The first of them is a deposition of metal films on a Si surface, followed by high-temperature annealing. The second is composed of sputtering targets made of a silicide powder. Unfortunately, the manufacture of targets using PM technologies usually leads to instabilities of sputtering and contamination of targets, which increase the specific resistivity of deposited films. Thus, vacuum-melting procedures, seemingly, become an optimal and logic decision for the production of targets. In recent years, interesting results have been obtained by the method of sputtering metal and semiconductor films by a laser radiation which has several advantages over other methods of depositing films. It is compatible with high vacuum setups and does not require using a working gas. When the laser radiation flux density in the affected area exceeds 10−9 W s−2, the evaporation of the target material takes place without a formation of a liquid phase (laser ablation), so that the stoichiometry of the film corresponds to the composition of the target. This is an excellent opportunity of using laser deposition films for substances with a complex stoichiometry. A high efficient sputter rate (10−6 A s−1) supports reducing the contamination of the film by the residual gasses of the vacuum system. Due to the high energy of condensed atoms (10<sup>5</sup> K), it is possible to obtain epitaxial films at lower substrate temperatures than for other methods. Here, experimental results of our studies are presented of obtaining the CoSi2 films by laser ablation of cast high-purity targets.

#### *2.9.2. Depositing cobalt disilicide films*

and Si, respectively, at *E*p=100 eV. By measuring values for thin Ti-Si films, their presence can be found in the layer of 0.4 nm thick. Of course, there is a problem of distinguishing a simple

Ti+Si mixture is produced by a superposition of EEL spectra normalized to the elastic peak intensity and taken with corresponding weights. It can be shown that at low primary electron energy (*E*p=100 eV), when a peak width is greater, a value of Δ3/4 close to that for TiSi2

be received at a certain mixture composition. In this case, the simple unreacted Ti+Si mixture

the location of the maximum in the spectrum of the mixture is close either to the location of the maximum in Ti spectrum (8.4 eV) or Si spectrum (15.2 eV), excluding a small transition region of compositions near Ti-Si=1; (*b*) with coincident maxima in spectra, the *a* location on

mechanical Ti+Si mixture, because for mixture spectra the location of the main maximum are

Ti-Si mixture. Thus, EELS enables one to carry out an analysis of an interaction of components

An interest in silicides of refractory metals has increased significantly due to their great potential as a material of low resistance contacts, gates, and interconnects of the thin-film metallization

metallurgical methods is developed [15, 32]. The optimal conditions of sputter targets have been

**Figure 22.** Electron energy-loss spectra of Ti (1) and Si (2); a linear combination of these spectra with different weight

exhibits also a second maximum at energy of ≈38 eV that is missing in spectra of

trum. With *E*p = 2 keV, it is not difficult to distinguish EEL spectrum of TiSi2

of Si integrated circuits. The principal possibility of obtaining pure CoSi2

with EEL spectra. The artificial spectrum of a simple unreacted

layer after a chemical reaction may be distinguished, because (*a*)

this value is 18.8 eV (**Figure 22**). Besides, the EEL spec-

films with the specific resistivity of 30 μΩ cm. By X-ray

and 24.6 eV for the mixture of Ti+Si spec-

may

from those of the

targets by vacuum-

mixture of Ti+Si and TiSi2

102 Very-Large-Scale Integration

and a composition of TiSi2

trum of TiSi2

fractions.

*2.9.1. Short background*

within 17–17.4 eV, whereas for TiSi2

in Ti-Si system with a high depth resolution.

revealed, providing a deposition of CoSi2

**2.9. Depositing cobalt disilicide films by laser ablation**

the energy-loss scale corresponds to 29.9 eV for TiSi2

As the initial materials for preparing CoSi2 targets are used a polycrystalline Si of 99.999% purity and a commercial Co. To further increase the purity of Co, a double EB vacuum refining is performed [15]. A typical content of impurities after chemical and EB floating zone purifying is shown in **Table 1**. For the preparation of CoSi2 of a stoichiometric composition, the mixture of high-purity Co and Si is melted in a vacuum induction furnace in high purity Ar. The melt is poured into molds receiving rods of 10 mm in diameter and 150 mm in length. The resulting bars are subjected to double floating EB zone melting. CoSi2 targets are of 20×15×5 mm. They are evaporated by laser in a vacuum setup. A solid-state Nd-glass laser is used with wavelength of 1.06 μm, pulse repetition rate of 10 Hz, and pulse energy of 0.8 J. The vacuum chamber is evacuated to a vacuum of 1×10−6 Torr using a turbo pump. The laser beam is focused by a lens; the focal spot size is 2–3 mm. A distance between the target and substrate is 70 mm. For heating the substrate, an infrared heater with halogen lamps is used. The Si(100) wafers, mica, MgO, Al2 O3 , and ZrO<sup>2</sup> are used as substrates. Substrates are subjected to chemical cleaning and then immediately prior to depositing are heated at 850° for 10 min in vacuum. The temperature of substrates is varied in the range of 100–800°; the deposition time is varied from 5 to 20 min. A film thickness is measured using a profilometer and is from 300 to 1500 Å. The specific resistivity of bulk samples and thin films is measured by the four-point probe method. XRD data of CoSi2 samples show that they are a single phase and composed of stoichiometric CoSi2 . A local X-ray analysis of cross sections has revealed the homogeneity of the chemical composition of CoSi2 samples. Double EB melting of CoSi2 ingots does not lead to a significant change in its phase composition. The specific resistivity of bulk samples of CoSi2 is 16–20 μΩ cm, which is close to the data, obtained for single


thickness of the stoichiometric film is about 600 Å. The transition layer between the film and the substrate is not detected. **Figure 24** shows the dependence on the substrate temperature

the substrate temperature, the specific resistivity of the film decreases. Especially sharply it is at the range of 100–500°C where the specific resistivity is reduced by about one order of magnitude (from 800 to 60 μΩ cm). In the range of 600–800°C, the specific resistivity depends weakly on the temperature and reaches the level of 30 μΩ cm. The relatively high specific

excess Si in the composition of films. At high temperatures, the predominance of the substrate

sharp decrease in their resistivity, which explains the behavior of the curve depending on the

**1.** The multiple EB floating zone melting, multiple EB melting, vacuum levitation melting, and electric arc vacuum melting have been successfully used together with chemical techniques of a preliminary purifying by halides and ion exchange of refractory metals. Preparing highly pure refractory metals containing trace contents (on the level of ppm and ppb) of gas-forming interstitials as well as radioactive impurities and light metals

films of 600 Å thick on Si(100). It is seen that with increasing

films on Si(111) on substrate temperature.

High-purity Refractory Metals for Thin Film Metallization of VLSI

http://dx.doi.org/10.5772/intechopen.69126

105

films at low temperatures can be attributed to the presence of the

films, as well as increasing the degree of texture of samples, leads to a

of the specific resistance of CoSi2

**Figure 24.** The dependence of the specific resistivity of CoSi2

resistivity values of CoSi2

composed of CoSi2

specific resistivity.

**3. Key findings**

**Table 7.** Interplanar distances of CoSi2 for the cast target and the film deposited on the Si(100) substrate at 400°C.

**Figure 23.** RBS spectra of the CoSi2 film structure. Arrows indicate the position of energy corresponding to surface bedding Co and Si atoms.

**Figure 24.** The dependence of the specific resistivity of CoSi2 films on Si(111) on substrate temperature.

thickness of the stoichiometric film is about 600 Å. The transition layer between the film and the substrate is not detected. **Figure 24** shows the dependence on the substrate temperature of the specific resistance of CoSi2 films of 600 Å thick on Si(100). It is seen that with increasing the substrate temperature, the specific resistivity of the film decreases. Especially sharply it is at the range of 100–500°C where the specific resistivity is reduced by about one order of magnitude (from 800 to 60 μΩ cm). In the range of 600–800°C, the specific resistivity depends weakly on the temperature and reaches the level of 30 μΩ cm. The relatively high specific resistivity values of CoSi2 films at low temperatures can be attributed to the presence of the excess Si in the composition of films. At high temperatures, the predominance of the substrate composed of CoSi2 films, as well as increasing the degree of texture of samples, leads to a sharp decrease in their resistivity, which explains the behavior of the curve depending on the specific resistivity.

### **3. Key findings**

crystals of CoSi2

104 Very-Large-Scale Integration

films are disilicides CoSi2

(CoSi2

bi-phasic, and at 200°C together with the CoSi2

also affords films consisting of CoSi2

**Table 7.** Interplanar distances of CoSi2

**Figure 23.** RBS spectra of the CoSi2

bedding Co and Si atoms.

. The samples prepared by the PM technology have an electrical resistivity of

(**Table 7**). The films deposited at other substrate temperatures are

for the cast target and the film deposited on the Si(100) substrate at 400°C.

film structure. Arrows indicate the position of energy corresponding to surface

, which is the main phase, an excess of Si

and a small amount of CoSi. From RBS, at the films

65–68 μΩ cm. An important advantage of the method of depositing films by the laser ablation compared with annealing a Co-Si system is a deposition of films at a substrate temperature of 700–800°C. This temperature is 200–300°C lower than in the case of annealing. In addition, the film does not contain Ar, which usually occurs in magnetron sputtering. The results of XRD of the cast target and films obtained in the range of the substrate temperature from 200 to 750°C show that as-deposited films are textured, and with increasing the substrate temperature, the degree of texturing increases (when the temperature increases, the amount of equiaxed polycrystalline grains decreases sharply). At the substrate temperature of 400°C,

is presented as well. At temperatures of 600, 700, and 750°C together with the main phase

deposited at the substrate temperature of 600°C, the ratio of Si/Co is about 2 (**Figure 23**). The

 3.096 90 3.099 80 3.118 82 1.898 100 1.897 100 1.897 82 1.618 23 1.616 24 1.620 14 1.548 1 – – – – 1.340 17 1.340 12 1.346 13 1.230 11 1.230 10 1.231 18 1.095 2 1.094 20 1.094 22

*hkl* **CoSi2 Target Film**

), a small amount of CoSi is found. Sputtering onto substrates ZrO or MgO at 700°C

*d***tab** *I d I d I*

**1.** The multiple EB floating zone melting, multiple EB melting, vacuum levitation melting, and electric arc vacuum melting have been successfully used together with chemical techniques of a preliminary purifying by halides and ion exchange of refractory metals. Preparing highly pure refractory metals containing trace contents (on the level of ppm and ppb) of gas-forming interstitials as well as radioactive impurities and light metals is demonstrated to be possible. To extend a range of the analyzing limitations, the advanced analytic techniques are used, which allowed to determine the real trace contents even on the lowest level—of ppb. It is also shown that both the production methods of cast targets and sputter conditions have a strong effect on the physical properties of deposited refractory metal thin films. By indicating ways to evaluate interstitials and other impurities in as-deposited films, this approach allows one to determine regimes of sputtering providing the deposition of high-purity metallic layers with the optimal specific resistivity.

**6.** The principal possibilities of obtaining high-purity cast targets of CoSi2

Institute of Solid State Physics, The Russian Academy of Sciences, Russia

lurgy—Facts and fiction. Kontakte (Darmstadt). 1987;**3**:3-7

application in microelectronics. Kontakte (Darmstadt). 1988;**3**:38-52

and WSi2

.

and WSi2

Address all correspondence to:glebovs@issp.ac.ru

tronics. 1982;**55**(17):116-119

1983;**26**(6):119-126

pp. 343-353

Austria. 1989. pp. 201-210

stoichiometric CoSi2

disilicides CoSi2

**Author details**

Vadim Glebovsky

**References**

tallization from its liquid phase using a set of metallurgical methods are studied. The modes of the laser evaporating (ablation) have revealed to ensure a stable deposition of

tively. The results of XRD of cast targets and films obtained in the range of the substrate temperature from 200 to 750°C show that the as-deposited films are textured and with increasing substrate temperature, the degree of texturing increases (when the temperature increases, the amount of equiaxed polycrystalline grains decreases sharply). It should be emphasized that at a substrate temperature of 400°C, as-deposited films are stoichiometric

[1] Benzing WC. Shrinking VLSI dimensions demand new interconnection materials. Elec-

[2] Ortner HM, Wilhartitz P, Grasserbauer M, Virag A, Friedbacher G. Ultrapurity in metal-

[3] Ortner HM, Bloedorn W, Friedbacher G, Grasserbauer M, Krivan V, Virag A, Wilhartitz P, Wuensch G. Ultrapurity in metallurgy—With special reference to refractory metals

[4] Iwata S, Yamamoto N, Kobayashi N, Tereda T, Mizutani T. A new tungsten gate process for VLSI applications. IEEE Transactions on Electron Devices. 1984;**31**(9):1174-1179 [5] Yamamoto N, Kume H, Iwata S, Yagi K, Kobayashi N, Mori N, Miyazaki H. Fabrication of highly reliable gate MOS VLSI's. Journal of Electrochemical Society. 1986;**133**(2):401-407

[6] Hoffman V. Tungsten-titanium diffusion barrier metallization. Solid State Technology.

[7] Sawada S. On advanced sputtering targets of refractory metals and their silicides for VLSI application. In: Proc. 12th International Plansee Seminar. Vol. 1; Reutte/Tirol, Austria,

[8] Glebovsky VG. Preparation of high purity refractory metals for thin film metallization. In: Proceedings of International Symposium on Rare Metals. Vol. 1; Kokura, Japan. 1990.

films with the specific resistivity of 30 and 50 μΩ cm, respec-

High-purity Refractory Metals for Thin Film Metallization of VLSI

and WSi2

http://dx.doi.org/10.5772/intechopen.69126

by crys-

107


**6.** The principal possibilities of obtaining high-purity cast targets of CoSi2 and WSi2 by crystallization from its liquid phase using a set of metallurgical methods are studied. The modes of the laser evaporating (ablation) have revealed to ensure a stable deposition of stoichiometric CoSi2 and WSi2 films with the specific resistivity of 30 and 50 μΩ cm, respectively. The results of XRD of cast targets and films obtained in the range of the substrate temperature from 200 to 750°C show that the as-deposited films are textured and with increasing substrate temperature, the degree of texturing increases (when the temperature increases, the amount of equiaxed polycrystalline grains decreases sharply). It should be emphasized that at a substrate temperature of 400°C, as-deposited films are stoichiometric disilicides CoSi2 and WSi2 .

### **Author details**

is demonstrated to be possible. To extend a range of the analyzing limitations, the advanced analytic techniques are used, which allowed to determine the real trace contents even on the lowest level—of ppb. It is also shown that both the production methods of cast targets and sputter conditions have a strong effect on the physical properties of deposited refractory metal thin films. By indicating ways to evaluate interstitials and other impurities in as-deposited films, this approach allows one to determine regimes of sputtering providing the deposition of high-purity metallic layers with the optimal

**2.** Impurity contents in thin TiW films deposited by co-sputtering of cast metal targets are quite low comparing with impurity contents of films deposited by magnetron sputtering of PM targets under similar conditions. The specific resistivity of TiW thin films strongly depends on Ti/W ratio. The resistivity of thin films of pure W and Ti is close to tabulated ones for bulk metals. The resistivity of films increases gradually as the Ti/W ratio changes from those for the pure W to the pure Ti; however, it is worth to mention that the resistivity

**3.** TiW films, deposited by magnetron sputtering of highly pure composite cast Ti/W targets, are grown and studied by AES, XRA, and XRD. AES data showed that Ti/W ratio in TiW films is nearly constant during the sputtering lifetime of composite targets. X-ray spectral analysis of contacts with TiW barrier layers, obtained at the increased sputtering power, is partly due to the higher dispersion of the microstructure. XRD data show that TiW films are solid solutions of Ti in W matrix with increased W lattice parameters. The structure is found to be a solid solution of α-Ti in *bcc* α-W with a lattice parameter of 0.318–0.323 nm. It is also shown that a relative increase in W lattice parameters depends on physical condi-

**4.** Schottky diodes with TiW films exhibit a higher level of current leakage than diodes with Mo films, although in both cases, leakage currents are not an obstacle for the commercial use of these highly pure refractory metals as Schottky diode barrier layers. The great advantage of Schottky diodes with Si/PtSi/TiW/Al structure is a high thermal stability of the

**5.** The refractory metal silicides are very brittle. Thus, one of the experimental approaches to produce these silicides would be used to cast refractory metal silicide targets by HF levitation melting and attaching cast silicide pieces to copper bases by ultrasonic soldering. Vacuum melting (and casting) of silicides solves three main problems of the silicide thin-film deposition: easy production of samples of desired geometries, any chemical compositions, and high purity of silicide thin films. For magnetron sputtering, the composite

regimes of the laser evaporation and magnetron sputtering of cast targets ensure the for-

Films about 200–250 nm thick are shown to be effective diffusion barriers and conducting paths at annealing temperatures up to 900–1000°C. Leakage currents do not deteriorate

layers with poly-Si sublayers.

targets of 152 mm in diameter are produced. Our study has revealed

films with the optimal specific resistivity of 50–70 μΩ cm.

films by both the laser evaporation of small

targets. The conditions and

of quasi-alloy films is always higher than those of pure metals.

tions of Si substrates or sublayers on which films are deposited.

specific resistivity.

106 Very-Large-Scale Integration

direct breakdown potential.

and MoSi2

mation of single-phase WSi2

diode junctions having WSi2

perspective possibilities of depositing WSi2

cast targets and magnetron sputtering of composite cast WSi2

cast WSi2

Vadim Glebovsky

Address all correspondence to:glebovs@issp.ac.ru

Institute of Solid State Physics, The Russian Academy of Sciences, Russia

### **References**


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[25] Murarka SP. Silicides for VLSI Applications. Academic Press, New York; 1983

from cast silicide targets. Materials Letters. 1998;**37**:44-48

spectroscopy as an analytical tool in the study of TiSi2

Si interface. Physical Review B. 1984;**30**(15):5421

1993;**15**:325-330

[26] Glebovsky VG, Oganyan RA, Ermolov SN, Stinov ED, Kolosova EV. Preparation of tungsten disilicide thin films by laser evaporation. Thin Solid Films. 1994;**239**:192-195

[27] Glebovsky VG, Ermolov SN, Motuzenko VN, Stinov ED. Thin silicide films deposited

[28] Shulga YM, Glebovsky VG, Dulinets YC, Rubtsov VI, Borodko YG. Electron energy loss

[29] Butz R, Rubloff GW, Tan TY, Ho PS. Chemical and structural aspects of reaction at the Ti/

[30] Raaijmakers IJMM. Fundamental aspects of reactions of titanium-silicon thin films for integrated circuits [PhD thesis]. Philips Research Laboratories, Eindhoven; 1988

ied by AES, SEELS and IXPS. Journal of Vacuum Science & Technology A. 1988;**6**:3120

[32] Glebovsky VG, Oganyan RA, Ermolov SN, Kolosova EV. Deposition of cobalt disilicide

[31] Sharma JKN, Chakraborty BR, Shivaprasad SM. Chemical shifts of Si and Ti in TiSi2

thin films by laser ablation. Thin Solid Films. 1994;**248**:145-148

/Si interfaces. Materials Letters.

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[25] Murarka SP. Silicides for VLSI Applications. Academic Press, New York; 1983

[9] Fromm E, Gebhardt E. Gase und Kohlenstoff in Metalle. Berlin: Springer Verlag; 1976 [10] Shipilevsky BM, Glebovsky VG. Competition of bulk and surface processes in the kinetics of hydrogen and nitrogen evolution from metals into vacuum. Surface Science.

[11] Ishigami T, Ishihara H, Shimotori K. High purity Ti sputter targets for VLSI. Toshiba

[12] Klimenko GL, Blohin AA, Glebovsky VG, Ermolov SN, Mayorov DY, Kopiryn AA. Production of high purity W and Mo powders by ion exchange. Russian Metallurgy

[13] Stinov ED, Sidorov NS, Glebovsky VG, Karandashev VK. The combined purification of

[14] Sidorov NS, Glebovsky VG, Shtinov ED. Refining of nickel by chemical & solidification

[15] Glebovsky VG, Sidorov NS, Stinov ED, and Gnesin BA. Electron-beam floating zone

[16] Glebovsky VG. Physical and technological aspects of processing high-purity refractory metals. In: Glebovsky VG, editor. Recrystallization in Materials Processing. Rieka,

[17] Amazawa T, Oikawa H, Shiono N, Honma N. Extended Abstracts of 16th Conference on

[18] Yamamoto N. A study on the low resistivity gate electrode interconnections for ultra high density devices [doctoral thesis]. School of Engineering, Tokyo University; Tokyo

[19] Glebovsky VG, Markaryants EA. Thin film metallization by magnetron sputtering from highly pure molybdenum targets. Journal of Alloys and Compounds. 1993;**190**:157-160

[20] Glebovsky VG, Markaryants EA, Titov EV. Deposition of W-Ti thin films by magnetron

[21] Babcock SE, Tu KN. Titanium-tungsten contacts to Si: The effects of alloying on schottky contact and silicide formation. Journal of Applied Physics. 1982;**53**(10):6898-6905

[22] Babcock SE, Tu KN. Titanium-tungsten contacts to Si: II. Its stability against aluminum

[23] Glebovsky VG, Yastschak VY, Baranov VV, Sackovich EL. Properties of tungsten-titanium thin films obtained by magnetron sputtering of composite targets. Thin Solid Films.

[24] Glebovsky VG. Metallurgical aspects of preparation of high purity refractory metals for thin film metallization. In: Proceedings of 12th International Plansee Seminar. Vol. 3;

growing of high purity cobalt crystals. Materials Letters. 1998;**36**:308-314

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University 1986

1995;**257**:1-6


**Section 4**

**Applications**

**Section 4**
