**Meet the editors**

Kim Ho Yeap is an Associate Professor at Universiti Tunku Abdul Rahman, Malaysia. He is an IEEE senior member and a chartered engineer registered with the UK Engineering Council. He received his MSc degree in microelectronics from Universiti Kebangsaan Malaysia in 2005 and his PhD degree from Universiti Tunku Abdul Rahman in 2011. In 2008 and 2015, respectively,

he underwent research attachment in the University of Oxford (UK) and Nippon Institute of Technology (Japan). He is the external examiner of Wawasan Open University. He is also the editor in chief of the i-manager's Journal on Digital Signal Processing. He has also been a guest editor for the Journal of Applied Environmental and Biological Sciences and Journal of Fundamental and Applied Sciences. When working in Intel Corporation, he was involved in the design of the Pentium IV PSC and Celeron NWD-V microprocessors. This earned him four Kudos awards from Intel Microelectronics. He has also been given the university teaching excellence award and 16 research grants. He has published close to 100 scientific articles, which include refereed journal and conference papers, books and book chapters.

Humaira Nisar has a BS degree in Electrical Engineering from the University of Engineering and Technology, Lahore, Pakistan; MS degree in Nuclear Engineering from Quaid-i-Azam University, Islamabad, Pakistan; and another MS degree in Mechatronics and PhD degree in Information and Mechatronics from Gwangju Institute of Science and Technology, Gwangju, South Korea. She

has more than 15 years of research experience. Currently, she is working as an Associate Professor in the Department of Electronic Engineering, Universiti Tunku Abdul Rahman, Malaysia. She is also the head of Programme for the Master of Engineering Science Programme. She is a senior member of IEEE. Her research interests include signal and image processing, biomedical imaging, brain signal and image analysis and image analysis for wastewater treatment. She has published a number of international journal and conference papers. She has also served on technical committees of various conferences and journals.

Contents

**Preface VII**

Chapter 1 **Introductory Chapter: VLSI 3**

**Technologies 15** Chang Yeol Lee

**Section 3 IC Design and Fabrication 45**

Vadim Glebovsky

**CMOS Technology 135** Kittipong Tripetch

**Section 4 Applications 111**

Chapter 3 **Low Power Design Methodology 47**

Pandian and Vinoth Gopi Savithri

Chapter 4 **High-purity Refractory Metals for Thin Film Metallization of VLSI 67**

Chapter 5 **Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices 113**

Chapter 6 **Design of High-Order CMOS Analog Notch Filter with 0.18 μm**

Muhaned Zaidi, Ian Grout and Abu Khari A'ain

**Section 2 Physics of MOSFET's 13**

Kim Ho Yeap and Humaira Nisar

Chapter 2 **Transistor Degradations in Very Large-Scale-Integrated CMOS**

Vithyalakshmi Natarajan, Ashok Kumar Nagarajan, Nagarajan

**Section 1 Introduction 1**

## Contents

### **Preface XI**


Preface

VLSI design.

aging—is also illustrated at the end of the chapter.

could be applied to achieve the concept of low-power designs.

in the silicon-oxide interfaces.

In this book, a variety of topics related to Very-Large-Scale Integration (VLSI) is extensively discussed. The topics encompass the physics of VLSI transistors, the process of integrated circuit (IC) design and fabrication and the applications of VLSI devices. The book is intend‐ ed to provide information on the latest advancement of VLSI technology to researchers, physicists as well as engineers working in the field of semiconductor manufacturing and

Chapter 1 gives an overview of VLSI-integrated circuit devices. A brief historical develop‐ ment of the transistor and integrated circuits is first presented. This is then followed by an introduction of the field effect transistors and of the technology progression driven by Moore's law, which necessitates the evolution of MOSFETs to FinFETs. A concise walk‐ through of the VLSI manufacturing process—from design to fabrication and finally to pack‐

In Chapter 2, the historical evolution of the hot carrier degradation mechanisms and their physical models are reviewed. An energy-driven hot carrier ageing model that can repro‐ duce the 62-nm-gate-long hot carrier degradation of the transistor is verified. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the VGS ratio is emphasized during practical case studies on CMOS inverter chains and a DRAM word line circuit. Negative bias temperature instability (NBTI) mecha‐ nisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) frame‐ work. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, , with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si-H bond breakage is also proven by the quan‐ tifying R-D simulation. The analysis shows that a low-pressure EOL anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffu‐ sion of hydrogen from the gate regions. It therefore prevents further breakage of Si-H bonds

As VLSI technology advances, power consumption in a chip becomes an essential factor, which must be accounted for during IC design. Hence, power optimization is necessary at all levels of the design process. Chapter 3 looks into various design methodologies that

Chapter 4 discusses in detail highly pure refractory metals, which are used in VLSI thin-film metallization. Cast targets of highly pure refractory metals, such as W, Mo, Ti, Ta, Co, etc., and their compounds can be produced by means of a set of vacuum metallurgical techni‐ ques, i.e., vacuum high-frequency levitation, EB floating zone melting, EB melting and elec‐ tric arc vacuum melting, as well as chemical purifying by ion exchange and halides. The cast

## Preface

In this book, a variety of topics related to Very-Large-Scale Integration (VLSI) is extensively discussed. The topics encompass the physics of VLSI transistors, the process of integrated circuit (IC) design and fabrication and the applications of VLSI devices. The book is intend‐ ed to provide information on the latest advancement of VLSI technology to researchers, physicists as well as engineers working in the field of semiconductor manufacturing and VLSI design.

Chapter 1 gives an overview of VLSI-integrated circuit devices. A brief historical develop‐ ment of the transistor and integrated circuits is first presented. This is then followed by an introduction of the field effect transistors and of the technology progression driven by Moore's law, which necessitates the evolution of MOSFETs to FinFETs. A concise walk‐ through of the VLSI manufacturing process—from design to fabrication and finally to pack‐ aging—is also illustrated at the end of the chapter.

In Chapter 2, the historical evolution of the hot carrier degradation mechanisms and their physical models are reviewed. An energy-driven hot carrier ageing model that can repro‐ duce the 62-nm-gate-long hot carrier degradation of the transistor is verified. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the VGS ratio is emphasized during practical case studies on CMOS inverter chains and a DRAM word line circuit. Negative bias temperature instability (NBTI) mecha‐ nisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) frame‐ work. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, , with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si-H bond breakage is also proven by the quan‐ tifying R-D simulation. The analysis shows that a low-pressure EOL anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffu‐ sion of hydrogen from the gate regions. It therefore prevents further breakage of Si-H bonds in the silicon-oxide interfaces.

As VLSI technology advances, power consumption in a chip becomes an essential factor, which must be accounted for during IC design. Hence, power optimization is necessary at all levels of the design process. Chapter 3 looks into various design methodologies that could be applied to achieve the concept of low-power designs.

Chapter 4 discusses in detail highly pure refractory metals, which are used in VLSI thin-film metallization. Cast targets of highly pure refractory metals, such as W, Mo, Ti, Ta, Co, etc., and their compounds can be produced by means of a set of vacuum metallurgical techni‐ ques, i.e., vacuum high-frequency levitation, EB floating zone melting, EB melting and elec‐ tric arc vacuum melting, as well as chemical purifying by ion exchange and halides. The cast

refractory metal targets are extremely pure and chemically homogeneous. For magnetron sputtering and laser ablation, the cast silicide targets are produced. The study reveals the possibilities and conditions of depositing the silicides and titanium-tungsten barrier layers by both laser evaporation and magnetron sputtering. The physical and structural parame‐ ters as well as a trace impurity composition of sputtered metals and deposited thin films are studied by grazing-beam incidence X-ray diffraction, Auger electron spectroscopy, Ruther‐ ford backscattering of helium ions, mass spectrometry with inductively coupled plasma, etc.

In Chapter 5, the design of the operational amplifier (op-amp) and its application at the front-end circuitry of a mixed-signal IC are illustrated. The chapter focuses on the design of the op-amp based on different compensation schemes and by incorporating negative Miller compensation. The op-amps are designed to operate at low voltage levels. The *gm/ID* ratio design approach is used to determine the transistor sizes. The op-amp performance is simu‐ lated using Cadence Spectre. Open-loop frequency responses are given emphasis during validation.

Chapter 6 presents the design of second-order analogue notch filters based on floating active inductors and conventional second-order notch LCR prototypes. The designs are validated using Cadence Spectre, 0.18 micron library. High-order notch filters are also reviewed. The simulation results of a sixth-order notch filter is shown to have ideal polynomial and ideal pole and zero position.

> **Kim Ho Yeap** Associate Professor Department of Electronic Engineering Faculty of Engineering and Green Technology Universiti Tunku Abdul Rahman, Malaysia

**Introduction**

**Section 1**

**Humaira Nisar** Associate Professor Department of Electronic Engineering Universiti Tunku Abdul Rahman, Malaysia

**Section 1**
